mirror of
https://github.com/wwarthen/RomWBW.git
synced 2026-02-06 14:11:48 -06:00
Finalize support for RC180 platform
This commit is contained in:
Wayne Warthen
@@ -3,7 +3,9 @@
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; XMHB.Z80 - XMODEMXX PATCH FILE FOR ROMWBW HBIOS
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;
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; Wayne Warthen - wwarthen@gmail.com
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; Updated: 2017-11-08
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; Updated: 2018-06-06
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;
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; 2018-06-06 WBW Added support for RC2014 w/ Z180
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;
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;=======================================================================
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;
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@@ -129,6 +131,8 @@ MINIT1:
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LD A,(PLTID) ; Get the platform id
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CP 7 ; Check for RC2014
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JR Z,RCINIT ; Handle RC2014 special
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CP 8 ; Check for RC2014 w/ Z180
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JR Z,ARCINIT ; Handle RC2014 w/ Z180
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;
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; Check for Z180 which implies ASCI serial port
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LD DE,00202H ; D := 2, E := 2
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@@ -153,6 +157,12 @@ RCINIT:
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LD DE,COMX ; HBIOS console notification string
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JR MINIT3 ; Complete the initialization
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;
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ARCINIT:
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; RC2014 running Z180
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LD HL,ARC_JPTBL ; ASCI RC2014 jump table address
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LD DE,ASCIRC ; ASCI RC2014 console notification string
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JR MINIT3 ; Complete the initialization
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;
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MINIT3:
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PUSH HL ; Save HL
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@@ -220,10 +230,11 @@ PLTID DB 0 ; Platform ID
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CPUSPD DB 10 ; CPU speed in MHz
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RCVSCL DW 2800 ; RECV loop timeout scalar
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;
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RBC DB "RBC, 08-Nov-2017$"
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RBC DB "RBC, 06-Jun-2018$"
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;
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UART DB ", UART0$"
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ASCI DB ", ASCI0$"
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ASCIRC DB ", ASCI0 (RC2014)$"
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COMX DB ", COM0$"
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;
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UBTAG DB " [UNA]$"
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@@ -365,7 +376,7 @@ U_SNDRDY:
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;
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;-----------------------------------------------------------------------
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;
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; Report baud rate (index into SPTBL returned in regsiter A)
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; Report baud rate (index into SPTBL returned in register A)
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;
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U_SPEED:
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LD A,8 ; arbitrarily return 9600 baud
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@@ -387,6 +398,7 @@ A_DATP EQU 48H ;Z180 TSR - ASCI receive data port
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A_DATO EQU 46H ;Z180 TDR - ASCI transmit data port
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A_CTLP EQU 44H ;Z180 STAT - ASCI status port
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A_CTL2 EQU 40H ;Z180 CNTLA - ASCI control port
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;
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A_SNDB EQU 02H ;Z180 STAT:TDRE - xmit data reg empty bit
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A_SNDR EQU 02H ;Z180 STAT:TDRE - xmit data reg empty value
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A_RCVB EQU 80H ;Z180 STAT:RDRF - rcv data reg full bit
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@@ -477,7 +489,7 @@ A_SNDRDY:
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;
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;-----------------------------------------------------------------------
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;
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; Report baud rate (index into SPTBL returned in regsiter A)
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; Report baud rate (index into SPTBL returned in register A)
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;
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A_SPEED:
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LD A,8 ; arbitrarily return 9600 baud
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@@ -486,6 +498,111 @@ A_SPEED:
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;=======================================================================
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;=======================================================================
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;
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; RC2014 Z180 primary ASCI port
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;
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; Will be used for all RC2014 Z180 systems.
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;
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;=======================================================================
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;=======================================================================
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;
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; ASCI port constants for RC2014
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;
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AR_DATP EQU 0C8H ;Z180 TSR - ASCI receive data port
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AR_DATO EQU 0C6H ;Z180 TDR - ASCI transmit data port
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AR_CTLP EQU 0C4H ;Z180 STAT - ASCI status port
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AR_CTL2 EQU 0C0H ;Z180 CNTLA - ASCI control port
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;
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; Following jump table is dynamically patched over initial jump
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; table at program startup. See MINIT above. Note that only a
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; subset of the jump table is overlaid (SENDR to SPEED).
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;
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ARC_JPTBL:
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JP AR_SENDR ;send character (via pop psw)
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JP AR_CAROK ;test for carrier
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JP AR_MDIN ;receive data byte
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JP AR_GETCHR ;get character from modem
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JP AR_RCVRDY ;check receive ready
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JP AR_SNDRDY ;check send ready
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JP AR_SPEED ;get speed value for file transfer time
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;
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;-----------------------------------------------------------------------
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;
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; Send character on top of stack
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;
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AR_SENDR:
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POP AF ; get character to send from stack
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OUT0 (AR_DATO),A ; send to port
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RET
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;
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;-----------------------------------------------------------------------
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;
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; Test and rep;ort carrier status, Z set if carrier present
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;
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AR_CAROK:
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XOR A ; not used, always indicate present
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RET
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;
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;-----------------------------------------------------------------------
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;
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; Get a character (assume character ready has already been tested)
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;
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AR_MDIN:
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AR_GETCHR:
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IN0 A,(AR_DATP) ; read character from port
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RET
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;
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;-----------------------------------------------------------------------
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;
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; Test for character ready to receive, Z = ready
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; Error code returned in A register
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; *** Error code does not seem to be used ***
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;
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AR_RCVRDY:
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IN0 A,(AR_CTLP) ; get modem status
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PUSH BC ; save scratch register
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PUSH AF ; save full status on stack
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AND A_FRME | A_OVRE | A_PARE ; isolate line err bits
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LD B,A ; save err status in B
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; Z180 ASCI ports will stall if there are errors.
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; Error bits are NOT cleared by merely reading
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; the status register. Below, bit 3 of ASCI
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; control register is written with a zero to
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; clear error(s) if needed.
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JP Z,A_RCVRDY2 ; if no errs, continue
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IN0 A,(AR_CTL2) ; get current control register
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AND 0F7H ; force err reset bit to zero
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OUT0 (AR_CTL2),A ; write control register
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AR_RCVRDY2:
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POP AF ; get full status back
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AND A_RCVB ; isolate ready bit
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CP A_RCVR ; test it (set flags)
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LD A,B ; get the error code back
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POP BC ; restore scratch register
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RET
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;
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;-----------------------------------------------------------------------
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;
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; Test for ready to send a character, Z = ready
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;
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AR_SNDRDY:
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IN A,(AR_CTLP) ; get status
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AND A_SNDB ; isolate transmit ready bit
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CP A_SNDR ; test for ready value
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RET
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;
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;-----------------------------------------------------------------------
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;
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; Report baud rate (index into SPTBL returned in register A)
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;
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AR_SPEED:
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LD A,8 ; arbitrarily return 9600 baud
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RET
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;
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;=======================================================================
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;=======================================================================
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;
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; HBIOS CONSOLE (COM0:)
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;
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; Will be used for all RC2014 systems
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@@ -603,7 +720,7 @@ HB_SNDRDY:
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;
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;-----------------------------------------------------------------------
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;
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; Report baud rate (index into SPTBL returned in regsiter A)
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; Report baud rate (index into SPTBL returned in register A)
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;
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HB_SPEED:
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LD A,8 ; arbitrarily return 9600 baud
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@@ -222,7 +222,6 @@ DEVMAP:
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; PUNCH (PUN:)
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.DB LD_TTY ; PUN:=TTY: (IOBYTE XX00XXXX)
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.DB LD_PTP ; PUN:=PTP: (IOBYTE XX01XXXX)
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.DB LD_PTP ; PUN:=PTP: (IOBYTE XX01XXXX)
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.DB LD_UP1 ; PUN:=UP1: (IOBYTE XX10XXXX)
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.DB LD_UP2 ; PUN:=UP2: (IOBYTE XX11XXXX)
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; LIST (LST:)
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@@ -2070,7 +2069,7 @@ DEV_INIT0:
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RET ; ALL DONE
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;
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DEV_INIT1:
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; PATCH IN COM0: DEVICE ENTRIES
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; PATCH IN COM0: DEVICE ENTRIES, COM0: IS TTY:
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LD (DEVMAP + 0),A ; TTY: @ CON:
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LD (DEVMAP + 4),A ; TTY: @ RDR:
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LD (DEVMAP + 8),A ; TTY: @ PUN:
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@@ -2079,7 +2078,7 @@ DEV_INIT1:
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RET
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;
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DEV_INIT2:
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; PATCH IN COM1: DEVICE ENTRIES
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; PATCH IN COM1: DEVICE ENTRIES, COM1: IS UC1:, PTR:, PTP:, LPT:
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LD (DEVMAP + 3),A ; UC1: @ CON:
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LD (DEVMAP + 5),A ; PTR: @ RDR:
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LD (DEVMAP + 9),A ; PTP: @ PUN:
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@@ -2088,7 +2087,7 @@ DEV_INIT2:
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RET
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;
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DEV_INIT3:
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; PATCH IN COM2: DEVICE ENTRIES
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; PATCH IN COM2: DEVICE ENTRIES, COM2: IS UR1:, UP1:, UL1:
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LD (DEVMAP + 6),A ; UR1: @ RDR:
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LD (DEVMAP + 10),A ; UP1: @ PUN:
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LD (DEVMAP + 15),A ; UL1: @ LST:
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@@ -2096,7 +2095,7 @@ DEV_INIT3:
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RET
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;
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DEV_INIT4:
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; PATCH IN COM3: DEVICE ENTRIES
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; PATCH IN COM3: DEVICE ENTRIES, COM3: IS UR2:, UP2:
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LD (DEVMAP + 7),A ; UR2: @ RDR:
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LD (DEVMAP + 11),A ; UP2: @ PUN:
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LD HL,DEV_INIT5 ; HL := CODE FOR NEXT DEVICE
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@@ -2,4 +2,4 @@
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#DEFINE RMN 9
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#DEFINE RUP 1
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#DEFINE RTP 0
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#DEFINE BIOSVER "2.9.1-pre.4"
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#DEFINE BIOSVER "2.9.1-pre.5"
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@@ -6,12 +6,13 @@
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#include "cfg_rc180.asm"
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;
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Z180_CLKDIV .SET 1 ; 0=OSC/2, 1=OSC, 2=OSC*2
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Z180_MEMWAIT .SET 3 ; MEMORY WAIT STATES TO INSERT (0-3)
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Z180_IOWAIT .SET 3 ; IO WAIT STATES TO INSERT (0-3)
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Z180_MEMWAIT .SET 0 ; MEMORY WAIT STATES TO INSERT (0-3)
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Z180_IOWAIT .SET 1 ; IO WAIT STATES TO INSERT (0-3)
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;
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CPUOSC .SET 18432000 ; CPU OSC FREQ
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DEFSERCFG .SET SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE)
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DEFSERCFG .SET SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG
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;
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ASCIENABLE .SET TRUE ; TRUE FOR Z180 ASCI SUPPORT
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SIOENABLE .SET FALSE ; TRUE TO AUTO-DETECT ZILOG SIO/2
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SIOMODE .SET SIOMODE_RC ; TYPE OF SIO/2 TO DETECT: SIOMODE_RC, SIOMODE_SMB
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ACIAENABLE .SET FALSE ; TRUE TO AUTO-DETECT MOTOROLA 6850 ACIA
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@@ -7,7 +7,7 @@
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;
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CPUOSC .EQU 18432000 ; CPU OSC FREQ
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RAMSIZE .EQU 512 ; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!!
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DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE)
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DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE)
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INTMODE .EQU 2 ; 0=NONE, 1=INT MODE 1, 2=INT MODE 2
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;
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CRTACT .EQU FALSE ; CRT ACTIVATION AT STARTUP
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@@ -559,10 +559,10 @@ UART_ENTRY:
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; D XXXXH YYYYH DUMP MEMORY FROM XXXX TO YYYY
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; F XXXXH YYYYH ZZH FILL MEMORY FROM XXXX TO YYYY WITH ZZ
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; H LOAD INTEL HEX FORMAT DATA
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; IXX INPUT FROM PORT XX AND SHOW HEX DATA
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; I XX INPUT FROM PORT XX AND SHOW HEX DATA
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; K ECHO KEYBOARD INPUT
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; M XXXXH YYYYH ZZZZH MOVE MEMORY BLOCK XXXX TO YYYY TO ZZZZ
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; OXX YY OUTPUT TO PORT XX HEX DATA YY
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; O XX YY OUTPUT TO PORT XX HEX DATA YY
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; P XXXXH YYH PROGRAM RAM FROM XXXXH WITH VALUE IN YYH, WILL PROMPT FOR NEXT LINES FOLLOWING UNTIL CR
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; R RUN A PROGRAM FROM CURRENT LOCATION
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;
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@@ -987,12 +987,13 @@ PHL:
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;
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POUT:
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POUT1:
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; INC HL ;
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INC HL ;
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CALL HEXIN ; GET PORT
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LD C,A ; SAVE PORT POINTER
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INC HL ;
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CALL HEXIN ; GET DATA
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OUTIT:
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LD B,0 ; MAKE SURE MSB IS ZERO
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OUT (C),A ;
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JP SERIALCMDLOOP ;
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@@ -1003,10 +1004,11 @@ OUTIT:
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;_____________________________________________________________________________
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;
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PIN:
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; INC HL ;
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INC HL ;
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CALL HEXIN ; GET PORT
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LD C,A ; SAVE PORT POINTER
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CALL CRLF ;
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LD B,0 ; MAKE SURE MSB IS ZERO
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IN A,(C) ; GET DATA
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CALL HXOUT ; SHOW IT
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JP SERIALCMDLOOP ;
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@@ -1651,27 +1653,6 @@ PROMPT:
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.DB CR,LF,'>',ENDT
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TXT_READY:
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.DB CR,LF
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.TEXT " NN NN 8888 VV VV EEEEEEEEEE MM MM"
|
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.DB CR,LF
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.TEXT " NNNN NN 88 88 VV VV EE MMMM MMMM"
|
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.DB CR,LF
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.TEXT " NN NN NN 88 88 VV VV EE MM MM MM MM"
|
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.DB CR,LF
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.TEXT " NN NNNN 88 88 VV VV EE MM MM MM"
|
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.DB CR,LF
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.TEXT " NN NN 8888 VV VV EEEEEEE MM MM"
|
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.DB CR,LF
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.TEXT " NN NN 88 88 VV VV EE MM MM"
|
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.DB CR,LF
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.TEXT " NN NN 88 88 VV VV EE MM MM"
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.DB CR,LF
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.TEXT " NN NN 88 88 VVV EE MM MM"
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.DB CR,LF
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.TEXT " NN NN 8888 V EEEEEEEEEE MM MM S B C"
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.DB CR,LF
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.DB CR,LF
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.TEXT " ****************************************************************************"
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.DB CR,LF
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.TEXT "MONITOR READY "
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.DB CR,LF,ENDT
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@@ -67,7 +67,9 @@ MODCNT .SET MODCNT + 1
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;
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||||
;
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;
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; #DEFINE DIAGP $00
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#IF ((PLATFORM == PLT_RC) | (PLATFORM == PLT_RC180))
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#DEFINE DIAGP $00
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#ENDIF
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;
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#IFDEF DIAGP
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#DEFINE DIAG(N) PUSH AF
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@@ -647,15 +649,21 @@ HB_STACK .EQU $ ; TOP OF HBIOS STACK
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HB_START:
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DI ; NO INTERRUPTS
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IM 1 ; INTERRUPT MODE 1
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;
|
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#IFDEF DIAGP
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LD A,%00000001
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OUT (DIAGP),A
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#ENDIF
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;
|
||||
LD SP,HBX_LOC ; SETUP INITIAL STACK JUST BELOW HBIOS PROXY
|
||||
|
||||
DIAG(%00000001)
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||||
;
|
||||
#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RC180))
|
||||
; SET BASE FOR CPU IO REGISTERS
|
||||
LD A,Z180_BASE
|
||||
OUT0 (Z180_ICR),A
|
||||
|
||||
DIAG(%00000010)
|
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|
||||
; DISABLE REFRESH
|
||||
XOR A
|
||||
OUT0 (Z180_RCR),A
|
||||
@@ -908,11 +916,11 @@ PSCNX .EQU $ + 1
|
||||
;
|
||||
#IF (INTMODE == 2)
|
||||
; SETUP Z80 IVT AND INT MODE 2
|
||||
; SETUP Z180 IVT
|
||||
LD A,HBX_IVT >> 8 ; SETUP HI BYTE OF IVT ADDRESS
|
||||
LD I,A ; ... AND PLACE IT IN I REGISTER
|
||||
|
||||
#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RC180))
|
||||
; SETUP Z180 IVT
|
||||
XOR A ; SETUP LO BYTE OF IVT ADDRESS
|
||||
OUT0 (Z180_IL),A ; ... AND PLACE IN Z180 IL REGISTER
|
||||
#ENDIF
|
||||
@@ -943,7 +951,8 @@ PSCNX .EQU $ + 1
|
||||
#IF (INTMODE == 2)
|
||||
;
|
||||
; MASK ALL EXTERNAL INTERRUPTS FOR NOW
|
||||
XOR A ; INT0-2 DISABLED
|
||||
;XOR A ; INT0-2 DISABLED
|
||||
LD A,$01 ; INT0 ENABLED, INT1-2 DISABLED
|
||||
OUT0 (Z180_ITC),A ; WRITE TO INT/TRAP CONTROL REGISTER
|
||||
;
|
||||
; SETUP Z180 TIMER0 INTERRUPT VECTOR IN IVT
|
||||
|
||||
@@ -6,5 +6,5 @@ MPGSEL_1 .EQU $79 ; BANK_1 PAGE SELECT REGISTER (WRITE ONLY)
|
||||
MPGSEL_2 .EQU $7A ; BANK_2 PAGE SELECT REGISTER (WRITE ONLY)
|
||||
MPGSEL_3 .EQU $7B ; BANK_3 PAGE SELECT REGISTER (WRITE ONLY)
|
||||
MPGENA .EQU $7C ; PAGING ENABLE REGISTER - BIT 0 = 1 (WRITE ONLY)
|
||||
|
||||
;
|
||||
RTC .EQU $C0 ; RTC PORT address
|
||||
|
||||
@@ -1,16 +1,13 @@
|
||||
;
|
||||
; RC2014 Z180 HARDWARE DEFINITIONS
|
||||
;
|
||||
SBC_BASE .EQU $60 ; I/O BASE ADDRESS FOR ONBOARD PERIPHERALS
|
||||
;
|
||||
MPGSEL_0 .EQU SBC_BASE + $18 ; BANK_0 PAGE SELECT REGISTER (WRITE ONLY)
|
||||
MPGSEL_1 .EQU SBC_BASE + $19 ; BANK_1 PAGE SELECT REGISTER (WRITE ONLY)
|
||||
MPGSEL_2 .EQU SBC_BASE + $1A ; BANK_2 PAGE SELECT REGISTER (WRITE ONLY)
|
||||
MPGSEL_3 .EQU SBC_BASE + $1B ; BANK_3 PAGE SELECT REGISTER (WRITE ONLY)
|
||||
MPGENA .EQU SBC_BASE + $1C ; PAGING ENABLE REGISTER - BIT 0 = 1 (WRITE ONLY)
|
||||
;
|
||||
RTC .EQU SBC_BASE + $10 ; ADDRESS OF RTC LATCH AND INPUT PORT
|
||||
PPIBASE .EQU SBC_BASE + $00 ; PPI 82C55 I/O IS DECODED TO PORT 60-67
|
||||
MPGSEL_0 .EQU $78 ; BANK_0 PAGE SELECT REGISTER (WRITE ONLY)
|
||||
MPGSEL_1 .EQU $79 ; BANK_1 PAGE SELECT REGISTER (WRITE ONLY)
|
||||
MPGSEL_2 .EQU $7A ; BANK_2 PAGE SELECT REGISTER (WRITE ONLY)
|
||||
MPGSEL_3 .EQU $7B ; BANK_3 PAGE SELECT REGISTER (WRITE ONLY)
|
||||
MPGENA .EQU $7C ; PAGING ENABLE REGISTER - BIT 0 = 1 (WRITE ONLY)
|
||||
;
|
||||
RTC .EQU $0C ; ADDRESS OF RTC LATCH AND INPUT PORT
|
||||
;
|
||||
Z180_BASE .EQU $C0 ; I/O BASE ADDRESS FOR INTERNAL Z180 REGISTERS
|
||||
#INCLUDE "z180.inc"
|
||||
|
||||
@@ -2,4 +2,4 @@
|
||||
#DEFINE RMN 9
|
||||
#DEFINE RUP 1
|
||||
#DEFINE RTP 0
|
||||
#DEFINE BIOSVER "2.9.1-pre.4"
|
||||
#DEFINE BIOSVER "2.9.1-pre.5"
|
||||
|
||||
Reference in New Issue
Block a user