@ -58,6 +58,7 @@ UARTCBASE .EQU $80
UARTMBASE .EQU $ 48
UART4BASE .EQU $ C0
UARTRBASE .EQU $ A0
UARTDBASE .EQU $ 80
;
# IF ( UARTINTS )
;
@ -557,6 +558,16 @@ UART_INITDEV1A:
LD A ,( IY + 5 ) ; GET CONFIG BYTE
AND ~ $ 1 F ; REMOVE ENCODED BAUD RATE BITS
OR $ 03 ; FORCE RTS & DTR
;
; SOME NEWER UARTS USE MCR:3 TO ACTIVATE THE INTERRUPT LINE.
; ALTHOUGH OTHER UARTS USE MCR:3 TO CONTROL A GPIO LINE CALLED
; OUT2, NO ROMWBW HARDWARE USES THIS GPIO LINE. SO, HERE, WE
; JUST SET MCR:3 TO ACTIVATE THE INTERRUPT LINE. NOTE THAT
; EVEN IF WE ARE NOT USING INTERRUPTS FOR THIS UART, THE
; INTERRUPT LINE MUST STILL BE ACTIVATED SO THAT IT WILL
; PRESENT A DEASSERTED CONDITION TO THE CPU. OTHERWISE, THE
; INTERRUPT LINE MAY BE LEFT FLOATING WHICH IS DEFINITELY BAD.
OR $ 08 ; ACTIVATE INT LINE
;
; THE MCR REGISTER AFE BIT WILL NORMALLY BE SET/RESET BY THE
; VALUE OF THE CONFIG BYTE. HOWEVER, IF THE CHIP IS NOT AFC CAPABLE
@ -1058,6 +1069,22 @@ UART_CFG_MFP:
.DW UARTCFG ; LINE CONFIGURATION
.DW 0 ; SHOULD NEVER NEED INT HANDLER
# ENDIF
# IF ( UARTDUAL )
; DUAL UART CHANNEL A
.DB 0 ; DEVICE NUMBER (UPDATED DURING INIT)
.DB 0 ; UART TYPE
.DB UARTDBASE ; IO PORT BASE (RBR, THR)
.DB UARTDBASE + UART_LSR ; LINE STATUS PORT (LSR)
.DW UARTCFG ; LINE CONFIGURATION
.DW 0 ; SHOULD NEVER NEED INT HANDLER
; DUAL UART CHANNEL B
.DB 0 ; DEVICE NUMBER (UPDATED DURING INIT)
.DB 0 ; UART TYPE
.DB UARTDBASE + 8 ; IO PORT BASE (RBR, THR)
.DB UARTDBASE + 8 + UART_LSR ; LINE STATUS PORT (LSR)
.DW UARTCFG ; LINE CONFIGURATION
.DW 0 ; SHOULD NEVER NEED INT HANDLER
# ENDIF
;
UART_CNT .EQU ( $ - UART_CFG ) / 8
;
Wayne Warthen
4 years ago