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S100 FPGA Z80 Printer Driver Fixes

- Printer driver was showing port as NOT PRESENT even though it is always present.
pull/609/head v3.6.0-dev.20
Wayne Warthen 5 months ago
parent
commit
d7dc9aafa4
No known key found for this signature in database GPG Key ID: 8B34ED29C07EEB0A
  1. 12
      Source/HBIOS/espsd.asm
  2. 5
      Source/HBIOS/hbios.asm
  3. 37
      Source/HBIOS/lpt.asm
  4. 2
      Source/ver.inc
  5. 2
      Source/ver.lib

12
Source/HBIOS/espsd.asm

@ -649,7 +649,7 @@ ESPSD_BLKWRITE1:
;
ESPSD_CMD:
PUSH DE
LD E,$33
LD E,$33 ; COMMAND PREFIX BYTE
CALL ESPSD_PUTBYTE
POP DE
RET NZ
@ -659,7 +659,7 @@ ESPSD_CMD:
;
ESPSD_CMD_SLOW:
PUSH DE
LD E,$33
LD E,$33 ; COMMAND PREFIX BYTE
CALL ESPSD_PUTBYTE_SLOW
POP DE
RET NZ
@ -699,7 +699,9 @@ ESPSD_PUTBYTE2:
;
ESPSD_PUTBYTE_SLOW:
PUSH HL
LD HL,50 * CPUMHZ ; CPU SPEED SCALED TIMEOUT
;;;LD HL,50 * CPUMHZ ; CPU SPEED SCALED TIMEOUT
LD HL,100 * CPUMHZ ; CPU SPEED SCALED TIMEOUT
;;;LD HL,1000 * CPUMHZ ; CPU SPEED SCALED TIMEOUT
;;;LD HL,0 ; *DEBUG*
ESPSD_PUTBYTE_SLOW1:
PUSH HL
@ -751,7 +753,9 @@ ESPSD_GETBYTE2:
;
ESPSD_GETBYTE_SLOW:
PUSH HL
LD HL,50 * CPUMHZ ; CPU SPEED SCALED TIMEOUT
;;;LD HL,50 * CPUMHZ ; CPU SPEED SCALED TIMEOUT
LD HL,100 * CPUMHZ ; CPU SPEED SCALED TIMEOUT
;;;LD HL,1000 * CPUMHZ ; CPU SPEED SCALED TIMEOUT
;;;LD HL,0 ; *DEBUG*
ESPSD_GETBYTE_SLOW1:
PUSH HL

5
Source/HBIOS/hbios.asm

@ -4427,10 +4427,9 @@ HB_DSKREAD:
LD A,C ; GET DISK UNIT NUMBER
LD B,A ; PUT IN B FOR LOOP COUNTER
INC B ; LOOP ONE EXTRA TIME TO HANDLE UNIT=0
XOR A ; START WITH ACCUM ZERO
SCF ; ... AND CF SET
LD A,%10000000 ; START WITH HIGH BIT SET
HB_DSKREAD0:
RLA ; ROTATE BIT
RLCA ; ROTATE BIT
DJNZ HB_DSKREAD0 ; ... UNTIL IN PROPER LOCATION
LD (HB_DSKBIT),A ; SAVE IT FOR DIAGNOSTICS
#ENDIF

37
Source/HBIOS/lpt.asm

@ -13,21 +13,21 @@
; IBM PC STANDARD PARALLEL PORT (SPP):
; - NHYODYNE PRINT MODULE
;
; PORT 0 (OUTPUT):
; DATA (BASE PORT + 0, OUTPUT):
;
; D7 D6 D5 D4 D3 D2 D1 D0
; +-------+-------+-------+-------+-------+-------+-------+-------+
; | PD7 | PD6 | PD5 | PD4 | PD3 | PD2 | PD1 | PD0 |
; +-------+-------+-------+-------+-------+-------+-------+-------+
;
; PORT 1 (INPUT):
; STATUS (BASE PORT + 1, INPUT):
;
; D7 D6 D5 D4 D3 D2 D1 D0
; +-------+-------+-------+-------+-------+-------+-------+-------+
; | /BUSY | /ACK | POUT | SEL | /ERR | 0 | 0 | 0 |
; +-------+-------+-------+-------+-------+-------+-------+-------+
;
; PORT 2 (OUTPUT):
; CONTROL (BASE PORT + 2, OUTPUT):
;
; D7 D6 D5 D4 D3 D2 D1 D0
; +-------+-------+-------+-------+-------+-------+-------+-------+
@ -39,21 +39,21 @@
; MG014 STYLE INTERFACE:
; - RCBUS MG014 MODULE
;
; PORT 0 (OUTPUT):
; DATA (BASE PORT + 0, OUTPUT):
;
; D7 D6 D5 D4 D3 D2 D1 D0
; +-------+-------+-------+-------+-------+-------+-------+-------+
; | PD7 | PD6 | PD5 | PD4 | PD3 | PD2 | PD1 | PD0 |
; +-------+-------+-------+-------+-------+-------+-------+-------+
;
; PORT 1 (INPUT):
; STATUS (BASE PORT + 1, INPUT):
;
; D7 D6 D5 D4 D3 D2 D1 D0
; +-------+-------+-------+-------+-------+-------+-------+-------+
; | | | | /ERR | SEL | POUT | BUSY | /ACK |
; +-------+-------+-------+-------+-------+-------+-------+-------+
;
; PORT 2 (OUTPUT):
; CONTROL (BASE PORT + 2, OUTPUT):
;
; D7 D6 D5 D4 D3 D2 D1 D0
; +-------+-------+-------+-------+-------+-------+-------+-------+
@ -65,21 +65,21 @@
; S100 STYLE INTERFACE:
; - S100 FPGA Z80
;
; BASE I/O PORT (OUTPUT):
; DATA (BASE PORT + 0, OUTPUT):
;
; D7 D6 D5 D4 D3 D2 D1 D0
; +-------+-------+-------+-------+-------+-------+-------+-------+
; | PD7 | PD6 | PD5 | PD4 | PD3 | PD2 | PD1 | PD0 |
; +-------+-------+-------+-------+-------+-------+-------+-------+
;
; STATUS PORT (INPUT, BASE I/O - 1):
; STATUS (BASE PORT + 0, INPUT):
;
; D7 D6 D5 D4 D3 D2 D1 D0
; +-------+-------+-------+-------+-------+-------+-------+-------+
; | | | | | | | BUSY | /ACK |
; +-------+-------+-------+-------+-------+-------+-------+-------+
;
; CONTROL PORT (OUTPUT, BASE I/O - 1):
; CONTROL (BASE PORT - 1, OUTPUT):
;
; D7 D6 D5 D4 D3 D2 D1 D0
; +-------+-------+-------+-------+-------+-------+-------+-------+
@ -168,13 +168,18 @@ LPT_IN:
; BYTE OUTPUT
;
LPT_OUT:
; WAIT WHILE PRINTER IS BUSY
CALL LPT_OST ; READY TO SEND?
JR Z,LPT_OUT ; LOOP IF NOT
;
; SET DATA PORT BITS
LD C,(IY+3) ; PORT 0 (DATA)
EZ80_IO
OUT (C),E ; OUTPUT DATA TO PORT
;
; SET STROBE
#IF (LPTMODE == LPTMODE_SPP)
LD A,%00001101 ; SELECT & STROBE, LEDS OFF
LD A,%00001101 ; SELECT & STROBE, LED OFF
#ENDIF
#IF (LPTMODE == LPTMODE_MG014)
LD A,%00000100 ; SELECT & STROBE, LED OFF
@ -192,6 +197,8 @@ LPT_OUT:
EZ80_IO
OUT (C),A ; OUTPUT DATA TO PORT
CALL DELAY
;
; CLEAR STROBE
#IF (LPTMODE == LPTMODE_SPP)
LD A,%00001100 ; SELECT, LEDS OFF
#ENDIF
@ -199,11 +206,12 @@ LPT_OUT:
LD A,%00000101 ; SELECT, LED OFF
#ENDIF
#IF (LPTMODE == LPTMODE_S100)
LD A,%11111111 ; STROBE
LD A,%11111111 ; CLEAR STROBE
#ENDIF
EZ80_IO
OUT (C),A ; OUTPUT DATA TO PORT
CALL DELAY
;
XOR A ; SIGNAL SUCCESS
RET
;
@ -215,21 +223,19 @@ LPT_IST:
RET ; DONE
;
; OUTPUT STATUS
; 0 = BUSY, 1 = READY
;
LPT_OST:
LD C,(IY+3) ; BASE PORT
#IF ((LPTMODE == LPTMODE_SPP) | (LPTMODE == LPTMODE_MG014))
INC C ; SELECT STATUS PORT
#ENDIF
#IF (LPTMODE == LPTMODE_S100)
DEC C ; SELECT STATUS PORT
#ENDIF
EZ80_IO
IN A,(C) ; GET STATUS INFO
#IF (LPTMODE == LPTMODE_SPP)
AND %10000000 ; ISOLATE /BUSY
#ENDIF
#IF (LPTMODE == LPTMODE_MG014)
#IF ((LPTMODE == LPTMODE_MG014) | (LPTMODE == LPTMODE_S100))
AND %00000010 ; ISOLATE BUSY
XOR %00000010 ; INVERT TO READY
#ENDIF
@ -295,6 +301,7 @@ LPT_INITDEV0:
LD A,$FF ; INIT VALUE
EZ80_IO
OUT (C),A ; DO IT
XOR A ; SIGNAL SUCCESS
RET ; RETURN
#ENDIF
;

2
Source/ver.inc

@ -2,7 +2,7 @@
#DEFINE RMN 6
#DEFINE RUP 0
#DEFINE RTP 0
#DEFINE BIOSVER "3.6.0-dev.19"
#DEFINE BIOSVER "3.6.0-dev.20"
#define rmj RMJ
#define rmn RMN
#define rup RUP

2
Source/ver.lib

@ -3,5 +3,5 @@ rmn equ 6
rup equ 0
rtp equ 0
biosver macro
db "3.6.0-dev.19"
db "3.6.0-dev.20"
endm

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