mirror of
https://github.com/wwarthen/RomWBW.git
synced 2026-02-06 14:11:48 -06:00
Update flashfs.asm
Add chip erase error/timeout detection
This commit is contained in:
@@ -75,6 +75,8 @@ FF_NXT0:PUSH BC ; WE DIDN'T MATCH SO POINT
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;
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FF_NXT2:CALL PRTSTR ; AFTER SEARCH DISPLAY THE RESULT
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;
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CALL FF_EINIT ; ERASE TEST
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XOR A ; INIT SUCCEEDED
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RET
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;
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@@ -114,7 +116,7 @@ FF_I_SZ .EQU $-FF_IDENT
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; ERASE FLASH CHIP.
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;======================================================================
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;
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FF_INIT_E:
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FF_EINIT:
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LD (FF_STACK),SP ; SAVE STACK
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LD HL,(FF_STACK)
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;
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@@ -138,7 +140,7 @@ FF_INIT_E:
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LD HL,(FF_STACK) ; RESTORE ORIGINAL
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LD SP,HL ; STACK POSITION
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;
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XOR A
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LD A,C ; RETURN WITH STATUS IN A
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RET
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;
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;======================================================================
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@@ -146,6 +148,7 @@ FF_INIT_E:
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; IT SWITCHES THE BOTTOM BANK TO ROM BANK 0 I.E. BOTTOM OF CHIP ADDRESS RANGE.
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; RETURNS THE BOTTOM BANK TO INITIAL STATE. ERASE COMMAND IS ISSUED TO
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; THE FLASH CHIP AND THEN TOGGLE BIT IS MONITORED FOR COMPLETION.
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; RETURN C=0 FOR SUCCESS OR C=FF FOR FAILURE.
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;======================================================================
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;
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FF_ERASE:
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@@ -170,12 +173,98 @@ FF_ERASE:
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LD A,$10
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LD ($5555),A
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;
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LD HL,$5555 ; WAIT FOR TOGGLE
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FF_WAIT:LD A,(HL) ; BIT CHANGE
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CP (HL)
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JR NZ,FF_WAIT
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LD A,(HL)
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LD A,(HL)
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LD HL,$5555 ; DO TWO SUCCESSIVE READS
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LD A,(HL) ; FROM THE SAME FLASH ADDRESS.
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FF_WT2: LD C,(HL) ; IF TOGGLE BIT (BIT 6)
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XOR C ; IS THE SAME ON BOTH READS
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BIT 6,A ; THEN ERASE IS COMPLETE SO EXIT.
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JR Z,FF_WT1 ; Z TRUE IF BIT 6=0 I.E. "NO TOGGLE" WAS DETECTED.
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;
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LD A,C ; OPERATION IS NOT COMPLETE. CHECK TIMEOUT BIT (BIT 5).
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BIT 5,C ; IF NO TIMEOUT YET THEN LOOP BACK AND KEEP CHECKING TOGGLE STATUS
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JR Z,FF_WT2 ; IF BIT 5=0 THEN RETRY; NZ TRUE IF BIT 5=1
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;
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LD A,(HL) ; WE GOT A TIMOUT. RECHECK TOGGLE BIT IN CASE WE DID COMPLETE
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XOR (HL) ; THE OPERATION. DO TWO SUCCESSIVE READS. ARE THEY THE SAME?
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BIT 6,A ; IF THEY ARE THEN OPERATION WAS COMPLETED
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JR Z,FF_WT1 ; OTHERWISE ERASE OPERATION FAILED OR TIMED OUT.
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;
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LD C,$FF ; SET FAIL STATUS
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JR FF_WT3
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;
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FF_WT1: LD C,0 ; SET SUCCESS STATUS
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FF_WT3: LD A,B ; RETURN TO ORIGINAL BANK
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CALL HBX_BNKSEL ; WHICH IS OUR RAM BIOS COPY
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HB_EI
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;
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RET
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;
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FF_E_SZ .EQU $-FF_ERASE
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;
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;======================================================================
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; ERASE FLASH SECTOR.
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;======================================================================
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;
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;
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FF_SINIT:
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LD (FF_STACK),SP ; SAVE STACK
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LD HL,(FF_STACK)
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;
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LD BC,FF_S_SZ ; CODE SIZE REQUIRED
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CCF ; CREATE A RELOCATABLE
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SBC HL,BC ; CODE BUFFER IN THE
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LD SP,HL ; STACK AREA
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;
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PUSH HL ; SAVE THE EXECUTE ADDRESS
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EX DE,HL ; PUT EXECUTE / START ADDRESS IN DE
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LD HL,FF_ERASE ; COPY OUR RELOCATABLE
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LDIR ; CODE TO THE BUFFER
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;
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LD A,(HB_CURBNK) ; WE ARE STARTING IN HB_CURBNK
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LD B,A ; WHICH IS THE RAM COPY OF THE BIOS
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;
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; SELECT THE CORRECT ROM BANK
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;
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LD A,BID_BOOT ; BID_BOOT IS ROM BANK 0
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;
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POP HL ; CALL OUR RELOCATABLE CODE
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CALL JPHL
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;
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LD HL,(FF_STACK) ; RESTORE ORIGINAL
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LD SP,HL ; STACK POSITION
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;
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XOR A
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RET
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;
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;======================================================================
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; ERASE FLASH CHIP SECTOR. THIS CODE IS RELOCATED AND EXECUTED IN THE STACK.
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; IT SWITCHES THE REQUIRED BANK TO THE BOTTOM OF CHIP ADDRESS RANGE.
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; RETURNS THE BOTTOM BANK TO INITIAL STATE. ERASE SECTOR COMMAND IS ISSUED TO
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; THE FLASH CHIP AND THEN TOGGLE BIT IS MONITORED FOR COMPLETION.
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; ON ENTRY HL CONTAINS THE SECTOR TO ERASE.
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;======================================================================
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;
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FF_SERASE:
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HB_DI
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CALL HBX_BNKSEL ; SELECT ROM BANK 0
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;
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LD A,$AA ; SET CHIP ERASE
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LD ($5555),A
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;
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LD A,$55
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LD ($2AAA),A
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;
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LD A,$80
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LD ($5555),A
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;
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LD A,$AA
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LD ($5555),A
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;
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LD A,$55
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LD ($2AAA),A
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;
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LD A,$30 ; SECTOR ADDRESS
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LD (HL),A
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;
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LD A,B ; RETURN TO ORIGINAL BANK
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CALL HBX_BNKSEL ; WHICH IS OUR RAM BIOS COPY
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@@ -183,7 +272,7 @@ FF_WAIT:LD A,(HL) ; BIT CHANGE
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;
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RET
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;
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FF_E_SZ .EQU $-FF_ERASE
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FF_S_SZ .EQU $-FF_SERASE
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;
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; FLASH STYLE
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;
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