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Phil's new ROM Applications document has been added to the documents generated and added to the /Doc directory.pull/246/head
Wayne Warthen
4 years ago
9 changed files with 59 additions and 1147 deletions
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DDTZ v2.7 |
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by C.B. Falconer |
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edited by George A. Havach |
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|
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Introduction: |
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============ |
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DDTZ v2.7 is a complete replacement for DDT, Digital Research's |
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famous Dynamic Debugging Tool, with improved functionality, bug |
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extermination, and full Z80 support. In general, DDTZ is fully |
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compatible with the original utility, but it has extra and |
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extended commands and many fewer quirks. All Z80-specific |
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instructions can be (dis)assembled, though in Intel rather then |
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Zilog format. Furthermore, DDTZ will correctly trace ('T' and 'U' |
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commands) both 8080 and Z80 instructions, depending on which CPU |
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is operating. On startup, the program announces which CPU it is |
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running on. |
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|
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DDTZ v2.7 now handles the 64180 added opcodes. It does NOT test |
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for a 64180 CPU, since this cannot be done without executing |
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illegal Z80 instructions, which in turn will crash some |
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simulators. However v2.7 does not execute any 64180 instructions |
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internally, only in the subject program. |
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|
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This issue supplies the "M" version assembled, to avoid errors |
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when switching between MSDOS and CPM systems. The command table |
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is updated accordingly. Most CPM users are also MSDOS users, but |
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not vice-versa. |
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|
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The program is invoked by typing |
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|
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ddtz<ret> |
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or |
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ddtz [d:]filespec<ret> |
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|
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In the second form, DDTZ will load the specified file into |
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memory starting at 0100H, unless it's a .HEX file that sets its |
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own load address. Besides reporting the NEXT free address and |
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the PC (program counter) after a successful load, DDTZ also shows |
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the number of memory pages needed for a SAVE. Instead of having |
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to write all this down, just use the 'X' command at any time to |
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redisplay these three values for the current application. |
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|
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NOTE: loading more code above the NEXT pointer revises these |
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values. |
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|
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As in DDT, when a program is loaded above the area holding the |
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'A' and 'U' (and now 'W') command code, these commands are |
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disabled, and the extra memory is released to the user. Thus, |
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DDTZ can occupy as little as 3K total memory space. Unlike DDT, |
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however, DDTZ will not overwrite itself or the system on program |
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loads (except .HEX files). |
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|
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At initialization, the stack pointer (SP) points to a return to |
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DDTZ, just like for the CCP. Thus, programs that normally return |
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to the CCP will be returned to DDTZ. The 'B' command |
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reinitializes this condition. |
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|
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|
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The intercept vector copies the BDOS version number, etc., so |
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an object program does not know that DDTZ is running (except |
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for BIOS-BDOS vector size). Thus, programs that check the version |
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number should execute correctly under DDTZ. |
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|
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All input parameters can now be entered in any of three formats: |
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|
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(1) hexadecimal (as in DDT), |
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(2) decimal, by adding a leading '#' character, |
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(3) ASCII, by enclosing between either single or double |
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quotes; either one or two characters are allowed. |
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|
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Leading blanks in command lines and parameters are absorbed. |
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Either a comma or a (single) space is a valid delimiter. |
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Either uppercase or lowercase input is accepted. |
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|
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The default command (for anything not otherwise recognizable) |
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is 'H'. This allows convenient calculation, along with the other |
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features described below. So, to convert a number, just enter |
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it! |
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|
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As in DDT, the prompt character is '-', and the only error |
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message is the query ('?'), which generally kicks you back to |
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command mode. |
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|
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New Commands (Over DDT): |
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======================= |
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|
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NOTE: letters in parenthesis, e.g. "(U)", show the equivalent |
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command for DDTZM version (compatible with MSDOS debug). |
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|
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@ Sets or shows (with no parameter) the internally stored |
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"base" value. Also used with the 'S' and 'D' commands as |
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an optional parameter (though without the '@') to display |
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memory from an arbitrary base marker (offset). When set to |
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zero (the default), it does not affect any screen displays. |
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|
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B B)egin: resets the USER stack pointer to its initial value, |
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such that any program that exits by an RET will return to |
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DDTZ. DDTZ provides a default stack space of |
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approximately 24 bytes for user programs. |
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|
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C C)ompare first_address,last_address,against_address: shows |
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all the byte differences between two memory areas, in the |
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format |
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|
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XXXX aa YYYY bb |
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|
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where XXXX and YYYY are the comparative memory addresses, |
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and aa and bb are the corresponding byte values. Can be |
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used to verify the identity of two files by first |
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loading them into different memory areas with the 'R' |
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command (see below). |
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|
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|
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W Write: stores the modified memory area to disk under the |
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(K) filename specified by the 'I' command, overwriting the |
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original file from which it was loaded (the user is queried |
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before doing so). By default, the image of memory from |
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0100H through the "NEXT" value -1 is saved. "K first_addr, |
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last_address" overrides this and allows writing ANY memory |
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area to a file. Almost a necessity for CPM 3.0 (no SAVE!). |
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K)eep on DDTZ |
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|
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X eXamine: redisplays the "NEXT PC SAVE" report at any time. |
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(Q) Q)uery size on DDTZ. |
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|
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S S)earch first_address, last_addr, value: searches the |
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(W) specified memory area for the value (a 16-bit word, not a |
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byte) and shows the locations of all such. Very useful for |
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finding CALL's or JMP's to a particular address, etc. |
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W)here on DDTZ |
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|
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Y Y)our_option parm1,parm2,address: executes an arbitrary |
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routine at the specified address, with the BC and DE |
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registers set to parm1 and parm2, respectively. |
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|
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Z Displays (but does not alter) the Z80's alternate register |
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set, including the index registers (disabled if running on |
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an 8080). On Z80's, automatically included as the last |
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part of the display by the 'X' command. |
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|
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|
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Based (Offset) Displays: |
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======================= |
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|
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The 'D' and 'E' commands can use a stored base value (offset), |
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as set by the '@' command. The current @ value may be |
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overridden for a single execution of these commands by adding the |
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base as an extra parameter in the command line. The effect is |
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to add this value to the first/last address and display |
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accordingly. The address listing on the left becomes XXXX:YYYY, |
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where XXXX is the offset address and YYYY is the actual memory |
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address being displayed. For example, if you have a data area |
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located at 42B7H and wish to preserve easy access, just enter |
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"@42b7". Now, "d0,3f" will dump memory starting at 4237H. |
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|
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|
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Further Changes from DDT: |
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======================== |
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|
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A A)ssemble now accepts the full Z80 as well as 8080 |
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instruction set, although it expects them in Intel rather |
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than Zilog format (see notes below under the 'L' |
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command). When in doubt, see the mnemnonic list below. |
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|
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D D)isplay or D)ump will accept an optional third parameter |
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to set the base value for a single execution only. Format |
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has been cleaned up. |
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|
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H H)ex_arithmetic on two values also shows their |
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difference in decimal. With only one value, converts to |
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hexadecimal, decimal, and ASCII (low-order byte only). |
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|
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|
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N N)ame now allows drive specification (d:...) and sets up |
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(I) the complete command line, including both FCB's (at |
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addresses 005CH and 006CH). The tail (stored at 0081H up) |
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is NOT upshifted. |
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I)nput on DDTZ |
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|
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U U)nassemble now displays the raw hexcode, especially handy |
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(L) when examining non-code areas. Intel (8080 style) mnemonics |
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are used, so some disassembled instructions may look |
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strange. E.g., the Z80's 'IN B,(C)' and 'OUT (C),B' become |
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'INP B' and 'OUTP B', respectively; 'LD (nnnn),BC' becomes |
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'SBCD nnnn', 'ADD IX, BC' becomes 'DADX B', and 'JP (IX)' |
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becomes 'PCIX'. |
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L)ist on DDTZ |
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|
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L L)oad now permits loading a file into memory with an |
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(R) offset, which is added to the default load address of |
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0100H. When reading in a .HEX file with a preset bias, |
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the 'R' command will not transfer control to an invalid |
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execution point. Another execution of the 'R' command will |
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reread the input file, e.g.: |
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|
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n blah<ret> |
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l<ret> |
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...modify the code and generally mess about... |
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l<ret> |
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|
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The original file is reloaded, and the modifications are |
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removed. |
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R)ead on DDTZ |
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|
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E E)nter, like D)isplay, now accepts an optional second |
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(S) parameter to set the base value for a single execution |
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only. |
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S)ubstitute or S)et on DDTZ |
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|
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T T)rap/trace on termination now shows the complete CPU |
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state. Traps and traces no longer lock up when a user RST |
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7 instruction is executed. Tracing of BDOS/BIOS calls is |
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heavily trun cated, avoiding clutter and preventing system |
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crashes. |
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|
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NOTE: Most of the UNDOCUMENTED Z80 op-codes are handled. Others |
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can crash the system. |
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|
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R R)egisters also shows what two-byte values the HL and SP |
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(X) registers are actually pointing to. On Z80's, displays the |
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alternate register set. |
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eX)amine on DDTZ |
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|
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NOTE: Any use of the 'W' or 'L' command resets the system DMA |
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transfer address to the standard default value of 0080H. |
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|
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|
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; This is the output of DDTZ when disassembling OPTYPE.TRY |
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NOP LDA 06A4 MOV M,H |
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LXI B,06A4 DCX SP MOV M,L |
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STAX B INR A HLT |
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INX B DCR A MOV M,A |
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INR B MVI A,20 MOV A,B |
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DCR B CMC MOV A,C |
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MVI B,20 MOV B,B MOV A,D |
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RLC MOV B,C MOV A,E |
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EXAF MOV B,D MOV A,H |
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DAD B MOV B,E MOV A,L |
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LDAX B MOV B,H MOV A,M |
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DCX B MOV B,L MOV A,A |
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INR C MOV B,M ADD B |
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DCR C MOV B,A ADD C |
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MVI C,20 MOV C,B ADD D |
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RRC MOV C,C ADD E |
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DJNZ 0134 MOV C,D ADD H |
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LXI D,06A4 MOV C,E ADD L |
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STAX D MOV C,H ADD M |
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INX D MOV C,L ADD A |
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INR D MOV C,M ADC B |
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DCR D MOV C,A ADC C |
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MVI D,20 MOV D,B ADC D |
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RAL MOV D,C ADC E |
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JR 0134 MOV D,D ADC H |
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DAD D MOV D,E ADC L |
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LDAX D MOV D,H ADC M |
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DCX D MOV D,L ADC A |
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INR E MOV D,M SUB B |
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DCR E MOV D,A SUB C |
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MVI E,20 MOV E,B SUB D |
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RAR MOV E,C SUB E |
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JRNZ 0134 MOV E,D SUB H |
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LXI H,06A4 MOV E,E SUB L |
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SHLD 06A4 MOV E,H SUB M |
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INX H MOV E,L SUB A |
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INR H MOV E,M SBB B |
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DCR H MOV E,A SBB C |
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MVI H,20 MOV H,B SBB D |
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DAA MOV H,C SBB E |
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JRZ 0134 MOV H,D SBB H |
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DAD H MOV H,E SBB L |
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LHLD 06A4 MOV H,H SBB M |
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DCX H MOV H,L SBB A |
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INR L MOV H,M ANA B |
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DCR L MOV H,A ANA C |
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MVI L,20 MOV L,B ANA D |
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CMA MOV L,C ANA E |
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JRNC 0134 MOV L,D ANA H |
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LXI SP,06A4 MOV L,E ANA L |
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STA 06A4 MOV L,H ANA M |
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INX SP MOV L,L ANA A |
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INR M MOV L,M XRA B |
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DCR M MOV L,A XRA C |
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MVI M,20 MOV M,B XRA D |
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STC MOV M,C XRA E |
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JRC 0134 MOV M,D XRA H |
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DAD SP MOV M,E XRA L |
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|
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|
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XRA M JPE 06A4 SLAR M |
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XRA A XCHG SLAR A |
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ORA B CPE 06A4 SRAR B |
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ORA C XRI 20 SRAR C |
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ORA D RST 5 SRAR D |
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ORA E RP SRAR E |
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ORA H POP PSW SRAR H |
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ORA L JP 06A4 SRAR L |
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ORA M DI SRAR M |
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ORA A CP 06A4 SRAR A |
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CMP B PUSH PSW SLLR B |
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CMP C ORI 20 SLLR C |
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CMP D RST 6 SLLR D |
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CMP E RM SLLR E |
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CMP H SPHL SLLR H |
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CMP L JM 06A4 SLLR L |
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CMP M EI SLLR M |
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CMP A CM 06A4 SLLR A |
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RNZ CPI 20 SRLR B |
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POP B RST 7 SRLR C |
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JNZ 06A4 RLCR B SRLR D |
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JMP 06A4 RLCR C SRLR E |
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CNZ 06A4 RLCR D SRLR H |
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PUSH B RLCR E SRLR L |
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ADI 20 RLCR H SRLR M |
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RST 0 RLCR L SRLR A |
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RZ RLCR M BIT 0,B |
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RET RLCR A BIT 0,C |
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JZ 06A4 RRCR B BIT 0,D |
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CZ 06A4 RRCR C BIT 0,E |
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CALL 06A4 RRCR D BIT 0,H |
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ACI 20 RRCR E BIT 0,L |
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RST 1 RRCR H BIT 0,M |
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RNC RRCR L BIT 0,A |
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POP D RRCR M BIT 1,B |
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JNC 06A4 RRCR A BIT 1,C |
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OUT 20 RALR B BIT 1,D |
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CNC 06A4 RALR C BIT 1,E |
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PUSH D RALR D BIT 1,H |
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SUI 20 RALR E BIT 1,L |
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RST 2 RALR H BIT 1,M |
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RC RALR L BIT 1,A |
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EXX RALR M BIT 2,B |
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JC 06A4 RALR A BIT 2,C |
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IN 20 RARR B BIT 2,D |
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CC 06A4 RARR C BIT 2,E |
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SBI 20 RARR D BIT 2,H |
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RST 3 RARR E BIT 2,L |
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RPO RARR H BIT 2,M |
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POP H RARR L BIT 2,A |
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JPO 06A4 RARR M BIT 3,B |
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XTHL RARR A BIT 3,C |
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CPO 06A4 SLAR B BIT 3,D |
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PUSH H SLAR C BIT 3,E |
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ANI 20 SLAR D BIT 3,H |
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RST 4 SLAR E BIT 3,L |
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RPE SLAR H BIT 3,M |
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PCHL SLAR L BIT 3,A |
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|
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|
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BIT 4,B RES 3,D SET 2,H |
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BIT 4,C RES 3,E SET 2,L |
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BIT 4,D RES 3,H SET 2,M |
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BIT 4,E RES 3,L SET 2,A |
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BIT 4,H RES 3,M SET 3,B |
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BIT 4,L RES 3,A SET 3,C |
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BIT 4,M RES 4,B SET 3,D |
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BIT 4,A RES 4,C SET 3,E |
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BIT 5,B RES 4,D SET 3,H |
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BIT 5,C RES 4,E SET 3,L |
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BIT 5,D RES 4,H SET 3,M |
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BIT 5,E RES 4,L SET 3,A |
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BIT 5,H RES 4,M SET 4,B |
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BIT 5,L RES 4,A SET 4,C |
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BIT 5,M RES 5,B SET 4,D |
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BIT 5,A RES 5,C SET 4,E |
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BIT 6,B RES 5,D SET 4,H |
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BIT 6,C RES 5,E SET 4,L |
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BIT 6,D RES 5,H SET 4,M |
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BIT 6,E RES 5,L SET 4,A |
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BIT 6,H RES 5,M SET 5,B |
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BIT 6,L RES 5,A SET 5,C |
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BIT 6,M RES 6,B SET 5,D |
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BIT 6,A RES 6,C SET 5,E |
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BIT 7,B RES 6,D SET 5,H |
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BIT 7,C RES 6,E SET 5,L |
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BIT 7,D RES 6,H SET 5,M |
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BIT 7,E RES 6,L SET 5,A |
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BIT 7,H RES 6,M SET 6,B |
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BIT 7,L RES 6,A SET 6,C |
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BIT 7,M RES 7,B SET 6,D |
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BIT 7,A RES 7,C SET 6,E |
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RES 0,B RES 7,D SET 6,H |
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RES 0,C RES 7,E SET 6,L |
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RES 0,D RES 7,H SET 6,M |
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RES 0,E RES 7,L SET 6,A |
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RES 0,H RES 7,M SET 7,B |
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RES 0,L RES 7,A SET 7,C |
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RES 0,M SET 0,B SET 7,D |
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RES 0,A SET 0,C SET 7,E |
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RES 1,B SET 0,D SET 7,H |
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RES 1,C SET 0,E SET 7,L |
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RES 1,D SET 0,H SET 7,M |
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RES 1,E SET 0,L SET 7,A |
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RES 1,H SET 0,M DADX B |
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RES 1,L SET 0,A DADX D |
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RES 1,M SET 1,B LXI X,06A4 |
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RES 1,A SET 1,C SIXD 06A4 |
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RES 2,B SET 1,D INX X |
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RES 2,C SET 1,E DADX X |
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RES 2,D SET 1,H LIXD 06A4 |
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RES 2,E SET 1,L DCX X |
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RES 2,H SET 1,M INR [X+05] |
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RES 2,L SET 1,A DCR [X+05] |
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RES 2,M SET 2,B MVI [X+05],20 |
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RES 2,A SET 2,C DADX SP |
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RES 3,B SET 2,D MOV B,[X+05] |
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RES 3,C SET 2,E MOV C,[X+05] |
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|
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|
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MOV D,[X+05] DSBC B DADY B |
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MOV E,[X+05] SBCD 06A4 DADY D |
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MOV H,[X+05] NEG LXI Y,06A4 |
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MOV L,[X+05] RETN SIYD 06A4 |
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MOV [X+05],B IM0 INX Y |
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MOV [X+05],C LDIA DADY Y |
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MOV [X+05],D INP C LIYD 06A4 |
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MOV [X+05],E OUTP C DCX Y |
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MOV [X+05],H DADC B INR [Y+05] |
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MOV [X+05],L LBCD 06A4 DCR [Y+05] |
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MOV [X+05],A RETI MVI [Y+05],2 |
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MOV A,[X+05] LDRA DADY SP |
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ADD [X+05] INP D MOV B,[Y+05] |
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ADC [X+05] OUTP D MOV C,[Y+05] |
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SUB [X+05] DSBC D MOV D,[Y+05] |
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SBB [X+05] SDED 06A4 MOV E,[Y+05] |
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ANA [X+05] IM1 MOV H,[Y+05] |
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XRA [X+05] LDAI MOV L,[Y+05] |
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ORA [X+05] INP E MOV [Y+05],B |
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CMP [X+05] OUTP E MOV [Y+05],C |
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POP X DADC D MOV [Y+05],D |
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XTIX LDED 06A4 MOV [Y+05],E |
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PUSH X IM2 MOV [Y+05],H |
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PCIX LDAR MOV [Y+05],L |
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SPIX INP H MOV [Y+05],A |
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RLCR [X+05] OUTP H MOV A,[Y+05] |
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RRCR [X+05] DSBC H ADD [Y+05] |
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RALR [X+05] shld 06A4 ADC [Y+05] |
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RARR [X+05] RRD SUB [Y+05] |
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SLAR [X+05] INP L SBB [Y+05] |
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SRAR [X+05] OUTP L ANA [Y+05] |
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SRLR [X+05] DADC H XRA [Y+05] |
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BIT 0,[X+05] lhld 06A4 ORA [Y+05] |
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BIT 1,[X+05] RLD CMP [Y+05] |
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BIT 2,[X+05] INP M POP Y |
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BIT 3,[X+05] OUTP M XTIY |
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BIT 4,[X+05] DSBC SP PUSH Y |
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BIT 5,[X+05] SSPD 06A4 PCIY |
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BIT 6,[X+05] INP A SPIY |
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BIT 7,[X+05] OUTP A RLCR [Y+05] |
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RES 0,[X+05] DADC SP RRCR [Y+05] |
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RES 1,[X+05] LSPD 06A4 RALR [Y+05] |
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RES 2,[X+05] LDI RARR [Y+05] |
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RES 3,[X+05] CCI SLAR [Y+05] |
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RES 4,[X+05] INI SRAR [Y+05] |
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RES 5,[X+05] OTI SRLR [Y+05] |
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RES 6,[X+05] LDD BIT 0,[Y+05] |
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RES 7,[X+05] CCD BIT 1,[Y+05] |
|||
SET 0,[X+05] IND BIT 2,[Y+05] |
|||
SET 1,[X+05] OTD BIT 3,[Y+05] |
|||
SET 2,[X+05] LDIR BIT 4,[Y+05] |
|||
SET 3,[X+05] CCIR BIT 5,[Y+05] |
|||
SET 4,[X+05] INIR BIT 6,[Y+05] |
|||
SET 5,[X+05] OTIR BIT 7,[Y+05] |
|||
SET 6,[X+05] LDDR RES 0,[Y+05] |
|||
SET 7,[X+05] CCDR RES 1,[Y+05] |
|||
INP B INDR RES 2,[Y+05] |
|||
OUTP B OTDR RES 3,[Y+05] |
|||
|
|||
|
|||
RES 4,[Y+05] SET 0,[Y+05] SET 4,[Y+05] |
|||
RES 5,[Y+05] SET 1,[Y+05] SET 5,[Y+05] |
|||
RES 6,[Y+05] SET 2,[Y+05] SET 6,[Y+05] |
|||
RES 7,[Y+05] SET 3,[Y+05] SET 7,[Y+05] |
|||
|
|||
; These are the result of disassembling 64180OPS.TRY |
|||
; These opcodes are available ONLY on the 64180 CPU |
|||
; DDTZ will both assemble and disassemble these. |
|||
IN0 B,20 TST E MLT B |
|||
OUT0 20,B IN0 H,20 MLT D |
|||
TST B OUT0 20,H TSTI 20 |
|||
IN0 C,20 TST H MLT H |
|||
OUT0 20,C IN0 L,20 TSIO 20 |
|||
TST C OUT0 20,L SLP |
|||
IN0 D,20 TST L MLT SP |
|||
OUT0 20,D TST M OTIM |
|||
TST D IN0 A,20 OTDM |
|||
IN0 E,20 OUT0 20,A OIMR |
|||
OUT0 20,E TST A ODMR |
|||
|
|||
; The following are UNDOCUMENTED z80 opcodes from XTDOPS.TRY. |
|||
; DDTZ will disassemble these, but will not assemble them. |
|||
; They use xh/xl (or yh/yl) as separate byte registers. |
|||
; Use these at your own risk. |
|||
INRX H ACXR H MOVY H,B |
|||
DCRX H ACXR L MOVY H,C |
|||
MVIX H,20 SUXR H MOVY H,D |
|||
INRX L SUXR L MOVY H,E |
|||
DCRX L SBXR H MOVY H,A |
|||
MVIX L,20 SBXR L MOVY L,B |
|||
MOVX B,H NDXR H MOVY L,C |
|||
MOVX B,L NDXR L MOVY L,D |
|||
MOVX C,H XRXR H MOVY L,E |
|||
MOVX C,L XRXR L MOVY L,A |
|||
MOVX D,H ORXR H MOVY A,H |
|||
MOVX D,L ORXR L MOVY A,L |
|||
MOVX E,H CPXR H ADYR H |
|||
MOVX E,L CPXR L ADYR L |
|||
MOVX H,B INRY H ACYR H |
|||
MOVX H,C DCRY H ACYR L |
|||
MOVX H,D MVIY H,20 SUYR H |
|||
MOVX H,E INRY L SUYR L |
|||
MOVX H,A DCRY L SBYR H |
|||
MOVX L,B MVIY L,20 SBYR L |
|||
MOVX L,C MOVY B,H NDYR H |
|||
MOVX L,D MOVY B,L NDYR L |
|||
MOVX L,E MOVY C,H XRYR H |
|||
MOVX L,A MOVY C,L XRYR L |
|||
MOVX A,H MOVY D,H ORYR H |
|||
MOVX A,L MOVY D,L ORYR L |
|||
ADXR H MOVY E,H CPYR H |
|||
ADXR L MOVY E,L CPYR L |
|||
|
|||
|
|||
Command Summary: |
|||
=============== |
|||
|
|||
DDTZM command DDTZ command |
|||
============= ============ |
|||
@ (base) |
|||
A)ssemble first_address A |
|||
B)egin {i.e., initialize stack and return} B |
|||
C)ompare first_address,last_address,against_address C |
|||
D)ump first_address[,last_address[,base]] D |
|||
E)nter_in_memory first_address[,base] S)ubstitute |
|||
F)ill first_address,last_address,value F |
|||
G)o_to [address][,trap1[,trap2]] G |
|||
H)ex_arithmetic value1(,value2) H |
|||
L)oad_file (offset) R)ead |
|||
M)ove first_address,last_address,destination M |
|||
N)nput FCBs_command_line I)nput |
|||
Q)uit (not avail) |
|||
R)egister examine/change [register|flag] X)amine |
|||
S)earch first_address,last_address,word W)hereis |
|||
T)race_execution [count] T |
|||
Untrace_execution [count] (i.e. do count instr) U)ntrace |
|||
U)nassemble_code first_address[,last_address] L)ist code |
|||
W)rite [first_address,last_address] K)eep |
|||
X)amine {i.e. display memory parameters for application} Q)uery |
|||
Y)our_option BC:=parm1,DE:=parm2,call_address Y |
|||
Z)80_register_display Z |
|||
|
|||
|
|||
If you find this program useful, contributions will be gratefully |
|||
accepted and will encourage further development and release of |
|||
useful CPM programs. My practice is to include source. |
|||
|
|||
C.B. Falconer |
|||
680 Hartford Turnpike, |
|||
Hamden, Conn. 06517 (203) 281-1438 |
|||
|
|||
DDTZ and its associated documentation and other files are |
|||
copyright (c) 1980-1988 by C.B. Falconer. They may be freely |
|||
copied and used for non-commercial purposes ONLY. |
|||
ôÙ |
|||
@ -1,535 +0,0 @@ |
|||
================================================================ |
|||
Floppy Disk Utility (FDU) v5.3 for RetroBrew Computers |
|||
Disk IO / Zeta / Dual-IDE / N8 / RC2014 / SmallZ80 / Dyno |
|||
================================================================ |
|||
|
|||
Updated January 5, 2020 |
|||
by Wayne Warthen (wwarthen@gmail.com) |
|||
|
|||
Application to test the hardware functionality of the Floppy |
|||
Disk Controller (FDC) on the ECB DISK I/O, DISK I/O V3, ZETA |
|||
SBC, Dual IDE w/ Floppy, or N8 board. |
|||
|
|||
The intent is to provide a testbed that allows direct testing |
|||
of all possible media types and modes of access. The |
|||
application supports read, write, and format by sector, track, |
|||
and disk as well as a random read/write test. |
|||
|
|||
The application supports access modes of polling, interrupt, |
|||
INT/WAIT, and DRQ/WAIT. At present, it supports 3.5" media at |
|||
DD (720KB) and HD (1.44MB) capacities. It also now supports |
|||
5.25" media (720KB and 1.2MB) and 8" media (1.11MB) as well. |
|||
Additional media will be added when I have time and access to |
|||
required hardware. Not all modes are supported on all |
|||
platforms and some modes are experimental in all cases. |
|||
|
|||
In many ways this application is merely reinventing the wheel |
|||
and performs functionality similar to existing applications, |
|||
but I have not seen any other applications for RetroBrew |
|||
Computers hardware that provide this range of functionality. |
|||
|
|||
While the application is now almost entirely new code, I would |
|||
like to acknowledge that much was derived from the previous |
|||
work of Andrew Lynch and Dan Werner. I also want to credit |
|||
Sergio Gimenez with testing the 5.25" drive support and Jim |
|||
Harre with testing the 8" drive support. Support for Zeta 2 |
|||
comes from Segey Kiselev. Thanks! |
|||
|
|||
General Usage |
|||
------------- |
|||
|
|||
In general, usage is self explanatory. At invocation, you |
|||
must select the floppy disk controller (FDC) that you are |
|||
using. Subsequently, the main menu allows you to set the |
|||
unit, media, and mode to test. These settings MUST match your |
|||
situation. Read, write, format, and verify functions are |
|||
provided. A sub-menu will allow you to choose sector, track, |
|||
disk, or random tests. |
|||
|
|||
The verify function requires a little explanation. It will |
|||
take the contents of the current in-memory disk buffer, save |
|||
it, and compare it to the selected sectors. So, you must |
|||
ensure that the sectors to be verified already have been |
|||
written with the same pattern as the buffer contains. I |
|||
typically init the buffer to a pattern, write the pattern to |
|||
the entire disk, then verify the entire disk. |
|||
|
|||
Another submenu is provided for FDC commands. This sub-menu |
|||
allows you to send low-level commands directly to FDC. You |
|||
*must* know what you are doing to use this sub-menu. For |
|||
example, in order to read a sector using this sub-menu, you |
|||
will need to perform specify, seek, sense int, and read |
|||
commands specifying correct values (nothing is value checked |
|||
in this menu). |
|||
|
|||
Required Hardware/BIOS |
|||
---------------------- |
|||
|
|||
Of course, the starting point is to have a supported hardware |
|||
configuration. The following Z80 / Z180 based CPU boards are |
|||
supported: |
|||
|
|||
- SBC V1/2 |
|||
- Zeta |
|||
- Zeta 2 |
|||
- N8 |
|||
- Mark IV |
|||
- RC2014 |
|||
- SmallZ80 |
|||
- Dyno |
|||
- MBC |
|||
|
|||
You must be using either a RomWBW or UBA based OS version. |
|||
|
|||
You must have one of the following floppy disk controllers: |
|||
|
|||
- Disk IO ECB Board FDC |
|||
- Disk IO 3 ECB Board FDC |
|||
- Dual-IDE ECB Board FDC |
|||
- Zeta SBC onboard FDC |
|||
- Zeta 2 SBC onboard FDC |
|||
- N8 SBC onboard FDC |
|||
- RC2014 Scott Baker SMC-based Floppy Module |
|||
- RC2014 Scott Baker WDC-based Floppy Module |
|||
- SmallZ80 FDC |
|||
- Dyno FDC |
|||
- MBC FDC |
|||
|
|||
Finally, you will need a floppy drive connected via an |
|||
appropriate cable: |
|||
|
|||
Disk IO - no twist in cable, drive unit 0/1 must be selected by jumper on drive |
|||
DISK IO 3, Zeta, Zeta 2, RC2014, Dyno - cable with twist, unit 0 after twist, unit 1 before twist |
|||
DIDE, N8, Mark IV, SmallZ80 - cable with twist, unit 0 before twist, unit 1 after twist |
|||
|
|||
Note that FDU does not utilize your systems ROM or OS to |
|||
access the floppy system. FDU interacts directly with |
|||
hardware. Upon exit, you may need to reset your OS to get the |
|||
floppy system back into a state that is expected. |
|||
|
|||
The Disk I/O should be jumpered as follows: |
|||
|
|||
J1: depends on use of interrupt modes (see interrupt modes below) |
|||
J2: pins 1-2, & 3-4 jumpered |
|||
J3: hardware dependent timing for DMA mode (see DMA modes below) |
|||
J4: pins 2-3 jumpered |
|||
J5: off |
|||
J6: pins 2-3 jumpered |
|||
J7: pins 2-3 jumpered |
|||
J8: off |
|||
J9: off |
|||
J10: off |
|||
J11: off |
|||
J12: off |
|||
|
|||
Note that J1 can be left on even when not using interrupt |
|||
modes. As long as the BIOS is OK with it, that is fine. Note |
|||
also that J3 is only relevant for DMA modes, but also can be |
|||
left in place when using other modes. |
|||
|
|||
The Disk I/O 3 board should be jumpered at the default settings: |
|||
|
|||
JP2: 3-4 |
|||
JP3: 1-2 for int mode support, otherwise no jumper |
|||
JP4: 1-2, 3-4 |
|||
JP5: 1-2 |
|||
JP6: 1-2 |
|||
JP7: 1-2, 3-4 |
|||
|
|||
Zeta & Zeta 2 do not have any relevant jumper settings. The |
|||
hardwired I/O ranges are assumed in the code. |
|||
|
|||
The Dual-IDE board should be jumpered as follows: |
|||
|
|||
K3 (DT/R or /RD): /RD |
|||
P5 (bd ID): 1-2, 3-4 (for $20-$3F port range) |
|||
|
|||
There are no specific N8 jumper settings, but the default |
|||
I/O range starting at $80 is assumed in the published code. |
|||
|
|||
The RC2014 Scott Baker SMC-based floppy module should be jumpered |
|||
for I/O base address 0x50 (SV1: 11-12), JP1 (TS) shorted, |
|||
JP2 (/FAULT) shorted, JP3 (MINI): 2-3, JP4 (/DC/RDY): 2-3. |
|||
|
|||
The RC2014 Scott Baker WDC-based floppy module should be jumpered |
|||
for I/O base address 0x50 (SV1: 11-12), JP1 (/DACK): 1-2, |
|||
JP2 (TC): 2-3. |
|||
|
|||
The RC2014 FDC by Alan Cox (Etched Pixels) needs to be strapped |
|||
for base I/O address 0x48. |
|||
|
|||
SmallZ80 does not have any relevant jumper settings. The |
|||
hardwired I/O ranges are assumed in the code. |
|||
|
|||
Dyno does not have any relevant jumper settings. The |
|||
hardwired I/O ranges are assumed in the code. |
|||
|
|||
The MBC FDC is expected to be strapped to use neither INT nor NMI. It |
|||
is also not expected to use DMA. |
|||
|
|||
Modes of Operation |
|||
------------------ |
|||
|
|||
You can select the following test modes. Please refer to the |
|||
chart that follows to determine which modes should work with |
|||
combinations of Z80 CPU speed and media format. |
|||
|
|||
WARNING: In general, only the polling mode is considered fully |
|||
reliable. The other modes are basically experimental and |
|||
should only be used if you know exactly what you are doing. |
|||
|
|||
Polling: Traditional polled input/output. Works well and very |
|||
reliable with robust timeouts and good error recovery. Also, |
|||
the slowest performance which precludes it from being used |
|||
with 1.44MB floppy on a 4MHz Z80. This is definitely the mode |
|||
you want to get working before any others. It does not require |
|||
J1 (interrupt enable) on DISK I/O and does not care about the |
|||
setting of J3. |
|||
|
|||
Interrupt: Relies on FDC interrupts to determine when a byte |
|||
is ready to be read/written. It does *not* implement a |
|||
timeout during disk operations. For example, if there is no |
|||
disk in the drive, this mode will just hang until a disk is |
|||
inserted. This mode *requires* that the host has interrupts |
|||
active using interrupt mode 1 (IM1) and interrupts attached to |
|||
the FDC controller. The BIOS must be configured to handle |
|||
these interrupts safely. |
|||
|
|||
Fast Interrupt: Same as above, but sacrifices additional |
|||
reliability for faster operation. This mode will allow a |
|||
1.44MB floppy to work with a 4MHz Z80 CPU. However, if any |
|||
errors occur (even a transient read error which is not |
|||
unusual), this mode will hang. The same FDC interrupt |
|||
requirements as above are required. |
|||
|
|||
INT/WAIT: Same as Fast Interrupt, but uses CPU wait instead of |
|||
actual interrupt. This mode is exclusive to the original Disk |
|||
IO board. It is subject to all the same issues as Fast |
|||
Interrupt, but does not need J1 shorted. J3 is irrelevant. |
|||
|
|||
DRQ/WAIT: Uses pseudo DMA to handle input/output. Does not |
|||
require that interrupts (J1) be enabled on the DISK I/O. |
|||
However, it is subject to all of the same reliability issues |
|||
as "Fast Interrupt". This mode is exclusive to the original |
|||
Disk IO board. At present, the mode is *not* implemented! |
|||
|
|||
The chart below attempts to describe the combinations that |
|||
work for me. By far, the most reliable mode is Polling, but |
|||
it requires 8MHz CPU for HD disks. |
|||
|
|||
DRQ/WAIT --------------------------------+ |
|||
INT/WAIT -----------------------------+ | |
|||
Fast Interrupt --------------------+ | | |
|||
Interrupt ----------------------+ | | | |
|||
Polling ---------------------+ | | | | |
|||
| | | | | |
|||
CPU Speed --------------+ | | | | | |
|||
| | | | | | |
|||
| | | | | | |
|||
|
|||
3.5" DD (720K) ------ 4MHz Y Y Y Y X |
|||
8MHz+ Y Y Y Y X |
|||
|
|||
3.5" HD (1.44M) ----- 4MHz N N Y Y X |
|||
8MHz+ Y Y Y Y X |
|||
|
|||
5.25" DD (360K) ----- 4MHz Y Y Y Y X |
|||
8MHz+ Y Y Y Y X |
|||
|
|||
5.25" HD (1.2M) ----- 4MHz N N Y Y X |
|||
8MHz+ Y Y Y Y X |
|||
|
|||
8" DD (1.11M) ------- 4MHz N N Y Y X |
|||
8MHz+ Y Y Y Y X |
|||
|
|||
Y = Yes, works |
|||
N = No, does not work |
|||
X = Experimental, probably won't work |
|||
|
|||
Tracing |
|||
------- |
|||
|
|||
Command/result activity to/from the FDC will be written out if |
|||
the trace setting is changed from '00' to '01' in setup. |
|||
Additionally, if a command failure is detected on any command, |
|||
that specific comand and results are written regardless of the |
|||
trace setting. |
|||
|
|||
The format of the line written is: |
|||
<OPERATION>: <COMMAND BYTES> --> <RESULT BYTES> [<RESULT>] |
|||
|
|||
For example, this is the output of a normal read operation: |
|||
READ: 46 01 00 00 01 02 09 1B FF --> 01 00 00 00 00 02 02 [OK] |
|||
|
|||
Please refer to the i8272 data sheet for information on the |
|||
command and result bytes. |
|||
|
|||
Note that the sense interrupt command can return a non-OK |
|||
result. This is completely normal in some cases. It is |
|||
necessary to "poll" the drive for seek status using sense |
|||
interrupt. If there is nothing to report, then the result |
|||
will be INVALID COMMAND. Additionally, during a recalibrate |
|||
operation, it may be necessary to issue the command twice |
|||
because the command will only step the drive 77 times looking |
|||
for track 0, but the head may be up to 80 tracks away. In |
|||
this case, the first recalibrate fails, but the second should |
|||
succeed. Here is what this would look like if trace is turned |
|||
on: |
|||
|
|||
RECALIBRATE: 07 01 --> <EMPTY> [OK] |
|||
SENSE INTERRUPT: 08 --> 80 [INVALID COMMAND] |
|||
... |
|||
... |
|||
... |
|||
SENSE INTERRUPT: 08 --> 80 [INVALID COMMAND] |
|||
SENSE INTERRUPT: 08 --> 71 00 [ABNORMAL TERMINATION] |
|||
RECALIBRATE: 07 01 --> <EMPTY> [OK] |
|||
SENSE INTERRUPT: 08 --> 21 00 [OK] |
|||
|
|||
Another example is when the FDC has just been reset. In this |
|||
case, you will see up to 4 disk change errors. Again these |
|||
are not a real problem and to be expected. |
|||
|
|||
When tracing is turned off, the application tries to be |
|||
intelligent about error reporting. The specific errors from |
|||
sense interrupt documented above will be suppressed because |
|||
they are not a real problem. All other errors will be |
|||
displayed. |
|||
|
|||
Error Handling |
|||
-------------- |
|||
|
|||
There is no automated error retry logic. This is very |
|||
intentional since the point is to expose the controller and |
|||
drive activity. Any error detected will result in a prompt to |
|||
abort, retry, or continue. Note that some number of errors is |
|||
considered normal for this technology. An occasional error |
|||
would not necessarily be considered a problem. |
|||
|
|||
CPU Speed |
|||
--------- |
|||
|
|||
Starting with v5.0, the application adjusts it's timing loops |
|||
to the actual system CPU speed by querying the BIOS for the |
|||
current CPU speed. |
|||
|
|||
Interleave |
|||
---------- |
|||
|
|||
The format command now allows the specification of a sector |
|||
interleave. It is almost always the case that the optimal |
|||
interleave will be 2 (meaning 2:1). |
|||
|
|||
360K Media |
|||
---------- |
|||
|
|||
The 360K media definition should work well for true 360K |
|||
drives. However, it will generally not work with 1.2M |
|||
drives. This is because these drives spin at 360RPM instead |
|||
of the 300RPM speed of true 360K drives. Additionally, 1.2M |
|||
drives are 80 tracks and 360K drives are 40 tracks and, so |
|||
far, there is no mechanism in FD to "double step" as a way to |
|||
use 40 track media in 80 track drives. |
|||
|
|||
With this said, it is possible to configure some 1.2M 5.25" |
|||
drives to automatically spin down to 300RPM based on a density |
|||
select signal (DENSEL). This signal is asserted by FD for |
|||
360K media, so IF you have configured your drive to react to |
|||
this signal correctly, you will be able to use the 360K media |
|||
defintion. Most 1.2M 5.25" drives are NOT configured this way |
|||
by default. TEAC drives are generally easy to modify and have |
|||
been tested by the author and do work in this manner. Note |
|||
that this does not address the issue of double stepping above; |
|||
you will just be using the first 40 of 80 tracks. |
|||
|
|||
Support |
|||
------- |
|||
|
|||
I am happy to answer questions as fast and well as I am able. |
|||
Best contact is wwarthen@gmail.com or post something on the |
|||
RetroBrew Computers Forum |
|||
https://www.retrobrewcomputers.org/forum/. |
|||
|
|||
Changes |
|||
------- |
|||
|
|||
WW 8/12/2011 |
|||
|
|||
Removed call to pulse TC in the FDC initialization after |
|||
determining that it periodically caused the FDC to write bad |
|||
sectors. I am mystified by this, but definitely found it to |
|||
be true. Will revisit at some point -- probably a timing |
|||
issue between puslsing TC and whatever happens next. |
|||
|
|||
Non-DMA mode was being set incorrectly for FAST-DMA mode. It |
|||
was set for non-DMA even though we were doing DMA. It is |
|||
interesting that it worked fine anyway. Fixed it anyway. |
|||
|
|||
DIO_SETMEDIA was not clearing DCD_DSKRDY as it should. Fixed. |
|||
|
|||
WW 8/26/2011: v1.1 |
|||
|
|||
Added support for Zeta. Note that INT/WAIT and DRQ/WAIT are |
|||
not available on Zeta. Note that Zeta provides the ability to |
|||
perform a reset of the FDC independent of a full CPU reset. |
|||
This is VERY useful and the FDC is reset anytime a drive reset |
|||
is required. |
|||
|
|||
Added INT/WAIT support. |
|||
|
|||
WW 8/28/2011: V1.2 |
|||
|
|||
All changes in this version are Zeta specific. Fixed FDC |
|||
reset logic and motor status display for Zeta (code from |
|||
Sergey). |
|||
|
|||
Modified Zeta disk change display to include it in the command |
|||
output line. This makes more sense because a command must be |
|||
issued to select the desired drive first. You can use the |
|||
SENSE INT command id you want to check the disk change value |
|||
at any time. It will also be displayed with any other command |
|||
output display. |
|||
|
|||
WW 9/1/2011: V1.3 |
|||
|
|||
Added CPUFREQ configuration setting to tune delays based on |
|||
cpu speed. The build app is set for 8MHz which also seems to |
|||
work well for 4MHz CPU's. Faster CPU speeds will probably |
|||
require tuning this setting. |
|||
|
|||
WW 9/5/2011: V1.4 |
|||
|
|||
Changed the polling execution routines to utilize CPUFREQ |
|||
variable to optimize timeout counter. Most importantly, this |
|||
should allow the use of faster CPUs (like 20MHz). |
|||
|
|||
WW 9/19/2011: V1.5 |
|||
|
|||
Zeta changes only. Added a call to FDC RESET after any |
|||
command failure. This solves an issue where the drive remains |
|||
selected if a command error occurs. Also added FDC RESET to |
|||
FDC CONTROL menu. |
|||
|
|||
WW 10/7/2011: V2.0 |
|||
|
|||
Added support for DIDE. Only supports polling IO and it does |
|||
not appear any other modes are possible given the hardware |
|||
constraints. |
|||
|
|||
WW 10/13/2011: V2.1 |
|||
|
|||
Modified to support N8. N8 is essentially identical to Dual |
|||
IDE. The only real change is the IO addresses. In theory, I |
|||
should be able to support true DMA on N8 and will work on that. |
|||
|
|||
WW 10/20/2011: v2.2 |
|||
|
|||
I had some problems with the results being read were sometimes |
|||
missing a byte. Fixed this by taking a more strict approach |
|||
to watching the MSR for the exact bits that are expected. |
|||
|
|||
WW 10/22/2011: V2.3 |
|||
|
|||
After spending a few days trying to track down an intermittent |
|||
data corruption issue with my Dual IDE board, I added a verify |
|||
function. This helped me isolate the problem very nicely |
|||
(turned out to be interference from the bus monitor). |
|||
|
|||
WW 11/25/2011: V2.4 |
|||
|
|||
Preliminary support for DISKIO V3. Basically just assumed |
|||
that it operates just like the Zeta. Needs to be verified |
|||
with real hardware as soon as I can. |
|||
|
|||
WW 1/9/2012: V2.5 |
|||
|
|||
Modified program termination to use CP/M reset call so that a |
|||
warm start is done and all drives are logged out. This is |
|||
important because media may have been formatted during the |
|||
program execution. |
|||
|
|||
WW 2/6/2012: v2.6 |
|||
|
|||
Added support for 5.25" drives as tested by Sergio. |
|||
|
|||
WW 4/5/2012: v2.7 |
|||
|
|||
Added support for 8" drives as tested by Jim Harre. |
|||
|
|||
WW 4/6/2012: v2.7a |
|||
|
|||
Fixed issue with media selection menu to remove duplicate |
|||
entries. |
|||
|
|||
WW 4/8/2012: v2.7b |
|||
|
|||
Corrected the handling of the density select signal. |
|||
|
|||
WW 5/22/2012: v2.8 |
|||
|
|||
Added new media definitions (5.25", 320K). |
|||
|
|||
WW 6/1/2012: v2.9 |
|||
|
|||
Added interleave capability on format. |
|||
|
|||
WW 6/5/2012: v3.0 |
|||
|
|||
Documentation cleanup. |
|||
|
|||
WW 7/1/2012: v3.1 |
|||
|
|||
Modified head load time (HLT) for 8" media based on YD-180 |
|||
spec. Now set to 50ms. |
|||
|
|||
WW 6/17/2013: v3.2 |
|||
|
|||
Cleaned up SRT, HLT, and HUT values. |
|||
|
|||
SK 2/10/2015: v3.3 |
|||
|
|||
Added Zeta SBC v2 support (Sergey Kiselev) |
|||
|
|||
WW 3/25/2015: v4.0 |
|||
|
|||
Renamed from FDTST --> FD |
|||
|
|||
WW 9/2/2017: v5.0 |
|||
|
|||
Renamed from FD to FDU. |
|||
Added runtime selection of FDC hardware. |
|||
Added runtime timing adjustment. |
|||
|
|||
WW 12/16/2017: v5.1 |
|||
|
|||
Improved polling version of read/write to fix occasional overrun errors. |
|||
|
|||
WW 1/8/2018: v5.2 |
|||
|
|||
Added support for RC2014 hardware: |
|||
- Scott Baker SMC 9266 FDC module |
|||
- Scott Baker WDC 37C65 FDC module |
|||
|
|||
WW 9/5/2018: v5.3 |
|||
- Removed use of pulsing TC to end R/W operations after one sector and |
|||
instead set EOT = R (sector number) so that after desired sector is |
|||
read, R/W stops with end of cylinder error which is a documented |
|||
method for controling number of sectors R/W. This specific termination |
|||
condition is no longer considered an error, but a successful end of |
|||
operation. |
|||
- Added support for SmallZ80 |
|||
|
|||
WW 1/5/2020: v5.4 |
|||
- Added support for Dyno (based on work by Steve Garcia) |
|||
|
|||
WW 4/29/2020: v5.5 |
|||
- Added support for Etched Pixels FDC |
|||
|
|||
WW 12/12/2020: v5.6 |
|||
- Updated SmallZ80 support for new I/O map |
|||
|
|||
WW 3/24/2021: v5.7 |
|||
- Added support for a few single-sided formats |
|||
|
|||
WW 7/26/2021: v5.8 |
|||
- Added support for MBC FDC |
|||
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Reference in new issue