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S100 2CF+1SD CF Interface Support 

- Implemented for FZ80 and Z180 CPU boards.
- Base I/O for FZ80 is moved from $30 to $38 to avoid conflict with FZ80 built-in CF interface.
pull/609/head v3.6.0-dev.16
Wayne Warthen 6 months ago
parent
a68ae0cd24
commit
e4c55edc02
No known key found for this signature in database GPG Key ID: 8B34ED29C07EEB0A
30 changed files with 229 additions and 56 deletions
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  1. 1
      Doc/ChangeLog.txt
  2. 4
      Source/HBIOS/Config/S100_std.asm
  3. 5
      Source/HBIOS/cfg_DUO.asm
  4. 5
      Source/HBIOS/cfg_DYNO.asm
  5. 5
      Source/HBIOS/cfg_EPITX.asm
  6. 5
      Source/HBIOS/cfg_EZZ80.asm
  7. 11
      Source/HBIOS/cfg_FZ80.asm
  8. 5
      Source/HBIOS/cfg_GMZ180.asm
  9. 5
      Source/HBIOS/cfg_HEATH.asm
  10. 5
      Source/HBIOS/cfg_MASTER.asm
  11. 5
      Source/HBIOS/cfg_MBC.asm
  12. 5
      Source/HBIOS/cfg_MK4.asm
  13. 5
      Source/HBIOS/cfg_MON.asm
  14. 5
      Source/HBIOS/cfg_N8.asm
  15. 5
      Source/HBIOS/cfg_NABU.asm
  16. 5
      Source/HBIOS/cfg_RCEZ80.asm
  17. 5
      Source/HBIOS/cfg_RCZ180.asm
  18. 5
      Source/HBIOS/cfg_RCZ280.asm
  19. 5
      Source/HBIOS/cfg_RCZ80.asm
  20. 5
      Source/HBIOS/cfg_RPH.asm
  21. 13
      Source/HBIOS/cfg_S100.asm
  22. 5
      Source/HBIOS/cfg_SBC.asm
  23. 5
      Source/HBIOS/cfg_SCZ180.asm
  24. 1
      Source/HBIOS/cfg_Z80RETRO.asm
  25. 1
      Source/HBIOS/cfg_ZETA.asm
  26. 1
      Source/HBIOS/cfg_ZETA2.asm
  27. 133
      Source/HBIOS/ppide.asm
  28. 21
      Source/HBIOS/std.asm
  29. 2
      Source/ver.inc
  30. 2
      Source/ver.lib

1
Doc/ChangeLog.txt
View File

@ -21,6 +21,7 @@ Version 3.6
- WBW: Implemented config driven slice name and system image specification
- D?N: Added native USB driver support (keyboard, floppy, mass storage)
- MGG: Added sample program source files for all language disk iamges
- WBW: Added support for S100 Dual CF Interface
Version 3.5.1
-------------

4
Source/HBIOS/Config/S100_std.asm
View File

@ -55,7 +55,7 @@ CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ
;
Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .SET 1 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 2 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
Z180_IOWAIT .SET 3 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
;
CRTACT .SET TRUE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
@ -66,7 +66,7 @@ SCONENABLE .SET TRUE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
;
IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
;
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
;
SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]

5
Source/HBIOS/cfg_DUO.asm
View File

@ -282,15 +282,18 @@ IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
PPIDE0MODE .SET PPIDEMODE_STD ; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE0BASE .SET $88 ; PPIDE 0: PPI REGISTERS BASE ADR
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE1MODE .SET PPIDEMODE_STD ; PPIDE 1: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE1BASE .SET $20 ; PPIDE 1: PPI REGISTERS BASE ADR
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2MODE .SET PPIDEMODE_STD ; PPIDE 2: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE2BASE .SET $14 ; PPIDE 2: PPI REGISTERS BASE ADR
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]

5
Source/HBIOS/cfg_DYNO.asm
View File

@ -297,15 +297,18 @@ IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
PPIDE0MODE .SET PPIDEMODE_STD ; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE0BASE .SET $4C ; PPIDE 0: PPI REGISTERS BASE ADR
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE1MODE .SET PPIDEMODE_STD ; PPIDE 1: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2MODE .SET PPIDEMODE_STD ; PPIDE 2: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]

5
Source/HBIOS/cfg_EPITX.asm
View File

@ -293,15 +293,18 @@ IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
PPIDE0MODE .SET PPIDEMODE_STD ; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE0BASE .SET $20 ; PPIDE 0: PPI REGISTERS BASE ADR
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE1MODE .SET PPIDEMODE_STD ; PPIDE 1: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2MODE .SET PPIDEMODE_STD ; PPIDE 2: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_EPITX ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]

5
Source/HBIOS/cfg_EZZ80.asm
View File

@ -302,15 +302,18 @@ IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
PPIDE0MODE .SET PPIDEMODE_STD ; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE0BASE .SET $20 ; PPIDE 0: PPI REGISTERS BASE ADR
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE1MODE .SET PPIDEMODE_STD ; PPIDE 1: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2MODE .SET PPIDEMODE_STD ; PPIDE 2: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_PIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]

11
Source/HBIOS/cfg_FZ80.asm
View File

@ -301,16 +301,19 @@ IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
;
PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
PPIDECNT .SET 3 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
PPIDE0MODE .SET PPIDEMODE_STD ; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE0BASE .SET $30 ; PPIDE 0: PPI REGISTERS BASE ADR
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR
PPIDE1MODE .SET PPIDEMODE_S100A ; PPIDE 1: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE1BASE .SET $38 ; PPIDE 1: PPI REGISTERS BASE ADR
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR
PPIDE2MODE .SET PPIDEMODE_S100B ; PPIDE 2: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE2BASE .SET $38 ; PPIDE 2: PPI REGISTERS BASE ADR
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_FZ80 ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]

5
Source/HBIOS/cfg_GMZ180.asm
View File

@ -292,15 +292,18 @@ IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
PPIDE0MODE .SET PPIDEMODE_STD ; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE0BASE .SET $20 ; PPIDE 0: PPI REGISTERS BASE ADR
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE1MODE .SET PPIDEMODE_STD ; PPIDE 1: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2MODE .SET PPIDEMODE_STD ; PPIDE 2: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_GM ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]

5
Source/HBIOS/cfg_HEATH.asm
View File

@ -302,15 +302,18 @@ IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
PPIDE0MODE .SET PPIDEMODE_STD ; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE0BASE .SET $20 ; PPIDE 0: PPI REGISTERS BASE ADR
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE1MODE .SET PPIDEMODE_STD ; PPIDE 1: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2MODE .SET PPIDEMODE_STD ; PPIDE 2: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]

5
Source/HBIOS/cfg_MASTER.asm
View File

@ -361,15 +361,18 @@ IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
PPIDE0MODE .EQU PPIDEMODE_NONE ; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE0BASE .EQU $60 ; PPIDE 0: PPI REGISTERS BASE ADR
PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE1MODE .EQU PPIDEMODE_NONE ; PPIDE 1: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE1BASE .EQU $20 ; PPIDE 1: PPI REGISTERS BASE ADR
PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2MODE .EQU PPIDEMODE_NONE ; PPIDE 2: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE2BASE .EQU $14 ; PPIDE 2: PPI REGISTERS BASE ADR
PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2B8BIT .EQU FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_NONE ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]

5
Source/HBIOS/cfg_MBC.asm
View File

@ -276,15 +276,18 @@ IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
PPIDE0MODE .SET PPIDEMODE_STD ; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE0BASE .SET $60 ; PPIDE 0: PPI REGISTERS BASE ADR
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE1MODE .SET PPIDEMODE_STD ; PPIDE 1: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE1BASE .SET $20 ; PPIDE 1: PPI REGISTERS BASE ADR
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2MODE .SET PPIDEMODE_STD ; PPIDE 2: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE2BASE .SET $14 ; PPIDE 2: PPI REGISTERS BASE ADR
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]

5
Source/HBIOS/cfg_MK4.asm
View File

@ -287,15 +287,18 @@ IDE2B8BIT .SET FALSE ; IDE 2B (MASTER): 8 BIT XFER
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDECNT .SET 2 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
PPIDE0MODE .SET PPIDEMODE_STD ; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE0BASE .SET $14 ; PPIDE 0: PPI REGISTERS BASE ADR
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE1MODE .SET PPIDEMODE_STD ; PPIDE 1: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE1BASE .SET $20 ; PPIDE 1: PPI REGISTERS BASE ADR
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2MODE .SET PPIDEMODE_STD ; PPIDE 2: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_MK4 ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]

5
Source/HBIOS/cfg_MON.asm
View File

@ -299,15 +299,18 @@ IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
PPIDE0MODE .SET PPIDEMODE_STD ; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE0BASE .SET $20 ; PPIDE 0: PPI REGISTERS BASE ADR
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE1MODE .SET PPIDEMODE_STD ; PPIDE 1: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2MODE .SET PPIDEMODE_STD ; PPIDE 2: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]

5
Source/HBIOS/cfg_N8.asm
View File

@ -289,15 +289,18 @@ IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
PPIDE0MODE .SET PPIDEMODE_STD ; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE0BASE .SET N8_PPI0 ; PPIDE 0: PPI REGISTERS BASE ADR
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE1MODE .SET PPIDEMODE_STD ; PPIDE 1: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2MODE .SET PPIDEMODE_STD ; PPIDE 2: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]

5
Source/HBIOS/cfg_NABU.asm
View File

@ -302,15 +302,18 @@ IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
PPIDE0MODE .SET PPIDEMODE_STD ; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE0BASE .SET $60 ; PPIDE 0: PPI REGISTERS BASE ADR
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE1MODE .SET PPIDEMODE_STD ; PPIDE 1: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2MODE .SET PPIDEMODE_STD ; PPIDE 2: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]

5
Source/HBIOS/cfg_RCEZ80.asm
View File

@ -300,15 +300,18 @@ IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
PPIDE0MODE .SET PPIDEMODE_STD ; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE0BASE .SET $20 ; PPIDE 0: PPI REGISTERS BASE ADR
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE1MODE .SET PPIDEMODE_STD ; PPIDE 1: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2MODE .SET PPIDEMODE_STD ; PPIDE 2: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]

5
Source/HBIOS/cfg_RCZ180.asm
View File

@ -297,15 +297,18 @@ IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
PPIDE0MODE .SET PPIDEMODE_STD ; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE0BASE .SET $20 ; PPIDE 0: PPI REGISTERS BASE ADR
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE1MODE .SET PPIDEMODE_STD ; PPIDE 1: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2MODE .SET PPIDEMODE_STD ; PPIDE 2: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_PIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]

5
Source/HBIOS/cfg_RCZ280.asm
View File

@ -307,15 +307,18 @@ IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
PPIDE0MODE .SET PPIDEMODE_STD ; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE0BASE .SET $20 ; PPIDE 0: PPI REGISTERS BASE ADR
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE1MODE .SET PPIDEMODE_STD ; PPIDE 1: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2MODE .SET PPIDEMODE_STD ; PPIDE 2: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_PIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]

5
Source/HBIOS/cfg_RCZ80.asm
View File

@ -305,15 +305,18 @@ IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
PPIDE0MODE .SET PPIDEMODE_STD ; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE0BASE .SET $20 ; PPIDE 0: PPI REGISTERS BASE ADR
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE1MODE .SET PPIDEMODE_STD ; PPIDE 1: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2MODE .SET PPIDEMODE_STD ; PPIDE 2: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_PIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]

5
Source/HBIOS/cfg_RPH.asm
View File

@ -277,15 +277,18 @@ IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
PPIDE0MODE .SET PPIDEMODE_STD ; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE0BASE .SET RPH_PPI0 ; PPIDE 0: PPI REGISTERS BASE ADR
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE1MODE .SET PPIDEMODE_STD ; PPIDE 1: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2MODE .SET PPIDEMODE_STD ; PPIDE 2: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]

13
Source/HBIOS/cfg_S100.asm
View File

@ -84,7 +84,7 @@ MPGENA .SET $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
Z180_BASE .SET $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .SET 1 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 2 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
Z180_IOWAIT .SET 3 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
Z180_TIMER .SET TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
;
RTCIO .SET $0C ; RTC LATCH REGISTER ADR
@ -296,16 +296,19 @@ IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
;
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
PPIDE0BASE .SET $20 ; PPIDE 0: PPI REGISTERS BASE ADR
PPIDECNT .SET 2 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
PPIDE0MODE .SET PPIDEMODE_S100A ; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE0BASE .SET $30 ; PPIDE 0: PPI REGISTERS BASE ADR
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR
PPIDE1MODE .SET PPIDEMODE_S100B ; PPIDE 1: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE1BASE .SET $30 ; PPIDE 1: PPI REGISTERS BASE ADR
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2MODE .SET PPIDEMODE_NONE ; PPIDE 2: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]

5
Source/HBIOS/cfg_SBC.asm
View File

@ -277,15 +277,18 @@ IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
PPIDE0MODE .SET PPIDEMODE_STD ; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE0BASE .SET $60 ; PPIDE 0: PPI REGISTERS BASE ADR
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE1MODE .SET PPIDEMODE_STD ; PPIDE 1: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE1BASE .SET $20 ; PPIDE 1: PPI REGISTERS BASE ADR
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2MODE .SET PPIDEMODE_STD ; PPIDE 2: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE2BASE .SET $14 ; PPIDE 2: PPI REGISTERS BASE ADR
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]

5
Source/HBIOS/cfg_SCZ180.asm
View File

@ -297,15 +297,18 @@ IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
PPIDE0MODE .SET PPIDEMODE_STD ; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE0BASE .SET $20 ; PPIDE 0: PPI REGISTERS BASE ADR
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE1MODE .SET PPIDEMODE_STD ; PPIDE 1: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2MODE .SET PPIDEMODE_STD ; PPIDE 2: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]

1
Source/HBIOS/cfg_Z80RETRO.asm
View File

@ -263,6 +263,7 @@ IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
PPIDE0MODE .SET PPIDEMODE_STD ; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE0BASE .SET $60 ; PPIDE 0: PPI REGISTERS BASE ADR
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER

1
Source/HBIOS/cfg_ZETA.asm
View File

@ -232,6 +232,7 @@ IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
PPIDE0MODE .SET PPIDEMODE_STD ; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE0BASE .SET $60 ; PPIDE 0: PPI REGISTERS BASE ADR
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER

1
Source/HBIOS/cfg_ZETA2.asm
View File

@ -243,6 +243,7 @@ IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
PPIDE0MODE .SET PPIDEMODE_STD ; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE0BASE .SET $60 ; PPIDE 0: PPI REGISTERS BASE ADR
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER

133
Source/HBIOS/ppide.asm
View File

@ -189,21 +189,22 @@ PPIDE_DRVSLAVE .EQU %11110000 ; LBA, SLAVE DEVICE
;
; PPIDE DEVICE CONFIGURATION
;
PPIDE_CFGSIZ .EQU 18 ; SIZE OF CFG TBL ENTRIES
PPIDE_CFGSIZ .EQU 19 ; SIZE OF CFG TBL ENTRIES
;
; PER DEVICE DATA OFFSETS
;
PPIDE_DEV .EQU 0 ; OFFSET OF DEVICE NUMBER (BYTE)
PPIDE_STAT .EQU 1 ; LAST STATUS (BYTE)
PPIDE_TYPE .EQU 2 ; DEVICE TYPE (BYTE)
PPIDE_ACC .EQU 3 ; ACCESS FLAG BITS BIT 0=MASTER, 1=8BIT (BYTE)
PPIDE_MED .EQU 4 ; MEDIA FLAG BITS BIT 0=CF, 1=LBA (BYTE)
PPIDE_MEDCAP .EQU 5 ; MEDIA CAPACITY (DWORD)
PPIDE_LBA .EQU 9 ; OFFSET OF LBA (DWORD)
PPIDE_DATALO .EQU 13 ; BASE PORT AND IDE DATA BUS LSB (8255 PORT A) (BYTE)
PPIDE_CTL .EQU 14 ; IDE ADDRESS BUS AND CONTROL SIGNALS (8255 PORT C)(BYTE)
PPIDE_PPI .EQU 15 ; 8255 CONTROL PORT(BYTE)
PPIDE_PARTNER .EQU 16 ; PARTNER DEVICE (MASTER <-> SLAVE) (WORD)
PPIDE_MODE .EQU 1 ; OPERATION MODE: PPIDE MODE (BYTE)
PPIDE_STAT .EQU 2 ; LAST STATUS (BYTE)
PPIDE_TYPE .EQU 3 ; DEVICE TYPE (BYTE)
PPIDE_ACC .EQU 4 ; ACCESS FLAG BITS BIT 0=MASTER, 1=8BIT (BYTE)
PPIDE_MED .EQU 5 ; MEDIA FLAG BITS BIT 0=CF, 1=LBA (BYTE)
PPIDE_MEDCAP .EQU 6 ; MEDIA CAPACITY (DWORD)
PPIDE_LBA .EQU 10 ; OFFSET OF LBA (DWORD)
PPIDE_DATALO .EQU 14 ; BASE PORT AND IDE DATA BUS LSB (8255 PORT A) (BYTE)
PPIDE_CTL .EQU 15 ; IDE ADDRESS BUS AND CONTROL SIGNALS (8255 PORT C)(BYTE)
PPIDE_PPI .EQU 16 ; 8255 CONTROL PORT(BYTE)
PPIDE_PARTNER .EQU 17 ; PARTNER DEVICE (MASTER <-> SLAVE) (WORD)
;
PPIDE_ACC_MAS .EQU %00000001 ; UNIT IS MASTER (ELSE SLAVE)
PPIDE_ACC_8BIT .EQU %00000010 ; UNIT WANTS 8 BIT I/O (ELSE 16 BIT)
@ -219,6 +220,7 @@ PPIDE_CFGTBL:
;
PPIDE_DEV0M: ; DEVICE 0, MASTER
.DB $FE ; DRIVER DEVICE NUMBER (FILLED DYNAMICALLY)
.DB PPIDE0MODE ; DRIVER DEVICE MODE
.DB 0 ; DEVICE STATUS
.DB 0 ; DEVICE TYPE
.DB PPIDE_ACC_MAS | (PPIDE0A8BIT & PPIDE_ACC_8BIT) ; UNIT ACCESS FLAGS
@ -230,13 +232,27 @@ PPIDE_DEV0M: ; DEVICE 0, MASTER
.DB PPIDE0BASE+3 ; PPI
.DW PPIDE_DEV0S ; PARTNER
;
DEVECHO "PPIDE: IO="
DEVECHO "PPIDE: MODE="
#IF (PPIDE0MODE == PPIDEMODE_NONE)
DEVECHO "NONE"
#ENDIF
#IF (PPIDE0MODE == PPIDEMODE_STD)
DEVECHO "STD"
#ENDIF
#IF (PPIDE0MODE == PPIDEMODE_S100A)
DEVECHO "S100A"
#ENDIF
#IF (PPIDE0MODE == PPIDEMODE_S100B)
DEVECHO "S100B"
#ENDIF
DEVECHO ", IO="
DEVECHO PPIDE0BASE
DEVECHO ", MASTER"
DEVECHO "\n"
;
PPIDE_DEV0S: ; DEVICE 0, SLAVE
.DB $FE ; DRIVER DEVICE NUMBER (FILLED DYNAMICALLY)
.DB PPIDE0MODE ; DRIVER DEVICE MODE
.DB 0 ; DEVICE STATUS
.DB 0 ; DEVICE TYPE
.DB (PPIDE0B8BIT & PPIDE_ACC_8BIT) ; UNIT ACCESS FLAGS
@ -248,7 +264,20 @@ PPIDE_DEV0S: ; DEVICE 0, SLAVE
.DB PPIDE0BASE+3 ; PPI
.DW PPIDE_DEV0M ; PARTNER
;
DEVECHO "PPIDE: IO="
DEVECHO "PPIDE: MODE="
#IF (PPIDE0MODE == PPIDEMODE_NONE)
DEVECHO "NONE"
#ENDIF
#IF (PPIDE0MODE == PPIDEMODE_STD)
DEVECHO "STD"
#ENDIF
#IF (PPIDE0MODE == PPIDEMODE_S100A)
DEVECHO "S100A"
#ENDIF
#IF (PPIDE0MODE == PPIDEMODE_S100B)
DEVECHO "S100B"
#ENDIF
DEVECHO ", IO="
DEVECHO PPIDE0BASE
DEVECHO ", SLAVE"
DEVECHO "\n"
@ -259,6 +288,7 @@ PPIDE_DEV0S: ; DEVICE 0, SLAVE
;
PPIDE_DEV1M: ; DEVICE 1, MASTER
.DB $FE ; DRIVER DEVICE NUMBER (FILLED DYNAMICALLY)
.DB PPIDE1MODE ; DRIVER DEVICE MODE
.DB 0 ; DEVICE STATUS
.DB 0 ; DEVICE TYPE
.DB PPIDE_ACC_MAS | (PPIDE1A8BIT & PPIDE_ACC_8BIT) ; UNIT ACCESS FLAGS
@ -270,13 +300,27 @@ PPIDE_DEV1M: ; DEVICE 1, MASTER
.DB PPIDE1BASE+3 ; PPI
.DW PPIDE_DEV1S ; PARTNER
;
DEVECHO "PPIDE: IO="
DEVECHO "PPIDE: MODE="
#IF (PPIDE1MODE == PPIDEMODE_NONE)
DEVECHO "NONE"
#ENDIF
#IF (PPIDE1MODE == PPIDEMODE_STD)
DEVECHO "STD"
#ENDIF
#IF (PPIDE1MODE == PPIDEMODE_S100A)
DEVECHO "S100A"
#ENDIF
#IF (PPIDE1MODE == PPIDEMODE_S100B)
DEVECHO "S100B"
#ENDIF
DEVECHO ", IO="
DEVECHO PPIDE1BASE
DEVECHO ", MASTER"
DEVECHO "\n"
;
PPIDE_DEV1S: ; DEVICE 1, SLAVE
.DB $FE ; DRIVER DEVICE NUMBER (FILLED DYNAMICALLY)
.DB PPIDE1MODE ; DRIVER DEVICE MODE
.DB 0 ; DEVICE STATUS
.DB 0 ; DEVICE TYPE
.DB (PPIDE1B8BIT & PPIDE_ACC_8BIT) ; UNIT ACCESS FLAGS
@ -288,7 +332,20 @@ PPIDE_DEV1S: ; DEVICE 1, SLAVE
.DB PPIDE1BASE+3 ; PPI
.DW PPIDE_DEV1M ; PARTNER
;
DEVECHO "PPIDE: IO="
DEVECHO "PPIDE: MODE="
#IF (PPIDE1MODE == PPIDEMODE_NONE)
DEVECHO "NONE"
#ENDIF
#IF (PPIDE1MODE == PPIDEMODE_STD)
DEVECHO "STD"
#ENDIF
#IF (PPIDE1MODE == PPIDEMODE_S100A)
DEVECHO "S100A"
#ENDIF
#IF (PPIDE1MODE == PPIDEMODE_S100B)
DEVECHO "S100B"
#ENDIF
DEVECHO ", IO="
DEVECHO PPIDE1BASE
DEVECHO ", SLAVE"
DEVECHO "\n"
@ -299,6 +356,7 @@ PPIDE_DEV1S: ; DEVICE 1, SLAVE
;
PPIDE_DEV2M: ; DEVICE 2, MASTER
.DB $FE ; DRIVER DEVICE NUMBER (FILLED DYNAMICALLY)
.DB PPIDE2MODE ; DRIVER DEVICE MODE
.DB 0 ; DEVICE STATUS
.DB 0 ; DEVICE TYPE
.DB PPIDE_ACC_MAS | (PPIDE2A8BIT & PPIDE_ACC_8BIT) ; UNIT ACCESS FLAGS
@ -310,13 +368,27 @@ PPIDE_DEV2M: ; DEVICE 2, MASTER
.DB PPIDE2BASE+3 ; PPI
.DW PPIDE_DEV2S ; PARTNER
;
DEVECHO "PPIDE: IO="
DEVECHO "PPIDE: MODE="
#IF (PPIDE2MODE == PPIDEMODE_NONE)
DEVECHO "NONE"
#ENDIF
#IF (PPIDE2MODE == PPIDEMODE_STD)
DEVECHO "STD"
#ENDIF
#IF (PPIDE2MODE == PPIDEMODE_S100A)
DEVECHO "S100A"
#ENDIF
#IF (PPIDE2MODE == PPIDEMODE_S100B)
DEVECHO "S100B"
#ENDIF
DEVECHO ", IO="
DEVECHO PPIDE2BASE
DEVECHO ", MASTER"
DEVECHO "\n"
;
PPIDE_DEV2S: ; DEVICE 2, SLAVE
.DB $FE ; DRIVER DEVICE NUMBER (FILLED DYNAMICALLY)
.DB PPIDE2MODE ; DRIVER DEVICE MODE
.DB 0 ; DEVICE STATUS
.DB 0 ; DEVICE TYPE
.DB (PPIDE2B8BIT & PPIDE_ACC_8BIT) ; UNIT ACCESS FLAGS
@ -328,7 +400,20 @@ PPIDE_DEV2S: ; DEVICE 2, SLAVE
.DB PPIDE2BASE+3 ; PPI
.DW PPIDE_DEV2M ; PARTNER
;
DEVECHO "PPIDE: IO="
DEVECHO "PPIDE: MODE="
#IF (PPIDE2MODE == PPIDEMODE_NONE)
DEVECHO "NONE"
#ENDIF
#IF (PPIDE2MODE == PPIDEMODE_STD)
DEVECHO "STD"
#ENDIF
#IF (PPIDE2MODE == PPIDEMODE_S100A)
DEVECHO "S100A"
#ENDIF
#IF (PPIDE2MODE == PPIDEMODE_S100B)
DEVECHO "S100B"
#ENDIF
DEVECHO ", IO="
DEVECHO PPIDE2BASE
DEVECHO ", SLAVE"
DEVECHO "\n"
@ -1482,6 +1567,20 @@ PPIDE_SELUNIT:
CALL PPIDE_PRTPREFIX
PRTS(" SELUNIT$")
#ENDIF
LD A,(IY+PPIDE_MODE)
CP PPIDEMODE_S100A
JR Z,PPIDE_SELS100
CP PPIDEMODE_S100B
JR Z,PPIDE_SELS100
JR PPIDE_SELUNIT0
;
PPIDE_SELS100:
LD C,(IY+PPIDE_PPI)
INC C
SUB PPIDEMODE_S100A
OUT (C),A
;
PPIDE_SELUNIT0:
BIT 0,(IY+PPIDE_ACC) ; MASTER?
JR Z,PPIDE_SELUNIT1 ; HANDLE SLAVE
LD A,PPIDE_DRVMASTER ; MASTER

21
Source/HBIOS/std.asm
View File

@ -221,13 +221,20 @@ IDEMODE_GIDE .EQU 5 ; GENESIS MODULES STD BUS IDE CONTROLLER
; PPIDE MODE SELECTIONS
;
PPIDEMODE_NONE .EQU 0
PPIDEMODE_SBC .EQU 1 ; STANDARD SBC PARALLEL PORT
PPIDEMODE_DIO3 .EQU 2 ; DISKIO V3 PARALLEL PORT
PPIDEMODE_MFP .EQU 3 ; MULTIFUNCTION / PIC
PPIDEMODE_N8 .EQU 4 ; MULTIFUNCTION / PIC
PPIDEMODE_RC .EQU 5 ; RCBUS PPIDE MODULE @ $20 (ED BRINDLEY)
PPIDEMODE_DYNO .EQU 6 ; DYNO PPIDE @ $4C
PPIDEMODE_RPH .EQU 7 ; RHYOPHYRE (RPH)
PPIDEMODE_STD .EQU 1 ; STANDARD
PPIDEMODE_S100A .EQU 2 ; S100 PRIMARY INTERFACE
PPIDEMODE_S100B .EQU 3 ; S100 SECONDARY INTERFACE
;;;;
;;;; PPIDE MODE SELECTIONS
;;;;
;;;PPIDEMODE_NONE .EQU 0
;;;PPIDEMODE_SBC .EQU 1 ; STANDARD SBC PARALLEL PORT
;;;PPIDEMODE_DIO3 .EQU 2 ; DISKIO V3 PARALLEL PORT
;;;PPIDEMODE_MFP .EQU 3 ; MULTIFUNCTION / PIC
;;;PPIDEMODE_N8 .EQU 4 ; MULTIFUNCTION / PIC
;;;PPIDEMODE_RC .EQU 5 ; RCBUS PPIDE MODULE @ $20 (ED BRINDLEY)
;;;PPIDEMODE_DYNO .EQU 6 ; DYNO PPIDE @ $4C
;;;PPIDEMODE_RPH .EQU 7 ; RHYOPHYRE (RPH)
;
; SD MODE SELECTIONS
;

2
Source/ver.inc
View File

@ -2,7 +2,7 @@
#DEFINE RMN 6
#DEFINE RUP 0
#DEFINE RTP 0
#DEFINE BIOSVER "3.6.0-dev.15"
#DEFINE BIOSVER "3.6.0-dev.16"
#define rmj RMJ
#define rmn RMN
#define rup RUP

2
Source/ver.lib
View File

@ -3,5 +3,5 @@ rmn equ 6
rup equ 0
rtp equ 0
biosver macro
db "3.6.0-dev.15"
db "3.6.0-dev.16"
endm

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