Browse Source

Cleanup

- Add Z280 interrupt mode 3 to INTTEST app
- Make application boot handle restart by using HBIOS restart in place
- Resolve multiple issues with HBIOS restart in place
pull/409/head v3.5.0-dev.41
Wayne Warthen 2 years ago
parent
commit
e5232c6696
  1. 6
      Source/Apps/Test/inttest/inttest.asm
  2. 2
      Source/HBIOS/Build.cmd
  3. 37
      Source/HBIOS/ay38910.asm
  4. 233
      Source/HBIOS/hbios.asm
  5. 1
      Source/HBIOS/hbios.inc
  6. 44
      Source/HBIOS/romldr.asm
  7. 22
      Source/HBIOS/spk.asm
  8. 120
      Source/HBIOS/std.asm
  9. 2
      Source/ver.inc
  10. 2
      Source/ver.lib

6
Source/Apps/Test/inttest/inttest.asm

@ -176,6 +176,8 @@ estidx:
jr z,hkim
cp 2
jr z,hkim
cp 3
jr z,hkim
ret
;
; Setup interrupt handler
@ -545,8 +547,8 @@ stack .equ $ ; stack top
;
; Messages
;
msgban .db "INTTEST v1.2, 15-May-2019",13,10
.db "Copyright (C) 2019, Wayne Warthen, GNU GPL v3",0
msgban .db "INTTEST v1.3, 16-May-2024",13,10
.db "Copyright (C) 2024, Wayne Warthen, GNU GPL v3",0
msginfo .db "Interrupt information request...",0
msgmode .db " Active interrupt mode: ",0
msgcnt .db " Vector entries in use: ",0

2
Source/HBIOS/Build.cmd

@ -72,7 +72,7 @@ copy ..\Fonts\font*.asm . || exit /b
tasm -t%CPUType% -g3 -dROMBOOT hbios.asm hbios_rom.bin hbios_rom.lst || exit /b
tasm -t%CPUType% -g3 -dAPPBOOT hbios.asm hbios_app.bin hbios_app.lst || exit /b
tasm -t%CPUType% -g3 -dIMGBOOT hbios.asm hbios_img.bin hbios_img.lst || exit /b
::tasm -t%CPUType% -g3 -dIMGBOOT hbios.asm hbios_img.bin hbios_img.lst || exit /b
::
:: Build ROM Components

37
Source/HBIOS/ay38910.asm

@ -219,7 +219,7 @@ AY_FND: LD IY, AY_IDAT ; SETUP FUNCTION TABLE
;
CALL AY_INIT ; SET DEFAULT CHIP CONFIGURATION
;
LD E,$07 ; SET VOLUME TO 50%
LD E,$08 ; SET VOLUME TO 50%
CALL AY_SETV ; ON ALL CHANNELS
;
; LD DE,(AY_R2CHBP*256)+$55 ; BEEP ON CHANNEL B (CENTER)
@ -227,14 +227,19 @@ AY_FND: LD IY, AY_IDAT ; SETUP FUNCTION TABLE
LD DE,(AY_R3CHBP*256)+$00
CALL AY_WRTPSG ; R03 = $00 = XXXX0000
;
#IF ((SYSTIM != TM_NONE) & (AYMODE != AYMODE_DUO))
#IF (SYSTIM != TM_NONE)
LD A, TICKFREQ / 3 ; SCHEDULE IN 1/3 SECOND TO TURN OFF SOUND
LD (AY_TIMTIK), A
;
LD HL, (VEC_TICK + 1) ; GET CUR TICKS VECTOR
LD (AY_TIMHOOK), HL ; SAVE IT INTERNALLY
LD HL, AY_TIMER ; INSTALL TIMER HOOK HANDLER
LD (VEC_TICK + 1), HL
; RESET THE AY_TIMER BYPASS
LD HL,AY_TIMER1
LD (AY_TIMER + 1),HL
;
; HOOK THE TICK VECTOR
LD HL,(VEC_TICK + 1) ; GET CUR TICKS VECTOR
LD (AY_TIMHOOK + 1),HL ; SAVE IT INTERNALLY
LD HL,AY_TIMER ; INSTALL TIMER HOOK HANDLER
LD (VEC_TICK + 1),HL
;
LD A, $02 ; NOT READY & IN INTERUPT HANDLER
LD (AY_READY), A
@ -249,27 +254,27 @@ AY_FND: LD IY, AY_IDAT ; SETUP FUNCTION TABLE
XOR A ; SUCCESSFULL INIT
RET
;
#IF ((SYSTIM != TM_NONE) & (AYMODE != AYMODE_DUO))
#IF (SYSTIM != TM_NONE)
AY_TIMER:
LD A, (AY_TIMTIK)
JP AY_TIMER1 ; SELF MODIFIED TO BYPASS HANDLER
AY_TIMER1:
LD A,(AY_TIMTIK)
DEC A
LD (AY_TIMTIK), A
JR NZ, AY_TIMER1
JR NZ,AY_TIMHOOK
;
LD E,$00 ; SET VOLUME OFF
CALL AY_SETV ; ON ALL CHANNELS
LD A, $01 ; READY & NOT IN INTERUPT HANDLER
LD (AY_READY), A
;
LD DE, AY_TIMER ; MAKE AY_TIMER A NO_OP HANDLER
LD HL, AY_TIMER1
LD BC, 3
LDIR
; MAKE AY_TIMER A NO-OP HANDLER
LD HL,(AY_TIMHOOK + 1)
LD (AY_TIMER + 1),HL
;
AY_TIMER1:
AY_TIMHOOK:
JP 0 ; OVERWRITTEN WITH NEXT HANDLER
AY_TIMHOOK: .EQU $ - 2
;
AY_TIMTIK .DB 0 ; COUNT DOWN TO FINISH BOOT BEEP
#ENDIF
;

233
Source/HBIOS/hbios.asm

@ -32,15 +32,17 @@
; HBIOS APPLICATION BINARY. THE APPENDED OS IMAGES ARE COPIED TO THE AUX RAM
; BANK AND LAUNCHED AFTER HBIOS HAS INSTALLED ITSELF.
;
;;;; - IMGBOOT: BOOT FROM AN IMAGE FILE THAT HAS BEEN PLACED IN THE USER BANK
;;;;
;;;; WHEN IMGBOOT IS DEFINED, THE FILE IS ASSEMBLED SUCH THAT IT CAN BE PRELOADED
;;;; INTO THE RAM USER BANK BY AN EXTERNAL PROCESS THAT SUBSEQUENTLY LAUNCHES
;;;; THE CODE AT ADDRESS 0. THE MOST COMMON EXAMPLE OF THIS IS THE UNA FSFAT
;;;; TOOL WHICH CAN LOAD AN IMAGE FROM A DOS FAT FILESYSTEM PROVIDING A SIMPLE
;;;; WAY TO LOAD A TEST COPY OF HBIOS. AS IS THE CASE WITH APPBOOT, IT IS ASSUMED
;;;; THAT AN OS IMAGES FILE IS APPENDED TO THE END OF THE IMAGE AND IS LAUNCHED
;;;; AFTER HBIOS IS INSTALLED.
; - IMGBOOT: BOOT FROM AN IMAGE FILE THAT HAS BEEN PLACED IN THE USER BANK
;
; NOTE: THIS BOOT MODE IS DEPRECATED.
;
; WHEN IMGBOOT IS DEFINED, THE FILE IS ASSEMBLED SUCH THAT IT CAN BE PRELOADED
; INTO THE RAM USER BANK BY AN EXTERNAL PROCESS THAT SUBSEQUENTLY LAUNCHES
; THE CODE AT ADDRESS 0. THE MOST COMMON EXAMPLE OF THIS IS THE UNA FSFAT
; TOOL WHICH CAN LOAD AN IMAGE FROM A DOS FAT FILESYSTEM PROVIDING A SIMPLE
; WAY TO LOAD A TEST COPY OF HBIOS. AS IS THE CASE WITH APPBOOT, IT IS ASSUMED
; THAT AN OS IMAGES FILE IS APPENDED TO THE END OF THE IMAGE AND IS LAUNCHED
; AFTER HBIOS IS INSTALLED.
;
; INCLUDE FILE NESTING:
;
@ -102,10 +104,17 @@
;
#DEFINE HBIOS
;
; INCLUDE GENERIC STUFF
;
#INCLUDE "std.asm"
;
; MAKE SURE EXACTLY ONE OF ROMBOOT, APPBOOT, IMGBOOT IS DEFINED.
;
MODCNT .EQU 0
BOOTMODE .EQU 0
;
#IFDEF ROMBOOT
BOOTMODE .SET BM_ROMBOOT
MODCNT .SET MODCNT + 1
;
#DEFINE BNKINFO
@ -114,12 +123,17 @@ MODCNT .SET MODCNT + 1
#DEFINE SYSINFO
;
#ENDIF
;
#IFDEF APPBOOT
BOOTMODE .SET BM_APPBOOT
MODCNT .SET MODCNT + 1
#ENDIF
#IFDEF IMGBOOT
;
#IFDEF IMGBOOT ; *** DEPRECATED ***
BOOTMODE .SET BM_IMGBOOT
MODCNT .SET MODCNT + 1
#ENDIF
;
#IF (MODCNT != 1)
.ECHO "*** ERROR: PLEASE DEFINE ONE AND ONLY ONE OF ROMBOOT, APPBOOT, IMGBOOT!!!\n"
!!! ; FORCE AN ASSEMBLY ERROR
@ -141,10 +155,6 @@ MODCNT .SET MODCNT + 1
#DEFINE MEMECHO \;
#ENDIF
;
; INCLUDE GENERIC STUFF
;
#INCLUDE "std.asm"
;
SUPCTS .EQU FALSE ; SUPPRESS CTS DURING HBIOS BOOT
;
; HELPER MACROS
@ -195,7 +205,8 @@ SUPCTS .EQU FALSE ; SUPPRESS CTS DURING HBIOS BOOT
#ENDIF
#IF (LEDMODE == LEDMODE_NABU)
#DEFINE DIAG(N) PUSH AF
#DEFCONT \ LD A,+((N << 3) & %00011000)
;#DEFCONT \ LD A,+((N << 3) & %00011000)
#DEFCONT \ LD A,+((N << 3) & %00111000)
#DEFCONT \ OUT (LEDPORT),A
#DEFCONT \ POP AF
#ENDIF
@ -427,6 +438,7 @@ CB_CRTDEV .DB $FF ; PRIMARY CRT UNIT, $FF UNTIL AFTER HBIOS INIT
CB_CONDEV .DB $FF ; CONSOLE UNIT, $FF UNTIL AFTER HBIOS INIT
;
CB_DIAGLVL .DB DIAGLVL ; ROMWBW HBIOS DIAGNOSTIC LEVEL
CB_BOOTMODE .DB BOOTMODE ; HBIOS BOOTMODE
;
; MEMORY MANAGEMENT VARIABLES START AT $20
;
@ -1037,26 +1049,26 @@ HBX_INTSTK .EQU $
;
#ENDIF
;
; HBIOS INTERRUPT SLOT ASSIGNMENTS
;
; # Z80 Z180
; --- -------------- --------------
; 0 CTC0A INT1 -+
; 1 CTC0B INT2 |
; 2 CTC0C TIM0 |
; 3 CTC0D TIM1 |
; 4 UART0 DMA0 +- Z180 INTERNAL
; 5 UART1 DMA1 |
; 6 CSIO |
; 7 SIO0 SER0 |
; 8 SIO1 SER1 -+
; 9 PIO0A PIO0A
; 10 PIO0B PIO0B
; 11 PIO1A PIO1A
; 12 PIO1B PIO1B
; 13 SIO0
; 14 SIO1
; 15
; HBIOS INTERRUPT MODE 2 SLOT ASSIGNMENTS (SEE STD.ASM)
;
; # Z80/Z280 Z180 MBC DUO NABU
; --- -------------- -------------- -------------- -------------- --------------
; 0 CTC0A INT1 -+ -+ -+ HCCARCV -+
; 1 CTC0B INT2 | | | HCCASND |
; 2 CTC0C TIM0 | | IM2 | IM2 NABUKB | IM2
; 3 CTC0D TIM1 | | INT | INT VDP | INT
; 4 UART0 DMA0 | Z180 UART0 | VEC UART0 | VEC OPTCRD0 | VEC
; 5 UART1 DMA1 | CPU UART1 | GEN UART1 | GEN OPTCRD1 | GEN
; 6 CSIO | | | OPTCRD2 |
; 7 SIO0 SER0 | -+ -+ OPTCRD3 -+
; 8 SIO1 SER1 -+ SIO0 SIO0
; 9 PIO0A PIO0A SIO1 SIO1
; 10 PIO0B PIO0B PIO0A PIO0A
; 11 PIO1A PIO1A PIO0B PIO0B
; 12 PIO1B PIO1B CTC0A CTC0A
; 13 SIO0 CTC0B CTC0B
; 14 SIO1 CTC0C CTC0C
; 15 CTC0D CTC0D
;
; IVT MUST START AT PAGE BOUNDARY
ALIGN($100)
@ -1341,13 +1353,26 @@ HB_START:
CALL HB_APPBOOT ; PREPARE APP BOOT
RET NZ ; RETURN ON ERROR
;
HB_APPBOOT_Z:
;
#ENDIF
;
HB_RESTART:
;
DI ; NO INTERRUPTS
IM 1 ; INTERRUPT MODE 1
;
#IFDEF APPBOOT
;
; IF THIS IS AN APPLICATION BOOT, WE CAPTURE THE CURRENT BANK ID
; AND UPDATE THE PROXY IMAGE. LATER, WHEN THE PROXY IMAGE IS COPIED
; TO IT'S RUNNING LOCATION AT TOP OF RAM, THE CORRECT HB_CURBNK
; VALUE WILL BE INSTALLED. NOTE: THE ADDRESSES IN THE PROXY
; IMAGE ARE FOR IT'S RUNNING LOCATION, SO WE NEED TO USE *MATH*
; TO DERIVE THE LOCATION OF HB_CURBNK IN THE IMAGE.
LD A,(HB_CURBNK)
LD (HB_CURBNK - HBX_LOC + HBX_IMG),A
;
#ENDIF
;
#IF ((PLATFORM == PLT_DUO) & TRUE)
; THIS ARBITRARY DELAY SEEMS TO HELP DUODYNE CPU V1.0 SYSTEMS
; STARTUP CLEANLY. DOUDYNE CPU V1.1 INTRODUCES A RESET
@ -1460,11 +1485,11 @@ BOOTWAIT:
; LEFT ALONE.
;
; INITIALIZE ALL OF THE USER PAGE DESCRIPTORS WITH BLOCK MOVE
#IFDEF APPBOOT
#IFDEF APPBOOT
LD A,$08 ; FIRST USER PDR IN HI MEM
#ELSE
#ELSE
LD A,$00 ; FIRST USER PDR
#ENDIF
#ENDIF
OUT (Z280_MMUPDRPTR),A ; SET THE PDR POINTER
LD HL,Z280_BOOTPDRTBL ; START OF PDR VALUES TABLE
LD C,Z280_MMUBLKMOV ; PDR BLOCK MOVE PORT
@ -1472,11 +1497,11 @@ BOOTWAIT:
OTIRW ; OTIRW PROGS PDRS SEQUENTIALLY
;
; INITIALIZE ALL OF THE SYSTEM PAGE DESCRIPTORS WITH BLOCK MOVE
#IFDEF APPBOOT
#IFDEF APPBOOT
LD A,$18 ; FIRST SYSTEM PDR IN HI MEM
#ELSE
#ELSE
LD A,$10 ; FIRST SYSTEM PDR
#ENDIF
#ENDIF
OUT (Z280_MMUPDRPTR),A ; SET THE PDR POINTER
LD HL,Z280_BOOTPDRTBL ; START OF PDR VALUES TABLE
LD C,Z280_MMUBLKMOV ; PDR BLOCK MOVE PORT
@ -1493,7 +1518,7 @@ BOOTWAIT:
ALIGN(2) ; WORD ALIGN THE PDR TABLE
;
Z280_BOOTPDRTBL:
#IFNDEF APPBOOT
#IFNDEF APPBOOT
; LOWER 32 K (BANKED)
.DW ((Z2_BANK(BID_BOOT) + 0) << 4) | $A
.DW ((Z2_BANK(BID_BOOT) + 1) << 4) | $A
@ -1503,7 +1528,7 @@ Z280_BOOTPDRTBL:
.DW ((Z2_BANK(BID_BOOT) + 5) << 4) | $A
.DW ((Z2_BANK(BID_BOOT) + 6) << 4) | $A
.DW ((Z2_BANK(BID_BOOT) + 7) << 4) | $A
#ENDIF
#ENDIF
; UPPER 32 K (COMMON)
.DW ((Z2_BANK(BID_COM) + 0) << 4) | $A
.DW ((Z2_BANK(BID_COM) + 1) << 4) | $A
@ -2012,6 +2037,41 @@ CB_IDS: LD (HL),A ; POPULATE CB_BIDCOM
LD (RTC_DISPACT),A ; RTC DEVICE
LD (DSKY_DISPACT),A ; DSKY DEVICE
;
; CLEAR INTERRUPT VECTOR TABLES
;
; THIS IS REALLY ONLY REQUIRED ON A RESTART, BUT IT DOESN'T HURT TO
; DO IT ALL THE TIME.
;
LD HL,HB_IVT + 1 ; FIRST VECTOR (IM2)
LD B,16 ; CLEAR 16 VECTORS
CALL HB_CLRIVT ; DO IT
LD HL,HB_IM1INT + 1 ; FIRST VECTOR (IM1)
LD B,8 ; CLEAR 8 VECTORS
CALL HB_CLRIVT ; DO IT
XOR A ; ZERO ACCUM
LD (HB_IM1CNT),A ; ... TO CLEAR IM1 VECTOR CNT
LD HL,HB_IM1INT ; POINTER TO START OF IM1 IVT
LD (HB_IM1PTR),HL ; ... TO CLEAR IM1 PTR
LD HL,HB_TICK
LD (VEC_TICK + 1),HL
LD HL,HB_SECOND
LD (VEC_SECOND + 1),HL
JR HB_CLRIVT_Z ; DONE, JUMP OVER SUBROUTINE
;
HB_CLRIVT:
LD (HL),HB_BADINT & $FF
INC HL
LD (HL),HB_BADINT >> 8
INC HL
INC HL
INC HL
DJNZ HB_CLRIVT
RET
;
HB_CLRIVT_Z:
;
; INITIALIZE HEAP STORAGE
;
; INITIALIZE POINTERS
@ -2707,34 +2767,6 @@ NXTMIO: LD A,(HL)
NOT_REC_M2:
;
FPLEDS(DIAG_08)
#IF (PLATFORM == PLT_NABU) & TRUE
;
; GET CURRENT VALUE OF PSG ENABLE REGISTER
LD A,7
OUT (NABU_RSEL),A
NOP
IN A,(NABU_RDAT)
LD B,A
;
; GET CURRENT VALUE OF PSG ENABLE REGISTER
LD A,7
OUT (NABU_RSEL),A
NOP
IN A,(NABU_RDAT)
LD C,A
;
; DUMP IT
CALL PC_ASTERISK
LD A,B
CALL PRTHEXBYTE
LD A,C
CALL PRTHEXBYTE
CALL PC_ASTERISK
;
#ENDIF
;
;--------------------------------------------------------------------------------------------------
; IO PORT SCAN
@ -4538,31 +4570,38 @@ SYS_RESWARM:
;
SYS_RESCOLD:
;
#IF (MEMMGR == MM_Z280)
#IFDEF APPBOOT
JP HB_RESTART
#ELSE
;
; MAKE ROM BOOT BANK ACTIVE IN LOW SYS MEM
;
#IF (MEMMGR == MM_Z280)
; FOR Z280, NEED TO REMAP THE LOW 32K IN SYSTEM MODE AND
; CONTINUE AT ADDRESS ZERO. WE CANNOT RETURN HERE AFTER THE
; BNKSEL IS DONE BECAUSE THE SYSTEM BANK HAS BEEN CHANGED!
; SO, WE PRESET THE STACK TO CAUSE A JUMP TO ADDRESS ZERO
; ON RETURN FROM THE BNKSEL. SLICK, RIGHT?
; SO, WE PRESET THE STACK TO CAUSE A JUMP TO THE RESTART
; ADDRESS ON RETURN FROM THE BNKSEL. SLICK, RIGHT?
DI ; KILL INTERRUPTS
LD SP,HBX_LOC ; STACK IN HIGH MEMORY
LD HL,0 ; VALUE TO RESUME
LD HL,HB_RESTART ; RESUME AT RESTART ADDRESS
PUSH HL ; ... IS PRESET ON STACK
;
; MAKE ROM BOOT BANK ACTIVE IN LOW SYS MEM
LD A,BID_BOOT ; BOOT BANK
LD A,BID_BOOT ; BANK TO LAUNCH RESTART
LD B,$10 ; FIRST SYS PDR
JP Z280_BNKSEL ; DO IT AND RESUME FROM STACK
#ELSE
#ELSE
; FOR OTHER THAN Z280, JUST DO AN INTERBANK CALL TO THE
; RESTART ADDRESS.
DI
LD SP,HBX_LOC ; STACK JUST BELOW HBIOS PROXY
LD A,BID_BOOT ; BOOT BANK
LD IX,0 ; ADDRESS ZERO
LD A,BID_BOOT ; BANK TO LAUNCH RESTART
LD IX,HB_RESTART ; RESUME AT RESTART ADDRESS
CALL HB_BNKCALL ; DOES NOT RETURN
#ENDIF
#ENDIF
;
; HOOK CALLED WHEN A USERLAND RESET IS INVOKED, TYPICALLY VIA A JUMP
; TO LOGICAL CPU ADDRESS $0000
; TO CPU ADDRESS $0000
;
; CREDIT TO PHILLIP STEVENS FOR SUGGESTING AND SIGNIFICANT CONTRIBUTIONS
; TO THE Z180 INVALID OPCODE TRAP ENHANCEMENT.
@ -5541,7 +5580,7 @@ SYS_INTINFO:
LD A,(HB_IM1CNT) ; RETURN IM1 CALL LIST SIZE
LD E,A
#ENDIF
#IF (INTMODE == 2)
#IF ((INTMODE == 2) | (INTMODE == 3))
LD E,HBX_IVTCNT ; RETURN INT VEC TABLE SIZE
#ENDIF
XOR A ; INDICATE SUCCESS
@ -5560,7 +5599,7 @@ SYS_INTVECADR:
INC A ; ALLOW FOR EXTRA ENTRY TO APPEND AT END
LD C,A ; SAVE IN C FOR COMPARE
#ENDIF
#IF (INTMODE == 2)
#IF ((INTMODE == 2) | (INTMODE == 3))
LD C,HBX_IVTCNT ; GET CURRENT ENTRY COUNT
#ENDIF
LD A,E ; INCOMING INDEX POSITION TO A
@ -5578,7 +5617,7 @@ SYS_INTGET1:
#IF (INTMODE == 1)
LD DE,HB_IM1INT ; DE := START OF VECTOR TABLE
#ENDIF
#IF (INTMODE == 2)
#IF ((INTMODE == 2) | (INTMODE == 3))
LD DE,HB_IVT ; DE := START OF VECTOR TABLE
#ENDIF
ADD HL,DE ; HL := ADR OF VECTOR
@ -6026,9 +6065,9 @@ HB_TIMDBG1:
; THESE CAN BE HOOKED AS DESIRED BY DRIVERS
;
VEC_TICK:
JP HB_TICK ; TICK PROCESSING VECTOR
JP HB_TICK ; TICKS PROCESSING VECTOR
VEC_SECOND:
JP HB_SECOND ; SECOND PROCESSING VECTOR
JP HB_SECOND ; SECONDS PROCESSING VECTOR
;
; TIMER HANDLERS
;
@ -8484,15 +8523,6 @@ STR_APPBOOT .DB "\r\n\r\n*** Launching RomWBW HBIOS v", BIOSVER, ", ", TIMESTAMP
.DB "\r\n\r\n ", PLATFORM_NAME, "$"
;
HB_APPBOOT2:
; IF THIS IS AN APPLICATION BOOT, WE CAPTURE THE CURRENT BANK ID
; AND UPDATE THE PROXY IMAGE. LATER, WHEN THE PROXY IMAGE IS COPIED
; TO IT'S RUNNING LOCATION AT TOP OF RAM, THE CORRECT HB_CURBNK
; VALUE WILL BE INSTALLED. NOTE: THE ADDRESSES IN THE PROXY
; IMAGE ARE FOR IT'S RUNNING LOCATION. WE NEED TO USE *MATH*
; TO DERIVE THE LOCATION OF HB_CURBNK IN THE IMAGE.
LD A,(HB_CURBNK)
LD (HB_CURBNK - HBX_LOC + HBX_IMG),A
;
; FOR AN APPLICATION BOOT, WE ALSO COPY THE CONCATENATED OS
; IMAGES TO THE AUX BANK WHERE WE WILL JUMP TO ROMLDR LATER.
; THE AUX BANK WILL BE DESTROYED IF CP/M 3 IS LOADED. WE DON'T
@ -8512,12 +8542,15 @@ HB_APPBOOT2:
; WE NEED TO SWITCH FROM USER MODE TO SYSTEM MODE, BUT CONTINUE
; RUNNING IN THE CURRENT BANK. THIS IS A LITTLE MESSY.
;
; FIRST, OVERLAY PROXY CODE WITH NEW CODE SO WE CAN USE THE
; FIRST, OVERLAY PROXY CODE WITH FRESH CODE SO WE CAN USE THE
; PROXY ROUTINES SAFELY.
LD A,(HB_CURBNK) ; GET CURBNK
LD DE,HBX_LOC ; RUNNING LOCATION
LD HL,HBX_IMG ; LOCATION IN IMAGE
LD BC,HBX_SIZ ; SIZE
LDIR ; INSTALL IT
LD (HB_CURBNK),A ; RESTORE CURBNK
;
; NEXT, COPY A BIT OF CODE TO DO THE SYSTEM TRANSITION TO
; UPPER MEM. WE CAN BORROW THE PROXY BOUNCE BUFFER FOR THIS.
@ -8541,7 +8574,7 @@ Z280_GOSYS:
LD A,(HB_CURBNK) ; CURRENT BANK
LD B,$10 ; FIRST SYSTEM PDR
CALL Z280_BNKSEL ; DO THE SWITCH
JP HB_APPBOOT_Z ; AND RESUME BOOT
JP HB_RESTART ; AND RESUME BOOT
;
Z280_GOSYS_LEN .EQU $ - Z280_GOSYS
;

1
Source/HBIOS/hbios.inc

@ -432,6 +432,7 @@ HCB_SERDEV .EQU $10 ; PRIMARY SERIAL DEVICE/UNIT (BYTE)
HCB_CRTDEV .EQU $11 ; CRT DISPLAY DEVICE/UNIT (BYTE)
HCB_CONDEV .EQU $12 ; ACTIVE CONSOLE DEVICE/UNIT (BYTE)
HCB_DIAGLVL .EQU $13 ; HBIOS DIAGNOSTIC LEVEL (BYTE)
HCB_BOOTMODE .EQU $14 ; HBIOS BOOTMODE (BYTE)
;
HCB_HEAP .EQU $20 ; DWORD ADDRESS OF START OF HEAP
HCB_HEAPTOP .EQU $22 ; DWORD ADDRESS OF TOP OF HEAP

44
Source/HBIOS/romldr.asm

@ -47,7 +47,6 @@ cmdbuf .equ $80 ; cmd buf is in second half of page zero
cmdmax .equ 60 ; max cmd len (arbitrary), must be < bufsiz
bufsiz .equ $80 ; size of cmd buf
;
;;int_im1 .equ $FF00 ; IM1 vector target for RomWBW HBIOS proxy
hbx_int .equ $FF60 ; IM1 vector target for RomWBW HBIOS proxy
;
bid_cur .equ -1 ; used below to indicate current bank
@ -132,16 +131,22 @@ start:
di
#endif
;
; Switch to user RAM bank
; Switch to user RAM bank and establish boot mode
;
#if (BIOS == BIOS_WBW)
; Get the boot mode
ld b,BF_SYSPEEK ; HBIOS func: PEEK
ld d,BID_BIOS ; BIOS bank
ld hl,HCB_LOC + HCB_BOOTMODE ; boot mode byte
rst 08
ld a,e ; put in A
ld (bootmode),a ; save it
;
ld b,BF_SYSSETBNK ; HBIOS func: set bank
ld c,BID_USR ; select user bank
rst 08 ; do it
ld a,c ; previous bank to A
ld (bid_ldr),a ; save previous bank for later
;;;bit 7,a ; starting from ROM?
cp BID_IMG0 ; ROM startup?
#endif
;
#if (BIOS == BIOS_UNA)
@ -149,16 +154,22 @@ start:
ld de,BID_USR ; select user bank
rst 08 ; do it
ld (bid_ldr),de ; save previous bank for later
;
ld a,BM_ROMBOOT ; assume ROM boot
bit 7,d ; starting from ROM?
jr z,start1 ; if so, skip ahead
ld a,BM_APPBOOT ; else this is APP boot
start1:
ld (bootmode),a ; save it
#endif
;
; For app mode startup, use alternate table
ld hl,ra_tbl ; assume ROM startup
jr z,start1 ; if so, ra_tbl OK, skip ahead
ld hl,ra_tbl_app ; not ROM boot, get app tbl loc
ld a,$ff ; signal for app boot
ld (appboot),a ; ... goes in flag
start1:
ld hl,ra_tbl ; assume ROM application table
ld a,(bootmode) ; get boot mode
cp BM_ROMBOOT ; ROM boot?
jr z,start2 ; if so, ra_tbl OK, skip ahead
ld hl,ra_tbl_app ; switch to RAM application table
start2:
ld (ra_tbl_loc),hl ; and overlay pointer
;
; Copy original page zero into user page zero
@ -178,9 +189,9 @@ start1:
;
#if (BIOS == BIOS_WBW)
; Get the current console unit
ld b,BF_SYSPEEK ; HBIOS func: POKE
ld b,BF_SYSPEEK ; HBIOS func: PEEK
ld d,BID_BIOS ; BIOS bank
ld hl,HCB_LOC + HCB_CONDEV ; Con unit num in HCB
ld hl,HCB_LOC + HCB_CONDEV ; console unit num in HCB
rst 08 ; do it
ld a,e ; put in A
ld (curcon),a ; save it
@ -208,10 +219,10 @@ start1:
call nl2 ; formatting
ld hl,str_banner ; display boot banner
call pstr ; do it
ld a,(appboot) ; get app boot flag
or a ; set flags
ld a,(bootmode) ; get app boot flag
cp BM_APPBOOT ; APP boot?
ld hl,str_appboot ; signal application boot mode
call nz,pstr ; print if app boot active
call z,pstr ; print if APP boot
call clrbuf ; zero fill the cmd buffer
;
#if ((BIOS == BIOS_WBW) & FPSW_ENABLE)
@ -2488,7 +2499,7 @@ dma .dw 0 ; address for load
sps .dw 0 ; sectors per slice
mediaid .db 0 ; media id
;
appboot .db 0 ; app boot if != 0
bootmode .db 0 ; ROM, APP, or IMG boot
ra_tbl_loc .dw 0 ; points to active ra_tbl
bootunit .db 0 ; boot disk unit
bootslice .db 0 ; boot disk slice
@ -2503,7 +2514,6 @@ ciocnt .db 1 ; count of char units
savcon .db 0 ; con save for conpoll
conpend .db $ff ; pending con unit (first <space> pressed)
#endif
;
;=======================================================================
; Pad remainder of ROM Loader

22
Source/HBIOS/spk.asm

@ -40,6 +40,7 @@ SP_RTCIOMSK .EQU 00000100B
SP_PENDING_PERIOD .DW SP_NOTE_C8 ; PENDING PERIOD (16 BITS)
SP_PENDING_VOLUME .DB $FF ; PENDING VOL (8 BITS)
SP_PENDING_DURATION .DW 0 ; PENDING DURATION (16 BITS)
SP_TBLRDY .DB 0 ; IF != 0, NOTE TABLE IS READY
;
DEVECHO "SPK: IO="
DEVECHO RTCIO
@ -59,8 +60,18 @@ SP_INIT:
PRTS("SPK: IO=0x$")
LD A,RTCIO
CALL PRTHEXBYTE
;
; RESET DEFAULTS IN CASE OF AN IN-PLACE HBIOS RESTART
LD HL,SP_NOTE_C8
LD (SP_PENDING_PERIOD),HL
LD A,$FF
LD (SP_PENDING_VOLUME),A
XOR A
LD (SP_PENDING_DURATION),A
;
CALL SP_SETTBL ; SETUP TONE TABLE
CALL SP_PLAY ; PLAY DEFAULT NOTE
;
XOR A
RET
;
@ -164,6 +175,13 @@ SP_QUERY_DEV:
;======================================================================
;
SP_SETTBL:
; IN CASE OF HBIOS RESTART IN PLACE, WE CHECK TO SEE IF THE
; NOT TABLE IS ALREADY INITIALIZED (READY). IF SO, WE DON'T
; WANT TO DO IT AGAIN.
LD A,(SP_TBLRDY)
OR A
RET NZ
;
LD BC,(CB_CPUMHZ) ; GET MHZ CPU SPEED (IN C).
;
SP_SETTBL3:
@ -202,6 +220,10 @@ SP_SETBL4:
INC HL ; TO NEXT
;
DJNZ SP_SETTBL2 ; NEXT NOTE
;
OR $FF ; SIGNAL TABLE READY
LD (SP_TBLRDY),A ; SAVE IT
;
RET
;
;======================================================================

120
Source/HBIOS/std.asm

@ -70,6 +70,12 @@ BIOS_NONE .EQU 0 ; NO BIOS TYPE DEFINED
BIOS_WBW .EQU 1 ; ROMWBW HBIOS
BIOS_UNA .EQU 2 ; UNA UBIOS
;
; HBIOS BOOT MODES
;
BM_ROMBOOT .EQU 1 ; ROM BOOT
BM_APPBOOT .EQU 2 ; APPLICATION BOOT
BM_IMGBOOT .EQU 3 ; IMAGE BOOT (DEPRECATED)
;
; MEMORY MANAGERS
;
MM_NONE .EQU 0
@ -978,75 +984,38 @@ MON_SERIAL .EQU MON_LOC + (1 * 3) ; MONITOR ENTRY (SERIAL PORT)
;
; INTERRUPT MODE 2 SLOT ASSIGNMENTS
;
#IF (((CPUFAM == CPU_Z180) | (CPUFAM == CPU_Z280)) & (INTMODE > 0))
; NOTE THAT Z180 PROCESSES ALL INTERNAL INTERRUPTS JUST LIKE
; IM2 EVEN WHEN CHIP IS IN IM1 MODE. SO WE INCLUDE THE IM2
; INTERRUPT ASSIGNMENTS FOR IM1 BELOW.
; Z180-BASED SYSTEMS
INT_INT1 .EQU 0 ; Z180 INT 1
INT_INT2 .EQU 1 ; Z180 INT 2
INT_TIM0 .EQU 2 ; Z180 TIMER 0
INT_TIM1 .EQU 3 ; Z180 TIMER 1
INT_DMA0 .EQU 4 ; Z180 DMA 0
INT_DMA1 .EQU 5 ; Z180 DMA 1
INT_CSIO .EQU 6 ; Z180 CSIO
INT_SER0 .EQU 7 ; Z180 SERIAL 0
INT_SER1 .EQU 8 ; Z180 SERIAL 0
INT_PIO0A .EQU 9 ; ZILOG PIO 0, CHANNEL A
INT_PIO0B .EQU 10 ; ZILOG PIO 0, CHANNEL B
INT_PIO1A .EQU 11 ; ZILOG PIO 1, CHANNEL A
INT_PIO1B .EQU 12 ; ZILOG PIO 1, CHANNEL B
INT_SIO0 .EQU 13 ; ZILOG SIO 0, CHANNEL A & B
INT_SIO1 .EQU 14 ; ZILOG SIO 1, CHANNEL A & B
#ENDIF
#IF ((CPUFAM == CPU_Z80) & (INTMODE == 2))
#IF (PLATFORM == PLT_MBC)
;
; MBC Z80 INTERRUPTS
;
;INT_CTC0A .EQU 0 ; ZILOG CTC 0, CHANNEL A
;INT_CTC0B .EQU 1 ; ZILOG CTC 0, CHANNEL B
;INT_CTC0C .EQU 2 ; ZILOG CTC 0, CHANNEL C
;INT_CTC0D .EQU 3 ; ZILOG CTC 0, CHANNEL D
INT_UART0 .EQU 4 ; UART 0
INT_UART1 .EQU 5 ; UART 1
INT_INT6 .EQU 6 ;
INT_INT7 .EQU 7 ;
INT_SIO0 .EQU 8 ; ZILOG SIO 0, CHANNEL A & B
INT_SIO1 .EQU 9 ; ZILOG SIO 1, CHANNEL A & B
INT_PIO0A .EQU 10 ; ZILOG PIO 0, CHANNEL A
INT_PIO0B .EQU 11 ; ZILOG PIO 0, CHANNEL B
INT_CTC0A .EQU 12 ; ZILOG CTC 0, CHANNEL A
INT_CTC0B .EQU 13 ; ZILOG CTC 0, CHANNEL B
INT_CTC0C .EQU 14 ; ZILOG CTC 0, CHANNEL C
INT_CTC0D .EQU 15 ; ZILOG CTC 0, CHANNEL D
;INT_PIO0A .EQU 9 ; ZILOG PIO 0, CHANNEL A
;INT_PIO0B .EQU 10 ; ZILOG PIO 0, CHANNEL B
;INT_PIO1A .EQU 11 ; ZILOG PIO 1, CHANNEL A
;INT_PIO1B .EQU 12 ; ZILOG PIO 1, CHANNEL B
#ENDIF
#IF (PLATFORM == PLT_DUO)
;
; DUO Z80 IM2 INTERRUPTS
;
INT_UART0 .EQU 7 ; UART 0
INT_UART1 .EQU 6 ; UART 1 ?????
INT_CTC0A .EQU 0 ; ZILOG CTC 0, CHANNEL A
INT_CTC0B .EQU 1 ; ZILOG CTC 0, CHANNEL B
INT_CTC0C .EQU 2 ; ZILOG CTC 0, CHANNEL C
INT_CTC0D .EQU 3 ; ZILOG CTC 0, CHANNEL D
INT_SIO0 .EQU 6 ; ZILOG SIO 0, CHANNEL A & B
INT_SIO1 .EQU 8 ; ZILOG SIO 1, CHANNEL A & B
INT_PIO0A .EQU 9 ; ZILOG PIO 0, CHANNEL A
INT_PIO0B .EQU 10 ; ZILOG PIO 0, CHANNEL B
INT_PIO1A .EQU 11 ; ZILOG PIO 1, CHANNEL A
INT_PIO1B .EQU 12 ; ZILOG PIO 1, CHANNEL B
INT_UART0 .EQU 4 ; UART 0
INT_UART1 .EQU 5 ; UART 1
INT_SIO0 .EQU 8 ; ZILOG SIO 0, CHANNEL A & B
INT_SIO1 .EQU 9 ; ZILOG SIO 1, CHANNEL A & B
INT_PIO0A .EQU 10 ; ZILOG PIO 0, CHANNEL A
INT_PIO0B .EQU 11 ; ZILOG PIO 0, CHANNEL B
INT_CTC0A .EQU 12 ; ZILOG CTC 0, CHANNEL A
INT_CTC0B .EQU 13 ; ZILOG CTC 0, CHANNEL B
INT_CTC0C .EQU 14 ; ZILOG CTC 0, CHANNEL C
INT_CTC0D .EQU 15 ; ZILOG CTC 0, CHANNEL D
#ENDIF
#IF (PLATFORM == PLT_NABU)
@ -1061,13 +1030,12 @@ INT_OPTCRD0 .EQU 4 ; OPTION CARD 0
INT_OPTCRD1 .EQU 5 ; OPTION CARD 1
INT_OPTCRD2 .EQU 6 ; OPTION CARD 2
INT_OPTCRD3 .EQU 7 ; OPTION CARD 3
#ENDIF
#IF ((PLATFORM != PLT_MBC) & (PLATFORM != PLT_DUO) & (PLATFORM != PLT_NABU))
;
; GENERIC Z80 M2 INTERRUPTS
;
INT_CTC0A .EQU 0 ; ZILOG CTC 0, CHANNEL A
INT_CTC0B .EQU 1 ; ZILOG CTC 0, CHANNEL B
INT_CTC0C .EQU 2 ; ZILOG CTC 0, CHANNEL C
@ -1080,11 +1048,57 @@ INT_PIO0A .EQU 9 ; ZILOG PIO 0, CHANNEL A
INT_PIO0B .EQU 10 ; ZILOG PIO 0, CHANNEL B
INT_PIO1A .EQU 11 ; ZILOG PIO 1, CHANNEL A
INT_PIO1B .EQU 12 ; ZILOG PIO 1, CHANNEL B
#ENDIF
#ENDIF
#IF ((CPUFAM == CPU_Z180) & (INTMODE > 0))
;
; Z180-BASED SYSTEMS
;
; NOTE THAT Z180 PROCESSES ALL INTERNAL INTERRUPTS JUST LIKE
; IM2 EVEN WHEN CHIP IS IN IM1 MODE. SO WE INCLUDE THE IM2
; INTERRUPT ASSIGNMENTS FOR IM1 BELOW.
;
INT_INT1 .EQU 0 ; Z180 INT 1
INT_INT2 .EQU 1 ; Z180 INT 2
INT_TIM0 .EQU 2 ; Z180 TIMER 0
INT_TIM1 .EQU 3 ; Z180 TIMER 1
INT_DMA0 .EQU 4 ; Z180 DMA 0
INT_DMA1 .EQU 5 ; Z180 DMA 1
INT_CSIO .EQU 6 ; Z180 CSIO
INT_SER0 .EQU 7 ; Z180 SERIAL 0
INT_SER1 .EQU 8 ; Z180 SERIAL 0
INT_PIO0A .EQU 9 ; ZILOG PIO 0, CHANNEL A
INT_PIO0B .EQU 10 ; ZILOG PIO 0, CHANNEL B
INT_PIO1A .EQU 11 ; ZILOG PIO 1, CHANNEL A
INT_PIO1B .EQU 12 ; ZILOG PIO 1, CHANNEL B
INT_SIO0 .EQU 13 ; ZILOG SIO 0, CHANNEL A & B
INT_SIO1 .EQU 14 ; ZILOG SIO 1, CHANNEL A & B
#ENDIF
#IF ((CPUFAM == CPU_Z280) & (INTMODE >= 2))
;
; Z280-BASED SYSTEMS
;
; FOR Z280 MODE 3, THESE APPLY TO THE INTA SIGNAL
; THESE ARE IDENTICAL TO THE GENERIC Z80 ASSIGNMENTS
;
INT_CTC0A .EQU 0 ; ZILOG CTC 0, CHANNEL A
INT_CTC0B .EQU 1 ; ZILOG CTC 0, CHANNEL B
INT_CTC0C .EQU 2 ; ZILOG CTC 0, CHANNEL C
INT_CTC0D .EQU 3 ; ZILOG CTC 0, CHANNEL D
INT_UART0 .EQU 4 ; UART 0
INT_UART1 .EQU 5 ; UART 1
INT_SIO0 .EQU 7 ; ZILOG SIO 0, CHANNEL A & B
INT_SIO1 .EQU 8 ; ZILOG SIO 1, CHANNEL A & B
INT_PIO0A .EQU 9 ; ZILOG PIO 0, CHANNEL A
INT_PIO0B .EQU 10 ; ZILOG PIO 0, CHANNEL B
INT_PIO1A .EQU 11 ; ZILOG PIO 1, CHANNEL A
INT_PIO1B .EQU 12 ; ZILOG PIO 1, CHANNEL B
#ENDIF
#DEFINE IVT(INTX) HB_IVT+(INTX * 4)+1
#DEFINE VEC(INTX) INTX*2

2
Source/ver.inc

@ -2,7 +2,7 @@
#DEFINE RMN 5
#DEFINE RUP 0
#DEFINE RTP 0
#DEFINE BIOSVER "3.5.0-dev.40"
#DEFINE BIOSVER "3.5.0-dev.41"
#define rmj RMJ
#define rmn RMN
#define rup RUP

2
Source/ver.lib

@ -3,5 +3,5 @@ rmn equ 5
rup equ 0
rtp equ 0
biosver macro
db "3.5.0-dev.40"
db "3.5.0-dev.41"
endm

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