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@ -281,7 +281,7 @@ RCVSCL DW 6600 ; RECV loop timeout scalar |
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UNIT DB 0 ; BIOS serial device unit number |
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UNIT DB 0 ; BIOS serial device unit number |
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BIOSBID DB 00H ; BIOS bank id |
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BIOSBID DB 00H ; BIOS bank id |
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; |
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; |
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TAG DB "RomWBW, 23-May-2020$" |
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TAG DB "RomWBW, 30-May-2020$" |
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; |
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; |
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HB_LBL DB ", HBIOS FastPath$" |
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HB_LBL DB ", HBIOS FastPath$" |
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UB_LBL DB ", UNA UBIOS$" |
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UB_LBL DB ", UNA UBIOS$" |
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@ -776,8 +776,8 @@ UF_JPTBL: |
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; USB-FIFO initialization |
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; USB-FIFO initialization |
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; |
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; |
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UF_INIT: |
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UF_INIT: |
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LD HL,12000 ; Receive loop timeout scalar |
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LD (RCVSCL),HL ; ... for UART RCVRDY timing |
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LD DE,12000 ; Receive loop timeout scalar |
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LD (RCVSCL),DE ; ... for UART RCVRDY timing |
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; |
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; |
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LD A,L ; Get base I/O port address (data port) |
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LD A,L ; Get base I/O port address (data port) |
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LD (UF_SCDP),A ; Set data port in SENDR |
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LD (UF_SCDP),A ; Set data port in SENDR |
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