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@ -119,31 +119,40 @@ SD_NOPULLUP .EQU TRUE ; ASSUME NO PULLUP |
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SD_DEVCNT .EQU 1 ; NUMBER OF PHYSICAL UNITS (SOCKETS) |
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SD_OPRREG .EQU RTCIO ; USES RTC LATCHES FOR OPERATION |
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SD_OPRDEF .EQU %00000001 ; QUIESCENT STATE |
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SD_OPRMSK .EQU %10000111 ; MASK FOR BITS WE OWN IN RTC LATCH PORT |
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SD_INPREG .EQU RTCIO ; INPUT REGISTER IS RTC |
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SD_CS0 .EQU %00000100 ; RTC:2 IS SELECT |
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SD_CLK .EQU %00000010 ; RTC:1 IS CLOCK |
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SD_DI .EQU %00000001 ; RTC:0 IS DATA IN (CARD <- CPU) |
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SD_DO .EQU %10000000 ; RTC:7 IS DATA OUT (CARD -> CPU) |
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; |
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RTCDEF .SET SD_OPRDEF ; SET DEFAULT IN HBIOS MAINLINE |
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#ENDIF |
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; |
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#IF (SDMODE == SDMODE_N8) ; UNMODIFIED N8-2511 |
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SD_DEVCNT .EQU 1 ; NUMBER OF PHYSICAL UNITS (SOCKETS) |
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SD_OPRREG .EQU RTCIO ; USES RTC LATCHES FOR OPERATION |
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SD_OPRDEF .EQU %00000001 ; QUIESCENT STATE |
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SD_OPRMSK .EQU %01000111 ; MASK FOR BITS WE OWN IN RTC LATCH PORT |
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SD_INPREG .EQU RTCIO ; INPUT REGISTER IS RTC |
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SD_CS0 .EQU %00000100 ; RTC:2 IS SELECT |
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SD_CLK .EQU %00000010 ; RTC:1 IS CLOCK |
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SD_DI .EQU %00000001 ; RTC:0 IS DATA IN (CARD <- CPU) |
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SD_DO .EQU %01000000 ; RTC:6 IS DATA OUT (CARD -> CPU) |
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; |
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RTCDEF .SET SD_OPRDEF ; SET DEFAULT IN HBIOS MAINLINE |
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#ENDIF |
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; |
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#IF (SDMODE == SDMODE_CSIO) ; N8-2312 |
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SD_DEVCNT .EQU 1 ; NUMBER OF PHYSICAL UNITS (SOCKETS) |
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SD_OPRREG .EQU RTCIO ; USES RTC LATCHES FOR OPERATION |
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SD_OPRDEF .EQU %00000000 ; QUIESCENT STATE |
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SD_OPRMSK .EQU %00000100 ; MASK FOR BITS WE OWN IN RTC LATCH PORT |
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SD_CS0 .EQU %00000100 ; RTC:2 IS SELECT |
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SD_CNTR .EQU Z180_CNTR |
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SD_TRDR .EQU Z180_TRDR |
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; |
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RTCDEF .SET SD_OPRDEF ; SET DEFAULT IN HBIOS MAINLINE |
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#ENDIF |
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; |
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#IF (SDMODE == SDMODE_PPI) ; PPISD |
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@ -165,6 +174,7 @@ SD_DO .EQU %10000000 ; PPIB:7 IS DATA OUT (CARD -> CPU) |
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SD_DEVCNT .EQU 1 ; NUMBER OF PHYSICAL UNITS (SOCKETS) |
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SD_OPRREG .EQU SIO_MCR ; UART MCR PORT (OUTPUT: CS, CLK, DIN) |
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SD_OPRDEF .EQU %00001100 ; QUIESCENT STATE |
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SD_OPRMSK .EQU %00101101 ; MASK FOR BITS WE OWN IN RTC LATCH PORT |
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SD_INPREG .EQU SIO_MSR ; INPUT REGISTER IS MSR |
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SD_CS0 .EQU %00001000 ; UART MCR:3 IS SELECT |
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SD_CLK .EQU %00000100 ; UART MCR:2 IS CLOCK |
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@ -198,10 +208,13 @@ SD_TRDR .EQU Z180_TRDR |
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SD_DEVCNT .EQU SDCNT ; NUMBER OF PHYSICAL UNITS (SOCKETS) |
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SD_OPRREG .EQU RTCIO ; USES RTC LATCHES FOR OPERATION |
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SD_OPRDEF .EQU %00001100 ; QUIESCENT STATE (/CS1 & /CS2 DEASSERTED) |
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SD_OPRMSK .EQU %00001100 ; MASK FOR BITS WE OWN IN RTC LATCH PORT |
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SD_CS0 .EQU %00000100 ; RTC:2 IS SELECT FOR PRIMARY SPI CARD |
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SD_CS1 .EQU %00001000 ; RTC:3 IS SELECT FOR SECONDARY SPI CARD |
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SD_CNTR .EQU Z180_CNTR |
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SD_TRDR .EQU Z180_TRDR |
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; |
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RTCDEF .SET SD_OPRDEF ; SET DEFAULT IN HBIOS MAINLINE |
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#ENDIF |
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; |
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#IF (SDMODE == SDMODE_MT) ; MT shift register for RC2014 (ref SDMODE_CSIO) |
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@ -318,6 +331,7 @@ SD_INIT: |
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CALL PRTHEXBYTE |
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; |
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LD A,(RTCVAL) ; GET RTC PORT SHADOW VALUE |
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AND ~SD_OPRMSK ; CLEAR OUR BITS |
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OR SD_OPRDEF ; SET OUR BIT DEFAULTS |
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LD (RTCVAL),A ; SAVE IT |
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#ENDIF |
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@ -329,6 +343,7 @@ SD_INIT: |
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CALL PRTHEXBYTE |
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; |
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LD A,(RTCVAL) ; GET RTC PORT SHADOW VALUE |
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AND ~SD_OPRMSK ; CLEAR OUR BITS |
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OR SD_OPRDEF ; SET OUR BIT DEFAULTS |
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LD (RTCVAL),A ; SAVE IT |
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#ENDIF |
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@ -349,6 +364,7 @@ SD_INIT: |
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CALL PRTHEXBYTE |
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; |
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LD A,(RTCVAL) ; GET RTC PORT SHADOW VALUE |
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AND ~SD_OPRMSK ; CLEAR OUR BITS |
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OR SD_OPRDEF ; SET OUR BIT DEFAULTS |
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LD (RTCVAL),A ; SAVE IT |
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#ENDIF |
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@ -412,6 +428,7 @@ SD_INIT: |
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CALL PRTHEXBYTE |
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; |
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LD A,(RTCVAL) ; GET RTC PORT SHADOW VALUE |
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AND ~SD_OPRMSK ; CLEAR OUR BITS |
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OR SD_OPRDEF ; SET OUR BIT DEFAULTS |
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LD (RTCVAL),A ; SAVE IT |
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#ENDIF |
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@ -844,6 +861,12 @@ SD_INITCARD1: |
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CALL SD_PUT ; SEND 8 CLOCKS |
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POP BC ; RESTORE LOOP CONTROL |
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DJNZ SD_INITCARD1 ; LOOP AS NEEDED |
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; |
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; MAKE SURE WE FINISH SENDING |
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#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC)) |
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CALL SD_WAITTX ; WAIT FOR TE TO CLEAR |
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CALL DLY4 ; WAIT A BIT MORE FOR FINAL BIT |
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#ENDIF |
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; |
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; PUT CARD IN IDLE STATE |
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CALL SD_GOIDLE ; GO TO IDLE |
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@ -1538,8 +1561,8 @@ SD_SETUP: |
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; |
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#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC)) |
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; CSIO SETUP FOR Z180 CSIO |
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; LD A,2 ; 18MHz/20 <= 400kHz |
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LD A,6 ; ??? |
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; LD A,2 ; DIV 80, 225KHZ @ 18MHZ CLK |
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LD A,6 ; DIV 1280, 14KHZ @ 18MHZ CLK |
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OUT0 (SD_CNTR),A |
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#ENDIF |
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; |
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@ -1556,7 +1579,6 @@ SD_SETUP: |
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#ENDIF |
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; |
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#IF (SDMODE == SDMODE_UART) |
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SD_OPRMSK .EQU (SD_CS0 | SD_CLK | SD_DI) |
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IN A,(SD_OPRREG) ; OPRREG == SIO_MCR |
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AND ~SD_OPRMSK ; MASK OFF SD CONTROL BITS |
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OR SD_OPRDEF ; SET DEFAULT BITS |
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@ -1605,9 +1627,10 @@ SD_CHKWP: |
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; SELECT CARD |
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; |
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SD_SELECT: |
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#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC)) |
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CALL SD_WAITTX |
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#ENDIF |
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; ; FINISH SENDING BEFORE ASSERTING CS! |
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;#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC)) |
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; CALL SD_WAITTX |
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;#ENDIF |
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; |
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LD A,(IY+SD_DEV) ; GET CURRENT DEVICE |
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OR A ; SET FLAGS |
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@ -1641,6 +1664,22 @@ SD_SELECT2: |
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; DESELECT CARD |
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; |
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SD_DESELECT: |
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#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC)) |
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; DON'T REMOVE CS UNTIL WE ARE DONE SENDING! |
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CALL SD_WAITTX ; WAIT FOR TE TO CLEAR |
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; |
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; ACCORDING TO Z180 DOCS, IT MAY TAKE UP TO 1 BIT TIME TO |
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; FINISH SENDING AFTER TE IS CLEARED. THE DELAY BELOW WILL |
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; DO THIS FOR THE SLOWEST POSSIBLE SEND RATE WHICH IS |
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; CLK / 1320, SO DELAY AT LEAST 1320 T-STATES |
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;CALL DLY64 ; DELAY FOR FINAL BIT |
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; |
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; IN PRACTICE, IT LOOKS LIKE THIS WORST CASE SCENARIO NEVER |
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; OCCURS. FOR NOW, USE A SMALL DELAY WHICH SEEMS TO BE MORE |
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; THAN ADEQUATE BASED ON LOGIC ANALYZER TRACES. |
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CALL DLY4 ; DELAY FOR FINAL BIT |
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#ENDIF |
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; |
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LD A,(SD_OPRVAL) |
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#IF (SD_DEVCNT > 1) |
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AND ~(SD_CS0 | SD_CS1) |
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Wayne Warthen
6 years ago