- Update PR template for new branching under v3.4
- Tweak Makefile.inc for slightly improved performance
- Improve UART driver messaging when bad CTS signal is detected
- Minor doc updates
- Comment updates in ansi.asm and tms.asm
- Correction to build process for ROMless systems
- Fix for ZRC (default configuration) to use all available RAM
- Split out the SD and USB specific support from the main CH37x driver to optimize code space usage.
- Ensure CH37x mode switch is handled properly when there are multiple devices active in a system.
I am encountering some CH376 chips that go haywire after a
reset command. They stop responding for a very long time.
I am seeing this only on "LC Tech" adapters and only on Z80
systems (not Z180). No idea what is going on, so I am
giving up for now and removing the reset.
- Last check-in had a couple of config file errors which are corrected here.
- Also updated Appendix A of the User Guide to reflect new CH37x port addressing.
- Updated to standardize on 0x3E/0x3F for primary CH device and 0x3C/0x3D for secondary CH device. Both devices are optional and detected automatically.
- The post-reset delay of both the IDE and PPIDE drivers has been extended. The SD-IDE adapters need more time to initialize before being ready to behave as proper IDE devices.
- Added support for the FDC section of the Duodyne Disk-IO board.
- Credit and thanks to Martin R for providing a substantial list of suggested fixes and improvements to the User Guide. I have done my best to address them -- others will require more time and will hopefully be addressed in the future.
- The 40 column mode of the TMS driver now conforms to the memory map from the TMS9918 documentation and is also now consistent with the existing TMS9918 video programs from the RC2014 forum.
When using the Z2 memory manager, if the HBIOS exceeds 16K, RTCDEFVAL will not be accessible prior to programming the Z2 memory bank registers. In this corner case the RTC latch could be mis-programmed. This commit introduces a workaround.
- ACIA driver was not properly returning ZF to indicate if it handled an interrupt.
- APPBOOT was failing on ROMless systems because it was copying the HBIOS code overtop of itself.
- Added support for Duodyne to PS2INFO application.
- Switched all build paths to consistently use OpenSpin since it appears to be compatible with all build environments supported by RomWBW.
- Added support for Duodyne Multi-IO board
- Added support for Duodyne Zilog-IO board
- Added SUPCTS equate in hbios.asm to allow selectively adding code to suppress use of CTS during HBIOS boot
- Added reference in User Guide to Bruce Hall's Assembly Language Programming document
- CP/M 3 ldrbios had not been properly updated for device type id change.
- ASSIGN command was not handling DPB's correctly due to device type id change.
FAT application had not been updated to reflect a change in the HBIOS Disk Device API call return data. This is corrected in this check-in. Related discussion in #368.
- Detect CTS at startup to ensure it is asserted. If not, disable hardware flow control to avoid stalling the console at boot. Only for UART driver because this is the only place it is currently relevant.
- The naming of ZZRCC was incorrectly ZZRC. Corrected.
- Max Scane has provided a small bug fix for CLRDIR.
- Minor build updates for new HTalk utility.
- Dean Jenkins has motivated me to implement additional protection from using a slice that does not fit within the capacity of the physical disk being used. You can still assign an unusable slice, but when you try to refer to it, you will immediately get a "no disk" error from the OS.
Driver Device Type ID's have been stored in the upper nibble. However, running out of ID's, I have changed them to occupy the entire byte.
This is a breaking change, so I have updated the minor version number to maintain integrity between components. So, v3.3 will never become a stable release and I am moving directly to v3.4.
- The build process was enhanced by Dean Jenkins to support the Raspberry Pi. Note that the Propeller firmware will not be generated by a RPi build. See Issue #358.
- Initial support for USB storage via CH375/6.