Floppy I/O was failing for slower CPUs when the timer interrupts were active. Now fixed.
Credit to Jorge Jorge Rodrigues for finding this problem and pointing me in the right direction for the fix.
Supports double-buffered disk i/o to read/write to/from any memory bank specified.
NOTE: Disk I/O will be temporarily slower than normal because all I/O is being forced thru double-buffering for testing.
Remove debug code.
Resolve issue with battery status being lost on stack.
Battery status variable moved to DSRTC driver.
Fix build failures for DSRTCENABLE=FALSE (spk.asm requires dsrtc)
DS1210 datasheet "The fourth function the DS1210 performs is a battery status warning so that potential data loss is avoided. Each time that the circuit is powered up the battery voltage is checked with a precision comparator. If the battery voltage is less than 2.0 volts, the second memory cycle is inhibited. Battery status can, therefore, be determined by performing a read cycle after power-up to any location in memory, verifying that memory location content. A subsequent write cycle can then be executed to the same memory location altering the data. If the next read cycle fails to verify the written data, then the batteries are less than 2.0V and data is in danger of being corrupted"
This also works:
LD HL,HBX_IMG-2
LD DE,HBX_LOC-2
LD BC,HBX_SIZ+2
LDIR
Regards Phil
- Added official support for Steve Cousin's RC2014 Z180 + Native Memory modules (SC111 & SC119). Thanks to Steve for his assistance with this.
- Improved interrupt framework to remove need to extra stubs for each IM2 interrupt handler.
Add periodic timer interrupt support for CTC platforms Easy Z80 and Zeta 2. Includes watchdog servicing for Easy Z80. Default interrupt mode for Easy Z80 and Zeta 2 is now IM2.
