- Update PR template for new branching under v3.4
- Tweak Makefile.inc for slightly improved performance
- Improve UART driver messaging when bad CTS signal is detected
- Minor doc updates
- Comment updates in ansi.asm and tms.asm
- Correction to build process for ROMless systems
- Fix for ZRC (default configuration) to use all available RAM
- Split out the SD and USB specific support from the main CH37x driver to optimize code space usage.
- Ensure CH37x mode switch is handled properly when there are multiple devices active in a system.
I am encountering some CH376 chips that go haywire after a
reset command. They stop responding for a very long time.
I am seeing this only on "LC Tech" adapters and only on Z80
systems (not Z180). No idea what is going on, so I am
giving up for now and removing the reset.
- Last check-in had a couple of config file errors which are corrected here.
- Also updated Appendix A of the User Guide to reflect new CH37x port addressing.
- Updated to standardize on 0x3E/0x3F for primary CH device and 0x3C/0x3D for secondary CH device. Both devices are optional and detected automatically.
- The post-reset delay of both the IDE and PPIDE drivers has been extended. The SD-IDE adapters need more time to initialize before being ready to behave as proper IDE devices.
- Added support for the FDC section of the Duodyne Disk-IO board.
- Credit and thanks to Martin R for providing a substantial list of suggested fixes and improvements to the User Guide. I have done my best to address them -- others will require more time and will hopefully be addressed in the future.
- The 40 column mode of the TMS driver now conforms to the memory map from the TMS9918 documentation and is also now consistent with the existing TMS9918 video programs from the RC2014 forum.
Experimental command line script (Windows only) to add a ROM image to user area 0 of hd1k_combo.img. Intended to make it easier to get a ROM image to a system for subsequent FLASHing.
When using the Z2 memory manager, if the HBIOS exceeds 16K, RTCDEFVAL will not be accessible prior to programming the Z2 memory bank registers. In this corner case the RTC latch could be mis-programmed. This commit introduces a workaround.
