Finalize v2.8.4

Small bug fixes

Doc/ChangeLog.txt

@@ -1,3 +1,17 @@
+Version 2.8.4
+-------------
+- WBW: FD.COM renamed to FDU.COM and integrated with build
+- WBW: FDU.COM enhanced to select FDC hardare at startup to
+       eliminate multiple versions.
+
+Version 2.8.3
+-------------
+- WBW: Added MODE command
+- WBW: Removed obsolete 1200.COM, 9600.COM, and 38400.COM
+- WBW: New XM.COM that automatically adapts to primary port of platform
+- WBW: XM.COM now handles 38400 baud at 4MHz
+- WBW: Removed obsolete XM versions: XM5.COM, XM-A0.COM, XM-A1.COM
+
 Version 2.8.2
 -------------
 - WBW: Adjusted VGA3 register setup per John's recommendations

Doc/FDU.txt

@@ -0,0 +1,473 @@
+================================================================
+Floppy Disk Utility (FDU) v5.0 for RetroBrew Computers 
+Disk IO / Zeta / Dual-IDE / N8
+================================================================
+
+Updated September 2, 2017
+by Wayne Warthen (wwarthen@gmail.com)
+
+Application to test the hardware functionality of the Floppy 
+Disk Controller (FDC) on the ECB DISK I/O, DISK I/O V3, ZETA 
+SBC, Dual IDE w/ Floppy, or N8 board.
+ 
+The intent is to provide a testbed that allows direct testing 
+of all possible media types and modes of access.  The 
+application supports read, write, and format by sector, track, 
+and disk as well as a random read/write test.
+
+The application supports access modes of polling, interrupt, 
+INT/WAIT, and DRQ/WAIT.  At present, it supports 3.5" media at 
+DD (720KB) and HD (1.44MB) capacities.  It also now supports 
+5.25" media (720KB and 1.2MB) and 8" media (1.11MB) as well.   
+Additional media will be added when I have time and access to 
+required hardware.  Not all modes are supported on all 
+platforms and some modes are experimental in all cases.
+
+In many ways this application is merely reinventing the wheel 
+and performs functionality similar to existing applications, 
+but I have not seen any other applications for RetroBrew 
+Computers hardware that provide this range of functionality.
+
+While the application is now almost entirely new code, I would 
+like to acknowledge that much was derived from the previous 
+work of Andrew Lynch and Dan Werner.  I also want to credit 
+Sergio Gimenez with testing the 5.25" drive support and Jim 
+Harre with testing the 8" drive support.  Support for Zeta 2 
+comes from Segey Kiselev.  Thanks!
+
+General Usage
+-------------
+
+In general, usage is self explanatory.  At invocation, you 
+must select the floppy disk controller (FDC) that you are 
+using.  Subsequently, the main menu allows you to set the 
+unit, media, and mode to test.  These settings MUST match your 
+situation.  Read, write, format, and verify functions are 
+provided.  A sub-menu will allow you to choose sector, track, 
+disk, or random tests.
+
+The verify function requires a little explanation.  It will 
+take the contents of the current in-memory disk buffer, save 
+it, and compare it to the selected sectors.  So, you must 
+ensure that the sectors to be verified already have been 
+written with the same pattern as the buffer contains.  I 
+typically init the buffer to a pattern, write the pattern to 
+the entire disk, then verify the entire disk.
+
+Another submenu is provided for FDC commands.  This sub-menu 
+allows you to send low-level commands directly to FDC.  You 
+*must* know what you are doing to use this sub-menu.  For 
+example, in order to read a sector using this sub-menu, you 
+will need to perform specify, seek, sense int, and read 
+commands specifying correct values (nothing is value checked 
+in this menu).
+
+Required Hardware/BIOS
+----------------------
+
+Of course, the starting point is to have a supported hardware 
+configuration. The following Z80 / Z180 based CPU boards are 
+supported:
+
+ - SBC V1/2
+ - Zeta
+ - Zeta 2
+ - N8
+ - Mark IV
+
+You must be using either a RomWBW or UBA based OS version.
+
+You must have one of the following floppy disk controllers:
+
+ - Disk IO ECB Board FDC
+ - Disk IO 3 ECB Board FDC
+ - Dual-IDE ECB Board FDC
+ - Zeta SBC onboard FDC
+ - Zeta 2 SBC onboard FDC
+ - N8 SBC onboard FDC
+ 
+Finally, you will need a floppy drive connected via an 
+appropriate cable:
+
+Disk IO - no twist in cable, drive unit 0/1 must be selected by jumper on drive
+DISK IO 3, Zeta, Zeta 2 - cable with twist, unit 0 after twist, unit 1 before twist
+DIDE, N8 - cable with twist, unit 0 before twist, unit 1 after twist
+
+Note that FDU does not utilize your systems ROM or OS to 
+access the floppy system.  FDU interacts directly with 
+hardware.  Upon exit, you may need to reset your OS to get the 
+floppy system back into a state that is expected.
+
+The Disk I/O should be jumpered as follows:
+
+J1: depends on use of interrupt modes (see interrupt modes below)
+J2: pins 1-2, & 3-4 jumpered
+J3: hardware dependent timing for DMA mode (see DMA modes below)
+J4: pins 2-3 jumpered
+J5: off
+J6: pins 2-3 jumpered
+J7: pins 2-3 jumpered
+J8: off
+J9: off
+J10: off
+J11: off
+J12: off
+
+Note that J1 can be left on even when not using interrupt 
+modes.  As long as the BIOS is OK with it, that is fine.  Note 
+also that J3 is only relevant for DMA modes, but also can be 
+left in place when using other modes.
+
+The Disk I/O 3 board should be jumpered at the default settings:
+
+JP2: 3-4
+JP3: 1-2 for int mode support, otherwise no jumper
+JP4: 1-2, 3-4
+JP5: 1-2
+JP6: 1-2
+JP7: 1-2, 3-4
+
+Zeta & Zeta 2 do not have any relevant jumper settings.  The 
+hardwired I/O ranges are assumed in the code.
+
+The Dual-IDE board should be jumpered as follows:
+
+K3 (DT/R or /RD): /RD
+P5 (bd ID): 1-2, 3-4 (for $20-$3F port range)
+
+There are no specific N8 jumper settings, but the default
+I/O range starting at $80 is assumed in the published code.
+
+
+Modes of Operation
+------------------
+
+You can select the following test modes.  Please refer to the 
+chart that follows to determine which modes should work with 
+combinations of Z80 CPU speed and media format.
+
+WARNING: In general, only the polling mode is considered fully 
+reliable.  The other modes are basically experimental and 
+should only be used if you know exactly what you are doing.
+
+Polling: Traditional polled input/output.  Works well and very 
+reliable with robust timeouts and good error recovery.  Also, 
+the slowest performance which precludes it from being used 
+with 1.44MB floppy on a 4MHz Z80. This is definitely the mode 
+you want to get working before any others. It does not require 
+J1 (interrupt enable) on DISK I/O and does not care about the 
+setting of J3.
+
+Interrupt: Relies on FDC interrupts to determine when a byte 
+is ready to be read/written.  It does *not* implement a 
+timeout during disk operations.  For example, if there is no 
+disk in the drive, this mode will just hang until a disk is 
+inserted. This mode *requires* that the host has interrupts 
+active using interrupt mode 1 (IM1) and interrupts attached to 
+the FDC controller.  The BIOS must be configured to handle 
+these interrupts safely.
+
+Fast Interrupt: Same as above, but sacrifices additional 
+reliability for faster operation.  This mode will allow a 
+1.44MB floppy to work with a 4MHz Z80 CPU.  However, if any 
+errors occur (even a transient read error which is not 
+unusual), this mode will hang.  The same FDC interrupt 
+requirements as above are required.
+
+INT/WAIT: Same as Fast Interrupt, but uses CPU wait instead of 
+actual interrupt.  This mode is exclusive to the original Disk 
+IO board.  It is subject to all the same issues as Fast 
+Interrupt, but does not need J1 shorted.  J3 is irrelevant.
+
+DRQ/WAIT: Uses pseudo DMA to handle input/output.  Does not 
+require that interrupts (J1) be enabled on the DISK I/O.  
+However, it is subject to all of the same reliability issues 
+as "Fast Interrupt".  This mode is exclusive to the original 
+Disk IO board.  At present, the mode is *not* implemented!
+
+The chart below attempts to describe the combinations that 
+work for me.  By far, the most reliable mode is Polling, but 
+it requires 8MHz CPU for HD disks.
+
+DRQ/WAIT --------------------------------+
+INT/WAIT -----------------------------+  |
+Fast Interrupt --------------------+  |  |
+Interrupt ----------------------+  |  |  |
+Polling ---------------------+  |  |  |  |
+                             |  |  |  |  |
+CPU Speed --------------+    |  |  |  |  |
+                        |    |  |  |  |  |
+                        |    |  |  |  |  |
+
+3.5" DD (720K) ------  4MHz  Y  Y  Y  Y  X
+                       8MHz+ Y  Y  Y  Y  X
+
+3.5" HD (1.44M) -----  4MHz  N  N  Y  Y  X
+                       8MHz+ Y  Y  Y  Y  X
+					   
+5.25" DD (360K) -----  4MHz  Y  Y  Y  Y  X
+                       8MHz+ Y  Y  Y  Y  X
+
+5.25" HD (1.2M) -----  4MHz  N  N  Y  Y  X
+                       8MHz+ Y  Y  Y  Y  X
+					   
+8" DD (1.11M) -------  4MHz  N  N  Y  Y  X
+                       8MHz+ Y  Y  Y  Y  X
+					   
+Y = Yes, works
+N = No, does not work
+X = Experimental, probably won't work
+
+Tracing
+-------
+
+Command/result activity to/from the FDC will be written out if 
+the trace setting is changed from '00' to '01' in setup. 
+Additionally, if a command failure is detected on any command, 
+that specific comand and results are written regardless of the 
+trace setting.
+
+The format of the line written is:
+<OPERATION>: <COMMAND BYTES> --> <RESULT BYTES> [<RESULT>]
+
+For example, this is the output of a normal read operation:
+READ: 46 01 00 00 01 02 09 1B FF --> 01 00 00 00 00 02 02 [OK]
+
+Please refer to the i8272 data sheet for information on the 
+command and result bytes.
+
+Note that the sense interrupt command can return a non-OK 
+result.  This is completely normal in some cases.  It is 
+necessary to "poll" the drive for seek status using sense 
+interrupt.  If there is nothing to report, then the result 
+will be INVALID COMMAND.  Additionally, during a recalibrate 
+operation, it may be necessary to issue the command twice 
+because the command will only step the drive 77 times looking 
+for track 0, but the head may be up to 80 tracks away.  In 
+this case, the first recalibrate fails, but the second should 
+succeed.  Here is what this would look like if trace is turned 
+on:
+
+RECALIBRATE: 07 01 --> <EMPTY> [OK]
+SENSE INTERRUPT: 08 --> 80 [INVALID COMMAND]
+	...
+	...
+	...
+SENSE INTERRUPT: 08 --> 80 [INVALID COMMAND]
+SENSE INTERRUPT: 08 --> 71 00 [ABNORMAL TERMINATION]
+RECALIBRATE: 07 01 --> <EMPTY> [OK]
+SENSE INTERRUPT: 08 --> 21 00 [OK]
+
+Another example is when the FDC has just been reset.  In this 
+case, you will see up to 4 disk change errors.  Again these 
+are not a real problem and to be expected.
+
+When tracing is turned off, the application tries to be 
+intelligent about error reporting.  The specific errors from 
+sense interrupt documented above will be suppressed because 
+they are not a real problem.  All other errors will be 
+displayed.
+
+Error Handling
+--------------
+
+There is no automated error retry logic.  This is very 
+intentional since the point is to expose the controller and 
+drive activity.  Any error detected will result in a prompt to 
+abort, retry, or continue.  Note that some number of errors is 
+considered normal for this technology.  An occasional error 
+would not necessarily be considered a problem.
+
+CPU Speed
+---------
+
+Starting with v5.0, the application adjusts it's timing loops 
+to the actual system CPU speed by querying the BIOS for the 
+current CPU speed.
+
+Interleave
+----------
+
+The format command now allows the specification of a sector 
+interleave.  It is almost always the case that the optimal 
+interleave will be 2 (meaning 2:1).
+
+360K Media
+----------
+
+The 360K media definition should work well for true 360K 
+drives.  However, it will generally not work with 1.2M 
+drives.  This is because these drives spin at 360RPM instead 
+of the 300RPM speed of true 360K drives.  Additionally, 1.2M 
+drives are 80 tracks and 360K drives are 40 tracks and, so 
+far, there is no mechanism in FD to "double step" as a way to 
+use 40 track media in 80 track drives.
+
+With this said, it is possible to configure some 1.2M 5.25" 
+drives to automatically spin down to 300RPM based on a density 
+select signal (DENSEL).  This signal is asserted by FD for 
+360K media, so IF you have configured your drive to react to 
+this signal correctly, you will be able to use the 360K media 
+defintion. Most 1.2M 5.25" drives are NOT configured this way 
+by default. TEAC drives are generally easy to modify and have 
+been tested by the author and do work in this manner.  Note 
+that this does not address the issue of double stepping above; 
+you will just be using the first 40 of 80 tracks.
+
+Support
+-------
+
+I am happy to answer questions as fast and well as I am able. 
+Best contact is wwarthen@gmail.com or post something on the 
+RetroBrew Computers Forum 
+https://www.retrobrewcomputers.org/forum/.
+
+Changes
+-------
+
+WW 8/12/2011
+
+Removed call to pulse TC in the FDC initialization after 
+determining that it periodically caused the FDC to write bad 
+sectors.  I am mystified by this, but definitely found it to 
+be true.  Will revisit at some point -- probably a timing 
+issue between puslsing TC and whatever happens next.
+
+Non-DMA mode was being set incorrectly for FAST-DMA mode. It 
+was set for non-DMA even though we were doing DMA.  It is 
+interesting that it worked fine anyway.  Fixed it anyway.
+
+DIO_SETMEDIA was not clearing DCD_DSKRDY as it should.  Fixed.
+
+WW 8/26/2011: v1.1
+
+Added support for Zeta.  Note that INT/WAIT and DRQ/WAIT are 
+not available on Zeta.  Note that Zeta provides the ability to 
+perform a reset of the FDC independent of a full CPU reset.  
+This is VERY useful and the FDC is reset anytime a drive reset 
+is required.
+
+Added INT/WAIT support.
+
+WW 8/28/2011: V1.2
+
+All changes in this version are Zeta specific.  Fixed FDC 
+reset logic and motor status display for Zeta (code from 
+Sergey).
+
+Modified Zeta disk change display to include it in the command 
+output line.  This makes more sense because a command must be 
+issued to select the desired drive first.  You can use the 
+SENSE INT command id you want to check the disk change value 
+at any time.  It will also be displayed with any other command 
+output display.
+
+WW 9/1/2011: V1.3
+
+Added CPUFREQ configuration setting to tune delays based on 
+cpu speed.  The build app is set for 8MHz which also seems to 
+work well for 4MHz CPU's.  Faster CPU speeds will probably 
+require tuning this setting.
+
+WW 9/5/2011: V1.4
+
+Changed the polling execution routines to utilize CPUFREQ 
+variable to optimize timeout counter.  Most importantly, this 
+should allow the use of faster CPUs (like 20MHz).
+
+WW 9/19/2011: V1.5
+
+Zeta changes only.  Added a call to FDC RESET after any 
+command failure.  This solves an issue where the drive remains 
+selected if a command error occurs.  Also added FDC RESET to 
+FDC CONTROL menu.
+
+WW 10/7/2011: V2.0
+
+Added support for DIDE.  Only supports polling IO and it does 
+not appear any other modes are possible given the hardware 
+constraints.
+
+WW 10/13/2011: V2.1
+
+Modified to support N8.  N8 is essentially identical to Dual 
+IDE. The only real change is the IO addresses.  In theory, I 
+should be able to support true DMA on N8 and will work on that.
+
+WW 10/20/2011: v2.2
+
+I had some problems with the results being read were sometimes 
+missing a byte.  Fixed this by taking a more strict approach 
+to watching the MSR for the exact bits that are expected.
+
+WW 10/22/2011: V2.3
+
+After spending a few days trying to track down an intermittent 
+data corruption issue with my Dual IDE board, I added a verify 
+function.  This helped me isolate the problem very nicely 
+(turned out to be interference from the bus monitor).
+
+WW 11/25/2011: V2.4
+
+Preliminary support for DISKIO V3.  Basically just assumed 
+that it operates just like the Zeta.  Needs to be verified 
+with real hardware as soon as I can.
+
+WW 1/9/2012: V2.5
+
+Modified program termination to use CP/M reset call so that a 
+warm start is done and all drives are logged out.  This is 
+important because media may have been formatted during the 
+program execution.
+
+WW 2/6/2012: v2.6
+
+Added support for 5.25" drives as tested by Sergio.
+
+WW 4/5/2012: v2.7
+
+Added support for 8" drives as tested by Jim Harre.
+
+WW 4/6/2012: v2.7a
+
+Fixed issue with media selection menu to remove duplicate 
+entries.
+
+WW 4/8/2012: v2.7b
+
+Corrected the handling of the density select signal.
+
+WW 5/22/2012: v2.8
+
+Added new media definitions (5.25", 320K).
+
+WW 6/1/2012: v2.9
+
+Added interleave capability on format.
+
+WW 6/5/2012: v3.0
+
+Documentation cleanup.
+
+WW 7/1/2012: v3.1
+
+Modified head load time (HLT) for 8" media based on YD-180 
+spec.  Now set to 50ms.
+
+WW 6/17/2013: v3.2
+
+Cleaned up SRT, HLT, and HUT values.
+
+SK 2/10/2015: v3.3
+
+Added Zeta SBC v2 support (Sergey Kiselev)
+
+WW 3/25/2015: v4.0
+
+Renamed from FDTST --> FD
+
+WW 9/2/2017: v5.0
+
+Renamed from FD to FDU.
+Added runtime selection of FDC hardware.
+Added runtime timing adjustment.

ReadMe.txt

@@ -7,7 +7,7 @@
 ***********************************************************************
 
 Wayne Warthen (wwarthen@gmail.com)
-Version 2.8.2, 2017-07-18
+Version 2.8.4, 2017-09-02
 https://www.retrobrewcomputers.org/
 
 RomWBW is a ROM-based implementation of CP/M-80 2.2 and Z-System for 

Source/Apps/Build.cmd

@@ -16,14 +16,17 @@ call :asm Assign || goto :eof
 call :asm Format || goto :eof
 call :asm Talk || goto :eof
 call :asm OSLdr || goto :eof
+call :asm Mode || goto :eof
 
 zx Z80ASM -SYSGEN/F
 
+setlocal & cd XM && call Build || exit /b 1 & endlocal
+setlocal & cd FDU && call Build || exit /b 1 & endlocal
+
 goto :eof
 
 :asm
 echo.
 echo Building %1...
-rem tasm -t80 -b -g3 -fFF %1.asm %1.com %1.lst
 tasm -t80 -g3 -fFF %1.asm %1.com %1.lst
 goto :eof

Source/Apps/Clean.cmd

@@ -3,4 +3,7 @@ setlocal
 
 if exist *.bin del *.bin
 if exist *.com del *.com
-if exist *.lst del *.lst
+if exist *.lst del *.lst
+
+setlocal & cd XM && call Clean || exit /b 1 & endlocal
+setlocal & cd FDU && call Clean || exit /b 1 & endlocal

Source/Apps/Decode.asm

@@ -0,0 +1,79 @@
+;
+;==================================================================================================
+; DECODE 32-BIT VALUES FROM A 5-BIT SHIFT-ENCODED VALUE
+;==================================================================================================
+;
+;   Copyright (C) 2014 John R. Coffman.  All rights reserved.
+;   Provided for hobbyist use on the Z180 SBC Mark IV board.
+;
+; This program is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program.  If not, see <http://www.gnu.org/licenses/>.
+;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;
+; THE FUNCTION(S) IN THIS FILE ARE BASED ON LIKE FUNCTIONS CREATED BY JOHN COFFMAN
+; IN HIS UNA BIOS PROJECT.  THEY ARE INCLUDED HERE BASED ON GPLV3 PERMISSIBLE USE.
+;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;
+; An encoded value (V) is defined as V = C * 2^X * 3^Y
+; where C is a prearranged constant, X is 0 or 1 and Y is 0-15
+; The encoded value is stored as 5 bits: YXXXX
+; At present, C=75 for baud rate encoding and C=3 for CPU OSC encoding
+;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;  DECODE
+;
+; Enter with:
+;	HL	=  word to be decoded (5-bits)    FXXXX
+;		   F=extra 3 factor, XXXX=shift factor, reg H must be zero
+;	DE	=  encode divisor OSC_DIV = 3, or BAUD_DIV = 75
+;
+; Exit with:
+;	DE:HL	=  decoded value
+;       A	=  non-zero on error
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;
+decode:
+	ld	a,h			; set to test
+	ld	c,$ff			; presume error condition
+	or	a			; test for zero
+	jr	nz,decode9		; not an encoded value
+	ld	a,l			; get low order 5 bits
+	cp	32			; test for error
+	jr	nc,decode9		; error return if not below
+	; argument hl is validated
+	ld	h,d
+	ld	l,e			; copy to hl
+	cp	16	
+	jr	c,decode2		; if < 16, no 3 factor
+	add	hl,de			; introduce factor of 3
+	add	hl,de			; **
+decode2:	
+	ld	de,0			; zero the high order
+	and	15			; mask to 4 bits
+	jr	z,decode8		; good exit
+	ld	c,b			; save b-reg
+	ld	b,a			;
+decode3:	
+	add	hl,hl			; shift left by 1, set carry
+	rl	e	
+	rl	d			; **
+	djnz	decode3	
+	ld	b,c			; restore b-reg
+decode8:	
+	ld	c,0			; signal good return
+decode9:	
+	ld	a,c			; error code test
+	or	a			; error code in reg-c and z-flag
+	ret

Source/Apps/Encode.asm

@@ -0,0 +1,75 @@
+;
+;==================================================================================================
+; ENCODE 32-BIT VALUES TO A 5-BIT SHIFT-ENCODED VALUE
+;==================================================================================================
+;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;
+; An encoded value (V) is defined as V = C * 2^X * 3^Y
+; where C is a prearranged constant, Y is 0 or 1 and X is 0-15
+; The encoded value is stored as 5 bits: YXXXX
+; At present, C=75 for baud rate encoding and C=3 for CPU OSC encoding
+;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;  ENCODE
+;
+; Enter with:
+;	DE:HL	=  dword value to be encoded
+;	C	=  divisor (0 < C < 256)
+;		   encode divisor OSC_DIV = 3, or BAUD_DIV = 75
+;
+; Exit with:
+;	C	=  encoded value
+;       A	=  non-zero on error
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;
+encode:
+	; incoming value of zero is a failure
+	call	encode5			; test DE:HL for zero
+	jr	z,encode4		; if zero, failure return
+;
+	; apply encoding divisor
+	call	div32x8			; DE:HL / C (remainder in A)
+	or	a			; set flags to test for zero
+	ret	nz			; error if not evenly divisible
+;
+	; test divide by 3 to see if it is possible
+	push	de			; save working
+	push	hl			; ... value
+	ld	c,3			; divide by 3
+	call	div32x8			; ... test
+	pop	hl			; restore working
+	pop	de			; ... value
+;
+	; implmement divide by 3 if possible
+	ld	c,$00			; init result in c w/ div 3 flag clear
+	or	a			; set flags to test for remainder
+	jr	nz,encode2		; jump if it failed
+;
+	; if divide by 3 worked, do it again for real
+	ld	c,3			; setup to divide by 3 again
+	call	div32x8			; do it
+	ld	c,$10			; init result in c w/ div 3 flag set
+;
+encode2:
+	; loop to determine power of 2
+	ld	b,16			; can only represent up to 2^15
+encode3:
+	srl	d			; right shift de:hl into carry
+	rr	e			; ...
+	rr	h			; ...
+	rr	l			; ...
+	jr	c,encode5		; if carry, then done, c has result
+	inc	c			; bump the result value
+	djnz	encode3			; keep shifting if possible
+encode4:
+	or	$ff			; signal error
+	ret				; and done
+;
+encode5:
+	; test de:hl for zero (sets zf, clobbers a)
+	ld	a,h
+	or	l
+	or	d
+	or	e
+	ret				; ret w/ Z set if DE:HL == 0

Source/Apps/FDU/Build.cmd

@@ -0,0 +1,13 @@
+@echo off
+setlocal
+
+set TOOLS=../../../Tools
+set PATH=%TOOLS%\tasm32;%PATH%
+set TASMTABS=%TOOLS%\tasm32
+
+tasm -t80 -b -fFF FDU.asm FDU.com FDU.lst
+
+if errorlevel 1 goto :eof
+
+move /Y FDU.com ..
+copy /Y FDU.txt ..\..\..\Doc\

Source/Apps/FDU/Clean.cmd

@@ -0,0 +1,4 @@
+@echo off
+if exist *.com del *.com
+if exist *.lst del *.lst
+if exist *.zip del *.zip

Source/Apps/FDU/FDU.txt

@@ -0,0 +1,473 @@
+================================================================
+Floppy Disk Utility (FDU) v5.0 for RetroBrew Computers 
+Disk IO / Zeta / Dual-IDE / N8
+================================================================
+
+Updated September 2, 2017
+by Wayne Warthen (wwarthen@gmail.com)
+
+Application to test the hardware functionality of the Floppy 
+Disk Controller (FDC) on the ECB DISK I/O, DISK I/O V3, ZETA 
+SBC, Dual IDE w/ Floppy, or N8 board.
+ 
+The intent is to provide a testbed that allows direct testing 
+of all possible media types and modes of access.  The 
+application supports read, write, and format by sector, track, 
+and disk as well as a random read/write test.
+
+The application supports access modes of polling, interrupt, 
+INT/WAIT, and DRQ/WAIT.  At present, it supports 3.5" media at 
+DD (720KB) and HD (1.44MB) capacities.  It also now supports 
+5.25" media (720KB and 1.2MB) and 8" media (1.11MB) as well.   
+Additional media will be added when I have time and access to 
+required hardware.  Not all modes are supported on all 
+platforms and some modes are experimental in all cases.
+
+In many ways this application is merely reinventing the wheel 
+and performs functionality similar to existing applications, 
+but I have not seen any other applications for RetroBrew 
+Computers hardware that provide this range of functionality.
+
+While the application is now almost entirely new code, I would 
+like to acknowledge that much was derived from the previous 
+work of Andrew Lynch and Dan Werner.  I also want to credit 
+Sergio Gimenez with testing the 5.25" drive support and Jim 
+Harre with testing the 8" drive support.  Support for Zeta 2 
+comes from Segey Kiselev.  Thanks!
+
+General Usage
+-------------
+
+In general, usage is self explanatory.  At invocation, you 
+must select the floppy disk controller (FDC) that you are 
+using.  Subsequently, the main menu allows you to set the 
+unit, media, and mode to test.  These settings MUST match your 
+situation.  Read, write, format, and verify functions are 
+provided.  A sub-menu will allow you to choose sector, track, 
+disk, or random tests.
+
+The verify function requires a little explanation.  It will 
+take the contents of the current in-memory disk buffer, save 
+it, and compare it to the selected sectors.  So, you must 
+ensure that the sectors to be verified already have been 
+written with the same pattern as the buffer contains.  I 
+typically init the buffer to a pattern, write the pattern to 
+the entire disk, then verify the entire disk.
+
+Another submenu is provided for FDC commands.  This sub-menu 
+allows you to send low-level commands directly to FDC.  You 
+*must* know what you are doing to use this sub-menu.  For 
+example, in order to read a sector using this sub-menu, you 
+will need to perform specify, seek, sense int, and read 
+commands specifying correct values (nothing is value checked 
+in this menu).
+
+Required Hardware/BIOS
+----------------------
+
+Of course, the starting point is to have a supported hardware 
+configuration. The following Z80 / Z180 based CPU boards are 
+supported:
+
+ - SBC V1/2
+ - Zeta
+ - Zeta 2
+ - N8
+ - Mark IV
+
+You must be using either a RomWBW or UBA based OS version.
+
+You must have one of the following floppy disk controllers:
+
+ - Disk IO ECB Board FDC
+ - Disk IO 3 ECB Board FDC
+ - Dual-IDE ECB Board FDC
+ - Zeta SBC onboard FDC
+ - Zeta 2 SBC onboard FDC
+ - N8 SBC onboard FDC
+ 
+Finally, you will need a floppy drive connected via an 
+appropriate cable:
+
+Disk IO - no twist in cable, drive unit 0/1 must be selected by jumper on drive
+DISK IO 3, Zeta, Zeta 2 - cable with twist, unit 0 after twist, unit 1 before twist
+DIDE, N8 - cable with twist, unit 0 before twist, unit 1 after twist
+
+Note that FDU does not utilize your systems ROM or OS to 
+access the floppy system.  FDU interacts directly with 
+hardware.  Upon exit, you may need to reset your OS to get the 
+floppy system back into a state that is expected.
+
+The Disk I/O should be jumpered as follows:
+
+J1: depends on use of interrupt modes (see interrupt modes below)
+J2: pins 1-2, & 3-4 jumpered
+J3: hardware dependent timing for DMA mode (see DMA modes below)
+J4: pins 2-3 jumpered
+J5: off
+J6: pins 2-3 jumpered
+J7: pins 2-3 jumpered
+J8: off
+J9: off
+J10: off
+J11: off
+J12: off
+
+Note that J1 can be left on even when not using interrupt 
+modes.  As long as the BIOS is OK with it, that is fine.  Note 
+also that J3 is only relevant for DMA modes, but also can be 
+left in place when using other modes.
+
+The Disk I/O 3 board should be jumpered at the default settings:
+
+JP2: 3-4
+JP3: 1-2 for int mode support, otherwise no jumper
+JP4: 1-2, 3-4
+JP5: 1-2
+JP6: 1-2
+JP7: 1-2, 3-4
+
+Zeta & Zeta 2 do not have any relevant jumper settings.  The 
+hardwired I/O ranges are assumed in the code.
+
+The Dual-IDE board should be jumpered as follows:
+
+K3 (DT/R or /RD): /RD
+P5 (bd ID): 1-2, 3-4 (for $20-$3F port range)
+
+There are no specific N8 jumper settings, but the default
+I/O range starting at $80 is assumed in the published code.
+
+
+Modes of Operation
+------------------
+
+You can select the following test modes.  Please refer to the 
+chart that follows to determine which modes should work with 
+combinations of Z80 CPU speed and media format.
+
+WARNING: In general, only the polling mode is considered fully 
+reliable.  The other modes are basically experimental and 
+should only be used if you know exactly what you are doing.
+
+Polling: Traditional polled input/output.  Works well and very 
+reliable with robust timeouts and good error recovery.  Also, 
+the slowest performance which precludes it from being used 
+with 1.44MB floppy on a 4MHz Z80. This is definitely the mode 
+you want to get working before any others. It does not require 
+J1 (interrupt enable) on DISK I/O and does not care about the 
+setting of J3.
+
+Interrupt: Relies on FDC interrupts to determine when a byte 
+is ready to be read/written.  It does *not* implement a 
+timeout during disk operations.  For example, if there is no 
+disk in the drive, this mode will just hang until a disk is 
+inserted. This mode *requires* that the host has interrupts 
+active using interrupt mode 1 (IM1) and interrupts attached to 
+the FDC controller.  The BIOS must be configured to handle 
+these interrupts safely.
+
+Fast Interrupt: Same as above, but sacrifices additional 
+reliability for faster operation.  This mode will allow a 
+1.44MB floppy to work with a 4MHz Z80 CPU.  However, if any 
+errors occur (even a transient read error which is not 
+unusual), this mode will hang.  The same FDC interrupt 
+requirements as above are required.
+
+INT/WAIT: Same as Fast Interrupt, but uses CPU wait instead of 
+actual interrupt.  This mode is exclusive to the original Disk 
+IO board.  It is subject to all the same issues as Fast 
+Interrupt, but does not need J1 shorted.  J3 is irrelevant.
+
+DRQ/WAIT: Uses pseudo DMA to handle input/output.  Does not 
+require that interrupts (J1) be enabled on the DISK I/O.  
+However, it is subject to all of the same reliability issues 
+as "Fast Interrupt".  This mode is exclusive to the original 
+Disk IO board.  At present, the mode is *not* implemented!
+
+The chart below attempts to describe the combinations that 
+work for me.  By far, the most reliable mode is Polling, but 
+it requires 8MHz CPU for HD disks.
+
+DRQ/WAIT --------------------------------+
+INT/WAIT -----------------------------+  |
+Fast Interrupt --------------------+  |  |
+Interrupt ----------------------+  |  |  |
+Polling ---------------------+  |  |  |  |
+                             |  |  |  |  |
+CPU Speed --------------+    |  |  |  |  |
+                        |    |  |  |  |  |
+                        |    |  |  |  |  |
+
+3.5" DD (720K) ------  4MHz  Y  Y  Y  Y  X
+                       8MHz+ Y  Y  Y  Y  X
+
+3.5" HD (1.44M) -----  4MHz  N  N  Y  Y  X
+                       8MHz+ Y  Y  Y  Y  X
+					   
+5.25" DD (360K) -----  4MHz  Y  Y  Y  Y  X
+                       8MHz+ Y  Y  Y  Y  X
+
+5.25" HD (1.2M) -----  4MHz  N  N  Y  Y  X
+                       8MHz+ Y  Y  Y  Y  X
+					   
+8" DD (1.11M) -------  4MHz  N  N  Y  Y  X
+                       8MHz+ Y  Y  Y  Y  X
+					   
+Y = Yes, works
+N = No, does not work
+X = Experimental, probably won't work
+
+Tracing
+-------
+
+Command/result activity to/from the FDC will be written out if 
+the trace setting is changed from '00' to '01' in setup. 
+Additionally, if a command failure is detected on any command, 
+that specific comand and results are written regardless of the 
+trace setting.
+
+The format of the line written is:
+<OPERATION>: <COMMAND BYTES> --> <RESULT BYTES> [<RESULT>]
+
+For example, this is the output of a normal read operation:
+READ: 46 01 00 00 01 02 09 1B FF --> 01 00 00 00 00 02 02 [OK]
+
+Please refer to the i8272 data sheet for information on the 
+command and result bytes.
+
+Note that the sense interrupt command can return a non-OK 
+result.  This is completely normal in some cases.  It is 
+necessary to "poll" the drive for seek status using sense 
+interrupt.  If there is nothing to report, then the result 
+will be INVALID COMMAND.  Additionally, during a recalibrate 
+operation, it may be necessary to issue the command twice 
+because the command will only step the drive 77 times looking 
+for track 0, but the head may be up to 80 tracks away.  In 
+this case, the first recalibrate fails, but the second should 
+succeed.  Here is what this would look like if trace is turned 
+on:
+
+RECALIBRATE: 07 01 --> <EMPTY> [OK]
+SENSE INTERRUPT: 08 --> 80 [INVALID COMMAND]
+	...
+	...
+	...
+SENSE INTERRUPT: 08 --> 80 [INVALID COMMAND]
+SENSE INTERRUPT: 08 --> 71 00 [ABNORMAL TERMINATION]
+RECALIBRATE: 07 01 --> <EMPTY> [OK]
+SENSE INTERRUPT: 08 --> 21 00 [OK]
+
+Another example is when the FDC has just been reset.  In this 
+case, you will see up to 4 disk change errors.  Again these 
+are not a real problem and to be expected.
+
+When tracing is turned off, the application tries to be 
+intelligent about error reporting.  The specific errors from 
+sense interrupt documented above will be suppressed because 
+they are not a real problem.  All other errors will be 
+displayed.
+
+Error Handling
+--------------
+
+There is no automated error retry logic.  This is very 
+intentional since the point is to expose the controller and 
+drive activity.  Any error detected will result in a prompt to 
+abort, retry, or continue.  Note that some number of errors is 
+considered normal for this technology.  An occasional error 
+would not necessarily be considered a problem.
+
+CPU Speed
+---------
+
+Starting with v5.0, the application adjusts it's timing loops 
+to the actual system CPU speed by querying the BIOS for the 
+current CPU speed.
+
+Interleave
+----------
+
+The format command now allows the specification of a sector 
+interleave.  It is almost always the case that the optimal 
+interleave will be 2 (meaning 2:1).
+
+360K Media
+----------
+
+The 360K media definition should work well for true 360K 
+drives.  However, it will generally not work with 1.2M 
+drives.  This is because these drives spin at 360RPM instead 
+of the 300RPM speed of true 360K drives.  Additionally, 1.2M 
+drives are 80 tracks and 360K drives are 40 tracks and, so 
+far, there is no mechanism in FD to "double step" as a way to 
+use 40 track media in 80 track drives.
+
+With this said, it is possible to configure some 1.2M 5.25" 
+drives to automatically spin down to 300RPM based on a density 
+select signal (DENSEL).  This signal is asserted by FD for 
+360K media, so IF you have configured your drive to react to 
+this signal correctly, you will be able to use the 360K media 
+defintion. Most 1.2M 5.25" drives are NOT configured this way 
+by default. TEAC drives are generally easy to modify and have 
+been tested by the author and do work in this manner.  Note 
+that this does not address the issue of double stepping above; 
+you will just be using the first 40 of 80 tracks.
+
+Support
+-------
+
+I am happy to answer questions as fast and well as I am able. 
+Best contact is wwarthen@gmail.com or post something on the 
+RetroBrew Computers Forum 
+https://www.retrobrewcomputers.org/forum/.
+
+Changes
+-------
+
+WW 8/12/2011
+
+Removed call to pulse TC in the FDC initialization after 
+determining that it periodically caused the FDC to write bad 
+sectors.  I am mystified by this, but definitely found it to 
+be true.  Will revisit at some point -- probably a timing 
+issue between puslsing TC and whatever happens next.
+
+Non-DMA mode was being set incorrectly for FAST-DMA mode. It 
+was set for non-DMA even though we were doing DMA.  It is 
+interesting that it worked fine anyway.  Fixed it anyway.
+
+DIO_SETMEDIA was not clearing DCD_DSKRDY as it should.  Fixed.
+
+WW 8/26/2011: v1.1
+
+Added support for Zeta.  Note that INT/WAIT and DRQ/WAIT are 
+not available on Zeta.  Note that Zeta provides the ability to 
+perform a reset of the FDC independent of a full CPU reset.  
+This is VERY useful and the FDC is reset anytime a drive reset 
+is required.
+
+Added INT/WAIT support.
+
+WW 8/28/2011: V1.2
+
+All changes in this version are Zeta specific.  Fixed FDC 
+reset logic and motor status display for Zeta (code from 
+Sergey).
+
+Modified Zeta disk change display to include it in the command 
+output line.  This makes more sense because a command must be 
+issued to select the desired drive first.  You can use the 
+SENSE INT command id you want to check the disk change value 
+at any time.  It will also be displayed with any other command 
+output display.
+
+WW 9/1/2011: V1.3
+
+Added CPUFREQ configuration setting to tune delays based on 
+cpu speed.  The build app is set for 8MHz which also seems to 
+work well for 4MHz CPU's.  Faster CPU speeds will probably 
+require tuning this setting.
+
+WW 9/5/2011: V1.4
+
+Changed the polling execution routines to utilize CPUFREQ 
+variable to optimize timeout counter.  Most importantly, this 
+should allow the use of faster CPUs (like 20MHz).
+
+WW 9/19/2011: V1.5
+
+Zeta changes only.  Added a call to FDC RESET after any 
+command failure.  This solves an issue where the drive remains 
+selected if a command error occurs.  Also added FDC RESET to 
+FDC CONTROL menu.
+
+WW 10/7/2011: V2.0
+
+Added support for DIDE.  Only supports polling IO and it does 
+not appear any other modes are possible given the hardware 
+constraints.
+
+WW 10/13/2011: V2.1
+
+Modified to support N8.  N8 is essentially identical to Dual 
+IDE. The only real change is the IO addresses.  In theory, I 
+should be able to support true DMA on N8 and will work on that.
+
+WW 10/20/2011: v2.2
+
+I had some problems with the results being read were sometimes 
+missing a byte.  Fixed this by taking a more strict approach 
+to watching the MSR for the exact bits that are expected.
+
+WW 10/22/2011: V2.3
+
+After spending a few days trying to track down an intermittent 
+data corruption issue with my Dual IDE board, I added a verify 
+function.  This helped me isolate the problem very nicely 
+(turned out to be interference from the bus monitor).
+
+WW 11/25/2011: V2.4
+
+Preliminary support for DISKIO V3.  Basically just assumed 
+that it operates just like the Zeta.  Needs to be verified 
+with real hardware as soon as I can.
+
+WW 1/9/2012: V2.5
+
+Modified program termination to use CP/M reset call so that a 
+warm start is done and all drives are logged out.  This is 
+important because media may have been formatted during the 
+program execution.
+
+WW 2/6/2012: v2.6
+
+Added support for 5.25" drives as tested by Sergio.
+
+WW 4/5/2012: v2.7
+
+Added support for 8" drives as tested by Jim Harre.
+
+WW 4/6/2012: v2.7a
+
+Fixed issue with media selection menu to remove duplicate 
+entries.
+
+WW 4/8/2012: v2.7b
+
+Corrected the handling of the density select signal.
+
+WW 5/22/2012: v2.8
+
+Added new media definitions (5.25", 320K).
+
+WW 6/1/2012: v2.9
+
+Added interleave capability on format.
+
+WW 6/5/2012: v3.0
+
+Documentation cleanup.
+
+WW 7/1/2012: v3.1
+
+Modified head load time (HLT) for 8" media based on YD-180 
+spec.  Now set to 50ms.
+
+WW 6/17/2013: v3.2
+
+Cleaned up SRT, HLT, and HUT values.
+
+SK 2/10/2015: v3.3
+
+Added Zeta SBC v2 support (Sergey Kiselev)
+
+WW 3/25/2015: v4.0
+
+Renamed from FDTST --> FD
+
+WW 9/2/2017: v5.0
+
+Renamed from FD to FDU.
+Added runtime selection of FDC hardware.
+Added runtime timing adjustment.

Source/Apps/Format.asm

@@ -201,12 +201,12 @@ stksav	.dw	0		; stack pointer saved at start
 	.fill	stksiz,0	; stack
 stack	.equ	$		; stack top
 ;
-msgban1	.db	"FORMAT v0.1 for RomWBW CP/M 2.2, 24-Apr-2016",0
+msgban1	.db	"FORMAT v0.1a for RomWBW CP/M 2.2, 02-Sep-2017",0
 msghb	.db	" (HBIOS Mode)",0
 msgub	.db	" (UBIOS Mode)",0
-msgban2	.db	"Copyright 2016, Wayne Warthen, GNU GPL v3",0
+msgban2	.db	"Copyright (C) 2017, Wayne Warthen, GNU GPL v3",0
 msguse	.db	"FORMAT command is not yet implemented!",13,10,13,10
-	.db	"Use FD command to physically format floppy diskettes",13,10
+	.db	"Use FDU command to physically format floppy diskettes",13,10
 	.db	"Use CLRDIR command to (re)initialize directories",13,10
 	.db	"Use SYSCOPY command to make disks bootable",13,10
 	.db	"Use FDISK80 command to partition mass storage media",0

Source/Apps/XM/Build.cmd

@@ -0,0 +1,19 @@
+@echo off
+setlocal
+
+set TOOLS=..\..\..\Tools
+
+set PATH=%TOOLS%\zx;%PATH%
+
+set ZXBINDIR=%TOOLS%\cpm\bin\
+set ZXLIBDIR=%TOOLS%\cpm\lib\
+set ZXINCDIR=%TOOLS%\cpm\include\
+
+zx mac xmdm125
+zx slr180 -xmhb/HF
+zx mload25 XM=xmdm125,xmhb
+
+rem set PROMPT=[Build] %PROMPT%
+rem %comspec%
+
+move /Y XM.com ..

Source/Apps/XM/Clean.cmd

@@ -0,0 +1,7 @@
+@echo off
+setlocal
+
+if exist *.hex del *.hex
+if exist *.prn del *.prn
+if exist *.lst del *.lst
+if exist xm.com del xm.com

Source/Apps/XM/xmhb.180

@@ -0,0 +1,412 @@
+;=======================================================================
+;
+; XMHB.Z80 - XMODEMXX PATCH FILE FOR ROMWBW HBIOS
+;
+;   Wayne Warthen - wwarthen@gmail.com
+;   Updated: 2017-08-09
+;
+;=======================================================================
+;
+; Overlay file is Z80, build with M80:
+;   M80 =XMHB
+;   L80 XMHB,XMHB/N/X/E
+;
+	.Z80
+	ASEG
+;
+NO	EQU	0
+YES	EQU	NOT NO
+;
+ERRDET	EQU	NO		; detect parity/framing/overrun errs
+;
+BASE	EQU	100H		; start of cp/m normal program area
+;
+BDOS	EQU	00005H		; BDOS function dispatch vector
+;
+;=======================================================================
+;
+; Jump table: The jump table must be in exactly the same sequence as the
+; one in XMODEM.  Note the ORG of 103H - This jump table has no jump to
+; 'BEGIN'.
+;
+	ORG	BASE + 3	;start after 'JMP BEGIN'
+;
+	JP	CONOUT		;must be 00000h if not used, see below
+	JP	MINIT		;initialization routine (if needed)
+	JP	UNINIT		;undo whatever 'MINIT' did (or return)
+JPTBL:
+	JP	SENDR		;send character (via pop psw)
+	JP	CAROK		;test for carrier
+	JP	MDIN		;receive data byte
+	JP	GETCHR		;get character from modem
+	JP	RCVRDY		;check receive ready
+	JP	SNDRDY		;check send ready
+	JP	SPEED		;get speed value for file transfer time
+	JP	EXTRA1		;extra for custom routine
+	JP	EXTRA2		;extra for custom routine
+	JP	EXTRA3		;extra for custom routine
+;
+;-----------------------------------------------------------------------
+;
+; Output character to console
+;
+CONOUT	EQU	0		; not used
+;
+;-----------------------------------------------------------------------
+;
+; Initialize modem
+;
+; This procedure has been usurped to dynamically detect the type
+; of system we are running on and install the *real* jump table
+; entries as appropriate.
+;
+MINIT:
+;
+	; Announce
+	LD	DE,RBC		; RetroBrew Computers
+	LD	C,9		; BDOS string display function
+	CALL	BDOS		; Do it
+;
+	; Get system type
+	LD	DE,00202H	; D := 2, E := 2
+	MLT	DE		; DE := D * E == 4
+	BIT	2,E		; Bit 2 wil be set if mlt happend
+	LD	HL,U_JPTBL	; Assume Z80 (UART)
+	LD	DE,UART		; UART port notification string
+	JR	Z,MINIT2	; Yes, Z80, do vector copy
+	LD	HL,A_JPTBL	; Otherwise Z180 (ASCI)
+	LD	DE,ASCI		; ASCI port notification string
+;
+MINIT2:
+	; Display port notification string
+	PUSH	HL		; Save HL
+	LD	C,9		; BDOS string display function
+	CALL	BDOS		; Do it
+	POP	HL		; Recover HL
+;
+	; Copy real vectors into active jump table
+	LD	DE,JPTBL	; Real jump table is destination
+	LD	BC,7 * 3	; Copy 7 3-byte entries
+	LDIR			; Do the copy
+;
+	; Check for UNA (UBIOS)
+	LD	A,(0FFFDH)	; fixed location of UNA API vector
+	CP	0C3H		; jp instruction?
+	JR	NZ,MINIT3	; if not, not UNA
+	LD	HL,(0FFFEH)	; get jp address
+	LD	A,(HL)		; get byte at target address
+	CP	0FDH		; first byte of UNA push ix instruction
+	JR	NZ,MINIT3	; if not, not UNA
+	INC	HL		; point to next byte
+	LD	A,(HL)		; get next byte
+	CP	0E5H		; second byte of UNA push ix instruction
+	JR	NZ,MINIT3	; if not, not UNA
+;
+	; Display UNA notification string
+	LD	DE,UBIOS	; BIOS notification string
+	LD	C,9		; BDOS string display function
+	CALL	BDOS
+;
+	; Get CPU speed from UNA and return
+	LD	C,0F8H		; UNA BIOS Get PHI function
+	RST	08		; Returns speed in Hz in DE:HL
+	LD	B,4		; Divide MHz in DE:HL by 100000H 
+MINIT2A:
+	SRL	D		; ... to get approx CPU speed in
+	RR	E		; ...MHz.  Throw away HL, and
+	DJNZ	MINIT2A		; ...right shift DE by 4.
+	INC	E		; Fix up for value truncation
+	LD	A,E		; Put in A
+	RET			; Done
+;
+MINIT3:
+	; Not UNA, try RomwBW HBIOS for CPU speed lookup
+	LD	HL,(0FFFEH)	; HL := HBIOS ident location
+	LD	A,'W'		; First byte of ident
+	CP	(HL)		; Compare
+	JR	NZ,MINIT4	; Not HBIOS
+	INC	HL		; Next byte of ident
+	LD	A,~'W'		; Second byte of ident
+	CP	(HL)		; Compare
+	JR	NZ,MINIT4	; Not HBIOS
+;
+	; Display RomWBW notification string
+	LD	DE,HBIOS	; BIOS notification string
+	LD	C,9		; BDOS string display function
+	CALL	BDOS		; Do it
+;
+	; Get CPU speed from RomWBW HBIOS and return
+	LD	B,0F8H		; HBIOS SYSGET function 0xF8
+	LD	C,0F0H		; CPUINFO subfunction 0xF0
+	RST	08		; Do it, L := CPU speed in MHz
+	LD	A,L		; Move it to A
+	RET			; Done
+;
+MINIT4:
+	; Neither UNA nor RomWBW
+	LD	DE,BIOERR	; BIOS error message
+	LD	C,9		; BDOS string display function
+	CALL	BDOS		; Do it
+	JP	0		; Bail out!
+;
+RBC	DB	"RBC, 28-Aug-2017, $"
+;
+UART	DB	"UART0$"
+ASCI	DB	"ASCI0$"
+;
+UBIOS	DB	" [UNA]", 13, 10, "$"
+HBIOS	DB	" [WBW]", 13, 10, "$"
+;
+BIOERR	DB	13, 10, 13, 10, "*** Unknown BIOS ***", 13, 10, "$"
+;
+;-----------------------------------------------------------------------
+;
+; Uninitialize modem
+;
+UNINIT:
+	RET			; not initialized, so no 'UN-INITIALIZE'
+;
+;-----------------------------------------------------------------------
+;
+; The following are all dummy routines that are unused because MINIT
+; dynamically installs the real jump table.
+;
+SENDR:
+CAROK:
+MDIN:
+GETCHR:
+RCVRDY:
+SNDRDY:
+SPEED:
+EXTRA1:
+EXTRA2:
+EXTRA3:
+	RET
+;
+;=======================================================================
+;=======================================================================
+;
+; Standard RBC Projects 8250-like UART port @ 68H
+;
+; Will be used for all RBC Z80 systems.
+;
+;=======================================================================
+;=======================================================================
+;
+; UART port constants
+;
+U_BASE	EQU	68H		; UART base port
+U_DATP	EQU	U_BASE + 0	; data in port
+U_DATO	EQU	U_BASE + 0	; data out port
+U_CTLP	EQU	U_BASE + 5	; control/status port
+U_SNDB	EQU	20H		; bit to test for send ready
+U_SNDR	EQU	20H		; value when ready to send
+U_RCVB	EQU	01H		; bit to test for receive ready
+U_RCVR	EQU	01H		; value when ready to receive
+U_PARE	EQU	04H		; bit for parity error
+U_OVRE	EQU	02H		; bit for overrun error
+U_FRME	EQU	08H		; bit for framing error
+;
+; Following jump table is dynamically patched into real jump
+; table at program startup.  See MINIT above.  Note that only a
+; subset of the jump table is overlaid (SENDR to SPEED).
+;
+U_JPTBL:
+	JP	U_SENDR		; send character (via pop psw)
+	JP	U_CAROK		; test for carrier
+	JP	U_MDIN		; receive data byte
+	JP	U_GETCHR	; get character from modem
+	JP	U_RCVRDY	; check receive ready
+	JP	U_SNDRDY	; check send ready
+	JP	U_SPEED		; get speed value for file transfer time
+;
+;-----------------------------------------------------------------------
+;
+; Send character on top of stack
+;
+U_SENDR:
+	POP	AF		; get character to send from stack
+	OUT	(U_DATO),A	; send to port
+	RET
+;
+;-----------------------------------------------------------------------
+;
+; Test and rep;ort carrier status, Z set if carrier present
+;
+U_CAROK:
+	XOR	A		; not used, always indicate present
+	RET
+;
+;-----------------------------------------------------------------------
+;
+; Get a character (assume character ready has already been tested)
+;
+U_MDIN:
+U_GETCHR:
+	IN	A,(U_DATP)	; read character from port
+	RET
+;
+;-----------------------------------------------------------------------
+;
+; Test for character ready to receive, Z = ready
+; Error code returned in A register
+; *** Error code does not seem to be used ***
+;
+U_RCVRDY:
+	IN	A,(U_CTLP)	; get modem status
+;
+	 IF ERRDET
+;
+	; With error detection (slower)
+	PUSH	BC		; save scratch register
+	PUSH	AF		; save full status on stack
+	AND	U_FRME | U_OVRE | U_PARE ; isolate line err bits
+	LD	B,A		; save err status in B
+	POP	AF		; get full status back
+	AND	U_RCVB		; isolate ready bit
+	CP	U_RCVR		; test it (set flags)
+	LD	A,B		; get the error code back
+	POP	BC		; restore scratch register
+;
+	 ELSE
+;
+	; No error detection (faster)
+	AND	U_RCVB		; isolate ready bit
+	CP	U_RCVR		; test it (set flags)
+	LD	A,0		; report no line errors
+;
+	 ENDIF
+;
+	RET
+;
+;-----------------------------------------------------------------------
+;
+; Test for ready to send a character, Z = ready
+;
+U_SNDRDY:
+	IN	A,(U_CTLP)	; get status
+	AND	U_SNDB		; isolate transmit ready bit
+	CP	U_SNDR		; test for ready value
+	RET
+;
+;-----------------------------------------------------------------------
+;
+; Report baud rate (index into SPTBL returned in regsiter A)
+;
+U_SPEED:
+	LD	A,8		; arbitrarily return 9600 baud
+	RET
+;
+;=======================================================================
+;=======================================================================
+;
+; Standard RBC Projects Z180 primary ASCI port
+;
+; Will be used for all RBC Z180 systems.
+;
+;=======================================================================
+;=======================================================================
+;
+; ASCI port constants
+;
+A_DATP	EQU	48H		;Z180 TSR - ASCI receive data port
+A_DATO	EQU	46H		;Z180 TDR - ASCI transmit data port
+A_CTLP	EQU	44H		;Z180 STAT - ASCI status port
+A_CTL2	EQU	40H		;Z180 CNTLA - ASCI control port
+A_SNDB	EQU	02H		;Z180 STAT:TDRE - xmit data reg empty bit
+A_SNDR	EQU	02H		;Z180 STAT:TDRE - xmit data reg empty value
+A_RCVB	EQU	80H		;Z180 STAT:RDRF - rcv data reg full bit
+A_RCVR	EQU	80H		;Z180 STAT:RDRF - rcv data reg full value
+A_PARE	EQU	20H		;Z180 STAT:PE - parity error bit
+A_OVRE	EQU	40H		;Z180 STAT:OVRN - overrun error bit
+A_FRME	EQU	10H		;Z180 STAT:FE - framing error bit
+;
+; Following jump table is dynamically patched over initial jump
+; table at program startup.  See MINIT above.  Note that only a
+; subset of the jump table is overlaid (SENDR to SPEED).
+;
+A_JPTBL:
+	JP	A_SENDR		;send character (via pop psw)
+	JP	A_CAROK		;test for carrier
+	JP	A_MDIN		;receive data byte
+	JP	A_GETCHR	;get character from modem
+	JP	A_RCVRDY	;check receive ready
+	JP	A_SNDRDY	;check send ready
+	JP	A_SPEED		;get speed value for file transfer time
+;
+;-----------------------------------------------------------------------
+;
+; Send character on top of stack
+;
+A_SENDR:
+	POP	AF		; get character to send from stack
+	OUT0	(A_DATO),A	; send to port
+	RET
+;
+;-----------------------------------------------------------------------
+;
+; Test and rep;ort carrier status, Z set if carrier present
+;
+A_CAROK:
+	XOR	A		; not used, always indicate present
+	RET
+;
+;-----------------------------------------------------------------------
+;
+; Get a character (assume character ready has already been tested)
+;
+A_MDIN:
+A_GETCHR:
+	IN0	A,(A_DATP)	; read character from port
+	RET
+;
+;-----------------------------------------------------------------------
+;
+; Test for character ready to receive, Z = ready
+; Error code returned in A register
+; *** Error code does not seem to be used ***
+;
+A_RCVRDY:
+	IN0	A,(A_CTLP)	; get modem status
+	PUSH	BC		; save scratch register
+	PUSH	AF		; save full status on stack
+	AND	A_FRME | A_OVRE | A_PARE ; isolate line err bits
+	LD	B,A		; save err status in B
+	
+	; Z180 ASCI ports will stall if there are errors.
+	; Error bits are NOT cleared by merely reading
+	; the status register.  Below, bit 3 of ASCI
+	; control register is written with a zero to 
+	; clear error(s) if needed.
+	JP	Z,A_RCVRDY2	; if no errs, continue
+	IN0	A,(A_CTL2)	; get current control register
+	AND	0F7H		; force err reset bit to zero
+	OUT0	(A_CTL2),A	; write control register
+
+A_RCVRDY2:
+	POP	AF		; get full status back
+	AND	A_RCVB		; isolate ready bit
+	CP	A_RCVR		; test it (set flags)
+	LD	A,B		; get the error code back
+	POP	BC		; restore scratch register
+	RET
+;
+;-----------------------------------------------------------------------
+;
+; Test for ready to send a character, Z = ready
+;
+A_SNDRDY:
+	IN	A,(A_CTLP)	; get status
+	AND	A_SNDB		; isolate transmit ready bit
+	CP	A_SNDR		; test for ready value
+	RET
+;
+;-----------------------------------------------------------------------
+;
+; Report baud rate (index into SPTBL returned in regsiter A)
+;
+A_SPEED:
+	LD	A,8		; arbitrarily return 9600 baud
+	RET
+;
+	END

Source/Apps/bcd.asm

@@ -0,0 +1,104 @@
+;;
+;; make a bcd number from a binary number
+;; 32 bit binary number in hl:bc, result stored at (de)
+;; de is preserved, all other regs destroyed
+;;
+;bin2bcd:
+;	push	ix		; save ix
+;	push	bc		; move bc
+;	pop	ix		; ... to ix
+;	ld	c,32		; loop for 32 bits of binary dword
+;;
+;bin2bcd0:
+;	; outer loop (once for each bit in binary number)	
+;	ld	b,5		; loop for 5 bytes of result
+;	push	de		; save de
+;	add	ix,ix		; left shift next bit from hl:ix
+;	adc	hl,hl		; ... into carry
+;;
+;bin2bcd1:
+;	; inner loop (once for each byte of bcd number)
+;	ld	a,(de)		; get it
+;	adc	a,a		; double it w/ carry
+;	daa			; decimal adjust
+;	ld	(de),a		; save it
+;	inc	de		; point to next bcd byte
+;	djnz	bin2bcd1	; loop thru all bcd bytes
+;;
+;	; remainder of outer loop
+;	pop	de		; recover de
+;	dec	c		; dec bit counter
+;	jr	nz,bin2bcd0	; loop till done with all bits
+;	pop	ix		; restore ix
+;
+; make a bcd number from a binary number
+; 32 bit binary number in de:hl, result stored at (bc)
+; on output hl = bcd buf adr
+;
+bin2bcd:
+	push	ix		; save ix
+	; convert from de:hl -> (bc) to hl:ix -> (de)
+	; hl -> ix, de -> hl, bc -> de
+	ex	de,hl
+	push	de
+	pop	ix
+	push	bc
+	pop	de
+;
+	ld	c,32		; loop for 32 bits of binary dword
+;
+bin2bcd0:
+	; outer loop (once for each bit in binary number)	
+	ld	b,5		; loop for 5 bytes of result
+	push	de		; save de
+	add	ix,ix		; left shift next bit from hl:ix
+	adc	hl,hl		; ... into carry
+;
+bin2bcd1:
+	; inner loop (once for each byte of bcd number)
+	ld	a,(de)		; get it
+	adc	a,a		; double it w/ carry
+	daa			; decimal adjust
+	ld	(de),a		; save it
+	inc	de		; point to next bcd byte
+	djnz	bin2bcd1	; loop thru all bcd bytes
+;
+	; remainder of outer loop
+	pop	de		; recover de
+	dec	c		; dec bit counter
+	jr	nz,bin2bcd0	; loop till done with all bits
+	ex	de,hl		; hl -> bcd buf
+	pop	ix		; restore ix
+	ret
+;
+; print contents of 5 byte bcd number at (hl)
+; with leading zero suppression
+; all regs destroyed
+;
+prtbcd:
+	inc	hl		; bump hl to point to
+	inc	hl		; ...
+	inc	hl		; ...
+	inc	hl		; ... last byte of bcd
+	ld	b,5		; loop for 5 bytes
+	ld	c,0		; start by suppressing leading zeroes
+;
+prtbcd1:
+	; loop to print one bcd byte (two digits)
+	xor	a		; clear accum
+	rld			; rotate first nibble into a
+	call	prtbcd2		; print it
+	xor	a		; clear accum
+	rld			; rotate second nibble into a
+	call	prtbcd2		; print it
+	dec	hl		; point to prior byte
+	djnz	prtbcd1		; loop till done
+	ret			; return
+;
+prtbcd2:
+	; subroutine to print a digit in a
+	cp	c		; compare incoming to c
+	ret	z		; if equal, suppressing, abort
+	dec	c		; make c negative to stop suppression
+	add	a,'0'		; offset to printable value
+	jp	prtchr		; exit via character out

Source/CBIOS/ver.inc

@@ -1,5 +1,5 @@
 #DEFINE	RMJ	2
 #DEFINE	RMN	8
-#DEFINE	RUP	1
+#DEFINE	RUP	3
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"2.8.2"
+#DEFINE BIOSVER	"2.8.4"

Source/Doc/Build.cmd

@@ -2,5 +2,5 @@
 setlocal
 
 setlocal & cd "ZCPR Manual" && call Build.cmd || exit /b 1 & endlocal
-setlocal & cd "RomWBW User Guide" && call Build.cmd || exit /b 1 & endlocal
-setlocal & cd "RomWBW System Guide" && call Build.cmd || exit /b 1 & endlocal
+rem setlocal & cd "RomWBW User Guide" && call Build.cmd || exit /b 1 & endlocal
+rem setlocal & cd "RomWBW System Guide" && call Build.cmd || exit /b 1 & endlocal

Source/HBIOS/hbios.asm

@@ -2665,9 +2665,9 @@ PS_PRTSC0:
 	PUSH	DE			; PRESERVE DE
 	CALL	PC_COMMA		; FORMATTING
 	LD	A,E			; GET CONFIG BYTE
-	RLCA				; SHIFT RELEVANT BITS
-	RLCA				; ...
-	RLCA				; ...
+	RRCA				; SHIFT RELEVANT BITS
+	RRCA				; ...
+	RRCA				; ...
 	AND	$07			; AND ISOLATE DATA BITS VALUE
 	LD	HL,PS_STPARMAP		; CHARACTER LOOKUP TABLE
 	CALL	ADDHLA			; APPLY OFFSET
@@ -2678,8 +2678,8 @@ PS_PRTSC0:
 	; PRINT STOP BITS
 	CALL	PC_COMMA		; FORMATTING
 	LD	A,E			; GET CONFIG BYTE
-	RLCA				; SHIFT RELEVANT BITS
-	RLCA				; ...
+	RRCA				; SHIFT RELEVANT BITS
+	RRCA				; ...
 	AND	$01			; AND ISOLATE DATA BITS VALUE
 	ADD	A,'1'			; MAKE IT A CHARACTER
 	CALL	COUT			; AND PRINT

Source/HBIOS/util.asm

@@ -455,7 +455,6 @@ JPHL:	JP	(HL)
 ;
 ;   A REGISTER IS DESTROYED!
 ;
-
 ADDHLA:
 	ADD	A,L
 	LD	L,A
@@ -520,7 +519,7 @@ BYTE2BCD1:
 ;   IMPACT OF OVERHEAD DIMINISHES AS CPU SPEED INCREASES
 ;
 ; CPU SCALER (CPUSCL) = (CPUHMZ - 2) FOR 16US + 3TS DELAY
-;   NOTE: CPUSCL MUST BE >= 3!
+;   NOTE: CPUSCL MUST BE >= 1!
 ;
 ; EXAMPLE: 8MHZ CPU (DELAY GOAL IS 16US)
 ;   LOOP = ((6 * 16) - 5) = 91TS
@@ -602,9 +601,15 @@ LDELAY:
 ;
 DELAY_INIT:
 #IF (PLATFORM == PLT_UNA)
-	LD	C,$F9			; UBIOS FUNC=GET CPU INFO
-	RST	08			; E := CPU MHZ
-	LD	E,A			; PUT SPEED IN MHZ IN ACCUM
+	LD	C,$F8			; UNA BIOS GET PHI FUNCTION
+	RST	08			; RETURNS SPEED IN HZ IN DE:HL
+	LD	B,4			; DIVIDE MHZ IN DE:HL BY 100000H 
+DELAY_INIT0:	
+	SRL	D			; ... TO GET APPROX CPU SPEED IN
+	RR	E			; ...MHZ.  THROW AWAY HL, AND
+	DJNZ	DELAY_INIT0		; ...RIGHT SHIFT DE BY 4.
+	INC	E			; FIX UP FOR VALUE TRUNCATION
+	LD	A,E			; PUT IN A
 #ELSE
 	LD	B,BF_SYSGET		; HBIOS FUNC=GET SYS INFO
 	LD	C,BF_SYSGET_CPUINFO	; HBIOS SUBFUNC=GET CPU INFO

Source/HBIOS/ver.inc

@@ -1,5 +1,5 @@
 #DEFINE	RMJ	2
 #DEFINE	RMN	8
-#DEFINE	RUP	2
+#DEFINE	RUP	3
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"2.8.2"
+#DEFINE BIOSVER	"2.8.4"