CTC & CPU Speed

- Revamped CTC detection algorithm hoping to handle problem XRBR is having
- Fixed typo in dynamic CPU speed test that caused it to not be properly recorded/reported (credit XRBR)
- Allow use of DEL/RUBOUT keys as backspace in ROM Loader and Debug Monitor

Doc/ChangeLog.txt

@@ -1,3 +1,8 @@
+Version 3.2.1
+-------------
+- M?P: Fixed Zeta 2 FDD and CPUSPD config settings
+- WBW: Fixed SURVEY.COM (again)
+
 Version 3.2
 -----------
 - WBW: Version bump for release

ReadMe.md

@@ -1,9 +1,9 @@
 
 
 **RomWBW ReadMe** \
-Version 3.2 \
+Version 3.2.1 \
 Wayne Warthen  ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \
-18 Mar 2023
+22 Mar 2023
 
 # Overview
 
@@ -102,22 +102,22 @@ functionality.
 
 Complete instructions for installation and operation of RomWBW are found
 in the [RomWBW User
-Guide](https://github.com/wwarthen/RomWBW/raw/master/Doc/RomWBW%20User%20Guide.pdf).
+Guide](https://github.com/wwarthen/RomWBW/raw/dev/Doc/RomWBW%20User%20Guide.pdf).
 
 ## Documentation
 
 Documentation for RomWBW includes:
 
 - [RomWBW User
-  Guide](https://github.com/wwarthen/RomWBW/raw/master/Doc/RomWBW%20User%20Guide.pdf)
+  Guide](https://github.com/wwarthen/RomWBW/raw/dev/Doc/RomWBW%20User%20Guide.pdf)
 - [RomWBW System
-  Guide](https://github.com/wwarthen/RomWBW/raw/master/Doc/RomWBW%20System%20Guide.pdf)
+  Guide](https://github.com/wwarthen/RomWBW/raw/dev/Doc/RomWBW%20System%20Guide.pdf)
 - [RomWBW
-  Applications](https://github.com/wwarthen/RomWBW/raw/master/Doc/RomWBW%20Applications.pdf)
+  Applications](https://github.com/wwarthen/RomWBW/raw/dev/Doc/RomWBW%20Applications.pdf)
 - [RomWBW ROM
-  Applications](https://github.com/wwarthen/RomWBW/raw/master/Doc/RomWBW%20ROM%20Applications.pdf)
+  Applications](https://github.com/wwarthen/RomWBW/raw/dev/Doc/RomWBW%20ROM%20Applications.pdf)
 - [RomWBW
-  Errata](https://github.com/wwarthen/RomWBW/raw/master/Doc/RomWBW%20Errata.pdf)
+  Errata](https://github.com/wwarthen/RomWBW/raw/dev/Doc/RomWBW%20Errata.pdf)
 
 # Acknowledgments
 

ReadMe.txt

@@ -1,6 +1,6 @@
 RomWBW ReadMe
 Wayne Warthen (wwarthen@gmail.com)
-18 Mar 2023
+22 Mar 2023
 
 
 

Source/Apps/Survey/survey.mac

@@ -15,6 +15,13 @@
 ;
 ;VERSION LIST - Most recent version first.
 ;
+;21/Mar/23 - Previous hack was worthless because it broke
+;            the memory survey.  Rehacked to use HBIOS to
+;            detect if N8VEM SBC MPCL memory management is
+;            in use and bypass MPCL ports if so.  HBIOS check
+;            should allow use in non-RomWBW systems again.
+;            Wayne Warthen
+;
 ;10/Feb/23 - Total hack to avoid crash on ECB SBC
 ;            RomWBW now required by this version
 ;            Wayne Warthen
@@ -240,20 +247,6 @@ TABS	EQU	9		; Tab columns
 ;
 	;ORG	100H
 ;
-;
-;
-	.Z80
-	LD	HL,IMGORG
-	LD	DE,START
-	LD	BC,IMGEND-IMGORG
-	LDIR
-	JP	START
-	.8080
-;
-IMGORG:
-;
-	.PHASE	8000H
-;
 START:
 	LXI	H,0			; Save stack pointer
 	DAD	SP
@@ -261,9 +254,38 @@ START:
 	LXI	SP,FINIS+64
 	CALL	TYPE			; Type initial CRLF
 	DW	CRLF,CRLF
-	DB	TAB,'*** RomWBW System Survey (Feb 2023) ***'
+	DB	TAB,'*** RomWBW System Survey (Mar 2023) ***'
 	DW	CRLF,CRLFE
+;
+; Are we running an N8VEM SBC w/ MPCL on RomWBW???
+;
+	.Z80
+	XOR	A		; assume not
+	LD	(ISMPCL),A	; save it
 
+	; Check for RomWBW (HBIOS)
+	LD	HL,(0FFFEH)	; HL := HBIOS ident location
+	LD	A,'W'		; First byte of ident
+	CP	(HL)		; Compare
+	JR	NZ,NOTMPCL	; Not HBIOS
+	INC	HL		; Next byte of ident
+	LD	A,NOT 'W'	; Second byte of ident
+	CP	(HL)		; Compare
+	JR	NZ,NOTMPCL	; Not HBIOS
+;
+	LD	B,0F1H		; HBIOS: VER function
+	LD	C,0		; required reserved value
+	RST	08		; DE := version, L := platform id
+	LD	A,L		; Platform ID
+	CP	01H		; SBC?
+	JR	NZ,NOTMPCL	; Not SBC
+	LD	A,0FFH		; Flag
+	LD	(ISMPCL),A	; Set flag
+;
+	.8080
+;
+NOTMPCL:
+;
 ;DISK SURVEY
 	LXI	H,8			; Init drive counter
 	MVI	C,24			; Get login vector
@@ -445,20 +467,19 @@ MSURV:
 	ENDM
 	DB	'|'
 	DW	CRLF
-	db	' '			; dmb 31-May-82
-	DB	'T'+EOL
+	DB	'TT','T'+EOL
 	LXI	H,RAM
-	MVI	M,LOW 1023		; Init RAM counter
+	MVI	M,LOW 2047		; Init RAM counter
 	INX	H
-	MVI	M,HIGH 1023
+	MVI	M,HIGH 2047
 	MVI	B,4			; Clear ROM, EMP
 CLREG:
 	INX	H
 	MVI	M,0
 	DCR	B
 	JNZ	CLREG
-	LXI	H,1024			; Init memory pointer
-	MVI	C,63			; K to be checked
+	LXI	H,2048			; Init memory pointer
+	MVI	C,62			; K to be checked
 
 ;Start of analysis loop
 BEGANA:
@@ -492,7 +513,7 @@ NOTEM:
 	INXI	ROM
 NEXT:
 	INX	H			; Index next byte
-	DCX	D			; Decrement K counter
+	DCX	D			; DEC DE; Decrement K counter
 	XRA	A
 	ORA	D
 	ORA	E
@@ -545,8 +566,19 @@ NEXTK:
 ; contents of first page
 	call	type
 	db	'BIOS at',' '+eol
-	hexout	bios+2
-	hexout	bios+1
+	;hexout	bios+2
+	;hexout	bios+1
+	.z80
+	ld	hl,(bios+1)
+	ld	de,-3
+	add	hl,de
+	push	hl
+	ld	a,h
+	call	hexprn
+	pop	hl
+	ld	a,l
+	call	hexprn
+	.8080
 	call	type
 	db	tab,'iobyte',' '+eol
 	hexout	bios+3
@@ -555,8 +587,19 @@ NEXTK:
 	hexout	bios+4
 	call	type
 	db	tab,'BDOS at',' '+eol
-	hexout	bdos+2
-	hexout	bdos+1
+	;hexout	bdos+2
+	;hexout	bdos+1
+	.z80
+	ld	hl,(bdos+1)
+	ld	de,-6
+	add	hl,de
+	push	hl
+	ld	a,h
+	call	hexprn
+	pop	hl
+	ld	a,l
+	call	hexprn
+	.8080
 	call	type
 	dw	crlf,crlfe
 ;
@@ -607,9 +650,6 @@ PDLY:
 	JNZ	PDLY
 ;
 	.Z80
-	; record the active bank
-	ld	a,(0ffe0h)		; get current hbios bank id
-	ld	(BANK),a		; and save it
 	; Check for Z180 CPU
 	xor	a			; assume Z80
 	ld	(IS180),a		; save it
@@ -635,6 +675,17 @@ PORTLP:
 	ENDIF
 ;
 	.Z80
+;
+	ld	a,(ISMPCL)		; MPCL?
+	or	a			; set flags
+	jr	z,PCONT			; if not, skip ahead
+	ld	a,d			; get port to test
+	and	0F8H			; range of 8 ports
+	cp	078H			; starting at 78H
+	jr	z,ISPORT		; if in range, assume real port
+;
+PCONT:
+
 	di				; interrupts off
 	ld	a,(IS180)		; Z180?
 	or	a
@@ -679,11 +730,6 @@ pnum1b	equ	$-1
 	push	af
 ;
 rdz:
-	; Make sure correct bank is still selected!
-	push	af
-	ld	a,(BANK)
-	call	0FFF3H
-	pop	af
 ;
 	ei				; interrupts back on now
 ;
@@ -818,13 +864,9 @@ RAMF:	DS	1			; RAM good flag
 EMPF:	DS	1			; Empty so far flag
 BLKSHF:	DS	1			; block shift factor
 MAXALL:	DS	2			; maximum block number
-BANK:	DS	1			; saved HBIOS bank id
 IS180:	DS	1			; non-zero for Z180 CPU
+ISMPCL:	DS	1			; non-zero for N8VEM SBC MPCL
 FINIS	EQU	$			; End of program
-;
-	.DEPHASE
-;
-IMGEND:
 ;
 	END
 

Source/Doc/UserGuide.md

@@ -3353,7 +3353,7 @@ the RomWBW HBIOS configuration.
 | Interrupts        | Mode 2        |
 
  - CPU speed is detected at startup if DS1302 RTC is active
-   - Otherwise 20.000 MHz assumed
+   - Otherwise 8.000 MHz assumed
  - System timer is generated by onboard CTC
  - Hardware auto-detected:
    - Onboard DS1302 RTC

Source/HBIOS/Config/ZETA2_std.asm

@@ -26,7 +26,7 @@
 ;
 #include "cfg_zeta2.asm"
 ;
-CPUOSC		.SET	20000000	; CPU OSC FREQ IN MHZ
+CPUOSC		.SET	8000000		; CPU OSC FREQ IN MHZ
 INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 CRTACT		.SET	TRUE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
@@ -35,7 +35,7 @@ UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 UARTSBC		.SET	TRUE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_ZETA	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_ZETA2	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
 ;
 PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
 SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)

Source/HBIOS/cfg_zeta2.asm

@@ -28,7 +28,7 @@ BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
 ;
 CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
-CPUOSC		.EQU	20000000	; CPU OSC FREQ IN MHZ
+CPUOSC		.EQU	8000000		; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;

Source/HBIOS/ctc.asm

@@ -147,18 +147,16 @@ CTCTIVT		.EQU	INT_CTC0A + CTCTIMCH
 ;==================================================================================================
 ;
 CTC_PREINIT:
+	; BLINDLY RESET THE CTC ASSUMING IT IS THERE
+	LD	A,CTC_DEFCFG
+	OUT	(CTCBASE),A
+	OUT	(CTCBASE+1),A
+	OUT	(CTCBASE+2),A
+	OUT	(CTCBASE+3),A
+;
 	CALL	CTC_DETECT		; DO WE HAVE ONE?
 	LD	(CTC_EXIST),A		; SAVE IT
 	RET	NZ			; ABORT IF NONE
-;
-	; RESET ALL CTC CHANNELS
-	LD	B,4			; 4 CHANNELS
-	LD	C,CTCBASE		; FIRST CHANNEL PORT
-CTC_PREINIT1:
-	LD	A,CTC_DEFCFG		; CTC DEFAULT CONFIG
-	OUT	(C),A			; CTC COMMAND
-	INC	C			; NEXT CHANNEL PORT
-	DJNZ	CTC_PREINIT1
 ;
 #IF (CTCTIMER & (INTMODE == 2))
 	; SETUP TIMER INTERRUPT IVT SLOT
@@ -258,32 +256,33 @@ CTC_PRTCFG1:
 	RET
 ;
 ;==================================================================================================
-; DETECT CTC BY CHECKING REGISTER CAN BE WRITTEN AND READ, AND THEN BY SETTING UP ONE CHANNEL IN 
-; TIMER MODE AND CHECKING IT IS COUNTING DOWN.
+; DETECT CTC BY PROGRAMMING THE FIRST CHANNEL TO COUNT IN TIMER
+; MODE (BASED ON CPU CLOCK).  THEN CHECK IF COUNTER IS ACTUALLY
+; RUNNING.
 ;==================================================================================================
 ;
 CTC_DETECT:
-	LD	A,CTC_TIM256CFG
-	OUT	(CTCBASE),A
-	XOR	A
-	OUT	(CTCBASE),A
-	; CTC SHOULD NOW BE RUNNING WITH TIME CONSTANT 0
-	LD	A,CTC_TIM256CFG		; RESET
-	OUT	(CTCBASE),A
-	IN	A,(CTCBASE)		; SHOULD READ 0 NOW
-	CP	0
-	JR	NZ,CTC_NO
+	LD	A,CTC_TIM16CFG		; RESET & SETUP TIMER MODE
+	OUT	(CTCBASE),A		; SEND TO CTC
 	LD	A,$FF			; TIME CONSTANT $FF
-	OUT	(CTCBASE),A
-	IN	A,(CTCBASE)		; SHOULD NOT BE 0 NOW
-	CP	0
-	JR	Z,CTC_NO
-	XOR	A
-	RET
+	OUT	(CTCBASE),A		; SEND CONSTANT & START CTR
+	NOP				; BRIEF DELAY
+	IN	A,(CTCBASE)		; READ COUNTER
+	LD	C,A			; SAVE VALUE
+	CALL	DLY8			; WAIT A BIT
+	IN	A,(CTCBASE)		; READ COUNTER AGAIN
+	PUSH	AF			; SAVE RESULT
+	LD	A,CTC_DEFCFG		; DEFAULT CHANNEL CFG
+	OUT	(CTCBASE),A		; RESTORE TO DEFAULTS
+	POP	AF			; GET RESULT BACK
+	CP	C			; COMPARE TO PREVIOUS
+	JR	Z,CTC_NO		; IF SAME, FAIL
+	XOR	A			; SIGNAL SUCCESS
+	RET				; AND DONE
 CTC_NO:
-	OR	$FF
-	RET
+	OR	$FF			; SIGNAL FAILURE
+	RET				; AND DONE
 ;
+; CTC DRIVER DATA STORAGE
 ;
-;
-CTC_EXIST	.DB	$FF	
+CTC_EXIST	.DB	$FF		; SET TO ZERO IF EXISTS

Source/HBIOS/dbgmon.asm

@@ -878,6 +878,8 @@ GETLNLOP:
 	JR	Z,GETLNDONE		; YES, EXIT
 	CP	CHR_BS			; IS <BS>?
 	JR	Z,GETLNBS		; IF SO, HANDLE IT
+	CP	CHR_DEL			; IS <DEL>?
+	JR	Z,GETLNBS		; IF SO, HANDLE AS <BS>
 	CP	' '			; UNEXPECTED CONTROL CHAR?
 	JR	C,GETLNLOP		; IF SO, IGNORE IT AND GET NEXT
 	LD	B,A			; SAVE CHAR IN B FOR NOW
@@ -1854,6 +1856,7 @@ CHR_CR		.EQU	0DH
 CHR_LF		.EQU	0AH
 CHR_BS		.EQU	08H
 CHR_ESC		.EQU	1BH
+CHR_DEL		.EQU	7FH
 ;
 ;__________________________________________________________________________________________________
 ;

Source/HBIOS/hbios.asm

@@ -1898,8 +1898,8 @@ HB_CPU1:
 ;
 ; INIT OSCILLATOR SPEED FROM CONFIG
 ;
-	LD	HL,CPUOSC / 1000
-	LD	(HB_CPUOSC),HL
+	LD	HL,CPUOSC / 1000	; OSC SPD IN KHZ
+	LD	(HB_CPUOSC),HL		; INIT HB_CPUOSC DEFAULT
 ;
 ; ATTEMPT DYNAMIC CPU SPEED DERIVATION
 ; NOTE THAT FOR PLATFORMS WITH SOFTWARE SELECTABLE CPU SPEED,
@@ -1907,8 +1907,8 @@ HB_CPU1:
 ; POSSIBLE SETTING.  THE FINAL CPU SPEED WILL BE ADJUSTED
 ; LATER.
 ;
-	CALL	HB_CPUSPD		; CPU SPEED DETECTION
-	JR	NZ,HB_CPUSPD2		; SKIP IF FAILED
+	CALL	HB_CPUSPD		; DYNAMIC CPU SPEED DETECTION
+	JR	NZ,HB_CPUSPD2		; SKIP AHEAD IF FAILED
 ;
 ; RECORD THE UPDATED CPU OSCILLATOR SPEED
 ;
@@ -1917,8 +1917,9 @@ HB_CPU1:
 	; SO RECORD DOUBLE THE MEASURED VALUE
 	SLA	L
 	RL	H
-	LD	(HB_CPUOSC),HL
 #ENDIF
+;
+	LD	(HB_CPUOSC),HL		; RECORD MEASURED SPEED
 ;
 HB_CPUSPD2:
 ;

Source/HBIOS/romldr.asm

@@ -41,6 +41,7 @@ bel	.equ	7	; ASCII bell
 bs	.equ	8	; ASCII backspace
 lf	.equ	10	; ASCII linefeed
 cr	.equ	13	; ASCII carriage return
+del	.equ	127	; ASCII del/rubout
 ;
 cmdbuf	.equ	$80	; cmd buf is in second half of page zero
 cmdmax	.equ	60	; max cmd len (arbitrary), must be < bufsiz
@@ -1281,6 +1282,8 @@ rdln_nxt:
 	call	cin			; get a character
 	cp	bs			; backspace?
 	jr	z,rdln_bs		; handle it if so
+	cp	del			; del/rubout?
+	jr	z,rdln_bs		; handle as backspace
 	cp	cr			; return?
 	jr	z,rdln_cr		; handle it if so
 ;

Source/ver.inc

@@ -2,7 +2,7 @@
 #DEFINE	RMN	2
 #DEFINE	RUP	1
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.2.1-dev.0"
+#DEFINE BIOSVER	"3.2.1-dev.2"
 #define rmj	RMJ
 #define rmn	RMN
 #define rup	RUP

Source/ver.lib

@@ -3,5 +3,5 @@ rmn	equ	2
 rup	equ	1
 rtp	equ	0
 biosver	macro
-	db	"3.2.1-dev.0"
+	db	"3.2.1-dev.2"
 	endm