Fix S100 Z180 Board LED Operation

- Status LED for S100 Z180 board was not enabled.  Credit to Jay Cotton for finding this.

Binary/ReadMe.txt

@@ -39,8 +39,8 @@ image for the Mark IV with the standard configuration. If a custom
 configuration called "custom" is created and built, a new file called 
 MK4_custom.rom will be added to this directory.
 
-Documentation of the pre-built ROM Images is contained in the 
-RomList.txt file in this directory.
+Documentation of the pre-built ROM Images is contained in
+"RomWBW User Guide.pdf" in the Doc directory.
 
 ROM Firmware Update Images (<plt>_<cfg>.upd)
 -------------------------------------

Doc/ChangeLog.txt

@@ -15,6 +15,10 @@ Version 3.3
 - JBL: Added RCZ80 configuration for ColecoVision
 - WBW: Support for Z180 running interrupt mode 1
 - WBW: Preliminary support for S100 Computers Z180
+- WBW: Preliminary support for Dan Werner's ESP32 MBC Module
+- WBW: Early support for Duodyne base system (CPU/UART/ROM/RAM/RTC/SPK)
+- M?C: Fixed XM to allow specifying HBIOS port for send operations
+- WBW: Fix S100 Z180 LED operation (credit to Jay Cotton for finding this issue)
 
 Version 3.2.1
 -------------

ReadMe.md

@@ -3,7 +3,7 @@
 **RomWBW ReadMe** \
 Version 3.3 \
 Wayne Warthen  ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \
-07 Jul 2023
+08 Aug 2023
 
 # Overview
 

ReadMe.txt

@@ -1,6 +1,6 @@
 RomWBW ReadMe
 Wayne Warthen (wwarthen@gmail.com)
-07 Jul 2023
+08 Aug 2023
 
 
 

Source/Apps/Test/I2C/i2cscan.asm

@@ -5,12 +5,13 @@
 ; MARCO MACCAFERRI, HTTPS://WWW.MACCASOFT.COM
 ; HBIOS VERSION BY PHIL SUMMERS (B1ACKMAILER) DIFFICULTLEVELHIGH@GMAIL.COM
 ;
-PCF	.EQU	1
-P8X180	.EQU	0
-SC126	.EQU	0
-SC137	.EQU	0
+PCFECB		.EQU	0
+PCFDUO		.EQU	1
+P8X180		.EQU	0
+SC126		.EQU	0
+SC137		.EQU	0
 ;
-#IF (PCF)
+#IF (PCFECB)
 I2C_BASE 	.EQU  	0F0H
 PCF_ID   	.EQU  	0AAH
 CPU_CLK	 	.EQU  	12
@@ -20,6 +21,16 @@ PCF_RS1  	.EQU  	PCF_RS0+1
 PCF_OWN	 	.EQU  	(PCF_ID >> 1)        	; PCF'S ADDRESS IN SLAVE MODE
 #ENDIF
 ;
+#IF (PCFDUO)
+I2C_BASE 	.EQU  	056H
+PCF_ID   	.EQU  	0AAH
+CPU_CLK	 	.EQU  	12
+;
+PCF_RS0  	.EQU  	I2C_BASE
+PCF_RS1  	.EQU  	PCF_RS0+1
+PCF_OWN	 	.EQU  	(PCF_ID >> 1)        	; PCF'S ADDRESS IN SLAVE MODE
+#ENDIF
+;
 #IF (P8X180)
 I2C_BASE	.EQU	0A0h
 _sda		.EQU	0
@@ -153,8 +164,11 @@ lp5f:	ld	a,(addr)	; next address
 	jp	0
 
 signon:	.db	"I2C Bus Scanner"
-#IF (PCF)
-	.DB	" - PCF8584"
+#IF (PCFECB)
+	.DB	" - PCF8584 (ECB)"
+#ENDIF
+#IF (PCFDUO)
+	.DB	" - PCF8584 (Duodyne)"
 #ENDIF
 #IF (SC126)
 	.DB	" - SC126"
@@ -219,7 +233,7 @@ _cout:				; character
 	ret
 
 ;-----------------------------------------------------------------------------
-#IF (PCF)
+#IF (PCFECB | PCFDUO)
 _i2c_start:
 PCF_START:
         LD     A,PCF_START_  
@@ -418,7 +432,7 @@ PCF_PINFAIL 	.DB	"PIN FAIL$"
 PCF_BBFAIL	.DB	"BUS BUSY$"
 ;
 ;-----------------------------------------------------------------------------
-#IF (PCF)
+#IF (PCFECB | PCFDUO)
 _i2c_stop:  
 PCF_STOP: 
 	LD   	A,PCF_STOP_	; issue 

Source/Apps/XM/xmdm125.asm

@@ -720,12 +720,17 @@ NOBYE:	LXI	H,FCB+1		; Get primary option
 ; Send option processor
 ; Single option: "K"	- force 1k mode
 ;
-	INX	H		; Look for a 'K'
+	CALL	SNDOPC
+	CALL	SNDOPC
+	JMP	ALLSET
+SNDOPC:INX	H		; Look for an option
 	MOV	A,M
 	CPI	' '		; Is it a space?
-	JZ	ALLSET		; Then we're ready to send...
-	CPI	'K'
-	JNZ	OPTERR		; "K" is the only setable 2nd option
+	JNZ	CHKK
+	POP	PSW
+	JMP	ALLSET
+CHKK:	CPI	'K'
+	JNZ	CHK6TH		; If it's not K it should be a port number
 	LDA	MSPEED
 	CPI	MINKSP		; If less than MINKSP bps, ignore 1k
 	JC	ALLSET		; Request
@@ -733,7 +738,7 @@ NOBYE:	LXI	H,FCB+1		; Get primary option
 	STA	KFLAG		; First, force us to 1K mode
 	CALL	ILPRT
 	DB	'(1k protocol selected)',CR,LF,0
-	JMP	ALLSET		; That's it for send...
+	RET		; That's it for send...
 ;
 ; Receive option processor
 ; 3 or 4 options: "X"	- disable auto-protocol select
@@ -5789,4 +5794,4 @@ BDPTOS	EQU	83		; Print Time on System
 	 ENDIF			; BYEBDOS
 ;
 	END
-
+

Source/Apps/rtc.asm

@@ -51,7 +51,7 @@ PORT_DYNO	.EQU	$0C		; RTC port for DYNO
 PORT_RCZ280	.EQU	$C0		; RTC port for RCZ280
 PORT_MBC	.EQU	$70		; RTC port for MBC
 PORT_RPH	.EQU	$84		; RTC port for RHYOPHYRE
-PORT_DUO	.EQU	$70		; RTC port for DUODYNE
+PORT_DUO	.EQU	$94		; RTC port for DUODYNE
 
 
 BDOS		.EQU	5		; BDOS invocation vector
@@ -1140,7 +1140,7 @@ HINIT:
 ;
 	LD	C,PORT_DUO
 	LD	DE,PLT_DUO
-	CP	13		; DUODYNE
+	CP	17		; DUODYNE
 	JP	Z,RTC_INIT2
 ;
 	; Unknown platform

Source/Doc/UserGuide.md

@@ -2308,26 +2308,35 @@ This application understands both FAT filesystems as well as CP/M filesystems.
 * Long filenames are not supported.  Files with long filenames will
   show up with their names truncated into the older 8.3 convention.
 * A FAT filesystem can be located on floppy or hard disk media.  For
-  hard disk media, the FAT filesystem must be located within a valid
-  FAT partition.
+  hard disk media, a valid FAT Filesystem partition must exist.
+* Note that CP/M (and compatible) OSes do not support all of the
+  filename characters that a modern computer does.  The following
+  characters are **not permitted** in a CP/M filename:
+
+  `< > . , ; : = ? * [ ] _ % | ( ) / \`
   
+  The FAT application does not auto-rename files when it encounters
+  invalid filenames.  It will just issue an error and quit.
+  Additionally, the error message is not very clear about the problem.
+
 ## FAT Filesystem Preparation
 
 In general, you can create media formatted with a FAT filesystem on
 your RomWBW computer or on your modern computer.  We will only be
 discussing the RomWBW-based approach here.
 
-In the case of a floppy disk, you can use the `FAT` application to
-format the floppy disk.  For example, if your floppy disk is on RomWBW
-disk unit 2, you could use `FAT FORMAT 2:`.  This will overwrite the
-floppy with a FAT filesystem and all previous contents will be lost.
-Once formatted this way, the floppy disk can be used in a floppy drive
-attached to a modern computer or it can be used on RomWBW using the
+In the case of a floppy disk, you can use the `FAT` application to 
+format the floppy disk.  The floppy disk must already be physically 
+formatted using RomWBW FDU or equivalent.  If your floppy disk is on 
+RomWBW disk unit 2, you could use `FAT FORMAT 2:`.  This will overwrite 
+the floppy with a FAT filesystem and all previous contents will be lost.
+Once formatted this way, the floppy disk can be used in a floppy drive 
+attached to a modern computer or it can be used on RomWBW using the 
 other `FAT` tool commands.
 
 In the case of hard disk media, it is necessary to have a FAT
 partition.  If you prepared your RomWBW hard disk media using the
-disk image process, then this partition will already be present and
+disk image process, then this partition will already be defined and
 you do not need to recreate it.  This default FAT partition is located
 at approximately 512MB from the start of your disk and it is 384MB in
 size.  So, your hard disk media must be 1GB or greater to use this
@@ -2375,8 +2384,13 @@ If your RomWBW system has multiple disk drives/slots, you can also just
 create a disk with your modern computer that is a dedicated FAT 
 filesystem disk.  You can use your modern computer to format the disk 
 (floppy, CF Card, SD Card, etc.), then insert the disk in your RomWBW 
-computer and access if using `FAT` based on its RomWBW unit number.
+computer and access it using `FAT` based on its RomWBW unit number.
 
+**WARNING**: Microsoft Windows will sometimes suggest reformatting
+partitions that it does not recognize.  If you are prompted to format
+a partition of your SD/CF Card when inserting the card into a Windows
+computer, you probably want to select Cancel.
+  
 ## FAT Application Usage
 
 Complete instructions for the `FAT` application are found in $doc_apps$.
@@ -3953,26 +3967,15 @@ the RomWBW HBIOS configuration.
 |-------------------|---------------|
 | ROM Image File    | DUO_std.rom   |
 | Console Baud Rate | 38400         |
-| Interrupts        | None          |
+| Interrupts        | Mode 2        |
 
  - CPU speed is detected at startup if DS1302 RTC is active
    - Otherwise 8.000 MHz assumed
  - System timer is generated by CTC if available
  - Hardware auto-detected:
    - DS1302 RTC
-   - Zilog CTC
    - Zilog DMA Module
    - UART Serial Adapter
-   - SIO Serial Interface
-   - LPT Printer Interface
-   - Zilog Parallel Interface
-   - CVDU Display Adapter
-   - TMS9938/58 Display Adapter
-   - PS/2 Keyboard Interface
-   - AY-3-8910/YM2149 Sound Module
-   - Floppy Disk Controller w/ 3.5" HD Drives
-   - PPIDE Hard Disk Interface
- - Interrupts may be enabled in build options
 
 `\clearpage`{=latex}
 

Source/HBIOS/Config/DUO_std.asm

@@ -29,30 +29,18 @@
 CPUOSC		.SET	8000000		; CPU OSC FREQ IN MHZ
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
-INTMODE		.SET	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 ;
-DMAENABLE	.SET	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+;;;DMAENABLE	.SET	TRUE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 ;
-BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
-;
-CPUSPDDEF	.SET	SPD_LOW		; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+BATCOND		.SET	TRUE		; ENABLE LOW BATTERY WARNING MESSAGE
 ;
 ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
 RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ;
-MDFFENABLE	.SET	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+PCFENABLE	.SET	TRUE		; ENABLE PCF8584 I2C CONTROLLER
 ;
-DSKYENABLE	.SET	TRUE		; ENABLES DSKY FUNCTIONALITY
-ICMENABLE	.SET	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
-PKDENABLE	.SET	TRUE		; ENABLES DSKY NG PKD DRIVER (8259)
+MDFFENABLE	.SET	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
 UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 ;UARTCFG	.SET	UARTCFG | SER_RTS
-;
-LPTENABLE	.SET	TRUE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
-;
-CVDUMON		.SET	CVDUMON_CGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
-;
-FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-;
-PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)

Source/HBIOS/Config/MBC_std.asm

@@ -49,6 +49,8 @@ PKDENABLE	.SET	TRUE		; ENABLES DSKY NG PKD DRIVER (8259)
 UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 ;UARTCFG	.SET	UARTCFG | SER_RTS
 ;
+ESPENABLE	.SET	TRUE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 LPTENABLE	.SET	TRUE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
 ;
 CVDUMON		.SET	CVDUMON_CGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]

Source/HBIOS/Config/RCZ280_zz80mb.asm

@@ -28,7 +28,7 @@
 ;
 #include "cfg_rcz280.asm"
 ;
-CPUOSC		.SET	12000000	; CPU OSC FREQ IN MHZ
+CPUOSC		.SET	24000000	; CPU OSC FREQ IN MHZ
 INTMODE		.SET	3		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;

Source/HBIOS/ROM Layout.txt

@@ -1,4 +1,4 @@
-RomWBW ROM Layout Notes
+RomWBW ROM Layout
 
 Bank		Module		Start	Size
 ------		------		------	------		
@@ -24,4 +24,16 @@ Bank		Module		Start	Size
 3		imgpad2		0x0000	0x8000
 		<end>		0x8000
 
-4-N		ROM Disk Data
+4 - N		ROM Disk Data
+
+
+RomWBW RAM Layout
+
+Bank ID         Usage                   Physical Address
+-------         ------                  ----------------
+0x80-0x87       RAM Disk Data           0x80000-0xBFFFF
+0x88-0x8B       CP/M 3 Buffers          0xC0000-0xDFFFF
+0x8C            CP/M 3 OS               0xE0000-0xE7FFF
+0x8D            RomWBW HBIOS            0xE8000-0xEFFFF
+0x8E            User TPA                0xF0000-0xF7FFF
+0x8F            Common                  0xF8000-0xFFFFF

Source/HBIOS/cfg_duo.asm

@@ -26,28 +26,28 @@ TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
 BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
 BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
 ;
-CPUSPDCAP	.EQU	SPD_HILO	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
-CPUSPDDEF	.EQU	SPD_LOW		; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.EQU	SPD_UNSUP	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	8000000		; CPU OSC FREQ IN MHZ
-INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
 MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
-MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
-MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
+MPGSEL_0	.EQU	$50		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_1	.EQU	$51		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_2	.EQU	$52		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_3	.EQU	$53		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
+MPGENA		.EQU	$54		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ;
-RTCIO		.EQU	$70		; RTC LATCH REGISTER ADR
+RTCIO		.EQU	$94		; RTC LATCH REGISTER ADR
 ;
 KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
 KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
 ;
-CTCENABLE	.EQU	TRUE		; ENABLE ZILOG CTC SUPPORT
+CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
 CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$B0		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	TRUE		; ENABLE CTC PERIODIC TIMER
@@ -57,6 +57,9 @@ CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	(4915200/8)	; CTC CLOCK FREQUENCY
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$56		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -65,7 +68,7 @@ WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
 FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
 FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
-FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPLED_DSKACT	.EQU	FALSE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
 FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
 FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
 ;
@@ -123,13 +126,14 @@ UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
 UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
-UARTDUAL	.EQU	TRUE		; UART: AUTO-DETECT DUAL UART
+UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+UARTDUO		.EQU	TRUE		; UART: AUTO-DETECT DUODYNE UART
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
@@ -137,7 +141,7 @@ Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 ;
 ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ;
-SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
@@ -154,11 +158,11 @@ XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 VDUSIZ		.EQU	V80X25		; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
-CVDUENABLE	.EQU	TRUE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 CVDUMODE	.EQU	CVDUMODE_MBC	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
 CVDUMON		.EQU	CVDUMON_CGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
 GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
-TMSENABLE	.EQU	TRUE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
 TMSMODE		.EQU	TMSMODE_MBC	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
@@ -232,10 +236,12 @@ PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 HDSKTRACE	.EQU	1		; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 ;
-PIOENABLE	.EQU	TRUE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
 PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
 PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
 PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
@@ -289,10 +295,9 @@ AYMODE		.EQU	AYMODE_MBC	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|
 ;
 SPKENABLE	.EQU	TRUE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
-DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
-DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_MBC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAENABLE	.EQU	TRUE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.EQU	$40		; DMA: DMA BASE ADDRESS
+DMAMODE		.EQU	DMAMODE_DUO	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
 YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
 VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
-

Source/HBIOS/cfg_dyno.asm

@@ -60,6 +60,9 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -133,6 +136,7 @@ UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
 UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+UARTDUO		.EQU	FALSE		; UART: AUTO-DETECT DUODYNE UART
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
@@ -243,6 +247,8 @@ PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
@@ -277,7 +283,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
 YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
 VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)

Source/HBIOS/cfg_master.asm

@@ -87,6 +87,9 @@ CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	614400		; CTC CLOCK FREQUENCY
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -169,6 +172,7 @@ UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
 UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+UARTDUO		.EQU	FALSE		; UART: AUTO-DETECT DUODYNE UART
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
@@ -305,6 +309,9 @@ PPPSDENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
 PPPSDTRACE	.EQU	1		; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 PPPCONENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+ESPCONENABLE	.EQU	TRUE		; ESP: ENABLE ESP32 CONSOLE IO DRIVER VIDEO/KBD SUPPORT
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 HDSKTRACE	.EQU	1		; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 ;
@@ -364,7 +371,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
 YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
 VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)

Source/HBIOS/cfg_mbc.asm

@@ -54,6 +54,9 @@ CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	(4915200/8)	; CTC CLOCK FREQUENCY
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -127,6 +130,7 @@ UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
 UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	TRUE		; UART: AUTO-DETECT DUAL UART
+UARTDUO		.EQU	FALSE		; UART: AUTO-DETECT DUODYNE UART
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
@@ -229,6 +233,9 @@ PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+ESPCONENABLE	.EQU	TRUE		; ESP: ENABLE ESP32 CONSOLE IO DRIVER VIDEO/KBD SUPPORT
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 HDSKTRACE	.EQU	1		; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 ;
@@ -288,7 +295,7 @@ SPKENABLE	.EQU	TRUE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_MBC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_MBC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
 YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
 VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)

Source/HBIOS/cfg_mk4.asm

@@ -60,6 +60,9 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$B0		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -133,6 +136,7 @@ UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	TRUE		; UART: AUTO-DETECT 4UART UART
 UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+UARTDUO		.EQU	FALSE		; UART: AUTO-DETECT DUODYNE UART
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
@@ -243,6 +247,8 @@ PPPSDENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
 PPPSDTRACE	.EQU	1		; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 PPPCONENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
@@ -286,7 +292,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_ECB	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_ECB	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
 YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
 VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)

Source/HBIOS/cfg_n8.asm

@@ -62,6 +62,9 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$B0		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -135,6 +138,7 @@ UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	TRUE		; UART: AUTO-DETECT 4UART UART
 UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+UARTDUO		.EQU	FALSE		; UART: AUTO-DETECT DUODYNE UART
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
@@ -241,6 +245,8 @@ PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
@@ -279,7 +285,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
 YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
 VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)

Source/HBIOS/cfg_rcz180.asm

@@ -60,6 +60,9 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -139,6 +142,7 @@ UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
 UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+UARTDUO		.EQU	FALSE		; UART: AUTO-DETECT DUODYNE UART
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
@@ -249,6 +253,8 @@ PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
@@ -303,7 +309,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
 YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
 VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)

Source/HBIOS/cfg_rcz280.asm

@@ -60,6 +60,9 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -133,6 +136,7 @@ UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
 UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+UARTDUO		.EQU	FALSE		; UART: AUTO-DETECT DUODYNE UART
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
@@ -253,6 +257,8 @@ PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
@@ -307,7 +313,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z280	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_Z280	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
 YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
 VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)

Source/HBIOS/cfg_rcz80.asm

@@ -57,6 +57,9 @@ CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	CPUOSC		; CTC CLOCK FREQUENCY
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -132,6 +135,7 @@ UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
 UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+UARTDUO		.EQU	FALSE		; UART: AUTO-DETECT DUODYNE UART
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
@@ -247,6 +251,8 @@ PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
@@ -301,7 +307,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_RC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_RC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
 YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
 VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)

Source/HBIOS/cfg_rph.asm

@@ -60,6 +60,9 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$B0		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -133,6 +136,7 @@ UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
 UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+UARTDUO		.EQU	FALSE		; UART: AUTO-DETECT DUODYNE UART
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
@@ -230,6 +234,8 @@ PRPCONENABLE	.EQU	FALSE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
@@ -268,7 +274,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
 YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
 VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)

Source/HBIOS/cfg_s100.asm

@@ -60,6 +60,9 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -74,7 +77,7 @@ FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
 ;
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
-LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
+LEDENABLE	.EQU	TRUE		; ENABLES STATUS LED (SINGLE LED)
 LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|RTC]
 LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
 LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
@@ -133,6 +136,7 @@ UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
 UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+UARTDUO		.EQU	FALSE		; UART: AUTO-DETECT DUODYNE UART
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
@@ -243,6 +247,8 @@ PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
@@ -297,7 +303,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
 YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
 VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)

Source/HBIOS/cfg_sbc.asm

@@ -54,6 +54,9 @@ CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	614400		; CTC CLOCK FREQUENCY
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -127,6 +130,7 @@ UARTMFP		.EQU	TRUE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	TRUE		; UART: AUTO-DETECT 4UART UART
 UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+UARTDUO		.EQU	FALSE		; UART: AUTO-DETECT DUODYNE UART
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
@@ -228,6 +232,8 @@ PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 HDSKTRACE	.EQU	1		; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 ;
@@ -267,7 +273,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_ECB	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_ECB	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
 YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
 VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)

Source/HBIOS/cfg_scz180.asm

@@ -60,6 +60,9 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -133,6 +136,7 @@ UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
 UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+UARTDUO		.EQU	FALSE		; UART: AUTO-DETECT DUODYNE UART
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
@@ -243,6 +247,8 @@ PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
@@ -297,7 +303,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
 YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
 VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)

Source/HBIOS/cfg_z80retro.asm

@@ -57,6 +57,9 @@ CTCPRECH	.EQU	0		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	1		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	7372800		; CTC CLOCK FREQUENCY
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -125,6 +128,7 @@ UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
 UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+UARTDUO		.EQU	FALSE		; UART: AUTO-DETECT DUODYNE UART
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
@@ -203,6 +207,8 @@ PPPSDENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
 PPPSDTRACE	.EQU	1		; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 PPPCONENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
@@ -228,7 +234,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
 YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
 VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)

Source/HBIOS/cfg_zeta.asm

@@ -46,6 +46,9 @@ KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
 ;
 CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -114,6 +117,7 @@ UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
 UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+UARTDUO		.EQU	FALSE		; UART: AUTO-DETECT DUODYNE UART
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
@@ -174,6 +178,8 @@ PPPSDENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
 PPPSDTRACE	.EQU	1		; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 PPPCONENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
@@ -199,7 +205,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
 YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
 VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)

Source/HBIOS/cfg_zeta2.asm

@@ -57,6 +57,9 @@ CTCPRECH	.EQU	0		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	1		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	921600		; CTC CLOCK FREQUENCY
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -125,6 +128,7 @@ UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
 UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+UARTDUO		.EQU	FALSE		; UART: AUTO-DETECT DUODYNE UART
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
@@ -185,6 +189,8 @@ PPPSDENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
 PPPSDTRACE	.EQU	1		; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 PPPCONENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
@@ -210,7 +216,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
 YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
 VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)

Source/HBIOS/dma.asm

@@ -2,6 +2,18 @@
 ; Z80 DMA DRIVER
 ;==================================================================================================
 ;
+#IF ((DMAMODE == DMAMODE_ECB) | (DMAMODE == DMAMODE_MBC))
+DMA_IO		.EQU	DMABASE
+DMA_CTL		.EQU	DMABASE + 1
+DMA_USEHALF	.EQU	TRUE
+#ENDIF
+;
+#IF (DMAMODE == DMAMODE_DUO)
+DMA_IO		.EQU	DMABASE
+DMA_CTL		.EQU	DMABASE + 3
+DMA_USEHALF	.EQU	FALSE
+#ENDIF
+;
 DMA_CONTINUOUS			.equ 	%10111101	; + Pulse
 DMA_BYTE			.equ 	%10011101	; + Pulse
 DMA_BURST 			.equ	%11011101	; + Pulse
@@ -30,21 +42,18 @@ DMA_FORCE			.EQU	0
 ; DMA CLOCK SPEED CONTROL - OPTION TO SWITCH TO HALF CLOCK SPEED. MOST SYSTEMS NEED THIS.
 ;==================================================================================================
 ;
-DMA_USEHALF			.equ	TRUE	; USE CLOCK DIVIDER
-;
-#IF (DMA_USEHALF & (DMAMODE=DMAMODE_MBC))
-#DEFINE DMAIOHALF LD A,(HB_RTCVAL) \ AND ~%00001000 \ OUT (RTCIO),A
-#DEFINE DMAIOFULL PUSH AF \ LD A,(HB_RTCVAL) \ OUT (RTCIO),A \ POP AF
-#ENDIF
-;
-#IF (DMA_USEHALF & (DMAMODE=DMAMODE_ECB))
-#DEFINE DMAIOHALF LD A,(HB_RTCVAL) \ OR %00001000 \ OUT (RTCIO),A 
-#DEFINE DMAIOFULL PUSH AF \ LD A,(HB_RTCVAL) \ OUT (RTCIO),A \ POP AF
-#ENDIF
-;
-#IF (!DMA_USEHALF)
-#DEFINE DMAIOHALF \;
-#DEFINE DMAIOFULL \;
+#IF (DMA_USEHALF)
+  #IF (DMAMODE=DMAMODE_MBC)
+    #DEFINE DMAIOHALF LD A,(HB_RTCVAL) \ AND ~%00001000 \ OUT (RTCIO),A
+    #DEFINE DMAIOFULL PUSH AF \ LD A,(HB_RTCVAL) \ OUT (RTCIO),A \ POP AF
+  #ENDIF
+  #IF (DMAMODE=DMAMODE_ECB)
+    #DEFINE DMAIOHALF LD A,(HB_RTCVAL) \ OR %00001000 \ OUT (RTCIO),A 
+    #DEFINE DMAIOFULL PUSH AF \ LD A,(HB_RTCVAL) \ OUT (RTCIO),A \ POP AF
+  #ENDIF
+#ELSE
+  #DEFINE DMAIOHALF \;
+  #DEFINE DMAIOFULL \;
 #ENDIF
 ;
 ;==================================================================================================
@@ -54,11 +63,11 @@ DMA_USEHALF			.equ	TRUE	; USE CLOCK DIVIDER
 DMA_INIT:
 	CALL	NEWLINE
 	PRTS("DMA: IO=0x$")		; announce
-	LD	A, DMABASE
+	LD	A, DMA_IO
 	CALL	PRTHEXBYTE
 ;
 	LD	A,DMA_FORCE
-	out	(DMABASE+1),a		; force ready off
+	out	(DMA_CTL),a		; force ready off
 ;
 	DMAIOHALF
 ;
@@ -67,7 +76,7 @@ DMA_INIT:
 ;
 	ld	hl,DMACode		; program the
 	ld	b,DMACode_Len		; dma command
-	ld	c,DMABASE		; block
+	ld	c,DMA_IO		; block
 ;
 	di
 	otir				; load dma
@@ -103,31 +112,31 @@ DMA_FAIL_FLAG:
 ;==================================================================================================
 ;
 DMAProbe:
-	ld	a,DMA_RESET	
-	out	(DMABASE),a
-	ld	a,%01111101 		; R0-Transfer mode, A -> B, start address follows
-	out	(DMABASE),a
+	ld	a,DMA_RESET		; $C3
+	out	(DMA_IO),a
+	ld	a,%01111101 		; R0-Transfer mode, A -> B, start address follows $7D
+	out	(DMA_IO),a
 	ld	a,$cc
-	out	(DMABASE),a
+	out	(DMA_IO),a
 	ld	a,$dd
-	out	(DMABASE),a
+	out	(DMA_IO),a
 	ld	a,$e5
-	out	(DMABASE),a
+	out	(DMA_IO),a
 	ld	a,$1a
-	out	(DMABASE),a
-	ld	a,DMA_LOAD
-	out	(DMABASE),a
+	out	(DMA_IO),a
+	ld	a,DMA_LOAD		; $CF
+	out	(DMA_IO),a
 ;
-	ld	a,DMA_READ_MASK_FOLLOWS	; set up
-	out	(DMABASE),a		; for 
-	ld	a,%00011000		; register
-	out	(DMABASE),a		; read
-	ld	a,DMA_START_READ_SEQUENCE
-	out	(DMABASE),a
+	ld	a,DMA_READ_MASK_FOLLOWS	; set up ; $BB
+	out	(DMA_IO),a		; for 
+	ld	a,%00011000		; register $18
+	out	(DMA_IO),a		; read
+	ld	a,DMA_START_READ_SEQUENCE	; $A7
+	out	(DMA_IO),a
 ;
-	in	a,(DMABASE)		; read in 
+	in	a,(DMA_IO)		; read in 
 	ld	c,a			; address
-	in	a,(DMABASE)
+	in	a,(DMA_IO)
 	ld	b,a
 ;
 	xor	a			; is it
@@ -165,7 +174,7 @@ DMALDIR:
 ;
 	ld	hl,DMACopy		; program the
 	ld	b,DMACopy_Len		; dma command
-	ld	c,DMABASE		; block
+	ld	c,DMA_IO		; block
 ;
 	DMAIOHALF
 ;
@@ -174,8 +183,8 @@ DMALDIR:
 	ei
 ;
 	ld	a,DMA_READ_STATUS_BYTE	; check status
-	out	(DMABASE),a		; of transfer
-	in	a,(DMABASE)		; set non-zero
+	out	(DMA_IO),a		; of transfer
+	in	a,(DMA_IO)		; set non-zero
 	and	%00111011		; if failed
 	sub	%00011011
 
@@ -211,7 +220,7 @@ DMAOTIR:
 ;
 	ld	hl,DMAOutCode		; program the
 	ld	b,DMAOut_Len		; dma command
-	ld	c,DMABASE		; block
+	ld	c,DMA_IO		; block
 ;
 	DMAIOHALF
 
@@ -220,8 +229,8 @@ DMAOTIR:
 	ei
 ;
 	ld	a,DMA_READ_STATUS_BYTE	; check status
-	out	(DMABASE),a		; of transfer
-	in	a,(DMABASE)		; set non-zero
+	out	(DMA_IO),a		; of transfer
+	in	a,(DMA_IO)		; set non-zero
 	and	%00111011		; if failed
 	sub	%00011011
 ;
@@ -262,7 +271,7 @@ DMAINIR:
 ;
 	ld	hl,DMAInCode		; program the
 	ld	b,DMAIn_Len		; dma command
-	ld	c,DMABASE		; block
+	ld	c,DMA_IO		; block
 ;
 	DMAIOHALF
 ;
@@ -271,8 +280,8 @@ DMAINIR:
 	ei
 ;
 	ld	a,DMA_READ_STATUS_BYTE	; check status
-	out	(DMABASE),a		; of transfer
-	in	a,(DMABASE)		; set non-zero
+	out	(DMA_IO),a		; of transfer
+	in	a,(DMA_IO)		; set non-zero
 	and	%00111011		; if failed
 	sub	%00011011
 ;
@@ -306,31 +315,31 @@ DMAIn_Len 	.equ	$-DMAInCode
 ;
 DMARegDump:
 	ld	a,DMA_READ_MASK_FOLLOWS
-	out	(DMABASE),a
+	out	(DMA_IO),a
 	ld	a,%01111110
-	out	(DMABASE),a
+	out	(DMA_IO),a
 	ld	a,DMA_START_READ_SEQUENCE
-	out	(DMABASE),a
+	out	(DMA_IO),a
 ;
-	in	a,(DMABASE)
+	in	a,(DMA_IO)
 	ld	c,a
-	in	a,(DMABASE)
+	in	a,(DMA_IO)
 	ld	b,a
 	call	PRTHEXWORD
 	ld	a,':'
 	call	COUT
 ;
-	in	a,(DMABASE)
+	in	a,(DMA_IO)
 	ld	c,a
-	in	a,(DMABASE)
+	in	a,(DMA_IO)
 	ld	b,a
 	call	PRTHEXWORD
 	ld	a,':'
 	call	COUT
 ;
-	in	a,(DMABASE)
+	in	a,(DMA_IO)
 	ld	c,a
-	in	a,(DMABASE)
+	in	a,(DMA_IO)
 	ld	b,a
 	call	PRTHEXWORD
 ;

Source/HBIOS/ds7rtc.asm

@@ -5,6 +5,11 @@
 ;
 ;==================================================================================================
 ;
+#IF (!PCFENABLE)
+	.ECHO	"*** DS7 DRIVER REQUIRES PCF DRIVER.  SET PCFENABLE!!!\n"
+	!!!	; FORCE AN ASSEMBLY ERROR
+#ENDIF
+;
 DS7_OUT		.EQU	10000000B		; SELECT SQUARE WAVE FUNCTION
 DS7_SQWE	.EQU	00010000B		; ENABLE SQUARE WAVE OUTPUT
 DS7_RATE	.EQU	00000000B		; SET 1HZ OUPUT
@@ -31,6 +36,7 @@ DS7_CTL		.EQU	(DS7_OUT | DS7_SQWE | DS7_RATE)
 ; 12HR MODE IS CURRENTLY ASSUMED
 ;
 DS7RTC_INIT:
+	CALL	NEWLINE			; Formatting
 	PRTS("DS1307: $")		; ANNOUNCE DRIVER
 ;
 	LD	A,(PCF_FAIL_FLAG)	; CHECK IF THE

Source/HBIOS/esp.asm

@@ -0,0 +1,314 @@
+;
+;==================================================================================================
+; ESP32 DRIVER
+;
+; SUPPORTS DAN WERNER'S NHYODYNE (MBC) ESP32 MODULE
+; https://github.com/danwerner21/nhyodyne/tree/main/Z80ESP
+;==================================================================================================
+;
+; TODO:
+;
+ESP_IOBASE	.EQU	$9C
+ESP_0_IO	.EQU	ESP_IOBASE + 0
+ESP_1_IO	.EQU	ESP_IOBASE + 1
+ESP_STAT	.EQU	ESP_IOBASE + 2
+;
+; ESP  STATUS PORT
+; MSB XX S S S S S S
+;        | | | | | +- ESP0 READY OUTPUT
+;        | | | | +--- ESP0 BUSY
+;        | | | +----- ESP0 SPARE
+;        | | +------- ESP1 READY OUTPUT
+;        | +--------- ESP1 BUSY
+;        +----------- ESP1 SPARE
+;
+ESP_0_RDY	.EQU	%00000001
+ESP_0_BUSY	.EQU	%00000010
+ESP_0_SPARE	.EQU	%00000100
+ESP_1_RDY	.EQU	%00001000
+ESP_1_BUSY	.EQU	%00010000
+ESP_1_SPARE	.EQU	%00100000
+;
+; COMMAND OPCODES
+;
+ESP_CMD_NOP	.EQU	0		; NO OP
+ESP_CMD_COUT	.EQU	1		; CHAR OUT
+ESP_CMD_SOUT	.EQU	2		; STRING OUT
+ESP_CMD_KIN	.EQU	3		; KEY IN
+ESP_CMD_KST	.EQU	4		; KBD BUF STATUS
+ESP_CMD_DISC	.EQU	$FF		; DISCOVER
+;
+; GLOBAL ESP INITIALIZATION
+;
+ESP_INIT:
+;
+	CALL	NEWLINE			; FORMATTING
+	PRTS("ESP: IO=0x$")
+	LD	A,ESP_IOBASE
+	CALL	PRTHEXBYTE
+;
+	CALL	ESP_DETECT
+	LD	DE,ESP_STR_NOHW
+	JP	NZ,WRITESTR
+;
+	; PRINT FIRMWARE VERSION
+	PRTS(" F/W=$")
+	CALL	ESP_PRTVER
+;
+	CALL	ESPCON_INIT		; CONSOLE INITIALIZATION
+;
+	RET
+;
+;==================================================================================================
+; ESP32 INTERFACE FUNCTIONS
+;==================================================================================================
+;
+ESP_DETECT:
+	CALL	ESP_CLR			; CLEAR ANY PENDING DATA
+	RET	NZ			; IF FAILS, ASSUME NOT PRESENT
+	LD	A,ESP_CMD_DISC		; DISCOVER COMMAND
+	CALL	ESP_OUT			; SEND IT
+;
+	; LOOK FOR SIGNATURE STARTING WITH "ESP"
+	CALL	ESP_INWAIT		; ATTEMPT TO GET CHAR
+	;CALL	PRTHEXBYTE
+	CP	'E'
+	RET	NZ
+	CALL	ESP_INWAIT		; ATTEMPT TO GET CHAR
+	;CALL	PRTHEXBYTE
+	CP	'S'
+	RET	NZ
+	CALL	ESP_INWAIT		; ATTEMPT TO GET CHAR
+	;CALL	PRTHEXBYTE
+	CP	'P'
+	RET
+
+	;LD	DE,10			; DELAY 160US
+	;CALL	VDELAY			; ... TO ENSURE OUTPUT RDY SET
+	;IN	A,(ESP_STAT)		; GET STATUS
+	;AND	ESP_0_RDY		; ISOLATE OUTPUT READY BIT
+	;XOR	ESP_0_RDY		; INVERT SO 0=FOUND
+	;RET				; DONE
+;
+; CLEAR ESP INPUT QUEUE
+;
+ESP_CLR:
+	LD	B,0			; MAX CHARS TO READ
+ESP_CLR0:
+	CALL	ESP_WTNBSY		; WAIT TILL NOT BUSY
+	RET	NZ			; BAIL OUT IF TIMEOUT
+	IN	A,(ESP_STAT)		; GET STATUS
+	AND	ESP_0_RDY		; IS THERE MORE DATA?
+	RET	Z			; IF NOT, DONE
+	IN	A,(ESP_0_IO)		; GET CHAR
+	DJNZ	ESP_CLR0		; LOOP TILL DONE
+	OR	$FF			; SIGNAL FAILURE
+	RET
+;
+; PRINT ESP VERSION STRING TO CONSOLE
+;
+ESP_PRTVER:
+	CALL	ESP_CLR			; CLEAR ANY PENDING DATA
+	LD	A,ESP_CMD_DISC		; DISCOVER COMMAND
+	CALL	ESP_OUT			; SEND IT
+	CALL	ESP_WTRDY		; WAIT FOR READY TO OUTPUT
+ESP_PRTVER1:
+	CALL	ESP_WTNBSY		; WAIT TILL NOT BUSY
+	IN	A,(ESP_STAT)		; GET STATUS
+	AND	ESP_0_RDY		; ISOLATE OUTPUT READY BIT
+	RET	Z			; DONE IF NOTHING READY
+	CALL	ESP_IN			; GET NEXT CHAR
+	CALL	COUT			; PRINT CHAR
+	JR	ESP_PRTVER1		; LOOP
+;
+; SEND BYTE TO ESP
+;
+ESP_OUT:
+	PUSH	AF			; SAVE VALUE
+	CALL	ESP_WTNBSY		; WAIT TILL NOT BUSY
+	POP	AF			; POP VALUE
+	OUT	(ESP_0_IO),A		; SEND CHARACTER
+	JR	ESP_WTBSY		; RETURN VIA WTBSY
+;
+; GET BYTE FROM ESP (BLOCKING)
+;
+ESP_INWAIT:
+	CALL	ESP_WTNBSY		; WAIT TILL NOT BUSY
+	CALL	ESP_WTRDY		; WAIT FOR READY TO OUTPUT
+	; FALL THRU (GET CHAR VIA ESP_IN)
+;
+; GET BYTE FROM ESP (NON BLOCKING)
+;
+ESP_IN:
+	CALL	ESP_WTNBSY		; WAIT TILL NOT BUSY
+ESP_IN1:	
+	IN	A,(ESP_0_IO)		; GET BYTE
+	PUSH	AF			; SAVE VALUE
+	CALL	ESP_WTBSY		; WAIT TILL BUSY
+	POP	AF			; RESTORE VALUE
+	RET				; AND RETURN
+;
+; WAIT FOR ESP TO BE NOT BUSY
+;
+ESP_WTNBSY:
+	LD	B,0			; MAX TRIES
+ESP_WTNBSY1:	
+	IN	A,(ESP_STAT)		; GET STATUS
+	AND	ESP_0_BUSY		; IS ESP BUSY?
+	RET	Z			; RETURN IF NOT BUSY
+	DJNZ	ESP_WTNBSY1		; ELSE LOOP
+	OR	$FF			; SIGNAL TIMEOUT
+	RET				; AND RETURN
+;
+; WAIT FOR ESP TO BE BUSY
+;
+ESP_WTBSY:
+	LD	B,20			; MAX TRIES
+ESP_WTBSY1:	
+	IN	A,(ESP_STAT)		; GET STATUS
+	AND	ESP_0_BUSY		; IS ESP BUSY?
+	XOR	ESP_0_BUSY		; INVERT
+	RET	Z			; RETURN IF BUSY
+	DJNZ	ESP_WTBSY1		; ELSE LOOP
+	OR	$FF			; SIGNAL TIMEOUT
+	RET				; AND RETURN
+;
+; WAIT FOR ESP TO BE READY TO OUTPUT
+;
+ESP_WTRDY:
+	LD	B,0			; MAX TRIES
+ESP_WTRDY1:
+	IN	A,(ESP_STAT)		; GET STATUS
+	AND	ESP_0_RDY		; IS ESP READY TO OUTPUT
+	XOR	ESP_0_RDY		; INVERT, 0=READY
+	RET	Z			; RETURN IF READY
+	DJNZ	ESP_WTRDY1		; ELSE LOOP
+	OR	$FF			; SIGNAL TIMEOUT
+	RET				; AND RETURN
+;
+;
+;
+ESP_STR_NOHW		.TEXT	" NOT PRESENT$"
+ESP_STR_UPGRADE		.TEXT	" !!!UPGRADE REQUIRED!!!$"
+;
+;==================================================================================================
+; ESP32 CONSOLE DRIVER
+;==================================================================================================
+;
+;
+ESPCON_ROWS	.EQU	25		; VGA DISPLAY ROWS
+ESPCON_COLS	.EQU	80		; VGA DISPLAY COLS
+;
+;
+;
+ESPCON_INIT:
+;
+	CALL	NEWLINE
+	PRTS("ESPCON:$")
+;
+	; DISPLAY CONSOLE DIMENSIONS
+	CALL	PC_SPACE
+	LD	A,ESPCON_COLS
+	CALL	PRTDECB
+	LD	A,'X'
+	CALL	COUT
+	LD	A,ESPCON_ROWS
+	CALL	PRTDECB
+	CALL	PRTSTRD
+	.TEXT	" TEXT (ANSI)$"
+;
+; ADD OURSELVES TO CIO DISPATCH TABLE
+;
+	LD	D,0			; PHYSICAL UNIT IS ZERO
+	LD	E,CIODEV_ESPCON		; DEVICE TYPE
+	LD	BC,ESPCON_FNTBL		; BC := FUNCTION TABLE ADDRESS
+	CALL	CIO_ADDENT		; ADD ENTRY, A := UNIT ASSIGNED
+	LD	(HCB + HCB_CRTDEV),A	; SET OURSELVES AS THE CRT DEVICE
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; DRIVER FUNCTION TABLE
+;
+ESPCON_FNTBL:
+	.DW	ESPCON_IN
+	.DW	ESPCON_OUT
+	.DW	ESPCON_IST
+	.DW	ESPCON_OST
+	.DW	ESPCON_INITDEV
+	.DW	ESPCON_QUERY
+	.DW	ESPCON_DEVICE
+#IF (($ - ESPCON_FNTBL) != (CIO_FNCNT * 2))
+	.ECHO	"*** INVALID ESPCON FUNCTION TABLE ***\n"
+#ENDIF
+;
+;
+;
+ESPCON_IN:
+	CALL	ESPCON_IST
+	JR	Z,ESPCON_IN
+	LD	A,ESP_CMD_KIN		; KBD INPUT
+	CALL	ESP_OUT			; SEND CMD OPCODE
+	CALL	ESP_INWAIT		; GET KEY
+	LD	E,A			; PUT IN E
+	XOR	A			; SIGNAL SUCCES
+	RET				; AND DONE
+;
+;
+;
+ESPCON_IST:
+	LD	A,ESP_CMD_KST		; KBD BUF STATUS
+	CALL	ESP_OUT			; SEND CMD OPCODE
+	CALL	ESP_INWAIT		; GET BUF SIZE
+	OR	A			; SET FLAGS
+	RET	Z			; AND DONE
+	OR	A
+	RET
+;
+;
+;
+ESPCON_OUT:
+	PUSH	DE
+	LD	A,ESP_CMD_COUT		; CHAR OUT OPCODE
+	CALL	ESP_OUT
+	POP	DE
+	LD	A,E
+	CALL	ESP_OUT			; SEND CHAR VALUE
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+;
+;
+ESPCON_OST:
+	OR	$FF			; SIGNAL OUTPUT QUEUE READY
+	RET				; RETURN
+;
+;
+;
+ESPCON_INITDEV:
+	SYSCHKERR(ERR_NOTIMPL)
+	RET
+;
+;
+;
+ESPCON_QUERY:
+	LD	DE,0
+	LD	HL,0
+	XOR	A
+	RET
+;
+;
+;
+ESPCON_DEVICE:
+	LD	D,CIODEV_ESPCON		; D := DEVICE TYPE
+	LD	E,0			; E := DEVICE NUM, ALWAYS 0
+	LD	C,$BF			; C := DEVICE TYPE, 0xBF IS PROP TERM
+	LD	H,0			; H := 0, DRIVER HAS NO MODES
+	LD	L,ESP_IOBASE		; L := BASE I/O ADDRESS
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+;=============================================================================
+; DATA STORAGE
+;=============================================================================
+;

Source/HBIOS/hbios.asm

@@ -105,44 +105,46 @@ MODCNT	.SET	MODCNT + 1
 ;
 ;
 #IF (FPLED_ENABLE)
-#DEFINE	DIAG(N)	PUSH AF
-  #DEFCONT \	LD A,N
-;  #DEFCONT \	OUT (DIAGPORT),A
-  #DEFCONT \	CALL	FP_SETLEDS
-  #DEFCONT \	POP AF
+  #DEFINE DIAG(N)	PUSH AF
+  #DEFCONT \		LD A,N
+;  #DEFCONT \		OUT (DIAGPORT),A
+  #DEFCONT \		CALL	FP_SETLEDS
+  #DEFCONT \		POP AF
 #ELSE
-#DEFINE	DIAG(N)	\;
+  #DEFINE		DIAG(N)	\;
 #ENDIF
 ;
 ; SCxxx: LED Port=0x0E, bit 2, inverted, dedicated port
 ; TinyZ80: LED Port=0x6E, bit 0, inverted, dedicated port
 ; Z80-512K: LED Port=0x6E, bit 0, inverted, dedicated port
 ; MBC: LED Port=0x70, bits 1-0, normal, shared w/ RTC port
+; DUO: LED Port=0x94, bits 1-0, normal, shared w/ RTC port
+; S100: LED Port = $0E, bit 2, inverted, dedicated port
 ; 
 #IF (LEDENABLE)
   #IF (LEDMODE == LEDMODE_STD)
-#DEFINE	LED(N)	PUSH	AF
-  #DEFCONT \	LD	A,~N
-  #DEFCONT \	OUT	(LEDPORT),A
-  #DEFCONT \	POP	AF
+    #DEFINE LED(N)	PUSH	AF
+    #DEFCONT \		LD	A,~N
+    #DEFCONT \		OUT	(LEDPORT),A
+    #DEFCONT \		POP	AF
   #ENDIF
   #IF (LEDMODE == LEDMODE_RTC)
-#DEFINE LED(N)	PUSH	AF
-  #DEFCONT \	LD	A,(HB_RTCVAL)
-  #DEFCONT \	AND	%11111100
-  #DEFCONT \	OR	(N & %00000011)
-  #DEFCONT \	LD	(HB_RTCVAL),A
-  #DEFCONT \	OUT	(LEDPORT),A
-  #DEFCONT \	POP	AF
+    #DEFINE LED(N)	PUSH	AF
+    #DEFCONT \		LD	A,(HB_RTCVAL)
+    #DEFCONT \		AND	%11111100
+    #DEFCONT \		OR	(N & %00000011)
+    #DEFCONT \		LD	(HB_RTCVAL),A
+    #DEFCONT \		OUT	(LEDPORT),A
+    #DEFCONT \		POP	AF
   #ENDIF
 #ELSE
-#DEFINE	LED(N)	\;
+  #DEFINE LED(N)	\;
 #ENDIF
 ;
 #DEFINE SYSCHKERR(HB_ERR) \
-  #DEFCONT \	CALL	SYSCHKA
-  #DEFCONT \	LD	A,HB_ERR
-  #DEFCONT \	OR	A
+#DEFCONT \	CALL	SYSCHKA
+#DEFCONT \	LD	A,HB_ERR
+#DEFCONT \	OR	A
 ;
 ;
 ;
@@ -465,7 +467,11 @@ HBX_ROM:
 	BIT	7,A			; BIT 7 SET REQUESTS RAM PAGE
 	JR	Z,HBX_ROM		; NOT SET, SELECT ROM PAGE
 	RES	7,A			; RAM PAGE REQUESTED: CLEAR ROM BIT
+  #IF (PLATFORM == PLT_DUO)
+	ADD	A,64			; ADD 64 x 32K - RAM STARTS FROM 2048K
+  #ELSE
 	ADD	A,16			; ADD 16 x 32K - RAM STARTS FROM 512K
+  #ENDIF
 ;
 HBX_ROM:
 	RLCA				; TIMES 2 - GET 16K PAGE INSTEAD OF 32K
@@ -1105,7 +1111,23 @@ Z280_BOOTERR	.TEXT	"\r\n\r\n*** Application mode boot not supported under Z280 n
 ;
 	DI				; NO INTERRUPTS
 	IM	1			; INTERRUPT MODE 1
-
+;
+#IF ((PLATFORM == PLT_DUO) & FALSE)
+	; WAIT A WHILE
+	LD	B,0
+	DJNZ	$
+#ENDIF
+;
+#IF ((PLATFORM == PLT_DUO) & TRUE)
+	; WAIT A WHILE
+	LD	HL,0
+BOOTWAIT:
+	DEC	HL
+	LD	A,H
+	OR	L
+	JR	NZ,BOOTWAIT
+#ENDIF
+;
 ;#IF ((PLATFORM == PLT_MBC) | (PLATFORM == PLT_SBC))
 	; INITIALIZE RTC LATCH BYTE
 	; FOR SOME PLATFORMS THIS CONTROLS HI/LO SPEED CIRCUIT
@@ -1310,7 +1332,13 @@ Z280_INITZ:
 	INC	A
 	OUT	(MPGSEL_1),A
   #ENDIF
-	LD	A,62
+;
+  #IF (PLATFORM == PLT_DUO)
+	LD	A,128 + (RAMSIZE / 16) - 2
+  #ELSE
+	LD	A,64 - 2
+  #ENDIF
+;
 	OUT	(MPGSEL_2),A
 	INC	A
 	OUT	(MPGSEL_3),A
@@ -2772,6 +2800,7 @@ HB_WDZ:
 ;
 	LD	A,(CB_CONDEV)		; GET CURRENT CONSOLE
 	LD	(HB_NEWCON),A		; AND INIT NEW CONSOLE VAR
+;
 #IF CRTACT
 ;
 ; BIOS IS CONFIGURED TO AUTO ACTIVATE CRT DEVICE.  FIRST,
@@ -2795,11 +2824,6 @@ HB_WDZ:
 ;
 #ENDIF
 ;
-; THIS IS A GOOD PLACE TO DETERMINE IF FRONT PANEL HARDWARE REALLY
-; EXISTS.
-;
-	CALL	FP_DETECT
-;
 #IF (FPSW_ENABLE)
 ;
 ; IF WE HAVE FRONT PANEL SWITCHES, THIS IS THE RIGHT PLACE TO HANDLE
@@ -2813,8 +2837,9 @@ HB_WDZ:
 	LD	A,FPSW_IO
 	CALL	PRTHEXBYTE
 ;
-	; THE EXISTENCE OF THE FP WAS TESTED EARLIER.  IF IT DOESN'T
-	; EXIST, BAIL OUT.
+	CALL	FP_DETECT
+;
+	; IF FP DOESN'T EXIST, BAIL OUT.
 	LD	A,(FPSW_ACTIVE)		; GET FP EXISTENCE FLAG
 	OR	A			; SET FLAGS
 	JR	NZ,HB_FP1		; IF WE HAVE ONE, CONTINUE
@@ -3155,6 +3180,9 @@ HB_INITTBL:
 #IF (CTCENABLE)
 	.DW	CTC_INIT
 #ENDIF
+#IF (PCFENABLE)
+	.DW	PCF_INIT
+#ENDIF
 #IF (DSKYENABLE)
   #IF (ICMENABLE)
 	.DW	ICM_INIT
@@ -3223,7 +3251,6 @@ HB_INITTBL:
 	.DW	INTRTC_INIT
 #ENDIF
 #IF (DS7RTCENABLE)
-	.DW	PCF8584_INIT
 	.DW	DS7RTC_INIT
 #ENDIF
 #IF (RP5RTCENABLE)
@@ -3286,6 +3313,9 @@ HB_INITTBL:
 #IF (PPPENABLE)
 	.DW	PPP_INIT
 #ENDIF
+#IF (ESPENABLE)
+	.DW	ESP_INIT
+#ENDIF
 ;
 HB_INITTBLLEN	.EQU	(($ - HB_INITTBL) / 2)
 ;
@@ -5111,6 +5141,99 @@ SYS_INTSET1:
 	RET				; DONE
 ;
 ;==================================================================================================
+;   Z280 INTERRUPT VECTOR TABLE
+;==================================================================================================
+;
+#IF (MEMMGR == MM_Z280)
+;
+	; THE Z280 IVT MUST BE ON A 4K BOUNDARY.  IT HAS BEEN LOCATED
+	; HERE IN AN EFFORT TO MINIMIZE WASTED SPACE.  THERE SHOULD BE
+	; A LITTLE LESS THAN 4K OF CODE ABOVE.
+;
+Z280_IVT_SLACK	.EQU	$1000 - ($ & $FFF)
+		.ECHO	"Z280 IVT SLACK occupies "
+		.ECHO	Z280_IVT_SLACK
+		.ECHO	" bytes.\n"
+		;.FILL	$1000 - ($ & $FFF)	; MUST BE 4K ALIGNED!
+		.FILL	Z280_IVT_SLACK		; MUST BE 4K ALIGNED!
+;
+Z280_IVT:
+	.DW	0, 0			; RESERVED
+	.DW	0			; NMI MSR
+	.DW	0			; NMI VECTOR
+	.DW	$0000			; INT A MSR
+	.DW	Z280_BADINT		; INT A VECTOR
+	.DW	$0000			; INT B MSR
+	.DW	Z280_BADINT		; INT B VECTOR
+	.DW	$0000			; INT C MSR
+	.DW	Z280_BADINT		; INT C VECTOR
+	.DW	$0000			; COUNTER/TIMER 0 MSR
+	.DW	Z280_BADINT		; COUNTER/TIMER 0 VECTOR
+	.DW	$0000			; COUNTER/TIMER 1 MSR
+	.DW	Z280_BADINT		; COUNTER/TIMER 1 VECTOR
+	.DW	0, 0			; RESERVED
+	.DW	$0000			; COUNTER/TIMER 2 MSR
+	.DW	Z280_BADINT		; COUNTER/TIMER 2 VECTOR
+	.DW	$0000			; DMA CHANNEL 0 MSR
+	.DW	Z280_BADINT		; DMA CHANNEL 0 VECTOR
+	.DW	$0000			; DMA CHANNEL 1 MSR
+	.DW	Z280_BADINT		; DMA CHANNEL 1 VECTOR
+	.DW	$0000			; DMA CHANNEL 2 MSR
+	.DW	Z280_BADINT		; DMA CHANNEL 2 VECTOR
+	.DW	$0000			; DMA CHANNEL 3 MSR
+	.DW	Z280_BADINT		; DMA CHANNEL 3 VECTOR
+	.DW	$0000			; UART RECEIVER MSR
+	.DW	Z280_BADINT		; UART RECEIVER VECTOR
+	.DW	$0000			; UART TRANSMITTER MSR
+	.DW	Z280_BADINT		; UART TRANSMITTER VECTOR
+	.DW	$0000			; SINGLE STEP TRAP MSR
+	.DW	Z280_SSTEP		; SINGLE STEP TRAP VECTOR
+	.DW	$0000			; BREAK ON HALT TRAP MSR
+	.DW	Z280_BRKHLT		; BREAK ON HALT TRAP VECTOR
+	.DW	$0000			; DIVISION EXCEPTION TRAP MSR
+	.DW	Z280_DIVEXC		; DIVISION EXCEPTION TRAP VECTOR
+	.DW	$0000			; STACK OVERFLOW WARNING TRAP MSR
+	.DW	Z280_STKOVR		; STACK OVERFLOW WARNING TRAP VECTOR
+	.DW	$0000			; ACCESS VIOLATION TRAP MSR
+	.DW	Z280_ACCVIO		; ACCESS VIOLATION TRAP VECTOR
+	.DW	$0000			; SYSTEM CALL TRAP MSR
+	.DW	Z280_SYSCALL		; SYSTEM CALL TRAP VECTOR
+	.DW	$0000			; PRIVILEGED INSTRUCTION TRAP MSR
+	.DW	Z280_PRIVINST		; PRIVILEGED INSTRUCTION TRAP VECTOR
+	.DW	$0000			; EPU <- MEMORY EXTENDED INSTRUCTION TRAP MSR
+	.DW	$0000			; EPU <- MEMORY EXTENDED INSTRUCTION TRAP VECTOR
+	.DW	$0000			; MEMORY <- EPU EXTENDED INSTRUCTION TRAP MSR
+	.DW	$0000			; MEMORY <- EPU EXTENDED INSTRUCTION TRAP VECTOR
+	.DW	$0000			; A <- EPU EXTENDED INSTRUCTION TRAP MSR
+	.DW	$0000			; A <- EPU EXTENDED INSTRUCTION TRAP VECTOR
+	.DW	$0000			; EPU INTERNAL OPERATION EXTENDED INSTRUCTION TRAP MSR
+	.DW	$0000			; EPU INTERNAL OPERATION EXTENDED INSTRUCTION TRAP VECTOR
+	.DW	0, 0			; RESERVED
+	.DW	0, 0			; RESERVED
+	; PROGRAM COUNTER VALUES FOR NMI/INTA (16)
+	.DW	HBX_IV00
+	.DW	HBX_IV01
+	.DW	HBX_IV02
+	.DW	HBX_IV03
+	.DW	HBX_IV04
+	.DW	HBX_IV05
+	.DW	HBX_IV06
+	.DW	HBX_IV07
+	.DW	HBX_IV08
+	.DW	HBX_IV09
+	.DW	HBX_IV0A
+	.DW	HBX_IV0B
+	.DW	HBX_IV0C
+	.DW	HBX_IV0D
+	.DW	HBX_IV0E
+	.DW	HBX_IV0F
+	; THE REMAINDER OF THE Z280 IVT IS TRUNCATED HERE BECAUSE IT
+	; TAKES A BUNCH OF SPACE AND IS NOT USED.  WE SUPPORT ONLY
+	; 16 VECTORED INTERRUPTS AND THEY MUST BE CONNECTED TO INTA.
+;
+#ENDIF
+;
+;==================================================================================================
 ;   GLOBAL HBIOS FUNCTIONS
 ;==================================================================================================
 ;
@@ -5670,94 +5793,6 @@ HB_ALLOC1:
 HB_TMPSZ	.DW	0
 HB_TMPREF	.DW	0
 ;
-;==================================================================================================
-;   Z280 INTERRUPT VECTOR TABLE
-;==================================================================================================
-;
-#IF (MEMMGR == MM_Z280)
-;
-	; THE Z280 IVT MUST BE ON A 4K BOUNDARY.  IT HAS BEEN LOCATED
-	; HERE IN AN EFFORT TO MINIMIZE WASTED SPACE.  THERE SHOULD BE
-	; A LITTLE LESS THAN 4K OF CODE ABOVE.
-;
-	.FILL	$1000 - ($ & $FFF)	; MUST BE 4K ALIGNED!
-;
-Z280_IVT:
-	.DW	0, 0			; RESERVED
-	.DW	0			; NMI MSR
-	.DW	0			; NMI VECTOR
-	.DW	$0000			; INT A MSR
-	.DW	Z280_BADINT		; INT A VECTOR
-	.DW	$0000			; INT B MSR
-	.DW	Z280_BADINT		; INT B VECTOR
-	.DW	$0000			; INT C MSR
-	.DW	Z280_BADINT		; INT C VECTOR
-	.DW	$0000			; COUNTER/TIMER 0 MSR
-	.DW	Z280_BADINT		; COUNTER/TIMER 0 VECTOR
-	.DW	$0000			; COUNTER/TIMER 1 MSR
-	.DW	Z280_BADINT		; COUNTER/TIMER 1 VECTOR
-	.DW	0, 0			; RESERVED
-	.DW	$0000			; COUNTER/TIMER 2 MSR
-	.DW	Z280_BADINT		; COUNTER/TIMER 2 VECTOR
-	.DW	$0000			; DMA CHANNEL 0 MSR
-	.DW	Z280_BADINT		; DMA CHANNEL 0 VECTOR
-	.DW	$0000			; DMA CHANNEL 1 MSR
-	.DW	Z280_BADINT		; DMA CHANNEL 1 VECTOR
-	.DW	$0000			; DMA CHANNEL 2 MSR
-	.DW	Z280_BADINT		; DMA CHANNEL 2 VECTOR
-	.DW	$0000			; DMA CHANNEL 3 MSR
-	.DW	Z280_BADINT		; DMA CHANNEL 3 VECTOR
-	.DW	$0000			; UART RECEIVER MSR
-	.DW	Z280_BADINT		; UART RECEIVER VECTOR
-	.DW	$0000			; UART TRANSMITTER MSR
-	.DW	Z280_BADINT		; UART TRANSMITTER VECTOR
-	.DW	$0000			; SINGLE STEP TRAP MSR
-	.DW	Z280_SSTEP		; SINGLE STEP TRAP VECTOR
-	.DW	$0000			; BREAK ON HALT TRAP MSR
-	.DW	Z280_BRKHLT		; BREAK ON HALT TRAP VECTOR
-	.DW	$0000			; DIVISION EXCEPTION TRAP MSR
-	.DW	Z280_DIVEXC		; DIVISION EXCEPTION TRAP VECTOR
-	.DW	$0000			; STACK OVERFLOW WARNING TRAP MSR
-	.DW	Z280_STKOVR		; STACK OVERFLOW WARNING TRAP VECTOR
-	.DW	$0000			; ACCESS VIOLATION TRAP MSR
-	.DW	Z280_ACCVIO		; ACCESS VIOLATION TRAP VECTOR
-	.DW	$0000			; SYSTEM CALL TRAP MSR
-	.DW	Z280_SYSCALL		; SYSTEM CALL TRAP VECTOR
-	.DW	$0000			; PRIVILEGED INSTRUCTION TRAP MSR
-	.DW	Z280_PRIVINST		; PRIVILEGED INSTRUCTION TRAP VECTOR
-	.DW	$0000			; EPU <- MEMORY EXTENDED INSTRUCTION TRAP MSR
-	.DW	$0000			; EPU <- MEMORY EXTENDED INSTRUCTION TRAP VECTOR
-	.DW	$0000			; MEMORY <- EPU EXTENDED INSTRUCTION TRAP MSR
-	.DW	$0000			; MEMORY <- EPU EXTENDED INSTRUCTION TRAP VECTOR
-	.DW	$0000			; A <- EPU EXTENDED INSTRUCTION TRAP MSR
-	.DW	$0000			; A <- EPU EXTENDED INSTRUCTION TRAP VECTOR
-	.DW	$0000			; EPU INTERNAL OPERATION EXTENDED INSTRUCTION TRAP MSR
-	.DW	$0000			; EPU INTERNAL OPERATION EXTENDED INSTRUCTION TRAP VECTOR
-	.DW	0, 0			; RESERVED
-	.DW	0, 0			; RESERVED
-	; PROGRAM COUNTER VALUES FOR NMI/INTA (16)
-	.DW	HBX_IV00
-	.DW	HBX_IV01
-	.DW	HBX_IV02
-	.DW	HBX_IV03
-	.DW	HBX_IV04
-	.DW	HBX_IV05
-	.DW	HBX_IV06
-	.DW	HBX_IV07
-	.DW	HBX_IV08
-	.DW	HBX_IV09
-	.DW	HBX_IV0A
-	.DW	HBX_IV0B
-	.DW	HBX_IV0C
-	.DW	HBX_IV0D
-	.DW	HBX_IV0E
-	.DW	HBX_IV0F
-	; THE REMAINDER OF THE Z280 IVT IS TRUNCATED HERE BECAUSE IT
-	; TAKES A BUNCH OF SPACE AND IS NOT USED.  WE SUPPORT ONLY
-	; 16 VECTORED INTERRUPTS AND THEY MUST BE CONNECTED TO INTA.
-;
-#ENDIF
-;
 ; Z280 BANK SELECTION (CALLED FROM PROXY)
 ;
 #IF (MEMMGR == MM_Z280)
@@ -6132,6 +6167,7 @@ SIZ_BQRTC	.EQU	$ - ORG_BQRTC
 		.ECHO	SIZ_BQRTC
 		.ECHO	" bytes.\n"
 #ENDIF
+;
 #IF (SIMRTCENABLE)
 ORG_SIMRTC	.EQU	$
   #INCLUDE "simrtc.asm"
@@ -6140,15 +6176,16 @@ SIZ_SIMRTC	.EQU	$ - ORG_SIMRTC
 		.ECHO	SIZ_SIMRTC
 		.ECHO	" bytes.\n"
 #ENDIF
-#IF (DS7RTCENABLE & (DS7RTCMODE=DS7RTCMODE_PCF))
-ORG_PCF8584	.EQU	$
-  #INCLUDE "pcf8584.asm"
-SIZ_PCF8584	.EQU	$ - ORG_PCF8584
-		.ECHO	"PCF8584 occupies "
-		.ECHO	SIZ_PCF8584
+;
+#IF (PCFENABLE)
+ORG_PCF		.EQU	$
+  #INCLUDE "pcf.asm"
+SIZ_PCF		.EQU	$ - ORG_PCF
+		.ECHO	"PCF occupies "
+		.ECHO	SIZ_PCF
 		.ECHO	" bytes.\n"
 #ENDIF
-
+;
 #IF (DS7RTCENABLE)
 ORG_DS7RTC	.EQU	$
   #INCLUDE "ds7rtc.asm"
@@ -6434,6 +6471,15 @@ SIZ_PPP		.EQU	$ - ORG_PPP
 		.ECHO	" bytes.\n"
 #ENDIF
 ;
+#IF (ESPENABLE)
+ORG_ESP		.EQU	$
+  #INCLUDE "esp.asm"
+SIZ_ESP		.EQU	$ - ORG_ESP
+		.ECHO	"ESP occupies "
+		.ECHO	SIZ_ESP
+		.ECHO	" bytes.\n"
+#ENDIF
+;
 #IF (MDENABLE)
 ORG_MD		.EQU	$
   #INCLUDE "md.asm"
@@ -7104,7 +7150,7 @@ PS_PRTSC1:
 	RET
 ;
 PS_PRTSC2:
-	PRTS("PropTerm$")		; ASSUME PROPELLER
+	PRTS("Term Module$")
 	CALL	PC_COMMA
 	PRTS("ANSI$")
 	RET
@@ -7343,6 +7389,7 @@ PS_SDUF		.TEXT	"UF$"
 PS_SDDUART	.TEXT	"DUART$"
 PS_SDZ2U	.TEXT	"Z2U$"
 PS_SDLPT	.TEXT	"LPT$"
+PS_SDESPCON	.TEXT	"ESPCON$"
 ;
 ; CHARACTER SUB TYPE STRINGS
 ;

Source/HBIOS/hbios.inc

@@ -313,6 +313,7 @@ CIODEV_UF	.EQU	$80
 CIODEV_DUART	.EQU	$90
 CIODEV_Z2U	.EQU	$A0
 CIODEV_LPT	.EQU	$B0
+CIODEV_ESPCON	.EQU	$C0
 ;
 ; SUB TYPES OF CHAR DEVICES
 ;

Source/HBIOS/pcf.asm

@@ -2,12 +2,11 @@
 ; PCF8584 I2C CLOCK DRIVER
 ;==================================================================================================
 ;
-PCF_BASE  	.EQU  0F0H
+PCF_BASE  	.EQU  PCFBASE
 PCF_ID   	.EQU  0AAH
-CPU_CLK	  	.EQU  12
-
+;
 PCF_RS0		.EQU  PCF_BASE
-PCF_RS1		.EQU  PCF_RS0+1
+PCF_RS1		.EQU  PCF_BASE+1
 PCF_OWN	 	.EQU  (PCF_ID >> 1)	 	; PCF'S ADDRESS IN SLAVE MODE
 ;
 ;T4LC512D	.EQU	10100000B		; DEVICE IDENTIFIER
@@ -37,10 +36,10 @@ PCF_STA  	.EQU  00000100B
 PCF_STO  	.EQU  00000010B
 PCF_ACK  	.EQU  00000001B
 ;
-PCF_START_		.EQU  (PCF_PIN | PCF_ES0 | PCF_STA | PCF_ACK)
-PCF_STOP_		.EQU  (PCF_PIN | PCF_ES0 | PCF_STO | PCF_ACK)
-PCF_REPSTART_ 	.EQU  (	   PCF_ES0 | PCF_STA | PCF_ACK)
-PCF_IDLE_		.EQU  (PCF_PIN | PCF_ES0		| PCF_ACK)
+PCF_START_	.EQU  (PCF_PIN | PCF_ES0 | PCF_STA | PCF_ACK)
+PCF_STOP_	.EQU  (PCF_PIN | PCF_ES0 | PCF_STO | PCF_ACK)
+PCF_REPSTART_ 	.EQU  (PCF_ES0 | PCF_STA | PCF_ACK)
+PCF_IDLE_	.EQU  (PCF_PIN | PCF_ES0 | PCF_ACK)
 ;
 ; STATUS REGISTER BITS
 ;
@@ -54,43 +53,6 @@ PCF_AAS   	.EQU  00000100B
 PCF_LAB   	.EQU  00000010B
 PCF_BB		.EQU  00000001B
 ;
-; CLOCK CHIP FREQUENCIES
-;
-PCF_CLK3   	.EQU	000H
-PCF_CLK443 	.EQU	010H
-PCF_CLK6   	.EQU	014H
-PCF_CLK8   	.EQU	018H
-PCF_CLK12  	.EQU	01cH
-;
-; TRANSMISSION FREQUENCIES
-;
-PCF_TRNS90 	.EQU	000H	;  90 kHz */
-PCF_TRNS45 	.EQU	001H	;  45 kHz */
-PCF_TRNS11 	.EQU	002H	;  11 kHz */
-PCF_TRNS15 	.EQU	003H	; 1.5 kHz */
-;
-; TIMEOUT AND DELAY VALUES (ARBITRARY)
-;
-PCF_PINTO	.EQU	65000
-PCF_ACKTO	.EQU	65000
-PCF_BBTO	.EQU	65000
-PCF_LABDLY	.EQU	65000
-;
-; DATA PORT REGISTERS
-;
-#IF (CPU_CLK = 443)
-PCF_CLK .EQU PCF_CLK4433
-#ELSE 
- #IF (CPU_CLK = 8)
-PCF_CLK .EQU PCF_CLK8
- #ELSE 
-  #IF (CPU_CLK = 12)
-PCF_CLK .EQU PCF_CLK12
-  #ELSE ***ERROR
-  #ENDIF
- #ENDIF	
-#ENDIF
-;
 ; THE PCF8584 TARGETS A TOP I2C CLOCK SPEED OF 90KHZ AND SUPPORTS DIVIDERS FOR 
 ; 3, 4.43, 6, 8 AND 12MHZ TO ACHEIVE THIS.
 ;
@@ -104,14 +66,44 @@ PCF_CLK .EQU PCF_CLK12
 ; |  12MHz  |       |        |       |         |        | 90Khz | 120Khz |   138Khz  |  150Khz |
 ; +----------------------------------------------------------------------------------+---------+
 ;
-PCF8584_INIT:
+; CLOCK CHIP FREQUENCIES
+;
+PCF_CLK3   	.EQU	000H
+PCF_CLK443 	.EQU	010H
+PCF_CLK6   	.EQU	014H
+PCF_CLK8   	.EQU	018H
+PCF_CLK12  	.EQU	01CH
+;
+; TRANSMISSION FREQUENCIES
+;
+PCF_TRNS90 	.EQU	000H	;  90 kHz */
+PCF_TRNS45 	.EQU	001H	;  45 kHz */
+PCF_TRNS11 	.EQU	002H	;  11 kHz */
+PCF_TRNS15 	.EQU	003H	; 1.5 kHz */
+;
+; BELOW VARIABLES CONTROL PCF CLOCK DIVISOR PROGRAMMING
+; HARD-CODED FOR NOW
+;
+PCF_CLK	  	.EQU	PCF_CLK12
+PCF_TRNS	.EQU	PCF_TRNS90
+;
+; TIMEOUT AND DELAY VALUES (ARBITRARY)
+;
+PCF_PINTO	.EQU	65000
+PCF_ACKTO	.EQU	65000
+PCF_BBTO	.EQU	65000
+PCF_LABDLY	.EQU	65000
+;
+; DATA PORT REGISTERS
+;
+PCF_INIT:
 	CALL	NEWLINE				; Formatting
-	PRTS("I2C: IO=0x$")
+	PRTS("PCF: IO=0x$")
 	LD	A, PCF_BASE
 	CALL	PRTHEXBYTE
 	CALL	PC_SPACE
-	CALL	PCF_INIT
-	CALL	NEWLINE
+	CALL	PCF_INITDEV
+	;CALL	NEWLINE
 	RET
 ;
 ; LINUX DRIVER BASED CODE
@@ -141,11 +133,13 @@ PCF_STOP:
 ;
 ;-----------------------------------------------------------------------------
 ;
-PCF_INIT:
+PCF_INITDEV:
 	LD	A,PCF_PIN   	; S1=80H: S0 SELECTED, SERIAL 
 	OUT	(PCF_RS1),A	; INTERFACE OFF
 	NOP
 	IN	A,(PCF_RS1)	; CHECK TO SEE S1 NOW USED AS R/W
+	;CALL	PC_SPACE
+	;CALL	PRTHEXBYTE
 	AND	07FH	  	; CTRL. PCF8584 DOES THAT WHEN ESO
 	JR	NZ,PCF_FAIL	; IS ZERO
 ;
@@ -153,6 +147,8 @@ PCF_INIT:
 	OUT	(PCF_RS0),A	; EFFECTIVE ADDRESS IS (OWN <<1)
 	NOP
 	IN	A,(PCF_RS0)	; CHECK IT IS REALLY WRITTEN
+	;CALL	PC_SPACE
+	;CALL	PRTHEXBYTE
 	CP	PCF_OWN
 	JP	NZ,PCF_SETERR
 ;
@@ -160,14 +156,18 @@ PCF_INIT:
 	OUT	(PCF_RS1),A		; NEXT BYTE IN S2
 	NOP
 	IN	A,(PCF_RS1)
+	;CALL	PC_SPACE
+	;CALL	PRTHEXBYTE
 	AND	07FH
 	CP	PCF_ES1
 	JP	NZ,PCF_REGERR
 ;
-	LD	A,PCF_CLK	; LOAD CLOCK REGISTER S2
+	LD	A,PCF_CLK | PCF_TRNS	; LOAD CLOCK REGISTER S2
 	OUT	(PCF_RS0),A
 	NOP
 	IN	A,(PCF_RS0)	; CHECK IT'S REALLY WRITTEN, ONLY
+	;CALL	PC_SPACE
+	;CALL	PRTHEXBYTE
 	AND	1FH	   	; THE LOWER 5 BITS MATTER
 	CP	PCF_CLK
 	JP	NZ,PCF_CLKERR
@@ -176,6 +176,8 @@ PCF_INIT:
 	OUT	(PCF_RS1),A  
 	NOP
 	IN	A,(PCF_RS1)  
+	;CALL	PC_SPACE
+	;CALL	PRTHEXBYTE
 	CP	+(PCF_PIN | PCF_BB)
 	JP	NZ,PCF_IDLERR
 ;
@@ -381,12 +383,12 @@ PCF_READI2C:
 ;
 ; POLL THE BUS BUSY BIT TO DETERMINE IF BUS IS FREE.
 ; RETURN WITH A=00H/Z STATUS IF BUS IS FREE
-; RETURN WITH A=FFH/NZ STATUS IF BUS
+; RETURN WITH A=FFH/NZ STATUS IF BUS IS BUSY
 ;
 ; AFTER RESET THE BUS BUSY BIT WILL BE SET TO 1 I.E. NOT BUSY
 ;
 PCF_WAIT_FOR_BB:
-	 LD	HL,PCF_BBTO
+	LD	HL,PCF_BBTO
 PCF_WFBB0:
 	IN	A,(PCF_RS1)
 	AND	PCF_BB

Source/HBIOS/ppp.asm

@@ -4,7 +4,6 @@
 ;==================================================================================================
 ;
 ; TODO:
-;   1) ADD SUPPORT FOR DSKY
 ;
 PPP_IO		.EQU	PPPBASE + 0	; PPP DATA I/O (PPI PORT A)
 PPP_CTL		.EQU	PPPBASE + 2	; PPP CTL LINES (PPI PORT C)

Source/HBIOS/prp.asm

@@ -4,7 +4,6 @@
 ;==================================================================================================
 ;
 ; TODO:
-;   1) ADD SUPPORT FOR DSKY
 ;
 PRP_IOBASE	.EQU	$A8
 ;

Source/HBIOS/romldr.asm

@@ -1343,6 +1343,36 @@ diskread:
 ;
 #endif
 ;
+; Built-in mini-loader for S100 Monitor.  The S100 platform build
+; imbeds the S100 Monitor in the ROM at the start of bank 3 (BID_IMG2).
+; This bit of code just launches the monitor directly from that bank.
+;
+#if (BIOS == BIOS_WBW)
+  #if (PLATFORM == PLT_S100)
+;
+s100mon:
+	; Warn user that console is being directed to the S100 bus
+	; if the IOBYTE bit 0 is 0 (%xxxxxxx0).
+	in	a,($75)			; get IO byte
+	and	%00000001		; isolate console bit
+	jr	nz,s100mon1		; if 0, bypass msg
+	ld	hl,str_s100con		; console msg string
+	call	pstr			; display it
+;
+s100mon1:
+	; Launch S100 Monitor from ROM Bank 3
+	call	ldelay			; wait for UART buf to empty
+	di				; suspend interrupts
+	ld	a,BID_IMG2		; S100 monitor bank
+	ld	ix,0			; execution resumes here
+	jp	HB_BNKCALL		; do it
+;
+str_smon	.db	"S100 Z180 Monitor",0
+str_s100con	.db	"\r\n\r\nConsole on S100 Bus",0
+;
+  #endif
+#endif
+;
 ;=======================================================================
 ; Utility functions
 ;=======================================================================
@@ -2311,6 +2341,11 @@ ra_tbl:
 ;      ---------  -------  -----  --------  -----        -------  -------  ----------
 ra_ent(str_mon,	  'M',	   KY_CL, BID_IMG0, MON_IMGLOC,  MON_LOC, MON_SIZ, MON_SERIAL)
 ra_entsiz	.equ	$ - ra_tbl
+#if (BIOS == BIOS_WBW)
+  #if (PLATFORM == PLT_S100)
+ra_ent(str_smon,  'S',	   $FF,	  bid_cur , $8000,       $8000,   $0001,   s100mon)
+  #endif
+#endif
 ra_ent(str_zsys,  'Z',	   KY_FW, BID_IMG0, ZSYS_IMGLOC, CPM_LOC, CPM_SIZ, CPM_ENT)
 ra_ent(str_cpm22, 'C',	   KY_BK, BID_IMG0, CPM_IMGLOC,  CPM_LOC, CPM_SIZ, CPM_ENT)
 #if (BIOS == BIOS_WBW)
@@ -2333,7 +2368,7 @@ ra_tbl_app:
 ;      Name	  Key	   Dsky	  Bank	    Src	         Dest	    Size     Entry
 ;      ---------  -------  -----  --------  -----       -------  -------  ----------
 ra_ent(str_mon,	  'M',	   KY_CL, bid_cur,  MON_IMGLOC,  MON_LOC, MON_SIZ, MON_SERIAL)
-ra_ent(str_zsys,  'Z',	   KY_FW, bid_cur,  ZSYS_IMGLOC,  CPM_LOC, CPM_SIZ, CPM_ENT)
+ra_ent(str_zsys,  'Z',	   KY_FW, bid_cur,  ZSYS_IMGLOC, CPM_LOC, CPM_SIZ, CPM_ENT)
 #if (DSKYENABLE)
 ra_ent(str_dsky,  'Y'+$80, KY_GO, bid_cur,  MON_IMGLOC,  MON_LOC, MON_SIZ, MON_DSKY)
 #endif

Source/HBIOS/sd.asm

@@ -9,14 +9,14 @@
 ;	- TEST XC CARD TYPE DETECTION
 ;	- TRY TO GET INIT TO FAIL, REMOVE DELAYS AT START OF GOIDLE?
 ;
-;----------------------------------------------------------------------------------------------
-; SD Signal	Active	JUHA	N8	CSIO	PPI	UART	DSD	MK4	SC	MT
-; ------------	------- ------- ------- ------- ------- ------- ------- -------	-------	-------
-; CS (DAT3)	LO ->	RTC:2	RTC:2	RTC:2	~PC:4	~MCR:3	OPR:2	SD:2	~RTC:2/3OPR:4/5
-; CLK		HI ->	RTC:1	RTC:1	CSIO	PC:1	~MCR:2	OPR:1	CSIO	CSIO	SPI
-; DI (CMD)	HI ->	RTC:0	RTC:0	CSIO	PC:0	~MCR:0	OPR:0	CSIO	CSIO	SPI
-; DO (DAT0)	HI ->	RTC:7	RTC:6	CSIO	PB:7	~MSR:5	OPR:0	CSIO	CSIO	SPI
-;----------------------------------------------------------------------------------------------
+;-----------------------------------------------------------------------------------------------------
+; SD Signal	Active	JUHA	N8	CSIO	PPI	UART	DSD	MK4	SC	MT     PIO
+; ------------	------- ------- ------- ------- ------- ------- ------- -------	-------	--------------
+; CS (DAT3)	LO ->	RTC:2	RTC:2	RTC:2	~PC:4	~MCR:3	OPR:2	SD:2	~RTC:2/3OPR:4/5~OPR:3
+; CLK		HI ->	RTC:1	RTC:1	CSIO	PC:1	~MCR:2	OPR:1	CSIO	CSIO	SPI    OPR:4
+; DI (CMD)	HI ->	RTC:0	RTC:0	CSIO	PC:0	~MCR:0	OPR:0	CSIO	CSIO	SPI    OPR:0
+; DO (DAT0)	HI ->	RTC:7	RTC:6	CSIO	PB:7	~MSR:5	OPR:0	CSIO	CSIO	SPI    OPR:7
+;-----------------------------------------------------------------------------------------------------
 ;
 ; CS = CHIP SELECT (AKA DAT3 FOR NON-SPI MODE)
 ; CLK = CLOCK
@@ -167,6 +167,7 @@ RTCDEF		.SET	RTCDEF | SD_OPRDEF	; SET DEFAULT IN HBIOS MAINLINE
 SD_DEVMAX	.EQU	1		; NUMBER OF PHYSICAL UNITS (SOCKETS)
 SD_PPIBASE	.EQU	SDPPIBASE	; BASE IO PORT FOR PPI
 SD_PPIB		.EQU	SDPPIBASE + 1	; PPI PORT B (INPUT: DOUT)
+SD_PPIB		.EQU	SDPPIBASE + 1	; PPI PORT B (INPUT: DOUT)
 SD_PPIC		.EQU	SDPPIBASE + 2	; PPI PORT C (OUTPUT: CS, CLK, DIN)
 SD_PPIX		.EQU	SDPPIBASE + 3	; PPI CONTROL PORT
 SD_OPRREG	.EQU	SD_PPIC		; PPI PORT C IS OPR REG
@@ -298,7 +299,10 @@ SD_INVCS	.EQU	FALSE		; INVERT CS
 SD_DEVMAX	.EQU	1		; NUMBER OF PHYSICAL UNITS (SOCKETS)
 SD_IOBASE	.EQU	$69		; IO BASE ADDRESS FOR SD INTERFACE
 SD_OPRREG	.EQU	SD_IOBASE	; OUTPUT PORT (OUTPUT: CS, CLK, DIN)
-SD_OPRDEF	.EQU	%11111111	; OUTPUT PORT DEFAULT STATE
+;--- WBW
+;SD_OPRDEF	.EQU	%11111111	; OUTPUT PORT DEFAULT STATE
+SD_OPRDEF	.EQU	%11101111	; OUTPUT PORT DEFAULT STATE
+;---
 SD_INPREG	.EQU	SD_IOBASE	; INPUT REGISTER
 SD_CS0		.EQU	%00001000	; SELECT
 SD_CLK		.EQU	%00010000	; CLOCK
@@ -1801,6 +1805,7 @@ SD_SETUP:
 ;
 #IF (SDMODE == SDMODE_PIO)
 	LD	A,SD_OPRDEF		; All output bits high
+	LD	(SD_OPRVAL),A		; WBW
 	OUT	(SD_OPRREG),A
 	LD	A,$CF			; Port B mode 3
 	OUT	(SD_DDR),A

Source/HBIOS/std.asm

@@ -282,6 +282,7 @@ DMAMODE_Z180	.EQU	2		; Z180 INTEGRATED DMA
 DMAMODE_Z280	.EQU	3		; Z280 INTEGRATED DMA
 DMAMODE_RC	.EQU	4		; RCBUS Z80 DMA
 DMAMODE_MBC	.EQU	5		; MBC
+DMAMODE_DUO	.EQU	6		; DUO
 ;
 ; KEYBOARD MODE SELECTIONS
 ;

Source/HBIOS/uart.asm

@@ -59,6 +59,7 @@ UARTMBASE		.EQU	$18
 UART4BASE		.EQU	$C0
 UARTRBASE		.EQU	$A0
 UARTDBASE		.EQU	$80
+UARTYBASE		.EQU	$58
 ;
 #IF (UARTINTS)
 ;
@@ -1087,6 +1088,16 @@ UART_CFG_MFP:
 	.DW	UARTCFG				; LINE CONFIGURATION
 	.DW	0				; SHOULD NEVER NEED INT HANDLER
 #ENDIF
+#IF (UARTDUO)
+UART_CFG_DUO:
+	; DUODYNE ONBOARD SERIAL PORT
+	.DB	0				; DEVICE NUMBER (UPDATED DURING INIT)
+	.DB	0				; UART TYPE
+	.DB	UARTYBASE			; IO PORT BASE (RBR, THR)
+	.DB	UARTYBASE + UART_LSR		; LINE STATUS PORT (LSR)
+	.DW	UARTCFG				; LINE CONFIGURATION
+	.DW	0				; POINTER TO RCV BUFFER STRUCT
+#ENDIF
 ;
 UART_CNT	.EQU	($ - UART_CFG) / 8
 ;

Source/ver.inc

@@ -2,7 +2,7 @@
 #DEFINE	RMN	3
 #DEFINE	RUP	0
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.3.0-dev.32"
+#DEFINE BIOSVER	"3.3.0-dev.42"
 #define rmj	RMJ
 #define rmn	RMN
 #define rup	RUP

Source/ver.lib

@@ -3,5 +3,5 @@ rmn	equ	3
 rup	equ	0
 rtp	equ	0
 biosver	macro
-	db	"3.3.0-dev.32"
+	db	"3.3.0-dev.42"
 	endm