RPi Builds & CH375/6 Support

- The build process was enhanced by Dean  Jenkins to support the Raspberry Pi.  Note that the Propeller firmware will not be generated by a RPi build.  See Issue #358.
- Initial support for USB storage via CH375/6.

Binary/ReadMe.txt

@@ -39,8 +39,8 @@ image for the Mark IV with the standard configuration. If a custom
 configuration called "custom" is created and built, a new file called 
 MK4_custom.rom will be added to this directory.
 
-Documentation of the pre-built ROM Images is contained in the 
-RomList.txt file in this directory.
+Documentation of the pre-built ROM Images is contained in
+"RomWBW User Guide.pdf" in the Doc directory.
 
 ROM Firmware Update Images (<plt>_<cfg>.upd)
 -------------------------------------

Doc/ChangeLog.txt

@@ -17,6 +17,12 @@ Version 3.3
 - WBW: Preliminary support for S100 Computers Z180
 - WBW: Preliminary support for Dan Werner's ESP32 MBC Module
 - WBW: Early support for Duodyne base system (CPU/UART/ROM/RAM/RTC/SPK)
+- M?C: Fixed XM to allow specifying HBIOS port for send operations
+- WBW: Fix S100 Z180 LED operation (credit to Jay Cotton for finding this issue)
+- WBW: QPM system image is now combined with current CBIOS during build
+- WBW: Added framework for Heath platform
+- WBW: Support for USB Disks via CH375/CH376
+- D?J: Support for Raspberry Pi build process
 
 Version 3.2.1
 -------------

ReadMe.md

@@ -3,7 +3,7 @@
 **RomWBW ReadMe** \
 Version 3.3 \
 Wayne Warthen  ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \
-07 Jul 2023
+14 Sep 2023
 
 # Overview
 

ReadMe.txt

@@ -1,6 +1,6 @@
 RomWBW ReadMe
 Wayne Warthen (wwarthen@gmail.com)
-07 Jul 2023
+14 Sep 2023
 
 
 

Source/Apps/FDU/fdu.doc

@@ -153,7 +153,8 @@ JP2 (/FAULT) shorted, JP3 (MINI): 2-3, JP4 (/DC/RDY): 2-3.
 
 The RCBus Scott Baker WDC-based floppy module should be jumpered
 for I/O base address 0x50 (SV1: 11-12), JP1 (/DACK): 1-2,
-JP2 (TC): 2-3.
+JP2 (TC): 2-3.  Note that pin 1 of JPX jumpers is toward the bottom
+of the board.
 
 The RCBus FDC by Alan Cox (Etched Pixels) needs to be strapped
 for base I/O address 0x48.

Source/Apps/Test/DMAmon/dmamon.asm

@@ -12,12 +12,26 @@ DMAMODE_Z180	.EQU	2		; Z180 INTEGRATED DMA
 DMAMODE_Z280	.EQU	3		; Z280 INTEGRATED DMA
 DMAMODE_RC	.EQU	4		; RCBUS Z80 DMA
 DMAMODE_MBC	.EQU	5		; MBC
-DMAMODE_VDG	.EQU	6		; VELESOFT DATAGEAR
+DMAMODE_DUO	.EQU	6		; DUO
+DMAMODE_VDG	.EQU	7		; VELESOFT DATAGEAR
+;
+DMAMODE		.EQU	DMAMODE_DUO	; SELECT DMA DEVICE FOR TESTING
+;
+;==================================================================================================
+; SOME DEFAULT PLATFORM CONFIGURATIONS
+;==================================================================================================
 ;
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_MBC	; SELECT DMA DEVICE FOR TESTING
+DMALATCH	.EQU	DMABASE+1	; DMA: DMA LATCH ADDRESS
 DMAIOTST	.EQU	$68		; AN OUTPUT PORT FOR TESTING - 16C450 SERIAL OUT
 ;
+#IF (DMAMODE==DMAMODE_DUO)
+DMABASE		.SET	$40		; DMA: DMA0 BASE ADDRESS
+DMALATCH	.SET	$43		; DMA: DMA LATCH ADDRESS
+DMAIOTST	.SET	$58		; AN OUTPUT PORT FOR TESTING - 16C450 SERIAL OUT
+;DMAIOTST	.SET	$94		; AN ALT OUTPUT PORT FOR TESTING - RTC/SPEAKER/LEDS PORT
+#ENDIF
+;
 ;==================================================================================================
 ; HELPER MACROS AND EQUATES
 ;==================================================================================================
@@ -113,7 +127,7 @@ MAIN:
 	LD	SP,STACK		; STACK
 ;
 	call	PRTSTRD			; WELCOME
-	.db	"\n\rDMA Monitor V3\n\r$"
+	.db	"\n\rDMA Monitor V3.1\n\r$"
 ;
 #IF (INTENABLE)
 ;
@@ -122,6 +136,8 @@ MAIN:
 	ld	de,$A000
 	ld	bc,hsiz
 	ldir
+	ld	a,(dmaport)
+	ld	(int_dmaport),a
 ;
 	; Install interrupt vector (RomWBW specific!!!)
 	ld	hl,int		; pointer to my interrupt handler
@@ -156,17 +172,17 @@ MENULP1:
 	CP	'N'
 	JP	Z,DMATST_N		; MEMORY COPY ITER
 	CP	'0'
-	JP	Z,DMATST_01
+	JP	Z,DMATST_0		; PULSE DMA PORT
+	CP	'1'
+	JP	Z,DMATST_1		; PULSE LATCH PORT
 	CP	'O'
 	JP	Z,DMATST_O
-#IF !(DMAMODE==DMAMODE_VDG)
-	CP	'1'
-	JP	Z,DMATST_01
 	CP	'R'
 	JP	Z,DMATST_R		; TOGGLE RESET
 	CP	'Y'
-	JP	Z,DMATST_Y		; TOGGLE READY
-#ENDIF
+	JP	Z,DMATST_Y
+	cp	'L'
+	jp	z,DMACFG_L		; SET LATCH PORT
 	cp	'S'
 	jp	z,DMACFG_S		; SET PORT
 	cp	'V'
@@ -197,12 +213,20 @@ DMABYE:
 ;
 DMACFG_S:
 	call	PRTSTRD
-	.db	"\n\rSet port address\n\rPort:$"
+	.db	"\n\rSet DMA port address\n\rPort:$"
 	call	HEXIN
 	ld	hl,dmaport
 	ld	(hl),a
-	inc	hl
-	inc	a
+#IF (INTENABLE)
+	ld	(int_dmaport),a
+#ENDIF
+	jp	MENULP
+;
+DMACFG_L:
+	call	PRTSTRD
+	.db	"\n\rSet Latch port address\n\rPort:$"
+	call	HEXIN
+	ld	hl,dmalach
 	ld	(hl),a
 	jp	MENULP
 ;
@@ -234,11 +258,17 @@ DMATST_N:
 	CALL	DMAMemTestIter
 	JP	MENULP
 ;
-DMATST_01:
+DMATST_0:
 	call	PRTSTRD
-	.db	"\n\rPerforming Port Selection Test\n\r$"
-	CALL	DMA_Port01
-	JP	MENULP
+	.db	"\n\rPerforming DMA Port Selection Test\n\r$"
+	CALL	DMA_Port0
+	ret
+
+DMATST_1:
+	call	PRTSTRD
+	.db	"\n\rPerforming Latch Port Selection Test\n\r$"
+	CALL	DMA_Port1
+	ret
 ;
 DMATST_O:
 	call	PRTSTRD
@@ -255,7 +285,7 @@ DMATST_D:
 DMATST_Y:
 	call	PRTSTRD
 	.db	"\n\rPerforming Ready Bit Test\n\r$"
-	CALL	DMA_ReadyT
+	CALL	DMA_ReadyY
 	JP	MENULP
 ;
 DMATST_R:
@@ -289,6 +319,10 @@ DISPM:	call	PRTSTRD
 	.db	", Port=0x$"
 	LD	A,(dmaport)		; DISPLAY
 	CALL	PRTHEXBYTE		; DMA PORT
+	call	PRTSTRD
+	.db	", Latch Port=0x$"
+	ld	A,(dmalach)
+	CALL	PRTHEXBYTE		; DMA PORT
 ;
 #IF (INTENABLE)
 ;
@@ -351,7 +385,7 @@ DMA_INIT:
 	CALL	PRTHEXBYTE
 ;
 #IF !(DMAMODE==DMAMODE_VDG)
-	ld	a,(dmautil)
+	ld	a,(dmalach)
 	ld	c,a
 	LD	A,DMA_FORCE
 	out	(c),a			; force ready off
@@ -369,7 +403,8 @@ DMA_INIT:
 ;
 	ld	hl,DMACode		; program the
 	ld	b,DMACode_Len		; dma command
-	ld	c,DMABASE		; block
+	ld	a,(dmaport)
+	ld	c,a		; block
 ;
 	di
 	otir				; load dma
@@ -417,6 +452,7 @@ DMA_DEV_STR:
 	.TEXT	"Z280$"
 	.TEXT	"RCBUS$"
 	.TEXT	"MBC$"
+	.TEXT	"DUODYNE$"
 	.TEXT	"DATAGEAR$"
 ;
 DMA_SPD_STR:
@@ -479,11 +515,12 @@ DMACFG_V:
 ;==================================================================================================
 ;
 DMABUF	.TEXT	"0123456789abcdef"
+;DMABUF	.DB	$04,$00,$04,$00,$04,$00,$04,$00,$04,$00,$04,$00,$04,$00,$04,$00,$00,$00,$00 ; SPEAKER
 ;
 DMA_ReadyO:
 	call	PRTSTRD
 	.db	"\r\nOutputing string to port 0x$"
-	ld	a,DMAIOTST
+	ld	a,(tstport)
 	call	PRTHEXBYTE
 	call	NEWLINE
 ;
@@ -491,7 +528,7 @@ DMA_ReadyO:
 IOLoop:	push	bc
 	call	NEWLINE
 	ld	hl,DMABUF
-	ld	a,DMAIOTST
+	ld	a,(tstport)
 	ld	bc,16
 ;
 	call	DMAOTIR
@@ -502,16 +539,17 @@ IOLoop:	push	bc
 	ret
 ;
 ;==================================================================================================
-; PULSE PORT (COMMON ROUTINE WHERE A CONTAINS THE ASCII PORT OFFSET)
+; PULSE PORT
 ;==================================================================================================
 ;
-DMA_Port01:
+DMA_Port0:
+	ld	a,(dmaport)
+	jr	DMA_Port
+DMA_Port1:
+	ld	a,(dmalach)
+DMA_Port:
 	call	PRTSTRD
 	.db	"\r\nPulsing port 0x$"
-	sub	'0'			; Calculate
-	ld	c,a
-	ld	a,(dmaport)		; Port to
-	add	a,c
 	call	PRTHEXBYTE
 	call	NEWLINE
 	ld	c,a			; toggle
@@ -543,12 +581,9 @@ dlylp:	dec	bc
 ; TOGGLE READY BIT
 ;==================================================================================================
 ;
-DMA_ReadyT:
+DMA_ReadyY:
 	call	NEWLINE
-#IF !(DMAMODE==DMAMODE_VDG)
-
-#ENDIF
-	ld	a,(dmautil)
+	ld	a,(dmalach)
 	ld	c,a			; toggle
 	ld	b,$20			; loop counter
 portlp2:push	bc
@@ -558,14 +593,12 @@ portlp2:push	bc
 	.db	": ON$"
 	call	delay
 	ld	a,$FF
-;	ld	c,DMABASE+1
 	out	(c),a
 	call	PRTSTRD
 	.db	" -> OFF$"
 	call	delay
 	call	PRTSTRD
 	.db	"\r               \r$"
-;	ld	c,DMABASE+1
 	ld	a,0
 	out	(c),a
 	pop	bc
@@ -605,9 +638,9 @@ DMAMemMove1:
 ;
 DMAMemMove2:
 ;
-;	LD	HL,$8400	; PLANT
-;	LD	A,$00		; BAD
-;	LD	(HL),A		; SEED
+	;LD	HL,$8400	; PLANT
+	;LD	A,$00		; BAD
+	;LD	(HL),A		; SEED
 ;
 	LD	A,$AA		; CHECK COPY SUCCESSFULL
 	LD	HL,$8000
@@ -615,6 +648,14 @@ DMAMemMove2:
 NXTCMP:	CPI
 	JP	PO,CMPOK
 	JR	Z,NXTCMP
+
+	DEC	HL
+	CALL	PRTHEXWORDHL
+	LD	A,' '
+	CALL	COUT
+	LD	A,(HL)
+	CALL	PRTHEXBYTE
+	
 	RET			; RET W/ ZF CLEAR
 ;
 CMPOK:
@@ -1167,10 +1208,10 @@ CST:
 	RET
 ;
 USEINT	.DB	FALSE		; USE INTERRUPTS FLAG
-counter	.dw	0	
 dmaport	.db	DMABASE
-dmautil	.db	DMABASE+1
+dmalach	.db	DMALATCH
 dmaxfer	.db	DMA_XMODE
+tstport	.db	DMAIOTST
 dmavbs	.db	0
 SAVSTK:	.DW	2
 	.FILL	64
@@ -1187,11 +1228,16 @@ reladr	.equ	$		; relocation start adr
 	.org	$A000		; code will run here
 ;
 int:
+	;LD	E,'.'			; OUTPUT CHAR TO E
+	;LD	C,CIO_CONSOLE		; CONSOLE UNIT TO C
+	;LD	B,BF_CIOOUT		; HBIOS FUNC: OUTPUT CHAR
+	;CALL	$FFF0			; HBIOS OUTPUTS CHARACTER
+
 	; According to the DMA doc, you must issue
 	; a DMA_DISABLE command prior to a
 	; DMA_REINIT_STATUS_BYTE command to avoid a
 	; potential race condition.
-	ld	a,(dmaport)
+	ld	a,(int_dmaport)
 	ld	c,a
 	ld	a,DMA_DISABLE
 	out	(c),a
@@ -1211,6 +1257,11 @@ int:
 	or	$ff		; signal int handled
 	ret
 ;
+; data referred to in handler must reside in high mem
+;
+int_dmaport	.db	0	; hi mem copy of dmaport
+counter		.dw	0	; interrupt counter
+;
 hsiz	.equ	$ - $A000	; size of handler to relocate
 ;
 	.org	reladr + hsiz

Source/Apps/Test/I2C/Build.cmd

@@ -8,6 +8,8 @@ set TASMTABS=%TOOLS%\tasm32
 tasm -t180 -g3 -fFF i2cscan.asm i2cscan.com i2cscan.lst || exit /b
 tasm -t180 -g3 -fFF rtcds7.asm rtcds7.com rtcds7.lst || exit /b
 tasm -t180 -g3 -fFF i2clcd.asm i2clcd.com i2clcd.lst || exit /b
+tasm -t80 -g3 -ff srom.asm srom.com srom.lst || exit /b
 
 copy /Y i2c*.com ..\..\..\..\Binary\Apps\Test\ || exit /b
 copy /Y rtcds7*.com ..\..\..\..\Binary\Apps\Test\ || exit /b
+copy /Y srom.com ..\..\..\..\Binary\Apps\Test\ || exit /b

Source/Apps/Test/I2C/Makefile

@@ -1,4 +1,4 @@
-OBJECTS = i2cscan.com rtcds7.com i2clcd.com
+OBJECTS = i2cscan.com rtcds7.com i2clcd.com srom.com
 DEST = ../../../../Binary/Apps/Test/
 TOOLS = ../../../../Tools
 

Source/Apps/Test/I2C/i2cscan.asm

@@ -5,12 +5,13 @@
 ; MARCO MACCAFERRI, HTTPS://WWW.MACCASOFT.COM
 ; HBIOS VERSION BY PHIL SUMMERS (B1ACKMAILER) DIFFICULTLEVELHIGH@GMAIL.COM
 ;
-PCF	.EQU	1
-P8X180	.EQU	0
-SC126	.EQU	0
-SC137	.EQU	0
+PCFECB		.EQU	0
+PCFDUO		.EQU	1
+P8X180		.EQU	0
+SC126		.EQU	0
+SC137		.EQU	0
 ;
-#IF (PCF)
+#IF (PCFECB)
 I2C_BASE 	.EQU  	0F0H
 PCF_ID   	.EQU  	0AAH
 CPU_CLK	 	.EQU  	12
@@ -20,6 +21,16 @@ PCF_RS1  	.EQU  	PCF_RS0+1
 PCF_OWN	 	.EQU  	(PCF_ID >> 1)        	; PCF'S ADDRESS IN SLAVE MODE
 #ENDIF
 ;
+#IF (PCFDUO)
+I2C_BASE 	.EQU  	056H
+PCF_ID   	.EQU  	0AAH
+CPU_CLK	 	.EQU  	12
+;
+PCF_RS0  	.EQU  	I2C_BASE
+PCF_RS1  	.EQU  	PCF_RS0+1
+PCF_OWN	 	.EQU  	(PCF_ID >> 1)        	; PCF'S ADDRESS IN SLAVE MODE
+#ENDIF
+;
 #IF (P8X180)
 I2C_BASE	.EQU	0A0h
 _sda		.EQU	0
@@ -153,8 +164,11 @@ lp5f:	ld	a,(addr)	; next address
 	jp	0
 
 signon:	.db	"I2C Bus Scanner"
-#IF (PCF)
-	.DB	" - PCF8584"
+#IF (PCFECB)
+	.DB	" - PCF8584 (ECB)"
+#ENDIF
+#IF (PCFDUO)
+	.DB	" - PCF8584 (Duodyne)"
 #ENDIF
 #IF (SC126)
 	.DB	" - SC126"
@@ -219,7 +233,7 @@ _cout:				; character
 	ret
 
 ;-----------------------------------------------------------------------------
-#IF (PCF)
+#IF (PCFECB | PCFDUO)
 _i2c_start:
 PCF_START:
         LD     A,PCF_START_  
@@ -418,7 +432,7 @@ PCF_PINFAIL 	.DB	"PIN FAIL$"
 PCF_BBFAIL	.DB	"BUS BUSY$"
 ;
 ;-----------------------------------------------------------------------------
-#IF (PCF)
+#IF (PCFECB | PCFDUO)
 _i2c_stop:  
 PCF_STOP: 
 	LD   	A,PCF_STOP_	; issue 

Source/Apps/XM/xmdm125.asm

@@ -720,12 +720,17 @@ NOBYE:	LXI	H,FCB+1		; Get primary option
 ; Send option processor
 ; Single option: "K"	- force 1k mode
 ;
-	INX	H		; Look for a 'K'
+	CALL	SNDOPC
+	CALL	SNDOPC
+	JMP	ALLSET
+SNDOPC:INX	H		; Look for an option
 	MOV	A,M
 	CPI	' '		; Is it a space?
-	JZ	ALLSET		; Then we're ready to send...
-	CPI	'K'
-	JNZ	OPTERR		; "K" is the only setable 2nd option
+	JNZ	CHKK
+	POP	PSW
+	JMP	ALLSET
+CHKK:	CPI	'K'
+	JNZ	CHK6TH		; If it's not K it should be a port number
 	LDA	MSPEED
 	CPI	MINKSP		; If less than MINKSP bps, ignore 1k
 	JC	ALLSET		; Request
@@ -733,7 +738,7 @@ NOBYE:	LXI	H,FCB+1		; Get primary option
 	STA	KFLAG		; First, force us to 1K mode
 	CALL	ILPRT
 	DB	'(1k protocol selected)',CR,LF,0
-	JMP	ALLSET		; That's it for send...
+	RET		; That's it for send...
 ;
 ; Receive option processor
 ; 3 or 4 options: "X"	- disable auto-protocol select
@@ -5789,4 +5794,4 @@ BDPTOS	EQU	83		; Print Time on System
 	 ENDIF			; BYEBDOS
 ;
 	END
-
+

Source/Apps/assign.asm

@@ -31,6 +31,7 @@
 ;   2022-02-28 [WBW] Use HBIOS to swap banks under CP/M 3
 ;                    Use CPM3 BDOS direct BIOS call to get DRVTBL adr
 ;   2023-06-19 [WBW] Update for revised DIODEVICE API
+;   2023-09-19 [WBW] Added CHUSB & CHSD device support
 ;_______________________________________________________________________________
 ;
 ; ToDo:
@@ -1920,8 +1921,8 @@ dev09	.db	"HDSK",0
 dev10	.db	"PPA",0
 dev11	.db	"IMM",0
 dev12	.db	"SYQ",0
-dev13	.equ	devunk
-dev14	.equ	devunk
+dev13	.db	"CHUSB",0
+dev14	.db	"CHSD",0
 dev15	.equ	devunk
 ;
 devcnt	.equ	10		; 10 devices defined
@@ -1942,10 +1943,10 @@ stack	.equ	$		; stack top
 ; Messages
 ;
 indent	.db	"   ",0
-msgban1	.db	"ASSIGN v1.6 for RomWBW CP/M ",0
+msgban1	.db	"ASSIGN v1.7 for RomWBW CP/M ",0
 msg22	.db	"2.2",0
 msg3	.db	"3",0
-msbban2	.db	", 16-Jun-2023",0
+msbban2	.db	", 19-Sep-2023",0
 msghb	.db	" (HBIOS Mode)",0
 msgub	.db	" (UBIOS Mode)",0
 msgban3	.db	"Copyright 2021, Wayne Warthen, GNU GPL v3",0

Source/BuildShared.cmd

@@ -4,6 +4,7 @@ setlocal
 pushd HDIAG && call Build || exit /b & popd
 pushd CBIOS && call Build || exit /b & popd
 pushd CPM22 && call Build || exit /b & popd
+pushd QPM && call Build || exit /b & popd
 pushd ZCPR && call Build || exit /b & popd
 pushd ZCPR-DJ && call Build || exit /b & popd
 pushd ZSDOS && call Build || exit /b & popd

Source/CBIOS/cbios.asm

@@ -3394,8 +3394,8 @@ DEV09	.DB	"HDSK$"
 DEV10	.DB	"PPA$"
 DEV11	.DB	"IMM$"
 DEV12	.DB	"SYQ$"
-DEV13	.EQU	DEVUNK
-DEV14	.EQU	DEVUNK
+DEV13	.DB	"CHUSB$"
+DEV14	.DB	"CHSD$"
 DEV15	.EQU	DEVUNK
 ;
 #ENDIF

Source/Clean.cmd

@@ -4,6 +4,7 @@ setlocal
 pushd HDIAG && call Clean.cmd & popd
 pushd Apps && call Clean.cmd & popd
 pushd CPM22 && call Clean.cmd & popd
+pushd QPM && call Clean.cmd & popd
 pushd ZCPR && call Clean.cmd & popd
 pushd ZCPR-DJ && call Clean.cmd & popd
 pushd ZSDOS && call Clean.cmd & popd

Source/Doc/UserGuide.md

@@ -58,8 +58,9 @@ produced by these developer communities:
 
 General features include:
 
+* Z80 Family CPUs including Z80, Z180, and Z280
 * Banked memory services for several banking designs
-* Disk drivers for RAM, ROM, Floppy, IDE, CF, and SD
+* Disk drivers for RAM, ROM, Floppy, IDE ATA/ATAPI, CF, SD, Zip, Iomega
 * Serial drivers including UART (16550-like), ASCI, ACIA, SIO
 * Video drivers including TMS9918, SY6545, MOS8563, HD6445
 * Keyboard (PS/2) drivers via VT8242 or PPI interfaces
@@ -195,6 +196,7 @@ below, **carefully** pick the appropriate ROM image for your hardware.
 | [Small Computer SC131 Z180 Pocket Computer]^5^                 | -       | SCZ180_sc131.rom   | 115200        |
 | [Small Computer SC140 Z180 CPU Module]^5^                      | Z50     | SCZ180_sc140.rom   | 115200        |
 | [Small Computer SC503 Z180 CPU Module]^5^                      | Z50     | SCZ180_sc503.rom   | 115200        |
+| [Small Computer SC700 Z180 CPU Module]^5^                      | RCBus   | SCZ180_sc700.rom   | 115200        |
 | [Dyno Z180 SBC]^6^                                             | Dyno    | DYNO_std.rom       | 38400         |
 | [Nhyodyne Z80 MBC]^1^                                          | MBC     | MBC_std.rom        | 38400         |
 | [Rhyophyre Z180 SBC]^1^                                        | -       | RPH_std.rom        | 38400         |
@@ -204,6 +206,7 @@ below, **carefully** pick the appropriate ROM image for your hardware.
 | [Z80-Retro SBC]^8^                                             | -       | Z80RETRO_std.rom   | 38400         |
 | [S100 Computers Z180]^9^                                       | S100    | S100_std.rom       | 38400         |
 | [Duodyne Z80 System]^1^                                        | Duo     | DUO_std.rom        | 38400         |
+| [Heath H8 Z80 System]                                          | H8      | HEATH_std.rom      | 115200        |
 
 | ^1^Designed by Andrew Lynch
 | ^2^Designed by Sergey Kiselev
@@ -2143,10 +2146,36 @@ regarding the RomWBW adaptation and customizations.
 
 #### Boot Disk
 
-There is no RomWBW-specific boot disk creation procedure.  QP/M
-comes with a QINSTALL which is used to install QPM over an existing
-CP/M 2 installation or to update an existing QPM disk.  `QINSTALL.COM`
-is included with the RomWBW distribution.
+
+To create or update a bootable QP/M Z-System disk, a special process
+is required.  QP/M is not provided in source format.  You are expected
+to install QP/M over an existing CP/M installation using the
+`QINSTALL.COM` application.
+
+To update an existing QP/M boot disk with the latest RomWBW CBIOS, you
+must use 2 steps: apply the generic CP/M system track, then reinstall
+the QP/M components.  To do this, you can perform the following steps:
+
+1. Boot to the existing QP/M disk.  At this point, drive A should be
+   the QP/M disk that you wish to update.  You may receive a warning
+   about CBIOS/HBIOS version mismatch.
+
+1. Use RomWBW `SYSCOPY` to place the stock RomWBW CP/M OS image
+   onto the system tracks of the QP/M boot disk:
+   
+   `SYSCOPY A:=x:CPM.SYS`
+   
+   where x is the drive letter of your ROM Disk.
+
+1. Run `QINSTALL` to overlay the QP/M OS components on your
+   QP/M boot disk.
+
+**WARNING**: `QINSTALL` has no mechanism for retaining previous
+non-default settings.  Any previous non-default settings you
+previously made with `QINSTALL` will need to be reapplied.  The
+pre-built RomWBW QP/M disk image includes a couple of specific
+non-default settings to optimize use with RomWBW.  Please review the
+notes in the ReadMe.txt file in Source/Images/d_qpm.
 
 #### Notes
 
@@ -2154,6 +2183,9 @@ is included with the RomWBW distribution.
   on the QPM binary distribution and has been minimally customized
   for RomWBW.
 
+- When booted, the QPM startup banner will indicate CP/M 2.2.  This
+  is because QPM uses the CP/M 2.2 CBIOS code.
+
 - QINSTALL is used to customize QPM.  It is included on the
   disk image.  You should review the notes in the ReadMe.txt
   file in Source/Images/d_qpm before making changes.
@@ -2308,26 +2340,35 @@ This application understands both FAT filesystems as well as CP/M filesystems.
 * Long filenames are not supported.  Files with long filenames will
   show up with their names truncated into the older 8.3 convention.
 * A FAT filesystem can be located on floppy or hard disk media.  For
-  hard disk media, the FAT filesystem must be located within a valid
-  FAT partition.
+  hard disk media, a valid FAT Filesystem partition must exist.
+* Note that CP/M (and compatible) OSes do not support all of the
+  filename characters that a modern computer does.  The following
+  characters are **not permitted** in a CP/M filename:
+
+  `< > . , ; : = ? * [ ] _ % | ( ) / \`
   
+  The FAT application does not auto-rename files when it encounters
+  invalid filenames.  It will just issue an error and quit.
+  Additionally, the error message is not very clear about the problem.
+
 ## FAT Filesystem Preparation
 
 In general, you can create media formatted with a FAT filesystem on
 your RomWBW computer or on your modern computer.  We will only be
 discussing the RomWBW-based approach here.
 
-In the case of a floppy disk, you can use the `FAT` application to
-format the floppy disk.  For example, if your floppy disk is on RomWBW
-disk unit 2, you could use `FAT FORMAT 2:`.  This will overwrite the
-floppy with a FAT filesystem and all previous contents will be lost.
-Once formatted this way, the floppy disk can be used in a floppy drive
-attached to a modern computer or it can be used on RomWBW using the
+In the case of a floppy disk, you can use the `FAT` application to 
+format the floppy disk.  The floppy disk must already be physically 
+formatted using RomWBW FDU or equivalent.  If your floppy disk is on 
+RomWBW disk unit 2, you could use `FAT FORMAT 2:`.  This will overwrite 
+the floppy with a FAT filesystem and all previous contents will be lost.
+Once formatted this way, the floppy disk can be used in a floppy drive 
+attached to a modern computer or it can be used on RomWBW using the 
 other `FAT` tool commands.
 
 In the case of hard disk media, it is necessary to have a FAT
 partition.  If you prepared your RomWBW hard disk media using the
-disk image process, then this partition will already be present and
+disk image process, then this partition will already be defined and
 you do not need to recreate it.  This default FAT partition is located
 at approximately 512MB from the start of your disk and it is 384MB in
 size.  So, your hard disk media must be 1GB or greater to use this
@@ -2375,8 +2416,13 @@ If your RomWBW system has multiple disk drives/slots, you can also just
 create a disk with your modern computer that is a dedicated FAT 
 filesystem disk.  You can use your modern computer to format the disk 
 (floppy, CF Card, SD Card, etc.), then insert the disk in your RomWBW 
-computer and access if using `FAT` based on its RomWBW unit number.
+computer and access it using `FAT` based on its RomWBW unit number.
 
+**WARNING**: Microsoft Windows will sometimes suggest reformatting
+partitions that it does not recognize.  If you are prompted to format
+a partition of your SD/CF Card when inserting the card into a Windows
+computer, you probably want to select Cancel.
+  
 ## FAT Application Usage
 
 Complete instructions for the `FAT` application are found in $doc_apps$.
@@ -3777,6 +3823,31 @@ the RomWBW HBIOS configuration.
 
 `\clearpage`{=latex}
 
+### Small Computer SC700 Z180 CPU Module
+
+|                   |                  |
+|-------------------|------------------|
+| ROM Image Files   | SCZ180_sc700.rom |
+| Console Baud Rate | 115200           |
+| Interrupts        | Mode 2           |
+
+ - CPU speed is detected at startup if DS1302 RTC is active
+   - Otherwise 18.432 MHz assumed
+ - System timer is generated by Z180 CPU
+ - Hardware auto-detected:
+   - DS1302 RTC
+   - Z180 ASCI Serial Ports
+   - SIO Serial Interface Module
+   - EP Dual UART Serial Interface Module
+   - WDC Floppy Disk Controller w/ 3.5" HD Drives
+   - IDE Hard Disk Interface Module
+   - PPIDE Hard Disk Interface Module
+   - Onboard SD Card Interface
+ - Use of Interrupt Mode 2 requires proper IEI/IEO configuration
+   for all peripherals generating interrupts
+
+`\clearpage`{=latex}
+
 ### Dyno Z180 SBC
 
 |                   |                |
@@ -3953,26 +4024,38 @@ the RomWBW HBIOS configuration.
 |-------------------|---------------|
 | ROM Image File    | DUO_std.rom   |
 | Console Baud Rate | 38400         |
-| Interrupts        | None          |
+| Interrupts        | Mode 2        |
 
  - CPU speed is detected at startup if DS1302 RTC is active
    - Otherwise 8.000 MHz assumed
  - System timer is generated by CTC if available
  - Hardware auto-detected:
    - DS1302 RTC
-   - Zilog CTC
    - Zilog DMA Module
    - UART Serial Adapter
-   - SIO Serial Interface
-   - LPT Printer Interface
-   - Zilog Parallel Interface
-   - CVDU Display Adapter
-   - TMS9938/58 Display Adapter
-   - PS/2 Keyboard Interface
-   - AY-3-8910/YM2149 Sound Module
-   - Floppy Disk Controller w/ 3.5" HD Drives
-   - PPIDE Hard Disk Interface
- - Interrupts may be enabled in build options
+
+`\clearpage`{=latex}
+
+### Heath H8 Z80 System
+
+|                   |               |
+|-------------------|---------------|
+| ROM Image File    | HEATH_std.rom |
+| Console Baud Rate | 115200        |
+| Interrupts        | Mode 1        |
+
+ - CPU speed is detected at startup if DS1302 RTC is active
+   - Otherwise 7.3728 MHz assumed
+ - Hardware auto-detected:
+   - DS1302 RTC
+   - ACIA Serial Interface Module
+   - SIO Serial Interface Module
+   - EP Dual UART Serial Interface Module
+   - WDC Floppy Disk Controller w/ 3.5" HD Drives
+   - IDE Hard Disk Interface Module
+   - PPIDE Hard Disk Interface Module
+ - Serial baud rate is usually determined by hardware for ACIA and
+   SIO interfaces
 
 `\clearpage`{=latex}
 
@@ -3998,7 +4081,7 @@ may be discovered by RomWBW in your system.
 | FD        | Disk     | 8272 or compatible Floppy Disk Controller              |
 | GDC       | Video    | uPD7220 Video Display Controller                       |
 | HDSK      | Disk     | SIMH Simulator Hard Disk                               |
-| IDE       | Disk     | IDE/ATA Hard Disk Interface                            |
+| IDE       | Disk     | IDE/ATA/ATAPI Hard Disk Interface                      |
 | ICM       | DsKy     | ICM7218-based Display/Keypad on PPI                    |
 | IMM       | Disk     | IMM Zip Drive on PPI                                   |
 | INTRTC    | RTC      | Interrupt-based Real Time Clock                        |
@@ -4010,7 +4093,7 @@ may be discovered by RomWBW in your system.
 | I2C       | System   | I2C Interface                                          |
 | PIO       | Char     | Zilog Parallel Interface Controller                    |
 | PKD       | DsKy     | P8279-based Display/Keypad on PPI                      |
-| PPIDE     | Disk     | 8255 IDE/ATA Hard Disk Interface                       |
+| PPIDE     | Disk     | 8255 IDE/ATA/ATAPI Hard Disk Interface                 |
 | PPA       | Disk     | PPA Zip Drive on PPI                                   |
 | PPK       | Kbd      | Matrix Keyboard                                        |
 | PPPSD     | Disk     | ParPortProp SD Card Interface                          |

Source/HBIOS/Build.cmd

@@ -227,11 +227,13 @@ call Build SCZ180 sc130 || exit /b
 call Build SCZ180 sc131 || exit /b
 call Build SCZ180 sc140 || exit /b
 call Build SCZ180 sc503 || exit /b
+call Build SCZ180 sc700 || exit /b
 call Build DYNO std || exit /b
 call Build UNA std || exit /b
 call Build RPH std || exit /b
 call Build Z80RETRO std || exit /b
 call Build S100 std || exit /b
 call Build DUO std || exit /b
+call Build HEATH std || exit /b
 
 goto :eof

Source/HBIOS/Build.ps1

@@ -27,7 +27,7 @@ $ErrorAction = 'Stop'
 # UNA BIOS is simply imbedded, it is not built here.
 #
 
-$PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "Z80RETRO", "DUO", "UNA"
+$PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "Z80RETRO", "DUO", "UNA", "HEATH"
 $PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO", "RPH", "S100"
 $PlatformListZ280 = "RCZ280"
 

Source/HBIOS/Build.sh

@@ -38,11 +38,13 @@ if [ "${ROM_PLATFORM}" == "dist" ] ; then
 	ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc131"; bash Build.sh
 	ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc140"; bash Build.sh
 	ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc503"; bash Build.sh
+	ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc700"; bash Build.sh
 	ROM_PLATFORM="S100"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="UNA"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="Z80RETRO"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="ZETA"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="ZETA2"; ROM_CONFIG="std"; bash Build.sh
+	ROM_PLATFORM="HEATH"; ROM_CONFIG="std"; bash Build.sh
 	exit
 fi
 

Source/HBIOS/Config/DUO_std.asm

@@ -29,16 +29,20 @@
 CPUOSC		.SET	8000000		; CPU OSC FREQ IN MHZ
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
-INTMODE		.SET	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 ;
-DMAENABLE	.SET	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+;;;DMAENABLE	.SET	TRUE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 ;
 BATCOND		.SET	TRUE		; ENABLE LOW BATTERY WARNING MESSAGE
 ;
 ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
 RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ;
+PCFENABLE	.SET	TRUE		; ENABLE PCF8584 I2C CONTROLLER
+;
 MDFFENABLE	.SET	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
 UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 ;UARTCFG	.SET	UARTCFG | SER_RTS
+;
+ESPENABLE	.SET	TRUE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)

Source/HBIOS/Config/HEATH_std.asm

@@ -0,0 +1,69 @@
+;
+;==================================================================================================
+;   HEATH H8 Z80 STANDARD CONFIGURATION
+;==================================================================================================
+;
+; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
+; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
+; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
+; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
+; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
+; YOUR FILE IN THE BUILD PROCESS.
+;
+; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
+; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
+; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
+; SETTINGS.
+;
+; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
+; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
+; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
+; DIRECTORIES ABOVE THIS ONE).
+;
+#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
+;
+#include "cfg_rcz80.asm"
+;
+CPUOSC		.SET	7372800		; CPU OSC FREQ IN MHZ
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+;
+DSKYENABLE	.SET	TRUE		; ENABLES DSKY FUNCTIONALITY
+H8PENABLE	.SET	TRUE		; ENABLES HEATH H8 FRONT PANEL
+;
+FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+;
+DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
+UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+ACIAENABLE	.SET	TRUE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+;
+LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+;
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
+MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+;
+AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
+AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+;
+FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
+;
+IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.SET	SDMODE_PIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|USR]
+SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY
+IMMENABLE	.SET	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+;
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)

Source/HBIOS/Config/MK4_std.asm

@@ -47,7 +47,7 @@ VGAENABLE	.SET	TRUE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_DIDE	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_DIDE	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)

Source/HBIOS/Config/RCZ180_ext.asm

@@ -58,7 +58,7 @@ AYMODE		.SET	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LI
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)

Source/HBIOS/Config/RCZ180_nat.asm

@@ -57,7 +57,7 @@ AYMODE		.SET	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LI
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)

Source/HBIOS/Config/RCZ280_ext.asm

@@ -56,7 +56,7 @@ AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LIN
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)

Source/HBIOS/Config/RCZ280_nat.asm

@@ -56,7 +56,7 @@ AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LIN
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)

Source/HBIOS/Config/RCZ280_zz80mb.asm

@@ -62,7 +62,7 @@ AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LIN
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)

Source/HBIOS/Config/RCZ280_zzrc.asm

@@ -70,7 +70,7 @@ AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LIN
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)

Source/HBIOS/Config/RCZ80_easy.asm

@@ -41,6 +41,7 @@ WDOGIO		.SET	$6F		; WATCHDOG REGISTER ADR
 ;
 DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+INTRTCENABLE	.SET	TRUE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
 CTCENABLE	.SET	TRUE		; ENABLE ZILOG CTC SUPPORT
 CTCTIMER	.SET	TRUE		; ENABLE CTC PERIODIC TIMER
@@ -69,7 +70,7 @@ AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LIN
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)

Source/HBIOS/Config/RCZ80_jbl.asm

@@ -69,7 +69,7 @@ AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LIN
 SN76489ENABLE	.SET	TRUE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)

Source/HBIOS/Config/RCZ80_kio.asm

@@ -66,7 +66,7 @@ AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LIN
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)

Source/HBIOS/Config/RCZ80_skz.asm

@@ -61,7 +61,7 @@ AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LIN
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)

Source/HBIOS/Config/RCZ80_std.asm

@@ -54,7 +54,7 @@ AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LIN
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)

Source/HBIOS/Config/RCZ80_tiny.asm

@@ -75,7 +75,7 @@ AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LIN
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 IDE0BASE	.SET	$90		; IDE 0: IO BASE ADDRESS

Source/HBIOS/Config/RCZ80_zrc.asm

@@ -53,7 +53,7 @@ AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LIN
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)

Source/HBIOS/Config/RCZ80_zrc_ram.asm

@@ -57,7 +57,7 @@ AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LIN
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)

Source/HBIOS/Config/S100_std.asm

@@ -27,18 +27,17 @@
 #include "cfg_s100.asm"
 ;
 CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
+CRTACT		.SET	TRUE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
 Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
-Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
-Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+Z180_MEMWAIT	.SET	1		; Z180: MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.SET	2		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 ;
 DSRTCENABLE	.SET	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 INTRTCENABLE	.SET	TRUE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
-UARTENABLE	.SET	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 ASCIENABLE	.SET	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
-ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
-SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SCONENABLE	.SET	TRUE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 ;
 IDEENABLE	.SET	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)

Source/HBIOS/Config/SBC_std.asm

@@ -45,7 +45,7 @@ VGAENABLE	.SET	TRUE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_DIO3	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_DIO3	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)

Source/HBIOS/Config/SCZ180_sc126.asm

@@ -59,7 +59,7 @@ AYMODE		.SET	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LI
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)

Source/HBIOS/Config/SCZ180_sc130.asm

@@ -60,7 +60,7 @@ AYMODE		.SET	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LI
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)

Source/HBIOS/Config/SCZ180_sc140.asm

@@ -54,7 +54,7 @@ AYMODE		.SET	AYMODE_LINC	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)

Source/HBIOS/Config/SCZ180_sc503.asm

@@ -54,7 +54,7 @@ AYMODE		.SET	AYMODE_LINC	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)

Source/HBIOS/Config/SCZ180_sc700.asm

@@ -0,0 +1,71 @@
+;
+;==================================================================================================
+;   SC700 STANDARD CONFIGURATION
+;==================================================================================================
+;
+; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
+; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
+; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
+; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
+; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
+; YOUR FILE IN THE BUILD PROCESS.
+;
+; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
+; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
+; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
+; SETTINGS.
+;
+; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
+; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
+; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
+; DIRECTORIES ABOVE THIS ONE).
+;
+#DEFINE PLATFORM_NAME "Small Computer SC700", " [", CONFIG, "]"
+;
+#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
+;
+#include "cfg_scz180.asm"
+;
+CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+;
+Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
+Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+;
+LEDENABLE	.SET	TRUE		; ENABLE STATUS LED (SINGLE LED)
+LEDPORT		.SET	$0E		; STATUS LED PORT ADDRESS
+;
+FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.SET	$00		; FP: PORT ADDRESS FOR FP LEDS
+;
+DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+INTRTCENABLE	.SET	TRUE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+;
+UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+ASCIENABLE	.SET	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+;
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
+MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+;
+AY38910ENABLE	.SET	TRUE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
+AYMODE		.SET	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+;
+FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+;
+IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+SDENABLE	.SET	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.SET	SDMODE_SC	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
+;
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)

Source/HBIOS/Config/ZETA2_std.asm

@@ -35,7 +35,7 @@ UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 UARTSBC		.SET	TRUE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_ZETA2	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_ZETA2	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
 SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)

Source/HBIOS/Config/ZETA_std.asm

@@ -35,7 +35,7 @@ UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 UARTSBC		.SET	TRUE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_ZETA	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_ZETA	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
 SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)

Source/HBIOS/ROM Layout.txt

@@ -1,4 +1,4 @@
-RomWBW ROM Layout Notes
+RomWBW ROM Layout
 
 Bank		Module		Start	Size
 ------		------		------	------		
@@ -24,4 +24,16 @@ Bank		Module		Start	Size
 3		imgpad2		0x0000	0x8000
 		<end>		0x8000
 
-4-N		ROM Disk Data
+4 - N		ROM Disk Data
+
+
+RomWBW RAM Layout
+
+Bank ID         Usage                   Physical Address
+-------         ------                  ----------------
+0x80-0x87       RAM Disk Data           0x80000-0xBFFFF
+0x88-0x8B       CP/M 3 Buffers          0xC0000-0xDFFFF
+0x8C            CP/M 3 OS               0xE0000-0xE7FFF
+0x8D            RomWBW HBIOS            0xE8000-0xEFFFF
+0x8E            User TPA                0xF0000-0xF7FFF
+0x8F            Common                  0xF8000-0xFFFFF

Source/HBIOS/cfg_duo.asm

@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW 2.X CONFIGURATION DEFAULTS FOR DUODYNE
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR DUODYNE
 ;==================================================================================================
 ;
 ; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_DUO		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
+PLATFORM	.EQU	PLT_DUO		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -29,7 +29,7 @@ BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
 CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_UNSUP	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	8000000		; CPU OSC FREQ IN MHZ
-INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
@@ -57,6 +57,9 @@ CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	(4915200/8)	; CTC CLOCK FREQUENCY
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$56		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -83,6 +86,7 @@ ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
 PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
@@ -123,14 +127,13 @@ UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
 UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
-UARTDUO		.EQU	TRUE		; UART: AUTO-DETECT DUODYNE UART
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
@@ -165,6 +168,7 @@ TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -226,6 +230,18 @@ SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$BE		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.EQU	$FF		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -234,6 +250,7 @@ PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
 ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+ESPCONENABLE	.EQU	TRUE		; ESP: ENABLE ESP32 CONSOLE IO DRIVER VIDEO/KBD SUPPORT
 ;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 HDSKTRACE	.EQU	1		; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -292,10 +309,9 @@ AYMODE		.EQU	AYMODE_MBC	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|
 ;
 SPKENABLE	.EQU	TRUE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
-DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
-DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_MBC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAENABLE	.EQU	TRUE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.EQU	$40		; DMA: DMA BASE ADDRESS
+DMAMODE		.EQU	DMAMODE_DUO	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
-
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_dyno.asm

@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW 2.X CONFIGURATION DEFAULTS FOR DYNO
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR DYNO
 ;==================================================================================================
 ;
 ; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_DYNO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
+PLATFORM	.EQU	PLT_DYNO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -60,6 +60,9 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -79,7 +82,14 @@ LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|RTC]
 LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
 LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
-DSKYENABLE	.EQU	FALSE		; ENABLES DSKY (DO NOT COMBINE WITH PPIDE)
+DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
@@ -126,14 +136,13 @@ UARTENABLE	.EQU	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
 UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
-UARTDUO		.EQU	FALSE		; UART: AUTO-DETECT DUODYNE UART
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
@@ -177,6 +186,7 @@ TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MS
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -237,6 +247,8 @@ SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -280,7 +292,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_heath.asm

@@ -0,0 +1,322 @@
+;
+;==================================================================================================
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR RCBUS Z80
+;==================================================================================================
+;
+; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
+; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
+; UNDER THIS DIRECTORY.
+;
+; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
+; FOR THE PLATFORM.
+;
+#DEFINE PLATFORM_NAME "RCBus", " [", CONFIG, "]"
+;
+#INCLUDE "hbios.inc"
+;
+PLATFORM	.EQU	PLT_HEATH	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+;
+BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+;
+CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.EQU	7372800		; CPU OSC FREQ IN MHZ
+INTMODE		.EQU	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;
+RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
+MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
+;
+RTCIO		.EQU	$C0		; RTC LATCH REGISTER ADR
+;
+KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+;
+CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
+CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
+CTCMODE		.EQU	CTCMODE_TIM16	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
+CTCPRE		.EQU	256		; PRESCALE CONSTANT (1-256)
+CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
+CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
+CTCOSC		.EQU	CPUOSC		; CTC CLOCK FREQUENCY
+;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
+SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+SKZDIV		.EQU	DIV_1		; UART CLK (CLK2) DIVIDER FOR Z80-512K
+;
+WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+WDOGIO		.EQU	$6E		; WATCHDOG REGISTER ADR
+;
+FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+;
+DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+;
+LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
+LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|RTC]
+LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
+LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+;
+DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+;
+BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYENABLE	.EQU	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+;
+DSRTCENABLE	.EQU	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
+DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+;
+DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+;
+BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+;
+INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+;
+RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
+HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+;
+DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+;
+DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+DUARTCNT	.EQU	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
+DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
+DUART0ACFG	.EQU	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
+DUART0BCFG	.EQU	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
+DUART1BASE	.EQU	$40		; DUART 1: BASE ADDRESS OF CHIP
+DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
+DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
+;
+UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
+UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
+UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
+UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
+UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
+UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+;
+ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+;
+Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+;
+ACIAENABLE	.EQU	TRUE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+ACIADEBUG	.EQU	FALSE		; ACIA: ENABLE DEBUG OUTPUT
+ACIACNT		.EQU	1		; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
+ACIA0BASE	.EQU	$80		; ACIA 0: REGISTERS BASE ADR
+ACIA0CLK	.EQU	CPUOSC		; ACIA 0: OSC FREQ IN HZ
+ACIA0DIV	.EQU	1		; ACIA 0: SERIAL CLOCK DIVIDER
+ACIA0CFG	.EQU	DEFSERCFG	; ACIA 0: SERIAL LINE CONFIG  (SEE STD.ASM)
+ACIA1BASE	.EQU	$40		; ACIA 1: REGISTERS BASE ADR
+ACIA1CLK	.EQU	CPUOSC		; ACIA 1: OSC FREQ IN HZ
+ACIA1DIV	.EQU	1		; ACIA 1: SERIAL CLOCK DIVIDER
+ACIA1CFG	.EQU	DEFSERCFG	; ACIA 1: SERIAL LINE CONFIG  (SEE STD.ASM)
+;
+SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.EQU	CPUOSC		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
+SIO1ACLK	.EQU	CPUOSC		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1ACFG	.EQU	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
+SIO1ACTCC	.EQU	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1BCLK	.EQU	CPUOSC		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1BCFG	.EQU	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
+SIO1BCTCC	.EQU	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+;
+XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+;
+VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
+TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+;
+MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+;
+FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+;
+RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+;
+IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.EQU	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT		.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.EQU	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE0BASE	.EQU	$10		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.EQU	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.EQU	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.EQU	TRUE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.EQU	TRUE		; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.EQU	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE1BASE	.EQU	$00		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.EQU	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.EQU	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.EQU	TRUE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.EQU	TRUE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.EQU	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE2BASE	.EQU	$00		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.EQU	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.EQU	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.EQU	TRUE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.EQU	TRUE		; IDE 2B (MASTER): 8 BIT XFER
+;
+PPIDEENABLE	.EQU	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.EQU	$20		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1BASE	.EQU	$00		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE2BASE	.EQU	$00		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+;
+SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+;
+PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+;
+PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
+HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+;
+LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTMODE		.EQU	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTCNT		.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
+LPTTRACE	.EQU	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+LPT0BASE	.EQU	$0C		; LPT 0: REGISTERS BASE ADR
+LPT1BASE	.EQU	$00		; LPT 1: REGISTERS BASE ADR
+;
+PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
+PPACNT		.EQU	1		; PPA: NUMBER OF PPA DEVICES (1-2)
+PPATRACE	.EQU	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPAMODE		.EQU	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
+PPA0BASE	.EQU	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
+PPA1BASE	.EQU	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
+;
+IMMENABLE	.EQU	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+IMMCNT		.EQU	1		; IMM: NUMBER OF IMM DEVICES (1-2)
+IMMTRACE	.EQU	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IMMMODE		.EQU	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
+IMM0BASE	.EQU	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
+IMM1BASE	.EQU	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
+;
+SYQENABLE	.EQU	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
+SYQCNT		.EQU	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
+SYQTRACE	.EQU	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SYQMODE		.EQU	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
+SYQ0BASE	.EQU	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQ1BASE	.EQU	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
+;
+PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+;
+UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+;
+SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
+SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
+;
+AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
+AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
+;
+SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+;
+DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.EQU	DMAMODE_RC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
+;
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_master.asm

@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW 2.X CONFIGURATION MASTER
+;   ROMWBW 3.X CONFIGURATION MASTER
 ;==================================================================================================
 ;
 ; THIS FILE IS *NOT* A REAL CONFIGURATION FILE.	 IT IS A MASTER TEMPLATE FILE
@@ -12,7 +12,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
+PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -87,6 +87,9 @@ CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	614400		; CTC CLOCK FREQUENCY
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -115,6 +118,7 @@ ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
 PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
@@ -162,14 +166,13 @@ UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
 UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
-UARTDUO		.EQU	FALSE		; UART: AUTO-DETECT DUODYNE UART
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
@@ -234,6 +237,7 @@ TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -295,6 +299,18 @@ SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$BE		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.EQU	$FF		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -368,7 +384,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_mbc.asm

@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW 2.X CONFIGURATION DEFAULTS FOR MBC
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR MBC
 ;==================================================================================================
 ;
 ; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_MBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
+PLATFORM	.EQU	PLT_MBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -54,6 +54,9 @@ CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	(4915200/8)	; CTC CLOCK FREQUENCY
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -80,6 +83,7 @@ ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
 PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
@@ -120,14 +124,13 @@ UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
 UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	TRUE		; UART: AUTO-DETECT DUAL UART
-UARTDUO		.EQU	FALSE		; UART: AUTO-DETECT DUODYNE UART
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
@@ -162,6 +165,7 @@ TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -223,6 +227,8 @@ SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -292,8 +298,7 @@ SPKENABLE	.EQU	TRUE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_MBC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_MBC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
-
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_mk4.asm

@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW 2.X CONFIGURATION FOR MARK IV
+;   ROMWBW 3.X CONFIGURATION FOR MARK IV
 ;==================================================================================================
 ;
 ; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_MK4		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
+PLATFORM	.EQU	PLT_MK4		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -60,6 +60,9 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$B0		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -86,6 +89,7 @@ ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
 PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
@@ -126,14 +130,13 @@ UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	TRUE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	TRUE		; UART: AUTO-DETECT 4UART UART
 UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
-UARTDUO		.EQU	FALSE		; UART: AUTO-DETECT DUODYNE UART
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
@@ -173,6 +176,7 @@ TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -233,6 +237,8 @@ SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	TRUE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -289,7 +295,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_ECB	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_ECB	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER 
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_n8.asm

@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW 2.X CONFIGURATION FOR N8
+;   ROMWBW 3.X CONFIGURATION FOR N8
 ;==================================================================================================
 ;
 ; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_N8		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
+PLATFORM	.EQU	PLT_N8		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -62,6 +62,9 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$B0		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -88,6 +91,7 @@ ICMPPIBASE	.EQU	N8_PPI0		; BASE I/O ADDRESS OF ICM PPI
 PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	N8_PPI0		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
@@ -128,14 +132,13 @@ UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	TRUE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	TRUE		; UART: AUTO-DETECT 4UART UART
 UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
-UARTDUO		.EQU	FALSE		; UART: AUTO-DETECT DUODYNE UART
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
@@ -175,6 +178,7 @@ TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -235,6 +239,8 @@ SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -282,7 +288,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER 
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_rcz180.asm

@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW 2.X CONFIGURATION DEFAULTS FOR RCBUS Z180 CPU
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR RCBUS Z180 CPU
 ;==================================================================================================
 ;
 ; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
+PLATFORM	.EQU	PLT_RCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -60,6 +60,9 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -85,7 +88,14 @@ LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|RTC]
 LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
 LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
-DSKYENABLE	.EQU	FALSE		; ENABLES DSKY (DO NOT COMBINE WITH PPIDE)
+DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
@@ -132,14 +142,13 @@ UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
 UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
-UARTDUO		.EQU	FALSE		; UART: AUTO-DETECT DUODYNE UART
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
@@ -183,6 +192,7 @@ TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MS
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -243,6 +253,18 @@ SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$BE		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.EQU	$FF		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -306,7 +328,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_rcz280.asm

@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW 2.X CONFIGURATION DEFAULTS FOR RCBUS Z280 CPU
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR RCBUS Z280 CPU
 ;==================================================================================================
 ;
 ; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RCZ280	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
+PLATFORM	.EQU	PLT_RCZ280	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
 CPUFAM		.EQU	CPU_Z280	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -60,6 +60,9 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -79,7 +82,14 @@ LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|RTC]
 LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
 LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
-DSKYENABLE	.EQU	FALSE		; ENABLES DSKY (DO NOT COMBINE WITH PPIDE)
+DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
@@ -126,14 +136,13 @@ UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
 UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
-UARTDUO		.EQU	FALSE		; UART: AUTO-DETECT DUODYNE UART
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
@@ -187,6 +196,7 @@ TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MS
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -247,6 +257,18 @@ SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$BE		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.EQU	$FF		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -310,7 +332,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z280	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_Z280	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_rcz80.asm

@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW 2.X CONFIGURATION DEFAULTS FOR RCBUS Z80
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR RCBUS Z80
 ;==================================================================================================
 ;
 ; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RCZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
+PLATFORM	.EQU	PLT_RCZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -57,6 +57,9 @@ CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	CPUOSC		; CTC CLOCK FREQUENCY
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -78,7 +81,14 @@ LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|RTC]
 LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
 LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
-DSKYENABLE	.EQU	FALSE		; ENABLES DSKY (DO NOT COMBINE WITH PPIDE)
+DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
@@ -125,14 +135,13 @@ UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
 UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
-UARTDUO		.EQU	FALSE		; UART: AUTO-DETECT DUODYNE UART
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
@@ -181,6 +190,7 @@ TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MS
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -241,6 +251,18 @@ SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$BE		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.EQU	$FF		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -304,7 +326,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_RC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_RC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_rph.asm

@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW 2.X CONFIGURATION FOR RHYOPHYRE
+;   ROMWBW 3.X CONFIGURATION FOR RHYOPHYRE
 ;==================================================================================================
 ;
 ; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RPH		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
+PLATFORM	.EQU	PLT_RPH		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	TRUE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -60,6 +60,9 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$B0		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -84,8 +87,9 @@ DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
 ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
 ICMPPIBASE	.EQU	RPH_PPI0	; BASE I/O ADDRESS OF ICM PPI
 PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
-PKDPPIBASE	.EQU	RPH_PPI0		; BASE I/O ADDRESS OF PKD PPI
+PKDPPIBASE	.EQU	RPH_PPI0	; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
@@ -126,14 +130,13 @@ UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
 UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
-UARTDUO		.EQU	FALSE		; UART: AUTO-DETECT DUODYNE UART
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
@@ -164,6 +167,7 @@ TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -224,6 +228,8 @@ SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	FALSE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -253,7 +259,7 @@ PIO4BASE	.EQU	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIOZBASE	.EQU	$88		; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
 PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
-PIOSBASE	.EQU	RPH_PPI0		; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
+PIOSBASE	.EQU	RPH_PPI0	; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
 ;
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 FIFO_BASE	.EQU	$0C		; UF: REGISTERS BASE ADR
@@ -271,7 +277,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_s100.asm

@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW 2.X CONFIGURATION DEFAULTS FOR S100 Z180
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR S100 Z180
 ;==================================================================================================
 ;
 ; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_S100	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
+PLATFORM	.EQU	PLT_S100	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -46,8 +46,8 @@ MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ;
 Z180_BASE	.EQU	$C0		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
 Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
-Z180_MEMWAIT	.EQU	0		; Z180: MEMORY WAIT STATES (0-3)
-Z180_IOWAIT	.EQU	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+Z180_MEMWAIT	.EQU	1		; Z180: MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.EQU	2		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 Z180_TIMER	.EQU	TRUE		; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
 ;
 RTCIO		.EQU	$0C		; RTC LATCH REGISTER ADR
@@ -60,6 +60,9 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -74,12 +77,19 @@ FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
 ;
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
-LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
+LEDENABLE	.EQU	TRUE		; ENABLES STATUS LED (SINGLE LED)
 LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|RTC]
 LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
 LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
-DSKYENABLE	.EQU	FALSE		; ENABLES DSKY (DO NOT COMBINE WITH PPIDE)
+DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
@@ -122,18 +132,17 @@ DUART1BASE	.EQU	$40		; DUART 1: BASE ADDRESS OF CHIP
 DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
 DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
 ;
-UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTENABLE	.EQU	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
 UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
-UARTDUO		.EQU	FALSE		; UART: AUTO-DETECT DUODYNE UART
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
@@ -146,7 +155,7 @@ Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 ;
 ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ;
-SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
@@ -177,6 +186,7 @@ TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MS
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -237,6 +247,8 @@ SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -300,7 +312,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_sbc.asm

@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW 2.X CONFIGURATION DEFAULTS FOR SBC
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR SBC
 ;==================================================================================================
 ;
 ; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
+PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -54,6 +54,9 @@ CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	614400		; CTC CLOCK FREQUENCY
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -80,6 +83,7 @@ ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
 PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
@@ -120,14 +124,13 @@ UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	TRUE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	TRUE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	TRUE		; UART: AUTO-DETECT 4UART UART
 UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
-UARTDUO		.EQU	FALSE		; UART: AUTO-DETECT DUODYNE UART
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
@@ -162,6 +165,7 @@ TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -222,6 +226,8 @@ SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -270,7 +276,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_ECB	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_ECB	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_scz180.asm

@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW 2.X CONFIGURATION DEFAULTS FOR SC Z180 VARIANTS (SC126, SC130, ETC.)
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR SC Z180 VARIANTS (SC126, SC130, ETC.)
 ;==================================================================================================
 ;
 ; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_SCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
+PLATFORM	.EQU	PLT_SCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -60,6 +60,9 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -79,7 +82,14 @@ LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|RTC]
 LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
 LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
-DSKYENABLE	.EQU	FALSE		; ENABLES DSKY (DO NOT COMBINE WITH PPIDE)
+DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
@@ -126,14 +136,13 @@ UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
 UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
-UARTDUO		.EQU	FALSE		; UART: AUTO-DETECT DUODYNE UART
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
@@ -177,6 +186,7 @@ TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MS
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -237,6 +247,18 @@ SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$BE		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.EQU	$FF		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -300,7 +322,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_una.asm

@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW 2.X CONFIGURATION DEFAULTS FOR UNA
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR UNA
 ;==================================================================================================
 ;
 ; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -15,7 +15,7 @@
 ;
 #INCLUDE "../UBIOS/ubios.inc"
 ;
-;PLATFORM	.EQU	PLT_UNA		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
+;PLATFORM	.EQU	PLT_UNA		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_UNA	; HARDWARE BIOS: BIOS_[WBW|UNA]
 ;

Source/HBIOS/cfg_z80retro.asm

@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW 2.X CONFIGURATION DEFAULTS FOR SIMPLE Z80 RETRO
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR SIMPLE Z80 RETRO
 ;==================================================================================================
 ;
 ; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_Z80RETRO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
+PLATFORM	.EQU	PLT_Z80RETRO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -57,6 +57,9 @@ CTCPRECH	.EQU	0		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	1		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	7372800		; CTC CLOCK FREQUENCY
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -83,6 +86,7 @@ ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
 PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
@@ -118,14 +122,13 @@ UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
 UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
-UARTDUO		.EQU	FALSE		; UART: AUTO-DETECT DUODYNE UART
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
@@ -164,6 +167,7 @@ TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|M
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -196,6 +200,8 @@ SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
@@ -231,7 +237,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_zeta.asm

@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW 2.X CONFIGURATION DEFAULTS FOR ZETA V1
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR ZETA V1
 ;==================================================================================================
 ;
 ; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_ZETA	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
+PLATFORM	.EQU	PLT_ZETA	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; BIOS_[WBW|UNA]: HARDWARE BIOS
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -46,6 +46,9 @@ KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
 ;
 CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -72,6 +75,7 @@ ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
 PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
@@ -114,7 +118,6 @@ UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
 UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
-UARTDUO		.EQU	FALSE		; UART: AUTO-DETECT DUODYNE UART
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
@@ -134,6 +137,7 @@ TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|M
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -167,6 +171,8 @@ SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
@@ -202,7 +208,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_zeta2.asm

@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW 2.X CONFIGURATION DEFAULTS FOR ZETA V2
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR ZETA V2
 ;==================================================================================================
 ;
 ; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_ZETA2	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
+PLATFORM	.EQU	PLT_ZETA2	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -57,6 +57,9 @@ CTCPRECH	.EQU	0		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	1		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	921600		; CTC CLOCK FREQUENCY
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -83,6 +86,7 @@ ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
 PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
@@ -118,14 +122,13 @@ UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
 UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
-UARTDUO		.EQU	FALSE		; UART: AUTO-DETECT DUODYNE UART
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
@@ -145,6 +148,7 @@ TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|M
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -178,6 +182,8 @@ SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
@@ -213,7 +219,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
 YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/dma.asm

@@ -2,6 +2,18 @@
 ; Z80 DMA DRIVER
 ;==================================================================================================
 ;
+#IF ((DMAMODE == DMAMODE_ECB) | (DMAMODE == DMAMODE_MBC))
+DMA_IO		.EQU	DMABASE
+DMA_CTL		.EQU	DMABASE + 1
+DMA_USEHALF	.EQU	TRUE
+#ENDIF
+;
+#IF (DMAMODE == DMAMODE_DUO)
+DMA_IO		.EQU	DMABASE
+DMA_CTL		.EQU	DMABASE + 3
+DMA_USEHALF	.EQU	FALSE
+#ENDIF
+;
 DMA_CONTINUOUS			.equ 	%10111101	; + Pulse
 DMA_BYTE			.equ 	%10011101	; + Pulse
 DMA_BURST 			.equ	%11011101	; + Pulse
@@ -30,21 +42,18 @@ DMA_FORCE			.EQU	0
 ; DMA CLOCK SPEED CONTROL - OPTION TO SWITCH TO HALF CLOCK SPEED. MOST SYSTEMS NEED THIS.
 ;==================================================================================================
 ;
-DMA_USEHALF			.equ	TRUE	; USE CLOCK DIVIDER
-;
-#IF (DMA_USEHALF & (DMAMODE=DMAMODE_MBC))
-#DEFINE DMAIOHALF LD A,(HB_RTCVAL) \ AND ~%00001000 \ OUT (RTCIO),A
-#DEFINE DMAIOFULL PUSH AF \ LD A,(HB_RTCVAL) \ OUT (RTCIO),A \ POP AF
-#ENDIF
-;
-#IF (DMA_USEHALF & (DMAMODE=DMAMODE_ECB))
-#DEFINE DMAIOHALF LD A,(HB_RTCVAL) \ OR %00001000 \ OUT (RTCIO),A 
-#DEFINE DMAIOFULL PUSH AF \ LD A,(HB_RTCVAL) \ OUT (RTCIO),A \ POP AF
-#ENDIF
-;
-#IF (!DMA_USEHALF)
-#DEFINE DMAIOHALF \;
-#DEFINE DMAIOFULL \;
+#IF (DMA_USEHALF)
+  #IF (DMAMODE=DMAMODE_MBC)
+    #DEFINE DMAIOHALF LD A,(HB_RTCVAL) \ AND ~%00001000 \ OUT (RTCIO),A
+    #DEFINE DMAIOFULL PUSH AF \ LD A,(HB_RTCVAL) \ OUT (RTCIO),A \ POP AF
+  #ENDIF
+  #IF (DMAMODE=DMAMODE_ECB)
+    #DEFINE DMAIOHALF LD A,(HB_RTCVAL) \ OR %00001000 \ OUT (RTCIO),A 
+    #DEFINE DMAIOFULL PUSH AF \ LD A,(HB_RTCVAL) \ OUT (RTCIO),A \ POP AF
+  #ENDIF
+#ELSE
+  #DEFINE DMAIOHALF \;
+  #DEFINE DMAIOFULL \;
 #ENDIF
 ;
 ;==================================================================================================
@@ -54,11 +63,11 @@ DMA_USEHALF			.equ	TRUE	; USE CLOCK DIVIDER
 DMA_INIT:
 	CALL	NEWLINE
 	PRTS("DMA: IO=0x$")		; announce
-	LD	A, DMABASE
+	LD	A, DMA_IO
 	CALL	PRTHEXBYTE
 ;
 	LD	A,DMA_FORCE
-	out	(DMABASE+1),a		; force ready off
+	out	(DMA_CTL),a		; force ready off
 ;
 	DMAIOHALF
 ;
@@ -67,7 +76,7 @@ DMA_INIT:
 ;
 	ld	hl,DMACode		; program the
 	ld	b,DMACode_Len		; dma command
-	ld	c,DMABASE		; block
+	ld	c,DMA_IO		; block
 ;
 	di
 	otir				; load dma
@@ -103,31 +112,31 @@ DMA_FAIL_FLAG:
 ;==================================================================================================
 ;
 DMAProbe:
-	ld	a,DMA_RESET	
-	out	(DMABASE),a
-	ld	a,%01111101 		; R0-Transfer mode, A -> B, start address follows
-	out	(DMABASE),a
+	ld	a,DMA_RESET		; $C3
+	out	(DMA_IO),a
+	ld	a,%01111101 		; R0-Transfer mode, A -> B, start address follows $7D
+	out	(DMA_IO),a
 	ld	a,$cc
-	out	(DMABASE),a
+	out	(DMA_IO),a
 	ld	a,$dd
-	out	(DMABASE),a
+	out	(DMA_IO),a
 	ld	a,$e5
-	out	(DMABASE),a
+	out	(DMA_IO),a
 	ld	a,$1a
-	out	(DMABASE),a
-	ld	a,DMA_LOAD
-	out	(DMABASE),a
+	out	(DMA_IO),a
+	ld	a,DMA_LOAD		; $CF
+	out	(DMA_IO),a
 ;
-	ld	a,DMA_READ_MASK_FOLLOWS	; set up
-	out	(DMABASE),a		; for 
-	ld	a,%00011000		; register
-	out	(DMABASE),a		; read
-	ld	a,DMA_START_READ_SEQUENCE
-	out	(DMABASE),a
+	ld	a,DMA_READ_MASK_FOLLOWS	; set up ; $BB
+	out	(DMA_IO),a		; for 
+	ld	a,%00011000		; register $18
+	out	(DMA_IO),a		; read
+	ld	a,DMA_START_READ_SEQUENCE	; $A7
+	out	(DMA_IO),a
 ;
-	in	a,(DMABASE)		; read in 
+	in	a,(DMA_IO)		; read in 
 	ld	c,a			; address
-	in	a,(DMABASE)
+	in	a,(DMA_IO)
 	ld	b,a
 ;
 	xor	a			; is it
@@ -165,7 +174,7 @@ DMALDIR:
 ;
 	ld	hl,DMACopy		; program the
 	ld	b,DMACopy_Len		; dma command
-	ld	c,DMABASE		; block
+	ld	c,DMA_IO		; block
 ;
 	DMAIOHALF
 ;
@@ -174,8 +183,8 @@ DMALDIR:
 	ei
 ;
 	ld	a,DMA_READ_STATUS_BYTE	; check status
-	out	(DMABASE),a		; of transfer
-	in	a,(DMABASE)		; set non-zero
+	out	(DMA_IO),a		; of transfer
+	in	a,(DMA_IO)		; set non-zero
 	and	%00111011		; if failed
 	sub	%00011011
 
@@ -211,7 +220,7 @@ DMAOTIR:
 ;
 	ld	hl,DMAOutCode		; program the
 	ld	b,DMAOut_Len		; dma command
-	ld	c,DMABASE		; block
+	ld	c,DMA_IO		; block
 ;
 	DMAIOHALF
 
@@ -220,8 +229,8 @@ DMAOTIR:
 	ei
 ;
 	ld	a,DMA_READ_STATUS_BYTE	; check status
-	out	(DMABASE),a		; of transfer
-	in	a,(DMABASE)		; set non-zero
+	out	(DMA_IO),a		; of transfer
+	in	a,(DMA_IO)		; set non-zero
 	and	%00111011		; if failed
 	sub	%00011011
 ;
@@ -262,7 +271,7 @@ DMAINIR:
 ;
 	ld	hl,DMAInCode		; program the
 	ld	b,DMAIn_Len		; dma command
-	ld	c,DMABASE		; block
+	ld	c,DMA_IO		; block
 ;
 	DMAIOHALF
 ;
@@ -271,8 +280,8 @@ DMAINIR:
 	ei
 ;
 	ld	a,DMA_READ_STATUS_BYTE	; check status
-	out	(DMABASE),a		; of transfer
-	in	a,(DMABASE)		; set non-zero
+	out	(DMA_IO),a		; of transfer
+	in	a,(DMA_IO)		; set non-zero
 	and	%00111011		; if failed
 	sub	%00011011
 ;
@@ -306,31 +315,31 @@ DMAIn_Len 	.equ	$-DMAInCode
 ;
 DMARegDump:
 	ld	a,DMA_READ_MASK_FOLLOWS
-	out	(DMABASE),a
+	out	(DMA_IO),a
 	ld	a,%01111110
-	out	(DMABASE),a
+	out	(DMA_IO),a
 	ld	a,DMA_START_READ_SEQUENCE
-	out	(DMABASE),a
+	out	(DMA_IO),a
 ;
-	in	a,(DMABASE)
+	in	a,(DMA_IO)
 	ld	c,a
-	in	a,(DMABASE)
+	in	a,(DMA_IO)
 	ld	b,a
 	call	PRTHEXWORD
 	ld	a,':'
 	call	COUT
 ;
-	in	a,(DMABASE)
+	in	a,(DMA_IO)
 	ld	c,a
-	in	a,(DMABASE)
+	in	a,(DMA_IO)
 	ld	b,a
 	call	PRTHEXWORD
 	ld	a,':'
 	call	COUT
 ;
-	in	a,(DMABASE)
+	in	a,(DMA_IO)
 	ld	c,a
-	in	a,(DMABASE)
+	in	a,(DMA_IO)
 	ld	b,a
 	call	PRTHEXWORD
 ;

Source/HBIOS/ds7rtc.asm

@@ -5,6 +5,11 @@
 ;
 ;==================================================================================================
 ;
+#IF (!PCFENABLE)
+	.ECHO	"*** DS7 DRIVER REQUIRES PCF DRIVER.  SET PCFENABLE!!!\n"
+	!!!	; FORCE AN ASSEMBLY ERROR
+#ENDIF
+;
 DS7_OUT		.EQU	10000000B		; SELECT SQUARE WAVE FUNCTION
 DS7_SQWE	.EQU	00010000B		; ENABLE SQUARE WAVE OUTPUT
 DS7_RATE	.EQU	00000000B		; SET 1HZ OUPUT
@@ -31,6 +36,7 @@ DS7_CTL		.EQU	(DS7_OUT | DS7_SQWE | DS7_RATE)
 ; 12HR MODE IS CURRENTLY ASSUMED
 ;
 DS7RTC_INIT:
+	CALL	NEWLINE			; Formatting
 	PRTS("DS1307: $")		; ANNOUNCE DRIVER
 ;
 	LD	A,(PCF_FAIL_FLAG)	; CHECK IF THE

Source/HBIOS/esp.asm

@@ -7,20 +7,22 @@
 ;==================================================================================================
 ;
 ; TODO:
+; - CLEAR CONSOLE SCREEN AT INITIALIZATION
+; - INITIALIZE BAUD/MODE OF SERIAL INTERFACES AT INITIALIZATION?
 ;
 ESP_IOBASE	.EQU	$9C
 ESP_0_IO	.EQU	ESP_IOBASE + 0
 ESP_1_IO	.EQU	ESP_IOBASE + 1
 ESP_STAT	.EQU	ESP_IOBASE + 2
 ;
-; ESP  STATUS PORT
-; MSB XX S S S S S S
-;        | | | | | +- ESP0 READY OUTPUT
-;        | | | | +--- ESP0 BUSY
-;        | | | +----- ESP0 SPARE
-;        | | +------- ESP1 READY OUTPUT
-;        | +--------- ESP1 BUSY
-;        +----------- ESP1 SPARE
+; ESP   STATUS PORT
+; MSB X X S S S S S S
+;         | | | | | +- ESP0 READY OUTPUT
+;         | | | | +--- ESP0 BUSY
+;         | | | +----- ESP0 SPARE
+;         | | +------- ESP1 READY OUTPUT
+;         | +--------- ESP1 BUSY
+;         +----------- ESP1 SPARE
 ;
 ESP_0_RDY	.EQU	%00000001
 ESP_0_BUSY	.EQU	%00000010
@@ -31,13 +33,27 @@ ESP_1_SPARE	.EQU	%00100000
 ;
 ; COMMAND OPCODES
 ;
-ESP_CMD_NOP	.EQU	0		; NO OP
-ESP_CMD_COUT	.EQU	1		; CHAR OUT
-ESP_CMD_SOUT	.EQU	2		; STRING OUT
-ESP_CMD_KIN	.EQU	3		; KEY IN
-ESP_CMD_KST	.EQU	4		; KBD BUF STATUS
+ESP_CMD_NOP	.EQU	0		; NO OP/SYNC
+ESP_CMD_SYNC	.EQU	0		; NO OP/SYNC
+ESP_0_CMD_COUT	.EQU	1		; CHAR OUT
+ESP_0_CMD_CSTR	.EQU	2		; STRING OUT
+ESP_0_CMD_KIN	.EQU	3		; KEY IN
+ESP_0_CMD_KST	.EQU	4		; KBD BUF STATUS
+ESP_CMD_SBAUD	.EQU	6		; SET SERIAL BAUD RATE
+ESP_CMD_SMODE	.EQU	7		; SET SERIAL LINE MODE
+ESP_CMD_SOUT	.EQU	8		; SERIAL BYTE OUT
+ESP_CMD_SIN	.EQU	10		; SERIAL BYTE IN
+ESP_CMD_SST	.EQU	11		; SERIAL INPUT STATUS
 ESP_CMD_DISC	.EQU	$FF		; DISCOVER
 ;
+; ESP CONFIG TABLE ENTRY OFFSETS
+;
+ESP_CFG_DEV	.EQU	0		; DEVICE NUMBER
+ESP_CFG_IO	.EQU	1		; ESP I/O PORT
+ESP_CFG_ST	.EQU	2		; ESP STATUS PORT
+ESP_CFG_RDYMSK	.EQU	3		; ESP READY MASK
+ESP_CFG_BSYMSK	.EQU	4		; ESP BUSY MASK
+;
 ; GLOBAL ESP INITIALIZATION
 ;
 ESP_INIT:
@@ -47,16 +63,63 @@ ESP_INIT:
 	LD	A,ESP_IOBASE
 	CALL	PRTHEXBYTE
 ;
+	XOR	A			; ZERO ACCUM
+	LD	(ESP_PRES),A		; CLEAR MODULE PRESENCE BITS
+;
+	; DETECT FIRST ESP32 MODULE
+	PRTS(" A=$")
+	LD	IY,ESPSER0_CFG
 	CALL	ESP_DETECT
+	JR	Z,ESP_INIT1		; FOUND
 	LD	DE,ESP_STR_NOHW
-	JP	NZ,WRITESTR
+	CALL	WRITESTR
+	JR	ESP_INIT2
 ;
-	; PRINT FIRMWARE VERSION
-	PRTS(" F/W=$")
+ESP_INIT1:
 	CALL	ESP_PRTVER
+
+	LD	A,(ESP_PRES)
+	SET	0,A
+	LD	(ESP_PRES),A
+
 ;
+ESP_INIT2:
+	; DETECT SECOND ESP32 MODULE
+	PRTS(" B=$")
+	LD	IY,ESPSER1_CFG
+	CALL	ESP_DETECT
+	JR	Z,ESP_INIT3		; FOUND
+	LD	DE,ESP_STR_NOHW
+	CALL	WRITESTR
+	JR	ESP_INIT4
+;
+ESP_INIT3:
+	CALL	ESP_PRTVER
+
+	LD	A,(ESP_PRES)
+	SET	1,A
+	LD	(ESP_PRES),A
+
+;
+ESP_INIT4:
+	; INITIALIZE FIRST MODULE CHILD DRIVERS
+	LD	A,(ESP_PRES)
+	BIT	0,A
+	JR	Z,ESP_INIT5
+	LD	IY,ESPSER0_CFG
+	CALL	ESPSER_INIT		; SERIAL INITIALIZATION
+	LD	IY,ESPCON0_CFG
 	CALL	ESPCON_INIT		; CONSOLE INITIALIZATION
 ;
+ESP_INIT5:
+	; INITIALIZE SECOND MODULE CHILD DRIVERS
+	LD	A,(ESP_PRES)
+	BIT	1,A
+	JR	Z,ESP_INIT6
+	LD	IY,ESPSER1_CFG
+	CALL	ESPSER_INIT		; SERIAL INITIALIZATION
+;
+ESP_INIT6:
 	RET
 ;
 ;==================================================================================================
@@ -64,42 +127,100 @@ ESP_INIT:
 ;==================================================================================================
 ;
 ESP_DETECT:
+	; TRY TO DETECT IF PORT IS FLOATING AND
+	; FAIL DETECTION IF SO
+	LD	C,(IY+ESP_CFG_ST)	; ESP STATUS PORT
+	IN	A,(C)			; READ IT
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	AND	%11100000		; ISOLATE TOP 3 BITS
+	CP	$00			; ALWAYS ZERO IF PRESENT
+	RET	NZ			; ABORT ON FAILURE
+;
+	; ESP32 PROCESSOR MAY TAKE A FEW SECONDS TO START UP, SO
+	; HERE WE WAIT FOR BUSY TO CLEAR WITH ABOUT A 5 SECOND TIMEOUT
+	LD	B,0			; LOOP UP TO 256 TIMES
+	LD	C,(IY+ESP_CFG_ST)	; ESP STATUS PORT
+ESP_DETECT1:
+	IN	A,(C)			; GET STATUS
+	AND	(IY+ESP_CFG_BSYMSK)	; IS ESP BUSY?
+	JR	Z,ESP_DETECT2		; MOVE ALONG IF NOT BUSY
+	LD	DE,1500			; 1500 * 16US = 24MS
+	CALL	VDELAY			; DELAY
+	DJNZ	ESP_DETECT1		; LOOP
+	OR	$FF			; SIGNAL FAILURE
+	RET				; DONE
+;
+ESP_DETECT2:
+	CALL 	ESP_SYNC
+	;LD	A,B			; *DEBUG*
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
 	CALL	ESP_CLR			; CLEAR ANY PENDING DATA
-	RET	NZ			; IF FAILS, ASSUME NOT PRESENT
 	LD	A,ESP_CMD_DISC		; DISCOVER COMMAND
 	CALL	ESP_OUT			; SEND IT
-	LD	DE,10			; DELAY 160US
-	CALL	VDELAY			; ... TO ENSURE OUTPUT RDY SET
-	IN	A,(ESP_STAT)		; GET STATUS
-	AND	ESP_0_RDY		; ISOLATE OUTPUT READY BIT
-	XOR	ESP_0_RDY		; INVERT SO 0=FOUND
-	RET				; DONE
+;
+	; LOOK FOR SIGNATURE STARTING WITH "ESP"
+	CALL	ESP_INWAIT		; ATTEMPT TO GET CHAR
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CP	'E'
+	RET	NZ
+	CALL	ESP_INWAIT		; ATTEMPT TO GET CHAR
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CP	'S'
+	RET	NZ
+	CALL	ESP_INWAIT		; ATTEMPT TO GET CHAR
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CP	'P'
+	RET
 ;
 ; CLEAR ESP INPUT QUEUE
 ;
 ESP_CLR:
-	LD	B,0			; MAX CHARS TO READ
-ESP_CLR0:
+;	LD	B,0			; MAX CHARS TO READ   /Removed DDW
+;ESP_CLR0:   /Removed DDW
 	CALL	ESP_WTNBSY		; WAIT TILL NOT BUSY
+	RET	NZ			; BAIL OUT IF TIMEOUT
 	IN	A,(ESP_STAT)		; GET STATUS
-	AND	ESP_0_RDY		; IS THERE MORE DATA?
+	AND	(IY+ESP_CFG_RDYMSK)	; IS THERE MORE DATA?
 	RET	Z			; IF NOT, DONE
-	IN	A,(ESP_0_IO)		; GET CHAR
-	DJNZ	ESP_CLR0		; LOOP TILL DONE
-	OR	$FF			; SIGNAL FAILURE
+	LD	C,(IY+ESP_CFG_IO)	; ESP I/O PORT
+	IN	A,(C)			; GET BYTE
+	JP 	ESP_CLR
+;	DJNZ	ESP_CLR0		; LOOP TILL DONE /Removed DDW
+;	OR	$FF			; SIGNAL FAILURE /Removed DDW
+;	RET /Removed DDW
+
+;
+; RE-SYNC ESP  (added DDW)
+;
+ESP_SYNC:
+	LD	B,0				; sync count -- WORST CASE  PERFORMACE COULD BE IMPROVED BY REDUCING THIS VALUE
+ESP_SYNC0:
+	PUSH 	BC
+	LD	A,ESP_CMD_SYNC		; Sync ESP
+	CALL	ESP_OUT			; SEND CMD OPCODE
+	POP 	BC
+	DJNZ	ESP_SYNC0		; LOOP TILL DONE
 	RET
 ;
 ; PRINT ESP VERSION STRING TO CONSOLE
 ;
 ESP_PRTVER:
+	CALL 	ESP_SYNC
 	CALL	ESP_CLR			; CLEAR ANY PENDING DATA
+	;LD	DE,1000			; SMALL DELAY HERE
+	;CALL	VDELAY			; ... SEEMS TO HELP RELIABILITY
 	LD	A,ESP_CMD_DISC		; DISCOVER COMMAND
 	CALL	ESP_OUT			; SEND IT
 	CALL	ESP_WTRDY		; WAIT FOR READY TO OUTPUT
 ESP_PRTVER1:
 	CALL	ESP_WTNBSY		; WAIT TILL NOT BUSY
 	IN	A,(ESP_STAT)		; GET STATUS
-	AND	ESP_0_RDY		; ISOLATE OUTPUT READY BIT
+	AND	(IY+ESP_CFG_RDYMSK)	; ISOLATE OUTPUT READY BIT
 	RET	Z			; DONE IF NOTHING READY
 	CALL	ESP_IN			; GET NEXT CHAR
 	CALL	COUT			; PRINT CHAR
@@ -111,7 +232,8 @@ ESP_OUT:
 	PUSH	AF			; SAVE VALUE
 	CALL	ESP_WTNBSY		; WAIT TILL NOT BUSY
 	POP	AF			; POP VALUE
-	OUT	(ESP_0_IO),A		; SEND CHARACTER
+	LD	C,(IY+ESP_CFG_IO)	; ESP I/O PORT
+	OUT	(C),A			; SEND BYTE
 	JR	ESP_WTBSY		; RETURN VIA WTBSY
 ;
 ; GET BYTE FROM ESP (BLOCKING)
@@ -119,14 +241,15 @@ ESP_OUT:
 ESP_INWAIT:
 	CALL	ESP_WTNBSY		; WAIT TILL NOT BUSY
 	CALL	ESP_WTRDY		; WAIT FOR READY TO OUTPUT
-	; FALL THRU (GET CHAR VIA ESP_IN)
+	JP 		ESP_IN1			; Added DDW
 ;
 ; GET BYTE FROM ESP (NON BLOCKING)
 ;
 ESP_IN:
 	CALL	ESP_WTNBSY		; WAIT TILL NOT BUSY
-ESP_IN1:	
-	IN	A,(ESP_0_IO)		; GET BYTE
+ESP_IN1:
+	LD	C,(IY+ESP_CFG_IO)	; ESP I/O PORT
+	IN	A,(C)			; GET BYTE
 	PUSH	AF			; SAVE VALUE
 	CALL	ESP_WTBSY		; WAIT TILL BUSY
 	POP	AF			; RESTORE VALUE
@@ -136,44 +259,82 @@ ESP_IN1:
 ;
 ESP_WTNBSY:
 	LD	B,0			; MAX TRIES
-ESP_WTNBSY1:	
-	IN	A,(ESP_STAT)		; GET STATUS
-	AND	ESP_0_BUSY		; IS ESP BUSY?
+	;PUSH	HL			; SAVE HL
+	;LD	HL,0			; MAX TRIES
+ESP_WTNBSY1:
+	LD	C,(IY+ESP_CFG_ST)	; ESP STATUS PORT
+	IN	A,(C)			; GET STATUS
+	AND	(IY+ESP_CFG_BSYMSK)	; IS ESP BUSY?
 	RET	Z			; RETURN IF NOT BUSY
+	;JR	Z,ESP_WTNBSY_Z		; RETURN IF NOT BUSY
 	DJNZ	ESP_WTNBSY1		; ELSE LOOP
+	;DEC	HL			; DEC LOOP COUNTER
+	;LD	A,H			; CHECK FOR
+	;OR	L			; ... TIMEOUT
+	;JR	NZ,ESP_WTNBSY1		; LOOP AS NEEDED
+	;CALL	PC_ASTERISK		; *DEBUG*
 	OR	$FF			; SIGNAL TIMEOUT
+;ESP_WTNBSY_Z:
+	;POP	HL			; RECOVER HL
 	RET				; AND RETURN
 ;
 ; WAIT FOR ESP TO BE BUSY
 ;
 ESP_WTBSY:
-	LD	B,20			; MAX TRIES
-ESP_WTBSY1:	
-	IN	A,(ESP_STAT)		; GET STATUS
-	AND	ESP_0_BUSY		; IS ESP BUSY?
-	XOR	ESP_0_BUSY		; INVERT
+	LD	B,3			; MAX TRIES
+ESP_WTBSY1:
+	LD	C,(IY+ESP_CFG_ST)	; ESP STATUS PORT
+	IN	A,(C)			; GET STATUS
+	XOR	$FF			; INVERT SO 0=BUSY
+	AND	(IY+ESP_CFG_BSYMSK)	; IS ESP BUSY?
 	RET	Z			; RETURN IF BUSY
 	DJNZ	ESP_WTBSY1		; ELSE LOOP
 	OR	$FF			; SIGNAL TIMEOUT
 	RET				; AND RETURN
+;;;;
+;;;; WAIT FOR ESP TO BE READY TO OUTPUT
+;;;;
+;;;ESP_WTRDY:
+;;;	PUSH	HL			; SAVE HL
+;;;	LD	HL,0			; MAX TRIES
+;;;ESP_WTRDY1:
+;;;	LD	C,(IY+ESP_CFG_ST)	; ESP STATUS PORT
+;;;	IN	A,(C)			; GET STATUS
+;;;	XOR	$FF			; INVERT SO 0=READY
+;;;	AND	(IY+ESP_CFG_RDYMSK)	; IS ESP READY TO OUTPUT
+;;;	JR	Z,ESP_WTRDY_Z		; RETURN IF READY
+;;;	DEC	HL			; DEC LOOP COUNTER
+;;;	LD	A,H			; CHECK FOR
+;;;	OR	L			; ... TIMEOUT
+;;;	JR	NZ,ESP_WTRDY1		; LOOP AS NEEDED
+;;;	CALL	PC_PERIOD		; *DEBUG*
+;;;	OR	$FF			; SIGNAL TIMEOUT
+;;;ESP_WTRDY_Z:
+;;;	POP	HL			; RECOVER HL
+;;;	RET				; AND RETURN
 ;
 ; WAIT FOR ESP TO BE READY TO OUTPUT
 ;
 ESP_WTRDY:
 	LD	B,0			; MAX TRIES
 ESP_WTRDY1:
-	IN	A,(ESP_STAT)		; GET STATUS
-	AND	ESP_0_RDY		; IS ESP READY TO OUTPUT
-	XOR	ESP_0_RDY		; INVERT, 0=READY
+	LD	C,(IY+ESP_CFG_ST)	; ESP STATUS PORT
+	IN	A,(C)			; GET STATUS
+	XOR	$FF			; INVERT SO 0=READY
+	AND	(IY+ESP_CFG_RDYMSK)	; IS ESP READY TO OUTPUT
 	RET	Z			; RETURN IF READY
 	DJNZ	ESP_WTRDY1		; ELSE LOOP
+	;CALL	PC_PERIOD		; *DEBUG*
+	CALL 	ESP_SYNC 		; SOMETHING WENT WRONG, ENSURE SYNC (Added DDW)
 	OR	$FF			; SIGNAL TIMEOUT
 	RET				; AND RETURN
 ;
 ;
 ;
-ESP_STR_NOHW		.TEXT	" NOT PRESENT$"
-ESP_STR_UPGRADE		.TEXT	" !!!UPGRADE REQUIRED!!!$"
+ESP_PRES		.DB	0	; MODULE PRESENCE BITS
+;
+ESP_STR_NOHW		.TEXT	"NOT PRESENT$"
+ESP_STR_UPGRADE		.TEXT	"!!!UPGRADE REQUIRED!!!$"
 ;
 ;==================================================================================================
 ; ESP32 CONSOLE DRIVER
@@ -186,9 +347,26 @@ ESPCON_COLS	.EQU	80		; VGA DISPLAY COLS
 ;
 ;
 ESPCON_INIT:
+	LD	A,(ESPCON_DEVCNT)	; GET ESPCON PHYSICAL DEVICE COUNT
+	LD	(IY+ESP_CFG_DEV),A	; SAVE PHYSICAL UNIT NUMBER
+	INC	A			; UPDATE COUNT
+	LD	(ESPCON_DEVCNT),A	; SAVE COUNT
 ;
-	CALL	NEWLINE
-	PRTS("ESPCON:$")
+; ADD OURSELVES TO CIO DISPATCH TABLE
+;
+	LD	BC,ESPCON_FNTBL		; BC := FUNCTION TABLE ADDRESS
+	PUSH	IY			; COPY CONFIG ENTRY PTR
+	POP	DE			; ... TO DE
+	CALL	CIO_ADDENT		; ADD ENTRY, A := UNIT ASSIGNED
+	LD	(HCB + HCB_CRTDEV),A	; SET OURSELVES AS THE CRT DEVICE
+;
+; ANNOUNCE OURSLEVES
+;
+	CALL	NEWLINE			; FORMATTING
+	PRTS("ESPCON$")			; NAME
+	LD	A,(IY+ESP_CFG_DEV)	; GET PHYSICAL UNIT NUMBER
+	CALL	PRTDECB			; UNIT STILL IN A FROM ABOVE
+	CALL	PC_COLON		; FORMATTING
 ;
 	; DISPLAY CONSOLE DIMENSIONS
 	CALL	PC_SPACE
@@ -200,14 +378,6 @@ ESPCON_INIT:
 	CALL	PRTDECB
 	CALL	PRTSTRD
 	.TEXT	" TEXT (ANSI)$"
-;
-; ADD OURSELVES TO CIO DISPATCH TABLE
-;
-	LD	D,0			; PHYSICAL UNIT IS ZERO
-	LD	E,CIODEV_ESPCON		; DEVICE TYPE
-	LD	BC,ESPCON_FNTBL		; BC := FUNCTION TABLE ADDRESS
-	CALL	CIO_ADDENT		; ADD ENTRY, A := UNIT ASSIGNED
-	LD	(HCB + HCB_CRTDEV),A	; SET OURSELVES AS THE CRT DEVICE
 ;
 	XOR	A			; SIGNAL SUCCESS
 	RET
@@ -231,7 +401,7 @@ ESPCON_FNTBL:
 ESPCON_IN:
 	CALL	ESPCON_IST
 	JR	Z,ESPCON_IN
-	LD	A,ESP_CMD_KIN		; KBD INPUT
+	LD	A,ESP_0_CMD_KIN		; KBD INPUT
 	CALL	ESP_OUT			; SEND CMD OPCODE
 	CALL	ESP_INWAIT		; GET KEY
 	LD	E,A			; PUT IN E
@@ -241,7 +411,8 @@ ESPCON_IN:
 ;
 ;
 ESPCON_IST:
-	LD	A,ESP_CMD_KST		; KBD BUF STATUS
+	CALL	ESP_CLR			; CLEAR ANY PENDING DATA (Added DDW)
+	LD	A,ESP_0_CMD_KST		; KBD BUF STATUS
 	CALL	ESP_OUT			; SEND CMD OPCODE
 	CALL	ESP_INWAIT		; GET BUF SIZE
 	OR	A			; SET FLAGS
@@ -253,7 +424,7 @@ ESPCON_IST:
 ;
 ESPCON_OUT:
 	PUSH	DE
-	LD	A,ESP_CMD_COUT		; CHAR OUT OPCODE
+	LD	A,ESP_0_CMD_COUT	; CHAR OUT OPCODE
 	CALL	ESP_OUT
 	POP	DE
 	LD	A,E
@@ -264,13 +435,16 @@ ESPCON_OUT:
 ;
 ;
 ESPCON_OST:
-	OR	$FF			; SIGNAL OUTPUT QUEUE READY
+	XOR	A			; ZERO ACCUM
+	INC	A			; ACCUM := 1 TO SIGNAL 1 BUFFER POSITION
 	RET				; RETURN
 ;
 ;
 ;
 ESPCON_INITDEV:
-	SYSCHKERR(ERR_NOTIMPL)
+	CALL 	ESP_CLR
+	CALL 	ESP_SYNC
+;	SYSCHKERR(ERR_NOTIMPL)  Removed DDW
 	RET
 ;
 ;
@@ -285,14 +459,242 @@ ESPCON_QUERY:
 ;
 ESPCON_DEVICE:
 	LD	D,CIODEV_ESPCON		; D := DEVICE TYPE
-	LD	E,0			; E := DEVICE NUM, ALWAYS 0
+	LD	E,(IY+ESP_CFG_DEV)	; E := DEVICE NUM
 	LD	C,$BF			; C := DEVICE TYPE, 0xBF IS PROP TERM
 	LD	H,0			; H := 0, DRIVER HAS NO MODES
-	LD	L,ESP_IOBASE		; L := BASE I/O ADDRESS
+	LD	L,(IY+ESP_CFG_IO)	; L := BASE I/O ADDRESS
 	XOR	A			; SIGNAL SUCCESS
 	RET
 ;
-;=============================================================================
-; DATA STORAGE
-;=============================================================================
+; ESPCON CONFIGURATION
 ;
+ESPCON_CFG:
+ESPCON0_CFG:
+	.DB	0				; DEVICE NUMBER (UPDATED DURING INIT)
+	.DB	ESP_0_IO			; ESP DATA PORT
+	.DB	ESP_STAT			; ESP STATUS PORT
+	.DB	ESP_0_RDY			; ESP READY BIT MASK
+	.DB	ESP_0_BUSY			; ESP BUSY BIT MASK
+;
+;
+;
+ESPCON_DEVCNT	.DB	0			; ESPCON DEVICES COUNT
+;
+;==================================================================================================
+; ESP32 SERIAL DRIVER
+;==================================================================================================
+;
+ESPSER_LINECFG		.EQU	SER_115200_8N1
+;
+ESPSER_CFG_LINE		.EQU	5
+;
+;
+;
+ESPSER_INIT:
+	LD	A,(ESPSER_DEVCNT)	; GET ESPSER PHYSICAL DEVICE COUNT
+	LD	(IY+ESP_CFG_DEV),A	; SAVE PHYSICAL UNIT NUMBER
+	INC	A			; UPDATE COUNT
+	LD	(ESPSER_DEVCNT),A	; SAVE COUNT
+;
+; ADD OURSELVES TO CIO DISPATCH TABLE
+;
+	LD	BC,ESPSER_FNTBL		; BC := FUNCTION TABLE ADDRESS
+	PUSH	IY			; COPY CONFIG ENTRY PTR
+	POP	DE			; ... TO DE
+	CALL	CIO_ADDENT		; ADD ENTRY, A := UNIT ASSIGNED
+;
+; ANNOUNCE OURSLEVES
+;
+	CALL	NEWLINE			; FORMATTING
+	PRTS("ESPSER$")			; NAME
+	LD	A,(IY+ESP_CFG_DEV)	; GET PHYSICAL UNIT NUMBER
+	CALL	PRTDECB			; UNIT STILL IN A FROM ABOVE
+	CALL	PC_COLON		; FORMATTING
+;
+	PRTS(" MODE=$")				; FORMATTING
+	LD	E,(IY+ESPSER_CFG_LINE+0)	; FIRST CONFIG BYTE TO E
+	LD	D,(IY+ESPSER_CFG_LINE+1)	; SECOND CONFIG BYTE TO D
+	CALL	PS_PRTSC0			; PRINT CONFIG
+;
+; TODO: PRINT SERIAL CONFIG
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; DRIVER FUNCTION TABLE
+;
+ESPSER_FNTBL:
+	.DW	ESPSER_IN
+	.DW	ESPSER_OUT
+	.DW	ESPSER_IST
+	.DW	ESPSER_OST
+	.DW	ESPSER_INITDEV
+	.DW	ESPSER_QUERY
+	.DW	ESPSER_DEVICE
+#IF (($ - ESPSER_FNTBL) != (CIO_FNCNT * 2))
+	.ECHO	"*** INVALID ESPSER FUNCTION TABLE ***\n"
+#ENDIF
+;
+;
+;
+ESPSER_IN:
+	CALL	ESPSER_IST
+	JR	Z,ESPSER_IN
+	LD	A,ESP_CMD_SIN		; SERIAL INPUT
+	CALL	ESP_OUT			; SEND CMD OPCODE
+	CALL	ESP_INWAIT		; GET KEY
+	LD	E,A			; PUT IN E
+	XOR	A			; SIGNAL SUCCES
+	RET				; AND DONE
+;
+;
+;
+ESPSER_IST:
+	CALL	ESP_CLR			; CLEAR ANY PENDING DATA (Added DDW)
+	LD	A,ESP_CMD_SST		; SERIAL STATUS
+	CALL	ESP_OUT			; SEND CMD OPCODE
+	CALL	ESP_INWAIT		; GET BUF SIZE
+	OR	A			; SET FLAGS
+	RET	Z			; AND DONE
+	OR	A
+	RET
+;
+;
+;
+ESPSER_OUT:
+	PUSH	DE
+	LD	A,ESP_CMD_SOUT		; CHAR OUT OPCODE
+	CALL	ESP_OUT
+	POP	DE
+	LD	A,E
+	CALL	ESP_OUT			; SEND CHAR VALUE
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+;
+;
+ESPSER_OST:
+	XOR	A			; ZERO ACCUM
+	INC	A			; ACCUM := 1 TO SIGNAL 1 BUFFER POSITION
+	RET				; RETURN
+;
+;
+;
+ESPSER_INITDEV:
+	CALL 	ESP_CLR
+	CALL 	ESP_SYNC
+	PUSH	DE			; SAVE INCOMING CONFIG WORD
+;
+	; XLATE NEW LINE MODE INTO C
+	LD	A,E
+	AND	%00111111		; ISOLATE MODE BITS
+	LD	C,0			; 8N1 = 0
+	CP	SER_DATA8 | SER_PARNONE | SER_STOP1
+	JR	Z,ESPSER_INITDEV1	; IF MATCH, DO IT
+	INC	C			; 8E1 = 1
+	CP	SER_DATA8 | SER_PAREVEN | SER_STOP1
+	JR	Z,ESPSER_INITDEV1	; IF MATCH, DO IT
+	INC	C			; 8O1 = 2
+	CP	SER_DATA8 | SER_PARODD | SER_STOP1
+	JR	Z,ESPSER_INITDEV1	; IF MATCH, DO IT
+	INC	C			; 7N1 = 3
+	CP	SER_DATA7 | SER_PARNONE | SER_STOP1
+	JR	Z,ESPSER_INITDEV1	; IF MATCH, DO IT
+	INC	C			; 7E1 = 4
+	CP	SER_DATA7 | SER_PAREVEN | SER_STOP1
+	JR	Z,ESPSER_INITDEV1	; IF MATCH, DO IT
+	INC	C			; 7O1 = 5
+	CP	SER_DATA7 | SER_PARODD | SER_STOP1
+	JR	Z,ESPSER_INITDEV1	; IF MATCH, DO IT
+	JR	NZ,ESPSER_INITDEV_ERR	; ELSE FAIL
+;
+ESPSER_INITDEV1:
+	; DECODE NEW BAUD RATE INTO DE:HL
+	LD	H,0
+	LD	A,D
+	AND	%00011111
+	LD	L,A
+	LD	DE,75
+	PUSH	BC			; SAVE NEW LINE MODE
+	CALL	DECODE			; DE:HL IS DECODED BAUD RATE
+	POP	BC			; RESTORE NEW LINE MODE
+	JR	NZ,ESPSER_INITDEV_ERR	; IF ERROR, FAIL
+;
+	; PROGRAM NEW LINE MODE
+	PUSH	BC
+	LD	A,ESP_CMD_SMODE
+	CALL	ESP_OUT
+	POP	BC
+	LD	A,C
+	;CALL	PRTHEXBYTE
+	;CALL	LDELAY
+	CALL	ESP_OUT
+;
+	; PROGRAM NEW BAUD RATE
+	LD	A,ESP_CMD_SBAUD
+	CALL	ESP_OUT
+	LD	A,L
+	CALL	ESP_OUT
+	LD	A,H
+	CALL	ESP_OUT
+	LD	A,E
+	CALL	ESP_OUT
+	LD	A,D
+	CALL	ESP_OUT
+;
+	; SAVE NEW LINE CONFIG WORD
+	POP	DE				; RESTORE CONFIG WORD
+	LD	(IY+ESPSER_CFG_LINE+0),E	; FIRST CONFIG BYTE
+	LD	(IY+ESPSER_CFG_LINE+1),D	; SECOND CONFIG BYTE
+;
+	XOR	A
+	RET
+;
+ESPSER_INITDEV_ERR:
+	POP	DE			; THROW AWAY CONFIG WORD ON STACK
+	OR	$FF
+	RET
+;
+;
+;
+ESPSER_QUERY:
+	LD	E,(IY+ESPSER_CFG_LINE+0)	; FIRST CONFIG BYTE TO E
+	LD	D,(IY+ESPSER_CFG_LINE+1)	; SECOND CONFIG BYTE TO D
+	LD	HL,0
+	XOR	A
+	RET
+;
+;
+;
+ESPSER_DEVICE:
+	LD	D,CIODEV_ESPSER		; D := DEVICE TYPE
+	LD	E,(IY+ESP_CFG_DEV)	; E := DEVICE NUM
+	LD	C,$00			; C := DEVICE TYPE, 0x00 IS RS-232
+	LD	H,0			; H := 0, DRIVER HAS NO MODES
+	LD	L,(IY+ESP_CFG_IO)	; L := BASE I/O ADDRESS
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; ESPSER CONFIGURATION
+;
+ESPSER_CFG:
+ESPSER0_CFG:
+	.DB	0				; DEVICE NUMBER (UPDATED DURING INIT)
+	.DB	ESP_0_IO			; ESP DATA PORT
+	.DB	ESP_STAT			; ESP STATUS PORT
+	.DB	ESP_0_RDY			; ESP READY BIT MASK
+	.DB	ESP_0_BUSY			; ESP BUSY BIT MASK
+	.DW	ESPSER_LINECFG			; LINE CONFIGURATION
+
+;
+ESPSER1_CFG:
+	.DB	0				; DEVICE NUMBER (UPDATED DURING INIT)
+	.DB	ESP_1_IO			; ESP DATA PORT
+	.DB	ESP_STAT			; ESP STATUS PORT
+	.DB	ESP_1_RDY			; ESP READY BIT MASK
+	.DB	ESP_1_BUSY			; ESP BUSY BIT MASK
+	.DW	ESPSER_LINECFG			; LINE CONFIGURATION
+;
+;
+;
+ESPSER_DEVCNT	.DB	0			; ESPSER DEVICES COUNT

Source/HBIOS/fd.asm

@@ -811,19 +811,27 @@ FD_DETECT:
 	IN	A,(FDC_MSR)	; READ MSR
 	;CALL	PC_SPACE	; *DEBUG*
 	;CALL	PRTHEXBYTE	; *DEBUG*
-	CP	$80
-	JR	Z,FD_DETECT1	; $80 IS OK
-	CP	$D0
-	JR	Z,FD_DETECT1	; $D0 IS OK
-	RET			; NOPE, ABORT WITH ZF=NZ
-;
-FD_DETECT1:
-	CALL	DLY32		; WAIT A BIT FOR FDC
-	IN	A,(FDC_MSR)	; READ MSR AGAIN
+	
+	CP	$D0		; SPECIAL CASE: DATA PENDING?
+	JR	NZ,FD_DETECT1	; NOPE, MOVE ALONG
+	IN	A,(FDC_DATA)	; SWALLOW THE PENDING DATA
+	CALL	DLY32		; SETTLE
+	IN	A,(FDC_MSR)	; ... AND REREAD THE STATUS
 	;CALL	PC_SPACE	; *DEBUG*
 	;CALL	PRTHEXBYTE	; *DEBUG*
-	CP	$80
-	RET			; $80 OK, ELSE NOT PRESENT
+
+FD_DETECT1:
+	CP	$80		; WE EXPECT $80
+	RET	Z		; IF SO, ALL DONE
+
+	; WE HAVE SEEN AN FDC THAT NEEDS A SECOND READ TO GET
+	; DESIRED VALUE, SO TRY ONE MORE TIME
+	CALL	DLY32		; WAIT A BIT
+	IN	A,(FDC_MSR)	; ... AND REREAD THE STATUS
+	;CALL	PC_SPACE	; *DEBUG*
+	;CALL	PRTHEXBYTE	; *DEBUG*
+	CP	$80		; CHECK FOR CORRECT VALUE
+	RET			; RETURN WITH ZF ACCORDING TO RESULT
 ;
 ; UNIT INITIALIZATION
 ;

Source/HBIOS/h8p.asm

@@ -0,0 +1,162 @@
+;
+;==================================================================================================
+; HEATH H8 FRONT PANEL (DISPLAY AND KEYBOARD) ROUTINES
+;==================================================================================================
+;
+; LED SEGMENTS (BIT VALUES)
+;
+;	+--02--+
+;	40    04
+;	+--01--+
+;	20    08
+;	+--10--+  80
+;
+;__H8P_PREINIT_______________________________________________________________________________________
+;
+;  CONFIGURE AND RESET PANEL
+;____________________________________________________________________________________________________
+;
+; HARDWARE RESET PRIOR TO ROMWBW CONSOLE INITIALIZATION
+;
+H8P_PREINIT:
+	LD	A,(DSKY_DISPACT)	; DSKY DISPATCHER ALREADY SET?
+	OR	A			; SET FLAGS
+	RET	NZ			; IF ALREADY ACTIVE, ABORT
+;
+	; REGISTER DRIVER WITH HBIOS
+	LD	BC,H8P_DISPATCH
+	CALL	DSKY_SETDISP
+;
+	RET
+;
+;__H8P_INIT__________________________________________________________________________________________
+;
+;  DISPLAY DSKY INFO ON ROMWBW CONSOLE
+;____________________________________________________________________________________________________
+;
+H8P_INIT:
+	CALL	NEWLINE			; FORMATTING
+	PRTS("H8P:$")			; DRIVER TAG
+;
+	RET				; DONE
+;
+; DSKY DEVICE FUNCTION DISPATCH ENTRY
+;   A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR
+;   B: FUNCTION (IN)
+;
+H8P_DISPATCH:
+	LD	A,B			; GET REQUESTED FUNCTION
+	AND	$0F			; ISOLATE SUB-FUNCTION
+	JP	Z,H8P_RESET		; RESET DSKY HARDWARE
+	DEC	A	
+	JP	Z,H8P_STAT		; GET KEYPAD STATUS
+	DEC	A	
+	JP	Z,H8P_GETKEY		; READ A KEY FROM THE KEYPAD
+	DEC	A	
+	JP	Z,H8P_SHOWHEX		; DISPLAY A 32-BIT BINARY VALUE IN HEX
+	DEC	A	
+	JP	Z,H8P_SHOWSEG		; DISPLAY SEGMENTS
+	DEC	A	
+	JP	Z,H8P_KEYLEDS		; SET KEYPAD LEDS
+	DEC	A	
+	JP	Z,H8P_STATLED		; SET STATUS LED
+	DEC	A	
+	JP	Z,H8P_BEEP		; BEEP DSKY SPEAKER
+	DEC	A
+	JP	Z,H8P_DEVICE		; DEVICE INFO
+	SYSCHKERR(ERR_NOFUNC)
+	RET
+;
+; RESET DSKY -- CLEAR DISPLAY AND KEYPAD FIFO
+;
+H8P_RESET:
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+;  CHECK FOR KEY PRESS, SAVE RAW VALUE, RETURN STATUS
+;
+H8P_STAT:
+	XOR	A			; ZERO KEYS PENDING (FOR NOW)
+	RET
+;
+;  WAIT FOR A DSKY KEYPRESS AND RETURN
+;
+H8P_GETKEY:
+	; PUT KEY VALUE IN REGISTER E
+	XOR	A			; SIGNAL SUCCESS	
+	RET
+;
+; DISPLAY HEX VALUE FROM DE:HL
+;
+H8P_SHOWHEX:
+	LD	BC,DSKY_HEXBUF		; POINT TO HEX BUFFER
+	CALL	ST32			; STORE 32-BIT BINARY THERE
+	LD	HL,DSKY_HEXBUF		; FROM: BINARY VALUE (HL)
+	LD	DE,DSKY_BUF		; TO: SEGMENT BUFFER (DE)
+	CALL	DSKY_BIN2SEG		; CONVERT
+	LD	HL,DSKY_BUF		; POINT TO SEGMENT BUFFER
+	; AND FALL THRU TO DISPLAY IT
+;
+; DISPLAY BYTE VALUES POINTED TO BY DE.  THE INCOMING BYTES ARE IN
+; THE STANDARD ROMWBW SEGMENT ENCODING AND MUST BE TRANSLATED TO THE
+; HEATH ENCODING (SEE ICM.ASM FOR EXAMPLE):
+;
+;
+;	From:		To:
+;	+--01--+	+--02--+
+;	20    02	40    04
+;	+--40--+	+--01--+
+;	10    04	20    08
+;	+--08--+  80	+--10--+  80
+;
+H8P_SHOWSEG:
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; UPDATE KEY LEDS (H8 HAS NONE)
+;
+H8P_KEYLEDS:
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; SET STATUS LEDS BASED ON BITS IN E
+;
+H8P_STATLED:
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; BEEP THE SPEAKER ON THE H8P
+;
+H8P_BEEP:
+	POP	BC
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; DEVICE INFORMATION
+;
+H8P_DEVICE:
+	LD	D,DSKYDEV_H8P		; D := DEVICE TYPE
+	LD	E,0			; E := PHYSICAL DEVICE NUMBER
+	LD	H,0			; H := MODE
+	LD	L,0			; L := BASE I/O ADDRESS
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+;_KEYMAP_TABLE_____________________________________________________________________________________________________________
+;
+H8P_KEYMAP:	; *** NEEDS TO BE UPDATED ***
+	; POS	$00  $01  $02  $03  $04  $05  $06  $07
+	; KEY   [0]  [1]  [2]  [3]  [4]  [5]  [6]  [7]
+	.DB	$0D, $04, $0C, $14, $03, $0B, $13, $02
+;
+	; POS	$08  $09  $0A  $0B  $0C  $0D  $0E  $0F
+	; KEY   [8]  [9]  [A]  [B]  [C]  [D]  [E]  [F]
+	.DB	$0A, $12, $01, $09, $11, $00, $08, $10
+;
+	; POS	$10  $11  $12  $13  $14  $15  $16  $17
+	; KEY   [FW] [BK] [CL] [EN] [DE] [EX] [GO] [BO]
+	.DB	$05, $15, $1D, $1C, $1B, $1A, $19, $18
+
+	; POS	$18  $19  $1A  $1B
+	; KEY   [F4] [F3] [F2] [F1]
+	.DB	$23, $22, $21, $20

Source/HBIOS/hbios.asm

@@ -105,13 +105,13 @@ MODCNT	.SET	MODCNT + 1
 ;
 ;
 #IF (FPLED_ENABLE)
-#DEFINE	DIAG(N)	PUSH AF
-  #DEFCONT \	LD A,N
-;  #DEFCONT \	OUT (DIAGPORT),A
-  #DEFCONT \	CALL	FP_SETLEDS
-  #DEFCONT \	POP AF
+  #DEFINE DIAG(N)	PUSH AF
+  #DEFCONT \		LD A,N
+;  #DEFCONT \		OUT (DIAGPORT),A
+  #DEFCONT \		CALL	FP_SETLEDS
+  #DEFCONT \		POP AF
 #ELSE
-#DEFINE	DIAG(N)	\;
+  #DEFINE		DIAG(N)	\;
 #ENDIF
 ;
 ; SCxxx: LED Port=0x0E, bit 2, inverted, dedicated port
@@ -119,31 +119,32 @@ MODCNT	.SET	MODCNT + 1
 ; Z80-512K: LED Port=0x6E, bit 0, inverted, dedicated port
 ; MBC: LED Port=0x70, bits 1-0, normal, shared w/ RTC port
 ; DUO: LED Port=0x94, bits 1-0, normal, shared w/ RTC port
+; S100: LED Port = $0E, bit 2, inverted, dedicated port
 ; 
 #IF (LEDENABLE)
   #IF (LEDMODE == LEDMODE_STD)
-#DEFINE	LED(N)	PUSH	AF
-  #DEFCONT \	LD	A,~N
-  #DEFCONT \	OUT	(LEDPORT),A
-  #DEFCONT \	POP	AF
+    #DEFINE LED(N)	PUSH	AF
+    #DEFCONT \		LD	A,~N
+    #DEFCONT \		OUT	(LEDPORT),A
+    #DEFCONT \		POP	AF
   #ENDIF
   #IF (LEDMODE == LEDMODE_RTC)
-#DEFINE LED(N)	PUSH	AF
-  #DEFCONT \	LD	A,(HB_RTCVAL)
-  #DEFCONT \	AND	%11111100
-  #DEFCONT \	OR	(N & %00000011)
-  #DEFCONT \	LD	(HB_RTCVAL),A
-  #DEFCONT \	OUT	(LEDPORT),A
-  #DEFCONT \	POP	AF
+    #DEFINE LED(N)	PUSH	AF
+    #DEFCONT \		LD	A,(HB_RTCVAL)
+    #DEFCONT \		AND	%11111100
+    #DEFCONT \		OR	(N & %00000011)
+    #DEFCONT \		LD	(HB_RTCVAL),A
+    #DEFCONT \		OUT	(LEDPORT),A
+    #DEFCONT \		POP	AF
   #ENDIF
 #ELSE
-#DEFINE	LED(N)	\;
+  #DEFINE LED(N)	\;
 #ENDIF
 ;
 #DEFINE SYSCHKERR(HB_ERR) \
-  #DEFCONT \	CALL	SYSCHKA
-  #DEFCONT \	LD	A,HB_ERR
-  #DEFCONT \	OR	A
+#DEFCONT \	CALL	SYSCHKA
+#DEFCONT \	LD	A,HB_ERR
+#DEFCONT \	OR	A
 ;
 ;
 ;
@@ -1110,7 +1111,17 @@ Z280_BOOTERR	.TEXT	"\r\n\r\n*** Application mode boot not supported under Z280 n
 ;
 	DI				; NO INTERRUPTS
 	IM	1			; INTERRUPT MODE 1
-
+;
+#IF ((PLATFORM == PLT_DUO) & TRUE)
+	; WAIT A WHILE
+	LD	HL,0
+BOOTWAIT:
+	DEC	HL
+	LD	A,H
+	OR	L
+	JR	NZ,BOOTWAIT
+#ENDIF
+;
 ;#IF ((PLATFORM == PLT_MBC) | (PLATFORM == PLT_SBC))
 	; INITIALIZE RTC LATCH BYTE
 	; FOR SOME PLATFORMS THIS CONTROLS HI/LO SPEED CIRCUIT
@@ -1911,12 +1922,14 @@ HB_CPU1:
   #IF (ICMENABLE)
 	CALL	ICM_PREINIT
   #ENDIF
-#ENDIF
 ;
-#IF (DSKYENABLE)
   #IF (PKDENABLE)
 	CALL	PKD_PREINIT
   #ENDIF
+;
+  #IF (H8PENABLE)
+	CALL	H8P_PREINIT
+  #ENDIF
 #ENDIF
 ;
 #IF (DSKYENABLE)
@@ -2131,11 +2144,40 @@ HB_CPU3:
 	LD	HL,HB_TIMINT
 	CALL	HB_ADDIM1		; ADD TO IM1 CALL LIST
     #ENDIF
-
+;
   #ENDIF
 ;
 #ENDIF
 ;
+; TEMPLATE FOR SETTING UP INTERRUPTS USING THE MBC/DUODYNE IM2 INTERRUPT
+; PIN HEADERS. UPDATE HB_DUMMYx TO POINT TO THE INTERRUPT ROUTINE.
+; IN STD.ASM ALLOCATE THE EQUIVALENT INT_IM2PHx INTERRUPT TABLE ENTRY NUMBER. 
+;
+;
+;	LD	HL,HB_DUMMY0
+;	LD	(IVT(INT_IM2PH0)),HL
+;
+;	LD	HL,HB_DUMMY1
+;	LD	(IVT(INT_IM2PH1)),HL
+;
+;	LD	HL,HB_DUMMY2
+;	LD	(IVT(INT_IM2PH2)),HL
+;
+;	LD	HL,HB_DUMMY3
+;	LD	(IVT(INT_IM2PH3)),HL
+;
+;	LD	HL,HB_DUMMY4
+;	LD	(IVT(INT_IM2PH4)),HL
+;
+;	LD	HL,HB_DUMMY5
+;	LD	(IVT(INT_IM2PH5)),HL
+;
+;	LD	HL,HB_DUMMY6
+;	LD	(IVT(INT_IM2PH6)),HL
+;
+;	LD	HL,HB_DUMMY7
+;	LD	(IVT(INT_IM2PH7)),HL
+;
 #IF (KIOENABLE)
 	CALL	KIO_PREINIT
 #ENDIF
@@ -2801,6 +2843,12 @@ HB_WDZ:
 	BIT	6,A			; BIT 6 HAS CONFIG JUMPER STATE
 	JR	Z,INITSYS3		; Z=SHORTED, BYPASS CONSOLE SWITCH
   #ENDIF
+;
+  #IF (PLATFORM == PLT_S100)
+	IN	A,($75)			; GET IO BYTE
+	AND	%00000001		; ISOLATE CONSOLE BIT
+	JR	NZ,INITSYS3		; NOT SET, BYPASS CONSOLE SWITCH
+  #ENDIF
 ;
 	LD	A,(CB_CRTDEV)		; GET CRT DISPLAY DEVICE
 	LD	(HB_NEWCON),A		; AND QUEUE TO SWITCH
@@ -3150,6 +3198,9 @@ HB_PCINITTBL:
 #IF (TMSENABLE)
 	.DW	TMS_PREINIT
 #ENDIF
+#IF (SCONENABLE)
+	.DW	SCON_PREINIT
+#ENDIF
 HB_PCINITTBLLEN	.EQU	(($ - HB_PCINITTBL) / 2)
 
 ;==================================================================================================
@@ -3163,15 +3214,19 @@ HB_INITTBL:
 #IF (CTCENABLE)
 	.DW	CTC_INIT
 #ENDIF
+#IF (PCFENABLE)
+	.DW	PCF_INIT
+#ENDIF
 #IF (DSKYENABLE)
   #IF (ICMENABLE)
 	.DW	ICM_INIT
   #ENDIF
-#ENDIF
-#IF (DSKYENABLE)
   #IF (PKDENABLE)
 	.DW	PKD_INIT
   #ENDIF
+  #IF (H8PENABLE)
+	.DW	H8P_INIT
+  #ENDIF
 #ENDIF
 #IF (AY38910ENABLE)
 	.DW	AY38910_INIT		; AUDIBLE INDICATOR OF BOOT START
@@ -3231,7 +3286,6 @@ HB_INITTBL:
 	.DW	INTRTC_INIT
 #ENDIF
 #IF (DS7RTCENABLE)
-	.DW	PCF8584_INIT
 	.DW	DS7RTC_INIT
 #ENDIF
 #IF (RP5RTCENABLE)
@@ -3252,6 +3306,9 @@ HB_INITTBL:
 #IF (TMSENABLE)
 	.DW	TMS_INIT
 #ENDIF
+#IF (SCONENABLE)
+	.DW	SCON_INIT
+#ENDIF
 #IF (VRCENABLE)
 	.DW	VRC_INIT
 #ENDIF
@@ -3294,6 +3351,9 @@ HB_INITTBL:
 #IF (PPPENABLE)
 	.DW	PPP_INIT
 #ENDIF
+#IF (CHENABLE)
+	.DW	CH_INIT
+#ENDIF
 #IF (ESPENABLE)
 	.DW	ESP_INIT
 #ENDIF
@@ -6109,9 +6169,7 @@ SIZ_ICM	.EQU	$ - ORG_ICM
 		.ECHO	SIZ_ICM
 		.ECHO	" bytes.\n"
   #ENDIF
-#ENDIF
 ;
-#IF (DSKYENABLE)
   #IF (PKDENABLE)
 ORG_PKD	.EQU	$
   #INCLUDE "pkd.asm"
@@ -6120,6 +6178,15 @@ SIZ_PKD	.EQU	$ - ORG_PKD
 		.ECHO	SIZ_PKD
 		.ECHO	" bytes.\n"
   #ENDIF
+;
+  #IF (H8PENABLE)
+ORG_H8P	.EQU	$
+  #INCLUDE "h8p.asm"
+SIZ_H8P	.EQU	$ - ORG_H8P
+		.ECHO	"H8P occupies "
+		.ECHO	SIZ_H8P
+		.ECHO	" bytes.\n"
+  #ENDIF
 #ENDIF
 ;
 #IF (DSRTCENABLE)
@@ -6148,6 +6215,7 @@ SIZ_BQRTC	.EQU	$ - ORG_BQRTC
 		.ECHO	SIZ_BQRTC
 		.ECHO	" bytes.\n"
 #ENDIF
+;
 #IF (SIMRTCENABLE)
 ORG_SIMRTC	.EQU	$
   #INCLUDE "simrtc.asm"
@@ -6156,15 +6224,16 @@ SIZ_SIMRTC	.EQU	$ - ORG_SIMRTC
 		.ECHO	SIZ_SIMRTC
 		.ECHO	" bytes.\n"
 #ENDIF
-#IF (DS7RTCENABLE & (DS7RTCMODE=DS7RTCMODE_PCF))
-ORG_PCF8584	.EQU	$
-  #INCLUDE "pcf8584.asm"
-SIZ_PCF8584	.EQU	$ - ORG_PCF8584
-		.ECHO	"PCF8584 occupies "
-		.ECHO	SIZ_PCF8584
+;
+#IF (PCFENABLE)
+ORG_PCF		.EQU	$
+  #INCLUDE "pcf.asm"
+SIZ_PCF		.EQU	$ - ORG_PCF
+		.ECHO	"PCF occupies "
+		.ECHO	SIZ_PCF
 		.ECHO	" bytes.\n"
 #ENDIF
-
+;
 #IF (DS7RTCENABLE)
 ORG_DS7RTC	.EQU	$
   #INCLUDE "ds7rtc.asm"
@@ -6311,12 +6380,21 @@ SIZ_VDU		.EQU	$ - ORG_VDU
 #IF (TMSENABLE)
 ORG_TMS		.EQU	$
   #INCLUDE "tms.asm"
-SIZ_TMS		.EQU	$ - ORG_TMS
+SIZ_TMS	.EQU	$ - ORG_TMS
 		.ECHO	"TMS occupies "
 		.ECHO	SIZ_TMS
 		.ECHO	" bytes.\n"
 #ENDIF
 ;
+#IF (SCONENABLE)
+ORG_SCON		.EQU	$
+  #INCLUDE "scon.asm"
+SIZ_SCON	.EQU	$ - ORG_SCON
+		.ECHO	"SCON occupies "
+		.ECHO	SIZ_SCON
+		.ECHO	" bytes.\n"
+#ENDIF
+;
 #IF (GDCENABLE)
 ORG_GDC	.EQU	$
   #INCLUDE "gdc.asm"
@@ -6450,6 +6528,15 @@ SIZ_PPP		.EQU	$ - ORG_PPP
 		.ECHO	" bytes.\n"
 #ENDIF
 ;
+#IF (CHENABLE)
+ORG_CH		.EQU	$
+  #INCLUDE "ch.asm"
+SIZ_CH		.EQU	$ - ORG_CH
+		.ECHO	"CH occupies "
+		.ECHO	SIZ_CH
+		.ECHO	" bytes.\n"
+#ENDIF
+;
 #IF (ESPENABLE)
 ORG_ESP		.EQU	$
   #INCLUDE "esp.asm"
@@ -7323,6 +7410,8 @@ PS_DDHDSK	.TEXT	"HDSK$"
 PS_DDPPA	.TEXT	"PPA$"
 PS_DDIMM	.TEXT	"IMM$"
 PS_DDSYQ	.TEXT	"SYQ$"
+PS_DDCHUSB	.TEXT	"CHUSB$"
+PS_DDCHSD	.TEXT	"CHSD$"
 ;
 ; DISK TYPE STRINGS
 ;
@@ -7369,6 +7458,8 @@ PS_SDDUART	.TEXT	"DUART$"
 PS_SDZ2U	.TEXT	"Z2U$"
 PS_SDLPT	.TEXT	"LPT$"
 PS_SDESPCON	.TEXT	"ESPCON$"
+PS_SDESPSER	.TEXT	"ESPSER$"
+PS_SDSCON	.TEXT	"SCON$"
 ;
 ; CHARACTER SUB TYPE STRINGS
 ;

Source/HBIOS/hbios.inc

@@ -152,6 +152,7 @@ PLT_RPH		.EQU	14		; RHYOPHYRE GRAPHICS COMPUTER
 PLT_Z80RETRO	.EQU	15		; Z80 RETRO COMPUTER
 PLT_S100	.EQU	16		; S100 COMPUTERS Z180 SYSTEM
 PLT_DUO		.EQU	17		; DUODYNE Z80 SYSTEM
+PLT_HEATH	.EQU	18		; HEATHKIT H8 Z80 SYSTEM
 ;
 ; HBIOS GLOBAL ERROR RETURN VALUES
 ;
@@ -314,6 +315,8 @@ CIODEV_DUART	.EQU	$90
 CIODEV_Z2U	.EQU	$A0
 CIODEV_LPT	.EQU	$B0
 CIODEV_ESPCON	.EQU	$C0
+CIODEV_ESPSER	.EQU	$D0
+CIODEV_SCON	.EQU	$E0
 ;
 ; SUB TYPES OF CHAR DEVICES
 ;
@@ -337,6 +340,8 @@ DIODEV_HDSK	.EQU	$90
 DIODEV_PPA	.EQU	$A0
 DIODEV_IMM	.EQU	$B0
 DIODEV_SYQ	.EQU	$C0
+DIODEV_CHUSB	.EQU	$D0
+DIODEV_CHSD	.EQU	$E0
 ;
 ; RTC DEVICE IDS
 ;
@@ -351,6 +356,7 @@ RTCDEV_RP5	.EQU	$50		; RP5C01
 ;
 DSKYDEV_ICM	.EQU	$00		; Intersil ICM7218
 DSKYDEV_PKD	.EQU	$10		; Intel P8279
+DSKYDEV_H8P	.EQU	$20		; Heath H8 Panel
 ;
 ; VIDEO DEVICE IDS
 ;

Source/HBIOS/pcf.asm

@@ -2,12 +2,11 @@
 ; PCF8584 I2C CLOCK DRIVER
 ;==================================================================================================
 ;
-PCF_BASE  	.EQU  0F0H
+PCF_BASE  	.EQU  PCFBASE
 PCF_ID   	.EQU  0AAH
-CPU_CLK	  	.EQU  12
-
+;
 PCF_RS0		.EQU  PCF_BASE
-PCF_RS1		.EQU  PCF_RS0+1
+PCF_RS1		.EQU  PCF_BASE+1
 PCF_OWN	 	.EQU  (PCF_ID >> 1)	 	; PCF'S ADDRESS IN SLAVE MODE
 ;
 ;T4LC512D	.EQU	10100000B		; DEVICE IDENTIFIER
@@ -37,10 +36,10 @@ PCF_STA  	.EQU  00000100B
 PCF_STO  	.EQU  00000010B
 PCF_ACK  	.EQU  00000001B
 ;
-PCF_START_		.EQU  (PCF_PIN | PCF_ES0 | PCF_STA | PCF_ACK)
-PCF_STOP_		.EQU  (PCF_PIN | PCF_ES0 | PCF_STO | PCF_ACK)
-PCF_REPSTART_ 	.EQU  (	   PCF_ES0 | PCF_STA | PCF_ACK)
-PCF_IDLE_		.EQU  (PCF_PIN | PCF_ES0		| PCF_ACK)
+PCF_START_	.EQU  (PCF_PIN | PCF_ES0 | PCF_STA | PCF_ACK)
+PCF_STOP_	.EQU  (PCF_PIN | PCF_ES0 | PCF_STO | PCF_ACK)
+PCF_REPSTART_ 	.EQU  (PCF_ES0 | PCF_STA | PCF_ACK)
+PCF_IDLE_	.EQU  (PCF_PIN | PCF_ES0 | PCF_ACK)
 ;
 ; STATUS REGISTER BITS
 ;
@@ -54,43 +53,6 @@ PCF_AAS   	.EQU  00000100B
 PCF_LAB   	.EQU  00000010B
 PCF_BB		.EQU  00000001B
 ;
-; CLOCK CHIP FREQUENCIES
-;
-PCF_CLK3   	.EQU	000H
-PCF_CLK443 	.EQU	010H
-PCF_CLK6   	.EQU	014H
-PCF_CLK8   	.EQU	018H
-PCF_CLK12  	.EQU	01cH
-;
-; TRANSMISSION FREQUENCIES
-;
-PCF_TRNS90 	.EQU	000H	;  90 kHz */
-PCF_TRNS45 	.EQU	001H	;  45 kHz */
-PCF_TRNS11 	.EQU	002H	;  11 kHz */
-PCF_TRNS15 	.EQU	003H	; 1.5 kHz */
-;
-; TIMEOUT AND DELAY VALUES (ARBITRARY)
-;
-PCF_PINTO	.EQU	65000
-PCF_ACKTO	.EQU	65000
-PCF_BBTO	.EQU	65000
-PCF_LABDLY	.EQU	65000
-;
-; DATA PORT REGISTERS
-;
-#IF (CPU_CLK = 443)
-PCF_CLK .EQU PCF_CLK4433
-#ELSE 
- #IF (CPU_CLK = 8)
-PCF_CLK .EQU PCF_CLK8
- #ELSE 
-  #IF (CPU_CLK = 12)
-PCF_CLK .EQU PCF_CLK12
-  #ELSE ***ERROR
-  #ENDIF
- #ENDIF	
-#ENDIF
-;
 ; THE PCF8584 TARGETS A TOP I2C CLOCK SPEED OF 90KHZ AND SUPPORTS DIVIDERS FOR 
 ; 3, 4.43, 6, 8 AND 12MHZ TO ACHEIVE THIS.
 ;
@@ -104,14 +66,44 @@ PCF_CLK .EQU PCF_CLK12
 ; |  12MHz  |       |        |       |         |        | 90Khz | 120Khz |   138Khz  |  150Khz |
 ; +----------------------------------------------------------------------------------+---------+
 ;
-PCF8584_INIT:
+; CLOCK CHIP FREQUENCIES
+;
+PCF_CLK3   	.EQU	000H
+PCF_CLK443 	.EQU	010H
+PCF_CLK6   	.EQU	014H
+PCF_CLK8   	.EQU	018H
+PCF_CLK12  	.EQU	01CH
+;
+; TRANSMISSION FREQUENCIES
+;
+PCF_TRNS90 	.EQU	000H	;  90 kHz */
+PCF_TRNS45 	.EQU	001H	;  45 kHz */
+PCF_TRNS11 	.EQU	002H	;  11 kHz */
+PCF_TRNS15 	.EQU	003H	; 1.5 kHz */
+;
+; BELOW VARIABLES CONTROL PCF CLOCK DIVISOR PROGRAMMING
+; HARD-CODED FOR NOW
+;
+PCF_CLK	  	.EQU	PCF_CLK12
+PCF_TRNS	.EQU	PCF_TRNS90
+;
+; TIMEOUT AND DELAY VALUES (ARBITRARY)
+;
+PCF_PINTO	.EQU	65000
+PCF_ACKTO	.EQU	65000
+PCF_BBTO	.EQU	65000
+PCF_LABDLY	.EQU	65000
+;
+; DATA PORT REGISTERS
+;
+PCF_INIT:
 	CALL	NEWLINE				; Formatting
-	PRTS("I2C: IO=0x$")
+	PRTS("PCF: IO=0x$")
 	LD	A, PCF_BASE
 	CALL	PRTHEXBYTE
 	CALL	PC_SPACE
-	CALL	PCF_INIT
-	CALL	NEWLINE
+	CALL	PCF_INITDEV
+	;CALL	NEWLINE
 	RET
 ;
 ; LINUX DRIVER BASED CODE
@@ -141,11 +133,13 @@ PCF_STOP:
 ;
 ;-----------------------------------------------------------------------------
 ;
-PCF_INIT:
+PCF_INITDEV:
 	LD	A,PCF_PIN   	; S1=80H: S0 SELECTED, SERIAL 
 	OUT	(PCF_RS1),A	; INTERFACE OFF
 	NOP
 	IN	A,(PCF_RS1)	; CHECK TO SEE S1 NOW USED AS R/W
+	;CALL	PC_SPACE
+	;CALL	PRTHEXBYTE
 	AND	07FH	  	; CTRL. PCF8584 DOES THAT WHEN ESO
 	JR	NZ,PCF_FAIL	; IS ZERO
 ;
@@ -153,6 +147,8 @@ PCF_INIT:
 	OUT	(PCF_RS0),A	; EFFECTIVE ADDRESS IS (OWN <<1)
 	NOP
 	IN	A,(PCF_RS0)	; CHECK IT IS REALLY WRITTEN
+	;CALL	PC_SPACE
+	;CALL	PRTHEXBYTE
 	CP	PCF_OWN
 	JP	NZ,PCF_SETERR
 ;
@@ -160,14 +156,18 @@ PCF_INIT:
 	OUT	(PCF_RS1),A		; NEXT BYTE IN S2
 	NOP
 	IN	A,(PCF_RS1)
+	;CALL	PC_SPACE
+	;CALL	PRTHEXBYTE
 	AND	07FH
 	CP	PCF_ES1
 	JP	NZ,PCF_REGERR
 ;
-	LD	A,PCF_CLK	; LOAD CLOCK REGISTER S2
+	LD	A,PCF_CLK | PCF_TRNS	; LOAD CLOCK REGISTER S2
 	OUT	(PCF_RS0),A
 	NOP
 	IN	A,(PCF_RS0)	; CHECK IT'S REALLY WRITTEN, ONLY
+	;CALL	PC_SPACE
+	;CALL	PRTHEXBYTE
 	AND	1FH	   	; THE LOWER 5 BITS MATTER
 	CP	PCF_CLK
 	JP	NZ,PCF_CLKERR
@@ -176,6 +176,8 @@ PCF_INIT:
 	OUT	(PCF_RS1),A  
 	NOP
 	IN	A,(PCF_RS1)  
+	;CALL	PC_SPACE
+	;CALL	PRTHEXBYTE
 	CP	+(PCF_PIN | PCF_BB)
 	JP	NZ,PCF_IDLERR
 ;
@@ -381,12 +383,12 @@ PCF_READI2C:
 ;
 ; POLL THE BUS BUSY BIT TO DETERMINE IF BUS IS FREE.
 ; RETURN WITH A=00H/Z STATUS IF BUS IS FREE
-; RETURN WITH A=FFH/NZ STATUS IF BUS
+; RETURN WITH A=FFH/NZ STATUS IF BUS IS BUSY
 ;
 ; AFTER RESET THE BUS BUSY BIT WILL BE SET TO 1 I.E. NOT BUSY
 ;
 PCF_WAIT_FOR_BB:
-	 LD	HL,PCF_BBTO
+	LD	HL,PCF_BBTO
 PCF_WFBB0:
 	IN	A,(PCF_RS1)
 	AND	PCF_BB

Source/HBIOS/pkd.asm

@@ -371,7 +371,6 @@ PKD_KEYMAP:
 	; POS	$18  $19  $1A  $1B
 	; KEY   [F4] [F3] [F2] [F1]
 	.DB	$23, $22, $21, $20
-
 ;
 ;==================================================================================================
 ; PKD OUTPUT ROUTINES

Source/HBIOS/romldr.asm

@@ -1343,6 +1343,36 @@ diskread:
 ;
 #endif
 ;
+; Built-in mini-loader for S100 Monitor.  The S100 platform build
+; imbeds the S100 Monitor in the ROM at the start of bank 3 (BID_IMG2).
+; This bit of code just launches the monitor directly from that bank.
+;
+#if (BIOS == BIOS_WBW)
+  #if (PLATFORM == PLT_S100)
+;
+s100mon:
+	; Warn user that console is being directed to the S100 bus
+	; if the IOBYTE bit 0 is 0 (%xxxxxxx0).
+	in	a,($75)			; get IO byte
+	and	%00000001		; isolate console bit
+	jr	nz,s100mon1		; if 0, bypass msg
+	ld	hl,str_s100con		; console msg string
+	call	pstr			; display it
+;
+s100mon1:
+	; Launch S100 Monitor from ROM Bank 3
+	call	ldelay			; wait for UART buf to empty
+	di				; suspend interrupts
+	ld	a,BID_IMG2		; S100 monitor bank
+	ld	ix,0			; execution resumes here
+	jp	HB_BNKCALL		; do it
+;
+str_smon	.db	"S100 Z180 Monitor",0
+str_s100con	.db	"\r\n\r\nConsole on S100 Bus",0
+;
+  #endif
+#endif
+;
 ;=======================================================================
 ; Utility functions
 ;=======================================================================
@@ -2313,7 +2343,7 @@ ra_ent(str_mon,	  'M',	   KY_CL, BID_IMG0, MON_IMGLOC,  MON_LOC, MON_SIZ, MON_SE
 ra_entsiz	.equ	$ - ra_tbl
 #if (BIOS == BIOS_WBW)
   #if (PLATFORM == PLT_S100)
-ra_ent(str_smon,  'S',	   $FF,	  BID_IMG2, $0000,       $0000,   $2100,   $0000)
+ra_ent(str_smon,  'S',	   $FF,	  bid_cur , $8000,       $8000,   $0001,   s100mon)
   #endif
 #endif
 ra_ent(str_zsys,  'Z',	   KY_FW, BID_IMG0, ZSYS_IMGLOC, CPM_LOC, CPM_SIZ, CPM_ENT)
@@ -2338,7 +2368,7 @@ ra_tbl_app:
 ;      Name	  Key	   Dsky	  Bank	    Src	         Dest	    Size     Entry
 ;      ---------  -------  -----  --------  -----       -------  -------  ----------
 ra_ent(str_mon,	  'M',	   KY_CL, bid_cur,  MON_IMGLOC,  MON_LOC, MON_SIZ, MON_SERIAL)
-ra_ent(str_zsys,  'Z',	   KY_FW, bid_cur,  ZSYS_IMGLOC,  CPM_LOC, CPM_SIZ, CPM_ENT)
+ra_ent(str_zsys,  'Z',	   KY_FW, bid_cur,  ZSYS_IMGLOC, CPM_LOC, CPM_SIZ, CPM_ENT)
 #if (DSKYENABLE)
 ra_ent(str_dsky,  'Y'+$80, KY_GO, bid_cur,  MON_IMGLOC,  MON_LOC, MON_SIZ, MON_DSKY)
 #endif
@@ -2354,7 +2384,6 @@ str_tbas	.db	"Tasty BASIC",0
 str_play	.db	"Play a Game",0
 str_upd		.db	"XModem Flash Updater",0
 str_user	.db	"User App",0
-str_smon	.db	"S100 Z180 Monitor",0
 str_egg		.db	"",0
 str_net		.db	"Network Boot",0
 str_switches	.db	"FP Switches = 0x",0

Source/HBIOS/scon.asm

@@ -0,0 +1,126 @@
+;
+;==================================================================================================
+; S100 PROPELLER CONSOLE DRIVER
+;==================================================================================================
+;
+; TODO:
+;
+SCON_IOBASE	.EQU	$00
+;
+SCON_STATUS	.EQU	SCON_IOBASE
+SCON_DATA	.EQU	SCON_IOBASE + 1
+;
+SCON_KBDRDY	.EQU	%00000010
+SCON_DSPRDY	.EQU	%00000100
+;
+SCON_COLS	.EQU	80
+SCON_ROWS	.EQU	40
+;
+;
+;
+SCON_PREINIT:
+	XOR	A
+	RET
+;
+;
+;
+SCON_INIT:
+	CALL	NEWLINE
+	PRTS("SCON:$")
+;
+	; DISPLAY CONSOLE DIMENSIONS
+	CALL	PC_SPACE
+	LD	A,SCON_COLS
+	CALL	PRTDECB
+	LD	A,'X'
+	CALL	COUT
+	LD	A,SCON_ROWS
+	CALL	PRTDECB
+	CALL	PRTSTRD
+	.TEXT	" TEXT (ANSI)$"
+;
+; ADD OURSELVES TO CIO DISPATCH TABLE
+;
+	LD	D,0			; PHYSICAL UNIT IS ZERO
+	LD	E,CIODEV_SCON		; DEVICE TYPE
+	LD	BC,SCON_FNTBL		; BC := FUNCTION TABLE ADDRESS
+	CALL	CIO_ADDENT		; ADD ENTRY, A := UNIT ASSIGNED
+	LD	(HCB + HCB_CRTDEV),A	; SET OURSELVES AS THE CRT DEVICE
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; DRIVER FUNCTION TABLE
+;
+SCON_FNTBL:
+	.DW	SCON_IN
+	.DW	SCON_OUT
+	.DW	SCON_IST
+	.DW	SCON_OST
+	.DW	SCON_INITDEV
+	.DW	SCON_QUERY
+	.DW	SCON_DEVICE
+#IF (($ - SCON_FNTBL) != (CIO_FNCNT * 2))
+	.ECHO	"*** INVALID SCON FUNCTION TABLE ***\n"
+#ENDIF
+;
+;
+;
+SCON_IN:
+	CALL	SCON_IST		; CHECK FOR CHAR PENDING
+	JR	Z,SCON_IN		; WAIT FOR IT IF NECESSARY
+	IN0	A,(SCON_DATA)		; READ THE CHAR FROM PROPIO
+	LD	E,A
+	RET
+;
+;
+;
+SCON_IST:
+	IN0	A,(SCON_STATUS)		; READ LINE STATUS REGISTER
+	AND	SCON_KBDRDY		; ISOLATE KBDRDY
+	JP	Z,CIO_IDLE		; RETURN VIA IDLE PROCESSING
+	OR	$FF			; SET A=$FF TO SIGNAL READY
+	RET				; RETURN
+;
+;
+;
+SCON_OUT:
+	CALL	SCON_OST		; CHECK FOR OUTPUT READY
+	JR	Z,SCON_OUT		; WAIT IF NECESSARY
+	LD	A,E			; RECOVER THE CHAR TO WRITE
+	OUT0	(SCON_DATA),A		; WRITE THE CHAR TO PROPIO
+	RET
+;
+;
+;
+SCON_OST:
+	IN0	A,(SCON_STATUS)		; READ LINE STATUS REGISTER
+	AND	SCON_DSPRDY 		; ISOLATE DSPRDY
+	JP	Z,CIO_IDLE		; RETURN VIA IDLE PROCESSING
+	OR	$FF			; SET A=$FF TO SIGNAL READY
+	RET				; RETURN
+;
+;
+;
+SCON_INITDEV:
+	SYSCHKERR(ERR_NOTIMPL)
+	RET
+;
+;
+;
+SCON_QUERY:
+	LD	DE,0
+	LD	HL,0
+	XOR	A
+	RET
+;
+;
+;
+SCON_DEVICE:
+	LD	D,CIODEV_SCON		; D := DEVICE TYPE
+	LD	E,0			; E := DEVICE NUM, ALWAYS 0
+	LD	C,$BF			; C := DEVICE TYPE, 0xBF IS PROP TERM
+	LD	H,0			; H := 0, DRIVER HAS NO MODES
+	LD	L,SCON_IOBASE		; L := BASE I/O ADDRESS
+	XOR	A			; SIGNAL SUCCESS
+	RET

Source/HBIOS/std.asm

@@ -282,6 +282,8 @@ DMAMODE_Z180	.EQU	2		; Z180 INTEGRATED DMA
 DMAMODE_Z280	.EQU	3		; Z280 INTEGRATED DMA
 DMAMODE_RC	.EQU	4		; RCBUS Z80 DMA
 DMAMODE_MBC	.EQU	5		; MBC
+DMAMODE_DUO	.EQU	6		; DUO
+DMAMODE_VDG	.EQU	7		; VELESOFT DATAGEAR
 ;
 ; KEYBOARD MODE SELECTIONS
 ;
@@ -756,15 +758,30 @@ INT_SIO1	.EQU	14	; ZILOG SIO 1, CHANNEL A & B
 #ENDIF
 
 #IF ((CPUFAM == CPU_Z80) & (INTMODE == 2))
-  #IF (PLATFORM == PLT_MBC)
 
-; MBC Z80
+  #IF (PLATFORM == PLT_MBC)
+;
+; MBC IM2 PINHEADER INTERRUPTS
+;
+;INT_IM2PH0	.EQU	0	
+;INT_IM2PH1	.EQU	1
+;INT_IM2PH2	.EQU	2
+;INT_IM2PH3	.EQU	3
+;INT_IM2PH4	.EQU	4
+;INT_IM2PH5	.EQU	5
+;INT_IM2PH6	.EQU	6
+;INT_IM2PH7	.EQU	7
+;
+; MBC Z80 INTERRUPTS
+;
 ;INT_CTC0A	.EQU	0	; ZILOG CTC 0, CHANNEL A
 ;INT_CTC0B	.EQU	1	; ZILOG CTC 0, CHANNEL B
 ;INT_CTC0C	.EQU	2	; ZILOG CTC 0, CHANNEL C
 ;INT_CTC0D	.EQU	3	; ZILOG CTC 0, CHANNEL D
 INT_UART0	.EQU	4	; UART 0
 INT_UART1	.EQU	5	; UART 1
+INT_INT6	.EQU	6	;
+INT_INT7	.EQU	7	;
 INT_SIO0	.EQU	8	; ZILOG SIO 0, CHANNEL A & B
 INT_SIO1	.EQU	9	; ZILOG SIO 1, CHANNEL A & B
 INT_CTC0A	.EQU	12	; ZILOG CTC 0, CHANNEL A
@@ -776,9 +793,42 @@ INT_CTC0D	.EQU	15	; ZILOG CTC 0, CHANNEL D
 ;INT_PIO1A	.EQU	11	; ZILOG PIO 1, CHANNEL A
 ;INT_PIO1B	.EQU	12	; ZILOG PIO 1, CHANNEL B
 
-  #ELSE
+  #ENDIF
+
+  #IF (PLATFORM == PLT_DUO)
+
+; DUO IM2 PINHEADER INTERRUPTS
+
+;INT_IM2PH0	.EQU	0
+;INT_IM2PH1	.EQU	1
+;INT_IM2PH2	.EQU	2
+;INT_IM2PH3	.EQU	3
+;INT_IM2PH4	.EQU	4
+;INT_IM2PH5	.EQU	5
+;INT_IM2PH6	.EQU	6
+;INT_IM2PH7	.EQU	7
+;
+; DUO Z80 IM2 INTERRUPTS
+; 
+INT_UART0	.EQU	7	; UART 0
+INT_UART1	.EQU	6	; UART 1 ?????
+INT_CTC0A	.EQU	0	; ZILOG CTC 0, CHANNEL A
+INT_CTC0B	.EQU	1	; ZILOG CTC 0, CHANNEL B
+INT_CTC0C	.EQU	2	; ZILOG CTC 0, CHANNEL C
+INT_CTC0D	.EQU	3	; ZILOG CTC 0, CHANNEL D
+;INT_SIO0	.EQU	7	; ZILOG SIO 0, CHANNEL A & B
+INT_SIO1	.EQU	8	; ZILOG SIO 1, CHANNEL A & B
+INT_PIO0A	.EQU	9	; ZILOG PIO 0, CHANNEL A
+INT_PIO0B	.EQU	10	; ZILOG PIO 0, CHANNEL B
+INT_PIO1A	.EQU	11	; ZILOG PIO 1, CHANNEL A
+INT_PIO1B	.EQU	12	; ZILOG PIO 1, CHANNEL B
+
+  #ENDIF
+
+  #IF ((PLATFORM != PLT_MBC) & (PLATFORM != PLT_DUO))
+
+; GENERIC Z80 M2 INTERRUPTS
 
-; GENERIC Z80
 INT_CTC0A	.EQU	0	; ZILOG CTC 0, CHANNEL A
 INT_CTC0B	.EQU	1	; ZILOG CTC 0, CHANNEL B
 INT_CTC0C	.EQU	2	; ZILOG CTC 0, CHANNEL C
@@ -792,7 +842,8 @@ INT_PIO0B	.EQU	10	; ZILOG PIO 0, CHANNEL B
 INT_PIO1A	.EQU	11	; ZILOG PIO 1, CHANNEL A
 INT_PIO1B	.EQU	12	; ZILOG PIO 1, CHANNEL B
 
-    #ENDIF
+  #ENDIF
+
 #ENDIF
 
 #DEFINE IVT(INTX) HB_IVT+(INTX * 4)+1

Source/HBIOS/uart.asm

@@ -53,13 +53,16 @@ UART_INTACT		.EQU	7	; INT RCV ACTIVE BIT
 UART_FIFOACT		.EQU	6	; FIFO ACTIVE BIT
 UART_AFCACT		.EQU	5	; AUTO FLOW CONTROL ACTIVE BIT
 ;
+#IF (PLATFORM == PLT_DUO)
+UARTSBASE		.EQU	$58
+#ELSE
 UARTSBASE		.EQU	$68
+#ENDIF
 UARTCBASE		.EQU	$80
 UARTMBASE		.EQU	$18
 UART4BASE		.EQU	$C0
 UARTRBASE		.EQU	$A0
 UARTDBASE		.EQU	$80
-UARTYBASE		.EQU	$58
 ;
 #IF (UARTINTS)
 ;
@@ -1088,16 +1091,6 @@ UART_CFG_MFP:
 	.DW	UARTCFG				; LINE CONFIGURATION
 	.DW	0				; SHOULD NEVER NEED INT HANDLER
 #ENDIF
-#IF (UARTDUO)
-UART_CFG_DUO:
-	; DUODYNE ONBOARD SERIAL PORT
-	.DB	0				; DEVICE NUMBER (UPDATED DURING INIT)
-	.DB	0				; UART TYPE
-	.DB	UARTYBASE			; IO PORT BASE (RBR, THR)
-	.DB	UARTYBASE + UART_LSR		; LINE STATUS PORT (LSR)
-	.DW	UARTCFG				; LINE CONFIGURATION
-	.DW	0				; POINTER TO RCV BUFFER STRUCT
-#ENDIF
 ;
 UART_CNT	.EQU	($ - UART_CFG) / 8
 ;

Source/Images/Build.cmd

@@ -13,7 +13,7 @@ call BuildDisk.cmd nzcom fd wbw_fd144 ..\zsdos\zsys_wbw.sys || exit /b
 call BuildDisk.cmd cpm3 fd wbw_fd144 ..\cpm3\cpmldr.sys || exit /b
 call BuildDisk.cmd zpm3 fd wbw_fd144 ..\zpm3\zpmldr.sys || exit /b
 call BuildDisk.cmd ws4 fd wbw_fd144 || exit /b
-call BuildDisk.cmd qpm fd wbw_fd144 d_qpm\u0\qpm.sys || exit /b
+call BuildDisk.cmd qpm fd wbw_fd144 ..\qpm\qpm_wbw.sys || exit /b
 call BuildDisk.cmd z80asm hd wbw_fd144 || exit /b
 call BuildDisk.cmd aztecc hd wbw_fd144 || exit /b
 call BuildDisk.cmd hitechc hd wbw_fd144 || exit /b
@@ -32,7 +32,7 @@ call BuildDisk.cmd cpm3 hd wbw_hd512 ..\cpm3\cpmldr.sys || exit /b
 call BuildDisk.cmd zpm3 hd wbw_hd512 ..\zpm3\zpmldr.sys || exit /b
 call BuildDisk.cmd ws4 hd wbw_hd512 || exit /b
 call BuildDisk.cmd dos65 hd wbw_hd512 ..\zsdos\zsys_wbw.sys || exit /b
-call BuildDisk.cmd qpm hd wbw_hd512 d_qpm\u0\qpm.sys || exit /b
+call BuildDisk.cmd qpm hd wbw_hd512 ..\qpm\qpm_wbw.sys || exit /b
 call BuildDisk.cmd z80asm hd wbw_hd512 || exit /b
 call BuildDisk.cmd aztecc hd wbw_hd512 || exit /b
 call BuildDisk.cmd hitechc hd wbw_hd512 || exit /b
@@ -56,7 +56,7 @@ call BuildDisk.cmd nzcom hd wbw_hd1k ..\zsdos\zsys_wbw.sys || exit /b
 call BuildDisk.cmd cpm3 hd wbw_hd1k ..\cpm3\cpmldr.sys || exit /b
 call BuildDisk.cmd zpm3 hd wbw_hd1k ..\zpm3\zpmldr.sys || exit /b
 call BuildDisk.cmd ws4 hd wbw_hd1k || exit /b
-call BuildDisk.cmd qpm hd wbw_hd1k d_qpm\u0\qpm.sys || exit /b
+call BuildDisk.cmd qpm hd wbw_hd1k ..\qpm\qpm_wbw.sys || exit /b
 call BuildDisk.cmd z80asm hd wbw_hd1k || exit /b
 call BuildDisk.cmd aztecc hd wbw_hd1k || exit /b
 call BuildDisk.cmd hitechc hd wbw_hd1k || exit /b

Source/Images/Makefile

@@ -1,7 +1,7 @@
 #
 # this makefile subsumes all the work done in Build.cmd, BuildDisk.cmd, BuildDisk.ps1
 #
-SYSTEMS = ../CPM22/cpm_wbw.sys ../ZSDOS/zsys_wbw.sys ../CPM3/cpmldr.sys ../ZPM3/zpmldr.sys
+SYSTEMS = ../CPM22/cpm_wbw.sys ../ZSDOS/zsys_wbw.sys ../QPM/qpm_wbw.sys ../CPM3/cpmldr.sys ../ZPM3/zpmldr.sys
 
 FDIMGS = fd144_cpm22.img fd144_zsdos.img fd144_nzcom.img \
 	fd144_cpm3.img fd144_zpm3.img fd144_ws4.img fd144_qpm.img \
@@ -80,7 +80,7 @@ blankhd1k:
 	@sys= ; \
 	case $@ in \
 		(*cpm22*) sys=../CPM22/cpm_wbw.sys;; \
-		(*qpm*) sys=d_qpm/u0/qpm.sys;; \
+		(*qpm*) sys=../QPM/qpm_wbw.sys;; \
 		(*zsdos* | *nzcom* | *dos65*) sys=../ZSDOS/zsys_wbw.sys;; \
 		(*cpm3*) sys=../CPM3/cpmldr.sys;; \
 		(*zpm3*) sys=../ZPM3/zpmldr.sys;; \

Source/Images/d_qpm/ReadMe.txt

@@ -36,11 +36,19 @@ code brakpoints.  This conflicts the use of that vector for any
 system that is using interrupt mode 1.  DEBUGZ can be configured
 (using DBGINST) to use a different vector.
 
-The QSTAMP program, which is used to initialize a disk for date/time
-stamping, misbehavews when run on the (new) RomWBW 1024 directory
-format disks.  It creates an invalid directory entry for the
-date/time stamp data file.  This is definitely a QP/M issue.  The
-directory entry can be manually corrected.
+The QSTAMP program, which is used to initialize a disk for date/time 
+stamping, misbehavews when run on the (new) RomWBW 1024 directory 
+format disks.  It creates an invalid directory entry for the date/time 
+stamp data file.  This is definitely a QP/M issue.  The directory entry 
+can be manually corrected.  Specifically the byte offset 15 should 
+contain the number of 128-byte records in the file.  Instead, it is set 
+to 0x01.  You can edit the entry, change it to 0x80 and everything
+starts working.
+
+There are two text files (QPMCMDS.TXT and QPMUTILS.TXT) included.  They
+came from the original QP/M 2.7 distribution.  These files have
+escape sequences imbedded in them which makes them look a little
+strange depending on the terminal emulation you are using.
 
 == QPM 2.7 Files ==
 
@@ -48,10 +56,9 @@ The following files came from the official QP/M distribution.  Actually,
 they came from 3 Microcode Consulting files (qpm27.zip, debugz.zip,
 and linkz.zip).  The original distribution files can be found on the
 Microcode Consulting website at https://www.microcodeconsulting.com/.
-Documentation (pdf) files are incuded in these original distribution
-.zip files.  These documentation files have not been included in the
-RomWBW distribution.  Please retrieve them yourself from the website
-if desired.
+Documentation (pdf) files are included in these original distribution
+.zip files.  These documentation files have been included in the
+RomWBW distribution in the Doc folder.
 
 D.COM - Directory lister
 DBGINST.COM - Configures DEBUGZ debugger

Source/Images/fd_qpm.txt

@@ -44,7 +44,7 @@ d_cpm22/u0/*.* 0:
 #
 # Add OS image
 #
-../CPM22/cpm_wbw.sys 0:cpm.sys
+../QPM/qpm_wbw.sys 0:qpm.sys
 #
 # Add Common Applications
 #

Source/Images/hd_qpm.txt

@@ -51,7 +51,7 @@ cpnet12/*.* 4:
 #
 # Add OS image
 #
-../CPM22/cpm_wbw.sys 0:cpm.sys
+../QPM/qpm_wbw.sys 0:qpm.sys
 #
 # Add Common Applications
 #

Source/Makefile

@@ -1,14 +1,43 @@
 #
 # order is actually important, because of build dependencies
 #
+BUILDPROP := 1
+UNAME := $(shell uname)
+ifeq ($(UNAME), Linux)
+# Inhibit building Propeller on unsupported
+# Linux host architectures such as ARM eg. Raspberry Pi
+	BUILDPROP := 0
+	ARCH := $(shell uname -m)
+	ifeq ($(ARCH), x86_64)
+		BUILDPROP := 1
+	endif
+	ifeq ($(ARCH), i686)
+		BUILDPROP := 1
+	endif
+	ifeq ($(ARCH), i386)
+		BUILDPROP := 1
+	endif
+	ifeq ($(ARCH), x86)
+		BUILDPROP := 1
+	endif
+# Add here any more supported x86 based
+# uname machine strings for building Propeller
+endif
+
 SUBDIRS = HDIAG
+
+ifeq ($(BUILDPROP), 1)
 SUBDIRS += Prop
+else
+$(info "Builing Propeller is not supported on this $(ARCH) host Linux OS")
+endif
+
 SUBDIRS += Apps
 SUBDIRS += CBIOS
 SUBDIRS += Forth
 SUBDIRS += TastyBasic
 SUBDIRS += Fonts
-SUBDIRS += CPM22 ZCPR ZCPR-DJ ZSDOS CPM3 ZPM3
+SUBDIRS += CPM22 ZCPR ZCPR-DJ ZSDOS CPM3 ZPM3 QPM
 #SUBDIRS += BPBIOS
 SUBDIRS += pSys
 SUBDIRS += RomDsk

Source/QPM/Build.cmd

@@ -0,0 +1,20 @@
+@echo off
+setlocal
+
+set TOOLS=../../Tools
+
+set PATH=%TOOLS%\tasm32;%TOOLS%\zxcc;%PATH%
+
+set TASMTABS=%TOOLS%\tasm32
+
+set CPMDIR80=%TOOLS%/cpm/
+
+tasm -t80 -g3 -fFF loader.asm loader.bin loader.lst || exit /b
+
+copy /b qcp27.dat + qdos27.dat + ..\cbios\cbios_wbw.bin qpm_wbw.bin || exit /b
+copy /b qcp27.dat + qdos27.dat + ..\cbios\cbios_una.bin qpm_una.bin || exit /b
+
+copy /b loader.bin + qpm_wbw.bin qpm_wbw.sys || exit /b
+copy /b loader.bin + qpm_una.bin qpm_una.sys || exit /b
+
+goto :eof

Source/QPM/Clean.cmd

@@ -0,0 +1,8 @@
+@echo off
+setlocal
+
+if exist *.bin del *.bin
+if exist *.lst del *.lst
+if exist *.prn del *.prn
+if exist *.hex del *.hex
+if exist *.sys del *.sys

Source/QPM/Makefile

@@ -0,0 +1,15 @@
+SYSFILES = qpm_wbw.sys qpm_una.sys
+BINFILES = qpm_wbw.bin qpm_una.bin
+OBJECTS = loader.bin $(SYSFILES) $(BINFILES)
+OTHERS = *.hex
+TOOLS = ../../Tools
+include $(TOOLS)/Makefile.inc
+
+%.sys: %.bin loader.bin
+	cat loader.bin $*.bin > $@
+
+qpm_una.bin: qcp27.dat qdos27.dat ../CBIOS/cbios_una.bin
+	cat qcp27.dat qdos27.dat ../CBIOS/cbios_una.bin > $@
+
+qpm_wbw.bin: qcp27.dat qdos27.dat ../CBIOS/cbios_wbw.bin
+	cat qcp27.dat qdos27.dat ../CBIOS/cbios_wbw.bin > $@

Source/QPM/ReadMe.txt

@@ -0,0 +1,15 @@
+QPM27
+-----
+
+QPM is not available in source form.  In this folder, you will find
+qcp27.dat and qdos27.dat.  These are the CCP and BDOS components for
+QPM.  They were created by running QINSTALL on a normal RomWBW
+CP/M 2.2 system, then extracting the resultant CCP and BDOS binaries.
+
+When this folder goes through the build process, it just combines the
+QPM CCP and BDOS binaries with the RomWBW CBIOS to create an up-to-date
+QPM system image.
+
+QPM 2.7 is distributed at https://www.microcodeconsulting.com/.
+
+-- WBW 3:13 PM 9/9/2023

Source/QPM/loader.asm

@@ -0,0 +1,271 @@
+;===============================================================================
+; LOADER.ASM
+;
+; BOOTLOADER FOR ROMWBW DISK OPERATING SYSTEMS.
+;
+; CP/M DISK FORMATS ALLOW FOR RESERVED TRACKS THAT CONTAIN AN IMAGE OF THE
+; OPERATING SYSTEM TO BE LOADED WHEN THE DISK IS BOOTED.  THE OPERATING SYSTEM
+; IMAGE ITSELF IS NORMALLY PREFIXED BY A 1-N SECTORS CONTAINING OS BOOTSTRAP
+; CODE AND DISK METADATA.
+;
+; THE RETROBREW COMPUTING GROUP HAS BEEN USING A CONVENTION OF PREFIXING THE
+; OS IMAGE WITH 3 SECTORS (512 BYTES X 3 FOR A TOTAL OF 1536 BYTES):
+;
+;   SECTOR 1: IBM-PC STYLE BOOT BLOCK CONTAINING BOOTSTRAP, 
+;             PARTITION TABLE, AND BOOT SIGNATURE
+;   SECTOR 2: RESERVED
+;   SECTOR 3: METADATA
+;
+; THE HARDWARE BIOS IS EXPECTED TO READ AND LOAD THE FIRST TWO SECTORS FROM THE
+; DISK TO MEMORY ADDRESS $8000 AND JUMP TO THAT LOCATION TO BEGIN THE BOOT
+; PROCESS.  THE BIOS IS EXPECTED TO VERIFY THAT A STANDARD BOOT SIGNATURE
+; OF $55, $AA IS PRESENT AT OFFSET $1FE-$1FF.  IF THE SIGNATURE IS NOT FOUND,
+; THE BIOS SHOULD ASSUME THE DISK HAS NOT BEEN PROPERLY INITIALIZED AND SHOULD
+; NOT JUMP TO THE LOAD ADDRESS.
+;
+;===============================================================================
+;
+#INCLUDE "../ver.inc"
+;
+SYS_ENT		.EQU	$E600		; SYSTEM (OS) ENTRY POINT ADDRESS
+SYS_LOC		.EQU	$D000		; STARTING ADDRESS TO LOAD SYSTEM IMAGE
+SYS_END		.EQU	$FE00		; ENDING ADDRESS OF SYSTEM IMAGE
+;
+SEC_SIZE	.EQU	512		; DISK SECTOR SIZE
+BLK_SIZE	.EQU	128		; OS BLOCK/RECORD SIZE
+;
+PREFIX_SIZE	.EQU	(SEC_SIZE * 3)	; 3 SECTORS
+;
+META_SIZE	.EQU	32		; SEE BELOW
+META_LOC	.EQU	(PREFIX_SIZE - META_SIZE)
+;
+PT_LOC		.EQU	$1BE
+PT_SIZ		.EQU	$40
+;
+;-------------------------------------------------------------------------------
+; SECTOR 1
+;
+;   THIS SECTOR FOLLOWS THE CONVENTIONS OF AN IBM-PC MBR CONTAINING THE OS
+;   BOOTSTRAP CODE, PARTITION TABLE, AND BOOT SIGNATURE
+;
+;----------------------------------------------------------------------------
+;
+; THE FOLLOWING BOOTSTRAP CODE IS BUILT TO ASSUME IT WILL BE EXECUTED AT A STARTING
+; ADDRESS OF $8000.  THIS CODE IS *ONLY* FOR UNA.  THE ROMWBW ROM BOOTLOADER
+; USES THE METADATA TO LOAD THE OS DIRECTLY.
+;
+	.ORG	$8000
+	JR	BOOT
+;
+BOOT:
+	LD	DE,STR_LOAD	; LOADING STRING
+	CALL	PRTSTR		; PRINT
+	CALL	PRTDOT		; PROGRESS
+;
+	LD	BC,$00FC	; UNA FUNC: GET BOOTSTRAP HISTORY
+	CALL	$FFFD		; CALL UNA
+	JR	NZ,ERROR	; HANDLE ERROR
+	CALL	PRTDOT		; PROGRESS
+	LD	B,L		; MOVE BOOT UNIT ID TO B
+;
+	LD	C,$41		; UNA FUNC: SET LBA
+	LD	DE,0		; HI WORD ALWAYS ZERO
+	LD	HL,3		; IMAGE STARTS AT FOURTH SECTOR
+	CALL	$FFFD		; SET LBA
+	JR	NZ,ERROR	; HANDLE ERROR
+	CALL	PRTDOT		; PROGRESS
+;
+	LD	C,$42		; UNA FUNC: READ SECTORS
+	LD	DE,$D000	; STARTING ADDRESS FOR IMAGE
+	LD	L,22		; READ 22 SECTORS
+	CALL	$FFFD		; DO READ
+	JR	NZ,ERROR	; HANDLE ERROR
+	CALL	PRTDOT		; PROGRESS
+;
+	LD	DE,STR_DONE	; DONE MESSAGE
+	CALL	PRTSTR		; PRINT IT
+;
+	LD	D,B		; PASS BOOT UNIT TO OS
+	LD	E,0		; ASSUME LU IS ZERO
+	JP	SYS_ENT		; GO TO SYSTEM
+;
+PRTCHR:
+	PUSH	BC
+	PUSH	DE
+	LD	BC,$0012	; UNIT 0, WRITE CHAR
+	LD	E,A		; CHAR TO PRINT
+	CALL	$FFFD		; PRINT
+	POP	DE
+	POP	BC
+	RET
+;
+PRTSTR:
+	PUSH	BC
+	PUSH	HL
+	LD	BC,$0015	; UNIT 0, WRITE CHARS UNTIL TERMINATOR
+	LD	L,0		; TERMINATOR IS NULL
+	CALL	$FFFD		; PRINT
+	POP	HL
+	POP	BC
+	RET
+;
+PRTDOT:
+	LD	A,'.'		; DOT CHARACTER
+	JR	PRTCHR		; PRINT AND RETURN
+;
+; PRINT THE HEX BYTE VALUE IN A
+;
+PRTHEXBYTE:
+	PUSH	AF
+	PUSH	DE
+	CALL	HEXASCII
+	LD	A,D
+	CALL	PRTCHR
+	LD	A,E
+	CALL	PRTCHR
+	POP	DE
+	POP	AF
+	RET
+;
+; CONVERT BINARY VALUE IN A TO ASCII HEX CHARACTERS IN DE
+;
+HEXASCII:
+	LD	D,A
+	CALL	HEXCONV
+	LD	E,A
+	LD	A,D
+	RLCA
+	RLCA
+	RLCA
+	RLCA
+	CALL	HEXCONV
+	LD	D,A
+	RET
+;
+; CONVERT LOW NIBBLE OF A TO ASCII HEX
+;
+HEXCONV:
+	AND	$0F	     ;LOW NIBBLE ONLY
+	ADD	A,$90
+	DAA	
+	ADC	A,$40
+	DAA	
+	RET	
+;
+ERROR:
+	LD	DE,STR_ERR		; POINT TO ERROR STRING
+	CALL	PRTSTR			; PRINT IT
+	HALT				; HALT
+;
+; DATA
+;
+STR_LOAD	.DB	"\r\nLoading",0
+STR_DONE	.DB	"\r\n",0
+STR_ERR		.DB	" Read Error!",0
+;
+	.ORG	$ - $8000		; BACK TO ABSOLUTE ADDRESS
+;
+	.FILL	PT_LOC - $,0		; FILL TO START OF PARTITION TABLE
+;
+; STANDARD IBM-PC PARTITION TABLE.  ALTHOUGH A
+; PARTITION TABLE IS NOT RELEVANT FOR A FLOPPY DISK, IT DOES NO HARM.
+; THE CONTENTS OF THE PARTITION TABLE CAN BE MANAGED BY FDISK80.
+;
+; BELOW WE ALLOW FOR 32 SLICES OF ROMWBW CP/M FILESYSTEMS
+; FOLLOWED BY A FAT16 PARTITION.  THE SLICES FOLLOW THE ORIGINAL
+; HD512 ROMWBW FORMAT.  IF THE DISK IS USING HD1K, A SEPARATE
+; PARTITION TABLE WILL BE IN PLACE AND RENDER THIS PARTITION TABLE
+; IRRELEVANT.
+;
+; THE CYL/SEC FIELDS ENCODE CYLINDER AND SECTOR AS:
+;	CCCCCCCC:CCSSSSSS
+;	76543210:98543210
+;
+PART0:
+	.DB	0			; ACTIVE IF $80
+	.DB	0			; CHS START ADDRESS (HEAD)
+	.DW	0			; CHS START ADDRESS (CYL/SEC)
+	.DB	0			; PART TYPE ID
+	.DB	0			; CHS LAST ADDRESS (HEAD)
+	.DW	0			; CHS LAST ADDRESS (CYL/SEC)
+	.DW	0,0			; LBA FIRST (DWORD)
+	.DW	0,0			; LBA COUNT (DWORD)
+PART1:
+	.DB	0			; ACTIVE IF $80
+	.DB	0			; CHS START ADDRESS (HEAD)
+	.DW	%1111111111000001	; CHS START ADDRESS (CYL/SEC)
+	.DB	6			; PART TYPE ID
+	.DB	15			; CHS LAST ADDRESS (HEAD)
+	.DW	%1111111111010000	; CHS LAST ADDRESS (CYL/SEC)
+	.DW	$4000,$0010		; LBA FIRST (DWORD)
+	.DW	$0000,$000C		; LBA COUNT (DWORD)
+PART2:
+	.DB	0			; ACTIVE IF $80
+	.DB	0			; CHS START ADDRESS (HEAD)
+	.DW	0			; CHS START ADDRESS (CYL/SEC)
+	.DB	0			; PART TYPE ID
+	.DB	0			; CHS LAST ADDRESS (HEAD)
+	.DW	0			; CHS LAST ADDRESS (CYL/SEC)
+	.DW	0,0			; LBA FIRST (DWORD)
+	.DW	0,0			; LBA COUNT (DWORD)
+PART3:
+	.DB	0			; ACTIVE IF $80
+	.DB	0			; CHS START ADDRESS (HEAD)
+	.DW	0			; CHS START ADDRESS (CYL/SEC)
+	.DB	0			; PART TYPE ID
+	.DB	0			; CHS LAST ADDRESS (HEAD)
+	.DW	0			; CHS LAST ADDRESS (CYL/SEC)
+	.DW	0,0			; LBA FIRST (DWORD)
+	.DW	0,0			; LBA COUNT (DWORD)
+;
+; THE END OF THE FIRST SECTOR MUST CONTAIN THE TWO BYTE BOOT SIGNATURE.
+;
+BOOTSIG	.DB	$55,$AA			; STANDARD BOOT SIGNATURE
+;
+;-------------------------------------------------------------------------------
+; SECTOR 2
+;
+;   THIS SECTOR HAS NOT BEEN DEFINED AND IS RESERVED.
+;
+;----------------------------------------------------------------------------
+;
+	.FILL	SEC_SIZE,0			; JUST FILL SECTOR WITH ZEROES
+;
+;-------------------------------------------------------------------------------
+; SECTOR 3
+;
+;   OS AND DISK METADATA
+;
+;----------------------------------------------------------------------------
+;
+	.FILL	(BLK_SIZE * 3),0	; FIRST 384 BYTES ARE NOT YET DEFINED
+;
+; THE FOLLOWING TWO BYTES ARE AN ADDITIONAL SIGNATURE THAT IS VERIFIED BY
+; SOME HARDWARE BIOSES.
+;
+PR_SIG		.DB	$5A,$A5		; SIGNATURE GOES HERE
+;
+		.FILL	(META_LOC - $),0
+;
+; METADATA
+;
+PR_WP		.DB	0		; (1) WRITE PROTECT BOOLEAN
+PR_UPDSEQ	.DW	0		; (2) PREFIX UPDATE SEQUENCE NUMBER (DEPRECATED?)
+PR_VER		.DB	RMJ,RMN,RUP,RTP	; (4) OS BUILD VERSION
+PR_LABEL	.DB	"Unlabeled$$$$$$$","$"	; (17) DISK LABEL (EXACTLY 16 BYTES!!!)
+		.DW	0		; (2) DEPRECATED
+PR_LDLOC	.DW	SYS_LOC		; (2) ADDRESS TO START LOADING SYSTEM
+PR_LDEND	.DW	SYS_END		; (2) ADDRESS TO STOP LOADING SYSTEM
+PR_ENTRY	.DW	SYS_ENT		; (2) ADDRESS TO ENTER SYSTEM (OS)
+;
+#IF (META_SIZE != ($ - META_LOC))
+	.ECHO "META_SIZE VALUE IS WRONG!!!\r\n"
+	!!!
+#ENDIF
+;
+#IF ($ != PREFIX_SIZE)
+	.ECHO "LOADER PREFIX IS WRONG SIZE!!!\r\n"
+	!!!
+#ENDIF
+;
+	.END

Source/ver.inc

@@ -2,7 +2,7 @@
 #DEFINE	RMN	3
 #DEFINE	RUP	0
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.3.0-dev.38"
+#DEFINE BIOSVER	"3.3.0-dev.56"
 #define rmj	RMJ
 #define rmn	RMN
 #define rup	RUP

Source/ver.lib

@@ -3,5 +3,5 @@ rmn	equ	3
 rup	equ	0
 rtp	equ	0
 biosver	macro
-	db	"3.3.0-dev.38"
+	db	"3.3.0-dev.56"
 	endm