Enable Duodyne Front Panel

- Support for LEDs and switches by default

ReadMe.md

@@ -3,7 +3,7 @@
 **RomWBW ReadMe** \
 Version 3.4 \
 Wayne Warthen  ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \
-27 Nov 2023
+30 Nov 2023
 
 # Overview
 
@@ -14,15 +14,24 @@ platforms are supported including those produced by these developer
 communities:
 
 - [RetroBrew Computers](https://www.retrobrewcomputers.org)
-- [RC2014](https://rc2014.co.uk),
+  (<https://www.retrobrewcomputers.org>)
+- [RC2014](https://rc2014.co.uk) (<https://rc2014.co.uk>),  
   [RC2014-Z80](https://groups.google.com/g/rc2014-z80)
-- [retro-comp](https://groups.google.com/forum/#!forum/retro-comp)
+  (<https://groups.google.com/g/rc2014-z80>)
+- [Retro Computing](https://groups.google.com/g/retro-comp)
+  (<https://groups.google.com/g/retro-comp>)
 - [Small Computer Central](https://smallcomputercentral.com/)
+  (<https://smallcomputercentral.com/>)
+
+A complete list of the currently supported platforms is found in the
+\[Installation\] section.
 
 General features include:
 
+- Z80 Family CPUs including Z80, Z180, and Z280
 - Banked memory services for several banking designs
-- Disk drivers for RAM, ROM, Floppy, IDE, CF, and SD
+- Disk drivers for RAM, ROM, Floppy, IDE ATA/ATAPI, CF, SD, USB, Zip,
+  Iomega
 - Serial drivers including UART (16550-like), ASCI, ACIA, SIO
 - Video drivers including TMS9918, SY6545, MOS8563, HD6445
 - Keyboard (PS/2) drivers via VT8242 or PPI interfaces
@@ -42,11 +51,11 @@ ROM firmware itself:
 
 A dynamic disk drive letter assignment mechanism allows mapping
 operating system drive letters to any available disk media.
-Additionally, mass storage devices (IDE Disk, CF Card, SD Card) support
-the use of multiple slices (up to 256 per device). Each slice contains a
-complete CP/M filesystem and can be mapped independently to any drive
-letter. This overcomes the inherent size limitations in legacy OSes and
-allows up to 2GB of accessible storage on a single device.
+Additionally, mass storage devices (IDE Disk, CF Card, SD Card, etc.)
+support the use of multiple slices (up to 256 per device). Each slice
+contains a complete CP/M filesystem and can be mapped independently to
+any drive letter. This overcomes the inherent size limitations in legacy
+OSes and allows up to 2GB of accessible storage on a single device.
 
 The pre-built ROM firmware images are generally suitable for most users.
 However, it is also very easy to modify and build custom ROM images that
@@ -66,7 +75,7 @@ changing media.
 By design, RomWBW isolates all of the hardware specific functions in the
 ROM chip itself. The ROM provides a hardware abstraction layer such that
 all of the operating systems and applications on a disk will run on any
-RomWBW-based system. To put it simply, you can take a disk (or CF/SD
+RomWBW-based system. To put it simply, you can take a disk (or CF/SD/USB
 Card) and move it between systems transparently.
 
 A tool is provided that allows you to access a FAT-12/16/32 filesystem.
@@ -76,18 +85,19 @@ OSes such as Windows, MacOS, and Linux very easy.
 
 # Acquiring RomWBW
 
-The [RomWBW Repository](https://github.com/wwarthen/RomWBW) on GitHub is
-the official distribution location for all project source and
-documentation. The fully-built distribution releases are available on
-the [RomWBW Releases Page](https://github.com/wwarthen/RomWBW/releases)
-of the repository. On this page, you will normally see a Development
-Snapshot as well as recent stable releases. Unless you have a specific
-reason, I suggest you stick to the most recent stable release. Expand
-the “Assets” drop-down for the release you want to download, then select
-the asset named RomWBW-vX.X.X-Package.zip. The Package asset includes
-all pre-built ROM and Disk images as well as full source code. The other
-assets contain only source code and do not have the pre-built ROM or
-disk images.
+The [RomWBW Repository](https://github.com/wwarthen/RomWBW)
+(<https://github.com/wwarthen/RomWBW>) on GitHub is the official
+distribution location for all project source and documentation. The
+fully-built distribution releases are available on the [RomWBW Releases
+Page](https://github.com/wwarthen/RomWBW/releases)
+(<https://github.com/wwarthen/RomWBW/releases>) of the repository. On
+this page, you will normally see a Development Snapshot as well as
+recent stable releases. Unless you have a specific reason, I suggest you
+stick to the most recent stable release. Expand the “Assets” drop-down
+for the release you want to download, then select the asset named
+RomWBW-vX.X.X-Package.zip. The Package asset includes all pre-built ROM
+and Disk images as well as full source code. The other assets contain
+only source code and do not have the pre-built ROM or disk images.
 
 All source code and distributions are maintained on GitHub. Code
 contributions are very welcome.

ReadMe.txt

@@ -1,6 +1,6 @@
 RomWBW ReadMe
 Wayne Warthen (wwarthen@gmail.com)
-27 Nov 2023
+30 Nov 2023
 
 
 
@@ -13,15 +13,21 @@ Z80/180/280 retro-computing hardware systems. A wide variety of
 platforms are supported including those produced by these developer
 communities:
 
--   RetroBrew Computers
--   RC2014, RC2014-Z80
--   retro-comp
--   Small Computer Central
+-   RetroBrew Computers (https://www.retrobrewcomputers.org)
+-   RC2014 (https://rc2014.co.uk),
+    RC2014-Z80 (https://groups.google.com/g/rc2014-z80)
+-   Retro Computing (https://groups.google.com/g/retro-comp)
+-   Small Computer Central (https://smallcomputercentral.com/)
+
+A complete list of the currently supported platforms is found in the
+[Installation] section.
 
 General features include:
 
+-   Z80 Family CPUs including Z80, Z180, and Z280
 -   Banked memory services for several banking designs
--   Disk drivers for RAM, ROM, Floppy, IDE, CF, and SD
+-   Disk drivers for RAM, ROM, Floppy, IDE ATA/ATAPI, CF, SD, USB, Zip,
+    Iomega
 -   Serial drivers including UART (16550-like), ASCI, ACIA, SIO
 -   Video drivers including TMS9918, SY6545, MOS8563, HD6445
 -   Keyboard (PS/2) drivers via VT8242 or PPI interfaces
@@ -41,11 +47,11 @@ ROM firmware itself:
 
 A dynamic disk drive letter assignment mechanism allows mapping
 operating system drive letters to any available disk media.
-Additionally, mass storage devices (IDE Disk, CF Card, SD Card) support
-the use of multiple slices (up to 256 per device). Each slice contains a
-complete CP/M filesystem and can be mapped independently to any drive
-letter. This overcomes the inherent size limitations in legacy OSes and
-allows up to 2GB of accessible storage on a single device.
+Additionally, mass storage devices (IDE Disk, CF Card, SD Card, etc.)
+support the use of multiple slices (up to 256 per device). Each slice
+contains a complete CP/M filesystem and can be mapped independently to
+any drive letter. This overcomes the inherent size limitations in legacy
+OSes and allows up to 2GB of accessible storage on a single device.
 
 The pre-built ROM firmware images are generally suitable for most users.
 However, it is also very easy to modify and build custom ROM images that
@@ -65,7 +71,7 @@ changing media.
 By design, RomWBW isolates all of the hardware specific functions in the
 ROM chip itself. The ROM provides a hardware abstraction layer such that
 all of the operating systems and applications on a disk will run on any
-RomWBW-based system. To put it simply, you can take a disk (or CF/SD
+RomWBW-based system. To put it simply, you can take a disk (or CF/SD/USB
 Card) and move it between systems transparently.
 
 A tool is provided that allows you to access a FAT-12/16/32 filesystem.
@@ -78,16 +84,18 @@ OSes such as Windows, MacOS, and Linux very easy.
 ACQUIRING ROMWBW
 
 
-The RomWBW Repository on GitHub is the official distribution location
-for all project source and documentation. The fully-built distribution
-releases are available on the RomWBW Releases Page of the repository. On
-this page, you will normally see a Development Snapshot as well as
-recent stable releases. Unless you have a specific reason, I suggest you
-stick to the most recent stable release. Expand the “Assets” drop-down
-for the release you want to download, then select the asset named
-RomWBW-vX.X.X-Package.zip. The Package asset includes all pre-built ROM
-and Disk images as well as full source code. The other assets contain
-only source code and do not have the pre-built ROM or disk images.
+The RomWBW Repository (https://github.com/wwarthen/RomWBW) on GitHub is
+the official distribution location for all project source and
+documentation. The fully-built distribution releases are available on
+the RomWBW Releases Page (https://github.com/wwarthen/RomWBW/releases)
+of the repository. On this page, you will normally see a Development
+Snapshot as well as recent stable releases. Unless you have a specific
+reason, I suggest you stick to the most recent stable release. Expand
+the “Assets” drop-down for the release you want to download, then select
+the asset named RomWBW-vX.X.X-Package.zip. The Package asset includes
+all pre-built ROM and Disk images as well as full source code. The other
+assets contain only source code and do not have the pre-built ROM or
+disk images.
 
 All source code and distributions are maintained on GitHub. Code
 contributions are very welcome.

Source/Apps/Build.cmd

@@ -1,13 +1,10 @@
 @echo off
 setlocal
 
-set TOOLS=../../Tools
+set TOOLS=..\..\Tools
 set APPBIN=..\..\Binary\Apps
-
 set PATH=%TOOLS%\tasm32;%TOOLS%\zxcc;%PATH%
-
 set TASMTABS=%TOOLS%\tasm32
-
 set CPMDIR80=%TOOLS%/cpm/
 
 call :asm syscopy || exit /b

Source/BPBIOS/Build.cmd

@@ -3,8 +3,8 @@ setlocal
 
 pushd ZCPR33 && call Build || exit /b & popd
 
-set PATH=%PATH%;..\..\Tools\zxcc;..\..\Tools\cpmtools;
-
+set TOOLS=..\..\Tools
+set PATH=%PATH%;%TOOLS%\zxcc;%TOOLS%\cpmtools;
 set CPMDIR80=%TOOLS%/cpm/
 
 call :makebp 33
@@ -48,7 +48,8 @@ if exist bp%VER%.prn del bp%VER%.prn || exit /b
 ren bpbio-ww.prn bp%VER%.prn || exit /b
 if exist bp%VER%.err del bp%VER%.err || exit /b
 ren bpbio-ww.err bp%VER%.err || exit /b
-copy bpbio-ww.rel bp%VER%.rel || exit /b
+if exist bp%VER%.rel del bp%VER%.rel || exit /b
+ren bpbio-ww.rel bp%VER%.rel || exit /b
 
 rem pause
 

Source/BPBIOS/Makefile

@@ -1,44 +1,37 @@
 VERSIONS = \
-	33t 33tbnk \
-	33n 33nbnk \
-	34t 34tbnk \
-	34n 34nbnk \
-	41tbnk 41nbnk
+	33 33bnk \
+	33 33bnk \
+	34 34bnk \
+	34 34bnk \
+	41bnk
 
-HD0IMG = ../../Binary/hd_bp.img
 IMGFILES = $(foreach ver,$(VERSIONS),bp$(ver).img)
 DISTFILES = *.zex *.rel myterm.z3t
 
-OTHERS = zcpr33n.rel zcpr33t.rel \
-	bpbio-ww.rel bpsys.dat bpsys.bak bpbio-ww.err def-ww.lib *.img
+OTHERS = zcpr33.rel bp*.prn bp*.rel \
+	bpbio-ww.rel bpsys.dat bpsys.bak bpbio-ww.err def-ww.lib bp*.img
 
 TOOLS = ../../Tools
 
 SUBDIRS = ZCPR33
 include $(TOOLS)/Makefile.inc
 
-$(HD0IMG): $(IMGFILES)
-	if [ -f $(HD0IMG) ] ; then \
-		for f in $(IMGFILES) $(DISTFILES) ; do \
-			$(BINDIR)/cpmrm -f wbw_hd0 $(HD0IMG) 0:$$f ; \
-		done ; \
-		$(CPMCP) -f wbw_hd0 $(HD0IMG) $(IMGFILES) $(DISTFILES) 0: ; \
-	fi
-
-zcpr33n.rel zcpr33t.rel:
+zcpr33.rel:
 	(cd ZCPR33 ; make)
 
-all:: $(HD0IMG)
+all:: $(IMGFILES)
 
-clean::
-	@rm -f $(HD0IMG)
+# clean::
+# 	$(MAKE) --directory ZCPR3 clean
 
-%.img: zcpr33n.rel zcpr33t.rel
+%.img: zcpr33.rel
 	$(eval VER := $(subst .img,,$(subst bp,,$@)))
 	cp def-ww-z$(VER).lib def-ww.lib
 	rm -f bpbio-ww.rel
 	$(ZXCC) ZMAC -BPBIO-WW -/P
 	mv bpbio-ww.prn bp$(VER).prn
+	if [ -f bpbio-ww.err ] ; then mv bpbio-ww.err bp$(VER).err; fi
+	mv bpbio-ww.rel bp$(VER).rel
 	cp bp$(VER).dat bpsys.dat
 	$(ZXCC) ./bpbuild.com -bpsys.dat 0 < bpbld1.rsp
 	cp bpsys.img bpsys.dat

Source/BPBIOS/ZCPR33/Build.cmd

@@ -1,8 +1,8 @@
 @echo off
 setlocal
 
-set PATH=%PATH%;..\..\..\Tools\zxcc;..\..\..\Tools\cpmtools;
-
+set TOOLS=..\..\..\Tools
+set PATH=%PATH%;%TOOLS%\zxcc;%TOOLS%\cpmtools;
 set CPMDIR80=%TOOLS%/cpm/
 
 copy ..\z3base.lib . || exit /b

Source/BPBIOS/ZCPR33/Makefile

@@ -1,5 +1,5 @@
-OBJECTS = zcpr33n.rel zcpr33t.rel
-OTHERS = z3basen.lib z3baset.lib
+OBJECTS = zcpr33.rel
+OTHERS = z3base.lib *.prn *.rel
 TOOLS = ../../../Tools
 DEST = ..
 
@@ -7,12 +7,7 @@ include $(TOOLS)/Makefile.inc
 
 DIFFPATH = $(DIFFTO)/Source/BPBIOS
 
-zcpr33t.rel: ../z3baset.lib
-	cp ../z3baset.lib z3baset.lib
-	$(ZXCC) ZMAC -zcpr33t.z80 -/P
-	rm z3baset.lib
-
-zcpr33n.rel: ../z3basen.lib
-	cp ../z3basen.lib z3basen.lib
-	$(ZXCC) ZMAC -zcpr33n.z80 -/P
-	rm z3basen.lib
+zcpr33.rel: ../z3base.lib
+	cp ../z3base.lib z3base.lib
+	$(ZXCC) ZMAC -zcpr33.z80 -/P
+	rm z3base.lib

Source/BPBIOS/cboot-ww.z80

@@ -102,6 +102,9 @@ CBOOT:
 ; BPCNFG to configure a generic IMG file for specific Hard Drive Partitions.
 
 CBOOT0:
+	LD	BC,HBF_SYSRES_INT	; HB Func: Internal Reset
+	CALL	HBX_INVOKE		; Do it
+
 	LD	HL,BRAME	; Get end of banked RAM
 	LD	(HISAV),HL	;   and save for later use
 	  IF  HARDDSK

Source/BPBIOS/deblock.z80

@@ -268,16 +268,15 @@ MATCH:	LD	A,(SECMSK)	; Get the sector mask
 ;
 ; Modified to use HBIOS host buffer
 ;
-	; HSTBUF is always in HBIOS bank where I/O is done
-	LD	A,(TPABNK)	; TPA BANK
-	DEC	A		; HBIOS bank is one below
-	LD	C,A
+	; HSTBUF is always in HBIOS bank where I/O is actually done
+	LD	A,(HB_BNKBIOS)	; HBIOS bank id
+	LD	C,A		; Set Read Source Bank
 	  IF  BANKED
-	LD	A,(DMABNK)	; Set Read Destination Bank
+	LD	A,(DMABNK)	; Read Destination Bank
 	  ELSE
-	LD	A,(TPABNK)	; Set Read Destination Bank
+	LD	A,(TPABNK)	; Read Destination Bank
 	  ENDIF
-	LD	B,A
+	LD	B,A		; Set Read Destination Bank
 	LD	A,(READOP)	; Direction?
 	OR	A
 	JR	NZ,OKBNKS	; ..jump if read

Source/BPBIOS/def-ww-z33.lib

@@ -133,8 +133,8 @@ BNK1	EQU	BID_COM		;   Second TPA Bank (Common Bank)	48000H
 BNK2	EQU	BID_SYS		; System Bank (BIOS, DOS, CPR)		50000H
 BNKU	EQU	00H		; User Area Bank			58000H
 				; (set to 0 to disable)
-BNK3	EQU	BID_RAMD	; First Bank for RAM disk		60000H
-BNKM	EQU	BID_RAMM	; Maximum Bank #			F8000H
+BNK3	EQU	BID_BUF		; First Bank for RAM disk		60000H
+BNKM	EQU	BID_BUF		; Maximum Bank #			F8000H
 
 	  IF  NO	; REMOVE CODE - NOT NEEDED WITH HBIOS makes a
        			; nice resource for Z180 programing in general

Source/BPBIOS/def-ww-z33bnk.lib

@@ -133,8 +133,8 @@ BNK1	EQU	BID_COM		;   Second TPA Bank (Common Bank)	48000H
 BNK2	EQU	BID_SYS		; System Bank (BIOS, DOS, CPR)		50000H
 BNKU	EQU	00H		; User Area Bank			58000H
 				; (set to 0 to disable)
-BNK3	EQU	BID_RAMD	; First Bank for RAM disk		60000H
-BNKM	EQU	BID_RAMM	; Maximum Bank #			F8000H
+BNK3	EQU	BID_BUF		; First Bank for RAM disk		60000H
+BNKM	EQU	BID_BUF		; Maximum Bank #			F8000H
 
 	  IF  NO	; REMOVE CODE - NOT NEEDED WITH HBIOS makes a
        			; nice resource for Z180 programing in general

Source/BPBIOS/def-ww-z34.lib

@@ -133,8 +133,8 @@ BNK1	EQU	BID_COM		;   Second TPA Bank (Common Bank)	48000H
 BNK2	EQU	BID_SYS		; System Bank (BIOS, DOS, CPR)		50000H
 BNKU	EQU	00H		; User Area Bank			58000H
 				; (set to 0 to disable)
-BNK3	EQU	BID_RAMD	; First Bank for RAM disk		60000H
-BNKM	EQU	BID_RAMM	; Maximum Bank #			F8000H
+BNK3	EQU	BID_BUF		; First Bank for RAM disk		60000H
+BNKM	EQU	BID_BUF		; Maximum Bank #			F8000H
 
 	  IF  NO	; REMOVE CODE - NOT NEEDED WITH HBIOS makes a
        			; nice resource for Z180 programing in general

Source/BPBIOS/def-ww-z34bnk.lib

@@ -133,8 +133,8 @@ BNK1	EQU	BID_COM		;   Second TPA Bank (Common Bank)	48000H
 BNK2	EQU	BID_SYS		; System Bank (BIOS, DOS, CPR)		50000H
 BNKU	EQU	00H		; User Area Bank			58000H
 				; (set to 0 to disable)
-BNK3	EQU	BID_RAMD	; First Bank for RAM disk		60000H
-BNKM	EQU	BID_RAMM	; Maximum Bank #			F8000H
+BNK3	EQU	BID_BUF		; First Bank for RAM disk		60000H
+BNKM	EQU	BID_BUF		; Maximum Bank #			F8000H
 
 	  IF  NO	; REMOVE CODE - NOT NEEDED WITH HBIOS makes a
        			; nice resource for Z180 programing in general

Source/BPBIOS/def-ww-z41bnk.lib

@@ -133,8 +133,8 @@ BNK1	EQU	BID_COM		;   Second TPA Bank (Common Bank)	48000H
 BNK2	EQU	BID_SYS		; System Bank (BIOS, DOS, CPR)		50000H
 BNKU	EQU	00H		; User Area Bank			58000H
 				; (set to 0 to disable)
-BNK3	EQU	BID_RAMD	; First Bank for RAM disk		60000H
-BNKM	EQU	BID_RAMM	; Maximum Bank #			F8000H
+BNK3	EQU	BID_BUF		; First Bank for RAM disk		60000H
+BNKM	EQU	BID_BUF		; Maximum Bank #			F8000H
 
 	  IF  NO	; REMOVE CODE - NOT NEEDED WITH HBIOS makes a
        			; nice resource for Z180 programing in general

Source/BPBIOS/dpbhd-ww.lib

@@ -46,7 +46,7 @@
 ; NOTE: No Skew Table needed since Hard Disk Format is locked w/No Skew 
 
 ;.....
-; Currently, BPBIOS supports 2 memory drive devices and 3 phyical hard 
+; Currently, BPBIOS supports 2 memory drive devices and 3 physical hard 
 ;	drive like devices.  BPBIOS can support seven but unfortunately
 ;	BPCNFG only supports 3 hard drive like devices and the source 
 ;	code is not available, so menu 4 is meaningless.  Devices 
@@ -64,26 +64,22 @@
 ;
 ;	Starting with ver 2.8 of HBIOS, devices are discovered at boot
 ;	time and assigned device numbers.  Since devices are tested in
-;	a certain order, the device numbers are somewhat predicably 
+;	a certain order, the device numbers are somewhat predictably 
 ;	assigned.  Memory drives are discovered first.  IDE drives are 
 ;	discovered next so that IDE Hard drives including CF cards are 
 ;	assigned device 2 and device 3 if a slave drive is supported by
 ;	the interface.  Next comes the SD drive and is assigned device 3
 ;	or 4 depending on the whether there is an ide slave drive.
-;	USB drive is assigned device 4 or 5 .  For SIMH HDSK0 is device 0
+;	USB drive is assigned device 4 or 5.  For SIMH HDSK0 is device 0
 ;	and HDSK1 is device 1.  Memory drives are now handled as LBA
 ;	devices, ie like hard drives.
 ;
 ; The following non-memory drive capacities and configurations used for 
-; the SIMH, SD and IDE drives: Slice geometry is 256, 512 byte sectors, 
-; 1 head per track and 1 with one reserved track, a block size of 4096 
-; bytes with 512 directory entries.  An equivalent geometry is 16 
-; sectors and 16 heads per track.  Internally BPBIOS uses a uniform 
-; logical organization with 64 logical records per logical track.  
-; Thus there are 16 logical tracks per physical track with 1040 
-; logical (65 physical) tracks per slice.  If all partitions are not 
-; physically present, the missing partitions can be disabled in the 
-; BPBCNFG configuration file or by hand.  Note that HBIOS uses LBA, 
+; the SIMH, SD and IDE drives: Track geometry is 16 512 byte sectors.
+; A slice is exactly 64 tracks, with 1 of the 64 tracks as a system
+; track.  There are 1024 directory entries per slice. If all partitions
+; are not physically present, the missing partitions can be disabled in
+; the BPBCNFG configuration file or by hand.  Note that HBIOS uses LBA, 
 ; Logical Block Addressing, for non-floppy drives.
 ;
 ; For SBC V1,2, ZETA, MARK IV and N8, the following non-memory partitions 
@@ -94,26 +90,26 @@
 ;	partition	Size	Blocks	Block 	Offset in
 ;			MByte		Size	logical tracks
 ;====================================================================
-;	   C		 8	 2048	4096	1*16          = 16
-;	   D		 8	 2048	4096	(1+65)*16     = 1056
-;	   E		 8	 2048	4096	(1+2*65)*16   = 2096
-;	   F		 8	 2048	4096	(1+3*65)*16   = 3136
-;	   G		 8	 2048	4096	(1+4*65)*16   = 4176
-;	   H		 8	 2048	4096	(1+5*65)*16   = 5216
-;	   I		 8	 2048	4096	(1+6*65)*16   = 6256
-;	   J		 8	 2048	4096	(1+7*65)*16   = 7296
+;	   C		 8	 2044	4096	128+(1024*0)+2 = 130
+;	   D		 8	 2044	4096	128+(1024*1)+2 = 1154
+;	   E		 8	 2044	4096	128+(1024*2)+2 = 2178
+;	   F		 8	 2044	4096	128+(1024*3)+2 = 3202
+;	   G		 8	 2044	4096	128+(1024*4)+2 = 4226
+;	   H		 8	 2044	4096	128+(1024*5)+2 = 5250
+;	   I		 8	 2044	4096	128+(1024*6)+2 = 6274
+;	   J		 8	 2044	4096	128+(1024*7)+2 = 7298
 ;
 ; These are capacities and configurations used for SD card:
 ;
 ;	partition	Size	Blocks	Block 	Offset
 ;			MByte		Size	logical tracks
 ;====================================================================
-;	   K		 8	 2048	4096	1*16          = 16
-;	   L		 8	 2048	4096	(1+65)*16     = 1056
-;	   M		 8	 2048	4096	(1+2*65)*16   = 2096
-;	   N		 8	 2048	4096	(1+3*65)*16   = 3136
+;	   K		 8	 2044	4096	128+(1024*0)+2 = 130
+;	   L		 8	 2044	4096	128+(1024*1)+2 = 1154
+;	   M		 8	 2044	4096	128+(1024*2)+2 = 2178
+;	   N		 8	 2044	4096	128+(1024*3)+2 = 3202
 ;
-; RAM drive is paritition A while ROM drive is partition B. 
+; RAM drive is partition A while ROM drive is partition B. 
 ;
 ; For example, a typical Memory drive configuration is: 
 ;
@@ -199,17 +195,17 @@ DPBROM:	DEFW	64		; Sectors/Track
 				;  even though real layout is 256 physical
 				;  sectors per track
 	DEFB	0		; Physical tracks/side (No Meaning in HD)
-HSIZ0	EQU	2048		; # of blocks in first Partition  (1024 trks)
+HSIZ0	EQU	2048 - 4	; # of blocks in first Partition  (1022 trks)
 				;	
 DPB50:	DEFW	64		; Sctrs/Trk	
 	DEFB	5		; Blk Shf Fctr	
 	DEFB	31		; Block Mask	
 	DEFB	1		; Extent Mask	
-	DEFW	HSIZ0-1		; Disk Size-1	
-	DEFW	511		; Dir Max-1 - 4 blocks	
-	DEFB	0F0H,0		; Alloc 0,1 - 4 blocks	
+	DEFW	HSIZ0-1		; Disk Size-1
+	DEFW	1024-1		; Dir Max-1
+	DEFB	0FFH,0		; Alloc 0,1
 	DEFW	0		; Check Size	
-	DEFW	16		; Trk Offset	
+	DEFW	128+(1024*0)+2	; Trk Offset
 	  ENDIF
 ;
 ;.....
@@ -226,17 +222,17 @@ DPB50:	DEFW	64		; Sctrs/Trk
 				; sectors per track
 	DEFB	0		; Physical tracks/side (No Meaning in HD)
 
-HSIZ1	EQU	2048		; # of blocks in Second Partition  (1024 trks)
+HSIZ1	EQU	2048 - 4	; # of blocks in Second Partition  (1022 trks)
 				;		
 DPB51:	DEFW	64		; Scts/Trk	
 	DEFB	5		; Blk Shf Fctr
 	DEFB	31		; Block Mask	
 	DEFB	1		; Extent Mask	
 	DEFW	HSIZ1-1		; Disk Size-1	
-	DEFW	511		; Dir Max-1	4 blocks
-	DEFB	0F0H,0		; Alloc 0,1	
+	DEFW	1024-1		; Dir Max-1
+	DEFB	0FFH,0		; Alloc 0,1
 	DEFW	0		; Check size	
-	DEFW	(1+65)*16	; Track offset	1056
+	DEFW	128+(1024*1)+2	; Trk Offset
 	  ENDIF
 ;
 ;.....
@@ -253,21 +249,21 @@ DPB51:	DEFW	64		; Scts/Trk
 				; sectors per track
 	DEFB	0		; Physical tracks/side (No Meaning in HD)
 
-HSIZ2	EQU	2048		; # of blocks in third Partition (1024 tracks)
+HSIZ2	EQU	2048 - 4	; # of blocks in Second Partition  (1022 trks)
 				;	
 DPB52:	DEFW	64		; Scts/Trk	
 	DEFB	5		; Blk Shf Fctr	
 	DEFB	31		; Block Mask	
 	DEFB	1		; Extent Mask	
 	DEFW	HSIZ2-1		; Disk Size-1	
-	DEFW	511		; Dir Max-1	4 blocks
-	DEFB	0F0H,0		; Alloc 0,1	
+	DEFW	1024-1		; Dir Max-1
+	DEFB	0FFH,0		; Alloc 0,1
 	DEFW	0		; Check size	
-	DEFW	(1+2*65)*16	; Track offset = 2096
+	DEFW	128+(1024*2)+2	; Trk Offset
 	  ENDIF
 ;
 ;.....
-; Partition F.  HBIOS Disk 0, Slice 4
+; Partition F.  HBIOS Disk 0, Slice 3
 
 	  IF  DRV_F
 	DEFB	'HBDSK0:3 ','F'+80H ; Id - 10 bytes
@@ -280,17 +276,17 @@ DPB52:	DEFW	64		; Scts/Trk
 				; sectors per track
 	DEFB	0		; Physical tracks/side (No Meaning in HD)
 
-HSIZ3	EQU	2048		; # of blocks in Fourth Partition (1024 tracks)
+HSIZ3	EQU	2048 - 4	; # of blocks in Second Partition  (1022 trks)
 				;	
 DPB53:	DEFW	64		; Scts/Trk	
 	DEFB	5		; Blk Shf Fctr	
 	DEFB	31		; Block Mask	
 	DEFB	1		; Extent Mask	
 	DEFW	HSIZ3-1		; Disk Size-1	
-	DEFW	511		; Dir Max-1	4 blocks
-	DEFB	0F0H,0		; Alloc 0,1	
+	DEFW	1024-1		; Dir Max-1
+	DEFB	0FFH,0		; Alloc 0,1
 	DEFW	0		; Check size	
-	DEFW	(1+3*65)*16	; Track offset = 3136
+	DEFW	128+(1024*3)+2	; Trk Offset
 	  ENDIF
 ;	
 ;.....
@@ -307,17 +303,17 @@ DPB53:	DEFW	64		; Scts/Trk
 				; sectors per track
 	DEFB	0		; Physical tracks/side (No Meaning in HD)
 
-HSIZ4	EQU	2048		; # of blocks in first Partition  (1024 trks)
+HSIZ4	EQU	2048 - 4	; # of blocks in Second Partition  (1022 trks)
 				;	
 DPB54:	DEFW	64		; Sctrs/Trk	
 	DEFB	5		; Blk Shf Fctr
 	DEFB	31		; Block Mask
 	DEFB	1		; Extent Mask
 	DEFW	HSIZ4-1		; Disk Size - 1
-	DEFW	511		; Dir Max-1	4 blocks
-	DEFB	0F0H,0		; Alloc 0,1	
+	DEFW	1024-1		; Dir Max-1
+	DEFB	0FFH,0		; Alloc 0,1
 	DEFW	0		; Check size	
-	DEFW	(1+4*65)*16	; Track offset = 16
+	DEFW	128+(1024*4)+2	; Trk Offset
 	  ENDIF
 ;
 ;.....
@@ -334,17 +330,17 @@ DPB54:	DEFW	64		; Sctrs/Trk
 				;   sectors per track
 	DEFB	0		; Physical tracks/side (No Meaning in HD)
 
-HSIZ5	EQU	2048		; # of blocks in Second Partition  (1024 trks)
+HSIZ5	EQU	2048 - 4	; # of blocks in Second Partition  (1022 trks)
 				;		
 DPB55:	DEFW	64		; Sctrs/Trk - actually 256	
 	DEFB	5		; Blk Shf Fctr	
 	DEFB	31		; Block Mask	
 	DEFB	1		; Extent Mask	
 	DEFW	HSIZ5-1		; Disk Size-1	
-	DEFW	511		; Dir Max-1	
-	DEFB	0F0H,0		; Alloc 0,1 - 4 blocks	
+	DEFW	1024-1		; Dir Max-1
+	DEFB	0FFH,0		; Alloc 0,1
 	DEFW	0		; Check Size	
-	DEFW	(1+5*65)*16	; Trk Offset = 1056
+	DEFW	128+(1024*5)+2	; Trk Offset
 	  ENDIF
 ;
 ;.....
@@ -361,17 +357,17 @@ DPB55:	DEFW	64		; Sctrs/Trk - actually 256
 				; sectors per track
 	DEFB	0		; Physical tracks/side (No Meaning in HD)
 
-HSIZ6	EQU	2048		; # of blocks in third Partition (1024 tracks)
+HSIZ6	EQU	2048 - 4	; # of blocks in Second Partition  (1022 trks)
 				;	
 DPB56:	DEFW	64		; Scts/Trk	
 	DEFB	5		; Blk Shf Fctr	
 	DEFB	31		; Block Mask	
 	DEFB	1		; Extent Mask	
 	DEFW	HSIZ6-1		; Disk Size-1	
-	DEFW	511		; Dir Max-1	4 blocks
-	DEFB	0F0H,0		; Alloc 0,1	
+	DEFW	1024-1		; Dir Max-1
+	DEFB	0FFH,0		; Alloc 0,1
 	DEFW	0		; Check size	
-	DEFW	(1+6*65)*16	; Track offset	= 2096
+	DEFW	128+(1024*6)+2	; Trk Offset
 	  ENDIF
 
 ;.....
@@ -388,17 +384,17 @@ DPB56:	DEFW	64		; Scts/Trk
 				; sectors per track
 	DEFB	0		; Physical tracks/side (No Meaning in HD)
 
-HSIZ7	EQU	2048		; # of blocks in Fourth Partition (1024 tracks)
+HSIZ7	EQU	2048 - 4	; # of blocks in Second Partition  (1022 trks)
 				;
 DPB57:	DEFW	64		; Scts/Trk	
 	DEFB	5		; Blk Shf Fctr	
 	DEFB	31		; Block Mask	
 	DEFB	1		; Extent Mask	
 	DEFW	HSIZ7-1		; Disk Size-1	
-	DEFW	511		; Dir Max-1	4 blocks
-	DEFB	0F0H,0		; Alloc 0,1	
+	DEFW	1024-1		; Dir Max-1
+	DEFB	0FFH,0		; Alloc 0,1
 	DEFW	0		; Check size	
-	DEFW	(1+7*65)*16	; Track offset = 3136
+	DEFW	128+(1024*7)+2	; Trk Offset
 	  ENDIF
 ;
 ;.....
@@ -414,17 +410,18 @@ DPB57:	DEFW	64		; Scts/Trk
 				;  even though real layout is 256 physical
 				;  sectors per track
 	DEFB	0		; Physical tracks/side (No Meaning in HD)
-HSIZ8	EQU	2048		; # of blocks in first Partition  (1024 trks)
+
+HSIZ8	EQU	2048 - 4	; # of blocks in Second Partition  (1022 trks)
 				;	
 DPB58:	DEFW	64		; Sctrs/Trk	
 	DEFB	5		; Blk Shf Fctr	
 	DEFB	31		; Block Mask	
 	DEFB	1		; Extent Mask	
 	DEFW	HSIZ8-1		; Disk Size-1	
-	DEFW	511		; Dir Max-1 - 4 blocks	
-	DEFB	0F0H,0		; Alloc 0,1 - 4 blocks	
+	DEFW	1024-1		; Dir Max-1
+	DEFB	0FFH,0		; Alloc 0,1
 	DEFW	0		; Check Size	
-	DEFW	16		; Trk Offset	
+	DEFW	128+(1024*0)+2	; Trk Offset
 	  ENDIF
 ;
 ;.....
@@ -441,17 +438,17 @@ DPB58:	DEFW	64		; Sctrs/Trk
 				; sectors per track
 	DEFB	0		; Physical tracks/side (No Meaning in HD)
 
-HSIZ9	EQU	2048		; # of blocks in Second Partition  (1024 trks)
+HSIZ9	EQU	2048 - 4	; # of blocks in Second Partition  (1022 trks)
 				;		
 DPB59:	DEFW	64		; Scts/Trk	
 	DEFB	5		; Blk Shf Fctr
 	DEFB	31		; Block Mask	
 	DEFB	1		; Extent Mask	
 	DEFW	HSIZ9-1		; Disk Size-1	
-	DEFW	511		; Dir Max-1	4 blocks
-	DEFB	0F0H,0		; Alloc 0,1	
+	DEFW	1024-1		; Dir Max-1
+	DEFB	0FFH,0		; Alloc 0,1
 	DEFW	0		; Check size	
-	DEFW	(1+65)*16	; Track offset	1056
+	DEFW	128+(1024*1)+2	; Trk Offset
 	  ENDIF
 ;
 ;.....
@@ -468,17 +465,17 @@ DPB59:	DEFW	64		; Scts/Trk
 				; sectors per track
 	DEFB	0		; Physical tracks/side (No Meaning in HD)
 
-HSIZ10	EQU	2048		; # of blocks in Second Partition  (1024 trks)
+HSIZ10	EQU	2048 - 4	; # of blocks in Second Partition  (1022 trks)
 				;		
 DPB60:	DEFW	64		; Scts/Trk
 	DEFB	5		; Blk Shf Fctr
 	DEFB	31		; Block Mask	
 	DEFB	1		; Extent Mask	
-	DEFW	HSIZ10		; Disk Size-1	
-	DEFW	511		; Dir Max-1	4 blocks
-	DEFB	0F0H,0		; Alloc 0,1	
+	DEFW	HSIZ10-1		; Disk Size-1	
+	DEFW	1024-1		; Dir Max-1
+	DEFB	0FFH,0		; Alloc 0,1
 	DEFW	0		; Check size	
-	DEFW	(1+2*65)*16	; Track offset	2096
+	DEFW	128+(1024*2)+2	; Trk Offset
 	  ENDIF
 ;
 ;.....
@@ -492,18 +489,17 @@ DPB60:	DEFW	64		; Scts/Trk
 	DEFB	16		; Logical Sectors per track
 	DEFB	0		; Physical tracks/side (No Meaning in HD)
 
-HSIZ11	EQU	2048		; # of blocks in Forth Logical Drive 
-				;   (1024 tracks)
+HSIZ11	EQU	2048 - 4	; # of blocks in Second Partition  (1022 trks)
 
 DPB61:	DEFW	64		; Scts/Trk
 	DEFB	5		; Blk Shf Fctr
 	DEFB	31		; Block Mask
 	DEFB	1		; Extent Mask
 	DEFW	HSIZ11-1 	; Disk Size-1
-	DEFW	511		; Dir Max-1
-	DEFB	0F0H,0		; Alloc 0,1
+	DEFW	1024-1		; Dir Max-1
+	DEFB	0FFH,0		; Alloc 0,1
 	DEFW	0		; Check size
-	DEFW	(1+3*65)*16	; Track offset	3136
+	DEFW	128+(1024*3)+2	; Trk Offset
 	  ENDIF
 		
 ;=========== End of Hard Disk DPBs ===========

Source/BPBIOS/hard-ww.z80

@@ -183,7 +183,6 @@ HDSK_RW1:
 	POP	BC              ; RESTORE INCOMING FUNCTION, DEVICE/UNIT
 	RET	NZ              ; ABORT IF SEEK RETURNED AN ERROR W/ ERROR IN A
 	LD	HL,(HB_DSKBUF)  ; GET BUFFER ADDRESS
-	;LD	D,BID_HB	; BUFFER IN HBIOS BANK
 	LD	A,(HB_BNKBIOS)	; BUFFER IN HBIOS BANK
 	LD	D,A		; PUT IN D
 	LD	E,1		; ONE SECTOR

Source/BPBIOS/hbios.z80

@@ -9,6 +9,7 @@
 HBF_ALLOC	EQU	0F6H		; HBIOS Func: ALLOCATE Heap Memory
 HBF_PEEK	EQU	0FAH		; HBIOS Func: Peek Byte
 HBF_POKE	EQU	0FBH		; HBIOS Func: Poke Byte
+HBF_SYSRES_INT	EQU	0F000H		; HBIOS Func: Internal Reset
 HBF_MEMINFO	EQU	0F8F1H		; HBIOS Func: Get Memory Info
 HBF_BNKINFO	EQU	0F8F2H		; HBIOS Func: Get Bank Info
 ;
@@ -43,22 +44,23 @@ HBX_CPYLEN	EQU	0FFE8H
 ; call here, make required changes, then update the
 ; BIOSJT to point directly to the normal SELMEM routine for
 ; all subsequent calls.
+;
+; When called, the incoming bank id will be the original hard-coded
+; bank id prior to any adjustments.  These original bank id's are
+; coded to be an offset from the ending HBIOS RAM bank id which
+; is (80h + RAM banks).  See romwbw.lib.  We update the requested
+; bank id for this initial call to make it the proper absolute
+; HBIOS bank id.
+;
+; See romwbw.lib for additional RAM bank layout information.
 
-	; BPBIOS	HBIOS		Typical
-	; ------------	--------------	--------------
-	;  -1: <COMMON>	BID_COM		90h - 1 = 8Fh
-	;  -2: TPABNK	BID_USR         90h - 2 = 8Eh
-	;  -3: <HBIOS>	BID_BIOS	90h - 3 = 8Dh	
-	;  -4: SYSBNK	BID_AUX		90h - 4 = 8Ch
-	;  -9: BNKM	BID_AUX-5	90h - 9 = 87h
-	; -16: RAMBNK	RAMD0		90h - 16 = 80h
-	
 HB_SELMEM:
-	PUSH	AF
 	PUSH	BC
 	PUSH	DE
 	PUSH	HL
 	
+	PUSH	AF		; Save incoming bank request
+	
 	  IF HB_DEBUG AND FALSE
 	CALL	PRTSTRD
 	DEFB	'[HB_SELMEM: $'
@@ -68,23 +70,30 @@ HB_SELMEM:
 	  ENDIF
 	
 	LD	BC,HBF_BNKINFO	; HBIOS BNKINFO function
-	CALL	HBX_INVOKE	; DO IT, D=BID_BIOS, E=BID_USER
-	LD	A,D		; BID_BIOS
-	LD	(HB_BNKBIOS),A	; SET HB_BNKBIOS
-	ADD	A,3		; HBIOS + 3
-	LD	(HB_BNKEND),A	; ... is the ending RAM bank
-	  IF BANKED
-	LD	(BNKADJ+1),A	; Dynamically update SELBNK
-	  ENDIF
-	  
+	CALL	HBX_INVOKE	; Do it, D=BIOS bank, E=USER (TPA) bank
+	LD	A,D		; BIOS bank
+	LD	(HB_BNKBIOS),A	; Save it for later (deblock & hard-ww)
+	LD	A,E		; USER (TPA) bank
+	LD	(TPABNK),A	; Update BP register
+	DEC	A		; SYS bank is one below USER
+	LD	(SYSBNK),A	; Update BP register
+	DEC	A		; HBIOS BUF bank is one more below
+	;LD	(UABNK),A	; Set BPBIOS USER bank
+	LD	(RAMBNK),A	; Update BP RAM disk bank register
+	LD	(MAXBNK),A	; Update ending bank register
+	
 	LD	HL,SELMEM	; Future SELMEM calls will
 	LD	(BIOSJT+(27*3)+1),HL	; ... go to real SELMEM
 	
+	POP	BC		; Recover requested bank to B
+	LD	A,(TPABNK)	; Get TPA bank
+	ADD	2		; Offset to ending RAM bank id
+	ADD	B		; Adjust for incoming request
+	
 	POP	HL
 	POP	DE
 	POP	BC
-	POP	AF
-	JP	SELMEM
+	JP	SELMEM		; Continue to normal SELMEM
 	
 ;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
 ; Move Data - Possibly between banks.  This resembles CP/M 3, but
@@ -97,15 +106,10 @@ HB_SELMEM:
 ;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
 
 HB_MOVE:
-	PUSH	HL
-	LD	HL,HB_BNKEND
 	LD	A,(HB_SRCBNK)
-	ADD	A,(HL)		; Adjust for HBIOS bank ids
 	LD	(HBX_SRCBNK),A
 	LD	A,(HB_DSTBNK)
-	ADD	A,(HL)		; Adjust for HBIOS bank ids
 	LD	(HBX_DSTBNK),A
-	POP	HL
 	CALL	HBX_BNKCPY
 	PUSH	HL
 	LD	HL,(TPABNK)	; Get TPA Bank #
@@ -141,6 +145,5 @@ HB_XMOVE:
 HB_SRCBNK:	DEFS	1	; Move Source Bank #
 HB_DSTBNK:	DEFS	1	; Move Destination Bank #
 HB_BNKBIOS:	DEFS	1	; Bank id of HBIOS bank
-HB_BNKEND:	DEFS	1	; End of available RAM banks (last bank + 1)
 HB_DSKBUF:	DEFS	2	; Address of physical disk buffer in HBIOS bank
 

Source/BPBIOS/ibmv-ww.z80

@@ -115,10 +115,22 @@ SELMEM:	LD	(USRBNK),A	; Update user bank
 ;  Must preserve all Registers including Flags.
 ;  All Bank Switching MUST be done by this routine
 ;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
+;
+; Parameter to BNKADJ (ADD) is set dynamically at initialization.
 
 SELBNK:	PUSH	AF		; Save regs
 SELBN0:	LD	(CURBNK),A	; Save as current bank #
-BNKADJ:	ADD	A,90H		; Adjust for HBIOS bank ids
+
+	  IF HB_DEBUG AND FALSE
+
+	CALL	PRTSTRD
+	DEFB	'[SELBNK: $'
+	CALL	PRTHEXBYTE
+	CALL	PRTSTRD
+	DEFB	']$'
+
+	  ENDIF
+
 	CALL	HBX_BNKSEL
 	POP	AF		; restore regs
 	RET
@@ -172,7 +184,7 @@ FRGETB:
 	PUSH	BC		; Save BC
 	PUSH	DE		; Save DE
 	LD	B,0FAH		; HBIOS Peek function
-	LD	D,C		; Bank in D
+	LD	D,C
 	CALL	HBX_INVOKE	; Do it
 	LD	A,E		; Value to A
 	POP	DE		; Restore DE
@@ -203,8 +215,8 @@ FRPUTB:
 	PUSH	BC		; Save BC
 	PUSH	DE		; Save DE
 	LD	B,0FBH		; HBIOS Poke function
-	LD	D,C		; Bank in D
 	LD	E,A		; Value in E
+	LD	D,C
 	CALL	HBX_INVOKE	; Do it
 	POP	DE		; Restore DE
 	POP	BC		; Restore BC

Source/BPBIOS/romwbw.lib

@@ -48,20 +48,33 @@ DRV_P		SET	NO		; YES if system has flopy drives
 ;
 ; RAM/ROM Bank Reserve
 ;
-HB_RAMRESV	EQU	8		; RAM reserve is 8 banks
+HB_RAMRESV	EQU	5		; RAM reserve is 5 banks
 HB_ROMRESV	EQU	4		; ROM reserve is 4 banks
 ;
 ; Layout of RAM banks
 ;
-; TODO: Query system via HBIOS API to determine the actual bank
-; assignments, then adjust BPBIOS operation accordingly.
+; The BID_xxx values below are used to set the initial values of
+; the BPBIOS bank registers (see def-ww-xxx.lib and HB_SELMEM in
+; hbios.z80).  The running values of the BPBIOS bank registers (TPABNK,
+; SYSBNK, etc.) are set to absolute HBIOS bank ids in hbios.z80 during
+; startup.
 ;
-BID_RAMD	EQU	-16	; 90h - 16 = 80h
-BID_RAMM	EQU	-9	; 90h - 9 = 87h
-BID_SYS		EQU	-4	; 90h - 4 = 8Ch
-BID_HB		EQU	-3	; 90h - 3 = 8Dh
-BID_USR		EQU	-2	; 90h - 2 = 8Eh
-BID_COM		EQU	-1	; 90h - 1 = 8Fh
+; The values below are expressed as an offset from the ending HBIOS
+; RAM bank id.  They map to HBIOS bank ids
+; by subtracting from the ending HBIOS bank id (N).  HBIOS RAM bank ids
+; start at 80h.  The ending HBIOS bank id is (80h + RAM banks).  The
+; typical layout assumes 16 banks of RAM starting at HBIOS bank id 80h
+; and ending at bank id 90h (N = 90h).
+;
+; BPBIOS					HBIOS (TYPICAL)
+; --------------------------------------	---------------
+; <HBIOS>					80h   (80h)
+; <RAMD>					81h   (81h)
+; <RAMM>					N - 5 (8Bh)
+BID_BUF	EQU	-4	; BNK3 -> RAMBNK	N - 4 (8Ch)
+BID_SYS	EQU	-3	; BNK2 -> SYSBNK	N - 3 (8Dh)		
+BID_USR	EQU	-2	; BNK0 -> TPABNK	N - 2 (8Eh)		
+BID_COM	EQU	-1	; BNK1 ->		N - 1 (8Fh)		
 ;
 HB_EI	MACRO
 	EI

Source/Build.cmd

@@ -4,7 +4,7 @@ setlocal
 :: call BuildDoc || exit /b
 call BuildProp || exit /b
 call BuildShared || exit /b
-:: call BuildBP || exit /b
+call BuildBP || exit /b
 call BuildImages || exit /b
 call BuildROM %* || exit /b
 call BuildZRC || exit /b

Source/Doc/Book.h

@@ -30,7 +30,9 @@ header-includes:
       {\scshape \bfseries \fontsize{48pt}{56pt} \selectfont $doc_product$ \par}
       {\bfseries \fontsize{32pt}{36pt} \selectfont $doc_title$ \par}
       \vspace{24pt}
-      {\huge $doc_ver$ \\ $doc_date$ \par}
+      {\huge $doc_ver$ \par}
+      \vspace{12pt}
+      {\large Updated $doc_date$ \par}
       \vspace{24pt}
       {\large \itshape $doc_orgname$ \\ \href{http://$doc_orgurl$}{$doc_orgurl$} \par}
       \vspace{12pt}

Source/Doc/ReadMe.md

@@ -10,14 +10,23 @@ A wide variety of platforms are supported including those
 produced by these developer communities:
 
 * [RetroBrew Computers](https://www.retrobrewcomputers.org)
-* [RC2014](https://rc2014.co.uk), [RC2014-Z80](https://groups.google.com/g/rc2014-z80)
-* [retro-comp](https://groups.google.com/forum/#!forum/retro-comp)
+  (<https://www.retrobrewcomputers.org>)
+* [RC2014](https://rc2014.co.uk) (<https://rc2014.co.uk>), \
+  [RC2014-Z80](https://groups.google.com/g/rc2014-z80)
+  (<https://groups.google.com/g/rc2014-z80>)
+* [Retro Computing](https://groups.google.com/g/retro-comp)
+  (<https://groups.google.com/g/retro-comp>)
 * [Small Computer Central](https://smallcomputercentral.com/)
+  (<https://smallcomputercentral.com/>)
+
+A complete list of the currently supported platforms is found in the
+[Installation] section.
 
 General features include:
 
+* Z80 Family CPUs including Z80, Z180, and Z280
 * Banked memory services for several banking designs
-* Disk drivers for RAM, ROM, Floppy, IDE, CF, and SD
+* Disk drivers for RAM, ROM, Floppy, IDE ATA/ATAPI, CF, SD, USB, Zip, Iomega
 * Serial drivers including UART (16550-like), ASCI, ACIA, SIO
 * Video drivers including TMS9918, SY6545, MOS8563, HD6445
 * Keyboard (PS/2) drivers via VT8242 or PPI interfaces
@@ -34,12 +43,12 @@ ROM firmware itself:
 * ROM BASIC (Nascom BASIC and Tasty BASIC)
 * ROM Forth
 
-A dynamic disk drive letter assignment mechanism allows mapping
-operating system drive letters to any available disk media.
-Additionally, mass storage devices (IDE Disk, CF Card, SD Card) support
-the use of multiple slices (up to 256 per device). Each slice contains
-a complete CP/M filesystem and can be mapped independently to any
-drive letter. This overcomes the inherent size limitations in legacy
+A dynamic disk drive letter assignment mechanism allows mapping 
+operating system drive letters to any available disk media. 
+Additionally, mass storage devices (IDE Disk, CF Card, SD Card, etc.) 
+support the use of multiple slices (up to 256 per device). Each slice 
+contains a complete CP/M filesystem and can be mapped independently to 
+any drive letter. This overcomes the inherent size limitations in legacy
 OSes and allows up to 2GB of accessible storage on a single device.
 
 The pre-built ROM firmware images are generally suitable for most
@@ -61,7 +70,7 @@ By design, RomWBW isolates all of the hardware specific functions in
 the ROM chip itself.  The ROM provides a hardware abstraction layer
 such that all of the operating systems and applications on a disk
 will run on any RomWBW-based system.  To put it simply, you can take
-a disk (or CF/SD Card) and move it between systems transparently.
+a disk (or CF/SD/USB Card) and move it between systems transparently.
 
 A tool is provided that allows you to access a FAT-12/16/32 filesystem. 
 The FAT filesystem may be coresident on the same disk media as RomWBW 
@@ -70,18 +79,19 @@ OSes such as Windows, MacOS, and Linux very easy.
 
 # Acquiring RomWBW
 
-The [RomWBW Repository](https://github.com/wwarthen/RomWBW) on GitHub is
-the official distribution location for all project source and
-documentation.  The fully-built distribution releases are available on
-the [RomWBW Releases Page](https://github.com/wwarthen/RomWBW/releases)
-of the repository.  On this page, you will normally see a Development
-Snapshot as well as recent stable releases. Unless you have a specific
-reason, I suggest you stick to the most recent stable release. Expand
-the "Assets" drop-down for the release you want to download, then select
-the asset named RomWBW-vX.X.X-Package.zip. The Package asset includes
-all pre-built ROM and Disk images as well as full source code. The other
-assets contain only source code and do not have the pre-built ROM or
-disk images.
+The [RomWBW Repository](https://github.com/wwarthen/RomWBW)
+(<https://github.com/wwarthen/RomWBW>) on GitHub is the official 
+distribution location for all project source and documentation.  The 
+fully-built distribution releases are available on the
+[RomWBW Releases Page](https://github.com/wwarthen/RomWBW/releases)
+(<https://github.com/wwarthen/RomWBW/releases>) of the repository.  On 
+this page, you will normally see a Development Snapshot as well as 
+recent stable releases. Unless you have a specific reason, I suggest you
+ stick to the most recent stable release. Expand the "Assets" drop-down 
+for the release you want to download, then select the asset named 
+RomWBW-vX.X.X-Package.zip. The Package asset includes all pre-built ROM 
+and Disk images as well as full source code. The other assets contain 
+only source code and do not have the pre-built ROM or disk images.
 
 All source code and distributions are maintained on GitHub. Code
 contributions are very welcome.

Source/HBIOS/Build.cmd

@@ -33,6 +33,16 @@ PowerShell -ExecutionPolicy Unrestricted .\Build.ps1 %* || exit /b
 
 call build_env.cmd
 
+::
+:: Start of the actual build process for a given ROM.
+::
+
+echo.
+echo ============================================================
+echo %ROMName% for Z%CPUType% CPU
+echo ============================================================
+echo.
+
 ::
 :: Create a small app that is used to export key build variables of the build.
 :: Then run the app to output a file with the variables.  Finally, read the
@@ -43,12 +53,6 @@ tasm -t80 -g3 -dCMD hbios_env.asm hbios_env.com hbios_env.lst || exit /b
 zxcc hbios_env >hbios_env.cmd
 call hbios_env.cmd
 
-::
-:: Start of the actual build process for a given ROM.
-::
-
-echo Building %ROMSize%K ROM %ROMName% for Z%CPUType% CPU...
-
 ::
 :: UNA is a special case, check for it and jump if needed.
 ::

Source/HBIOS/acia.asm

@@ -717,6 +717,13 @@ ACIA0_CFG:
         .DW     ACIA0_INT                ; INT HANDLER POINTER
         .DW     (ACIA0CLK / ACIA0DIV) & $FFFF   ; CLOCK FREQ AS
         .DW     (ACIA0CLK / ACIA0DIV) >> 16     ; ... DWORD VALUE
+;
+	.ECHO	"ACIA: IO="
+	.ECHO	ACIA0BASE
+#IF (INTMODE == 1)
+	.ECHO	", INTERRUPTS ENABLED"
+#ENDIF
+	.ECHO	"\n"
 ;
 ACIA_CFGSIZ     .EQU    $ - ACIA_CFG    ; SIZE OF ONE CFG TABLE ENTRY
 ;
@@ -733,6 +740,13 @@ ACIA1_CFG:
         .DW     ACIA1_INT                ; INT HANDLER POINTER
         .DW     (ACIA1CLK / ACIA1DIV) & $FFFF   ; CLOCK FREQ AS
         .DW     (ACIA1CLK / ACIA1DIV) >> 16     ; ... DWORD VALUE
+;
+	.ECHO	"ACIA: IO="
+	.ECHO	ACIA1BASE
+#IF (INTMODE == 1)
+	.ECHO	", INTERRUPTS ENABLED"
+#ENDIF
+	.ECHO	"\n"
 ;
 #ENDIF
 ;

Source/HBIOS/asci.asm

@@ -836,6 +836,13 @@ ASCI1_CFG:
 	.DB	ASCI1_BASE		; BASE PORT
 	.DW	ASCI1CFG		; LINE CONFIGURATION
 	.DW	ASCI1_RCVBUF		; POINTER TO RCV BUFFER STRUCT
+;
+	.ECHO	"ASCI: IO="
+	.ECHO	ASCI1_BASE
+#IF ((ASCIINTS) & (INTMODE >0))
+	.ECHO	", INTERRUPTS ENABLED"
+#ENDIF
+	.ECHO	"\n"
 ;
 ASCI_CFGSIZ	.EQU	$ - ASCI_CFG	; SIZE OF ONE CFG TABLE ENTRY
 ;
@@ -847,6 +854,13 @@ ASCI0_CFG:
 	.DB	ASCI0_BASE		; BASE PORT
 	.DW	ASCI0CFG		; LINE CONFIGURATION
 	.DW	ASCI0_RCVBUF		; POINTER TO RCV BUFFER STRUCT
+;
+	.ECHO	"ASCI: IO="
+	.ECHO	ASCI0_BASE
+#IF ((ASCIINTS) & (INTMODE >0))
+	.ECHO	", INTERRUPTS ENABLED"
+#ENDIF
+	.ECHO	"\n"
 ;
 #ELSE
 ;
@@ -858,6 +872,13 @@ ASCI0_CFG:
 	.DB	ASCI0_BASE		; BASE PORT
 	.DW	ASCI0CFG		; LINE CONFIGURATION
 	.DW	ASCI0_RCVBUF		; POINTER TO RCV BUFFER STRUCT
+;
+	.ECHO	"ASCI: IO="
+	.ECHO	ASCI0_BASE
+#IF ((ASCIINTS) & (INTMODE >0))
+	.ECHO	", INTERRUPTS ENABLED"
+#ENDIF
+	.ECHO	"\n"
 ;
 ASCI_CFGSIZ	.EQU	$ - ASCI_CFG	; SIZE OF ONE CFG TABLE ENTRY
 ;
@@ -869,8 +890,14 @@ ASCI1_CFG:
 	.DB	ASCI1_BASE		; BASE PORT
 	.DW	ASCI1CFG		; LINE CONFIGURATION
 	.DW	ASCI1_RCVBUF		; POINTER TO RCV BUFFER STRUCT
+;
+	.ECHO	"ASCI: IO="
+	.ECHO	ASCI1_BASE
+#IF ((ASCIINTS) & (INTMODE > 0))
+	.ECHO	", INTERRUPTS ENABLED"
+#ENDIF
+	.ECHO	"\n"
 ;
 #ENDIF
 ;
-;
 ASCI_CFGCNT	.EQU	($ - ASCI_CFG) / ASCI_CFGSIZ

Source/HBIOS/ay38910.asm

@@ -19,12 +19,15 @@
 ;  VOLTAGE LEVEL OUTPUT ON A AY-3-8910 IS LOW AND AROUND 2V ON YM2149.
 ;
 AY_RCSND	.EQU	0		; 0 = EB MODULE, 1=MF MODULE
+;
+	.ECHO	"AY38910: MODE="
 ;
 #IF (AYMODE == AYMODE_SCG)
 AY_RSEL		.EQU	$9A
 AY_RDAT		.EQU	$9B
 AY_RIN		.EQU	AY_RSEL
 AY_ACR		.EQU	$9C
+		.ECHO	"SCG"
 #ENDIF
 ;
 #IF (AYMODE == AYMODE_N8)
@@ -32,30 +35,35 @@ AY_RSEL		.EQU	$9C
 AY_RDAT		.EQU	$9D
 AY_RIN		.EQU	AY_RSEL
 AY_ACR		.EQU	N8_DEFACR
+		.ECHO	"N8"
 #ENDIF
 ;
 #IF (AYMODE == AYMODE_RCZ80)
 AY_RSEL		.EQU	$D8
 AY_RDAT		.EQU	$D0
 AY_RIN		.EQU	AY_RSEL+AY_RCSND
+		.ECHO	"RCZ80"
 #ENDIF
 ;
 #IF (AYMODE == AYMODE_RCZ180)
 AY_RSEL		.EQU	$68
 AY_RDAT		.EQU	$60
 AY_RIN		.EQU	AY_RSEL+AY_RCSND
+		.ECHO	"RCZ180"
 #ENDIF
 ;
 #IF (AYMODE == AYMODE_MSX)
 AY_RSEL		.EQU	$A0
 AY_RDAT		.EQU	$A1
 AY_RIN		.EQU	$A2
+		.ECHO	"MSX"
 #ENDIF
 ;
 #IF (AYMODE == AYMODE_LINC)
 AY_RSEL		.EQU	$33
 AY_RDAT		.EQU	$32
 AY_RIN		.EQU	$32
+		.ECHO	"LINC"
 #ENDIF
 ;
 #IF (AYMODE == AYMODE_MBC)
@@ -63,7 +71,14 @@ AY_RSEL		.EQU	$A0
 AY_RDAT		.EQU	$A1
 AY_RIN		.EQU	AY_RSEL
 AY_ACR		.EQU	$A2
+		.ECHO	"MBC"
 #ENDIF
+;
+	.ECHO	", IO="
+	.ECHO	AY_RSEL
+	.ECHO	", CLOCK="
+	.ECHO	AY_CLK
+	.ECHO	" HZ\n"
 ;
 ;======================================================================
 ;
@@ -107,10 +122,6 @@ AY_NOISECNT	.EQU	1		; COUNT NUMBER OF NOISE CHANNELS
 ;#ELSE					; PRESCALE THE TONE PERIOD
 ;AY_SCALE	.EQU	3		; DATA TO MAINTAIN MAXIMUM
 ;#ENDIF					; RANGE AND ACCURACY
-;
-	.ECHO	"AY38910 CLOCK: "
-	.ECHO	AY_CLK
-	.ECHO	"\n"
 ;
 #INCLUDE "audio.inc"
 ;

Source/HBIOS/bqrtc.asm

@@ -91,6 +91,10 @@ BQRTC_UTI	.EQU	%00001000
 
 BQRTC_BUFSIZE	.EQU	6		; 6 BYTE BUFFER (YYMMDDHHMMSS)
 
+		.ECHO	"BQRTC: IO="
+		.ECHO	BQRTC_BASE
+		.ECHO	"\n"
+
 ; RTC Device Initialization Entry
 
 BQRTC_INIT:

Source/HBIOS/cfg_duo.asm

@@ -65,11 +65,11 @@ SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
-FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
-FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
-FPLED_DSKACT	.EQU	FALSE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
-FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
-FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+FPLED_ENABLE	.EQU	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.EQU	$42		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.EQU	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.EQU	$42		; FP: PORT ADDRESS FOR FP SWITCHES
 ;
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;

Source/HBIOS/ch.asm

@@ -102,6 +102,10 @@ CH_CFG0:	; DEVICE 0
 	.DW	CHUSB_CFG0		; USB SUB-DRIVER INIT ADR
 	.DB	CH0SDENABLE		; ENABLE SD CARD SUB-DRIVER
 	.DW	CHSD_CFG0		; SD CARD SUB-DRIVER INIT ADR
+;
+	.ECHO	"CH: IO="
+	.ECHO	CH0BASE
+	.ECHO	"\n"
 #ENDIF
 ;
 #IF (CHCNT >= 2)
@@ -113,6 +117,10 @@ CH_CFG1:	; DEVICE 1
 	.DW	CHUSB_CFG1		; USB SUB-DRIVER INIT ADR
 	.DB	CH1SDENABLE		; ENABLE SD CARD SUB-DRIVER
 	.DW	CHSD_CFG1		; SD CARD SUB-DRIVER INIT ADR
+;
+	.ECHO	"CH: IO="
+	.ECHO	CH1BASE
+	.ECHO	"\n"
 #ENDIF
 ;
 #IF ($ - CH_CFGTBL) != (CHCNT * CH_CFGSIZ)
@@ -451,6 +459,12 @@ CHUSB_CFG0:
 	.DB	0			; DEVICE STATUS
 	.DW	0,0			; DEVICE CAPACITY
 	.DW	0,0			; CURRENT LBA
+;
+  #IF (CH0USBENABLE)
+	.ECHO	"CHUSB: IO="
+	.ECHO	CH0BASE
+	.ECHO	"\n"
+  #ENDIF
 #ENDIF
 ;
 #IF (CHCNT >= 2)
@@ -461,6 +475,12 @@ CHUSB_CFG1:
 	.DB	0			; DEVICE STATUS
 	.DW	0,0			; DEVICE CAPACITY
 	.DW	0,0			; CURRENT LBA
+;
+  #IF (CH1USBENABLE)
+	.ECHO	"CHUSB: IO="
+	.ECHO	CH1BASE
+	.ECHO	"\n"
+  #ENDIF
 #ENDIF
 ;
 #IF ($ - CHUSB_CFGTBL) != (CHCNT * CHUSB_CFGSIZ)
@@ -1203,6 +1223,12 @@ CHSD_CFG0:
 	.DB	0			; DEVICE STATUS
 	.DW	0,0			; DEVICE CAPACITY
 	.DW	0,0			; CURRENT LBA
+;
+  #IF (CH0SDENABLE)
+	.ECHO	"CHSD: IO="
+	.ECHO	CH0BASE
+	.ECHO	"\n"
+  #ENDIF
 #ENDIF
 ;
 #IF (CHCNT >= 2)
@@ -1213,6 +1239,12 @@ CHSD_CFG1:
 	.DB	0			; DEVICE STATUS
 	.DW	0,0			; DEVICE CAPACITY
 	.DW	0,0			; CURRENT LBA
+;
+  #IF (CH1SDENABLE)
+	.ECHO	"CHSD: IO="
+	.ECHO	CH1BASE
+	.ECHO	"\n"
+  #ENDIF
 #ENDIF
 ;
 #IF ($ - CHSD_CFGTBL) != (CHCNT * CHSD_CFGSIZ)

Source/HBIOS/ctc.asm

@@ -28,6 +28,8 @@ CTC_TIM256CFG	.EQU	%00110111	; CTC TIMER/256 MODE CONFIG
 #IF (CTCTIMER & (INTMODE != 2))
 	.ECHO	"*** WARNING: CTC TIMER DISABLED -- INTMODE 2 REQUIRED!!!\n"
 #ENDIF
+	.ECHO	"CTC: IO="
+	.ECHO	CTCBASE
 ;
 #IF (CTCTIMER & (INTMODE == 2))
 ;
@@ -109,13 +111,24 @@ CTC_DIV		.EQU	CTCOSC / CTC_PRESCL / TICKFREQ
 CTC_DIVHI	.EQU	CTCPRE
 CTC_DIVLO	.EQU	(CTC_DIV / CTC_DIVHI)
 ;
-	.ECHO "CTC DIVISOR: "
+
+	.ECHO	", TIMER MODE="
+  #IF (CTCMODE == CTCMODE_CTR)
+		.ECHO	"COUNTER"
+  #ENDIF
+  #IF (CTCMODE == CTCMODE_TIM16)
+		.ECHO	"TIMER/16"
+  #ENDIF
+  #IF (CTCMODE == CTCMODE_TIM256)
+		.ECHO	"TIMER/256"
+  #ENDIF
+	.ECHO ", DIVISOR="
 	.ECHO CTC_DIV
-	.ECHO ", HI: "
+	.ECHO ", HI="
 	.ECHO CTC_DIVHI
-	.ECHO ", LO: "
+	.ECHO ", LO="
 	.ECHO CTC_DIVLO
-	.ECHO "\n"
+	.ECHO ", INTERRUPTS ENABLED"
 ;
   #IF ((CTC_DIV == 0) | (CTC_DIV > $FFFF))
 	.ECHO "COMPUTED CTC DIVISOR IS UNUSABLE!\n"
@@ -134,6 +147,8 @@ CTC_DIVLO	.EQU	(CTC_DIV / CTC_DIVHI)
 CTCTIVT		.EQU	INT_CTC0A + CTCTIMCH
 ;
 #ENDIF
+;
+	.ECHO "\n"
 ;
 ;==================================================================================================
 ; CTC PRE-INITIALIZATION

Source/HBIOS/cvdu.asm

@@ -17,6 +17,8 @@
 ;======================================================================
 ;
 CVDU_BASE	.EQU	$E0
+;
+		.ECHO	"CVDU: MODE="
 ;
 #IF (CVDUMODE == CVDUMODE_ECB)
 CVDU_KBDDATA	.EQU	CVDU_BASE + $02	; KBD CTLR DATA PORT
@@ -24,6 +26,7 @@ CVDU_KBDST	.EQU	CVDU_BASE + $0A	; KBD CTLR STATUS/CMD PORT
 CVDU_STAT	.EQU	CVDU_BASE + $04	; READ M8563 STATUS
 CVDU_REG	.EQU	CVDU_BASE + $04	; SELECT M8563 REGISTER
 CVDU_DATA	.EQU	CVDU_BASE + $0C	; READ/WRITE M8563 DATA
+		.ECHO	"ECB"
 #ENDIF
 ;
 #IF (CVDUMODE == CVDUMODE_MBC)
@@ -32,7 +35,15 @@ CVDU_KBDST	.EQU	CVDU_BASE + $03	; KBD CTLR STATUS/CMD PORT
 CVDU_STAT	.EQU	CVDU_BASE + $04	; READ M8563 STATUS
 CVDU_REG	.EQU	CVDU_BASE + $04	; SELECT M8563 REGISTER
 CVDU_DATA	.EQU	CVDU_BASE + $05	; READ/WRITE M8563 DATA
+		.ECHO	"MBC"
 #ENDIF
+;
+		.ECHO	", IO="
+		.ECHO	CVDU_BASE
+		.ECHO	", KBD MODE=PS/2"
+		.ECHO	", KBD IO="
+		.ECHO	CVDU_KBDDATA
+		.ECHO	"\n"
 ;
 CVDU_ROWS	.EQU	25
 CVDU_COLS	.EQU	80

Source/HBIOS/dma.asm

@@ -2,17 +2,31 @@
 ; Z80 DMA DRIVER
 ;==================================================================================================
 ;
+;
+	.ECHO	"DMA: MODE="
+;
 #IF ((DMAMODE == DMAMODE_ECB) | (DMAMODE == DMAMODE_MBC))
 DMA_IO		.EQU	DMABASE
 DMA_CTL		.EQU	DMABASE + 1
 DMA_USEHALF	.EQU	TRUE
+  #IF (DMAMODE == DMAMODE_ECB)
+	.ECHO	"ECB"
+  #ENDIF
+  #IF (DMAMODE == DMAMODE_MBC)
+	.ECHO	"MBC"
+  #ENDIF
 #ENDIF
 ;
 #IF (DMAMODE == DMAMODE_DUO)
 DMA_IO		.EQU	DMABASE
 DMA_CTL		.EQU	DMABASE + 3
 DMA_USEHALF	.EQU	FALSE
+	.ECHO	"DUO"
 #ENDIF
+;S
+	.ECHO	", IO="
+	.ECHO	DMA_IO
+	.ECHO	"\n"
 ;
 DMA_CONTINUOUS			.equ 	%10111101	; + Pulse
 DMA_BYTE			.equ 	%10011101	; + Pulse

Source/HBIOS/ds1501rtc.asm

@@ -111,6 +111,12 @@ DS1501RTC_TE	.EQU	%10000000
 
 DS1501RTC_BUFSIZE	.EQU	6		; 6 BYTE BUFFER (YYMMDDHHMMSS)
 
+	.ECHO	"DS1501RTC: RTCIO="
+	.ECHO	DS1501RTC_BASE
+	.ECHO	", NVMIO="
+	.ECHO	DS1501NVM_BASE
+	.ECHO	"\n"
+
 ; RTC Device Initialization Entry
 
 DS1501RTC_INIT:

Source/HBIOS/ds7rtc.asm

@@ -22,6 +22,8 @@ DS7_READ   	.EQU    (DS7_DS1307 | DS7_R)	; READ
 DS7_WRITE 	.EQU    (DS7_DS1307 | DS7_W)	; WRITE
 ;
 DS7_CTL		.EQU	(DS7_OUT | DS7_SQWE | DS7_RATE)
+;
+		.ECHO	"DS1307: ENABLED\n"
 ;
 ;-----------------------------------------------------------------------------
 ; DS1307 INITIALIZATION

Source/HBIOS/dsrtc.asm

@@ -88,6 +88,8 @@
 ; D2	--	--	--	--	--	--	--	--	--		--	--
 ; D1	----	--	--	--	--	--	--	--	--		CLKSEL	--
 ; D0	RTC_IN	RTC_IN	RTC_IN	RTC_IN	RTC_IN	RTC_IN	--	--	RTC_IN		RTC_IN	RTC_IN
+;
+	.ECHO	"DSRTC: MODE="
 ;
 #IF (DSRTCMODE == DSRTCMODE_STD)
 ;
@@ -113,6 +115,8 @@ DS1d8k		.EQU	%10100111	; 1 DOIDE 8K RESISTOR
 DS2d2k		.EQU	%10101001	; 2 DIODES 2K RESISTOR
 DS2d4k		.EQU	%10101010	; 2 DIODES 4K RESISTOR
 DS2d8k		.EQU	%10101011	; 2 DIODES 8K RESISTOR
+;
+		.ECHO	"STD"
 ;
 #ENDIF
 ;
@@ -129,8 +133,14 @@ DSRTC_MASK	.EQU	%00001111	; MASK FOR BITS WE OWN IN RTC LATCH PORT
 DSRTC_IDLE	.EQU	%00001000	; QUIESCENT STATE
 ;
 #DEFINE	DSRTC_OPRVAL	DSRTC_RTCVAL
+;
+		.ECHO	"MFPIC"
 ;
 #ENDIF
+;
+		.ECHO	", IO="
+		.ECHO	DSRTC_IO
+		.ECHO	"\n"
 ;
 DSRTC_BUFSIZ	.EQU	7		; 7 BYTE BUFFER (YYMMDDHHMMSSWW)
 ;

Source/HBIOS/duart.asm

@@ -822,6 +822,10 @@ DUART0A_CFG:
 	.DW	DUART0_ACR		; IY+6	POINTER TO SHADOW ACR FOR THIS CHIP
 	.DW	DUART0ACFG		; IY+8	LINE CONFIGURATION
 	.DB	1			; IY+10	MULTIPLIER WRT 3.6864MHZ CLOCK
+;
+	.ECHO	"DUART: IO="
+	.ECHO	DUART0BASE + $00
+	.ECHO	", CHANNEL A\n"
 ;
 DUART_CFGSIZ	.EQU	$ - DUART_CFG	; SIZE OF ONE CFG TABLE ENTRY
 ;
@@ -835,6 +839,10 @@ DUART0B_CFG:
 	.DW	DUART0_ACR		; POINTER TO SHADOW ACR FOR THIS CHIP
 	.DW	DUART0BCFG		; LINE CONFIGURATION
 	.DB	1			; MULTIPLIER WRT 3.6864MHZ CLOCK
+;
+	.ECHO	"DUART: IO="
+	.ECHO	DUART0BASE + $08
+	.ECHO	", CHANNEL B\n"
 ;
 #IF (DUARTCNT >= 2)
 ;
@@ -848,6 +856,10 @@ DUART1A_CFG:
 	.DW	DUART1_ACR		; POINTER TO SHADOW ACR FOR THIS CHIP
 	.DW	DUART1ACFG		; LINE CONFIGURATION
 	.DB	1			; MULTIPLIER WRT 3.6864MHZ CLOCK
+;
+	.ECHO	"DUART: IO="
+	.ECHO	DUART1BASE + $00
+	.ECHO	", CHANNEL A\n"
 ;
 DUART1B_CFG:
 	; 2ND DUART MODULE CHANNEL B
@@ -859,6 +871,10 @@ DUART1B_CFG:
 	.DW	DUART1_ACR		; POINTER TO SHADOW ACR FOR THIS CHIP
 	.DW	DUART1BCFG		; LINE CONFIGURATION
 	.DB	1			; MULTIPLIER WRT 3.6864MHZ CLOCK
+;
+	.ECHO	"DUART: IO="
+	.ECHO	DUART1BASE + $08
+	.ECHO	", CHANNEL B\n"
 ;
 #ENDIF
 ;

Source/HBIOS/esp.asm

@@ -53,6 +53,10 @@ ESP_CFG_IO	.EQU	1		; ESP I/O PORT
 ESP_CFG_ST	.EQU	2		; ESP STATUS PORT
 ESP_CFG_RDYMSK	.EQU	3		; ESP READY MASK
 ESP_CFG_BSYMSK	.EQU	4		; ESP BUSY MASK
+;
+	.ECHO	"ESP: IO="
+	.ECHO	ESP_IOBASE
+	.ECHO	"\n"
 ;
 ; GLOBAL ESP INITIALIZATION
 ;
@@ -343,6 +347,8 @@ ESP_STR_UPGRADE		.TEXT	"!!!UPGRADE REQUIRED!!!$"
 ;
 ESPCON_ROWS	.EQU	25		; VGA DISPLAY ROWS
 ESPCON_COLS	.EQU	80		; VGA DISPLAY COLS
+;
+	.ECHO	"ESPCON: ENABLED\n"
 ;
 ;
 ;
@@ -685,7 +691,8 @@ ESPSER0_CFG:
 	.DB	ESP_0_RDY			; ESP READY BIT MASK
 	.DB	ESP_0_BUSY			; ESP BUSY BIT MASK
 	.DW	ESPSER_LINECFG			; LINE CONFIGURATION
-
+;
+	.ECHO	"ESPSER: DEVICE=0\n"
 ;
 ESPSER1_CFG:
 	.DB	0				; DEVICE NUMBER (UPDATED DURING INIT)
@@ -694,6 +701,8 @@ ESPSER1_CFG:
 	.DB	ESP_1_RDY			; ESP READY BIT MASK
 	.DB	ESP_1_BUSY			; ESP BUSY BIT MASK
 	.DW	ESPSER_LINECFG			; LINE CONFIGURATION
+;
+	.ECHO	"ESPSER: DEVICE=1\n"
 ;
 ;
 ;

Source/HBIOS/fd.asm

@@ -14,6 +14,7 @@ FDC_DATA	.EQU	$37		; 8272 DATA PORT
 FDC_DIR		.EQU	$38		; DATA INPUT REGISTER
 FDC_DOR		.EQU	$3A		; DIGITAL OUTPUT REGISTER (LATCH)
 FDC_DMA		.EQU	$3C		; PSEUDO DMA DATA PORT
+  #DEFINE FDMODE_STR "DIO"
 #ENDIF
 #IF (FDMODE = FDMODE_ZETA2)
 FDC_MSR		.EQU	$30		; 8272 MAIN STATUS REGISTER
@@ -21,6 +22,7 @@ FDC_DATA	.EQU	$31		; 8272 DATA PORT
 FDC_DOR		.EQU	$38		; DIGITAL OUTPUT REGISTER
 FDC_DCR		.EQU	$28		; CONFIGURATION CONTROL REGISTER
 FDC_TC		.EQU	$38		; TERMINAL COUNT (W/ DACK)
+  #DEFINE FDMODE_STR "ZETA2"
 #ENDIF
 #IF (FDMODE == FDMODE_DIDE)
 FDC_BID		.EQU	$20		; IO RANGE 20H-3FH
@@ -31,6 +33,7 @@ FDC_DCR		.EQU	$2D		; DCR
 FDC_DACK	.EQU	$3C		; DACK
 FDC_TC		.EQU	$3D		; TERMINAL COUNT (W/ DACK)
 FDC_DMA		.EQU	$3C		; NOT USED BY DIDE
+  #DEFINE FDMODE_STR "DIDE"
 #ENDIF
 #IF (FDMODE == FDMODE_N8)
 FDC_MSR		.EQU	$8C		; 8272 MAIN STATUS REGISTER
@@ -40,11 +43,13 @@ FDC_DCR		.EQU	$91		; DCR
 FDC_DACK	.EQU	$90		; DACK
 FDC_TC		.EQU	$93		; TERMINAL COUNT (W/ DACK)
 FDC_DMA		.EQU	$3C		; NOT USED BY N8
+  #DEFINE FDMODE_STR "N8"
 #ENDIF
 #IF (FDMODE == FDMODE_RCSMC)
 FDC_MSR		.EQU	$50		; 8272 MAIN STATUS REGISTER
 FDC_DATA	.EQU	$51		; 8272 DATA PORT
 FDC_DOR		.EQU	$58		; DIGITAL OUTPUT REGISTER (LATCH)
+  #DEFINE FDMODE_STR "RCSMC"
 #ENDIF
 #IF (FDMODE == FDMODE_RCWDC)
 FDC_MSR		.EQU	$50		; 8272 MAIN STATUS REGISTER
@@ -52,6 +57,7 @@ FDC_DATA	.EQU	$51		; 8272 DATA PORT
 FDC_DOR		.EQU	$58		; DIGITAL OUTPUT REGISTER
 FDC_DCR		.EQU	$48		; CONFIGURATION CONTROL REGISTER
 FDC_TC		.EQU	$58		; TERMINAL COUNT (W/ DACK)
+  #DEFINE FDMODE_STR "RCWDC"
 #ENDIF
 #IF (FDMODE == FDMODE_DYNO)
 FDC_BASE        .EQU    $84
@@ -60,6 +66,7 @@ FDC_DATA	.EQU	FDC_BASE + $01	; 8272 DATA PORT
 FDC_DOR		.EQU	FDC_BASE + $02	; DIGITAL OUTPUT REGISTER
 FDC_DCR		.EQU	FDC_BASE + $03	; CONFIGURATION CONTROL REGISTER
 FDC_TC		.EQU	FDC_BASE + $02	; TERMINAL COUNT (W/ DACK)
+  #DEFINE FDMODE_STR "DYNO"
 #ENDIF
 #IF (FDMODE == FDMODE_EPFDC)
 FDC_MSR		.EQU	$48		; 8272 MAIN STATUS REGISTER
@@ -67,6 +74,7 @@ FDC_DATA	.EQU	$49		; 8272 DATA PORT
 FDC_DOR		.EQU	$4A		; DIGITAL OUTPUT REGISTER
 FDC_DCR		.EQU	$4B		; CONFIGURATION CONTROL REGISTER
 FDC_TC		.EQU	$4C		; TERMINAL COUNT (W/ DACK)
+  #DEFINE FDMODE_STR "EPFDC"
 #ENDIF
 #IF (FDMODE == FDMODE_MBC)
 FDC_MSR		.EQU	$30		; 8272 MAIN STATUS REGISTER
@@ -74,8 +82,10 @@ FDC_DATA	.EQU	$31		; 8272 DATA PORT
 FDC_DOR		.EQU	$36		; DIGITAL OUTPUT REGISTER
 FDC_DCR		.EQU	$35		; CONFIGURATION CONTROL REGISTER
 FDC_TC		.EQU	$37		; TERMINAL COUNT (W/ DACK)
+  #DEFINE FDMODE_STR "MBC"
 #ENDIF
 ;
+;
 ; DISK OPERATIONS
 ;
 DOP_READ	.EQU	0		; READ OPERATION
@@ -133,6 +143,33 @@ FD_CFGTBL:
 	.DB	0			; HOST SECTOR
 	.DB	0			; HOST HEAD
 	.DB	FD0TYPE			; DRIVE TYPE
+;
+	.ECHO	"FD: MODE="
+	.ECHO	FDMODE_STR
+	.ECHO	", IO="
+	.ECHO	FDC_MSR
+	.ECHO	", DRIVE 0"
+	.ECHO	", TYPE="
+  #IF (FD0TYPE == FDT_NONE
+	.ECHO	"NONE"
+  #ENDIF
+  #IF (FD0TYPE == FDT_3DD
+	.ECHO	"3.5\" DD"
+  #ENDIF
+  #IF (FD0TYPE == FDT_3HD
+	.ECHO	"3.5\" HD"
+  #ENDIF
+  #IF (FD0TYPE == FDT_5DD
+	.ECHO	"5.25\" DD"
+  #ENDIF
+  #IF (FD0TYPE == FDT_5HD
+	.ECHO	"5.25\" HD"
+  #ENDIF
+  #IF (FD0TYPE == FDT_8
+	.ECHO	"8\" DD"
+  #ENDIF
+	.ECHO	"\n"
+;
 #IF (FD_DEVCNT >= 2)
 	; DEVICE 1, PRIMARY SLAVE
 	.DB	1			; DRIVER DEVICE NUMBER
@@ -143,6 +180,32 @@ FD_CFGTBL:
 	.DB	0			; HOST SECTOR
 	.DB	0			; HOST HEAD
 	.DB	FD1TYPE			; DRIVE TYPE
+;
+	.ECHO	"FD: MODE="
+	.ECHO	FDMODE_STR
+	.ECHO	", IO="
+	.ECHO	FDC_MSR
+	.ECHO	", DRIVE 1"
+	.ECHO	", TYPE="
+  #IF (FD1TYPE == FDT_NONE
+	.ECHO	"NONE"
+  #ENDIF
+  #IF (FD1TYPE == FDT_3DD
+	.ECHO	"3.5\" DD"
+  #ENDIF
+  #IF (FD1TYPE == FDT_3HD
+	.ECHO	"3.5\" HD"
+  #ENDIF
+  #IF (FD1TYPE == FDT_5DD
+	.ECHO	"5.25\" DD"
+  #ENDIF
+  #IF (FD1TYPE == FDT_5HD
+	.ECHO	"5.25\" HD"
+  #ENDIF
+  #IF (FD1TYPE == FDT_8
+	.ECHO	"8\" DD"
+  #ENDIF
+	.ECHO	"\n"
 #ENDIF
 ;
 #IF ($ - FD_CFGTBL) != (FD_DEVCNT * FD_CFGSIZ)

Source/HBIOS/gdc.asm

@@ -36,16 +36,33 @@ GDC_COLS	.EQU	80
 ; *** TODO: CGA AND EGA ARE PLACEHOLDERS.  THESE EQUATES SHOULD
 ; BE USED TO ALLOW FOR MULTIPLE MONITOR TIMINGS AND/OR FONT
 ; DEFINITIONS.
+;
+	.ECHO	"GDC: MODE="
+;
+#IF (GDCMODE == GDCMODE_ECB)
+	.ECHO	"ECB"
+#ENDIF
+#IF (GDCMODE == GDCMODE_RPH)
+	.ECHO	"RPH"
+#ENDIF
+;
+	.ECHO	", DISPLAY="
 ;
 #IF (GDCMON == GDCMON_CGA)
   #DEFINE	USEFONTCGA
   #DEFINE	GDC_FONT FONTCGA
+	.ECHO	"CGA"
 #ENDIF
 ;
 #IF (GDCMON == GDCMON_EGA)
   #DEFINE	USEFONT8X16
   #DEFINE	GDC_FONT FONT8X16
+	.ECHO	"EGA"
 #ENDIF
+;
+	.ECHO	", IO="
+	.ECHO	GDC_BASE
+	.ECHO	"\n"
 ;
 TERMENABLE	.SET	TRUE		; INCLUDE TERMINAL PSEUDODEVICE DRIVER
 ;
@@ -70,7 +87,7 @@ GDC_INIT:
 #ENDIF	
 #IF (GDCMON == GDCMON_EGA)
 	PRTS(" EGA$")
-#ENDIF	
+#ENDIF
 ;
 	PRTS(" IO=0x$")
 	LD	A,GDC_BASE

Source/HBIOS/hbios.asm

@@ -217,6 +217,24 @@ RTCDEF		.SET	RTCDEF | %00001000	; INITIAL SPEED LOW
 ;
 ;
 ;
+#IF (FPLED_ENABLE | FPSW_ENABLE)
+	.ECHO	"FP: "
+  #IF (FPLED_ENABLE)
+	.ECHO	"LEDIO="
+	.ECHO	FPLED_IO
+  #ENDIF
+  #IF (FPLED_ENABLE & FPSW_ENABLE)
+	.ECHO	", "
+  #ENDIF
+  #IF (FPSW_ENABLE)
+	.ECHO	"SWIO="
+	.ECHO	FPSW_IO
+  #ENDIF
+	.ECHO	"\n"
+#ENDIF
+;
+;
+;
 #IFNDEF	APPBOOT
 ;
 	.ORG	0

Source/HBIOS/hdsk.asm

@@ -21,6 +21,12 @@ HDSK_CFGSIZ	.EQU	6		; SIZE OF CFG TBL ENTRIES
 HDSK_DEV	.EQU	0		; OFFSET OF DEVICE NUMBER (BYTE)
 HDSK_STAT	.EQU	1		; OFFSET OF STATUS (BYTE)
 HDSK_LBA	.EQU	2		; OFFSET OF LBA (DWORD)
+;
+	.ECHO	"HDSK: IO="
+	.ECHO	HDSK_IO
+	.ECHO	", DEVICE COUNT="
+	.ECHO	HDSK_DEVCNT
+	.ECHO	"\n"
 ;
 HDSK_CFGTBL:
 	; DEVICE 0

Source/HBIOS/ide.asm

@@ -213,6 +213,27 @@ IDE_DEV0M:	; DEVICE 0, MASTER
 	.DB	IDE0DATLO		; IO BASE ADDRESS
 	.DB	IDE0DATHI		; IO BASE ADDRESS
 	.DW	IDE_DEV0S		; PARTNER
+;
+	.ECHO	"IDE: MODE="
+  #IF (IDE0MODE == IDEMODE_NONE)
+	.ECHO	"NONE"
+  #ENDIF
+  #IF (IDE0MODE == IDEMODE_DIO)
+	.ECHO	"DIO"
+  #ENDIF
+  #IF (IDE0MODE == IDEMODE_DIDE)
+	.ECHO	"DIDE"
+  #ENDIF
+  #IF (IDE0MODE == IDEMODE_MK4)
+	.ECHO	"MK4"
+  #ENDIF
+  #IF (IDE0MODE == IDEMODE_RC)
+	.ECHO	"RC"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	IDE0BASE
+	.ECHO	", MASTER"
+	.ECHO	"\n"
 ;
 IDE_DEV0S:	; DEVICE 0, SLAVE
 	.DB	$FE			; DRIVER DEVICE NUMBER (FILLED DYNAMICALLY)
@@ -227,6 +248,27 @@ IDE_DEV0S:	; DEVICE 0, SLAVE
 	.DB	IDE0DATLO		; IO BASE ADDRESS
 	.DB	IDE0DATHI		; IO BASE ADDRESS
 	.DW	IDE_DEV0M		; PARTNER
+;
+	.ECHO	"IDE: MODE="
+  #IF (IDE0MODE == IDEMODE_NONE)
+	.ECHO	"NONE"
+  #ENDIF
+  #IF (IDE0MODE == IDEMODE_DIO)
+	.ECHO	"DIO"
+  #ENDIF
+  #IF (IDE0MODE == IDEMODE_DIDE)
+	.ECHO	"DIDE"
+  #ENDIF
+  #IF (IDE0MODE == IDEMODE_MK4)
+	.ECHO	"MK4"
+  #ENDIF
+  #IF (IDE0MODE == IDEMODE_RC)
+	.ECHO	"RC"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	IDE0BASE
+	.ECHO	", SLAVE"
+	.ECHO	"\n"
 #ENDIF
 ;
 #IF (IDECNT >= 2)
@@ -244,6 +286,27 @@ IDE_DEV1M:	; DEVICE 1, MASTER
 	.DB	IDE1DATLO		; IO BASE ADDRESS
 	.DB	IDE1DATHI		; IO BASE ADDRESS
 	.DW	IDE_DEV1S		; PARTNER
+;
+	.ECHO	"IDE: MODE="
+  #IF (IDE1MODE == IDEMODE_NONE)
+	.ECHO	"NONE"
+  #ENDIF
+  #IF (IDE1MODE == IDEMODE_DIO)
+	.ECHO	"DIO"
+  #ENDIF
+  #IF (IDE1MODE == IDEMODE_DIDE)
+	.ECHO	"DIDE"
+  #ENDIF
+  #IF (IDE1MODE == IDEMODE_MK4)
+	.ECHO	"MK4"
+  #ENDIF
+  #IF (IDE1MODE == IDEMODE_RC)
+	.ECHO	"RC"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	IDE1BASE
+	.ECHO	", MASTER"
+	.ECHO	"\n"
 ;
 IDE_DEV1S:	; DEVICE 1, SLAVE
 	.DB	$FE			; DRIVER DEVICE NUMBER (FILLED DYNAMICALLY)
@@ -258,6 +321,27 @@ IDE_DEV1S:	; DEVICE 1, SLAVE
 	.DB	IDE1DATLO		; IO BASE ADDRESS
 	.DB	IDE1DATHI		; IO BASE ADDRESS
 	.DW	IDE_DEV1M		; PARTNER
+;
+	.ECHO	"IDE: MODE="
+  #IF (IDE1MODE == IDEMODE_NONE)
+	.ECHO	"NONE"
+  #ENDIF
+  #IF (IDE1MODE == IDEMODE_DIO)
+	.ECHO	"DIO"
+  #ENDIF
+  #IF (IDE1MODE == IDEMODE_DIDE)
+	.ECHO	"DIDE"
+  #ENDIF
+  #IF (IDE1MODE == IDEMODE_MK4)
+	.ECHO	"MK4"
+  #ENDIF
+  #IF (IDE1MODE == IDEMODE_RC)
+	.ECHO	"RC"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	IDE1BASE
+	.ECHO	", SLAVE"
+	.ECHO	"\n"
 #ENDIF
 ;
 #IF (IDECNT >= 3)
@@ -275,6 +359,27 @@ IDE_DEV2M:	; DEVICE 2, MASTER
 	.DB	IDE2DATLO		; IO BASE ADDRESS
 	.DB	IDE2DATHI		; IO BASE ADDRESS
 	.DW	IDE_DEV2S		; PARTNER
+;
+	.ECHO	"IDE: MODE="
+  #IF (IDE2MODE == IDEMODE_NONE)
+	.ECHO	"NONE"
+  #ENDIF
+  #IF (IDE2MODE == IDEMODE_DIO)
+	.ECHO	"DIO"
+  #ENDIF
+  #IF (IDE2MODE == IDEMODE_DIDE)
+	.ECHO	"DIDE"
+  #ENDIF
+  #IF (IDE2MODE == IDEMODE_MK4)
+	.ECHO	"MK4"
+  #ENDIF
+  #IF (IDE2MODE == IDEMODE_RC)
+	.ECHO	"RC"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	IDE2BASE
+	.ECHO	", MASTER"
+	.ECHO	"\n"
 ;
 IDE_DEV2S:	; DEVICE 2, SLAVE
 	.DB	$FE			; DRIVER DEVICE NUMBER (FILLED DYNAMICALLY)
@@ -289,6 +394,27 @@ IDE_DEV2S:	; DEVICE 2, SLAVE
 	.DB	IDE2DATLO		; IO BASE ADDRESS
 	.DB	IDE2DATHI		; IO BASE ADDRESS
 	.DW	IDE_DEV1M		; PARTNER
+;
+	.ECHO	"IDE: MODE="
+  #IF (IDE2MODE == IDEMODE_NONE)
+	.ECHO	"NONE"
+  #ENDIF
+  #IF (IDE2MODE == IDEMODE_DIO)
+	.ECHO	"DIO"
+  #ENDIF
+  #IF (IDE2MODE == IDEMODE_DIDE)
+	.ECHO	"DIDE"
+  #ENDIF
+  #IF (IDE2MODE == IDEMODE_MK4)
+	.ECHO	"MK4"
+  #ENDIF
+  #IF (IDE2MODE == IDEMODE_RC)
+	.ECHO	"RC"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	IDE2BASE
+	.ECHO	", SLAVE"
+	.ECHO	"\n"
 #ENDIF
 ;
 #IF ($ - IDE_CFGTBL) != (IDE_DEVCNT * IDE_CFGSIZ)

Source/HBIOS/imm.asm

@@ -1525,6 +1525,17 @@ IMM0_CFG:	; DEVICE 0
 	.DB	IMM0BASE		; IO BASE ADDRESS
 	.DW	0,0			; DEVICE CAPACITY
 	.DW	0,0			; CURRENT LBA
+;
+	.ECHO	"IMM: MODE="
+  #IF (IMMMODE == IMMMODE_SPP)
+	.ECHO	"SPP"
+  #ENDIF
+  #IF (IMMMODE == IMMMODE_MG014)
+	.ECHO	"MG014"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	IMM0BASE
+	.ECHO	"\n"
 #ENDIF
 ;
 #IF (IMMCNT >= 2)
@@ -1536,6 +1547,17 @@ IMM1_CFG:	; DEVICE 1
 	.DB	IMM1BASE		; IO BASE ADDRESS
 	.DW	0,0			; DEVICE CAPACITY
 	.DW	0,0			; CURRENT LBA
+;
+	.ECHO	"IMM: MODE="
+  #IF (IMMMODE == IMMMODE_SPP)
+	.ECHO	"SPP"
+  #ENDIF
+  #IF (IMMMODE == IMMMODE_MG014)
+	.ECHO	"MG014"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	IMM1BASE
+	.ECHO	"\n"
 #ENDIF
 ;
 #IF ($ - IMM_CFG) != (IMMCNT * IMM_CFGSIZ)

Source/HBIOS/intrtc.asm

@@ -4,6 +4,8 @@
 ;==================================================================================================
 ;
 INTRTC_BUFSIZ	.EQU	6	; SIX BYTE BUFFER (YYMMDDHHMMSS)
+;
+		.ECHO	"INTRTC: ENABLED\n"
 ;
 ; RTC DEVICE INITIALIZATION ENTRY
 ;

Source/HBIOS/kbd.asm

@@ -55,6 +55,8 @@ KBD_RSTATE	.DB	0	; STATE BITS FOR "RIGHT" KEYS
 KBD_STATUS	.DB	0	; CURRENT STATUS BITS (SEE ABOVE)
 KBD_REPEAT	.DB	0	; CURRENT REPEAT RATE
 KBD_IDLE	.DB	0	; IDLE COUNT
+;
+	.ECHO	"KBD: ENABLED\n"
 ;
 ;__________________________________________________________________________________________________
 ; KEYBOARD INITIALIZATION

Source/HBIOS/lpt.asm

@@ -346,10 +346,10 @@ LPT_DETECT:
 	LD	A,$A5			; TEST VALUE
 	OUT	(C),A			; PUSH VALUE TO PORT
 	IN	A,(C)			; GET PORT VALUE
-#IF (LPTTRACE >= 3)
+  #IF (LPTTRACE >= 3)
 	CALL	PC_SPACE
 	CALL	PRTHEXBYTE
-#ENDIF
+  #ENDIF
 	CP	$A5			; CHECK FOR TEST VALUE
 	JR	Z,LPT_DETECT1		; FOUND IT
 	LD	A,LPTMODE_NONE		; NOT FOUND
@@ -420,6 +420,17 @@ LPT0_CFG:
 	.DB	0			; MODULE ID
 	.DB	LPT0BASE		; BASE PORT
 	.DW	0			; LINE CONFIGURATION
+;
+	.ECHO	"LPT: MODE="
+  #IF (LPTMODE == LPTMODE_SPP)
+	.ECHO	"SPP"
+  #ENDIF
+  #IF (LPTMODE == LPTMODE_MG014)
+	.ECHO	"MG014"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	LPT0BASE
+	.ECHO	"\n"
 ;
 LPT_CFGSIZ	.EQU	$ - LPT_CFG	; SIZE OF ONE CFG TABLE ENTRY
 ;
@@ -432,6 +443,17 @@ LPT1_CFG:
 	.DB	1			; MODULE ID
 	.DB	LPT1BASE		; BASE PORT
 	.DW	0			; LINE CONFIGURATION
+;
+	.ECHO	"LPT: MODE="
+  #IF (LPTMODE == LPTMODE_SPP)
+	.ECHO	"SPP"
+  #ENDIF
+  #IF (LPTMODE == LPTMODE_MG014)
+	.ECHO	"MG014"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	LPT1BASE
+	.ECHO	"\n"
 ;
 #ENDIF
 ;

Source/HBIOS/md.asm

@@ -39,6 +39,8 @@ MD_CFGTBL:
 	.DW	0,0			; CURRENT LBA
 	.DB	MID_MDRAM		; DEVICE MEDIA ID
 	.DB	MD_ARAM			; DEVICE ATTRIBUTE
+;
+	.ECHO	"MD: TYPE=RAM\n"
 #ENDIF
 ;
 #IF (MDROM)
@@ -48,6 +50,8 @@ MD_CFGTBL:
 	.DW	0,0			; CURRENT LBA
 	.DB	MID_MDROM		; DEVICE MEDIA ID
 	.DB	MD_AROM			; DEVICE ATTRIBUTE
+;
+	.ECHO	"MD: TYPE=ROM\n"
 #ENDIF
 ;
 MD_DEVCNT	.EQU	($ - MD_CFGTBL) / MD_CFGSIZ

Source/HBIOS/pcf.asm

@@ -93,6 +93,10 @@ PCF_PINTO	.EQU	65000
 PCF_ACKTO	.EQU	65000
 PCF_BBTO	.EQU	65000
 PCF_LABDLY	.EQU	65000
+;
+	.ECHO	"PCF: IO="
+	.ECHO	PCF_BASE
+	.ECHO	"\n"
 ;
 ; DATA PORT REGISTERS
 ;

Source/HBIOS/pio.asm

@@ -307,6 +307,10 @@ PIO0A_CFG:
 	.DB	PIO0A_DAT		; DATA PORT
 	.DW	DEFSERCFG		; LINE CONFIGURATION
 	.DW	PIO0A_RCVBUF		; POINTER TO RCV BUFFER STRUCT
+;
+	.ECHO	"PIO: IO="
+	.ECHO	PIO0BASE
+	.ECHO	", CHANNEL A\n"
 ;
 PIO_CFGSIZ	.EQU	$ - PIO_CFG	; SIZE OF ONE CFG TABLE ENTRY
 ;
@@ -319,6 +323,10 @@ PIO0B_CFG:
 	.DB	PIO0B_DAT		; DATA PORT
 	.DW	DEFSERCFG		; LINE CONFIGURATION
 	.DW	PIO0B_RCVBUF		; POINTER TO RCV BUFFER STRUCT
+;
+	.ECHO	"PIO: IO="
+	.ECHO	PIO0BASE
+	.ECHO	", CHANNEL B\n"
 ;
 #IF (PIOCNT >= 2)
 ;
@@ -331,6 +339,10 @@ PIO1A_CFG:
 	.DB	PIO1A_DAT		; DATA PORT
 	.DW	DEFSERCFG		; LINE CONFIGURATION
 	.DW	PIO1A_RCVBUF		; POINTER TO RCV BUFFER STRUCT
+;
+	.ECHO	"PIO: IO="
+	.ECHO	PIO1BASE
+	.ECHO	", CHANNEL A\n"
 ;
 	; PIO1 CHANNEL B
 PIO1B_CFG:
@@ -341,6 +353,10 @@ PIO1B_CFG:
 	.DB	PIO1B_DAT		; DATA PORT
 	.DW	DEFSERCFG		; LINE CONFIGURATION
 	.DW	PIO1B_RCVBUF		; POINTER TO RCV BUFFER STRUCT
+;
+	.ECHO	"PIO: IO="
+	.ECHO	PIO1BASE
+	.ECHO	", CHANNEL B\n"
 ;
 #ENDIF
 ;

Source/HBIOS/pkd.asm

@@ -65,6 +65,10 @@ PKD_CMD_CLK	.EQU	%00100000		; SET CLK PRESCALE
 PKD_CMD_FIFO	.EQU	%01000000		; READ FIFO
 ;
 PKD_PRESCL	.EQU	PKDOSC/100000		; PRESCALER
+;
+	.ECHO	"PKD: IO="
+	.ECHO	PKDPPIBASE
+	.ECHO	"\n"
 ;
 ;__PKD_PREINIT_______________________________________________________________________________________
 ;

Source/HBIOS/ppa.asm

@@ -139,7 +139,7 @@ PPA_LBA		.EQU	8		; OFFSET OF LBA (DWORD)
 ;
 ; INCLUDE MG014 NIBBLE MAP FOR MG014 MODE
 ;
-#IF (IMMMODE == IMMMODE_MG014)
+#IF (PPAMODE == IMMMODE_MG014)
   #DEFINE MG014_MAP
 #ENDIF
 ;
@@ -1385,6 +1385,17 @@ PPA0_CFG:	; DEVICE 0
 	.DB	PPA0BASE		; IO BASE ADDRESS
 	.DW	0,0			; DEVICE CAPACITY
 	.DW	0,0			; CURRENT LBA
+;
+	.ECHO	"PPA: MODE="
+  #IF (PPAMODE == PPAMODE_SPP)
+	.ECHO	"SPP"
+  #ENDIF
+  #IF (PPAMODE == PPAMODE_MG014)
+	.ECHO	"MG014"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	PPA0BASE
+	.ECHO	"\n"
 #ENDIF
 ;
 #IF (PPACNT >= 2)
@@ -1396,6 +1407,17 @@ PPA1_CFG:	; DEVICE 1
 	.DB	PPA1BASE		; IO BASE ADDRESS
 	.DW	0,0			; DEVICE CAPACITY
 	.DW	0,0			; CURRENT LBA
+;
+	.ECHO	"PPA: MODE="
+  #IF (PPAMODE == PPAMODE_SPP)
+	.ECHO	"SPP"
+  #ENDIF
+  #IF (PPAMODE == PPAMODE_MG014)
+	.ECHO	"MG014"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	PPA1BASE
+	.ECHO	"\n"
 #ENDIF
 ;
 #IF ($ - PPA_CFG) != (PPACNT * PPA_CFGSIZ)

Source/HBIOS/ppide.asm

@@ -229,6 +229,11 @@ PPIDE_DEV0M:	; DEVICE 0, MASTER
 	.DB	PPIDE0BASE+2		; CTL
 	.DB	PPIDE0BASE+3		; PPI
 	.DW	PPIDE_DEV0S		; PARTNER
+;
+	.ECHO	"PPIDE: IO="
+	.ECHO	PPIDE0BASE
+	.ECHO	", MASTER"
+	.ECHO	"\n"
 ;
 PPIDE_DEV0S:	; DEVICE 0, SLAVE
 	.DB	$FE			; DRIVER DEVICE NUMBER (FILLED DYNAMICALLY)
@@ -242,6 +247,11 @@ PPIDE_DEV0S:	; DEVICE 0, SLAVE
 	.DB	PPIDE0BASE+2		; CTL
 	.DB	PPIDE0BASE+3		; PPI
 	.DW	PPIDE_DEV0M		; PARTNER
+;
+	.ECHO	"PPIDE: IO="
+	.ECHO	PPIDE0BASE
+	.ECHO	", SLAVE"
+	.ECHO	"\n"
 ;
 #ENDIF
 ;
@@ -259,6 +269,11 @@ PPIDE_DEV1M:	; DEVICE 1, MASTER
 	.DB	PPIDE1BASE+2		; CTL
 	.DB	PPIDE1BASE+3		; PPI
 	.DW	PPIDE_DEV1S		; PARTNER
+;
+	.ECHO	"PPIDE: IO="
+	.ECHO	PPIDE1BASE
+	.ECHO	", MASTER"
+	.ECHO	"\n"
 ;
 PPIDE_DEV1S:	; DEVICE 1, SLAVE
 	.DB	$FE			; DRIVER DEVICE NUMBER (FILLED DYNAMICALLY)
@@ -272,6 +287,11 @@ PPIDE_DEV1S:	; DEVICE 1, SLAVE
 	.DB	PPIDE1BASE+2		; CTL
 	.DB	PPIDE1BASE+3		; PPI
 	.DW	PPIDE_DEV1M		; PARTNER
+;
+	.ECHO	"PPIDE: IO="
+	.ECHO	PPIDE1BASE
+	.ECHO	", SLAVE"
+	.ECHO	"\n"
 ;
 #ENDIF
 ;
@@ -289,6 +309,11 @@ PPIDE_DEV2M:	; DEVICE 2, MASTER
 	.DB	PPIDE2BASE+2		; CTL
 	.DB	PPIDE2BASE+3		; PPI
 	.DW	PPIDE_DEV2S		; PARTNER
+;
+	.ECHO	"PPIDE: IO="
+	.ECHO	PPIDE2BASE
+	.ECHO	", MASTER"
+	.ECHO	"\n"
 ;
 PPIDE_DEV2S:	; DEVICE 2, SLAVE
 	.DB	$FE			; DRIVER DEVICE NUMBER (FILLED DYNAMICALLY)
@@ -302,6 +327,11 @@ PPIDE_DEV2S:	; DEVICE 2, SLAVE
 	.DB	PPIDE2BASE+2		; CTL
 	.DB	PPIDE2BASE+3		; PPI
 	.DW	PPIDE_DEV2M		; PARTNER
+;
+	.ECHO	"PPIDE: IO="
+	.ECHO	PPIDE2BASE
+	.ECHO	", SLAVE"
+	.ECHO	"\n"
 ;
 #ENDIF
 ;

Source/HBIOS/ppk.asm

@@ -59,6 +59,8 @@ PPK_STATUS	.DB	0	; CURRENT STATUS BITS (SEE ABOVE)
 PPK_REPEAT	.DB	0	; CURRENT REPEAT RATE
 PPK_IDLE	.DB	0	; IDLE COUNT
 PPK_WAITTO	.DW	0	; TIMEOUT WAIT LOOP COUNT (COMPUTED IN INIT)
+;
+	.ECHO	"PPK: ENABLED\n"
 ;
 ;__________________________________________________________________________________________________
 ; KEYBOARD INITIALIZATION

Source/HBIOS/ppp.asm

@@ -8,6 +8,10 @@
 PPP_IO		.EQU	PPPBASE + 0	; PPP DATA I/O (PPI PORT A)
 PPP_CTL		.EQU	PPPBASE + 2	; PPP CTL LINES (PPI PORT C)
 PPP_PPICTL	.EQU	PPPBASE + 3	; PPI CONTROL PORT
+;
+		.ECHO	"PPP: IO="
+		.ECHO	PPP_IO
+		.ECHO	"\n"
 ;
 ; COMMAND BYTES
 ;
@@ -248,6 +252,8 @@ PPP_FWVER		.DB	$00, $00, $00, $00	; MMNNBBB (M=MAJOR, N=MINOR, B=BUILD)
 ;
 PPPCON_ROWS	.EQU	37		; PROPELLER VGA DISPLAY ROWS (40 - 3 STATUS LINES)
 PPPCON_COLS	.EQU	80		; PROPELLER VGA DISPLAY COLS
+;
+		.ECHO	"PPPCON: ENABLED\n"
 ;
 PPPCON_INIT:
 	CALL	NEWLINE
@@ -413,6 +419,8 @@ PPPSD_CFGTBL:
 #ENDIF
 ;
 	.DB	$FF			; END MARKER
+;
+		.ECHO	"PPPSD: ENABLED\n"
 ;
 ; SD CARD INITIALIZATION
 ;

Source/HBIOS/prp.asm

@@ -6,6 +6,10 @@
 ; TODO:
 ;
 PRP_IOBASE	.EQU	$A8
+;
+		.ECHO	"PRP: IO="
+		.ECHO	PRP_IOBASE
+		.ECHO	"\n"
 ;
 ; GLOBAL PROPIO INITIALIZATION
 ;
@@ -119,6 +123,8 @@ PRPCON_DSPRDY	.EQU	$10		; BIT SET WHEN DISPLAY BUF IS READY FOR A BYTE (BUF EMPT
 ;
 PRPCON_ROWS	.EQU	37		; PROPELLER VGA DISPLAY ROWS (40 - 3 STATUS LINES)
 PRPCON_COLS	.EQU	80		; PROPELLER VGA DISPLAY COLS
+;
+		.ECHO	"PRPCON: ENABLED\n"
 ;
 ;
 ;
@@ -310,6 +316,8 @@ PRPSD_CFGTBL:
 #ENDIF
 ;
 	.DB	$FF			; END MARKER
+;
+	.ECHO	"PRPSD: ENABLED\n"
 ;
 ; SD CARD INITIALIZATION
 ;

Source/HBIOS/rf.asm

@@ -42,6 +42,11 @@ RF_CFGTBL:
 	.DW	0,0			; CURRENT LBA
 	.DB	0			; UNUSED
 	.DB	RF_U0IO			; DEVICE BASE ADDR
+;
+	.ECHO	"RF: IO="
+	.ECHO	RF_U0IO
+	.ECHO	"\n"
+;
 #IF (RF_DEVCNT > 1)
 	; DEVICE 1
 	.DB	1			; DEVICE NUMBER
@@ -50,6 +55,11 @@ RF_CFGTBL:
 	.DB	0			; UNUSED
 	.DB	RF_U1IO			; DEVICE BASE ADDR
 #ENDIF
+;
+	.ECHO	"RF: IO="
+	.ECHO	RF_U1IO
+	.ECHO	"\n"
+;
 #IF (RF_DEVCNT > 2)
 	; DEVICE 2
 	.DB	2			; DRIVER DEVICE NUMBER
@@ -58,13 +68,23 @@ RF_CFGTBL:
 	.DB	0			; UNUSED
 	.DB	RF_U2IO			; DEVICE BASE ADDR
 #ENDIF
-;	; DEVICE 3
+;
+	.ECHO	"RF: IO="
+	.ECHO	RF_U2IO
+	.ECHO	"\n"
+;
 #IF (RF_DEVCNT > 3)
+	; DEVICE 3
 	.DB	3			; DEVICE NUMBER
 	.DB	0			; DEVICE STATUS
 	.DW	0,0			; CURRENT LBA
 	.DB	0			; UNUSED
 	.DB	RF_U3IO			; DEVICE BASE ADDR
+;
+	.ECHO	"RF: IO="
+	.ECHO	RF_U3IO
+	.ECHO	"\n"
+;
 #ENDIF
 ;
 #IF ($ - RF_CFGTBL) != (RF_DEVCNT * RF_CFGSIZ)

Source/HBIOS/rp5rtc.asm

@@ -55,6 +55,10 @@ MODE_RAM1	.EQU	3
 MD_TIME		.EQU	8
 MD_ALRM		.EQU	4
 
+		.ECHO	"RP5C01: IO="
+		.ECHO	RP5RTC_REG
+		.ECHO	"\n"
+
 RP5RTC_INIT:
 	LD	A, (RTC_DISPACT)	; RTC DISPATCHER ALREADY SET?
 	OR	A			; SET FLAGS

Source/HBIOS/scon.asm

@@ -15,6 +15,10 @@ SCON_DSPRDY	.EQU	%00000100
 ;
 SCON_COLS	.EQU	80
 SCON_ROWS	.EQU	40
+;
+		.ECHO	"SCON: IO="
+		.ECHO	SCON_IOBASE
+		.ECHO	"\n"
 ;
 ;
 ;

Source/HBIOS/sd.asm

@@ -116,6 +116,8 @@
 SD_NOPULLUP	.EQU	TRUE		; ASSUME NO PULLUP
 ;
 SD_DEVCNT	.EQU	SDCNT		; SET SD_DEVCNT TO SDCNT CONFIG VAR
+;
+		.ECHO	"SD: MODE="
 ;
 #IF (SDMODE == SDMODE_JUHA)		; JUHA MINI-BOARD
 SD_DEVMAX	.EQU	1		; NUMBER OF PHYSICAL UNITS (SOCKETS)
@@ -129,6 +131,7 @@ SD_DI		.EQU	%00000001	; RTC:0 IS DATA IN (CARD <- CPU)
 SD_DO		.EQU	%10000000	; RTC:7 IS DATA OUT (CARD -> CPU)
 SD_IOBASE	.EQU	SD_OPRREG	; IOBASE
 SD_INVCS	.EQU	FALSE		; INVERT CS
+		.ECHO	"JUHA"
 ;
 RTCDEF		.SET	RTCDEF | SD_OPRDEF	; SET DEFAULT IN HBIOS MAINLINE
 #ENDIF
@@ -145,6 +148,7 @@ SD_DI		.EQU	%00000001	; RTC:0 IS DATA IN (CARD <- CPU)
 SD_DO		.EQU	%01000000	; RTC:6 IS DATA OUT (CARD -> CPU)
 SD_IOBASE	.EQU	SD_OPRREG	; IOBASE
 SD_INVCS	.EQU	FALSE		; INVERT CS
+		.ECHO	"N8"
 ;
 RTCDEF		.SET	RTCDEF | SD_OPRDEF	; SET DEFAULT IN HBIOS MAINLINE
 #ENDIF
@@ -159,6 +163,7 @@ SD_CNTR		.EQU	Z180_CNTR
 SD_TRDR		.EQU	Z180_TRDR
 SD_IOBASE	.EQU	SD_OPRREG	; IOBASE
 SD_INVCS	.EQU	FALSE		; INVERT CS
+		.ECHO	"CSIO"
 ;
 RTCDEF		.SET	RTCDEF | SD_OPRDEF	; SET DEFAULT IN HBIOS MAINLINE
 #ENDIF
@@ -179,6 +184,7 @@ SD_DI		.EQU	%00000001	; PPIC:0 IS DATA IN (CARD <- CPU)
 SD_DO		.EQU	%10000000	; PPIB:7 IS DATA OUT (CARD -> CPU)
 SD_IOBASE	.EQU	SD_PPIBASE	; IOBASE
 SD_INVCS	.EQU	TRUE		; INVERT CS
+		.ECHO	"PPI"
 #ENDIF
 ;
 #IF (SDMODE == SDMODE_UART)
@@ -193,6 +199,7 @@ SD_DI		.EQU	%00000001	; UART MCR:0 IS DATA IN (CARD <- CPU)
 SD_DO		.EQU	%00100000	; UART MSR:5 IS DATA OUT (CARD -> CPU)
 SD_IOBASE	.EQU	UARTIOB		; IOBASE
 SD_INVCS	.EQU	TRUE		; INVERT CS
+		.ECHO	"UART"
 #ENDIF
 ;
 #IF (SDMODE == SDMODE_DSD)		; DUAL SD
@@ -208,6 +215,7 @@ SD_DI		.EQU	%00000001	; RTC:6 IS DATA IN (CARD <- CPU)
 SD_DO		.EQU	%00000001	; RTC:0 IS DATA OUT (CARD -> CPU)
 SD_IOBASE	.EQU	SD_OPRREG	; IOBASE
 SD_INVCS	.EQU	FALSE		; INVERT CS
+		.ECHO	"DSD"
 #ENDIF
 ;
 #IF (SDMODE == SDMODE_MK4)		; MARK IV (CSIO STYLE INTERFACE)
@@ -219,6 +227,7 @@ SD_CNTR		.EQU	Z180_CNTR
 SD_TRDR		.EQU	Z180_TRDR
 SD_IOBASE	.EQU	SD_OPRREG	; IOBASE
 SD_INVCS	.EQU	FALSE		; INVERT CS
+		.ECHO	"MK4"
 #ENDIF
 ;
 #IF (SDMODE == SDMODE_SC)		; SC
@@ -232,9 +241,16 @@ SD_CNTR		.EQU	Z180_CNTR
 SD_TRDR		.EQU	Z180_TRDR
 SD_IOBASE	.EQU	SD_OPRREG	; IOBASE
 SD_INVCS	.EQU	TRUE		; INVERT CS
+		.ECHO	"SC"
 ;
 RTCDEF		.SET	RTCDEF | SD_OPRDEF	; SET DEFAULT IN HBIOS MAINLINE
 #ENDIF
+;
+		.ECHO	", IO="
+		.ECHO	SD_IOBASE
+		.ECHO	", UNITS="
+		.ECHO	SDCNT
+		.ECHO	"\n"
 ;
 #IF (SDMODE == SDMODE_MT)		; MT shift register for RCBUS (ref SDMODE_CSIO)
 ;

Source/HBIOS/simrtc.asm

@@ -7,6 +7,10 @@ SIMRTC_IO	.EQU	$FE	; SIMH IO PORT
 SIMRTC_CLKREAD	.EQU	7	; READ CLOCK COMMAND
 SIMRTC_CLKWRITE	.EQU	8	; WRITE CLOCK COMMAND
 SIMRTC_BUFSIZ	.EQU	6	; SIX BYTE BUFFER (YYMMDDHHMMSS)
+;
+	.ECHO	"SIMRTC: IO="
+	.ECHO	SIMRTC_IO
+	.ECHO	"\n"
 ;
 ; RTC DEVICE INITIALIZATION ENTRY
 ;

Source/HBIOS/sio.asm

@@ -104,12 +104,12 @@ SIO1B_CMD	.EQU	SIO1BASE + $07
 SIO1B_DAT	.EQU	SIO1BASE + $05
   #ENDIF
 ;
-#IF (SIO1MODE == SIOMODE_Z80R)
-SIO1A_CMD	.EQU	SIO0BASE + $03
-SIO1A_DAT	.EQU	SIO0BASE + $01 
-SIO1B_CMD	.EQU	SIO0BASE + $02
-SIO1B_DAT	.EQU	SIO0BASE + $00
-#ENDIF
+  #IF (SIO1MODE == SIOMODE_Z80R)
+SIO1A_CMD	.EQU	SIO1BASE + $03
+SIO1A_DAT	.EQU	SIO1BASE + $01 
+SIO1B_CMD	.EQU	SIO1BASE + $02
+SIO1B_DAT	.EQU	SIO1BASE + $00
+  #ENDIF
 ;
 #ENDIF
 ;
@@ -1170,6 +1170,31 @@ SIO0A_CFG:
 	.DW	SIO0ACLK >> 16		; ... DWORD VALUE
 	.DB	SIO0ACTCC		; CTC CHANNEL
 	.DB	SIO0MODE		; MODE
+;
+	.ECHO	"SIO MODE="
+#IF (SIO0MODE == SIOMODE_STD)
+	.ECHO	"STD"
+#ENDIF
+#IF (SIO0MODE == SIOMODE_RC)
+	.ECHO	"RC"
+#ENDIF	
+
+#IF (SIO0MODE == SIOMODE_SMB)
+	.ECHO	"SMB"
+#ENDIF
+#IF (SIO0MODE == SIOMODE_ZP)
+	.ECHO	"ZP"
+#ENDIF
+#IF (SIO0MODE == SIOMODE_Z80R)
+	.ECHO	"Z80R"
+#ENDIF
+	.ECHO	", IO="
+	.ECHO	SIO0BASE
+	.ECHO	", CHANNEL A"
+  #IF (INTMODE > 0)
+		.ECHO	", INTERRUPTS ENABLED"
+  #ENDIF
+		.ECHO	"\n"
 ;
 SIO_CFGSIZ	.EQU	$ - SIO_CFG	; SIZE OF ONE CFG TABLE ENTRY
 ;
@@ -1186,6 +1211,30 @@ SIO0B_CFG:
 	.DW	SIO0BCLK >> 16		; ... DWORD VALUE
 	.DB	SIO0BCTCC		; CTC CHANNEL
 	.DB	SIO0MODE		; MODE
+;
+	.ECHO	"SIO MODE="
+#IF (SIO0MODE == SIOMODE_STD)
+	.ECHO	"STD"
+#ENDIF
+#IF (SIO0MODE == SIOMODE_RC)
+	.ECHO	"RC"
+#ENDIF	
+#IF (SIO0MODE == SIOMODE_SMB)
+	.ECHO	"SMB"
+#ENDIF
+#IF (SIO0MODE == SIOMODE_ZP)
+	.ECHO	"ZP"
+#ENDIF
+#IF (SIO0MODE == SIOMODE_Z80R)
+	.ECHO	"Z80R"
+#ENDIF
+	.ECHO	", IO="
+	.ECHO	SIO0BASE
+	.ECHO	", CHANNEL B"
+  #IF (INTMODE > 0)
+		.ECHO	", INTERRUPTS ENABLED"
+  #ENDIF
+		.ECHO	"\n"
 ;
 #IF (SIOCNT >= 2)
 ;
@@ -1202,6 +1251,31 @@ SIO1A_CFG:
 	.DW	SIO1ACLK >> 16		; ... DWORD VALUE
 	.DB	SIO1ACTCC		; CTC CHANNEL
 	.DB	SIO1MODE		; MODE
+;
+	.ECHO	"SIO MODE="
+#IF (SIO1MODE == SIOMODE_STD)
+	.ECHO	"STD"
+#ENDIF
+#IF (SIO1MODE == SIOMODE_RC)
+	.ECHO	"RC"
+#ENDIF	
+
+#IF (SIO1MODE == SIOMODE_SMB)
+	.ECHO	"SMB"
+#ENDIF
+#IF (SIO1MODE == SIOMODE_ZP)
+	.ECHO	"ZP"
+#ENDIF
+#IF (SIO1MODE == SIOMODE_Z80R)
+	.ECHO	"Z80R"
+#ENDIF
+	.ECHO	", IO="
+	.ECHO	SIO1BASE
+	.ECHO	", CHANNEL A"
+  #IF (INTMODE > 0)
+		.ECHO	", INTERRUPTS ENABLED"
+  #ENDIF
+		.ECHO	"\n"
 ;
 	; SIO1 CHANNEL B
 SIO1B_CFG:
@@ -1216,6 +1290,30 @@ SIO1B_CFG:
 	.DW	SIO1BCLK >> 16		; ... DWORD VALUE
 	.DB	SIO1BCTCC		; CTC CHANNEL
 	.DB	SIO1MODE		; MODE
+;
+	.ECHO	"SIO MODE="
+#IF (SIO1MODE == SIOMODE_STD)
+	.ECHO	"STD"
+#ENDIF
+#IF (SIO1MODE == SIOMODE_RC)
+	.ECHO	"RC"
+#ENDIF	
+#IF (SIO1MODE == SIOMODE_SMB)
+	.ECHO	"SMB"
+#ENDIF
+#IF (SIO1MODE == SIOMODE_ZP)
+	.ECHO	"ZP"
+#ENDIF
+#IF (SIO1MODE == SIOMODE_Z80R)
+	.ECHO	"Z80R"
+#ENDIF
+	.ECHO	", IO="
+	.ECHO	SIO1BASE
+	.ECHO	", CHANNEL B"
+  #IF (INTMODE > 0)
+		.ECHO	", INTERRUPTS ENABLED"
+  #ENDIF
+		.ECHO	"\n"
 ;
 #ENDIF
 ;

Source/HBIOS/sn76489.asm

@@ -15,16 +15,29 @@
 ;======================================================================
 ; CONSTANTS
 ;======================================================================
+;
+
+	.ECHO	"SN76489 MODE="
 ;
 #IF (SNMODE == SNMODE_VGM)
 SN76489_PORT_LEFT	.EQU	$C6	; PORTS FOR ACCESSING THE SN76489 CHIP (LEFT)
 SN76489_PORT_RIGHT	.EQU	$C7	; PORTS FOR ACCESSING THE SN76489 CHIP (RIGHT)
+	.ECHO	"VGM"
 #ENDIF
 ;
 #IF (SNMODE == SNMODE_RC)
 SN76489_PORT_LEFT	.EQU	$FF	; PORTS FOR ACCESSING THE SN76489 CHIP (LEFT)
 SN76489_PORT_RIGHT	.EQU	$FB	; PORTS FOR ACCESSING THE SN76489 CHIP (RIGHT)
+	.ECHO	"RC"
 #ENDIF
+;
+	.ECHO	", IO_LEFT="
+	.ECHO	SN76489_PORT_LEFT
+	.ECHO	", IO_RIGHT="
+	.ECHO	SN76489_PORT_RIGHT
+	.ECHO	", CLOCK="
+	.ECHO	SN7CLK
+	.ECHO	" HZ\n"
 ;
 SN7_IDAT		.EQU	0
 SN7_TONECNT		.EQU	3	; COUNT NUMBER OF TONE CHANNELS
@@ -34,10 +47,6 @@ CHANNEL_0_SILENT	.EQU	$9F
 CHANNEL_1_SILENT	.EQU	$BF
 CHANNEL_2_SILENT	.EQU	$DF
 CHANNEL_3_SILENT	.EQU	$FF
-;
-	.ECHO	"SN76489 CLOCK: "
-	.ECHO	SN7CLK
-	.ECHO	"\n"
 ;
 #INCLUDE "audio.inc"
 ;

Source/HBIOS/spk.asm

@@ -40,6 +40,10 @@ SP_RTCIOMSK	.EQU	00000100B
 SP_PENDING_PERIOD	.DW	SP_NOTE_C8	; PENDING PERIOD (16 BITS)
 SP_PENDING_VOLUME	.DB	$FF		; PENDING VOL (8 BITS)
 SP_PENDING_DURATION	.DW	0		; PENDING DURATION (16 BITS)
+;
+	.ECHO	"SPK: IO="
+	.ECHO	RTCIO
+	.ECHO	"\n"
 ;
 ;======================================================================
 ;	DRIVER INITIALIZATION

Source/HBIOS/std.asm

@@ -510,7 +510,7 @@ CPUMHZ		.EQU	CPUKHZ / 1000	; CPU FREQ IN MHZ
 ;
 	.ECHO	"ASSUMED CPU SPEED: "
 	.ECHO	CPUKHZ
-	.ECHO	" KHZ\r\n"
+	.ECHO	" KHZ\n"
 ;
 	.ECHO	"INTERRUPTS: "
 #IF (INTMODE == 0)
@@ -525,7 +525,7 @@ CPUMHZ		.EQU	CPUKHZ / 1000	; CPU FREQ IN MHZ
 #IF (INTMODE == 3)
 	.ECHO	"MODE 3"
 #ENDIF
-	.ECHO	"\r\n"
+	.ECHO	"\n"
 ;
 ; SYSTEM PERIODIC TIMER MODE
 ;
@@ -598,7 +598,7 @@ SYSTIM	.SET	TM_Z280
   #IF ((DEFSERCFG & %1111100000000) == SER_BAUD115200
 	.ECHO	"115200"
   #ENDIF
-	.ECHO	" BAUD\r\n"
+	.ECHO	" BAUD\n"
 #ENDIF
 ;
 ;
@@ -629,16 +629,16 @@ SYSTIM	.SET	TM_Z280
   #IF (MEMMGR == MM_RPH)
 	.ECHO	"RHYOPHYRE ONBOARD (RPH)"
   #ENDIF
-	.ECHO   "\r\n"
+	.ECHO   "\n"
 #ENDIF
 ;
 	.ECHO	"ROM SIZE: "
 	.ECHO	ROMSIZE
-	.ECHO	" KB\r\n"
+	.ECHO	" KB\n"
 ;
 	.ECHO	"RAM SIZE: "
 	.ECHO	RAMSIZE
-	.ECHO	" KB\r\n"
+	.ECHO	" KB\n"
 ;
 ; MEMORY BANK CONFIGURATION
 ;

Source/HBIOS/syq.asm

@@ -1446,6 +1446,17 @@ SYQ0_CFG:	; DEVICE 0
 	.DB	SYQ0BASE		; IO BASE ADDRESS
 	.DW	0,0			; DEVICE CAPACITY
 	.DW	0,0			; CURRENT LBA
+;
+	.ECHO	"SYQ: MODE="
+  #IF (SYQMODE == SYQMODE_SPP)
+	.ECHO	"SPP"
+  #ENDIF
+  #IF (SYQMODE == SYQMODE_MG014)
+	.ECHO	"MG014"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	SYQ0BASE
+	.ECHO	"\n"
 #ENDIF
 ;
 #IF (SYQCNT >= 2)
@@ -1457,6 +1468,17 @@ SYQ1_CFG:	; DEVICE 1
 	.DB	SYQ1BASE		; IO BASE ADDRESS
 	.DW	0,0			; DEVICE CAPACITY
 	.DW	0,0			; CURRENT LBA
+;
+	.ECHO	"SYQ: MODE="
+  #IF (SYQMODE == SYQMODE_SPP)
+	.ECHO	"SPP"
+  #ENDIF
+  #IF (SYQMODE == SYQMODE_MG014)
+	.ECHO	"MG014"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	SYQ1BASE
+	.ECHO	"\n"
 #ENDIF
 ;
 #IF ($ - SYQ_CFG) != (SYQCNT * SYQ_CFGSIZ)

Source/HBIOS/tms.asm

@@ -42,9 +42,7 @@
 TMSCTRL1:       .EQU   1               ; CONTROL BITS
 TMSINTEN:       .EQU   5               ; INTERRUPT ENABLE BIT
 ;
-#IF TMSTIMENABLE
-	.ECHO	"TMS INTERRUPTS ENABLED\n"
-#ENDIF
+		.ECHO	"TMS: MODE="
 ;
 #IF ((TMSMODE == TMSMODE_MSX) | (TMSMODE == TMSMODE_MSX9958))
 TMS_DATREG	.EQU	$98		; READ/WRITE DATA
@@ -53,6 +51,13 @@ TMS_PPIA	.EQU	0		; PPI PORT A
 TMS_PPIB	.EQU	0		; PPI PORT B
 TMS_PPIC	.EQU	0		; PPI PORT C
 TMS_PPIX	.EQU	0		; PPI CONTROL PORT
+;
+  #IF (TMSMODE == TMSMODE_MSX)
+		.ECHO	"MSX"
+  #ENDIF
+  #IF (TMSMODE == TMSMODE_MSX9958)
+		.ECHO	"MSX9958"
+  #ENDIF
 #ENDIF
 ;
 #IF (TMSMODE == TMSMODE_COLECO)
@@ -62,6 +67,7 @@ TMS_PPIA	.EQU	0		; PPI PORT A
 TMS_PPIB	.EQU	0		; PPI PORT B
 TMS_PPIC	.EQU	0		; PPI PORT C
 TMS_PPIX	.EQU	0		; PPI CONTROL PORT
+		.ECHO	"COLECO"
 #ENDIF
 ;
 #IF (TMSMODE == TMSMODE_MSXKBD)
@@ -69,6 +75,7 @@ TMS_DATREG	.EQU	$98		; READ/WRITE DATA
 TMS_CMDREG	.EQU	$99		; READ STATUS / WRITE REG SEL
 TMS_KBDDATA	.EQU	$E0		; KBD CTLR DATA PORT
 TMS_KBDST	.EQU	$E1		; KBD CTLR STATUS/CMD PORT
+		.ECHO	"MSXKBD"
 #ENDIF
 ;
 #IF (TMSMODE == TMSMODE_N8)
@@ -78,6 +85,7 @@ TMS_PPIA	.EQU	$84		; PPI PORT A
 TMS_PPIB	.EQU	$85		; PPI PORT B
 TMS_PPIC	.EQU	$86		; PPI PORT C
 TMS_PPIX	.EQU	$87		; PPI CONTROL PORT
+		.ECHO	"N8"
 #ENDIF
 ;
 #IF (TMSMODE == TMSMODE_SCG)
@@ -88,6 +96,7 @@ TMS_PPIA	.EQU	0		; PPI PORT A
 TMS_PPIB	.EQU	0		; PPI PORT B
 TMS_PPIC	.EQU	0		; PPI PORT C
 TMS_PPIX	.EQU	0		; PPI CONTROL PORT
+		.ECHO	"SCG"
 #ENDIF
 ;
 #IF (TMSMODE == TMSMODE_MBC)
@@ -100,7 +109,15 @@ TMS_PPIC	.EQU	0		; PPI PORT C
 TMS_PPIX	.EQU	0		; PPI CONTROL PORT
 TMS_KBDDATA	.EQU	$E2		; KBD CTLR DATA PORT
 TMS_KBDST	.EQU	$E3		; KBD CTLR STATUS/CMD PORT
+		.ECHO	"MBC"
 #ENDIF
+;
+		.ECHO	", IO="
+		.ECHO	TMS_DATREG
+#IF TMSTIMENABLE
+		.ECHO	", INTERRUPTS ENABLED"
+#ENDIF
+		.ECHO	"\n"
 ;
 TMS_ROWS	.EQU	24
 ;

Source/HBIOS/uart.asm

@@ -1041,6 +1041,13 @@ UART_CFG_SBC:
 	.DB	UARTSBASE + UART_LSR		; LINE STATUS PORT (LSR)
 	.DW	UARTCFG				; LINE CONFIGURATION
 	.DW	UARTSBC_RCVBUF			; POINTER TO RCV BUFFER STRUCT
+;
+	.ECHO	"UART: MODE=SBC, IO="
+	.ECHO	UARTSBASE
+  #IF ((UARTINTS) & (INTMODE > 0))
+	.ECHO	", INTERRUPTS ENABLED"
+  #ENDIF
+	.ECHO	"\n"
 #ENDIF
 #IF (UARTAUX)
 UART_CFG_AUX:
@@ -1051,6 +1058,10 @@ UART_CFG_AUX:
 	.DB	UARTABASE + UART_LSR		; LINE STATUS PORT (LSR)
 	.DW	UARTCFG				; LINE CONFIGURATION
 	.DW	0				; NO INT HANDLER
+;
+	.ECHO	"UART: MODE=AUX, IO="
+	.ECHO	UARTABASE
+	.ECHO	"\n"
 #ENDIF
 #IF (UARTCAS)
 UART_CFG_CAS:
@@ -1061,6 +1072,13 @@ UART_CFG_CAS:
 	.DB	UARTCBASE + UART_LSR		; LINE STATUS PORT (LSR)
 	.DW	UARTCASSPD			; LINE CONFIGURATION
 	.DW	UARTCAS_RCVBUF			; POINTER TO RCV BUFFER STRUCT
+;
+	.ECHO	"UART: MODE=CAS, IO="
+	.ECHO	UARTCBASE
+  #IF ((UARTINTS) & (INTMODE > 0))
+	.ECHO	", INTERRUPTS ENABLED"
+  #ENDIF
+	.ECHO	"\n"
 #ENDIF
 #IF (UARTMFP)
 UART_CFG_MFP:
@@ -1071,6 +1089,10 @@ UART_CFG_MFP:
 	.DB	UARTMBASE + UART_LSR		; LINE STATUS PORT (LSR)
 	.DW	UARTCFG				; LINE CONFIGURATION
 	.DW	0				; SHOULD NEVER NEED INT HANDLER
+;
+	.ECHO	"UART: MODE=MFP, IO="
+	.ECHO	UARTSBASE
+	.ECHO	"\n"
 #ENDIF
 #IF (UART4)
 	; 4UART SERIAL PORT A
@@ -1080,6 +1102,11 @@ UART_CFG_MFP:
 	.DB	UART4BASE+0 + UART_LSR		; LINE STATUS PORT (LSR)
 	.DW	UARTCFG				; LINE CONFIGURATION
 	.DW	0				; SHOULD NEVER NEED INT HANDLER
+;
+	.ECHO	"UART: MODE=4UART, IO="
+	.ECHO	UART4BASE+0
+	.ECHO	"\n"
+;
 	; 4UART SERIAL PORT B
 	.DB	0				; DEVICE NUMBER (UPDATED DURING INIT)
 	.DB	0				; UART TYPE
@@ -1087,6 +1114,11 @@ UART_CFG_MFP:
 	.DB	UART4BASE+8 + UART_LSR		; LINE STATUS PORT (LSR)
 	.DW	UARTCFG				; LINE CONFIGURATION
 	.DW	0				; SHOULD NEVER NEED INT HANDLER
+;
+	.ECHO	"UART: MODE=4UART, IO="
+	.ECHO	UART4BASE+8
+	.ECHO	"\n"
+;
 	; 4UART SERIAL PORT C
 	.DB	0				; DEVICE NUMBER (UPDATED DURING INIT)
 	.DB	0				; UART TYPE
@@ -1094,6 +1126,11 @@ UART_CFG_MFP:
 	.DB	UART4BASE+16 + UART_LSR		; LINE STATUS PORT (LSR)
 	.DW	UARTCFG				; LINE CONFIGURATION
 	.DW	0				; SHOULD NEVER NEED INT HANDLER
+;
+	.ECHO	"UART: MODE=4UART, IO="
+	.ECHO	UART4BASE+16
+	.ECHO	"\n"
+;
 	; 4UART SERIAL PORT D
 	.DB	0				; DEVICE NUMBER (UPDATED DURING INIT)
 	.DB	0				; UART TYPE
@@ -1101,6 +1138,10 @@ UART_CFG_MFP:
 	.DB	UART4BASE+24 + UART_LSR		; LINE STATUS PORT (LSR)
 	.DW	UARTCFG				; LINE CONFIGURATION
 	.DW	0				; SHOULD NEVER NEED INT HANDLER
+;
+	.ECHO	"UART: MODE=4UART, IO="
+	.ECHO	UART4BASE+24
+	.ECHO	"\n"
 #ENDIF
 #IF (UARTRC)
 	; UARTRC SERIAL PORT A
@@ -1110,6 +1151,11 @@ UART_CFG_MFP:
 	.DB	UARTRBASE + UART_LSR		; LINE STATUS PORT (LSR)
 	.DW	UARTCFG				; LINE CONFIGURATION
 	.DW	0				; SHOULD NEVER NEED INT HANDLER
+;
+	.ECHO	"UART: MODE=RC, IO="
+	.ECHO	UARTRBASE+0
+	.ECHO	"\n"
+;
 	; UARTRC SERIAL PORT B
 	.DB	0				; DEVICE NUMBER (UPDATED DURING INIT)
 	.DB	0				; UART TYPE
@@ -1117,6 +1163,11 @@ UART_CFG_MFP:
 	.DB	UARTRBASE+8 + UART_LSR		; LINE STATUS PORT (LSR)
 	.DW	UARTCFG				; LINE CONFIGURATION
 	.DW	0				; SHOULD NEVER NEED INT HANDLER
+;
+	.ECHO	"UART: MODE=RC, IO="
+	.ECHO	UARTRBASE+8
+	.ECHO	"\n"
+;
 #ENDIF
 #IF (UARTDUAL)
 	; DUAL UART CHANNEL A
@@ -1126,6 +1177,11 @@ UART_CFG_MFP:
 	.DB	UARTDBASE + UART_LSR		; LINE STATUS PORT (LSR)
 	.DW	UARTCFG				; LINE CONFIGURATION
 	.DW	0				; SHOULD NEVER NEED INT HANDLER
+;
+	.ECHO	"UART: MODE=DUAL, IO="
+	.ECHO	UARTDBASE+0
+	.ECHO	"\n"
+;
 	; DUAL UART CHANNEL B
 	.DB	0				; DEVICE NUMBER (UPDATED DURING INIT)
 	.DB	0				; UART TYPE
@@ -1133,6 +1189,11 @@ UART_CFG_MFP:
 	.DB	UARTDBASE+8 + UART_LSR		; LINE STATUS PORT (LSR)
 	.DW	UARTCFG				; LINE CONFIGURATION
 	.DW	0				; SHOULD NEVER NEED INT HANDLER
+;
+	.ECHO	"UART: MODE=DUAL, IO="
+	.ECHO	UARTDBASE+8
+	.ECHO	"\n"
+;
 #ENDIF
 ;
 UART_CNT	.EQU	($ - UART_CFG) / 8

Source/HBIOS/uf.asm

@@ -23,6 +23,10 @@ UF_USB_ACTIVE	.DB	0		; USB CABLE CONNECTED STATUS FLAG
 ; DEVICE DESCRIPTION TABLE
 ;
 UF_CFG:	.DW	SER_9600_8N1		; DUMMY CONFIGURATION
+;
+	.ECHO	"USB-FIFO: IO="
+	.ECHO	UFBASE
+	.ECHO	"\n"
 ;
 ; SETUP THE DISPATCH TABLE ENTRY AND INITIALIZE HARDWARE
 ;

Source/HBIOS/vdu.asm

@@ -81,6 +81,12 @@ VDU_R11		.EQU	DSCANL-1
 VDU_R10		.EQU	(VDU_BLNK + DSCANL-1)
 VDU_R11		.EQU	DSCANL-1
 #ENDIF
+;
+		.ECHO	"VDU: IO="
+		.ECHO	VDU_RAMRD
+		.ECHO	", PPK IO="
+		.ECHO	VDU_PPIA
+		.ECHO	"\n"
 ;
 ;======================================================================
 ; VDU DRIVER - INITIALIZATION

Source/HBIOS/vga.asm

@@ -20,6 +20,14 @@ VGA_CFG		.EQU	VGA_BASE + $04	; VGA3 BOARD CFG REGISTER
 VGA_HI		.EQU	VGA_BASE + $05	; BOARD RAM HI ADDRESS
 VGA_LO		.EQU	VGA_BASE + $06	; BOARD RAM LO ADDRESS
 VGA_DAT		.EQU	VGA_BASE + $07	; BOARD RAM BYTE R/W
+;
+		.ECHO	"VGA: "
+		.ECHO	"IO="
+		.ECHO	VGA_BASE
+		.ECHO	", KBD MODE=PS/2"
+		.ECHO	", KBD IO="
+		.ECHO	VGA_KBDDATA
+		.ECHO	"\n"
 ;
 VGA_NOBL	.EQU	00000000B	; NO BLINK
 VGA_NOCU	.EQU	00100000B	; NO CURSOR

Source/HBIOS/vrc.asm

@@ -25,6 +25,13 @@ VRC_COLS	.EQU	64
 #DEFINE	VRC_FONT FONTVGARC
 ;
 TERMENABLE	.SET	TRUE		; INCLUDE TERMINAL PSEUDODEVICE DRIVER
+;
+		.ECHO	"VRC: IO="
+		.ECHO	VRC_BASE
+		.ECHO	", KBD MODE=VRC"
+		.ECHO	", KBD IO="
+		.ECHO	VRC_KBDDATA
+		.ECHO	"\n"
 ;
 ;======================================================================
 ; VRC DRIVER - INITIALIZATION

Source/HBIOS/ym2612.asm

@@ -38,6 +38,10 @@ YM_RDY_RST		.DB	0	; FLAG INDICATES IF DEVICE IS IN READY (NZ) OR RESET STATE (Z)
 YM_DEBUG		.EQU	0	; CHANGE TO 1 TO ENABLE DEBUGGING
 YM_RSTCFG		.EQU	0	; SET TO 1 FOR FULL REGISTER CLEAR
 YM_FAST3438		.EQU	0	; FAST CPU'S WITH A YM3438 MAY REQUIRE A DELAY
+;
+		.ECHO	"YM: IO="
+		.ECHO	YMSEL
+		.ECHO	"\n"
 ;
 ;------------------------------------------------------------------------------
 ; Driver function table and instance data

Source/HBIOS/z2u.asm

@@ -715,6 +715,15 @@ Z2U0_CFG:
 	.DW	Z2U0CFG			; LINE CONFIGURATION
 	.DW	Z2U0_RCVBUF		; POINTER TO RCV BUFFER STRUCT
 ;
+;
+	.ECHO	"Z2U: IO="
+	.ECHO	Z2U0BASE
+#IF (INTMODE == 3)
+	.ECHO	", INTERRUPTS ENABLED"
+#ENDIF
+	.ECHO	"\n"
+
+;
 Z2U_CFGSIZ	.EQU	$ - Z2U_CFG	; SIZE OF ONE CFG TABLE ENTRY
 ;
 Z2U_CFGCNT	.EQU	($ - Z2U_CFG) / Z2U_CFGSIZ

Source/Images/Build.cmd

@@ -1,8 +1,9 @@
 @echo off
 setlocal
 
-::call BuildDisk.cmd bp hd wbw_hd512 || exit /b
-::goto :eof
+:: call BuildDisk.cmd bp hd wbw_hd1k
+:: copy /b hd1k_prefix.dat + ..\..\Binary\hd1k_bp.img + ..\..\Binary\hd1k_cpm22.img + ..\..\Binary\hd1k_zsdos.img + ..\..\Binary\hd1k_nzcom.img + ..\..\Binary\hd1k_cpm3.img + ..\..\Binary\hd1k_zpm3.img + ..\..\Binary\hd1k_ws4.img ..\..\Binary\hd1k_combo_bp.img || exit /b
+:: goto :eof
 
 echo.
 echo Building Floppy Disk Images...
@@ -42,8 +43,6 @@ call BuildDisk.cmd bascomp hd wbw_hd512 || exit /b
 call BuildDisk.cmd fortran hd wbw_hd512 || exit /b
 call BuildDisk.cmd games hd wbw_hd512 || exit /b
 
-if exist ..\BPBIOS\bpbio-ww.rel call BuildDisk.cmd bp hd wbw_hd512 || exit /b
-
 echo.
 echo Building Combo Disk (512 directory entry format) Image...
 copy /b ..\..\Binary\hd512_cpm22.img + ..\..\Binary\hd512_zsdos.img + ..\..\Binary\hd512_nzcom.img + ..\..\Binary\hd512_cpm3.img + ..\..\Binary\hd512_zpm3.img + ..\..\Binary\hd512_ws4.img ..\..\Binary\hd512_combo.img || exit /b
@@ -67,7 +66,7 @@ call BuildDisk.cmd bascomp hd wbw_hd1k || exit /b
 call BuildDisk.cmd fortran hd wbw_hd1k || exit /b
 call BuildDisk.cmd games hd wbw_hd1k || exit /b
 
-if exist ..\BPBIOS\bpbio-ww.rel call BuildDisk.cmd bp hd wbw_hd1k || exit /b
+if exist ..\BPBIOS\bp*.rel call BuildDisk.cmd bp hd wbw_hd1k || exit /b
 
 copy hd1k_prefix.dat ..\..\Binary\ || exit /b
 

Source/Images/Makefile

@@ -19,7 +19,7 @@ HD1KIMGS = hd1k_cpm22.img hd1k_zsdos.img hd1k_nzcom.img \
 HD1KXIMGS = hd1k_z80asm.img hd1k_aztecc.img hd1k_hitechc.img \
 	hd1k_bascomp.img hd1k_fortran.img hd1k_games.img \
 	hd1k_tpascal.img hd1k_qpm.img hd1k_blank.img
-# HD1KIMGS += hd1k_bp.img
+HD1KXIMGS += hd1k_bp.img
 
 HD512PREFIX =
 HD1KPREFIX = hd1k_prefix.dat

Source/Makefile

@@ -7,7 +7,7 @@
 .ONESHELL:
 .SHELLFLAGS = -cex
 
-all: prop shared images rom zrc z1rcc zzrcc
+all: prop shared bp images rom zrc z1rcc zzrcc
 
 doc:
 	$(MAKE) --directory Doc $(ACTION)

Source/ver.inc

@@ -2,7 +2,7 @@
 #DEFINE	RMN	4
 #DEFINE	RUP	0
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.4.0-dev.25"
+#DEFINE BIOSVER	"3.4.0-dev.30"
 #define rmj	RMJ
 #define rmn	RMN
 #define rup	RUP

Source/ver.lib

@@ -3,5 +3,5 @@ rmn	equ	4
 rup	equ	0
 rtp	equ	0
 biosver	macro
-	db	"3.4.0-dev.25"
+	db	"3.4.0-dev.30"
 	endm