Enable CH and LPT Drivers for Duodyne

Thanks and credit to Will Sowerbutts for contributing and maintaining this critical utility!

ReadMe.md

@@ -3,7 +3,7 @@
 **RomWBW ReadMe** \
 Version 3.4 \
 Wayne Warthen  ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \
-07 Oct 2023
+19 Oct 2023
 
 # Overview
 

ReadMe.txt

@@ -1,6 +1,6 @@
 RomWBW ReadMe
 Wayne Warthen (wwarthen@gmail.com)
-07 Oct 2023
+19 Oct 2023
 
 
 

Source/Apps/Build.cmd

@@ -32,6 +32,7 @@ pushd Dev && call Build || exit /b & popd
 pushd VGM && call Build || exit /b & popd
 pushd cpuspd && call Build || exit /b & popd
 pushd Survey && call Build || exit /b & popd
+pushd HTalk && call Build || exit /b & popd
 
 copy *.com %APPBIN%\ || exit /b
 

Source/Apps/Clean.cmd

@@ -18,3 +18,4 @@ pushd Dev && call Clean || exit /b 1 & popd
 pushd VGM && call Clean || exit /b 1 & popd
 pushd cpuspd && call Clean || exit /b 1 & popd
 pushd Survey && call Clean || exit /b 1 & popd
+pushd HTalk && call Clean || exit /b 1 & popd

Source/Apps/FAT/ReadMe.txt

@@ -1,7 +1,7 @@
 RomWBW HBIOS CP/M FAT Utility ("FAT.COM")
 
 Author: Wayne Warthen
-Updated: 12-Apr-2021
+Updated: 12-Oct-2023
 
 Application to manipulate and exchange files with a FAT (DOS)
 filesystem.  Runs on any HBIOS hosted CP/M implementation.
@@ -101,4 +101,5 @@ HISTORY:
   11-Oct-2019: v0.9.7 (beta) fix FORMAT to use existing partition table entries
                              add attributes to directory listing
   12-Apr-2021: v0.9.8 (beta) support CP/NET drives
+  12-Oct-2023: v0.9.9 (beta) handle updated HBIOS Disk Device call
 		      

Source/Apps/HTalk/Build.cmd

@@ -0,0 +1,14 @@
+@echo off
+setlocal
+
+set TOOLS=../../../Tools
+set PATH=%TOOLS%\tasm32;%PATH%
+set TASMTABS=%TOOLS%\tasm32
+
+echo Building HTalk...
+tasm -t80 -g3 -fFF htalk.asm htalk.com %htalk.lst || exit /b
+
+copy /Y htalk.com ..\..\..\Binary\Apps\ || exit /b
+rem copy /Y *.ovr ..\..\..\Binary\Apps\ || exit /b
+rem copy /Y *.hlp ..\..\..\Binary\Apps\ || exit /b
+rem copy /Y *.doc ..\..\..\Binary\Apps\ || exit /b

Source/Apps/HTalk/Clean.cmd

@@ -0,0 +1,5 @@
+@echo off
+setlocal
+
+if exist *.com del *.com
+if exist *.lst del *.lst

Source/Apps/HTalk/Makefile

@@ -0,0 +1,10 @@
+OBJECTS = htalk.com
+#DOCS = htalk.txt
+DEST = ../../../Binary/Apps
+DOCDEST = ../../../Binary/Apps
+TOOLS = ../../../Tools
+include $(TOOLS)/Makefile.inc
+
+%.com: USETASM=1
+
+

Source/Apps/HTalk/htalk.asm

@@ -0,0 +1,725 @@
+;===============================================================================
+;HTALK - BARE MINIMUM TERMINAL INTERFACE
+;
+; CONSOLE TALKS TO ARBITRARY CHARACTER DEVICE.
+;===============================================================================
+;
+; AUTHOR: TOM PLANO (TOMPLANO@PROTON.ME)
+;
+; USAGE:
+;	HTALK $<CHAR_DEVICE_NUM>
+;
+;_______________________________________________________________________________
+;
+; CHANGE LOG:
+;			I'VE NOTATED SECTIONS OF CODE THAT ARNT REQUIRED IF THIS APP IS
+;			INCORPORATED INTO DBGMOD WITH A <OPT> TAG
+;
+;_______________________________________________________________________________
+;
+; TODO:
+; 	SEE ENUM_DEV1 TODO
+;				
+;
+;_______________________________________________________________________________
+;
+;===============================================================================
+; DEFINITIONS
+;===============================================================================
+;
+STKSIZ	.EQU	$FF
+;
+; HBIOS SYSTEM CALLS AND ID STRING ADDRESS
+; 
+ROMWBW_ID	.EQU		$FFFE	; ROMWBW ID STRING ADDRESS
+HBIOS_SYS	.EQU		$FFF0 	; HBIOS SYSCALL ADDRESS
+
+H_SYSGET	.EQU		$F8		;	GET SYSTEM INFO
+H_CIOCNT	.EQU		$00		; GET CHAR DEV COUNT SUBFUNCTION
+
+BF_CIOIN			.EQU		$00	; HBIOS CHAR INPUT 
+BF_CIOOUT			.EQU		$01	; HBIOS CHAR OUTPUT 
+BF_CIOIST			.EQU		$02	; HBIOS CHAR INPUT STATUS 
+BF_CIOOST			.EQU		$03	; HBIOS CHAR OUTPUT STATUS 
+BF_CIOINIT		.EQU		$04	; HBIOS CHAR I/O INIT 
+BF_CIOQUERY		.EQU		$05	; HBIOS CHAR I/O QUERY 
+BF_CIODEVICE	.EQU		$06	; HBIOS CHAR I/O DEVICE
+;
+; SUPPORTED HBIOS CIO DEVICE TYPES
+; 
+CIODEV_UART		.EQU		$00 ; 16C550 FAMILY SERIAL INTERFACE UART.ASM
+CIODEV_ASCI		.EQU		$10 ; Z180 BUILT-IN SERIAL PORTS ASCI.ASM
+CIODEV_TERM		.EQU		$20 ; TERMINAL ANSI.ASM
+CIODEV_PRPCON	.EQU		$30 ; PROPIO SERIAL CONSOLE INTERFACE PRP.ASM
+CIODEV_PPPCON	.EQU 		$40 ; PARPORTPROP SERIAL CONSOLE INTERFACE PPP.ASM
+CIODEV_SIO		.EQU		$50 ; ZILOG SERIAL PORT INTERFACE SIO.ASM
+CIODEV_ACIA		.EQU		$60 ; MC68B50 ASYNCHRONOUS INTERFACE ACIA.ASM
+CIODEV_PIO		.EQU		$70 ; ZILOG PARALLEL INTERFACE CONTROLLER PIO.ASM
+CIODEV_UF			.EQU		$80 ; FT232H-BASED ECB USB FIFO UF.ASM
+CIODEV_DUART	.EQU		$90 ; SCC2681 FAMILY DUAL UART DUART.ASM
+CIODEV_Z2U		.EQU		$A0 ; ZILOG Z280 BUILT-IN SERIAL PORTS Z2U.ASM
+CIODEV_LPT		.EQU		$B0 ; PARALLEL I/O CONTROLLER LPT.ASM
+
+; HBIOS CURRENT CONSOLE NUMBER
+CIO_CONSOLE	.EQU	$80
+
+; SPECIAL CHARS
+CTRLC			.EQU	$03
+CHR_BEL		.EQU	$07
+CHR_CR		.EQU	$0D
+CHR_LF		.EQU	$0A
+CHR_BS		.EQU	$08
+CHR_ESC		.EQU	$1B
+CHR_DEL		.EQU	$7F
+
+;
+;===============================================================================
+; BEGIN MAIN PROGRAM 
+;===============================================================================
+;
+	.ORG	$0100
+;	
+; SETUP STACK (SAVE OLD VALUE)
+;	<OPT> HANDLED BY DBGMON	
+	LD		(STKSAV),SP
+	LD		SP,STACK
+	
+
+;
+; INITIALIZATION + STARTUP MESSAGE + HBIOS DETECT
+;	<OPT> HANDLED BY DBGMON	
+	CALL INIT_PROG
+	JP NZ,EXIT
+;
+; LIST HBIOS DEV OPTIONS FOR REFERENCE
+; ALSO GETS MAX CONN
+;	
+;	<OPT> THIS IS OPTIONAL BECAUSE IF A CHAR DEVICE DOESNT EXIST, WE NEVER READ OR
+; WRITE TO IT, WE SIMPLY CALL CIOIST AND CIOOST OVER AND OVER ON IT, WITHOUT
+;	EVER PUSHING DATA TO IT
+	CALL	ENUM_DEV
+	JP NZ,EXIT
+;
+; PARSE COMMAND LINE 
+;
+ 	CALL	PARSE		
+	JP NZ,EXIT
+;
+; RUN CONVERSTION WITH CHAR DEVICE
+;
+	CALL 	TALK
+;
+;  DONE
+	JP		EXIT
+
+
+;
+; CLEAN UP AND RETURN TO CALLING PROCESS
+;
+EXIT:	
+	CALL 	NEWLINE						; ...
+	LD		HL,STR_EXITMSG	; LOAD EXIT STRING
+	CALL	PRTSTR					;	PRINT IT
+	CALL 	NEWLINE						; ...
+	LD		SP,(STKSAV)			; RESET STACK
+	RET										; RETURN TO CALLER
+	
+
+;
+;===============================================================================
+; END MAIN PROGRAM 
+;===============================================================================
+;
+
+;
+;===============================================================================
+; BEGIN MAIN PROGRAM SUBROUTINES
+;===============================================================================
+;
+	
+INIT_PROG:
+	LD		HL, STR_BANNER 	; LOAD WELCOME BANNER
+	CALL	PRTSTR					;	PRINT IT
+	CALL 	NEWLINE					;	...
+	LD		HL,(ROMWBW_ID) 	; GET FIRST BYTE OF ROMWBW MARKER
+	LD		A,(HL)					;	... THROUGH HL 
+	CP		'W'							; MATCH?
+	JP		NZ,NOTHBIOS			; ABORT WITH INVALID CONFIG BLOCK
+	INC		HL							; NEXT BYTE (MARKER BYTE 2)
+	LD		A,(HL)					; LOAD IT
+	CP		~'W'						; MATCH?
+	JP		NZ,NOTHBIOS			; ABORT WITH INVALID CONFIG BLOCK
+	LD		HL,STR_HBIOS		; POINT TO HBIOS STR
+	CALL	PRTSTR					; PRINT IT
+	CALL 	NEWLINE					; ...
+	RET
+;
+;	HBOIS NOT DETECTED, BAIL OUT W/ ERROR
+;
+NOTHBIOS:
+	LD		HL,STR_BIOERR		; LOAD HBIOS NOT FOUND STR
+	CALL	PRTSTR					; PRINT IT
+	CALL 	NEWLINE					; ...
+	AND 	$FF							; SET FLAGS
+	RET
+
+ENUM_DEV:
+;
+; CHAR COUNT HEADER
+;
+	LD 		HL,STR_DEVS_FOUND
+	CALL 	PRTSTR
+;
+;GET COUNT OF CHAR UNITS
+;
+	LD 		B,H_SYSGET			; LOAD SYSGET HBIOS FUNCTION
+	LD		C,H_CIOCNT			; LOAD SYSGET CHAR DEV COUNT SUBFUNCTION
+	CALL 	HBIOS_SYS				; JUMP TO HBIOS
+	OR		A								; SET FLAGS
+	JP 		NZ, EXIT				; JUMP TO EXIT ON FAILED
+	LD 		A,E							;	NUM CHAR DEVICES NOW IN A
+
+	DEC 	A								; DEC NUM DEVICES TO BE	0 INDEXED
+	LD		(CIODEV_CNT), A	; STORE BEFORE PRINT 
+	LD		(CIODEV_MAX), A	; STORE BEFORE PRINT 
+	INC A									; RESTORE NUM DEVICES VALUE
+
+	CALL 	PRTHEX 					; PRINT NUMBER OF UNITS FOUND
+	CALL 	NEWLINE						; ...
+
+ENUM_DEV1:
+
+	LD 		IX, TGT_DEV				
+; TODO: H AND L DONT ALWAYS GET SET BY THE DRIVERS. FIND SOME WAY TO MASK
+; THEM OUT IF THEY ARE THE SAME BEFORE AND AFTER THE CALL?
+	LD 		B, BF_CIODEVICE		; LOAD HBIOS FUNCTION TO QUERRY DEVICE INFO
+	LD		HL, CIODEV_CNT		; REQUEST A CHAR DEVICE
+	LD		C, (HL)						; ...
+	LD		(IX), C						; REMEMBER WHAT DEVICE WE ASKED FOR BEFORE BE
+	CALL	HBIOS_SYS					; EXECUTE HBIOS SUBROUTINE
+	OR		A									; SET FLAGS
+	RET NZ									; RETURN FAILED
+;
+;	STORE RESULTS OF HBOIS DEVICE QUERRY
+;
+  LD 		A,C								; MOVE C TO A
+	LD		(IX+1),	A					; STORE A DEVICE ATTRIBUTES, SKIP FIRST ENTRY
+	LD		A,D
+	LD		(IX+2),	A
+	LD		A,E
+	LD		(IX+3),	A
+	LD		A,H
+	LD		(IX+4),	A
+	LD		A,L
+	LD		(IX+5),	A
+;
+;	PRINT FORMATED DATA LOOP 
+;
+	LD 		B, $06 					;	PRINT THE 5 ELEMENTS OF DEV_STR_TBL
+	LD		HL,DEV_STR_TBL	; TABLE BASE PTR
+
+PLOOP_BASE:
+	CALL 	PRTSTR					; PTRSTR INCREMENTS HL FOR US
+	LD		A, (IX)
+	CALL 	PRTHEX
+	LD		A, '|'
+	CALL 	COUT
+	INC 	IX
+	DJNZ	PLOOP_BASE
+
+	CALL NEWLINE
+
+	LD A, (CIODEV_CNT) 
+	DEC A
+	LD		(CIODEV_CNT), A
+	JP P,	ENUM_DEV1 ; JUMP WHILE CIODEV_CNT >=0
+	AND $00
+	RET
+
+
+;
+; RUN CONVERSTION WITH CHAR DEVICE
+;
+TALK:	
+;
+; INIT PING PONG DEVICE POINTERS 
+;
+	LD 		IX,	USER_CON 	; LOAD VALUE AT ADDR USER_CON
+	LD 		A, (IX) 			; LOAD VALUE AT ADDR USER_CON
+	LD		(RF_DEV), A		; STORE TO ADDR RF_DEV
+	LD		A, (IX+1)			;	LOAD VALUE AT ADDR TARGET_CON
+	LD		(WT_DEV), A		;	STORE TO ADDR WT_DEV
+;
+; READ FROM RF_DEV -> WRITE TO WT_DEV
+;
+TALK_LOOP:
+;
+; CHECK FOR DATA ON RF_DEV
+;
+	LD		B,BF_CIOIST		; SET HBIOS FUNCTION TO RUN
+	LD		HL, RF_DEV
+	LD		C,(HL)		
+	CALL	HBIOS_SYS			; CHECK FOR CHAR PENDING ON INPUT BUFFER USING HBIOS
+	OR		A							;	SET FLAGS	 
+	JP		Z,TALK_NEXT		; JUMP NO CHARACTERS  READY 
+	JP		M,TALK_NEXT		;	JUMP ERROR ON READ 	
+;
+; EXEC READ FROM RF_DEV 
+;
+	LD		B,BF_CIOIN			; SET FUNCTION TO RUN
+	LD		HL, RF_DEV
+	LD		C,(HL)				; RETRIEVE CON_DEV_NUM TO READ/WRITE FROM ACTIVE CONSOLE
+	CALL	HBIOS_SYS			; CHECK FOR CHAR PENDING USING HBIOS
+	LD 		A,E						; MOVE RESULT TO A
+	CP		CTRLC					; CHECK FOR EXIT REQUEST (CTRL+C)
+	RET		Z							; IF SO, BAIL OUT
+	PUSH	AF						; SAVE THE CHAR WE READ
+;
+; CHECK FOR SPACE ON WT_DEV
+;
+	LD		B,BF_CIOOST		; SET HBIOS FUNCTION TO RUN
+	LD		HL, WT_DEV
+	LD		C,(HL)	
+	CALL	HBIOS_SYS			; CHECK FOR SPACE IN OUTPUT BUFFER USING HBIOS
+	
+	OR		A							; 0 OR 1 IS A VALID RETURN 
+	JP		Z,TALK_NEXT		;	JUMP  NO SPACE
+	JP		M,TALK_NEXT		; JUMP 	ERROR ON WRITE 
+;
+; EXEC WRITE TO WT_DEV
+;
+	LD		B,BF_CIOOUT		; SET HBIOS FUNCTION TO RUN
+	LD		HL, WT_DEV
+	LD		C,(HL)				; RETRIEVE TGT_DEV_NUM TO READ/WRITE FROM TARGET CHAR DEVICE
+	;
+	POP		AF						; RECOVER THE CHARACTER
+	LD		E,A						; MOVE CHARACTER TO E
+	CALL	HBIOS_SYS			; WRITE CHAR USING HBIOS
+
+TALK_NEXT:
+;
+; SWAP RF_DEV  AND WT_DEV
+;
+	LD 		IX,	RF_DEV	 	; LOAD VALUE AT ADDR USER_CON
+	LD 		A, (IX)				; LOAD VALUE AT ADDR RF_DEV
+	LD 		B, (IX+1) 		; LOAD VALUE AT ADDR WT_DEV
+	LD		(IX+1), A			;	STORE TO OLD RF_DEV TO  ADDR WT_DEV
+	LD		A, B					;	MOVE OLD WT_DEV TO A 
+	LD		(IX), A				;	STORE TO OLD WT_DEF TO  ADDR RF_DEV
+	JP		TALK_LOOP			; LOOP
+
+;
+;===============================================================================
+; END MAIN PROGRAM SUBROUTINES
+;===============================================================================
+;
+
+;
+;===============================================================================
+; BEGIN ROUTINES THAT ARE NOT COMPATIBLE WITH DBGMON
+;===============================================================================
+;
+
+
+PARSE:
+;
+	LD		HL,$81					; POINT TO START OF COMMAND TAIL (AFTER LENGTH BYTE)
+	CALL	NONBLANK				; SKIP LEADING BLANKS, 
+	CALL	HEXBYTE 
+	JP		C,ERRHEXRD			; IF NOT, ERR
+  LD		(TARGET_CON),A	; REQUESTED TARGET CONN 
+	
+	LD		B,A	; MOVE  TO B							
+
+	LD		HL,CIODEV_MAX		; GRAB MAX VALUE OF TARGETCON
+	LD		A,(HL)
+
+	CP		B								; CHECK IF B<=A
+	JP		M, 	ERROOR				; IF B>A,  and both are less then 80 then S SET, ERR
+	JP		C,	ERROOR        ; IF B> 80 carry set instead (signed numbers problem)
+	; swap A and B
+
+	JP		PE, ERROOR					; IF B>A, C SET, ERR
+
+	LD	HL, MSGTALKING		; PRINT TARGET DEVICE
+	CALL PRTSTR
+	LD A, B								; RETRIEVE TARGET CON
+	CALL PRTHEX
+	CALL  NEWLINE
+	
+	AND $00
+	RET
+
+
+
+;
+;NOT COMPATIBLE WITH THE DBGMON FUNCTION OF THE SAME NAME
+;
+NONBLANK:
+	LD	A,(HL)				; LOAD NEXT CHARACTER
+	OR	A							; STRING ENDS WITH A NULL
+	RET	Z							; IF NULL, RETURN POINTING TO NULL
+	CP	' '						; CHECK FOR BLANK
+	RET	NZ						; RETURN IF NOT BLANK
+	INC	HL						; IF BLANK, INCREMENT CHARACTER POINTER
+	JR	NONBLANK			; AND LOOP
+
+;
+;
+;===============================================================================
+; END ROUTINES THAT ARE NOT COMPATIBLE WITH DBGMON
+;===============================================================================
+;
+
+
+
+
+;
+;===============================================================================
+; BEGIN ROUTINES THAT ARE LIFTED FROM  DBGMON
+;===============================================================================
+;
+
+
+;
+;	PRINT THE VALUE IN A IN HEX WITHOUT DESTROYING ANY REGISTERS
+;
+PRTHEX:
+	PUSH	DE				; SAVE DE
+	CALL	HEXASCII	; CONVERT VALUE IN A TO HEX CHARS IN DE
+	LD	A,D					; GET THE HIGH ORDER HEX CHAR
+	CALL	COUT			; PRINT IT
+	LD	A,E					; GET THE LOW ORDER HEX CHAR
+	CALL	COUT			; PRINT IT
+	POP	DE					; RESTORE DE
+	RET							; DONE
+
+;
+; CONVERT BINARY VALUE IN A TO ASCII HEX CHARACTERS IN DE
+;
+
+HEXASCII:
+	LD	D,A				; SAVE A IN D
+	CALL	HEXCONV	; CONVERT LOW NIBBLE OF A TO HEX
+	LD	E,A				; SAVE IT IN E
+	LD	A,D				; GET ORIGINAL VALUE BACK
+	RLCA					; ROTATE HIGH ORDER NIBBLE TO LOW BITS
+	RLCA
+	RLCA
+	RLCA
+	CALL	HEXCONV	; CONVERT NIBBLE
+	LD	D,A				; SAVE IT IN D
+	RET						; DONE
+
+;
+; CONVERT LOW NIBBLE OF A TO ASCII HEX
+;
+HEXCONV:
+	AND	$0F	     	; LOW NIBBLE ONLY
+	ADD	A,$90
+	DAA	
+	ADC	A,$40
+	DAA	
+	RET
+;
+
+
+;
+; ADD THE VALUE IN A TO HL (HL := HL + A)
+;
+ADDHL:
+	ADD	A,L				; A := A + L
+	LD	L,A				; PUT RESULT BACK IN L
+	RET	NC				; IF NO CARRY, WE ARE DONE
+	INC	H					; IF CARRY, INCREMENT H
+	RET						; AND RETURN
+
+
+;
+;__________________________________________________________________________________________________
+;
+; UTILITY PROCS TO PRINT SINGLE CHARACTERS WITHOUT TRASHING ANY REGISTERS
+;
+;__________________________________________________________________________________________________
+;
+PC_SPACE:
+	PUSH	AF
+	LD	A,' '
+	JR	PC_PRTCHR
+PC_COLON:
+	PUSH	AF
+	LD	A,':'
+	JR	PC_PRTCHR
+PC_CR:
+	PUSH	AF
+	LD	A,CHR_CR
+	JR	PC_PRTCHR
+
+PC_LF:
+	PUSH	AF
+	LD	A,CHR_LF
+	JR	PC_PRTCHR
+
+PC_PRTCHR:
+	CALL	COUT
+	POP	AF
+	RET
+
+NEWLINE2:
+	CALL	NEWLINE
+NEWLINE:
+	CALL	PC_CR
+	CALL	PC_LF
+	RET
+
+PRTSTR:
+	LD	A,(HL)
+	INC	HL
+	CP	'$'
+	RET	Z
+	CALL	COUT
+	JR	PRTSTR
+
+;
+;__COUT_______________________________________________________________________
+;
+;	OUTPUT CHARACTER FROM A
+;_____________________________________________________________________________
+;
+COUT:
+	; SAVE ALL INCOMING REGISTERS
+	PUSH	AF
+	PUSH	BC
+	PUSH	DE
+	PUSH	HL
+;
+	; OUTPUT CHARACTER TO CONSOLE VIA HBIOS
+	LD	E,A							; OUTPUT CHAR TO E
+	LD	C,CIO_CONSOLE		; CONSOLE UNIT TO C
+	LD	B,BF_CIOOUT			; HBIOS FUNC: OUTPUT CHAR
+	CALL	HBIOS_SYS			; HBIOS OUTPUTS CHARACTER
+;
+	; RESTORE ALL REGISTERS
+	POP	HL
+	POP	DE
+	POP	BC
+	POP	AF
+	RET
+;
+;__CIN________________________________________________________________________
+;
+;	INPUT CHARACTER TO A
+;_____________________________________________________________________________
+;
+CIN:
+	; SAVE INCOMING REGISTERS (AF IS OUTPUT)
+	PUSH	BC
+	PUSH	DE
+	PUSH	HL
+;
+	; INPUT CHARACTER FROM CONSOLE VIA HBIOS
+	LD	C,CIO_CONSOLE	; CONSOLE UNIT TO C
+	LD	B,BF_CIOIN		; HBIOS FUNC: INPUT CHAR
+	CALL	HBIOS_SYS		; HBIOS READS CHARACTER
+	LD	A,E						; MOVE CHARACTER TO A FOR RETURN
+;
+	; RESTORE REGISTERS (AF IS OUTPUT)
+	POP	HL
+	POP	DE
+	POP	BC
+	RET
+;
+;__CST________________________________________________________________________
+;
+;	RETURN INPUT STATUS IN A (0 = NO CHAR, !=0 CHAR WAITING)
+;_____________________________________________________________________________
+;
+CST:
+	; SAVE INCOMING REGISTERS (AF IS OUTPUT)
+	PUSH	BC
+	PUSH	DE
+	PUSH	HL
+;
+	; GET CONSOLE INPUT STATUS VIA HBIOS
+	LD	C,CIO_CONSOLE		; CONSOLE UNIT TO C
+	LD	B,BF_CIOIST			; HBIOS FUNC: INPUT STATUS
+	CALL	HBIOS_SYS			; HBIOS RETURNS STATUS IN A
+;
+	; RESTORE REGISTERS (AF IS OUTPUT)
+	POP	HL
+	POP	DE
+	POP	BC
+	RET
+;
+
+
+;
+;__ISHEX______________________________________________________________________
+;
+;	CHECK BYTE AT (HL) FOR HEX CHAR, RET Z IF SO, ELSE NZ
+;_____________________________________________________________________________
+;
+ISHEX:
+	LD	A,(HL)			; CHAR TO AS
+	CP	'0'					; < '0'?
+	JR	C,ISHEX1		; YES, NOT 0-9, CHECK A-F
+	CP	'9' + 1			; > '9'
+	JR	NC,ISHEX1		; YES, NOT 0-9, CHECK A-F
+	XOR	A						; MUST BE 0-9, SET ZF
+	RET							; AND DONE
+ISHEX1:
+	CP	'A'					; < 'A'?
+	JR	C,ISHEX2		; YES, NOT A-F, FAIL
+	CP	'F' + 1			; > 'F'
+	JR	NC,ISHEX2		; YES, NOT A-F, FAIL
+	XOR	A						; MUST BE A-F, SET ZF
+	RET							; AND DONE
+ISHEX2:
+	OR	$FF					; CLEAR ZF
+	RET							; AND DONE
+;
+;__HEXBYTE____________________________________________________________________
+;
+;	GET ONE BYTE OF HEX DATA FROM BUFFER IN HL, RETURN IN A
+;_____________________________________________________________________________
+;
+HEXBYTE:
+	LD	C,0					; INIT WORKING VALUE
+HEXBYTE1:
+	CALL	ISHEX			; DO WE HAVE A HEX CHAR?
+	JR	NZ,HEXBYTE3	; IF NOT, WE ARE DONE
+	LD	B,4					; SHIFT WORKING VALUE (C := C * 16)
+HEXBYTE2:
+	SLA	C						; SHIFT ONE BIT
+	RET	C						; RETURN W/ CF SET INDICATING OVERFLOW ERROR
+	DJNZ	HEXBYTE2	; LOOP FOR 4 BITS
+	CALL	NIBL			; CONVERT HEX CHAR TO BINARY VALUE IN A & INC HL
+	OR	C						; COMBINE WITH WORKING VALUE
+	LD	C,A					; AND PUT BACK IN WORKING VALUE
+	JR	HEXBYTE1		; DO ANOTHER CHARACTER
+HEXBYTE3:
+	LD	A,C					; WORKING VALUE TO A
+	OR	A						; CLEAR CARRY
+	RET		
+
+;
+;__NIBL_______________________________________________________________________
+;
+;	GET ONE BYTE OF HEX DATA FROM BUFFER IN HL, RETURN IN A
+;_____________________________________________________________________________
+;
+NIBL:
+	LD	A,(HL)		; GET K B. DATA
+	INC	HL				; INC KB POINTER
+	CP	40H				; TEST FOR ALPHA
+	JR	NC,ALPH
+	AND	0FH				; GET THE BITS
+	RET
+ALPH:
+	AND	0FH				; GET THE BITS
+	ADD	A,09H			; MAKE IT HEX A-F
+	RET
+
+
+;
+;===============================================================================
+; END ROUTINES THAT ARE LIFTED FROM  DBGMON
+;===============================================================================
+;
+
+
+
+
+;
+;===============================================================================
+; ERROR RESPONCES
+;===============================================================================
+;
+
+ERROOR:						; REQUESTED DEV OUT OF RANGE (SYNTAX)
+	CALL	NEWLINE
+	LD		A, 'R'
+	CALL	COUT	
+	LD 		HL,TARGET_CON
+	LD    A,(HL)
+	CALL	PRTHEX
+
+
+	LD		A, ':'
+	CALL	COUT
+	LD		A, 'M'
+	CALL	COUT
+	LD 		HL,CIODEV_MAX
+	LD    A,(HL)
+	CALL	PRTHEX
+
+	LD	HL,MSGOOR
+	JR	ERROR
+ERRHEXRD:					; COMMAND HEX READ ERROR (SYNTAX)
+	LD	HL,MSGHEXRD
+	JR	ERROR
+ERRUSE:						; COMMAND USAGE ERROR (SYNTAX)
+	LD	HL,MSGUSE
+	JR	ERROR
+ERRPRM:						; COMMAND PARAMETER ERROR (SYNTAX)
+	LD	HL,MSGPRM
+	JR	ERROR
+ERROR:						; PRINT ERROR STRING AND RETURN ERROR SIGNAL
+	CALL	NEWLINE		; PRINT NEWLINE
+	CALL	PRTSTR		; PRINT ERROR STRING
+	OR	$FF					; SIGNAL ERROR
+	RET							; DONE
+
+;===============================================================================
+; STORAGE SECTION
+;===============================================================================
+;
+
+; CHAR DEV COUNT 
+CIODEV_CNT	.DB	$0
+CIODEV_MAX	.DB	$0
+
+;TALK LOOP DATA, DEFAULT TO LOOPBACK
+USER_CON		.DB $80
+TARGET_CON	.DB $80
+
+; PING PONG POINTERS
+RF_DEV			.DB 0
+WT_DEV			.DB 0
+
+; TARGET CHARACTER DEVICE DATA
+TGT_DEV:
+	.DB	0		; HBIOS CHAR NUM
+	.DB	0		; C: DEVICE ATTRIBUTES
+	.DB	0		; D: DEVICE TYPE
+	.DB	0		; E: DEVICE NUMBER
+	.DB	0		; H: DEVICE MODE
+	.DB	0		; L: DEVICE I/O BASE ADDRESS
+
+; STRING LITERALS 
+MSGUSE			.TEXT	"USAGE: HTALK <CIO_DEV_ID>$"
+MSGPRM			.TEXT	"PARAMETER ERROR$"
+MSGOOR			.TEXT	"CIO VAL TOO LARGE$"
+MSGHEXRD		.TEXT	"HEX READ ERR$"
+MSGTALKING	.TEXT	"CONNECTING TO CHAR:$"
+
+
+DEV_STR_TBL:
+	.TEXT "CHAR:$"
+	.TEXT "ATTR:$"
+	.TEXT "TYPE:$"
+	.TEXT "NUMB:$"
+	.TEXT "MODE:$"
+	.TEXT "ADDR:$"
+
+STR_DEVS_FOUND	.TEXT "NUM CHAR DEVICES FOUND - $"
+STR_EXITMSG	.TEXT "HTALK DONE$"
+STR_BANNER	.TEXT	"HTALK V1.0 (CTRL-C TO EXIT)$"
+STR_HBIOS	.TEXT "HBIOS DETECTED$"
+STR_BIOERR	.TEXT	"*** UNKNOWN BIOS	-	BAILING OUT ***$"
+	
+STKSAV	.DW	0		; STACK POINTER SAVED AT START
+	.FILL	STKSIZ,0	; STACK
+STACK	.EQU	$		; STACK TOP
+;
+	.END

Source/Apps/Makefile

@@ -1,6 +1,6 @@
 OBJECTS = sysgen.com syscopy.com assign.com format.com talk.com \
 	mode.com rtc.com timer.com rtchb.com
-SUBDIRS = XM FDU FAT Tune Test ZMP ZMD Dev VGM cpuspd Survey
+SUBDIRS = HTalk XM FDU FAT Tune Test ZMP ZMD Dev VGM cpuspd Survey
 DEST = ../../Binary/Apps
 TOOLS =../../Tools
 

Source/Apps/assign.asm

@@ -32,6 +32,7 @@
 ;                    Use CPM3 BDOS direct BIOS call to get DRVTBL adr
 ;   2023-06-19 [WBW] Update for revised DIODEVICE API
 ;   2023-09-19 [WBW] Added CHUSB & CHSD device support
+;   2023-10-13 [WBW] Fixed DPH creation to select correct DPB
 ;_______________________________________________________________________________
 ;
 ; ToDo:
@@ -665,10 +666,10 @@ makdphwbw:	; determine appropriate dpb (WBW mode, unit number in A)
 	jr	makdph0		; jump ahead
 makdph00:	
 	ld	e,6		; assume floppy
-	cp	$10		; floppy?
+	cp	$01		; floppy?
 	jr	z,makdph0	; yes, jump ahead
 	ld	e,3		; assume ram floppy
-	cp	$20		; ram floppy?
+	cp	$02		; ram floppy?
 	jr	z,makdph0	; yes, jump ahead
 	ld	e,4		; everything else is assumed to be hard disk
 	jr	makdph0		; yes, jump ahead
@@ -1935,13 +1936,13 @@ stack	.equ	$		; stack top
 ; Messages
 ;
 indent	.db	"   ",0
-msgban1	.db	"ASSIGN v1.7 for RomWBW CP/M ",0
+msgban1	.db	"ASSIGN v1.8 for RomWBW CP/M ",0
 msg22	.db	"2.2",0
 msg3	.db	"3",0
-msbban2	.db	", 19-Sep-2023",0
+msbban2	.db	", 13-Oct-2023",0
 msghb	.db	" (HBIOS Mode)",0
 msgub	.db	" (UBIOS Mode)",0
-msgban3	.db	"Copyright 2021, Wayne Warthen, GNU GPL v3",0
+msgban3	.db	"Copyright 2023, Wayne Warthen, GNU GPL v3",0
 msguse	.db	"Usage: ASSIGN D:[=[{D:|<device>[<unitnum>]:[<slicenum>]}]][,...]",13,10
 	.db	"  ex. ASSIGN           (display all active assignments)",13,10
 	.db	"      ASSIGN /?        (display version and usage)",13,10

Source/Build.cmd

@@ -8,7 +8,7 @@ call BuildShared || exit /b
 call BuildImages || exit /b
 call BuildROM %* || exit /b
 call BuildZRC || exit /b
-call BuildZZRC || exit /b
+call BuildZZRCC || exit /b
 
 if "%1" == "dist" (
   call Clean || exit /b

Source/BuildZZRC.cmd

@@ -1,4 +0,0 @@
-@echo off
-setlocal
-
-pushd ZZRC && call Build || exit /b & popd

Source/BuildZZRCC.cmd

@@ -0,0 +1,4 @@
+@echo off
+setlocal
+
+pushd ZZRCC && call Build || exit /b & popd

Source/CPM3/biosldr.z80

@@ -346,8 +346,7 @@ read:
 	ld	b,17h			; HBIOS DEVICE function
 	rst	08			; Do it, D=device type
 	ld	a,d			; put in accum
-	and	0F0h			; isolate high bits
-	cp	10h			; floppy?
+	cp	01h			; floppy?
 	jr	nz,read2		; if not, do LBA i/o
 	
 	; Floppy I/O

Source/Clean.cmd

@@ -22,4 +22,4 @@ pushd Prop && call Clean & popd
 pushd RomDsk && call Clean & popd
 pushd Doc && call Clean & popd
 pushd ZRC && call Clean & popd
-pushd ZZRC && call Clean & popd
+pushd ZZRCC && call Clean & popd

Source/Doc/Applications.md

@@ -52,6 +52,7 @@ found:
 | FAT         | No       | Yes        | Yes      |
 | TUNE        | No       | Yes        | Yes      |
 | WDATE       | No       | Yes        | Yes      |
+| HTALK       | No       | Yes        | Yes      |
 
 `\clearpage`{=latex}
 
@@ -628,9 +629,9 @@ shown on your console.  The `TALK` application does this.
 `TALK` operates at the operating system level (not HBIOS).
 
 The parameter to `TALK` refers to logical CP/M serial devices.  Upon
-execution all characters types at the console will be sent to the
+execution all characters typed at the console will be sent to the
 device specified and all characters received by the specified device
-will be echoes on the console.
+will be echoed on the console.
 
 Press Control+Z on the console to terminate the application.
 
@@ -646,6 +647,36 @@ provided in the RomWBW distribution.
 
 `\clearpage`{=latex}
 
+# HTALK
+
+`HTALK` is a variation of the `TALK` utility, but it works directly
+against HBIOS Character Units.
+
+## Syntax
+
+`HTALK COMn:`
+
+## Usage
+
+`HTALK` operates at the HBIOS level.
+
+The parameter to `TALK` refers to a HBIOS character unit.  Upon
+execution all characters typed at the console will be sent to the
+device specified and all characters received by the specified device
+will be echoed on the console.
+
+Press Control+Z on the console to terminate the application.
+
+## Notes
+
+
+## Etymology
+
+The `TALK` command was created and donated to RomWBW by Tom Plano.  It
+is an original product designed specifically for RomWBW.
+
+`\clearpage`{=latex}
+
 # RTC
 
 Many RomWBW systems provide real time clock hardware.  The RTC

Source/Doc/UserGuide.md

@@ -1609,7 +1609,7 @@ filesystem partition and any CP/M filesystem slices that don't fit.  You
 will get "no disk" errors if you attempt to access a slice past the 
 end of the physical hard disk.
 
-**WARNING**:Your hard disk may be too small to contain the full 64
+**WARNING**: Your hard disk may be too small to contain the full 64
 CP/M filesystem slices.  The true number of CP/M filesystem slices that
 will fit on your specific physical hard disk can be calculated as
 described in [Hard Disk Capacity].
@@ -1625,12 +1625,20 @@ them using `CLRDIR` first.
 
 A great way to maintain your own data on a hard disk is to put this
 data in slices beyond the first 6.  By doing so, you can always
-"reimage" your drive with the combo image without overlaying the data
+"re-image" your drive with the combo image without overlaying the data
 stored in the slices beyond the first 6.  Just be very careful to use
 the same combo image layout (hd512 or hd1k) as you used originally.
 Also remember to calculate the maximum number of slices your hard disk
 will support and do not exceed this number.
 
+**WARNING**: The combo disk image includes a partition table at the 
+start of the image.  If you re-image drive with the combo image, you 
+will overwrite this partition table.  This is fine as long as you don't 
+make any changes to the partition table.  If you manually customize the 
+partition table (using `FDISK80` or other partition management 
+software), those changes will be lost if you re-image your disk with a 
+new combo disk image.
+
 #### Custom Hard Disk Image
 
 If you want to use specific slices in a specific order, you can easily
@@ -1640,8 +1648,9 @@ For hard disks, each .img file represents a single slice (CP/M
 filesystem).  Since a hard disk can contain many slices, you can just 
 concatenate the slices (.img files) together to create your desired hard
 disk image.  For example, if you want to create a hard disk image that 
-has slices for CP/M 2.2, CP/M 3, and WordStar in the hd512 format, you would use 
-the command line of your modern computer to create the final image:
+has slices for CP/M 2.2, CP/M 3, and WordStar in the hd512 format, you 
+would use the command line of your modern computer to create the final 
+image:
 
 Windows:
 
@@ -2363,6 +2372,53 @@ You can also contact Phillip for detailed information on the Z180
 implementation of FreeRTOS for RomWBW.
 [feilipu](https://github.com/feilipu)
 
+## Fuzix
+
+Fuzix is a Unix-ish operating system for small systems.  It is the work 
+of Alan Cox and is hosted on GitHub at
+<https://github.com/EtchedPixels/FUZIX>. Fuzix itself is a stand-alone 
+operating system, but it frequently utilizes RomWBW to boot and launch 
+on RomWBW-supported platforms.
+
+For those Fuzix platforms that leverage RomWBW for startup, you will
+program your ROM with the normal RomWBW ROM -- there
+is no Fuzix-specific ROM.  A Fuzix disk image for your system is then
+written to your disk media.  After booting your system via the normal
+RomWBW ROM, you start Fuzix simply by choosing the disk device
+containing the Fuzix image at the RomWBW Loader prompt.
+
+To create a Fuzix disk image:
+
+* Locate and download the Fuzix disk image for your system from
+  <https://www.fuzix.org/>.
+
+* Remove the 1KB header from the image file.  The Fuzix disk images
+  are built to run under an emulator that requires a 1KB prefix.  You
+  must remove this prefix before writing the image to your physical
+  disk media.  Unix dd is the easiest way to do this:
+  
+  `dd bs=1024 skip=1 if=sc126-0.3.ide of=sc126-0.3.trimmed`
+
+* Write the trimmed image to your disk media.  This can also be
+  done with dd or with Win32DiskImager under Windows.
+
+To boot into Fuzix:
+
+* Power-up or reset your system.  RomWBW should load normally
+  and bring you to the RomWBW Boot Loader prompt.
+
+* Change your baud rate to 38,400.  This can be done from the
+  RomWBW Boot Loader prompt with the following command:
+
+  `I 0 38400`
+
+  You will also need to change your terminal baud rate at this time.
+
+* At the `bootdev:` prompt, enter `hda1`.  Fuzix should load and
+  you will be prompted for a date/time.
+
+* At the `login:` prompt, enter `root`.  No password is required.
+
 # Custom Applications
 
 The operation of the RomWBW hosted operating systems is enhanced through
@@ -2604,6 +2660,166 @@ SAMPLE2.TXT ==> 4:/SAMPLE2.TXT ... [OK]
     2 File(s) Copied
 ```
 
+# Real Time Clock
+
+RomWBW supports a variety of real time clock hardware.  If your
+system has this hardware, then it will be able to maintain the
+current date and time even while your system is turned off.
+Additionally, depending on the operating system being used, you may be
+able to utilize date/time stamping of files.
+
+You can determine if your system has a real time clock present (and
+functioning) by looking at the boot messages.  Here is an example of
+a boot message reflecting the detection of a valid real time clock
+module:
+
+`DSRTC: MODE=STD IO=0x8A Thu 2023-10-19 14:07:11 CHARGE=ON`
+
+This example is from a DSRTC clock module.  You may have a different
+one, but it will always display the current date/time.
+
+In some cases, your real time clock will support charging of the
+battery or super-capacitor while the system has power.  The status of
+this charging is displayed.
+
+If the date/time of your RTC needs to be updated, you will need to do
+this with one of the utilities described below.  There is no ability to
+update the date/time of the RTC in the RomWBW Boot Loader or Monitor.
+
+## Date/Time Utilities
+
+RomwWBW includes two utilities for displaying or setting the date/time
+stored by the RTC.  They are both a bit different and are briefly
+described below.
+
+### WDATE Utility
+
+The `WDATE` utility (contributed by Kevin Boone) is an application
+that will display and/or update the current date/time.  Its operation is
+described in $doc_apps$.  This utility works with any of the supported
+RomWBW RTC hardware.  Here is an example of displaying and updating the
+date/time with this utility:
+
+```
+A>wdate
+Thursday 19 October 14:14:43 2023
+
+A>wdate 23 10 19 14 24 30
+
+A>wdate
+Thursday 19 October 14:24:34 2023
+
+```
+
+Note that `WDATE` does not have anything to do with date/time stamping
+of files.  It merely displays and sets the real time clock value.
+
+### RTC Utility
+
+Like `WDATE`, the `RTC` utility (contributed by Andrew Lynch) will let
+you display and set the current date/time.  However, this utility only
+works with the DSRTC hardware (DS1302 chip).  It is a "direct to
+hardware application".  Its operation is described in $doc_apps$.  Here
+is an example of displaying and updatting the date/time with this
+utility:
+
+```
+A>rtc
+Start RTC Program
+RomWBW HBIOS, Mark 4 RTC Latch Port 0x8A
+
+RTC: Version 1.9
+Commands: E)xit T)ime st(A)rt S)et R)aw L)oop C)harge N)ocharge D)elay I)nit G)et P)ut B)oot W)arm-start H)elp
+
+RTC>t
+Current time: 23-10-19 14:30:25-05
+
+RTC>i
+Init date/time.
+
+YEAR:23
+MONTH:10
+DATE:19
+HOURS:14
+MINUTES:31
+SECONDS:00
+DAY:05
+```
+
+The `RTC` utility is also capable of turning the charging feature of
+the DS1320 chip on or off.  Here is an example of turning if off and
+back on:
+
+```
+
+A>rtc
+Start RTC Program
+RomWBW HBIOS, Mark 4 RTC Latch Port 0x8A
+
+
+RTC: Version 1.9
+Commands: E)xit T)ime st(A)rt S)et R)aw L)oop C)harge N)ocharge D)elay I)nit G)et P)ut B)oot W)arm-start H)elp
+
+RTC>n
+Trickle charger disabled.
+
+RTC>c
+Trickle charger enabled.
+```
+
+Do **not** enable charging unless you are sure that your system
+supports this.  If your RTC is being powered by a normal battery, it
+would be dangerous to enable charging.
+
+## Date/Time File Stamping
+
+If an RTC is available in your system, then most operating systems
+can use it to date/time stamp files.  This just means recording the
+date/time of file creation, update, and or access in the directory.
+This capability is available in all of the RomWBW operating system
+except the original DRI CP/M 2.2.
+
+In some cases (such as ZSDOS), you must load an RSX (memory resident
+utility) to enable date/time stamping of files.  Additionally, you
+will need to initialize the directory.  The procedure varies in each
+operation system, so you must review the associated documentation.
+
+The date/time stamping mechanisms for each operating system are
+generally not compatible.  If you initialize a directory for a type
+of stamping, you should be careful not to manipulate that directory
+with a different operating system with a different date/time stamping
+mechanism.  Doing so may corrupt the directory.
+
+The RomWBW disk images do not have date/time stamping initialized.  This
+is to avoid any chance of directory corruption.
+
+## Timezone
+
+None of the operating systems distributed with RomWBW have any concept
+of timezone.  When files are date/time stamped, the date/time will
+simply be whatever date/time the RTC currently has.
+
+The normal practice is to set the RTC to your local time.  This implies
+that you would need to manually adjust the RTC for daylight savings time
+and/or when you travel to a different time zone.
+
+The date/time stamps of files in directories will also be stored in
+local time.  This includes files stored in a FAT filesystem.  If you
+subsequently view the directory from modern machines (Windows, Linux,
+etc.), the date/time displayed will depend on the behavior of the
+modern system.
+
+For example, Linux assumes that the date/time of files
+is UTC.  So, if you create a file on a FAT filesystem with your RomWBW
+computer and then use Linux to view the directory, the date/time stamps
+will seem "off" by a few hours.
+
+The only alternative you may consider is setting the date/time of your
+RTC to UTC.  Since UTC is consistent across all timezones and daylight
+savings time, your file date/time stamps will also be consistent.  Of
+course, this will mean that your RomWBW computer will display a
+date/time that seems wrong because it is not local time.
+
 # CP/NET Networking
 
 Digital Research created a simple network file sharing system called 
@@ -3301,8 +3517,10 @@ directed to complete a partial flash using the /P command line switch.
 # Related Projects
 
 Outside of the hardware platforms adapted to RomWBW, there are a variety 
-of software projects that either target RomWBW specifically or provide
-a RomWBW-specific variation.
+of projects that either target RomWBW specifically or provide
+a RomWBW-specific variation.  These efforts are greatly appreciated
+and are listed below.  Please contact the author if there are any other
+such projects that are not listed.
 
 ## Z88DK
 
@@ -3338,6 +3556,16 @@ the CP/M OS variants.  This tool (`WDATE`) is included on the RomWBW
 OS disk images.  The project is hosted at
 <https://github.com/kevinboone/wdate-cpm>.
 
+## Assembly Language Programming for the RC2014 Zed
+
+Bruce Hall has written a very nice document that describes how to
+develop assembly language applications on RomWBW.  It begins with the
+setup and configuration of a new RC2014 Zed system running RomWBW.
+It describes not only generic CP/M application development, but also
+RomWBW HBIOS programming and bare metal programming.  The latest copy
+of this document is hosted at
+[http://w8bh.net/Assembly for RC2014Z.pdf](http://w8bh.net/Assembly%20for%20RC2014Z.pdf).
+
 # Acknowledgments
 
 I want to acknowledge that a great deal of the code and inspiration
@@ -4012,7 +4240,7 @@ the RomWBW HBIOS configuration.
 |-------------------|--------------------|
 | ROM Image Files   | RCZ80_zrc.rom      |
 | Console Baud Rate | 115200             |
-| Interrupts        | Mode 1        |
+| Interrupts        | Mode 1             |
 
  - CPU speed is detected at startup if DS1302 RTC is active
    - Otherwise 14.7456 MHz assumed

Source/HBIOS/Bank Layout.txt

@@ -27,7 +27,18 @@ Bank ID		Module		Start	Size
 0x04 - N	ROM Disk Data
 
 
-RAM Bank Layout
+Typical ROM Bank Layout
+
+Bank ID         Usage
+-------         ------
+0x00            Boot Bank (HBIOS image)
+0x01		ROM Loader, Monitor, ROM OSes
+0x02		ROM Applications
+0x03		Reserved
+0x04-0x0F	ROM Disk Banks
+
+
+Typical RAM Bank Layout
 
 Bank ID         Usage
 -------         ------
@@ -39,7 +50,7 @@ Bank ID         Usage
 0x8F            Common
 
 
-ROMless Bank Layout
+Typical ROMless Bank Layout
 
 Bank ID         Usage
 -------         ------

Source/HBIOS/Build.cmd

@@ -219,8 +219,8 @@ call Build RCZ180 nat || exit /b
 call Build RCZ280 ext || exit /b
 call Build RCZ280 nat || exit /b
 call Build RCZ280 zz80mb || exit /b
-call Build RCZ280 zzrc || exit /b
-call Build RCZ280 zzrc_ram || exit /b
+call Build RCZ280 zzrcc || exit /b
+call Build RCZ280 zzrcc_ram || exit /b
 call Build SCZ180 sc126 || exit /b
 call Build SCZ180 sc130 || exit /b
 call Build SCZ180 sc131 || exit /b

Source/HBIOS/Build.sh

@@ -18,8 +18,8 @@ if [ "${ROM_PLATFORM}" == "dist" ] ; then
 	ROM_PLATFORM="RCZ280"; ROM_CONFIG="ext"; bash Build.sh
 	ROM_PLATFORM="RCZ280"; ROM_CONFIG="nat"; bash Build.sh
 	ROM_PLATFORM="RCZ280"; ROM_CONFIG="zz80mb"; bash Build.sh
-	ROM_PLATFORM="RCZ280"; ROM_CONFIG="zzrc"; bash Build.sh
-	ROM_PLATFORM="RCZ280"; ROM_CONFIG="zzrc_ram"; bash Build.sh
+	ROM_PLATFORM="RCZ280"; ROM_CONFIG="zzrcc"; bash Build.sh
+	ROM_PLATFORM="RCZ280"; ROM_CONFIG="zzrcc_ram"; bash Build.sh
 #	ROM_PLATFORM="RCZ80"; ROM_CONFIG="mt"; bash Build.sh
 #	ROM_PLATFORM="RCZ80"; ROM_CONFIG="duart"; bash Build.sh
 	ROM_PLATFORM="RCZ80"; ROM_CONFIG="std"; bash Build.sh

Source/HBIOS/Config/DUO_std.asm

@@ -43,6 +43,5 @@ PCFENABLE	.SET	TRUE		; ENABLE PCF8584 I2C CONTROLLER
 MDFFENABLE	.SET	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
 UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-;UARTCFG	.SET	UARTCFG | SER_RTS
 ;
 ESPENABLE	.SET	TRUE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)

Source/HBIOS/Config/DYNO_std.asm

@@ -34,8 +34,6 @@ Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
 Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 ;
 ASCIENABLE	.SET	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
-;ASCI0CFG	.SET	SER_115200_8N1	; ASCI 0: SERIAL LINE CONFIG
-;ASCI1CFG	.SET	SER_115200_8N1	; ASCI 1: SERIAL LINE CONFIG
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 ;

Source/HBIOS/Config/MBC_std.asm

@@ -47,7 +47,6 @@ ICMENABLE	.SET	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
 PKDENABLE	.SET	TRUE		; ENABLES DSKY NG PKD DRIVER (8259)
 ;
 UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-;UARTCFG	.SET	UARTCFG | SER_RTS
 ;
 ESPENABLE	.SET	TRUE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
 ;

Source/HBIOS/Config/RCZ280_zzrcc.asm

@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   RCBUS Z280 STANDARD CONFIGURATION (NATIVE Z280 MMU W/ LINEAR MEMORY ON ZZRC)
+;   RCBUS Z280 ZZRCC CONFIGURATION
 ;==================================================================================================
 ;
 ; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
@@ -22,7 +22,7 @@
 ; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
 ; DIRECTORIES ABOVE THIS ONE).
 ;
-#DEFINE PLATFORM_NAME "ZZRC", " [", CONFIG, "]"
+#DEFINE PLATFORM_NAME "ZZRCC", " [", CONFIG, "]"
 ;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;
@@ -47,7 +47,7 @@ Z280_IOWAIT	.SET	1		; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 Z280_INTWAIT	.SET	0		; Z280: INT ACK WAIT STATUS (0-3)
 ;
 MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
-MDRAM		.SET	FALSE		; MD: ENABLE RAM DISK
+MDRAM		.SET	TRUE		; MD: ENABLE RAM DISK
 ;
 Z2UENABLE	.SET	TRUE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 Z2UOSC		.SET	(CPUOSC / 8)	; Z2U: OSC FREQUENCY IN MHZ

Source/HBIOS/Config/RCZ280_zzrcc_ram.asm

@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   RCBUS Z280 STANDARD CONFIGURATION (NATIVE Z280 MMU W/ LINEAR MEMORY ON ZZRC)
+;   RCBUS Z280 ZZRCC CONFIGURATION (ROMLESS)
 ;==================================================================================================
 ;
 ; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
@@ -22,7 +22,7 @@
 ; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
 ; DIRECTORIES ABOVE THIS ONE).
 ;
-#DEFINE PLATFORM_NAME "ZZRC", " [", CONFIG, "]"
+#DEFINE PLATFORM_NAME "ZZRCC", " [", CONFIG, "]"
 ;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;

Source/HBIOS/Config/ZETA2_std.asm

@@ -31,7 +31,6 @@ INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 CRTACT		.SET	TRUE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
 UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-;UARTCFG	.SET	UARTCFG | SER_RTS
 UARTSBC		.SET	TRUE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)

Source/HBIOS/Config/ZETA_std.asm

@@ -31,7 +31,6 @@ INTMODE		.SET	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 CRTACT		.SET	TRUE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
 UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-;UARTCFG	.SET	UARTCFG | SER_RTS
 UARTSBC		.SET	TRUE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)

Source/HBIOS/cfg_duo.asm

@@ -30,7 +30,7 @@ CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_UNSUP	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	8000000		; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
@@ -46,15 +46,15 @@ RTCIO		.EQU	$94		; RTC LATCH REGISTER ADR
 KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
 KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
 ;
-CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCENABLE	.EQU	TRUE		; ENABLE ZILOG CTC SUPPORT
 CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
-CTCBASE		.EQU	$B0		; CTC BASE I/O ADDRESS
+CTCBASE		.EQU	$60		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	TRUE		; ENABLE CTC PERIODIC TIMER
 CTCMODE		.EQU	CTCMODE_CTR	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
 CTCPRE		.EQU	256		; PRESCALE CONSTANT (1-256)
 CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
-CTCOSC		.EQU	(4915200/8)	; CTC CLOCK FREQUENCY
+CTCOSC		.EQU	(7372800/8)	; CTC CLOCK FREQUENCY
 ;
 PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
 PCFBASE		.EQU	$56		; PCF8584 BASE I/O ADDRESS
@@ -122,7 +122,7 @@ DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
 UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTOSC		.EQU	7372800		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
@@ -132,7 +132,7 @@ UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
 UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
-UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+UARTDUAL	.EQU	TRUE		; UART: AUTO-DETECT DUAL UART
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
@@ -140,18 +140,18 @@ Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 ;
 ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ;
-SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
 SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO0BASE	.EQU	$B0		; SIO 0: REGISTERS BASE ADR
-SIO0ACLK	.EQU	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BASE	.EQU	$60		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.EQU	(7372800/4)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
-SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO0BCLK	.EQU	(4915200/8)	; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACTCC	.EQU	0		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.EQU	(7372800/4)	; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
-SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCTCC	.EQU	1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
 XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
@@ -229,12 +229,12 @@ SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
-CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHENABLE	.EQU	TRUE		; CH: ENABLE CH375/376 USB SUPPORT
 CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
-CH0BASE		.EQU	$BE		; CH 0: BASE I/O ADDRESS
+CH0BASE		.EQU	$4E		; CH 0: BASE I/O ADDRESS
 CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
 CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
 CH1BASE		.EQU	$FF		; CH 1: BASE I/O ADDRESS
@@ -254,16 +254,16 @@ ESPCONENABLE	.EQU	TRUE		; ESP: ENABLE ESP32 CONSOLE IO DRIVER VIDEO/KBD SUPPORT
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 HDSKTRACE	.EQU	1		; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 ;
-PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOENABLE	.EQU	TRUE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
 PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
-PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+PIO0BASE	.EQU	$68		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$6C		; PIO 1: REGISTERS BASE ADR
 ;
-LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTENABLE	.EQU	TRUE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
 LPTMODE		.EQU	LPTMODE_SPP	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
 LPTCNT		.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
 LPTTRACE	.EQU	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-LPT0BASE	.EQU	$E8		; LPT 0: REGISTERS BASE ADR
+LPT0BASE	.EQU	$48		; LPT 0: REGISTERS BASE ADR
 LPT1BASE	.EQU	$EC		; LPT 1: REGISTERS BASE ADR
 ;
 PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)

Source/HBIOS/cfg_dyno.asm

@@ -30,7 +30,7 @@ CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)

Source/HBIOS/cfg_heath.asm

@@ -30,7 +30,7 @@ CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	7372800		; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)

Source/HBIOS/cfg_master.asm

@@ -27,7 +27,7 @@ CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	8000000		; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)

Source/HBIOS/cfg_mbc.asm

@@ -30,7 +30,7 @@ CPUSPDCAP	.EQU	SPD_HILO	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_LOW		; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	8000000		; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)

Source/HBIOS/cfg_mk4.asm

@@ -30,7 +30,7 @@ CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)

Source/HBIOS/cfg_n8.asm

@@ -30,7 +30,7 @@ CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)

Source/HBIOS/cfg_rcz180.asm

@@ -30,7 +30,7 @@ CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)

Source/HBIOS/cfg_rcz280.asm

@@ -30,7 +30,7 @@ CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	12000000	; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)

Source/HBIOS/cfg_rcz80.asm

@@ -30,7 +30,7 @@ CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	7372800		; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
@@ -46,7 +46,7 @@ RTCIO		.EQU	$C0		; RTC LATCH REGISTER ADR
 KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
 KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
 ;
-CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCENABLE	.EQU	TRUE		; ENABLE ZILOG CTC SUPPORT
 CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER

Source/HBIOS/cfg_rph.asm

@@ -30,7 +30,7 @@ CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)

Source/HBIOS/cfg_s100.asm

@@ -30,7 +30,7 @@ CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_57600_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_57600_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)

Source/HBIOS/cfg_sbc.asm

@@ -30,7 +30,7 @@ CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	8000000		; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)

Source/HBIOS/cfg_scz180.asm

@@ -30,7 +30,7 @@ CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)

Source/HBIOS/cfg_z80retro.asm

@@ -30,7 +30,7 @@ CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	14745600	; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)

Source/HBIOS/cfg_zeta.asm

@@ -30,7 +30,7 @@ CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	20000000	; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)

Source/HBIOS/cfg_zeta2.asm

@@ -30,7 +30,7 @@ CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	8000000		; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)

Source/HBIOS/ctc.asm

@@ -25,7 +25,7 @@ CTC_TIM256CFG	.EQU	%00110111	; CTC TIMER/256 MODE CONFIG
 ; DETERMINE WHICH CHANNEL CAUSED AN INTERRUPT.
 ;==================================================================================================
 ;
-#IF (INTMODE != 2)
+#IF (CTCTIMER & (INTMODE != 2))
 	.ECHO	"*** WARNING: CTC TIMER DISABLED -- INTMODE 2 REQUIRED!!!\n"
 #ENDIF
 ;

Source/HBIOS/hbios.asm

@@ -71,6 +71,8 @@
 ;
 #DEFINE	HBIOS
 ;
+SUPCTS	.EQU	FALSE		; SUPPRESS CTS DURING HBIOS BOOT
+;
 ; MAKE SURE EXACTLY ONE OF ROMBOOT, APPBOOT, IMGBOOT IS DEFINED.
 ;
 MODCNT	.EQU	0
@@ -2300,12 +2302,15 @@ HB_BOOTDLY:
 	JR	C,HB_CONRDY		; IF TOO HIGH, JUST USE FAILSAFE
 	LD	A,BOOTCON		; GET REQUESTED CONSOLE DEV
 	LD	(CB_CONDEV),A		; SAVE IT
+;
 HB_CONRDY:
 ;
+#IF (SUPCTS)
+;
 ; MOST SERIAL PORTS ARE CONFIGURED WITH HARDWARE FLOW CONTROL ENABLED.
-; IF THERE IS A PROBLEM WITH THE RTS SIGNAL, THEN OUTPUT TO THE CONSOLE
+; IF THERE IS A PROBLEM WITH THE CTS SIGNAL, THEN OUTPUT TO THE CONSOLE
 ; WILL BE STALLED WHICH CAN LEAD A USER TO THINK THE SYSTEM IS TOTALLY
-; DEAD WHEN, IN FACT, IT IS JUST WAITING FOR RTS TO BE ASSERTED.  ALSO,
+; DEAD WHEN, IN FACT, IT IS JUST WAITING FOR CTS TO BE ASSERTED.  ALSO,
 ; IF THE USER IS BOOTING TO A CRT DEVICE AND DISCONNECTS THE CONSOLE
 ; SERIAL PORT, THE SYSTEM WILL WAIT FOR RTS AND NEVER BOOT.  SO, HERE
 ; WE SAVE THE ACTIVE CONSOLE CONFIGURATION, THEN TURN OFF HARDWARE
@@ -2315,16 +2320,18 @@ HB_CONRDY:
 	; RETRIEVE THE CONFIG FROM THE CONSOLE PORT
 	LD	B,BF_CIOQUERY		; HBIOS QUERY CIO CONFIG
 	LD	A,(CB_CONDEV)		; GET CONSOLE DEVICE
-	LD	(HB_BOOTCON),A		; SAVE IT FOR LATER
+	LD	(HB_BOOTCONSAV),A	; SAVE IT FOR LATER
 	LD	C,A			; BOOT CONSOLE TO C
 	CALL	HB_DISPATCH		; INTERNAL HBIOS CALL
-	LD	(HB_BOOTCFG),DE		; SAVE CONFIG
+	LD	(HB_CONCFGSAV),DE	; SAVE CONFIG
 	RES	5,D			; CLEAR RTS BIT
 	LD	B,BF_CIOINIT		; HBIOS CIO INIT
 	LD	A,(CB_CONDEV)		; GET CONSOLE DEVICE
 	LD	C,A			; BOOT CONSOLE TO C
 	CALL	HB_DISPATCH		; INTERNAL HBIOS CALL
-
+;
+#ENDIF
+;
 #IF (WBWDEBUG == USEMIO)		; OUTPUT ANY CACHED DEBUG TEXT
 	LD	HL,MIOOUTPTR
 	LD	E,(HL)
@@ -2871,6 +2878,19 @@ HB_FPZ:
 ;
 INITSYS3:
 ;
+#IF (SUPCTS)
+;
+; RESTORE BOOT CONSOLE CONFIGURATION
+;
+	CALL	LDELAY			; ALLOW SERIAL PORT TO FLUSH
+	LD	B,BF_CIOINIT		; HBIOS CIO INIT
+	LD	A,(HB_BOOTCONSAV)	; ORIGINAL BOOT CONSOLE DEVICE
+	LD	C,A			; BOOT CONSOLE TO C
+	LD	DE,(HB_CONCFGSAV)	; SAVED ORIGINAL CONSOLE CFG
+	CALL	HB_DISPATCH		; INTERNAL HBIOS CALL
+;
+#ENDIF
+;
 ; IF WE ARE GOING TO SWITCH CONSOLES, IT IS IMPLEMENTED HERE.  A
 ; MESSAGE IS PRINTED ON THE OLD CONSOLE INDICATING WHERE THE NEW
 ; CONSOLE IS AND THE NEW CONSOLE RECEIVES AN HBIOS BANNER.
@@ -2891,16 +2911,6 @@ INITSYS3:
 	CALL	NZ,WRITESTR		; OUTPUT IF CONSOLE MOVED
 ;
 INITSYS3A:
-;
-; RESTORE BOOT CONSOLE CONFIGURATION
-;
-	CALL	LDELAY			; ALLOW SERIAL PORT TO FLUSH
-	LD	B,BF_CIOINIT		; HBIOS CIO INIT
-	LD	A,(HB_BOOTCON)		; ORIGINAL BOOT CONSOLE DEVICE
-	LD	C,A			; BOOT CONSOLE TO C
-	LD	DE,(HB_BOOTCFG)		; SAVED ORIGINAL CONSOLE CFG
-	CALL	HB_DISPATCH		; INTERNAL HBIOS CALL
-;
 	CALL	PRTSUM			; PRINT UNIT/DEVICE SUMMARY TABLE
 ;
 #IF 0
@@ -7754,6 +7764,11 @@ HB_BOOTCON	.DB	0		; INITIAL BOOT CONSOLE SAVE AREA
 HB_BOOTCFG	.DW	0		; CONSOLE CONFIG SAVE AREA
 HB_NEWCON	.DB	0		; NEW CONSOLE TO SWITCH TO
 ;
+#IF (SUPCTS)
+HB_BOOTCONSAV	.DB	0		; INITIAL BOOT CONSOLE SAVE AREA
+HB_CONCFGSAV	.DW	0		; CONSOLE CONFIG SAVE AREA
+#ENDIF
+;
 HB_HASFP	.DB	0		; NON-ZERO MEANS FP EXISTS
 ;
 HB_WRKBUF	.FILL	512,0		; INTERNAL DISK BUFFER

Source/HBIOS/std.asm

@@ -640,27 +640,26 @@ RAMD_BNKS	.EQU	(BID_RAMDN - BID_RAMD0 + 1)
 ;
 #ENDIF
 ;
-#IF TRUE
-	.ECHO "BID_BUF: " \ .ECHO BID_BUF \ .ECHO "\n"
-	.ECHO "BID_AUX: " \ .ECHO BID_AUX \ .ECHO "\n"
-	.ECHO "BID_BIOS: " \ .ECHO BID_BIOS \ .ECHO "\n"
-	.ECHO "BID_USR: " \ .ECHO BID_USR \ .ECHO "\n"
-	.ECHO "BID_COM: " \ .ECHO BID_COM \ .ECHO "\n"
-
-	.ECHO "BID_BOOT: " \ .ECHO BID_BOOT \ .ECHO "\n"
-	.ECHO "BID_IMG0: " \ .ECHO BID_IMG0 \ .ECHO "\n"
-	.ECHO "BID_IMG1: " \ .ECHO BID_IMG1 \ .ECHO "\n"
-	.ECHO "BID_IMG2: " \ .ECHO BID_IMG2 \ .ECHO "\n"
-
-	.ECHO "BID_ROMD0: " \ .ECHO BID_ROMD0 \ .ECHO "\n"
-	.ECHO "BID_ROMDN: " \ .ECHO BID_ROMDN \ .ECHO "\n"
-	.ECHO "BID_RAMD0: " \ .ECHO BID_RAMD0 \ .ECHO "\n"
-	.ECHO "BID_RAMDN: " \ .ECHO BID_RAMDN \ .ECHO "\n"
-
+#IF FALSE
+	.ECHO "--- RAM/ROM CAPACITY ---\n"
 	.ECHO "BID_ROM0: " \ .ECHO BID_ROM0 \ .ECHO "\n"
 	.ECHO "BID_ROMN: " \ .ECHO BID_ROMN \ .ECHO "\n"
 	.ECHO "BID_RAM0: " \ .ECHO BID_RAM0 \ .ECHO "\n"
 	.ECHO "BID_RAMN: " \ .ECHO BID_RAMN \ .ECHO "\n"
+	.ECHO "--- BANK LAYOUT ---\n"
+	.ECHO "BID_BOOT: " \ .ECHO BID_BOOT \ .ECHO "\n"
+	.ECHO "BID_IMG0: " \ .ECHO BID_IMG0 \ .ECHO "\n"
+	.ECHO "BID_IMG1: " \ .ECHO BID_IMG1 \ .ECHO "\n"
+	.ECHO "BID_IMG2: " \ .ECHO BID_IMG2 \ .ECHO "\n"
+	.ECHO "BID_ROMD0: " \ .ECHO BID_ROMD0 \ .ECHO "\n"
+	.ECHO "BID_ROMDN: " \ .ECHO BID_ROMDN \ .ECHO "\n"
+	.ECHO "BID_BIOS: " \ .ECHO BID_BIOS \ .ECHO "\n"
+	.ECHO "BID_RAMD0: " \ .ECHO BID_RAMD0 \ .ECHO "\n"
+	.ECHO "BID_RAMDN: " \ .ECHO BID_RAMDN \ .ECHO "\n"
+	.ECHO "BID_BUF: " \ .ECHO BID_BUF \ .ECHO "\n"
+	.ECHO "BID_AUX: " \ .ECHO BID_AUX \ .ECHO "\n"
+	.ECHO "BID_USR: " \ .ECHO BID_USR \ .ECHO "\n"
+	.ECHO "BID_COM: " \ .ECHO BID_COM \ .ECHO "\n"
 #ENDIF
 ;
 ; MEMORY LAYOUT
@@ -838,7 +837,7 @@ INT_CTC0A	.EQU	0	; ZILOG CTC 0, CHANNEL A
 INT_CTC0B	.EQU	1	; ZILOG CTC 0, CHANNEL B
 INT_CTC0C	.EQU	2	; ZILOG CTC 0, CHANNEL C
 INT_CTC0D	.EQU	3	; ZILOG CTC 0, CHANNEL D
-;INT_SIO0	.EQU	7	; ZILOG SIO 0, CHANNEL A & B
+INT_SIO0	.EQU	6	; ZILOG SIO 0, CHANNEL A & B
 INT_SIO1	.EQU	8	; ZILOG SIO 1, CHANNEL A & B
 INT_PIO0A	.EQU	9	; ZILOG PIO 0, CHANNEL A
 INT_PIO0B	.EQU	10	; ZILOG PIO 0, CHANNEL B

Source/HBIOS/uart.asm

@@ -52,6 +52,7 @@ UART_EFR		.EQU	2	; LCR=$BF: ENHANCED FEATURE REG (READ/WRITE)
 UART_INTACT		.EQU	7	; INT RCV ACTIVE BIT
 UART_FIFOACT		.EQU	6	; FIFO ACTIVE BIT
 UART_AFCACT		.EQU	5	; AUTO FLOW CONTROL ACTIVE BIT
+UART_CTSBAD		.EQU	4	; CTS STALL DETECTED
 ;
 #IF (PLATFORM == PLT_DUO)
 UARTSBASE		.EQU	$58
@@ -62,7 +63,11 @@ UARTCBASE		.EQU	$80
 UARTMBASE		.EQU	$18
 UART4BASE		.EQU	$C0
 UARTRBASE		.EQU	$A0
+#IF (PLATFORM == PLT_DUO)
+UARTDBASE		.EQU	$70
+#ELSE
 UARTDBASE		.EQU	$80
+#ENDIF
 ;
 #IF (UARTINTS)
 ;
@@ -173,7 +178,19 @@ UART_INITUNIT:
 	LD	A,(HL)			; PUT IN ACCUM
 	INC	(HL)			; INCREMENT IT (FOR NEXT LOOP)
 	LD	(IY),A			; UDPATE UNIT NUM
+;
+	; CHECK FOR CTS STALL (CTS SHOULD BE ASSERTED HERE)
+	BIT	5,(IY+5)		; IS RTS REQUESTED?
+	JR	Z,UART_INITUNIT1	; IF NOT, SKIP CTS CHECK
+	UART_INP(UART_MSR)		; LOAD MODEM STATUS REG
+	BIT	4,A			; CTS
+	JR	NZ,UART_INITUNIT1	; IF CTS HIGH (GOOD), SKIP AHEAD
+;
+	; CTS LOOKS BORKED, SHUT OFF RTS/CTS FLOW CONTROL
+	RES	5,(IY+5)		; CLEAR RTS BIT OF CONFIG MSB
+	SET	UART_CTSBAD,(IY+1)	; RECORD BAD CTS
 ;	
+UART_INITUNIT1:
 	; SET DEFAULT CONFIG
 	LD	DE,-1			; LEAVE CONFIG ALONE
 	JP	UART_INITDEVX		; IMPLEMENT IT AND RETURN
@@ -197,8 +214,21 @@ UART_INIT1:
 	
 	LD	A,(IY+1)		; GET UART TYPE
 	OR	A			; SET FLAGS
-	CALL	NZ,UART_PRTCFG		; PRINT IF NOT ZERO
-
+	JR	Z,UART_INIT2		; SKIP IF ZERO (NOT DETECTED)
+	PUSH	AF			; SAVE TYPE VALUE
+	CALL	UART_PRTCFG		; PRINT IF NOT ZERO
+	POP	AF			; RESTORE TYPE VALUE
+	BIT	UART_CTSBAD,A		; CTS STALL?
+	JR	Z,UART_INIT2		; IF NOT, SKIP AHEAD
+	CALL	NEWLINE			; FORMATTING
+	PRTS("UART$")			; FORMATTING
+	LD	A,(IY)			; DEVICE NUM
+	CALL	PRTDECB			; PRINT DEVICE NUM
+	PRTS(": $")			; FORMATTING
+	LD	DE,UART_STR_BADCTS	; LOAD WARNING MESSAGE
+	CALL	WRITESTR		; ... AND PRINT IT
+;	
+UART_INIT2:
 	POP	BC			; RESTORE LOOP CONTROL
 	INC	C			; NEXT UNIT
 	DJNZ	UART_INIT1		; LOOP TILL DONE
@@ -992,6 +1022,8 @@ UART_STR_16850		.DB	"16850$"
 ;
 UART_PAR_MAP		.DB	"NONENMNS"
 ;
+UART_STR_BADCTS		.DB	"CTS STALL, HARDWARE FLOW CONTROL SUSPENDED$"
+;
 ; WORKING VARIABLES
 ;
 UART_DEV		.DB	0		; DEVICE NUM USED DURING INIT

Source/Images/Common/All/FLASH.DOC

@@ -17,6 +17,11 @@ FLASH4 has been tested and confirmed working on:
 It should work on many other machines that run RomWBW or UNA BIOS.  If you test
 it on another machine please let me know the outcome.
 
+FLASH030 (also included) is a Linux version of the same software. It is
+targetted at my 68030 machine but should be very easy to port to other
+machines. It expects a machine with a larger address space, and thus omits much
+of the bank switching and other tricks required on Z80 platforms.
+
 
 = Introduction =
 

Source/Images/Common/All/SUPERSUB.DOC

@@ -1,4 +1,4 @@
-			SUPERSUB DOCUMENTATION	(revised 09/13/81)
+			SUPERSUB DOCUMENTATION	(revised 09/25/84)
 			----------------------
 
 						09/05/81
@@ -11,6 +11,17 @@ are familiar with that utility and its use.
 
 			------------------
 
+Version 1.3 update:
+
+George Cary has added MP/M capability to version 1.2 of SuperSUB. In
+version 1.3 I fixed a problem that caused SuperSUB to bomb when the
+.SUB file did not end in a 1AH (which is an ascii end-of-file
+character). It was depending on the 1AH to end the file, and ignoring
+the physical end-of-file. Physical end-of-file will now terminate
+properly.			- Jeffrey J. Nonken
+
+			------------------
+
 Version 1.1 update:
 
 Control-character translation has been added.  This facility works
@@ -138,4 +149,4 @@ NOTES
 5) Interactive mode may be aborted by typing control-C as the first
    character of a line.  Also, all normal CP/M editing characters are
    available.
-
+

Source/Images/fd_bp.txt

@@ -22,6 +22,7 @@
 ../../Binary/Apps/syscopy.com 15:
 ../../Binary/Apps/sysgen.com 15:
 ../../Binary/Apps/talk.com 15:
+../../Binary/Apps/htalk.com 15:
 ../../Binary/Apps/tbasic.com 15:
 ../../Binary/Apps/timer.com 15:
 ../../Binary/Apps/tune.com 15:

Source/Images/fd_cpm22.txt

@@ -18,6 +18,7 @@ d_cpm22/ReadMe.txt 0:
 ../../Binary/Apps/syscopy.com 0:
 ../../Binary/Apps/sysgen.com 0:
 ../../Binary/Apps/talk.com 0:
+../../Binary/Apps/htalk.com 0:
 ../../Binary/Apps/tbasic.com 0:
 ../../Binary/Apps/timer.com 0:
 ../../Binary/Apps/tune.com 0:

Source/Images/fd_cpm3.txt

@@ -34,6 +34,7 @@
 ../../Binary/Apps/syscopy.com 0:
 #../../Binary/Apps/sysgen.com 0:
 #../../Binary/Apps/talk.com 0:
+#../../Binary/Apps/htalk.com 0:
 ../../Binary/Apps/tbasic.com 0:
 ../../Binary/Apps/timer.com 0:
 ../../Binary/Apps/tune.com 0:

Source/Images/fd_nzcom.txt

@@ -19,6 +19,7 @@ d_cpm22/u0/XSUB.COM 0:
 ../../Binary/Apps/rtc.com 0:
 ../../Binary/Apps/syscopy.com 0:
 ../../Binary/Apps/talk.com 0:
+../../Binary/Apps/htalk.com 0:
 ../../Binary/Apps/timer.com 0:
 ../../Binary/Apps/xm.com 0:
 #

Source/Images/fd_qpm.txt

@@ -22,6 +22,7 @@ d_cpm22/u0/*.* 0:
 ../../Binary/Apps/syscopy.com 0:
 ../../Binary/Apps/sysgen.com 0:
 ../../Binary/Apps/talk.com 0:
+../../Binary/Apps/htalk.com 0:
 ../../Binary/Apps/tbasic.com 0:
 ../../Binary/Apps/timer.com 0:
 ../../Binary/Apps/tune.com 0:

Source/Images/fd_zpm3.txt

@@ -32,6 +32,7 @@
 ../../Binary/Apps/syscopy.com 15:
 ../../Binary/Apps/sysgen.com 15:
 ../../Binary/Apps/talk.com 15:
+#../../Binary/Apps/htalk.com 15:
 #../../Binary/Apps/tbasic.com 15:
 ../../Binary/Apps/timer.com 15:
 #../../Binary/Apps/tune.com 15:

Source/Images/fd_zsdos.txt

@@ -31,6 +31,7 @@ d_cpm22/u0/XSUB.COM 0:
 ../../Binary/Apps/syscopy.com 0:
 ../../Binary/Apps/sysgen.com 0:
 ../../Binary/Apps/talk.com 0:
+../../Binary/Apps/htalk.com 0:
 ../../Binary/Apps/tbasic.com 0:
 ../../Binary/Apps/timer.com 0:
 ../../Binary/Apps/tune.com 0:

Source/Images/hd_bp.txt

@@ -22,6 +22,7 @@
 ../../Binary/Apps/syscopy.com 15:
 ../../Binary/Apps/sysgen.com 15:
 ../../Binary/Apps/talk.com 15:
+../../Binary/Apps/htalk.com 15:
 ../../Binary/Apps/tbasic.com 15:
 ../../Binary/Apps/timer.com 15:
 ../../Binary/Apps/tune.com 15:

Source/Images/hd_cpm22.txt

@@ -18,6 +18,7 @@ d_cpm22/ReadMe.txt 0:
 ../../Binary/Apps/syscopy.com 0:
 ../../Binary/Apps/sysgen.com 0:
 ../../Binary/Apps/talk.com 0:
+../../Binary/Apps/htalk.com 0:
 ../../Binary/Apps/tbasic.com 0:
 ../../Binary/Apps/timer.com 0:
 ../../Binary/Apps/tune.com 0:

Source/Images/hd_cpm3.txt

@@ -34,6 +34,7 @@
 ../../Binary/Apps/syscopy.com 0:
 #../../Binary/Apps/sysgen.com 0:
 #../../Binary/Apps/talk.com 0:
+../../Binary/Apps/htalk.com 0:
 ../../Binary/Apps/tbasic.com 0:
 ../../Binary/Apps/timer.com 0:
 ../../Binary/Apps/tune.com 0:

Source/Images/hd_nzcom.txt

@@ -35,6 +35,7 @@ d_zsdos/u0/*.* 0:
 ../../Binary/Apps/syscopy.com 0:
 ../../Binary/Apps/sysgen.com 0:
 ../../Binary/Apps/talk.com 0:
+../../Binary/Apps/htalk.com 0:
 ../../Binary/Apps/tbasic.com 0:
 ../../Binary/Apps/timer.com 0:
 ../../Binary/Apps/tune.com 0:

Source/Images/hd_qpm.txt

@@ -22,6 +22,7 @@ d_cpm22/u0/*.* 0:
 ../../Binary/Apps/syscopy.com 0:
 ../../Binary/Apps/sysgen.com 0:
 ../../Binary/Apps/talk.com 0:
+../../Binary/Apps/htalk.com 0:
 ../../Binary/Apps/tbasic.com 0:
 ../../Binary/Apps/timer.com 0:
 ../../Binary/Apps/tune.com 0:

Source/Images/hd_zpm3.txt

@@ -33,6 +33,7 @@
 ../../Binary/Apps/syscopy.com 15:
 ../../Binary/Apps/sysgen.com 15:
 ../../Binary/Apps/talk.com 15:
+../../Binary/Apps/htalk.com 15:
 ../../Binary/Apps/tbasic.com 15:
 ../../Binary/Apps/timer.com 15:
 ../../Binary/Apps/tune.com 15:

Source/Images/hd_zsdos.txt

@@ -31,6 +31,7 @@ d_cpm22/u0/XSUB.COM 0:
 ../../Binary/Apps/syscopy.com 0:
 ../../Binary/Apps/sysgen.com 0:
 ../../Binary/Apps/talk.com 0:
+../../Binary/Apps/htalk.com 0:
 ../../Binary/Apps/tbasic.com 0:
 ../../Binary/Apps/timer.com 0:
 ../../Binary/Apps/tune.com 0:

Source/Makefile

@@ -24,9 +24,9 @@ ifeq ($(UNAME), Linux)
 # uname machine strings for building Propeller
 endif
 
-.PHONY: doc prop shared bp images rom zrc zzrc
+.PHONY: doc prop shared bp images rom zrc zzrcc
 
-all: prop shared images rom zrc zzrc
+all: prop shared images rom zrc zzrcc
 
 doc:
 	$(MAKE) --directory Doc $(ACTION)
@@ -67,8 +67,8 @@ rom:
 zrc:
 	$(MAKE) --directory ZRC $(ACTION)
 
-zzrc:
-	$(MAKE) --directory ZZRC $(ACTION)
+zzrcc:
+	$(MAKE) --directory ZZRCC $(ACTION)
 
 
 clean: ACTION=clean

Source/ZRC/Bank Layout.txt

@@ -0,0 +1,41 @@
+ZRC has no real ROM.  It has a single 2048K RAM chip.  There
+are two startup modes supported by RomWBW.
+
+The normal startup mode treats the first 512KB like ROM and the
+remaining 1536KB as RAM.  The first 512KB (pseudo-ROM) must be preloaded
+by the ZRC CF Loader.  This mode simulates a normal ROM-based RomWBW
+startup.
+
+Bank		Contents	Description
+----		--------	-----------
+0x0		BOOT		Boot Bank (HBIOS image)		+
+0x1		IMG0		ROM Loader, Monitor, ROM OSes	|
+0x2		IMG1		ROM Applications		| Pseudo-ROM
+0x3		IMG2		Reserved			|
+0x4-0xF		ROMD		ROM Disk Banks			+
+0x10		BIOS		HBIOS Bank (operating)
+0x11-0x3B	RAMD		RAM Disk Banks
+0x3C		BUF		OS Buffers (CP/M3)
+0x3D		AUX		Aux Bank (CP/M 3, BPBIOS, etc.)
+0x3E		USR		User Bank (CP/M TPA, etc.)
+0x3F		COM		Common Bank, Upper 32KB
+
+The ROMless startup mode treats the entire 2048KB as RAM.  However, in
+this mode, only the first 512KB of RAM is utilized.  This is because
+the RAM Disk is seeded by the CF Loader which is currently constrained
+to loading 512KB.  The entire 512KB of RAM (less the top 32KB) must be
+preloaded by the ZRC CF Loader.  There will be no ROM disk available
+under RomWBW.  There will be a RAM Disk and it's initial contents will
+be seeded by the image loaded by the CF Loader.
+
+Bank		Contents	Description
+--------	--------	-----------
+0x0		BIOS		HBIOS Bank (operating)
+0x1		IMG0		ROM Loader, Monitor, ROM OSes
+0x2		IMG1		ROM Applications
+0x3		IMG2		Reserved
+0x4-0xB		RAMD		RAM Disk Banks
+0xC		BUF		OS Buffers (CP/M3)
+0xD		AUX		Aux Bank (CP/M 3, BPBIOS, etc.)
+0xE		USR		User Bank (CP/M TPA, etc.)
+0xF		COM		Common Bank, Upper 32KB

Source/ZRC/Build.cmd

@@ -14,8 +14,8 @@ goto :eof
 :build_zrc
 
 srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x0 0x100 zrc_cfldr.bin -binary -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x100 0x200 zrc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x0 0x200 zrc_cfldr.bin -binary -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x1B8 0x200 zrc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
 srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
 srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ80_zrc.rom -binary -offset 0x24000 -o temp.dat -binary
 move temp.dat ..\..\Binary\hd1k_zrc_prefix.dat
@@ -27,8 +27,8 @@ goto :eof
 :build_zrc_ram
 
 srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x0 0x100 zrc_cfldr.bin -binary -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x100 0x200 zrc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x0 0x200 zrc_cfldr.bin -binary -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x1B8 0x200 zrc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
 srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
 srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ80_zrc_ram.rom -binary -offset 0x24000 -o temp.dat -binary
 move temp.dat ..\..\Binary\hd1k_zrc_ram_prefix.dat

Source/ZRC/Makefile

@@ -27,16 +27,16 @@ DIFFPATH = $(DIFFTO)/Binary
 
 $(HD1KZRCPREFIX):
 	srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
-	srec_cat temp.dat -binary -exclude 0x0 0x100 zrc_cfldr.bin -binary -o temp.dat -binary
-	srec_cat temp.dat -binary -exclude 0x100 0x200 zrc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x0 0x200 zrc_cfldr.bin -binary -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x1B8 0x200 zrc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
 	srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
 	srec_cat temp.dat -binary -exclude 0x24000 0xA4000 $(ZRCROM) -binary -offset 0x24000 -o temp.dat -binary
 	mv temp.dat $@
 
 $(HD1KZRCRAMPREFIX):
 	srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
-	srec_cat temp.dat -binary -exclude 0x0 0x100 zrc_cfldr.bin -binary -o temp.dat -binary
-	srec_cat temp.dat -binary -exclude 0x100 0x200 zrc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x0 0x200 zrc_cfldr.bin -binary -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x1B8 0x200 zrc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
 	srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
 	srec_cat temp.dat -binary -exclude 0x24000 0xA4000 $(ZRCRAMROM) -binary -offset 0x24000 -o temp.dat -binary
 	mv temp.dat $@

Source/ZRC/ZRC Disk Layout.txt

@@ -1,24 +1,25 @@
-CF Boot Loader: Sector 0 (bytes 0-255)
-RomWBW Partition Table: Sector 0 (bytes 256-511)
-ZRC Monitor: Sectors 0xF8-0xFF (bytes 0x1F000-0x1FFFF)
-RomWBW: Sectors 0x120-0x51F (bytes 0x24000-0xA3FFF)
-Start of Slices (0x1E partition): Sector 0x800 (byte 0x100000)
+ZRC Disk Prefix Layout
+======================
 
-Start	Length	Description
--------	-------	---------------------------
-0x00000 0x00100	CF Boot Loader
-0x00100 0x00100	RomWBW Partition Table
-0x00200 0x1EE00	Filler
-0x1F000 0x01000	ZRC Monitor
-0x20000 0x04000	Filler
-0x24000 0x80000	RomWBW
-0xA4000 0x5C000	Filler
-0x100000: Start of slices (partition 0x1E)
+---- Bytes ----   --- Sectors ---
+Start   Length    Start   Length    Description
+------- -------   ------- -------   ---------------------------
+0x00000 0x001BE   0       1         CF Boot Loader
+0x001B8 0x00048                     RomWBW Partition Table
+0x00200 0x1EE00   1       247       Unused
+0x1F000 0x01000   248     8         ZRC Monitor v0.7
+0x20000 0x04000   256     32        Unused
+0x24000 0x80000   288     1024      RomWBW
+0xA4000 0x5C000   1312    736       Unused  
+0x100000          2048              Start of slices (partition 0x1E)
 
 Notes
 -----
 
 - At startup CPLD ROM is mapped to Z80 CPU address space 0x0000-0x003F, CPU begins execution at 0x0000
-- CPLD ROM (CF bootstrap mode) reads CF Boot Loader (256B) from start of CF (MBR) to 0xB000 and runs it
+- CPLD ROM (CF bootstrap mode) reads CF Boot Loader (512B) from start of CF (MBR) to 0xB000 and runs it
 - CF Boot Loader reads ZRC Monitor (4KB) from sectors 0xF8-0xFF of CF to 0xB400 and runs it
-- ZRC Monitor reads 512KB (RomWBW) from sectors 0x120-0x51F of CF into first 512KB of RAM
+- ZRC Monitor reads 512KB (RomWBW) from sectors 0x120-0x51F of CF into first 512KB of physical RAM
+- ZRC Monitor maps first 32KB of physical RAM to first 32KB of CPU RAM and starts execution at 0x0000
+
+-- WBW 3:30 PM 10/12/2023

Source/ZZRC/Bank Layout.txt

@@ -1,32 +0,0 @@
-ZZRCC has no real ROM.  It has a single 512K RAM chip.  The first
-256K of the RAM chip is loaded from the CF card.  This 256K is
-treated like ROM by RomWBW.  The remainder of the RAM (256K) is
-treated like RAM by RomWBW.
-
-Because of the memory constraints, notice that there is no RAM Disk,
-only a ROM disk.  If you perform a ROM boot to an OS, the A: drive
-will be the ROM disk and will not be writable.  Booting a ROM OS
-on this system is not typical since the system has a CF card by
-definition.
-
-Bank	ROM			RAM			RAM
-----	---			---			---
-0	HBIOS (IMG)					
-1	ROMLDR+MON+CP/M2+ZSYS				
-2	FTH+BAS+TBAS+PLAY+USR				
-3	RESERVED					
-4	ROMDISK						
-5	ROMDISK						
-6	ROMDISK						
-7	ROMDISK						
-							
-8				BUF (CPM3)		BUF (CPM3)
-9				BUF (CPM3)		BUF (CPM3)
-A				BUF (CPM3)		BUF (CPM3)
-B				BUF (CPM3)		BUF (CPM3)
-C				AUX (CPM3)		TPA (CPM3)
-D				HBIOS (EXEC)		HBIOS (EXEC)
-E				TPA-LO			OS (CPM3)
-F				COMMON (TPA-HI)		COMMON (TPA-HI)
-
---WBW 6:40 PM 2/16/2022

Source/ZZRC/Build.cmd

@@ -1,41 +0,0 @@
-:: @echo off
-setlocal
-
-set ROMFILE=..\..\Binary\RCZ280_zzrc.rom
-set ROMSIZE=262144
-
-set TOOLS=../../Tools
-
-set PATH=%TOOLS%\srecord;%PATH%
-
-if exist ..\..\Binary\RCZ280_zzrc.rom call :build_zzrc
-
-if exist ..\..\Binary\RCZ280_zzrc_ram.rom call :build_zzrc_ram
-
-goto :eof
-
-:build_zzrc
-
-srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x0 0x100 zzrc_cfldr.bin -binary -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x100 0x200 zzrc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ280_zzrc.rom -binary -offset 0x24000 -o temp.dat -binary
-move temp.dat ..\..\Binary\hd1k_zzrc_prefix.dat
-
-copy /b ..\..\Binary\hd1k_zzrc_prefix.dat + ..\..\Binary\hd1k_cpm22.img + ..\..\Binary\hd1k_zsdos.img + ..\..\Binary\hd1k_nzcom.img + ..\..\Binary\hd1k_cpm3.img + ..\..\Binary\hd1k_zpm3.img + ..\..\Binary\hd1k_ws4.img ..\..\Binary\hd1k_zzrc_combo.img || exit /b
-
-goto :eof
-
-:build_zzrc_ram
-
-srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x0 0x100 zzrc_cfldr.bin -binary -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x100 0x200 zzrc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ280_zzrc_ram.rom -binary -offset 0x24000 -o temp.dat -binary
-move temp.dat ..\..\Binary\hd1k_zzrc_ram_prefix.dat
-
-copy /b ..\..\Binary\hd1k_zzrc_ram_prefix.dat + ..\..\Binary\hd1k_cpm22.img + ..\..\Binary\hd1k_zsdos.img + ..\..\Binary\hd1k_nzcom.img + ..\..\Binary\hd1k_cpm3.img + ..\..\Binary\hd1k_zpm3.img + ..\..\Binary\hd1k_ws4.img ..\..\Binary\hd1k_zzrc_ram_combo.img || exit /b
-
-goto :eof

Source/ZZRC/Makefile

@@ -1,48 +0,0 @@
-HD1KZZRCPREFIX = hd1k_zzrc_prefix.dat
-HD1KZZRCCOMBOIMG = hd1k_zzrc_combo.img
-HD1KZZRCRAMPREFIX = hd1k_zzrc_ram_prefix.dat
-HD1KZZRCRAMCOMBOIMG = hd1k_zzrc_ram_combo.img
-ZZRCROM = ../../Binary/RCZ280_zzrc.rom
-ZZRCRAMROM = ../../Binary/RCZ280_zzrc_ram.rom
-HD1KIMGS = ../../Binary/hd1k_cpm22.img ../../Binary/hd1k_zsdos.img ../../Binary/hd1k_nzcom.img \
-	../../Binary/hd1k_cpm3.img ../../Binary/hd1k_zpm3.img ../../Binary/hd1k_ws4.img
-
-OBJECTS :=
-
-ifneq ($(wildcard $(ZZRCROM)),)
-	OBJECTS += $(HD1KZZRCPREFIX) $(HD1KZZRCCOMBOIMG)
-endif
-
-ifneq ($(wildcard $(ZZRCRAMROM)),)
-	OBJECTS += $(HD1KZZRCRAMPREFIX) $(HD1KZZRCRAMCOMBOIMG)
-endif
-
-DEST=../../Binary
-
-TOOLS = ../../Tools
-
-include $(TOOLS)/Makefile.inc
-
-DIFFPATH = $(DIFFTO)/Binary
-
-$(HD1KZZRCPREFIX):
-	srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
-	srec_cat temp.dat -binary -exclude 0x0 0x100 zzrc_cfldr.bin -binary -o temp.dat -binary
-	srec_cat temp.dat -binary -exclude 0x100 0x200 zzrc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
-	srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
-	srec_cat temp.dat -binary -exclude 0x24000 0xA4000 $(ZZRCROM) -binary -offset 0x24000 -o temp.dat -binary
-	mv temp.dat $@
-
-$(HD1KZZRCRAMPREFIX):
-	srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
-	srec_cat temp.dat -binary -exclude 0x0 0x100 zzrc_cfldr.bin -binary -o temp.dat -binary
-	srec_cat temp.dat -binary -exclude 0x100 0x200 zzrc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
-	srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
-	srec_cat temp.dat -binary -exclude 0x24000 0xA4000 $(ZZRCRAMROM) -binary -offset 0x24000 -o temp.dat -binary
-	mv temp.dat $@
-
-$(HD1KZZRCCOMBOIMG): $(HD1KZZRCPREFIX) $(HD1KIMGS)
-	cat $^ > $@
-
-$(HD1KZZRCRAMCOMBOIMG): $(HD1KZZRCRAMPREFIX) $(HD1KIMGS)
-	cat $^ > $@

Source/ZZRC/ZZRC Disk Layout.txt

@@ -1,31 +0,0 @@
-Start   Length  Sector  Count   Description
-------- ------- ------- ------- -----------------------------------------
-0x00000 0x00100 0x000   0x001   CF Boot Loader (first 256 bytes)
-0x00100 0x00100 0x000   0x001   RomWBW Partition Table (last 256 bytes)
-0x00200 0x1EE00 0x001   0x0F7   Filler
-0x1F000 0x01000 0x0F8   0x008   ZZRCC Monitor / RomWBW Loader
-0x20000 0x04000 0x100   0x020   Filler
-0x24000 0x40000 0x120   0x200   RomWBW (256KB ROM image)
-0x64000 0x9C000 0x320   0x4E0   Filler
-0x100000        0x800           Slices
-
-Notes
------
-
-- At startup CPLD ROM is mapped to Z80 CPU address space 0x0000-0x003F, CPU begins execution at 0x0000
-- CPLD ROM (CF bootstrap mode) loads CF Boot Loader (256B) to 0xB000 and runs it
-- CF Boot Loader loads ZZRCC Monitor to 0xB000 and runs it starting at address 0xB400
-- Monitor (Boot RomWBW) loads RomWBW ROM image to first 8 banks of RAM, then runs it starting at address 0x000
-
-Possible alternative layout:
-
-Start   Length  Sector  Count   Description
-------- ------- ------- ------- -----------------------------------------
-0x00000 0x00100 0       1       CF Boot Loader (first 256 bytes)
-0x00100 0x00100 0       1       RomWBW Partition Table (last 256 bytes)
-0x00200 0x01000 0x001   0x008   ZZRCC Monitor / RomWBW Loader
-0x01200 0x7EE00 0x009   0x3F7   Filler
-0x80000 0x40000 0x400   0x200   RomWBW (256KB ROM image)
-0xC0000 0x40000 0x600   0x200   Filler
-0x100000        0x800           Slices (0x1E partition start)
-