Added Support for Les Bird's RCBus Graphics/Sound/Joystick Module

- ROM Applications document has been consolidated into the Applications document
- Martin has done a significant overhaul of the Applications document

Co-Authored-By: MartinR <174514335+martinr-uk@users.noreply.github.com>

Binary/Apps/Test/inttest.doc

@@ -0,0 +1,44 @@
+INTTEST
+=======
+
+RomWBW includes an API allowing applications to "hook" interrupts.
+The `INTTEST` utility allows you to test this functionality.
+
+
+** Syntax **
+
+`INTTEST`
+
+
+** Usage **
+
+`INTTEST` is an interactive application.  At startup, it will display
+a list of the interrupt vector slots in your system along with the
+current vector address for each of them.
+
+It then prompts you to enter the slot number (in hex) of a vector to
+hook.  After entering this, the application will watch the hooked
+vector and countdown from 0xFF to 0x00 as interrupts are noted.
+
+When the counter reaches 0x00, the interrupt is unhooked and the
+application terminates.  The application can also be terminated by
+pressing <esc>.
+
+
+** Notes **
+
+If your system is running without interrupts active, the application
+will terminate immediately.
+
+All slots have vectors even if the corresponding interrupt is not
+doing anything.  In this case, the vector is pointing to the "bad
+interrupt" handler.
+
+If you hook a vector that is not receiving any interrupts, the
+down-counter will not do anything.
+
+
+** Etymology* *
+
+The `INTTEST` command is an original product and the source code is
+provided in the RomWBW distribution.

Doc/ChangeLog.txt

@@ -21,6 +21,11 @@ Version 3.5
 - M?R: Update Timer app to display output in decimal
 - WBW: Preliminary support for S100 FPGA Z80 platform
 - WBW: Added simple serial (SSER) driver
+- WBW: Added preliminary support for S100 FPGA Z80 SD Cards
+- M?R: Consolidated ROM Applications document into the Applications document
+- M?R: Reviewed and substantially improved the Applications document
+- WBW: Added support for DS1305 RTC on S100 FPGA Z80
+- WBW: Added support for Les Bird's RCBus Graphics/Sound/Joystick module
 
 Version 3.4
 -----------

ReadMe.md

@@ -3,7 +3,7 @@
 **RomWBW ReadMe** \
 Version 3.5 \
 Wayne Warthen  ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \
-30 Jun 2024
+08 Jul 2024
 
 # Overview
 
@@ -124,8 +124,6 @@ Documentation for RomWBW includes:
   Guide](https://github.com/wwarthen/RomWBW/raw/master/Doc/RomWBW%20System%20Guide.pdf)
 - [RomWBW
   Applications](https://github.com/wwarthen/RomWBW/raw/master/Doc/RomWBW%20Applications.pdf)
-- [RomWBW ROM
-  Applications](https://github.com/wwarthen/RomWBW/raw/master/Doc/RomWBW%20ROM%20Applications.pdf)
 - [RomWBW
   Errata](https://github.com/wwarthen/RomWBW/raw/master/Doc/RomWBW%20Errata.pdf)
 

ReadMe.txt

@@ -1,6 +1,6 @@
 RomWBW ReadMe
 Wayne Warthen (wwarthen@gmail.com)
-30 Jun 2024
+08 Jul 2024
 
 
 
@@ -122,7 +122,6 @@ Documentation for RomWBW includes:
 -   RomWBW User Guide
 -   RomWBW System Guide
 -   RomWBW Applications
--   RomWBW ROM Applications
 -   RomWBW Errata
 
 

Source/Apps/Test/inttest/Build.cmd

@@ -8,4 +8,5 @@ set TASMTABS=%TOOLS%\tasm32
 tasm -t180 -g3 -fFF inttest.asm inttest.com inttest.lst || exit /b
 
 copy /Y inttest.com ..\..\..\..\Binary\Apps\Test\ || exit /b
+copy /Y inttest.doc ..\..\..\..\Binary\Apps\Test\ || exit /b
 

Source/Apps/Test/inttest/Makefile

@@ -1,5 +1,7 @@
 OBJECTS = inttest.com
+DOCS = inttest.doc
 DEST = ../../../../Binary/Apps/Test
+DOCDEST = ../../../../Binary/Apps/Test
 TOOLS =../../../../Tools
 
 USETASM=1

Source/Apps/Test/inttest/inttest.doc

@@ -0,0 +1,44 @@
+INTTEST
+=======
+
+RomWBW includes an API allowing applications to "hook" interrupts.
+The `INTTEST` utility allows you to test this functionality.
+
+
+** Syntax **
+
+`INTTEST`
+
+
+** Usage **
+
+`INTTEST` is an interactive application.  At startup, it will display
+a list of the interrupt vector slots in your system along with the
+current vector address for each of them.
+
+It then prompts you to enter the slot number (in hex) of a vector to
+hook.  After entering this, the application will watch the hooked
+vector and countdown from 0xFF to 0x00 as interrupts are noted.
+
+When the counter reaches 0x00, the interrupt is unhooked and the
+application terminates.  The application can also be terminated by
+pressing <esc>.
+
+
+** Notes **
+
+If your system is running without interrupts active, the application
+will terminate immediately.
+
+All slots have vectors even if the corresponding interrupt is not
+doing anything.  In this case, the vector is pointing to the "bad
+interrupt" handler.
+
+If you hook a vector that is not receiving any interrupts, the
+down-counter will not do anything.
+
+
+** Etymology* *
+
+The `INTTEST` command is an original product and the source code is
+provided in the RomWBW distribution.

Source/Apps/Tune/tune.asm

@@ -49,6 +49,7 @@
 ;   2024-02-23 [WBW] Include ACR value in config table
 ;   2024-04-16 [WBW] Add support for NABU AY-3-8910
 ;   2024-05-10 [WBW] Hack to avoid corrupting bits 6&7 of PSG R7 for NABU!
+;   2024-07-08 [WBW] Add support for Les Bird's Graphics, Sound, Joystick
 ;_______________________________________________________________________________
 ;
 ; ToDo:
@@ -580,6 +581,9 @@ CFGSIZ	.EQU	$ - CFGTBL
 ;
 	.DB	$07,	$33,	$32,	$32,	$FF,	$FF,	$FF	; RCZ80 W/ LINC SOUND MODULE
 	.DW	HWSTR_LINC
+;
+	.DB	$07,	$A1,	$A0,	$A1,	$FF,	$FF,	$FF	; RCZ80 W/ RCGSJ
+	.DW	HWSTR_RCGSJ
 ;
 	.DB	$08,	$68,	$60,	$68,	$C0,	$FF,	$FF	; RCZ180 W/ RC SOUND MODULE (EB)
 	.DW	HWSTR_RCEB
@@ -604,6 +608,9 @@ CFGSIZ	.EQU	$ - CFGTBL
 ;
 	.DB	$09,	$33,	$32,	$32,	$FF,	$FF,	$FF	; EZZ80 W/ LINC SOUND MODULE
 	.DW	HWSTR_LINC
+;
+	.DB	$07,	$A1,	$A0,	$A1,	$FF,	$FF,	$FF	; EZZ80 W/ RCGSJ
+	.DW	HWSTR_RCGSJ
 ;
 	.DB	$0A,	$68,	$60,	$68,	$C0,	$FF,	$FF	; SCZ180 W/ RC SOUND MODULE (EB)
 	.DW	HWSTR_RCEB
@@ -666,7 +673,7 @@ TMP		.DB	0	; work around use of undocumented Z80
 HBIOSMD		.DB	0	; NON-ZERO IF USING HBIOS SOUND DRIVER, ZERO OTHERWISE
 OCTAVEADJ	.DB	0	; AMOUNT TO ADJUST OCTAVE UP OR DOWN
 
-MSGBAN		.DB	"Tune Player for RomWBW v3.8, 10-May-2024",0
+MSGBAN		.DB	"Tune Player for RomWBW v3.9, 8-Jul-2024",0
 MSGUSE		.DB	"Copyright (C) 2024, Wayne Warthen, GNU GPL v3",13,10
 		.DB	"PTxPlayer Copyright (C) 2004-2007 S.V.Bulba",13,10
 		.DB	"MYMPlay by Marq/Lieves!Tuore",13,10,13,10
@@ -689,6 +696,7 @@ HWSTR_N8	.DB	"N8 Onboard Sound",0
 HWSTR_RCEB	.DB	"RCBus Sound Module (EB)",0
 HWSTR_RCEB6	.DB	"RCBus Sound Module (EBv6)",0
 HWSTR_RCMF	.DB	"RCBus Sound Module (MF)",0
+HWSTR_RCGSJ	.DB	"RCBus Graphics, Sound Joystick",0
 HWSTR_LINC	.DB	"Z50 LiNC Sound Module",0
 HWSTR_MBC	.DB	"NHYODYNE Sound Module",0
 HWSTR_DUO	.DB	"DUODYNE Sound Module",0

Source/Doc/Basic.h

@@ -11,7 +11,6 @@ $define{doc_orgurl}{www.retrobrewcomputers.org}$
 $define{doc_user}{[RomWBW User Guide]($doc_root$/RomWBW User Guide.pdf)}$
 $define{doc_sys}{[RomWBW System Guide]($doc_root$/RomWBW System Guide.pdf)}$
 $define{doc_apps}{[RomWBW Applications]($doc_root$/RomWBW Applications.pdf)}$
-$define{doc_romapps}{[RomWBW ROM Applications]($doc_root$/RomWBW ROM Applications.pdf)}$
 $define{doc_catalog}{[RomWBW Disk Catalog]($doc_root$/RomWBW Disk Catalog.pdf)}$
 $define{doc_errata}{[RomWBW Errata]($doc_root$/RomWBW Errata.pdf)}$
 

Source/Doc/Build.cmd

@@ -15,7 +15,6 @@ call :GenDoc ReadMe
 call :GenDoc UserGuide
 call :GenDoc SystemGuide
 call :GenDoc Applications
-call :GenDoc ROM_Applications
 call :GenDoc Catalog
 call :GenDoc Errata
 
@@ -24,7 +23,6 @@ if exist ReadMe.txt copy ReadMe.txt ..\..\ReadMe.txt || exit /b
 if exist UserGuide.pdf copy UserGuide.pdf "..\..\Doc\RomWBW User Guide.pdf" || exit /b
 if exist SystemGuide.pdf copy SystemGuide.pdf "..\..\Doc\RomWBW System Guide.pdf" || exit /b
 if exist Applications.pdf copy Applications.pdf "..\..\Doc\RomWBW Applications.pdf" || exit /b
-if exist ROM_Applications.pdf copy ROM_Applications.pdf "..\..\Doc\RomWBW ROM Applications.pdf" || exit /b
 if exist Catalog.pdf copy Catalog.pdf "..\..\Doc\RomWBW Disk Catalog.pdf" || exit /b
 if exist Errata.pdf copy Errata.pdf "..\..\Doc\RomWBW Errata.pdf" || exit /b
 

Source/Doc/Makefile

@@ -3,7 +3,7 @@
 # and available on commandline for this build to work!!!
 # Typically "sudo apt install gpp pandoc texlive-latex-extra texlive-luatex texlive-fonts-extra fonts-roboto"
 #
-OBJECTS = ReadMe.gfm ReadMe.txt UserGuide.pdf SystemGuide.pdf Applications.pdf ROM_Applications.pdf Catalog.pdf Errata.pdf
+OBJECTS = ReadMe.gfm ReadMe.txt UserGuide.pdf SystemGuide.pdf Applications.pdf Catalog.pdf Errata.pdf
 # DEST = ../../Doc
 TOOLS = ../../Tools
 OTHERS = *.tmp
@@ -36,6 +36,5 @@ deploy :
 	cp UserGuide.pdf         "../../Doc/RomWBW User Guide.pdf"
 	cp SystemGuide.pdf       "../../Doc/RomWBW System Guide.pdf"
 	cp Applications.pdf      "../../Doc/RomWBW Applications.pdf"
-	cp ROM_Applications.pdf  "../../Doc/RomWBW ROM Applications.pdf"
 	cp Catalog.pdf           "../../Doc/RomWBW Disk Catalog.pdf"
 	cp Errata.pdf             "../../Doc/RomWBW Errata.pdf"

Source/Doc/ROM_Applications.md

@@ -1,635 +0,0 @@
-$define{doc_title}{ROM Applications}$
-$define{doc_author}{Phillip Summers}$
-$define{doc_authmail}{}$
-$include{"Book.h"}$
-
-# Summary
-
-RomWBW includes a small selection of built in utilities and
-programming languages.
-
-`\clearpage`{=latex}
-
-# RomWBW Monitor
-
-The Monitor program is a low level utility that can be used 
-for testing and programming. It allows programs to be entered,
-memory to be examined, and input/output devices to be read or
-written to.
-
-It's key advantage is that is available at boot up. 
-
-Its key disadvantages are that code cannot be entered in assembly 
-language and there is no ability to save to memory devices.
-
-The available memory area for programming is `0200-EDFFh`.
-The following areas are reserved:
-
-Memory Area | Function
-------------|-----------------------------------
-`0000-00FFh`| Jump and restart (RST) vectors
-`0100-01FFh`| HBIOS configuration block
-`EE00-FDFFh`| MONITOR
-`FE00-FFFFh`| HBIOS proxy
-
-Commands can be entered at the command prompt `>` 
-Automatic case conversion takes place on command entry and all 
-arguments are expected to be in hex format.
-
-The current memory bank in low memory is displayed before the prompt i.e.:
-
-`8E>`
-
-The Monitor allows access to all memory locations but ROM and
-Flash memory cannot be written to. Memory outside the normal
-address range can be accessed using the B command. The first
-256 bytes `0000-01FF` is critical for the HBIOS operation.
-Changing banks may make this information inaccessible.
-
-Refer to the RomWBW Architecture manual for details memory banking.
-
-A quick guide to using the Monitor program follows:
-
-## ? - Displays a summary of available commands.
-
-```
-Monitor Commands (all values in hex):
-B                    - Boot system
-D xxxx [yyyy]        - Dump memory from xxxx to yyyy
-F xxxx yyyy zz       - Fill memory from xxxx to yyyy with zz
-H                    - Halt system
-I xxxx               - Input from port xxxx
-K                    - Keyboard echo
-L                    - Load Intel hex data
-M xxxx yyyy zzzz     - Move memory block xxxx-yyyy to zzzz
-O xxxx yy            - Output value yy to port xxxx
-P xxxx               - Program RAM at address xxxx
-R xxxx [[yy] [zzzz]] - Run code at address xxxx
-                       Pass yy and zzzz to register A and BC
-T xxxx	             - X-modem transfer to memory location xxxx
-S xx                 - Set bank to xx
-X                    - Exit monitor
-```
-
-## Cold Boot
-
-B - Performs a cold boot of the ROMWBW system. A complete
-re-initialization of the system is performed and the system
-returns to the Boot Loader prompt.
-
-## Dump Memory
-
-D xxxx [yyyy] - Dump memory from hex location xxxx to yyyy
-on the screen as lines of 16 hexadecimal bytes with their
-ASCII equivalents (if within a set range, else a '.' is
-printed). If the end address is omitted then 256 bytes is
-displayed. 
-
-A good tool to see where code is located, check
-for version id, obtain details for chip configurations and
-execution paths.
-
-Examples: `D 100 1FF`
-
-```
-0100: 10 0B 01 5A 33 45 4E 56 01 00 00 2A 06 00 F9 11  ...Z3ENV...*..ù.
-0110: DE 38 37 ED 52 4D 44 0B 6B 62 13 36 00 ED B0 21  Þ87íRMD.kb.6.í°!
-0120: 7D 32 E5 21 80 00 4E 23 06 00 09 36 00 21 81 00  }2å!..N#...6.!..
-0130: E5 CD 6C 1F C1 C1 E5 2A C9 8C E5 CD 45 05 E5 CD  åÍl.ÁÁå*É.åÍE.åÍ
-0140: 59 1F C3 00 00 C3 AE 01 C3 51 04 C3 4C 02 C3 57  Y.Ã..î.ÃQ.ÃL.ÃW
-0150: 02 C3 64 02 C3 75 02 C3 88 02 C3 B2 03 C3 0D 04  .Ãd.Ãu.Ã..ò.Ã..
-0160: C3 19 04 C3 22 04 C3 2A 04 C3 35 04 C3 40 04 C3  Ã..Ã".Ã*.Ã5.Ã@.Ã
-0170: 48 04 C3 50 04 C3 50 04 C3 50 04 C3 8F 02 C3 93  H.ÃP.ÃP.ÃP.Ã..Ã.
-0180: 02 C3 94 02 C3 95 02 C3 85 04 C3 C7 04 C3 D1 01  .Ã..Ã..Ã..ÃÇ.ÃÑ.
-0190: C3 48 02 C3 E7 04 C3 56 03 C3 D0 01 C3 D0 01 C3  ÃH.Ãç.ÃV.ÃÐ.ÃÐ.Ã
-01A0: D0 01 C3 D0 01 C3 D0 01 C3 D0 01 01 02 01 CD 6B  Ð.ÃÐ.ÃÐ.ÃÐ....Ík
-01B0: 04 54 68 69 73 20 66 75 6E 63 74 69 6F 6E 20 6E  .This function n
-01C0: 6F 74 20 73 75 70 70 6F 72 74 65 64 2E 0D 0A 00  ot supported....
-01D0: C9 3E FF 32 3C 00 3A 5D 00 FE 20 28 14 D6 30 32  É>ÿ2<.:].þ (.Ö02
-01E0: AB 01 32 AD 01 3A 5E 00 FE 20 28 05 D6 30 32 AC  «.2­.:^.þ (.Ö02¬
-01F0: 01 C5 01 F0 F8 CF E5 26 00 0E 0A CD 39 02 7D 3C  .Å.ðøÏå&...Í9.}<
-```
-
-## Fill Memory
-
-F xxxx yyyy zz - Fill memory from hex xxxx to yyyy with
-a single value of zz over the full range. The Dump command
-can be used to confirm that the fill completed as expected. A
-good way to zero out memory areas before writing machine data
-for debug purposes.
-
-## Halt System
-
-H - Halt system. A Z80 HALT instruction is executed. The
-system remains in the halt state until the system is
-physically rebooted. Interrupts will not restart the
-system. On systems that support a HALT status LED, the
-LED will be illuminated.
-
-## Input from port
-
-I xxxx - Input data from port xxxx and display to the screen.
-This command is used to read values from hardware I/O ports
-and display the contents in hexadecimal. 
-
-## Keyboard Echo
-
-K - Echo any key-presses from the terminal. Press 'ESC' key
-to quit. This facility provides that any key stroke sent to
-the computer will be echoed back to the terminal. File down
-loads will be echoed as well while this facility is ‘on’.
-
-## Load Hex format file into memory
-
-L - Load a Intel Hex format file via the terminal program.
-The load address is defined in the hex file of the
-assembled code.
-
-The terminal emulator program should be configured to
-give a delay at the end of each line to allow the monitor
-enough time to parse the line and move the data to memory.
-
-Keep in mind that this will be a transient unless the
-system support battery backed memory. Saving to memory drive 
-is not supported.
-
-## Move memory
-
-M xxxx yyyy zzzz - Move hex memory block xxxx to yyyy to
-memory starting at hex location zzzz. Care should be taken
-to insure that there is enough memory at the destination so
-that code does not get over-written or memory wrapped around.
-
-## Output to port
-
-O xxxx yy - Output data byte xx to port xxxx. This command is
-used to send hexadecimal values to hardware I/O ports to
-verify their operation and is the companion to the I operation.
-Use clip leaded LEDs to confirm the data written.
-
-## Program memory location
-
-P xxxx - Program memory location xxxx. This routine will
-allow you to program a hexadecimal value 'into memory starting
-at location xxxx. Press 'Enter' on a blank line to
-return to the Monitor prompt.
-
-The limitation around programming memory is that it must be 
-entered in hexadecimal. An alternative is to use the L command
-to load a program that has been assembled to a hex file on the
-remote computer.
-
-An excellent online resource for looking up opcodes for entry
-can be found here: [https://clrhome.org/table](https://clrhome.org/table)
-
-## Run program
-
-R xxxx [[yy] [zzzz]] - Run program at location xxxx. If optional
-arguments yy and zzzz are entered they are loaded into the
-A and BC register respectively. The return address of the
-Monitor is saved on the stack so the program can return
-to the monitor. On return to the monitor, the contents of
-the A, HL, DE and BC registers are displayed.
-
-## Set bank
-
-S xx - Change the bank in memory to xx. Memory addresses
-0000-7FFF (i.e. bottom 32k) are affected. Because the
-interrupt vectors are stored in the bottom page of this
-range, this function is disable when interrupt mode 1 is
-being used (IM1). Interrupt mode 2 is not affected as the
-associated jump vectors are stored in high memory. 
-
-Changing the bank also impacts the restart vectors (RST),
-so executing code that call the HBIOS using the RST 08
-assembly code will not work.
-
-The monitor stack resides in high memory and is not affected
-but any code that changes the stack to low memory will be
-affected.
-
-### Bank codes and descriptions
-
-TYPE | DESCRIPTION        |BANK| DETAILS
------|--------------------|----|---------------------
-RAM  | COMMON BANK        | 9F | 1024K RAM SYSTEM
-RAM  | USER BANK          | 9E | 1024K RAM SYSTEM
-RAM  | BIOS BANK          | 9D | 1024K RAM SYSTEM
-RAM  | AUX BANK           | 9C | 1024K RAM SYSTEM
-RAM  | OS BUFFERS END     | 9B | 1024K RAM SYSTEM
-RAM  | OS BUFFERS START   | 98 | 1024K RAM SYSTEM
-RAM  | RAM DRIVE END	  | 97 | 1024K RAM SYSTEM
-RAM  | COMMON BANK        | 8F | 512K RAM SYSTEM
-RAM  | USER BANK          | 8E | 512K RAM SYSTEM
-RAM  | BIOS BANK          | 8D | 512K RAM SYSTEM
-RAM  | AUX BANK           | 8C | 512K RAM SYSTEM
-RAM  | OS BUFFERS         | 8B | 512K RAM SYSTEM
-RAM  | OS BUFFERS         | 8A | 512K RAM SYSTEM
-RAM  | OS BUFFERS         | 89 | 512K RAM SYSTEM
-RAM  | OS BUFFERS         | 88 | 512K RAM SYSTEM
-RAM  | RAM DRIVE END	  | 87 | 512K RAM SYSTEM
-RAM  | RAM DRIVE START    | 80 |
-ROM  | BOOT BANK          | 00 | COLD START & HBIOS
-ROM  | LOADER & IMAGES    | 01 | MONITOR, FORTH
-ROM  | ROM IMAGES CONTD.  | 02 | BASIC, ETC
-ROM  | FAT FILESYSTEM     | 03 | UNA ONLY, ELSE UNUSED
-ROM  | ROM DRIVE START    | 04 |
-ROM  | ROM DRIVE END      | 0F | 512K ROM SYSTEM
-ROM  | ROM DRIVE END      | 1F | 1024K ROM SYSTEM
-
-## X-modem transfer
-
-T xxxx - Receive an X-modem file transfer and load it into
-memory starting at location xxxx. 
-
-128 byte blocks and checksum mode is the only supported 
-protocol.
-
-If the monitor is assembled with the DSKY functionality,
-this feature will be exclude due to space limitations.
-
-
-## NOTES:
-
-The RTC utility on the CP/M ROM disk provides facilities
-to manipulate the Real Time Clock non-volatile Memory. 
-Use the C or Z option from the Boot Loader to load CP/M 
-and then run RTC to see the options list.
-
-# FORTH
-
-CamelForth is the version of Forth included as part of the boot
-ROM in ROMWBW. It has been converted from the Z80 CP/M version
-published here [www.camelforth.com/page.php?5](www.camelforth.com/page.php?5). The author is Brad
-Rodriguez who is a prolific Forth enthusiast, whose work can be
-found here: [www.bradrodriguez/papers/index.html](www.bradrodriguez/papers/index.html)
-
-For those are who are not familiar with Forth, I recommend the
-wikipedia article [en.wikipedia.org/wiki/Forth_(programming_language](en.wikipedia.org/wiki/Forth_(programming_language))
-and the Forth Interest Group website [www.forth.org](www.forth.org)
-
-## Important things to know
-
-Forth is case sensitive.
-
-To exit back to the boot loader type ***bye***
-
-To get a list of available words type ***WORDS***
-
-To reset Forth to its initial state type ***COLD***
-
-Most of the code you find on the internet will not run unless modified or additional Forth
-words are added to the dictionary.
-
-This implementation does not support loading or saving of programs. All programs
-need to be typed in. Additionally, screen editing and code blocks are not supported.
-
-## Structure of Forth source files
-
-File          | Description
---------------|-----------------------------
-camel80.azm   | Code Primitives
- camel80d.azm | CPU Dependencies
- camel80h.azm | High Level words
- camel80r.azm | ROMWBW additions
-glosshi.txt   | Glossary of high level words
-glosslo.txt   | Glossary of low level words
-glossr.txt    | Glossary of ROMWBW additions
-
-## ROMWBW Additions
-
-Extensions and changes to this implementation compared to the original distribution are:
-
-The source code has been converted from Z80mr assembler to Hector Peraza's zsm.
-
-An additional file camel80r.azm has been added for including additional words to 
-the dictionary at build time. However, as currently configured there is very little space
-allocated for addition words. Exceeding the allocated ROM space will generate an error
-message when building.
-
-James Bowman's double precision words have been added from his RC2014 version:
-[https://github.com/jamesbowman/camelforth-z80](https://github.com/jamesbowman/camelforth-z80)
-
-Word    | Syntax                     | Description
---------|----------------------------|---------------------------------
-D+	| d1 d2 -- d1+d2             | Add double numbers
-2>R	| d --                       | 2 to R
-2R>	| d --                       | fetch 2 from R
-M*/	| d1 n2 u3 --  d=(d1*n2)/u3  | double precision mult. div
-SVC	| hl de bc n -- hl de bc af  | Execute a ROMWBW function
-P!	| n p --                     | Write a byte to a I/O port
-P@      | p -- n                     | Read a byte from and I/O port
-
-# BASIC
-
-For those who are not familiar with BASIC, it stands for Beginners All purpose Symbolic
-Instruction Code. 
-
-ROMWBW contains two versions of ROM BASIC, a full implementation and a "tiny" BASIC.
-
-The full implementation is a version of Microsoft BASIC from the NASCOM Computer.
-
-A comprehensive instruction manual is available in the Doc\\Contrib directory.
-
-## ROMWBW specific features
-
-- Sound
-- Graphics
-- Terminal Support
-
-## ROMWBW unsupported features
-
-- This ROM-hosted implementation does not support cassette or disk
-  access for loading and saving programs.
-
-# TastyBASIC
-
-TastyBASIC offers a minimal implementation of BASIC that is only 2304 bytes in size. 
-It originates from Li-Chen Wang's Palo Alto Tiny BASIC from around 1976. It's small size suited the tiny memory capacities of the time. This implementation is by Dimitri Theulings and his
-original source can be found here [https://github.com/dimitrit/tastybasic](https://github.com/dimitrit/tastybasic)
-
-## Features / Limitations
-
-- This ROM-hosted implementation does not support disk access for
-  loading and saving programs.
-- Integer arithmetic, numbers -32767 to 32767
-- Singles letter variables A-Z
-- 1-dimensional array support
-- Strings are not supported
-
-## Direct Commands
-
-- `LIST`,`RUN`, `NEW`, `CLEAR`, `BYE`
-
-## Statements
-
-- `LET`, `IF`, `GOTO`, `GOSUB RETURN`, `REM`, `FOR TO NEXT STEP`, `INPUT`, `PRINT`, `POKE`, `END`
-
-## Functions
-
-- `PEEK`, `RND`, `ABS`, `USR`, `SIZE`
-
-## Operators
-
-- `>=`, `#`, `>`, `=`, `<=`, `<`
-
-- Operator precedence is supported.
-
-Type ***BYE*** to return to the monitor.
-
-# Play a Game
-
-## 2048
-
-2048 is a puzzle game that can be both mindless and challenging. It
-appears deceptively simple but failure can creep up on you suddenly.
-
-It requires an ANSI/VT-100 compatible colour terminal to play.
-
-2048 is like a sliding puzzle game except the puzzle tiles are 
-numbers instead of pictures. Instead of moving a single tile all 
-tiles are moved simultaneously in the same direction. Where two 
-tiles of the same number collide, they are reduced to one tile with
-the combined value. After every move a new tile is added with
-a starting value of 2. 
-
-The goal is to create a tile of 2048 before all tile locations are
-occupied. Reaching the highest points score, which is the sum of all
-the tiles is a secondary goal. The game will automatically end when 
-there are no more possible moves.
-
-Play consists of entering a direction to move. Directions can be entered
-using any of three different keyboard direction sets.
-
-```
-Direction | Keys
-----------|----------
-Up        | w ^E 8
-Down      | s ^X 2
-Left      | a ^S 4
-Right     | d ^D 6
-```
-The puzzle board is a 4x4 grid. At start, the grid will be populated
-with two 2 tiles. An example game sequence is shown below with new
-tiles to the game shown in brackets.
-
-```
-Start             Move 1 - Up       Move 2 - Left     Move 3 - Left
-+---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+
-|   |   |   |(2)| |   |   |   | 4 | | 4 |   |   |   | | 4 |   |   |   |
-+---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+
-|   |   |   |   | |   |   |   |   | |   |   |   |(4)| | 4 |   |   |   |
-+---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+
-|   |   |   |(2)| |   |   |   |   | |   |   |   |   | |   |   |   |   |
-+---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+
-|   |   |   |   | |   |   |(2)|   | | 2 |   |   |   | | 2 |   |(2)|   |
-+---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+
-
-Move 4 - Left     Move 5 - Up       Move 6 - Right    Move 7 - Up
-+---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+
-| 4 |   |   |   | | 8 |   |   | 4 | |   |   | 8 | 4 | |   |   | 8 | 8 |
-+---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+
-| 4 |   |   |(4)| | 4 |   |   |   | |   |   |   | 4 | |   |   |   | 2 |
-+---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+
-|   |   |   |   | |   |   |   |   | |   |   |   |   | |   |   |   |   |
-+---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+
-| 4 |   |   |   | |(2)|   |   |   | |(2)|   |   | 2 | |(2)|   |   |   |
-+---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+
-```
-This is how I lost this game:
-```
-+---+---+---+---+
-| 4 | 2 | 16| 4 |
-+---+---+---+---+
-| 32| 64| 8 | 2 |
-+---+---+---+---+
-| 4 | 8 |128| 32|
-+---+---+---+---+
-|(2)| 16| 8 | 4 |
-+---+---+---+---+
-```
-Press Q at any time to bring up the option to Quit or Restart the game.
-
-# Network Boot
-
-# Xmodem Flash Updater
-
-The ROMWBW Xmodem flash updater provides the capability to update ROMWBW from the boot loader using  an x-modem file transfer. It offers similar capabilities to Will Sowerbutts FLASH4 utility except that the flashing process occurs during the file transfer. 
-
-These are the key differences between the two methods are:
-
-Xmodem Flash Updater            | FLASH4
---------------------------------|-----------------
-Available from the boot loader   | Well proven and tested
-Xmodem transfer is integrated    | Wider range of supported chips and hardware
-Integrated checksum utilities    | Wider range of supported platforms
-Capability to copy a ROM image   | Only reprograms sectors that have changed
-More convenient one step process | Ability save and verify ROM images
-No intermediate storage required | Progress display while flashing
-.                                | Displays chip identification information
-.                                | Faster file transfer
-                                 
-The major disadvantages of the Updater is that it is new and relatively untested. There is the risk that a failed transfer will result in a partially flashed and unbootable ROM. There are some limitations on serial transfer speeds.
- 
-The updater utility was initially intended to support the Retrobrew SBC-V2-005 platform using Atmel 39SF040 flash chips but has now been extended to be more generic in operation.
-
-Supported flash chips are 
-39SF040, 29F040,  AT49F040, AT29C040, M29F040 , MX29F040,  A29010B, A29040B
-
-The Atmel 39SF040 chip is recommended as it can erase and write 4Kb sectors. Other chips require the whole chip to be erased.
-
-## Usage
-
-In most cases, completing a ROM update is a simple as:
-
-1. Booting to the boot loader prompt
-2. Selecting option X - Xmodem Flash Updater
-3. Selecting option U - Update
-4. Initiating an X-modem transfer of your ROM image on your console device
-5. Selecting option R - Reboot
-
-If your console device is not able to transfer a ROM image i.e. your console is a VDU then you will have to use the console options to identify which character-input/output device is to be used as the serial device for transfer.
-
-When your console is the serial device used for the transfer, no progress information is displayed as this would disrupt the x-modem file transfer. If you use an alternate character-input/output devices as the serial device for the transfer then progress information will be displayed on the console device.
-
-Due to different platform processor speeds,  serials speeds and flow control capabilities the default console or serial device speed may need to be reduced for a successful transfer and flash to occur. The **Set Console Interface/Baud code** option at the Boot Loader can be used to change the speed if required. Additionally, the Updater has options to set to and revert from a recommended speed. 
-
-See the ROMWBW Applications guide for additional information on performing upgrades.
-
-## Console Options
-
-Option ( C ) - Set Console Device
-
-Option ( S ) - Set Serial Device
-
-By default the updater assumes that the current console is a serial device and that the ROM file to be flashed will also be transferred across this device, so the Console and Serial device are both the same.
-
-Either device can be can be change to another character-input/output device but the updater will always expect to receive the x-modem transfer on the **Serial Device**
-
-The advantage of transferring on a different device to the console is that progress information can be displayed during the transfer.
-
-Option ( > ) - Set Recommended Baud Rate
-
-Option ( < ) - Revert to Original Baud Rate
-
-## Programming options
-
-Option ( U ) - Begin Update
-
-The will begin the update process. The updater will expect to start receiving
-an x-modem file on the serial device unit.
-
-X-modem sends the file in packets of 128 bytes. The updater will cache 32
-packets which is 1 flash sector and then write that sector to the
-flash device.
-
-If using separate console, bank and sector progress information will shown
-
-```
-BANK 00 s00 s01 s02 s03 s04 s05 s06 s06 s07
-BANK 01 s00 s01 s02 s03 s04 s05 s06 s06 s07
-BANK 02 s00 s01 s02 s03 s04 s05 s06 s06 s07 etc
-```
-
-The x-modem file transfer protocol does not provide any filename or size
-information for the transfer so the updater does not perform any checks
-on the file suitability.
-
-The updater expects the file size to be a multiple of 4 kilobytes and
-will write all data received to the flash device. A system update
-file (128kb .img) or complete ROM can be received and written (512kb or
-1024kb .rom)
-
-If the update fails it is recommended that you retry before rebooting or
-exiting to the Boot loader as your machine may not be bootable.
-
-Option ( D ) - Duplicate flash #1 to flash #2
- 
-This option will make a copy of flash #1 onto flash #2. The purpose of this is to enable
- making a backup copy of the current flash. Intended for systems using 2x512Kb Flash devices.
-
-Option ( V ) - Toggle Write Verify
-
-By default each flash sector will be verified after being written. Slight
-performance improvements can be gained if turned off and could be used if
-you are experiencing reliable transfers and flashing.
-
-## Exit options
-
-Option ( R ) - Reboot
-
-Execute a cold reboot. This should be done after a successful update. If
-you perform a cold reboot after a failed update then it is likely that
-your system will be unusable and removing and reprogramming the flash
-will be required.
-
-Option ( Q ) - Quit to boot loader. 
-
-The SBC Boot Loader is reloaded from ROM and
-executed. After a successful update a Reboot should be performed. However,
-in the case of a failed update this option could be used to attempt to
-load CP/M and perform the normal x-modem / flash process to recover.
-
-## CRC Utility options
-
-Option ( 1 ) and ( 2 ) - Calculate and display CRC32 of 1st or 2nd 512k ROM.
-Option ( 3 ) - Calculate and display CRC32 of a 1024k (2x512Kb) ROM.
-
-Can be used to verify if a ROM image has been transferred and flashed correctly. Refer  to the Teraterm section below for details on configuring the automatic display of a files CRC after it has been transferred.
-
-In Windows, right clicking on a file should also give you a context menu option CRC SHA which will allow you to select a CRC32 calculation to be done on the selected file.
-
-## Tera Term macro configuration 
-
-Macros are a useful tool for automatic common tasks. There are a number of instances where using macros to facilitate the update process could be worthwhile if you are:
-
-* Following the ROMWBW development builds.
-* Doing lots of configuration changes.
-* Doing development on ROMWBW drivers
-
-Macros can be used to automate sending ROM updates or images and for my own purposed I have set up a separate macro for transferring each of the standard build ROM, my own custom configuration ROM and update ROM.
-
-An example macro file to send an *.upd file, using checksum mode and display the crc32 value of the transmitted file:
-
-```
-Xmodem send, checksum, display crc32
-xmodemsend '\\desktop\users\phillip\documents\github\romwbw\binary\sbc_std_cust.upd' 1
-crc32file crc '\\desktop\users\phillip\documents\github\romwbw\binary\sbc_std_cust.rom'
-sprintf '0x%08x' crc
-messagebox inputstr 'crc32'
-```
-
-## Serial speed guidelines
-
-As identified in the introduction, there are limitations on serial speed depending on processor speed and flow control settings. Listed below are some of the results identified during testing.
-
-Platform / Configuration       | Processor Speed | Maximum Serial Speed
--------------------------------|-----------------|---------------------
-SBC-V2  UART no flow control   | 2mhz            | 9600
-SBC-V2  UART no flow control   | 4mhz            | 19200
-SBC-V2  UART no flow control   | 5mhz            | 19200
-SBC-V2  UART no flow control   | 8mhz            | 38400
-SBC-V2  UART no flow control   | 10mhz           | 38400
-SBC-V2  USB-FIFO 2mhz+         |                 | n/a
-SBC-MK4 ASCI no flow control   | 18.432mhz       | 9600
-SBC-MK4 ASCI with flow control | 18.432mhz       | 38400
-
-The **Set Recommend Baud Rate** option in the Updater menu follows the following guidelines.
-
-Processor Speed | Baud Rate
-----------------|----------
-1Mhz            | 4800
-2-3Mhz          | 9600
-4-7Mhz          | 19200
-8-20Mhz         | 38400
-
-These can be customized in the updater.asm source code in the CLKTBL table  if desired.
-Feedback to the ROMWBW developers on these guidelines would be appreciated.
-
-## Notes:
-- All testing was done with Teraterm x-modem, Forcing checksum mode using macros was found to give  the most reliable transfer.
-- Partial writes can be completed with 39SF040 chips. Other chips require entire flash to be erased before being written.
-- An SBC V2-005 MegaFlash or Z80 MBC required for 1mb flash support. The Updater assumes both chips are same type
-- Failure handling has not been tested.
-- Timing broadly calibrated on a Z80 SBC-v2
-- UNA BIOS not supported

Source/Doc/ReadMe.md

@@ -114,7 +114,6 @@ Documentation for $doc_product$ includes:
 * $doc_user$
 * $doc_sys$
 * $doc_apps$
-* $doc_romapps$
 * $doc_errata$
 
 # Acknowledgments

Source/Doc/UserGuide.md

@@ -11,11 +11,8 @@ companion documents you should refer to as appropriate:
   of RomWBW.  It includes a reference for the RomWBW HBIOS API
   functions.
 
-* $doc_romapps$ is a reference for the ROM-hosted applications provided
-  with RomWBW including the monitor, programming languages, etc.
-
-* $doc_apps$ is a reference for the OS-hosted proprietary command
-  line applications that were created to enhance RomWBW.
+* $doc_apps$ is a reference for the ROM-hosted and OS-hosted applications
+  created or customized to enhance the operation of RomWBW.
 
 * $doc_catalog$ is a reference for the contents of the disk images
   provided with RomWBW.  It is somewhat out of date at this time.
@@ -391,7 +388,7 @@ At the Boot Loader prompt, you can type `H <enter>` for help.  You
 can type `L <enter>` to list the available built-in ROM applications.
 If your terminal supports ANSI escape sequences, you can try the
 'P' command to play a simple on-screen game.  Instructions for the
-game are found in $doc_romapps$.
+game are found in $doc_apps$.
 
 If all of this seems fine, your ROM has been successfully programmed.
 See the [Boot Loader Operation] section of this document for further
@@ -645,7 +642,7 @@ return to the Boot Loader menu.  If you are interested in creating a
 custom application to run here, review the "usrrom.asm" file in the
 Source/HBIOS folder of the distribution.
 
-Each of the ROM Applications is documented in $doc_romapps$.  Some
+Each of the ROM Applications is documented in $doc_apps$.  Some
 of the applications (such as BASIC) also have their own independent
 manual in the Doc directory of the distribution.  The OSes included
 in the ROM (CP/M 2.2 & Z-System) are described in the Operating Systems
@@ -5915,6 +5912,16 @@ MD: TYPE=RAM
 PPIDE: IO=48, MASTER
 PPIDE: IO=48, SLAVE
 
+
+FP: LEDIO=255
+DS5RTC: RTCIO=104, IO=104
+SSER: IO=52
+SCON: IO=0
+MD: TYPE=RAM
+PPIDE: IO=48, MASTER
+PPIDE: IO=48, SLAVE
+SD: MODE=FZ80, IO=108, UNITS=2
+
 ##### Notes:
 
 - Requires matching FPGA code
@@ -5936,7 +5943,8 @@ may be discovered by RomWBW in your system.
 | CTC       | System   | Zilog Clock/Timer                                      |
 | CVDU      | Video    | MC8563-based Video Display Controller                  |
 | DMA       | System   | Zilog DMA Controller                                   |
-| DS1307    | RTC      | Maxim DS1307 PCF I2C Real-Time Clock w/ NVRAM          |
+| DS5RTC    | RTC      | Maxim DS1305 SPI Real-Time Clock w/ NVRAM              |
+| DS7RTC    | RTC      | Maxim DS1307 PCF I2C Real-Time Clock w/ NVRAM          |
 | DS1501RTC | RTC      | Maxim DS1501/DS1511 Watchdog Real-Time Clock           |
 | DSRTC     | RTC      | Maxim DS1302 Real-Time Clock w/ NVRAM                  |
 | DUART     | Char     | SCC2681 or compatible Dual UART                        |
@@ -5976,6 +5984,7 @@ may be discovered by RomWBW in your system.
 | SN76489   | Sound    | SN76489 Programmable Sound Generator                   |
 | SPK       | Sound    | Bit-bang Speaker                                       |
 | SYQ       | Disk     | Iomega SparQ Drive on PPI                              |
+| SSER      | Char     | Simple Serial Interface                                |
 | TMS       | Video    | TMS9918/38/58 Video Display Controller                 |
 | UART      | Char     | 16C550 Family Serial Interface                         |
 | USB-FIFO  | Char     | FT232H-based ECB USB FIFO                              |

Source/HBIOS/Config/FZ80_std.asm

@@ -25,3 +25,6 @@
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;
 #include "cfg_fz80.asm"
+;
+CPUOSC		.SET	8000000		; CPU OSC FREQ IN MHZ
+CRTACT		.SET	TRUE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP

Source/HBIOS/Config/SCZ180_sc503.asm

@@ -40,6 +40,7 @@ FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
 FPSW_IO		.SET	$A0		; FP: PORT ADDRESS FOR FP SWITCHES
 ;
 LEDENABLE	.SET	TRUE		; ENABLE STATUS LED (SINGLE LED)
+LEDMODE		.SET	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
 ;
 DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 INTRTCENABLE	.SET	TRUE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)

Source/HBIOS/Config/SCZ180_sc700.asm

@@ -37,7 +37,6 @@ Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 ;
 LEDENABLE	.SET	TRUE		; ENABLE STATUS LED (SINGLE LED)
 LEDMODE		.SET	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
-LEDPORT		.SET	$0E		; STATUS LED PORT ADDRESS
 ;
 FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
 FPLED_IO	.SET	$00		; FP: PORT ADDRESS FOR FP LEDS

Source/HBIOS/ay38910.asm

@@ -98,6 +98,13 @@ AY_RDAT		.EQU	$40
 AY_RIN		.EQU	$40
 		DEVECHO	"NABU"
 #ENDIF
+;
+#IF (AYMODE == AYMODE_RCGSJ)
+AY_RSEL		.EQU	$A1
+AY_RDAT		.EQU	$A0
+AY_RIN		.EQU	$A1
+		DEVECHO	"RCGSJ"
+#ENDIF
 ;
 	DEVECHO	", IO="
 	DEVECHO	AY_RSEL

Source/HBIOS/cfg_duo.asm

@@ -124,6 +124,8 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+;
 SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
@@ -239,7 +241,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -321,7 +323,7 @@ SNMODE		.EQU	SNMODE_DUO	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
 ;
 AY38910ENABLE	.EQU	TRUE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_DUO	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.EQU	AYMODE_DUO	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|RCGSJ]
 ;
 SPKENABLE	.EQU	TRUE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_dyno.asm

@@ -126,6 +126,8 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+;
 SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
@@ -254,7 +256,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -300,7 +302,7 @@ SNMODE		.EQU	SNMODE_NONE	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.EQU	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|RCGSJ]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_epitx.asm

@@ -128,6 +128,8 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+;
 SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
@@ -256,7 +258,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_EPITX	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|EPITX]
+SDMODE		.EQU	SDMODE_EPITX	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	$40		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
 SDTRACE		.EQU	2		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -332,7 +334,7 @@ SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.EQU	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|RCGSJ]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_fz80.asm

@@ -126,6 +126,8 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+DS5RTCENABLE	.EQU	TRUE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+;
 SSERENABLE	.EQU	TRUE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.EQU	$34		; SSER: STATUS PORT
@@ -258,8 +260,8 @@ PPIDE2BASE	.EQU	$00		; PPIDE 2: PPI REGISTERS BASE ADR
 PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
-SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.EQU	SDMODE_FZ80	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -335,7 +337,7 @@ SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|RCGSJ]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_heath.asm

@@ -126,6 +126,8 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+;
 SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
@@ -259,7 +261,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -325,7 +327,7 @@ SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|RCGSJ]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_master.asm

@@ -155,6 +155,8 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+;
 SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
@@ -306,7 +308,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_NONE	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_NONE	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -392,7 +394,7 @@ SNMODE		.EQU	SNMODE_NONE	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.EQU	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|RCGSJ]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_mbc.asm

@@ -121,6 +121,8 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+;
 SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
@@ -236,7 +238,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_JUHA	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_JUHA	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -308,7 +310,7 @@ SNMODE		.EQU	SNMODE_NONE	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_MBC	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.EQU	AYMODE_MBC	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|RCGSJ]
 ;
 SPKENABLE	.EQU	TRUE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_mk4.asm

@@ -126,6 +126,8 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+;
 SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
@@ -245,7 +247,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MK4	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_MK4	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -304,7 +306,7 @@ SNMODE		.EQU	SNMODE_VGM	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_SCG	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.EQU	AYMODE_SCG	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|RCGSJ]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_mon.asm

@@ -121,6 +121,8 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+;
 SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
@@ -254,7 +256,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -330,7 +332,7 @@ SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|RCGSJ]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_n8.asm

@@ -128,6 +128,8 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+;
 SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
@@ -247,7 +249,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_CSIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_CSIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	N8_PPI0		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -297,7 +299,7 @@ SNMODE		.EQU	SNMODE_VGM	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_N8	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.EQU	AYMODE_N8	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|RCGSJ]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_nabu.asm

@@ -126,6 +126,8 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+;
 SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
@@ -259,7 +261,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -335,7 +337,7 @@ SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
 AY38910ENABLE	.EQU	TRUE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_NABU	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.EQU	AYMODE_NABU	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|RCGSJ]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_rcz180.asm

@@ -132,6 +132,8 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+;
 SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
@@ -260,7 +262,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -336,7 +338,7 @@ SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO]
+AYMODE		.EQU	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|RCGSJ]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_rcz280.asm

@@ -126,6 +126,8 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+;
 SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
@@ -264,7 +266,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -340,7 +342,7 @@ SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|RCGSJ]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_rcz80.asm

@@ -126,6 +126,8 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+;
 SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
@@ -259,7 +261,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -335,7 +337,7 @@ SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|RCGSJ]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_rph.asm

@@ -126,6 +126,8 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+;
 SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
@@ -236,7 +238,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_CSIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_CSIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	RPH_PPI0	; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -286,7 +288,7 @@ SNMODE		.EQU	SNMODE_NONE	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_N8	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.EQU	AYMODE_N8	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|RCGSJ]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_s100.asm

@@ -126,6 +126,8 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+;
 SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
@@ -254,7 +256,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_SC	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_SC	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -320,7 +322,7 @@ SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.EQU	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|RCGSJ]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_sbc.asm

@@ -121,6 +121,8 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+;
 SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
@@ -235,7 +237,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_JUHA	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_JUHA	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -286,7 +288,7 @@ SNMODE		.EQU	SNMODE_VGM	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_SCG	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.EQU	AYMODE_SCG	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|RCGSJ]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_scz180.asm

@@ -126,6 +126,8 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+;
 SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
@@ -254,7 +256,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_SC	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_SC	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -330,7 +332,7 @@ SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.EQU	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|RCGSJ]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_z80retro.asm

@@ -119,6 +119,8 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+;
 SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
@@ -210,7 +212,7 @@ PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
 PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_Z80R	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_Z80R	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE

Source/HBIOS/cfg_zeta.asm

@@ -108,6 +108,8 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+;
 SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
@@ -180,7 +182,7 @@ PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
 PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_zeta2.asm

@@ -119,6 +119,8 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+;
 SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
@@ -191,7 +193,7 @@ PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
 PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/ds5rtc.asm

@@ -0,0 +1,566 @@
+;
+;==================================================================================================
+; MAXIM DS1305 RTC DRIVER
+;==================================================================================================
+;
+; THE DS1305 USES AN SPI INTERFACE.  THIS DRIVER CURRENTLY ASSUMES THE
+; FPGA-BASED SPI INTERFACE IMPLEMENTED IN THE S100 FPGA Z80.
+;
+; TRICKLE CHARGING IS NOT CURRENTLY IMPLEMENTED SINCE THE S100 FPGA Z80
+; DOES NOT SUPPORT THE USER OF A SUPER CAPACITOR.
+;
+;  REGISTER ADDRESSES (HEX / BCD):
+;
+;  +---+-----+---------------+-------------------+------------------+----------------+
+;  |ADR|  D7 | D6  | D5 | D4 | D3 | D2 | D1 | D0 | RANGE            | REGISTER       |
+;  +---+-----+---------------+-------------------+------------------+----------------+
+;  | 0 |  0  |     10-SECOND |          1-SECOND |            00-59 | SECONDS        |
+;  +---+-----+-----+---------+-------------------+------------------+----------------+
+;  | 1 |  0  |     10-MINUTE |          1-MINUTE |            00-59 | MINUTES        |
+;  +---+-----+-----+---------+-------------------+------------------+----------------+
+;  | 2 |  0  |  0  | 10-HOUR |            1-HOUR |            00-23 | HOURS          |
+;  +---+-----+-----+----+----+-------------------+------------------+----------------+
+;  | 3 |  0  |  0  |  0 |  0 |       DAY OF WEEK |            01-07 | DAY OF WEEK    |
+;  +---+-----+-----+----+----+----+--------------+------------------+----------------+
+;  | 4 |  0  |  0  | 10-DATE |            1-DATE |            01-31 | DATE           |
+;  +---+-----+-----+----+----+-------------------+------------------+----------------+
+;  | 5 |  0  |  0  |10-MONTH |           1-MONTH |            01-12 | MONTH          |
+;  +---+-----+-----+----+----+-------------------+------------------+----------------+
+;  | 6 |             10-YEAR |            1-YEAR |            00-99 | YEAR           |
+;  +---+-----+-----+----+----+----+----+----+----+------------------+----------------+
+;                        --- ALARM 0 ---
+;  +---+-----+-----+----+----+----+----+----+----+------------------+----------------+
+;  | 7 |  M  |     10-SECOND |          1-SECOND |            00-59 | SECONDS ALARM  |
+;  +---+-----+---------------+-------------------+------------------+----------------+
+;  | 8 |  M  |     10-MINUTE |          1-MINUTE |            00-59 | MINUTES ALARM  |
+;  +---+-----+-----+---------+-------------------+------------------+----------------+
+;  | 9 |  M  |  0  | 10-HOUR |            1-HOUR |            00-23 | HOURS ALARM    |
+;  +---+-----+-----+----+----+-------------------+------------------+----------------+
+;  | A |  M  |  0  | 0  | 0  |               DAY |              1-7 | DAY ALARM      |
+;  +---+-----+-----+----+----+----+--------------+------------------+----------------+
+;                        --- ALARM 1 ---
+;  +---+-----+-----+----+----+----+----+----+----+------------------+----------------+
+;  | B |  M  |     10-SECOND |          1-SECOND |            00-59 | SECONDS ALARM  |
+;  +---+-----+---------------+-------------------+------------------+----------------+
+;  | C |  M  |     10-MINUTE |          1-MINUTE |            00-59 | MINUTES ALARM  |
+;  +---+-----+-----+---------+-------------------+------------------+----------------+
+;  | D |  M  |  0  | 10-HOUR |            1-HOUR |            00-23 | HOURS ALARM    |
+;  +---+-----+-----+----+----+-------------------+------------------+----------------+
+;  | E |  M  |  0  | 0  | 0  |               DAY |              1-7 | DAY ALARM      |
+;  +---+-----+-----+----+----+----+--------------+------------------+----------------+
+;
+;  +---+-----+-----+---------+-------------------+------------------+----------------+
+;  | F |/EOSC| WP  | 0  | 0  | 0  |INTC|AIE1|AIE0|                  | CONTROL REG    |
+;  +---+-----+-----+----+----+----+----+----+----+------------------+----------------+
+;  |10 |  0  |  0  | 0  | 0  | 0  | 0  |IRQ1|IRQ0|                  | STATUS REG     |
+;  +---+-----+-----+----+----+----+----+----+----+------------------+----------------+
+;  |11 | TRICKLE CHG ENABLE  |  DIODE  |RESISTOR |                  | TRICKLE CHG REG|
+;  +---+-----+-----+----+----+----+----+----+----+------------------+----------------+
+;  |12-1F |              RESERVED                |                  |                |
+;  +---+-----+-----+----+----+----+----+----+----+------------------+----------------+
+;  |20-7F |              USER NVRAM              |            00-FF |                |
+;  +---+-----+-----+----+----+----+----+----+----+------------------+----------------+
+;
+;  0 = SHOULD BE SET TO 0 FOR VALID TIME/CALENDAR RANGE.
+;  CLOCK CALENDAR DATA IS BCD. AUTOMATIC LEAP YEAR ADJUSTMENT.
+;  DAY-OF-WEEK CODED AS SUNDAY = 1 THROUGH SATURDAY = 7.
+;
+; CONSTANTS
+;
+DS5RTC_BASE	.EQU	$68
+DS5RTC_DATA	.EQU	DS5RTC_BASE + 0
+DS5RTC_SELECT	.EQU	DS5RTC_BASE + 2	; WRITE
+DS5RTC_STATUS	.EQU	DS5RTC_BASE + 2	; READ
+DS5RTC_RUN	.EQU	DS5RTC_BASE + 3	; START READ/WRITE USING IN/OUT OPCODE
+;
+; IO PORTS
+;
+DS5NVM_BASE		.EQU	DS5RTC_BASE + $20
+
+DS5RTC_REG_SEC		.EQU	$00
+DS5RTC_REG_MIN		.EQU	$01
+DS5RTC_REG_HOUR		.EQU	$02
+DS5RTC_REG_WEEKDAY	.EQU	$03
+DS5RTC_REG_DATE		.EQU	$04
+DS5RTC_REG_MONTH	.EQU	$05
+DS5RTC_REG_YEAR		.EQU	$06
+DS5RTC_REG_ALM0_SEC	.EQU	$07
+DS5RTC_REG_ALM0_MIN	.EQU	$08
+DS5RTC_REG_ALM0_HOUR	.EQU	$09
+DS5RTC_REG_ALM0_DAY	.EQU	$0A
+DS5RTC_REG_ALM1_SEC	.EQU	$0B
+DS5RTC_REG_ALM1_MIN	.EQU	$0C
+DS5RTC_REG_ALM1_HOUR	.EQU	$0D
+DS5RTC_REG_ALM1_DAY	.EQU	$0E
+DS5RTC_REG_CONTROL	.EQU	$0F
+DS5RTC_REG_STATUS	.EQU	$10
+DS5RTC_REG_TCHG		.EQU	$11
+DS5RTC_REG_NVM_BASE	.EQU	$20
+;
+; VALUES FOR DIFFERENT BATTERY OR SUPERCAPACITOR CHARGE RATES
+;
+DS5RTC_TC1D2K	.EQU	%10100101	; 1 DIODE 2K RESISTOR (DEFAULT)
+DS5RTC_TC1D4K	.EQU	%10100110	; 1 DIODE 4K RESISTOR
+DS5RTC_TC1D8K	.EQU	%10100111	; 1 DOIDE 8K RESISTOR
+DS5RTC_TC2D2K	.EQU	%10101001	; 2 DIODES 2K RESISTOR
+DS5RTC_TC2D4K	.EQU	%10101010	; 2 DIODES 4K RESISTOR
+DS5RTC_TC2D8K	.EQU	%10101011	; 2 DIODES 8K RESISTOR
+;
+;
+;
+DS5RTC_BUFSIZE	.EQU	6		; 6 BYTE BUFFER (YYMMDDHHMMSS)
+;
+	DEVECHO	"DS5RTC: RTCIO="
+	DEVECHO	DS5RTC_BASE
+	DEVECHO	", IO="
+	DEVECHO	DS5RTC_BASE
+	DEVECHO	"\n"
+;
+; RTC DEVICE INITIALIZATION ENTRY
+;
+DS5RTC_INIT:
+	LD	A,(RTC_DISPACT)		; RTC DISPATCHER ALREADY SET?
+	OR	A			; SET FLAGS
+	RET	NZ			; IF ALREADY ACTIVE, ABORT
+;
+	CALL	NEWLINE			; FORMATTING
+	PRTS("DS5RTC: IO=0x$")
+	LD	A, DS5RTC_BASE
+	CALL	PRTHEXBYTE
+;
+	CALL	DS5RTC_DETECT		; HARDWARE DETECTION
+	JR	Z,DS5RTC_INIT1		; IF ZERO, ALL GOOD
+	PRTS(" NOT PRESENT$")		; NOT ZERO, H/W NOT PRESENT
+	OR	$FF			; SIGNAL FAILURE
+	RET				; BAIL OUT
+;
+DS5RTC_INIT1:
+	; DISPLAY CURRENT TIME
+	CALL	PC_SPACE		; FORMATTING
+	LD	HL,DS5RTC_BUF		; USE INTERNAL BUFFER
+	CALL	DS5RTC_RDCLK		; GET RAW RTC DATE/TIME
+	LD	HL,DS5RTC_TIMBUF	; POINT TO HBIOS TIME BUF
+	CALL	DS5RTC_CLK2TIM		; CONVERT TO HBIOS FMT
+	LD	HL,DS5RTC_TIMBUF	; POINT TO HBIOS TIME BUF
+	CALL	PRTDT			; PRINT FORMATTED DATE/TIME
+;
+	; ADD OURSELVES TO RTC DISPATCHER
+	LD	BC,DS5RTC_DISPATCH
+	CALL	RTC_SETDISP
+;
+	XOR	A
+	RET
+;
+; RTC DEVICE FUNCTION DISPATCH ENTRY
+;   A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR
+;   B: FUNCTION (IN)
+;
+DS5RTC_DISPATCH:
+	LD	A, B				; Get requested function
+	AND	$0F				; Isolate Sub-Function
+	JP	Z, DS5RTC_GETTIM		; Get Time
+	DEC	A
+	JP	Z, DS5RTC_SETTIM		; Set Time
+	DEC	A
+	JP	Z, DS5RTC_GETBYT		; Get NVRAM Byte Value
+	DEC	A
+	JP	Z, DS5RTC_SETBYT		; Set NVRAM Byte Value
+	DEC	A
+	JP	Z, DS5RTC_GETBLK		; Get NVRAM Data Block Value
+	DEC	A
+	JP	Z, DS5RTC_SETBLK		; Set NVRAM Data Block Value
+	DEC	A
+	JP	Z, DS5RTC_GETALM		; Get Alarm
+	DEC	A
+	JP	Z, DS5RTC_SETALM		; Set Alarm
+;
+; RTC GET TIME
+;   A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR
+;   HL: DATE/TIME BUFFER (OUT)
+; BUFFER FORMAT IS BCD: YYMMDDHHMMSS
+; 24 HOUR TIME FORMAT IS ASSUMED
+;
+DS5RTC_GETTIM:
+	PUSH	HL			; SAVE ADR OF OUTPUT BUF
+;
+	; READ THE CLOCK
+	LD	HL,DS5RTC_BUF		; POINT TO CLOCK BUFFER
+	CALL	DS5RTC_RDCLK		; READ THE CLOCK
+	LD	HL,DS5RTC_TIMBUF	; POINT TO TIME BUFFER
+	CALL	DS5RTC_CLK2TIM		; CONVERT CLOCK TO TIME
+;
+	; NOW COPY TO REAL DESTINATION (INTERBANK SAFE)
+	LD	A,BID_BIOS		; COPY FROM BIOS BANK
+	LD	(HB_SRCBNK),A           ; SET IT
+	LD	A,(HB_INVBNK)		; COPY TO CURRENT USER BANK
+	LD	(HB_DSTBNK),A           ; SET IT
+	LD	HL,DS5RTC_TIMBUF	; SOURCE ADR
+	POP	DE			; DEST ADR
+	LD	BC,6			; LENGTH IS 6 BYTES
+#IF (INTMODE == 1)
+	DI
+#ENDIF
+	CALL	HB_BNKCPY		; COPY THE CLOCK DATA
+#IF (INTMODE == 1)
+	EI
+#ENDIF
+;
+	; CLEAN UP AND RETURN
+	XOR	A			; SIGNAL SUCCESS
+	RET				; AND RETURN
+;
+; RTC SET TIME
+;   A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR
+;   HL: DATE/TIME BUFFER (IN)
+; BUFFER FORMAT IS BCD: YYMMDDHHMMSS
+; 24 HOUR TIME FORMAT IS ASSUMED
+;
+DS5RTC_SETTIM:
+	; COPY INCOMING TIME DATA TO OUR TIME BUFFER
+	LD	A,(HB_INVBNK)		; COPY FROM CURRENT USER BANK
+	LD	(HB_SRCBNK),A		; SET IT
+	LD	A,BID_BIOS		; COPY TO BIOS BANK
+	LD	(HB_DSTBNK),A		; SET IT
+	LD	DE,DS5RTC_TIMBUF	; DEST ADR
+	LD	BC,6			; LENGTH IS 6 BYTES
+#IF (INTMODE == 1)
+	DI
+#ENDIF
+	CALL	HB_BNKCPY		; COPY THE CLOCK DATA
+#IF (INTMODE == 1)
+	EI
+#ENDIF
+;
+	; WRITE TO CLOCK
+	LD	HL,DS5RTC_TIMBUF	; POINT TO TIME BUFFER
+	CALL	DS5RTC_TIM2CLK		; CONVERT TO CLOCK FORMAT
+	LD	HL,DS5RTC_BUF		; POINT TO CLOCK BUFFER
+	CALL	DS5RTC_WRCLK		; WRITE TO THE CLOCK
+;
+	; CLEAN UP AND RETURN
+	XOR	A			; SIGNAL SUCCESS
+	RET				; AND RETURN
+;
+; RTC GET NVRAM BYTE
+;   A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR
+;   C: INDEX (IN)
+;   E: VALUE (OUT)
+;
+DS5RTC_GETBYT:
+	LD	A,C			; INDEX TO A
+	ADD	A,$20			; NVRAM STARTS AT REG $20
+	LD	C,A			; BACK TO REG C
+	CALL	DS5RTC_GET		; DO IT
+	LD	E,A			; MOVE RESULT TO E
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
+;
+; RTC SET NVRAM BYTE
+;   A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR
+;   C: INDEX (IN)
+;   E: VALUE (IN)
+;
+DS5RTC_SETBYT:
+	LD	A,C			; INDEX TO A
+	ADD	A,$20			; NVRAM STARTS AT REG $20
+	LD	C,A			; BACK TO REG C
+	CALL	DS5RTC_WPOFF		; DISABLE WRITE PROTECT
+	CALL	DS5RTC_PUT		; DO IT
+	CALL	DS5RTC_WPOFF		; ENABLE WRITE PROTECT
+	LD	E,A			; MOVE RESULT TO E
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
+;
+; RTC GET BLOCK
+;   A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR
+;   HL: BUFFER ADDRESS (IN)
+;
+DS5RTC_GETBLK:
+	SYSCHKERR(ERR_NOTIMPL)
+	RET
+;
+; RTC GET BLOCK
+;   A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR
+;   HL: BUFFER ADDRESS (IN)
+;
+DS5RTC_SETBLK:
+	SYSCHKERR(ERR_NOTIMPL)
+	RET
+;
+; RTC GET ALARM
+;   A: RESULT (OUT), 0=OK, Z=OK, NZ=ERROR
+;   HL: DATE/TIME BUFFER ADDRESS (IN)
+; BUFFER FORMAT IS BCD: YYMMDDHHMMSS
+; 24 HOUR TIME FORMAT IS ASSUMED
+;
+DS5RTC_GETALM:
+	SYSCHKERR(ERR_NOTIMPL)
+	RET
+;
+; RTC SET ALARM
+;   A: RESULT (OUT), 0=OK, Z=OK, NZ=ERROR
+;   HL: DATE/TIME BUFFER ADDRESS (IN)
+; BUFFER FORMAT IS BCD: YYMMDDHHMMSS
+; 24 HOUR TIME FORMAT IS ASSUMED
+;
+DS5RTC_SETALM:
+	SYSCHKERR(ERR_NOTIMPL)
+	RET
+;
+;==================================================================================================
+; INTERNAL PROCEDURES
+;==================================================================================================
+;
+; TURN ON WRITE PROTECT
+;
+DS5RTC_WPON:
+	PUSH	AF
+	PUSH	BC
+	LD	A,%01000000		; CONTROL REGISTER W/P ON VALUE
+	LD	C,DS5RTC_REG_CONTROL	; CONTROL REGISTER ADR
+	CALL	DS5RTC_PUT		; SET CONTROL REGISTER
+	POP	BC
+	POP	AF
+	RET
+;
+; TURN OFF WRITE PROTECT
+;
+DS5RTC_WPOFF:
+	PUSH	AF
+	PUSH	BC
+	XOR	A			; CONTROL REGISTER W/P OFF VALUE
+	LD	C,DS5RTC_REG_CONTROL	; CONTROL REGISTER ADR
+	CALL	DS5RTC_PUT		; SET CONTROL REGISTER
+	POP	BC
+	POP	AF
+	RET
+;
+; DETECT RTC HARDWARE PRESENCE
+;
+DS5RTC_DETECT:
+	CALL	DS5RTC_WPOFF		; DISABLE WRITE PROTECT
+;
+	; TEST AN NVRAM BYTE (NON-DESTRUCTIVE)
+	LD	C,$7F			; LAST NVRAM BYTE
+	CALL	DS5RTC_GET		; GET CURRENT VALUE
+	LD	B,A			; SAVE IN B
+	XOR	$FF			; FLIP ALL BITS
+	CALL	DS5RTC_PUT		; SAVE TO RTC NVRAM
+	CALL	DS5RTC_GET		; GET UPDATED VALUE
+	XOR	$FF			; FLIP ALL BITS
+	CP	B			; COMPARE W/ ORIGINAL READ
+	PUSH	AF			; SAVE FLAGS
+	CALL	DS5RTC_PUT		; RESAVE ORIGINAL VALUE
+;
+	CALL	DS5RTC_WPON		; RESTORE WRITE PROTECT
+	POP	AF			; RESTORE FLAGS
+	RET				; ZF INDICATES PRESENCE
+;
+; READ RTC DATE/TIME INTO INTERNAL BUFFER
+;
+DS5RTC_RDCLK:
+	LD	B,7			; 7 BYTE DATE/TIME BUFFER
+	LD	C,DS5RTC_REG_SEC	; START W/ SECONDS REGISTER
+	LD	HL,DS5RTC_BUF		; USE INTERNAL BUFFER
+	CALL	DS5RTC_GETBUF		; FILL THE BUFFER
+	XOR	A			; SIGNAL SUCCESS
+	RET				; RETURN
+;
+; WRITE RTC DATE/TIME FROM INTERNAL BUFFER
+;
+DS5RTC_WRCLK:
+	CALL	DS5RTC_WPOFF		; DISABLE WRITE PROTECT
+	LD	B,7			; 7 BYTE DATE/TIME BUFFER
+	LD	C,DS5RTC_REG_SEC	; START W/ SECONDS REGISTER
+	LD	HL,DS5RTC_BUF		; USE INTERNAL BUFFER
+	CALL	DS5RTC_PUTBUF		; FILL THE BUFFER
+	CALL	DS5RTC_WPON		; RESTORE WRITE PROTECT
+	XOR	A			; SIGNAL SUCCESS
+	RET				; RETURN
+;
+; CONVERT DATA IN CLOCK BUFFER TO TIME BUFFER AT HL
+;
+DS5RTC_CLK2TIM:
+	LD	A,(DS5RTC_YR)
+	LD	(HL),A
+	INC	HL
+	LD	A,(DS5RTC_MON)
+	LD	(HL),A
+	INC	HL
+	LD	A,(DS5RTC_DT)
+	LD	(HL),A
+	INC	HL
+	LD	A,(DS5RTC_HR)
+	LD	(HL),A
+	INC	HL
+	LD	A,(DS5RTC_MIN)
+	LD	(HL),A
+	INC	HL
+	LD	A,(DS5RTC_SEC)
+	LD	(HL),A
+	RET
+;
+; CONVERT DATA IN TIME BUFFER AT HL TO CLOCK BUFFER
+;
+DS5RTC_TIM2CLK:
+	PUSH	HL
+	LD	A,(HL)
+	LD	(DS5RTC_YR),A
+	INC	HL
+	LD	A,(HL)
+	LD	(DS5RTC_MON),A
+	INC	HL
+	LD	A,(HL)
+	LD	(DS5RTC_DT),A
+	INC	HL
+	LD	A,(HL)
+	LD	(DS5RTC_HR),A
+	INC	HL
+	LD	A,(HL)
+	LD	(DS5RTC_MIN),A
+	INC	HL
+	LD	A,(HL)
+	LD	(DS5RTC_SEC),A
+	POP	HL
+	CALL	TIMDOW
+	INC	A			; CONVERT FROM 0-6 TO 1-7
+	LD	(DS5RTC_DAY),A
+	RET
+;
+; READ A BUFFER OF BYTES FROM THE RTC
+; START RTC ADR IN C, COUNT IN B, BUF PTR IN HL
+;
+DS5RTC_GETBUF:
+	LD	A,1
+	OUT	(DS5RTC_SELECT),A	; SELECT RTC
+	LD	A,C			; ADDRESS TO A
+	OUT	(DS5RTC_DATA),A		; SEND TO INTERFACE
+	OUT	(DS5RTC_RUN),A		; SPI TRANSACTION TO WRITE ADR
+	CALL	DS5RTC_WAITBSY		; WAIT FOR COMPLETION
+DS5RTC_GETBUF1:
+	OUT	(DS5RTC_RUN),A		; SPI TRANSACTION TO READ DATA
+	CALL	DS5RTC_WAITBSY		; WAIT FOR DATA
+	IN	A,(DS5RTC_DATA)		; GET VALUE
+	LD	(HL),A			; SAVE BYTE IN BUFFER
+	INC	HL			; BUMP BUF PTR
+	DJNZ	DS5RTC_GETBUF1		; LOOP FOR REQUESTED BYTES
+	LD	A,0
+	OUT	(DS5RTC_SELECT),A	; DESELECT DEVICE
+	RET
+;
+; WRITE A BUFFER OF BYTES TO THE RTC
+; START RTC ADR IN C, COUNT IN B, BUF PTR IN HL
+;
+DS5RTC_PUTBUF:
+	LD	A,1
+	OUT	(DS5RTC_SELECT),A	; SELECT RTC
+	LD	A,C			; ADDRESS TO A
+	SET	7,A			; SET WRITE BIT
+	OUT	(DS5RTC_DATA),A		; SEND TO INTERFACE
+	OUT	(DS5RTC_RUN),A		; SPI TRANSACTION TO WRITE ADR
+	CALL	DS5RTC_WAITBSY		; WAIT FOR COMPLETION
+DS5RTC_PUTBUF1:
+	LD	A,(HL)			; NEXT BYTE TO WRITE
+	INC	HL			; BUMP BUF PTR
+	OUT	(DS5RTC_DATA),A		; SEND TO INTERFACE
+	OUT	(DS5RTC_RUN),A		; SPI TRANSACTION TO WRITE BYTE
+	CALL	DS5RTC_WAITBSY		; WAIT FOR COMPLETION
+	DJNZ	DS5RTC_PUTBUF1		; LOOP FOR REQUESTED BYTES
+	LD	A,0
+	OUT	(DS5RTC_SELECT),A	; DESELECT DEVICE
+	RET
+;
+; GET A BYTE FROM THE RTC
+; ADDRESS IN C, RETURN VALLUE IN A
+;
+DS5RTC_GET:
+	LD	A,1
+	OUT	(DS5RTC_SELECT),A	; SELECT RTC
+	LD	A,C			; ADDRESS TO A
+	OUT	(DS5RTC_DATA),A		; SEND TO INTERFACE
+	OUT	(DS5RTC_RUN),A		; SPI TRANSACTION TO WRITE ADR
+	CALL	DS5RTC_WAITBSY		; WAIT FOR COMPLETION
+	OUT	(DS5RTC_RUN),A		; SPI TRANSACTION TO READ DATA
+	CALL	DS5RTC_WAITBSY		; WAIT FOR DATA
+	IN	A,(DS5RTC_DATA)		; GET VALUE
+	PUSH	AF			; SAVE VALUE
+	LD	A,0
+	OUT	(DS5RTC_SELECT),A	; DESELECT DEVICE
+	POP	AF			; RESTORE VALUE
+	RET
+;
+; PUT A BYTE TO THE RTC
+; ADDRESS IN C, VALUE IN A
+;
+DS5RTC_PUT:
+	PUSH	AF			; SAVE VALUE TO PUT
+	LD	A,1
+	OUT	(DS5RTC_SELECT),A	; SELECT RTC
+	LD	A,C			; ADDRESS TO A
+	SET	7,A			; SET WRITE BIT
+	OUT	(DS5RTC_DATA),A		; SEND TO INTERFACE
+	OUT	(DS5RTC_RUN),A		; SPI TRANSACTION TO WRITE ADR
+	CALL	DS5RTC_WAITBSY		; WAIT FOR COMPLETION
+	POP	AF			; RECOVER VALUE TO PUT
+	OUT	(DS5RTC_DATA),A		; VALUE TO OUTPUT
+	OUT	(DS5RTC_RUN),A		; SPI TRANSACTOIN TO WRITE VALUE
+	CALL	DS5RTC_WAITBSY		; WAIT FOR WRITE TO COMPLETE
+	LD	A,0
+	OUT	(DS5RTC_SELECT),A	; DESELECT DEVICE
+	RET
+;
+; WAIT UNTIL SPI INTERFACE IS NO LONGER BUSY
+;
+DS5RTC_WAITBSY:
+	PUSH	AF			; PRESERVE AF
+	PUSH	BC			; PRESERVE BC
+;
+	; AFTER INITIATING A SPI TRANSACTION, IT MAY TAKE A WHILE
+	; FOR THE BUSY STATUS TO BE REFLECTED.  THE DELAYS BELOW
+	; ENSURE ENOUGH TIME HAS ELAPSED.
+	CALL	DELAY
+	CALL	DELAY
+	CALL	DELAY
+	CALL	DELAY
+	CALL	DELAY
+	CALL	DELAY
+	CALL	DELAY
+	CALL	DELAY
+;
+	; SINCE THIS ROUTINE MAY BE USED TO DETECT AN RTC THAT DOES
+	; NOT EXIST, WE PROTECT THE WAIT WITH A TIMEOUT LOOP TO
+	; PREVENT A SYSTEM STALL.
+	LD	B,0
+DS5RTC_WAITBSY1:
+	IN	A,(DS5RTC_STATUS)	; GET STATUS BYTE
+	OR	A			; SET FLAGS
+	JR	Z,DS5RTC_WAITBSY2	; IF ZERO, WE ARE DONE
+	DJNZ	DS5RTC_WAITBSY1		; TRY TILL COUNTER EXHAUSTED
+DS5RTC_WAITBSY2:
+	POP	BC			; RECOVER BC
+	POP	AF			; RECOVER AF
+	RET
+;
+; DS5RTC_BUF IS USED FOR BURST READ/WRITE OF CLOCK DATA TO DS1305
+; FIELDS BELOW MATCH ORDER OF DS1305 FIELDS (BCD)
+;
+DS5RTC_BUF:
+DS5RTC_SEC	.DB	0		; SECOND
+DS5RTC_MIN	.DB	0		; MINUTE
+DS5RTC_HR	.DB	0		; HOUR
+DS5RTC_DAY	.DB	0		; DAY OF WEEK
+DS5RTC_DT	.DB	0		; DATE
+DS5RTC_MON	.DB	0		; MONTH
+DS5RTC_YR	.DB	0		; YEAR
+;
+; DS5RTC_TIMBUF IS TEMP BUF USED TO STORE TIME TEMPORARILY TO DISPLAY
+; IT.
+;
+DS5RTC_TIMBUF	.FILL	6,0		; 6 BYTES FOR GETTIM
+;
+; DS5RTC_TIMDEF IS DEFAULT TIME VALUE TO INITIALIZE CLOCK IF IT IS
+; NOT RUNNING.
+;
+DS5RTC_TIMDEF:	; DEFAULT TIME VALUE TO INIT CLOCK
+		.DB	$00,$01,$01	; 2000-01-01
+		.DB	$00,$00,$00	; 00:00:00

Source/HBIOS/dsrtc.asm

@@ -165,14 +165,6 @@ DSRTC_BUFSIZ	.EQU	7		; 7 BYTE BUFFER (YYMMDDHHMMSSWW)
 ; RTC DEVICE PRE-INITIALIZATION ENTRY
 ;
 DSRTC_PREINIT:
-;
-	;; SET RELEVANT BITS IN RTC LATCH SHADOW REGISTER
-	;; TO THEIR QUIESENT STATE
-	;LD	A,(DSRTC_OPRVAL)	; GET CURRENT SHADOW REG VAL
-	;AND	~DSRTC_MASK		; CLEAR OUR BITS
-	;OR	DSRTC_IDLE		; SET OUR IDLE BITS
-	;LD	(DSRTC_OPRVAL),A	; SAVE IT
-;
 	XOR	A			; ZERO
 	LD	(DSRTC_STAT),A		; CLEAR STATUS
 	CALL	DSRTC_DETECT		; HARDWARE DETECTION

Source/HBIOS/hbios.asm

@@ -173,7 +173,7 @@ SUPCTS	.EQU	FALSE		; SUPPRESS CTS DURING HBIOS BOOT
 ; SET DIAGNOSTIC LEDS
 ;
 ; SCxxx: LED Port=0x0E, bit 2, inverted, dedicated port (LEDMODE_SC)
-; SC7xx: LED Port=0x0E, bit 0, inverted, dedicated port (LEDMODE_STD)
+; SC7xx/SC5xx: LED Port=0x0E, bit 0, inverted, dedicated port (LEDMODE_STD)
 ; TinyZ80: LED Port=0x6E, bit 0, inverted, dedicated port (LEDMODE_STD)
 ; Z80-512K: LED Port=0x6E, bit 0, inverted, dedicated port (LEDMODE_STD)
 ; MBC: LED Port=0x70, bits 1-0, normal, shared w/ RTC port (LEDMODE_RTC)
@@ -3256,6 +3256,12 @@ HB_WDZ:
 	AND	%00000001		; ISOLATE CONSOLE BIT
 	JR	NZ,INITSYS3		; NOT SET, BYPASS CONSOLE SWITCH
   #ENDIF
+;
+  #IF (PLATFORM == PLT_FZ80)
+	IN	A,($36)			; GET IO BYTE
+	AND	%00000001		; ISOLATE CONSOLE BIT
+	JR	Z,INITSYS3		; NOT SET, BYPASS CONSOLE SWITCH
+  #ENDIF
 ;
 	LD	A,(CB_CRTDEV)		; GET CRT DISPLAY DEVICE
 	LD	(HB_NEWCON),A		; AND QUEUE TO SWITCH
@@ -3699,6 +3705,9 @@ HB_INITTBL:
 #IF (DS7RTCENABLE)
 	.DW	DS7RTC_INIT
 #ENDIF
+#IF (DS5RTCENABLE)
+	.DW	DS5RTC_INIT
+#ENDIF
 #IF (RP5RTCENABLE)
 	.DW	RP5RTC_INIT
 #ENDIF
@@ -7947,12 +7956,12 @@ SIZ_PCF		.EQU	$ - ORG_PCF
 		MEMECHO	" bytes.\n"
 #ENDIF
 ;
-#IF (DS7RTCENABLE)
-ORG_DS7RTC	.EQU	$
-  #INCLUDE "ds7rtc.asm"
-SIZ_DS7RTC	.EQU	$ - ORG_DS7RTC
-		MEMECHO	"DS7RTC occupies "
-		MEMECHO	SIZ_DS7RTC
+#IF (DS5RTCENABLE)
+ORG_DS5RTC	.EQU	$
+  #INCLUDE "ds5rtc.asm"
+SIZ_DS5RTC	.EQU	$ - ORG_DS5RTC
+		MEMECHO	"DS5RTC occupies "
+		MEMECHO	SIZ_DS5RTC
 		MEMECHO	" bytes.\n"
 #ENDIF
 ;

Source/HBIOS/hbios.inc

@@ -359,6 +359,7 @@ RTCDEV_SIMH	.EQU	$02		; SIMH
 RTCDEV_INT	.EQU	$03		; PERIODIC INT TIMER
 RTCDEV_DS7	.EQU	$04		; DS1307 (I2C)
 RTCDEV_RP5	.EQU	$05		; RP5C01
+RTCDEV_DS5	.EQU	$06		; DS1305 (SPI)
 ;
 ; DSKY DEVICE IDS
 ;

Source/HBIOS/scon.asm

@@ -5,7 +5,7 @@
 ;
 ; TODO:
 ;
-SCON_IOBASE	.EQU	$00
+SCON_IOBASE	.EQU	$0000			; NOTE: 16-BIT I/O
 ;
 SCON_STATUS	.EQU	SCON_IOBASE
 SCON_DATA	.EQU	SCON_IOBASE + 1
@@ -25,6 +25,9 @@ SCON_ROWS	.EQU	40
 SCON_INIT:
 	CALL	NEWLINE
 	PRTS("SCON:$")
+	PRTS(" IO=0x$")			; FORMATTING
+	LD	A,SCON_IOBASE
+	CALL	PRTHEXBYTE
 ;
 	; DISPLAY CONSOLE DIMENSIONS
 	CALL	PC_SPACE
@@ -68,7 +71,8 @@ SCON_IN:
 	CALL	SCON_IST		; CHECK FOR CHAR PENDING
 	JR	Z,SCON_IN		; WAIT FOR IT IF NECESSARY
 	;IN0	A,(SCON_DATA)		; READ THE CHAR FROM PROPIO
-	IN	A,(SCON_DATA)		; READ THE CHAR FROM PROPIO
+	LD	BC,SCON_DATA		; DATA PORT (16 BIT I/O)
+	IN	A,(C)			; READ THE CHAR FROM PROPIO
 	LD	E,A
 	RET
 ;
@@ -76,7 +80,8 @@ SCON_IN:
 ;
 SCON_IST:
 	;IN0	A,(SCON_STATUS)		; READ LINE STATUS REGISTER
-	IN	A,(SCON_STATUS)		; READ LINE STATUS REGISTER
+	LD	BC,SCON_STATUS		; STATUS PORT (16-BIT I/O)
+	IN	A,(C)			; READ LINE STATUS REGISTER
 	AND	SCON_KBDRDY		; ISOLATE KBDRDY
 	JP	Z,CIO_IDLE		; RETURN VIA IDLE PROCESSING
 	OR	$FF			; SET A=$FF TO SIGNAL READY
@@ -89,14 +94,16 @@ SCON_OUT:
 	JR	Z,SCON_OUT		; WAIT IF NECESSARY
 	LD	A,E			; RECOVER THE CHAR TO WRITE
 	;OUT0	(SCON_DATA),A		; WRITE THE CHAR TO PROPIO
-	OUT	(SCON_DATA),A		; WRITE THE CHAR TO PROPIO
+	LD	BC,SCON_DATA		; DATA PORT (16 BIT I/O)
+	OUT	(C),A			; WRITE THE CHAR TO PROPIO
 	RET
 ;
 ;
 ;
 SCON_OST:
 	;IN0	A,(SCON_STATUS)		; READ LINE STATUS REGISTER
-	IN	A,(SCON_STATUS)		; READ LINE STATUS REGISTER
+	LD	BC,SCON_STATUS		; STATUS PORT (16-BIT I/O)
+	IN	A,(C)			; READ LINE STATUS REGISTER
 	AND	SCON_DSPRDY 		; ISOLATE DSPRDY
 	JP	Z,CIO_IDLE		; RETURN VIA IDLE PROCESSING
 	OR	$FF			; SET A=$FF TO SIGNAL READY

Source/HBIOS/sd.asm

@@ -372,10 +372,10 @@ SD_CS0		.EQU	%00000100	; SELECT
 SD_DI		.EQU	%00000001	; DATA IN (CARD <- CPU) MOSI
 SD_DO		.EQU	%00000001	; DATA OUT (CARD -> CPU) MISO
 SD_CINIT	.EQU	FALSE		; INITIALIZE OUTPUT PORT
-SD_INVCS	.EQU	FALSE		; INVERT CS
+SD_INVCS	.EQU	TRUE		; INVERT CS
 		DEVECHO	"Z80R"
 #ENDIF
-
+;
 ; FOR NOW WE JUST HOOK UP ONE UNIT. THERE ARE EIGHT PORTS FOR DIFFERENT
 ; THINGS BUT THIS WILL GET US GOING
 #IF (SDMODE == SDMODE_EPITX)		; Z180 ITX - CSIO, 82C55 for CS
@@ -389,6 +389,39 @@ SD_IOBASE	.EQU	SD_OPRREG	; IOBASE
 SD_INVCS	.EQU	FALSE		; INVERT CS
 		DEVECHO	"EPITX"
 #ENDIF
+;
+; S100 FPGA Z80 SPI-BASED SD CARD
+;
+; BASE PORT: $6C
+;   BASE + 0: DATA IN/OUT
+;   BASE + 1: SPI CLOCK SPEED (0=LOW 4KHZ, 1=HIGH 10MHZ)
+;   BASE + 2: SELECT (W), STATUS (R)
+;   BASE + 3: START READ (IN OPCODE), START WRITE (OUT OPCODE), ANY VALUE
+;   
+; STATUS BITS:
+;   7: BUSY (1=BUSY)
+;   0: PRIMARY DEVICE SELECT STATUS (1=SELECTED)
+;   1: SECONDARY DEVICE SELECT STATUS  (1=SELECTED)
+;
+; SELECT BITS (INVERTED!!!):
+;   0: PRIMARY DEVICE, USE VALUE ~$01
+;   1: SECONDARY DEVICE, USE VALUE ~$02
+;
+#IF (SDMODE == SDMODE_FZ80)		; S100 FPGA Z80
+SD_IOBASE	.EQU	$6C		; IOBASE
+SD_DATA		.EQU	SD_IOBASE + 0	; DATA IN/OUT PORT
+SD_CLKSEL	.EQU	SD_IOBASE + 1	; CLOCK SPEED SELECT PORT
+SD_SELSTAT	.EQU	SD_IOBASE + 2	; DEVICE SELECT PORT (W) / STATUS (R)
+SD_ACTION	.EQU	SD_IOBASE + 3	; INITIATE R/W ACTION VIA IN/OUT
+;
+SD_DEVMAX	.EQU	2		; NUMBER OF PHYSICAL UNITS (SOCKETS)
+SD_OPRREG	.EQU	SD_SELSTAT	; SELECT/STATUS PORT
+SD_OPRDEF	.EQU	$FF		; QUIESCENT STATE
+SD_CS0		.EQU	%00000001	; PRIMARY DEVICE SELECT BIT
+SD_CS1		.EQU	%00000010	; SECONDARY DEVICE SELECT BIT
+SD_INVCS	.EQU	TRUE		; INVERT CS
+		DEVECHO	"FZ80"
+#ENDIF
 ;
 		DEVECHO	", IO="
 		DEVECHO	SD_IOBASE
@@ -640,6 +673,13 @@ SD_INIT:
 	LD	A,SD_TRDR
 	CALL	PRTHEXBYTE
 #ENDIF
+;
+#IF (SDMODE == SDMODE_FZ80)
+	PRTS(" MODE=FZ80$")
+	PRTS(" IO=0x$")
+	LD	A,SD_IOBASE
+	CALL	PRTHEXBYTE
+#ENDIF
 ;
 	CALL	SD_PROBE		; CHECK FOR HARDWARE
 	JR	Z,SD_INIT00		; CONTINUE IF PRESENT
@@ -1083,6 +1123,11 @@ SD_INITCARD:
 #IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
 	CALL	SD_CSIO_DEF		; ENSURE CSIO AT DEFAULT SPEED
 #ENDIF
+;
+#IF (SDMODE == SDMODE_FZ80)
+	;;; FORCE SLOW SPEED HERE?
+	;;; CALL SD_SELECT?
+#ENDIF
 ;
 	; WAKE UP THE CARD, KEEP DIN HI (ASSERTED) AND /CS HI (DEASSERTED)
 	LD	B,$10	; MIN 74 CLOCKS REQUIRED, WE USE 128 ($10 * 8)
@@ -1486,8 +1531,10 @@ SD_GOIDLE:
 ;
 SD_GOIDLE1:
 	; SEEMS TO HELP SOME CARDS?
-	;CALL	SD_SELECT		; ASSERT CS
-	;CALL	SD_DONE			; SEND 8 CLOCKS AND DEASSERT CS
+	;;; DEBUG
+	CALL	SD_SELECT		; ASSERT CS
+	CALL	SD_DONE			; SEND 8 CLOCKS AND DEASSERT CS
+	;;; DEBUG
 
 	; SMALL DELAY HERE HELPS SOME CARDS
 	;;LD	DE,300			; 16US * 300 = ~5MS
@@ -1884,6 +1931,15 @@ SD_SETUP:
 	LD	(SD_OPRVAL),A
 	OUT	(SD_OPRREG),A
 #ENDIF
+;
+#IF (SDMODE == SDMODE_FZ80)
+	LD	A,SD_OPRDEF		; DEFAULT SELECT VALUE
+	LD	(SD_OPRVAL),A		; PUT IN SHADOW
+	OUT	(SD_OPRREG),A		; WRITE TO PORT
+	XOR	A			; LOW SPEED OPERATION
+	LD	(SD_CLKSEL),A		; DO IT
+	CALL	SD_DESELECT		; MAKE SURE CARD(S) ARE NOT SELECTED
+#ENDIF
 ;
 	XOR	A
 	RET
@@ -1931,7 +1987,7 @@ SD_SELECT:
 ;	CALL	SD_WAITTX
 ;#ENDIF
 ;
-#IF ((SDMODE == SDMODE_SC) | SDMODE == SDMODE_MT))
+#IF ((SDMODE == SDMODE_SC) | (SDMODE == SDMODE_MT) | (SDMODE == SDMODE_FZ80))
 	LD	A,(IY+SD_DEV)		; GET CURRENT DEVICE
 	OR	A			; SET FLAGS
 	LD	A,(SD_OPRVAL)		; GET CURRENT OPRVAL BACK
@@ -1949,21 +2005,21 @@ SD_SELECT1:
 	OR	SD_CS1
   #ENDIF
 #ELSE
-#IF (SDMODE == SDMODE_EPITX)
+  #IF (SDMODE == SDMODE_EPITX)
 	LD	A,(SD_OPRVAL)
 	AND	$F8
 	OR	SD_CS0			; WILL DO 1-7 LATER
-#ELSE
+  #ELSE
 	LD	A,(SD_OPRVAL)		; GET CURRENT OPRVAL BACK
 	OR	SD_CS0
-#ENDIF
+  #ENDIF
 #ENDIF
 ;
 SD_SELECT2:
 ; ADJUST BIT(S) FOR INTERFACES USING INVERTED CS BITS
 ;#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC))
 #IF (SD_INVCS)
-  #IF ((SDMODE == SDMODE_SC) & (SD_DEVCNT > 1))
+  #IF (((SDMODE == SDMODE_SC) | (SDMODE == SDMODE_FZ80)) & (SD_DEVCNT > 1))
 	XOR	SD_CS0 | SD_CS1
   #ELSE
 	XOR	SD_CS0
@@ -1994,20 +2050,24 @@ SD_DESELECT:
 	; TRACES.
 	CALL	DLY32			; DELAY FOR FINAL BIT
 #ENDIF
+;
+#IF (SDMODE == SDMODE_FZ80)
+	CALL	SD_WAITBSY
+#ENDIF
 ;
 	LD	A,(SD_OPRVAL)
 #IF (((SDMODE == SDMODE_SC) | (SDMODE_MT)) & (SD_DEVCNT > 1))
 	AND	~(SD_CS0 | SD_CS1)
 #ELSE
-#if (SDMODE == SDMODE_EPITX)
+#IF (SDMODE == SDMODE_EPITX)
 	OR	7			; CHAN 7 IS USED FOR DESELECTS
 #ELSE
 	AND	~SD_CS0
 #ENDIF
 #ENDIF
 ; ADJUST BIT(S) FOR INTERFACES USING INVERTED CS BITS
-#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_PIO) | (SDMODE == SDMODE_Z80R))
-  #IF ((SDMODE == SDMODE_SC) & (SD_DEVCNT > 1))
+#IF (SD_INVCS)
+  #IF (((SDMODE == SDMODE_SC) | (SDMODE == SDMODE_FZ80)) & (SD_DEVCNT > 1))
 	XOR	SD_CS0 | SD_CS1
   #ELSE
 	XOR	SD_CS0
@@ -2037,24 +2097,38 @@ SD_WAITRX:
 ;
 #ENDIF
 ;
+#IF (SDMODE == SDMODE_FZ80)
+;
+; WAIT WHILE FPGA SPI INTERFACE IS BUSY SENDING OR RECEIVING
+;
+SD_WAITBSY:
+	PUSH	AF
+SD_WAITBSY1:
+	IN	A,(SD_SELSTAT)
+	BIT	7,A
+	JR	NZ,SD_WAITBSY1
+	POP	AF
+	RET
+#ENDIF
+;
 ; SEND ONE BYTE
 ;
 SD_PUT:
 ;
 #IF (SDMODE == SDMODE_MT)
 	OUT	(SD_WRTR),A
-#ELSE
+#ENDIF
 ;
-  #IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
+#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
 	CALL	MIRROR			; MSB<-->LSB MIRROR BITS, RESULT IN C
 	CALL	SD_WAITTX		; MAKE SURE WE ARE DONE SENDING
 	OUT0	(SD_TRDR),C		; PUT BYTE IN BUFFER
 	IN0	A,(SD_CNTR)
 	SET	4,A			; SET TRANSMIT ENABLE
 	OUT0	(SD_CNTR),A
-  #ELSE
-
-    #IF (SDMODE == SDMODE_Z80R)
+#ENDIF
+;
+#IF (SDMODE == SDMODE_Z80R)
 	; USE C - THE CALLING CODE FOR COMMAND SEND FAILS TO SAVE HL/DE
 	; WHILST THE OTHER PATHS DO ?
         LD	C,A
@@ -2090,8 +2164,9 @@ SD_PUT:
 	RLA
 	OUT	(SD_IOREG),A
 	OUT	(SD_IOCLK),A
-    #ELSE
-
+#ENDIF
+;
+#IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_N8) | (SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_DSD) | (SDMODE == SDMODE_USR) | (SDMODE == SDMODE_PIO))
       #IF (SDMODE == SDMODE_UART)
 	XOR	$FF			; DI IS INVERTED ON UART
       #ENDIF
@@ -2110,8 +2185,15 @@ SD_PUT1:
 	DJNZ	SD_PUT1			; REPEAT FOR ALL 8 BITS
 	LD	A,(SD_OPRVAL)		; LOAD CURRENT OPR VALUE
 	OUT	(SD_OPRREG),A		; LEAVE WITH CLOCK LOW
-    #ENDIF
-  #ENDIF
+#ENDIF
+;
+#IF (SDMODE == SDMODE_FZ80)
+	CALL	SD_WAITBSY		; WAIT FOR PENDING ACTIVITY
+	OUT	(SD_DATA),A		; POST THE VALUE
+	OUT	(SD_ACTION),A		; INITIATE THE WRITE
+	;;;CALL	PC_SPACE		; *DEBUG*
+	;;;CALL	PC_GT			; *DEBUG*
+	;;;CALL	PRTHEXBYTE		; *DEBUG*
 #ENDIF
 	RET				; DONE
 ;
@@ -2122,8 +2204,9 @@ SD_GET:
 ;
 #IF (SDMODE == SDMODE_MT)
 	IN	A,(SD_RDTR)
-#ELSE
-  #IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
+#ENDIF
+;
+#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
 	CALL	SD_WAITTX		; MAKE SURE WE ARE DONE SENDING
 	IN0	A,(SD_CNTR)		; GET CSIO STATUS
 	SET	5,A			; START RECEIVER
@@ -2132,8 +2215,9 @@ SD_GET:
 	IN0	A,(SD_TRDR)		; GET RECEIVED BYTE
 	CALL	MIRROR			; MSB<-->LSB MIRROR BITS
 	LD	A,C			; KEEP RESULT
-  #ELSE
-    #IF (SDMODE == SDMODE_Z80R)
+#ENDIF
+;
+#IF (SDMODE == SDMODE_Z80R)
 	; MUST PRESERVE HL,DE
 	PUSH	DE
 	LD	A,1
@@ -2180,38 +2264,48 @@ SD_GET:
 	RL	E
 	LD	A,E
 	POP	DE
-    #ELSE
+#ENDIF
+;
+#IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_N8) | (SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_DSD) | (SDMODE == SDMODE_USR) | (SDMODE == SDMODE_PIO))
 	LD	B,8			; RECEIVE 8 BITS (LOOP 8 TIMES)
 	LD	A,(SD_OPRVAL)		; LOAD CURRENT OPR VALUE
 SD_GET1:
 	XOR	SD_CLK			; TOGGLE CLOCK
 	OUT	(SD_OPRREG),A		; UPDATE CLOCK
 	IN	A,(SD_INPREG)		; READ THE DATA WHILE CLOCK IS ACTIVE
-      #IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_PIO))
+  #IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_PIO))
 	RLA				; ROTATE INP:7 INTO CF
-      #ENDIF
-      #IF (SDMODE == SDMODE_N8)
+  #ENDIF
+  #IF (SDMODE == SDMODE_N8)
 	RLA				; ROTATE INP:6 INTO CF
 	RLA				; "
-      #ENDIF
-      #IF (SDMODE == SDMODE_UART)
+  #ENDIF
+  #IF (SDMODE == SDMODE_UART)
 	RLA				; ROTATE INP:5 INTO CF
 	RLA				; "
 	RLA				; "
-      #ENDIF
-      #IF (SDMODE == SDMODE_DSD)
+  #ENDIF
+  #IF (SDMODE == SDMODE_DSD)
 	RRA				; ROTATE INP:0 INTO CF
-      #ENDIF
+  #ENDIF
 	RL	C			; ROTATE CF INTO C:0
 	LD	A,(SD_OPRVAL)		; BACK TO INITIAL VALUES (TOGGLE CLOCK)
 	OUT	(SD_OPRREG),A		; DO IT
 	DJNZ	SD_GET1			; REPEAT FOR ALL 8 BITS
 	LD	A,C			; GET BYTE RECEIVED INTO A
-      #IF (SDMODE == SDMODE_UART)
+  #IF (SDMODE == SDMODE_UART)
 	XOR	$FF			; DO IS INVERTED ON UART
-      #ENDIF
-    #ENDIF
   #ENDIF
+#ENDIF
+;
+#IF (SDMODE == SDMODE_FZ80)
+	CALL	SD_WAITBSY		; WAIT FOR PENDING ACTIVITY
+	IN	A,(SD_ACTION)		; INITIATE READ
+	CALL	SD_WAITBSY		; WAIT FOR DONE
+	IN	A,(SD_DATA)		; GET THE VALUE
+	;;;CALL	PC_SPACE		; *DEBUG*
+	;;;CALL	PC_LT			; *DEBUG*
+	;;;CALL	PRTHEXBYTE		; *DEBUG*
 #ENDIF
 	RET
 ;

Source/HBIOS/sser.asm

@@ -4,16 +4,6 @@
 ;==================================================================================================
 ;
 ; TODO:
-;
-;;;;SSER_IOBASE	.EQU	$34
-;;;;;
-;;;;SSER_STATUS	.EQU	SSER_IOBASE
-;;;;SSER_DATA	.EQU	SSER_IOBASE + 1
-;;;;;
-;;;;SSER_IRDY	.EQU	%00000001
-;;;;SSER_IINV	.EQU	FALSE
-;;;;SSER_ORDY	.EQU	%00000010
-;;;;SSER_OINV	.EQU	TRUE
 ;
 		DEVECHO	"SSER: IO="
 		DEVECHO	SSERSTATUS
@@ -37,8 +27,8 @@ SSER_PREINIT:
 ;
 SSER_INIT:
 	CALL	NEWLINE
-	PRTS("SSER$")
-	PRTS(": IO=0x$")		; FORMATTING
+	PRTS("SSER:$")
+	PRTS(" IO=0x$")			; FORMATTING
 	LD	A,SSERSTATUS
 	CALL	PRTHEXBYTE
 ;

Source/HBIOS/std.asm

@@ -222,6 +222,7 @@ SDMODE_USR	.EQU	10		; USER DEFINED (in sd.asm) (NOT COMPLETE)
 SDMODE_PIO	.EQU	11		; Z80 PIO bitbang
 SDMODE_Z80R	.EQU	12		; Z80 Retro
 SDMODE_EPITX	.EQU	13		; Mini ITX Z180
+SDMODE_FZ80	.EQU	14		; S100 FPGA Z80
 ;
 ; AY SOUND CHIP MODE SELECTIONS
 ;
@@ -235,6 +236,7 @@ AYMODE_LINC	.EQU	6		; LINC Z50 AY SOUND CARD
 AYMODE_MBC	.EQU	7		; MBC SOUND BOARD
 AYMODE_DUO	.EQU	8		; MBC SOUND BOARD
 AYMODE_NABU	.EQU	9		; NABU BUILT-IN SOUND
+AYMODE_RCGSJ	.EQU	10		; LES BIRD'S RCBUS GRAPHICS, SOUND, JOYSTICK
 ;
 ; SN SOUND CHIP MODE SELECTIONS
 ;

Source/Images/hd_bp.txt

@@ -40,6 +40,7 @@
 ../../Binary/Apps/vgmplay.com 15:
 #
 ../../Binary/Apps/Test/*.com 2:
+../../Binary/Apps/Test/*.doc 2:
 Test/*.* 2:
 #
 # Add Tune sample files

Source/Images/hd_cpm22.txt

@@ -36,6 +36,7 @@ d_cpm22/ReadMe.txt 0:
 ../../Binary/Apps/vgmplay.com 0:
 #
 ../../Binary/Apps/Test/*.com 2:
+../../Binary/Apps/Test/*.doc 2:
 Test/*.* 2:
 #
 # Add Tune sample files

Source/Images/hd_cpm3.txt

@@ -52,6 +52,7 @@
 ../../Binary/Apps/vgmplay.com 0:
 #
 ../../Binary/Apps/Test/*.com 2:
+../../Binary/Apps/Test/*.doc 2:
 Test/*.* 2:
 #
 # Add Tune sample files

Source/Images/hd_nzcom.txt

@@ -53,6 +53,7 @@ d_zsdos/u0/*.* 0:
 ../../Binary/Apps/vgmplay.com 0:
 #
 ../../Binary/Apps/Test/*.com 2:
+../../Binary/Apps/Test/*.doc 2:
 Test/*.* 2:
 #
 # Add Tune sample files

Source/Images/hd_qpm.txt

@@ -40,6 +40,7 @@ d_cpm22/u0/*.* 0:
 ../../Binary/Apps/vgmplay.com 0:
 #
 ../../Binary/Apps/Test/*.com 2:
+../../Binary/Apps/Test/*.doc 2:
 Test/*.* 2:
 #
 # Add Tune sample files

Source/Images/hd_zpm3.txt

@@ -51,6 +51,7 @@
 ../../Binary/Apps/vgmplay.com 15:
 #
 ../../Binary/Apps/Test/*.com 2:
+../../Binary/Apps/Test/*.doc 2:
 Test/*.* 2:
 #
 # Add Tune sample files

Source/Images/hd_zsdos.txt

@@ -49,6 +49,7 @@ d_cpm22/u0/XSUB.COM 0:
 ../../Binary/Apps/vgmplay.com 0:
 #
 ../../Binary/Apps/Test/*.com 2:
+../../Binary/Apps/Test/*.doc 2:
 Test/*.* 2:
 #
 # Add Tune sample files

Source/ver.inc

@@ -2,7 +2,7 @@
 #DEFINE	RMN	5
 #DEFINE	RUP	0
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.5.0-dev.49"
+#DEFINE BIOSVER	"3.5.0-dev.55"
 #define rmj	RMJ
 #define rmn	RMN
 #define rup	RUP

Source/ver.lib

@@ -3,5 +3,5 @@ rmn	equ	5
 rup	equ	0
 rtp	equ	0
 biosver	macro
-	db	"3.5.0-dev.49"
+	db	"3.5.0-dev.55"
 	endm