Minor Doc Updates

- Clarified Memory Manager and MMU terminology.

.github/workflows/release.yml

@@ -52,6 +52,21 @@ jobs:
           title: "${{env.TITLE}} ${{github.ref_name}}"
           files: |
             RomWBW-${{github.ref_name}}-Package.zip
+
+      - name: Build Docs
+        run: |
+          export TZ='America/Los_Angeles'
+          sudo apt-get install gpp pandoc
+          pip install mkdocs
+          make -C Source/Doc deploy_mkdocs
+          mkdocs build -f Source/Doc/mkdocs.yml
+
+      - name: Deploy Docs
+        uses: peaceiris/actions-gh-pages@v4
+#       if: github.ref == 'refs/heads/master'
+        with:
+          github_token: ${{ secrets.GITHUB_TOKEN }}
+          publish_dir: Source/Doc/site
       
 #      - name: Upload Package Archive
 #        uses: AButler/upload-release-assets@v2.0.2

.gitignore

@@ -77,7 +77,6 @@ Tools/unix/zx/zx
 
 !Source/ver.lib
 !Source/Apps/FAT/FAT.COM
-!Source/Apps/copysl/copysl.com
 !Source/Apps/ZMP/zmpx.com
 !Source/Apps/ZMD/zmdsubs.rel
 !Source/Apps/Test/vdctest/font.asm
@@ -121,11 +120,14 @@ Binary/Apps/Tunes/inchina.vgm
 Binary/Apps/Tunes/shirakaw.vgm
 Binary/Apps/Tunes/startdem.vgm
 Binary/Apps/Tunes/wonder01.vgm
+Binary/Apps/copysl.doc
 Binary/Apps/fdu.doc
 Binary/Apps/zmconfig.ovr
 Binary/Apps/zminit.ovr
 Binary/Apps/zmp.doc
 Binary/Apps/zmp.hlp
+Binary/Apps/zmp.cfg
+Binary/Apps/zmp.fon
 Binary/Apps/zmterm.ovr
 Binary/Apps/zmxfer.ovr
 Binary/CPM3/bdos3.spr
@@ -144,8 +146,7 @@ Binary/CPNET/cpn12ser.lbr
 Binary/CPNET/cpn3duo.lbr
 Binary/CPNET/cpn3mt.lbr
 Binary/CPNET/cpn3ser.lbr
-Binary/RCEZ80_std.upd
-Binary/RCZ80_std.upd
+Binary/*.upd
 Binary/ZPM3/bnkbdos3.spr
 Binary/ZPM3/bnkbios3.spr
 Binary/ZPM3/gencpm.dat
@@ -174,74 +175,17 @@ Source/Fonts/fontcgau.asm
 Source/Fonts/fontvgarcc.asm
 Source/Fonts/fontvgarcc.bin
 Source/Fonts/fontvgarcu.asm
-Source/HBIOS/RCEZ80_std.upd
-Source/HBIOS/RCZ80_std.upd
+Source/HBIOS/*.upd
 Source/HBIOS/build_env.cmd
 Source/HBIOS/hbios_env.sh
+Source/HBIOS/netboot.mod
+Source/Images/*.cat
+Source/Images/*.img
 Source/Images/blank144
 Source/Images/blankhd1k
 Source/Images/blankhd512
-Source/Images/fd144_aztecc.img
-Source/Images/fd144_bascomp.img
-Source/Images/fd144_cowgol.img
-Source/Images/fd144_cpm22.img
-Source/Images/fd144_cpm3.img
-Source/Images/fd144_fortran.img
-Source/Images/fd144_games.img
-Source/Images/fd144_hitechc.img
-Source/Images/fd144_nzcom.img
-Source/Images/fd144_qpm.img
-Source/Images/fd144_tpascal.img
-Source/Images/fd144_ws4.img
-Source/Images/fd144_z80asm.img
-Source/Images/fd144_zpm3.img
-Source/Images/fd144_zsdos.img
-Source/Images/hd1k_aztecc.img
-Source/Images/hd1k_bascomp.img
-Source/Images/hd1k_blank.img
-Source/Images/hd1k_bp.img
-Source/Images/hd1k_combo.img
-Source/Images/hd1k_cowgol.img
-Source/Images/hd1k_cpm22.img
-Source/Images/hd1k_cpm3.img
-Source/Images/hd1k_fortran.img
-Source/Images/hd1k_games.img
-Source/Images/hd1k_hitechc.img
-Source/Images/hd1k_nzcom.img
-Source/Images/hd1k_qpm.img
-Source/Images/hd1k_tpascal.img
-Source/Images/hd1k_ws4.img
-Source/Images/hd1k_z80asm.img
-Source/Images/hd1k_zpm3.img
-Source/Images/hd1k_zsdos.img
-Source/Images/hd512_aztecc.img
-Source/Images/hd512_bascomp.img
-Source/Images/hd512_blank.img
-Source/Images/hd512_combo.img
-Source/Images/hd512_cowgol.img
-Source/Images/hd512_cpm22.img
-Source/Images/hd512_cpm3.img
-Source/Images/hd512_dos65.img
-Source/Images/hd512_fortran.img
-Source/Images/hd512_games.img
-Source/Images/hd512_hitechc.img
-Source/Images/hd512_nzcom.img
-Source/Images/hd512_qpm.img
-Source/Images/hd512_tpascal.img
-Source/Images/hd512_ws4.img
-Source/Images/hd512_z80asm.img
-Source/Images/hd512_zpm3.img
-Source/Images/hd512_zsdos.img
-Source/RomDsk/rom0_una.dat
-Source/RomDsk/rom0_wbw.dat
-Source/RomDsk/rom128_una.dat
-Source/RomDsk/rom128_wbw.dat
-Source/RomDsk/rom256_una.dat
-Source/RomDsk/rom256_wbw.dat
-Source/RomDsk/rom384_una.dat
-Source/RomDsk/rom384_wbw.dat
-Source/RomDsk/rom896_una.dat
-Source/RomDsk/rom896_wbw.dat
+Source/RomDsk/*.cat
+Source/RomDsk/*.dat
 Source/ZCPR-DJ/zcprdemo.com
 Source/ZPM3/autotog.com
 Source/ZPM3/clrhist.com

Doc/ChangeLog.txt

@@ -1,6 +1,16 @@
-
 Version 3.6
 -----------
+- RDG: Added VDA driver for Xosera FPGA-based VDC
+- MGG: Added COBOL language disk image
+- WDC: Added config options to PCF driver
+- WBW: Enabled dynamic CPU speed update on LCD screen
+- WBW: Improve LPT driver boot messaging when not detected (per Robb Bates)
+- WBW: Correct DS1307 boot date/time display (per Tadeusz Pycio)
+- WBW: Add -DELAY option to TUNE app (per Robb Bates)
+- RDG: Add online documentation site
+- WBW: Added enhanced Hi-Tech C Compiler files from Ladislau Szilagyi
+- WBW: Added boundary check to ram/rom disk driver
+- WBW: Per Peter Onion, switch KERMIT default file xfer mode to binary
 
 Version 3.5.1
 -------------

ReadMe.md

@@ -7,7 +7,7 @@
 **RomWBW Introduction** \
 Version 3.6 \
 Wayne Warthen  ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \
-21 May 2025
+04 Jun 2025
 
 # Overview
 
@@ -49,7 +49,7 @@ Supported hardware features of RomWBW include:
 - Disk drivers for RAM, ROM, Floppy, IDE ATA/ATAPI, CF, SD, USB, Zip,
   Iomega
 - Serial drivers including UART (16550-like), ASCI, ACIA, SIO
-- Video drivers including TMS9918, SY6545, MOS8563, HD6445
+- Video drivers including TMS9918, SY6545, MOS8563, HD6445, Xosera
 - Keyboard (PS/2) drivers via VT8242 or PPI interfaces
 - Real time clock drivers including DS1302, BQ4845
 - Support for CP/NET networking using Wiznet, MT011 or Serial
@@ -340,6 +340,9 @@ let me know if I missed you!
 
 - Les Bird has contributed support for the NABU w/ Option Board
 
+- Rob Gowin created an online documentation site via MkDocs, and
+  contributed a driver for the Xosera FPGA-based video controller.
+
 ## Related Projects
 
 Outside of the hardware platforms adapted to RomWBW, there are a variety

ReadMe.txt

@@ -1,6 +1,6 @@
 RomWBW Introduction
 Wayne Warthen (wwarthen@gmail.com)
-21 May 2025
+04 Jun 2025
 
 
 
@@ -46,7 +46,7 @@ Supported hardware features of RomWBW include:
 - Disk drivers for RAM, ROM, Floppy, IDE ATA/ATAPI, CF, SD, USB, Zip,
   Iomega
 - Serial drivers including UART (16550-like), ASCI, ACIA, SIO
-- Video drivers including TMS9918, SY6545, MOS8563, HD6445
+- Video drivers including TMS9918, SY6545, MOS8563, HD6445, Xosera
 - Keyboard (PS/2) drivers via VT8242 or PPI interfaces
 - Real time clock drivers including DS1302, BQ4845
 - Support for CP/NET networking using Wiznet, MT011 or Serial
@@ -347,6 +347,9 @@ let me know if I missed you!
 
 - Les Bird has contributed support for the NABU w/ Option Board
 
+- Rob Gowin created an online documentation site via MkDocs, and
+  contributed a driver for the Xosera FPGA-based video controller.
+
 
 Related Projects
 

Source/Apps/Tune/cli.inc

@@ -23,6 +23,19 @@ CLI_HAVE_HBIOS_SWITCH1			; NOT MATCHED --HBIOS
 	LD	(HBIOSMD), A
 	RET
 
+CLI_HAVE_DELAY_SWITCH:
+ 	LD	HL, CLIARGS		; TEST FOR --DELAY ON COMMAND LINE
+	LD	DE, DELAYOPT
+	CALL	STRINDEX
+	JR	NZ, CLI_HAVE_DELAY_SWITCH1
+	OR	$FF			; MATCHED --DELAY
+	LD	(DELAYMD), A
+	RET
+CLI_HAVE_DELAY_SWITCH1			; NOT MATCHED --HBIOS
+	XOR	A
+	LD	(DELAYMD), A
+	RET
+
 CLI_PORTS:
  	LD	HL, CLIARGS		; TEST FOR -MSX ON COMMAND LINE
 	LD	DE, OPT_MSX
@@ -101,7 +114,8 @@ CLI_OCTAVE_ADJST5:
 
 OPT_MSX		.DB	"-MSX", 0			; USE MSX PORTS
 OPT_RC		.DB	"-RC", 0			; USE RC PORTS
-HBIOSOPT:	.DB	"--HBIOS", 0
+HBIOSOPT:	.DB	"--HBIOS", 0			; USE HBIOS API FOR PLAYBACK
+DELAYOPT:	.DB	"-DELAY",0			; FORCE DELAY MODE
 DOWN1		.DB	"-t1", 0			; DOWN AN OCTAVE
 DOWN2		.DB	"-t2", 0			; DOWN TWO OCTAVE
 UP1		.DB	"+t1", 0			; UP AN OCTAVE

Source/Apps/Tune/timing.inc

@@ -41,8 +41,14 @@ DLY1	DEC	BC              	; [6]
 ; Test for timer running to determine if it can be used for delay
 ; Return string message in DE
 ; Assigned (WMOD) with 0 if no hardware time, 1 if hardware timer found
+; If -DELAY on command line, force delay mode
 ;
 PROBETIMER:
+	LD	A,(DELAYMD)		; GET COMMAND LINE DELAY FLAG
+	OR	A			; TEST IT
+	LD	A,0			; ASSUME NO TIMER
+	LD	DE,MSGDLY		; DELAY MODE MESSAGE
+	JR	NZ,SETDLY		; IF TRUE, DONE
 	LD	B,BF_SYSGET		; HBIOS: GET function
 	LD	C,$D0			; TIMER subfunction
 	RST	08			; DE:HL := current tick count

Source/Apps/Tune/tune.asm

@@ -53,6 +53,7 @@
 ;   2024-07-11 [WBW] Updated, Les Bird's module now uses same settings as EB6
 ;   2024-09-17 [WBW] Add support for HEATH H8 with Les Bird's MSX Card
 ;   2024-12-12 [WBW] Add options to force standard MSX or RC ports
+;   2025-05-28 [WBW] Add option to force delay mode
 ;_______________________________________________________________________________
 ;
 ; ToDo:
@@ -113,6 +114,7 @@ Id		.EQU	1	; 5) Insert official identificator
 	CALL	CLI_ABRT_IF_OPT_FIRST
 	CALL	CLI_PORTS
 	CALL	CLI_HAVE_HBIOS_SWITCH
+	CALL	CLI_HAVE_DELAY_SWITCH
 	CALL	CLI_OCTAVE_ADJST
 	JP	CONTINUE
 
@@ -703,15 +705,16 @@ FILTYP		.DB	0	; Sound file type (TYPPT2, TYPPT3, TYPMYM)
 TMP		.DB	0	; work around use of undocumented Z80
 
 HBIOSMD		.DB	0	; NON-ZERO IF USING HBIOS SOUND DRIVER, ZERO OTHERWISE
+DELAYMD		.DB	0	; FORCE DELAY MODE IF TRUE (NON-ZERO)
 OCTAVEADJ	.DB	0	; AMOUNT TO ADJUST OCTAVE UP OR DOWN
 
 USEPORTS	.DB	0	; AUDIO CHIP PORT SELECTION MODE
 
-MSGBAN		.DB	"Tune Player for RomWBW v3.12, 12-Dec-2024",0
-MSGUSE		.DB	"Copyright (C) 2024, Wayne Warthen, GNU GPL v3",13,10
+MSGBAN		.DB	"Tune Player for RomWBW v3.13, 28-May-2025",0
+MSGUSE		.DB	"Copyright (C) 2025, Wayne Warthen, GNU GPL v3",13,10
 		.DB	"PTxPlayer Copyright (C) 2004-2007 S.V.Bulba",13,10
 		.DB	"MYMPlay by Marq/Lieves!Tuore",13,10,13,10
-		.DB	"Usage: TUNE <filename>.[PT2|PT3|MYM] [-msx|-rc] [--hbios] [+tn|-tn]",0
+		.DB	"Usage: TUNE <filename>.[PT2|PT3|MYM] [-msx|-rc] [-delay] [--hbios] [+tn|-tn]",0
 MSGBIO		.DB	"Incompatible BIOS or version, "
 		.DB	"HBIOS v", '0' + RMJ, ".", '0' + RMN, " required",0
 MSGPLT		.DB	"Hardware error, system not supported!",0

Source/CPM22/ReadMe.txt

@@ -38,7 +38,7 @@ It is an independent disassembly and reconstruction of CCP/BDOS.
 DRI CPM22PAT01 was already applied.  Unclear why, but the BDOS
 source was checking for a blank instead of a ctrl-s in the
 KBSTAT routine.  Ctrl-s seems to be correct based on all other
-BDOS images I have encountered.  Also, these files imbed the
+BDOS images I have encountered.  Also, these files embed the
 CP/M version number into the serial number fields.  Other than
 this, they are byte identical to the OS2CCP/OS3BDOS images above.
 
@@ -51,17 +51,24 @@ BDOS22.ASM - Modified ORG & fix for ctrl-S
 CCPB03 & BDOSB01
 ----------------
 
-Sourced from N8VEM effort to create an enhanced
-variant of CP/M 2.2.
+These files were derived from a disassembly of the Jade DD CP/M-80
+image by William Beech in 1982.
 
-It appears to be a disassembly and reconstruction of CCP/BDOS,
-but there are no comments attributing the work.  DRI CPM22PAT01
-was already applied.  The message string literals are all
+- Modified by Bill Beech for global CP/M size configuration
+  and separate CCP and BDOSE 2013.
+
+- Modified by Bill Beech for addition of MON
+  command and display/change of user on command line
+  1984.  Also removed all SN checks.
+
+Eventually modified as part of the N8VEM project and converted to
+the Z80 instruction set.
+
+DRI CPM22PAT01 has been applied.  The message string literals are all
 in CAPS in BDOS.  Additionally, there is explicit filler of 0x55
 value bytes at the end of the CCP/BDOS files padding their
 length out to full page.  Other than this, the BDOS
-is byte identical to the others above.  CCP contains multiple
-enhancements and is, therefore, not identical to others.
+is byte identical to the others above.
 
 CCPB03.ASM - Enhanced reassembly of CCP
 

Source/Doc/Applications.md

@@ -2438,10 +2438,11 @@ whether support for it is included in the RomWBW HBIOS configuration
 |  `-MSX`     | Force MSX port addresses A0H/A1H (no PSG detection)    |
 |  `-RC`      | Force RCBus port addresses D8H/D0H (no PSG detection)  |
 |  `--HBIOS`  | Utilise HBIOS' sound driver                            |
-| `+T1`       | Play tune an octave higher                             |
-| `+T2`       | Play tune two octaves higher                           |
-| `-T1`       | Play tune an octave lower                              |
-| `-T2`       | Play tune two octaves lower                            |
+|  `-DELAY`   | Force delay mode (don't use hardware timer)            |
+|  `+T1`      | Play tune an octave higher                             |
+|  `+T2`      | Play tune two octaves higher                           |
+|  `-T1`      | Play tune an octave lower                              |
+|  `-T2`      | Play tune two octaves lower                            |
 
 The +t and -t options apply only to HBIOS mode operation.  The `-MSX`,
 `-RC`, and `--HBIOS` options are mutually exclusive.  See Notes below.
@@ -2465,7 +2466,7 @@ an error message.
 
 Some hardware (notably Why-Em-Ulator) cannot be detected due limitations
 of the emulation.  In such cases, you can force the use of the two
-most common port addresses using the `-msx` or `-rc` options.
+most common port addresses using the `-MSX` or `-RC` options.
 
 On Z180 systems, I/O wait states are added when writing to the sound
 chip to avoid exceeding its speed limitations. On Z80 systems, you
@@ -2473,9 +2474,13 @@ will need to ensure that the CPU clock speed of your system does not
 exceed the timing limitations of your sound chip.
 
 The application probes for an active system timer and uses it to
-accurately pace the sound file output. If no system timer is
+accurately pace the sound file playback. If no system timer is
 available, a delay loop is calculated instead. The delay loop will not
-be as accurate as the system timer.
+be as accurate as the system timer.  If the `-DELAY` options is
+specified on the command line, then the delay loop will be used
+regardless of whether the system has a hardware timer.  This is useful
+if the hardware timer does not run at the 50Hz desired for sound
+playback.
 
 There are two modes of operation.  A direct hardware interface for the
 AY-3-8910 or YM2149 chips, or a compatibility layer thru HBIOS supporting

Source/Doc/Basic.h

@@ -14,7 +14,14 @@ $define{doc_sys}{[RomWBW System Guide]($doc_root$/RomWBW System Guide.pdf)}$
 $define{doc_apps}{[RomWBW Applications]($doc_root$/RomWBW Applications.pdf)}$
 $define{doc_catalog}{[RomWBW Disk Catalog]($doc_root$/RomWBW Disk Catalog.pdf)}$
 $define{doc_hardware}{[RomWBW Hardware]($doc_root$/RomWBW Hardware.pdf)}$
-
+$ifdef{GFM}$
+  $define{doc_intro}{[RomWBW Introduction](Introduction.md)}$
+  $define{doc_user}{[RomWBW User Guide](UserGuide.md)}$
+  $define{doc_sys}{[RomWBW System Guide](SystemGuide.md)}$
+  $define{doc_apps}{[RomWBW Applications](Applications.md)}$
+  $define{doc_catalog}{[RomWBW Disk Catalog](Catalog.md)}$
+  $define{doc_hardware}{[RomWBW Hardware](Hardware.md)}$
+$endif$
 ---
 title: $doc_product$ $doc_title$
 subtitle: $doc_ver$

Source/Doc/Catalog.md

@@ -573,7 +573,7 @@ This is a generic ZPM3 adaptation for RomWBW.
 
 The following files came from from Microcode Consulting. The official
 distribution files can be found on the Microcode Consulting website at
-[https://www.microcodeconsulting.com/z80/qpm.htm].
+<https://www.microcodeconsulting.com/z80/qpm.htm>.
 Also included in this image are debugz, and linkz frm the same company.
 
 This disk includes the standard DRI CP/M 2.2 files in addition to the
@@ -651,7 +651,7 @@ look a little strange depending on the terminal emulation you are using.
 
 User area 4 contains a full implementation of the CP/NET 1.2 client 
 provided by Doug Miller. Please refer to
-[https://github.com/durgadas311/cpnet-z80] for more information, 
+<https://github.com/durgadas311/cpnet-z80> for more information, 
 complete documentation and the latest source code.
 
 Please refer to the RomWBW User Guide for instructions on installing
@@ -979,7 +979,7 @@ The following files are found in
 | `ZEXDOC.COM`        | Z80 Instruction Set Exerciser                           |
 
 And The following CPU Tests - Which are probably originally from this source. 
-[https://github.com/raxoft/z80test]
+<https://github.com/raxoft/z80test>
 
 | **File**       | **Description**                                               |
 |----------------|---------------------------------------------------------------|
@@ -1002,7 +1002,7 @@ including MS-DOS, Apple II DOS 3.3 and PRoDOS, Commodore 64, Macintosh and
 Amiga. This disk contains the CP/M version of that compiler. A cross-compiler
 for MS-DOS or Windows XP is also available.
 
-For full documentation, see [https://www.aztecmuseum.ca] 
+For full documentation, see <https://www.aztecmuseum.ca> 
 The user manual is available in the Doc/Language directory
 Aztec_C_1.06_User_Manual_Mar84.pdf
 
@@ -1048,10 +1048,10 @@ NOTE : The above is incomplete
 
 The Cowgol 2.0 compiler and related tools.
 These files were provided by Ladislau Szilagyi and were sourced
-from his GitHub repository at [https://github.com/Laci1953/Cowgol_on_CP_M].
+from his GitHub repository at <https://github.com/Laci1953/Cowgol_on_CP_M>.
 
 The primary distribution site for Cowgol 2.0 is at
-[https://github.com/davidgiven/cowgol].
+<https://github.com/davidgiven/cowgol>.
 The user manual is available in the Doc/Language directory
 Cowgol Language.pdf
 
@@ -1061,23 +1061,64 @@ The following files are found in
 
 | **File**     | **Description**                            |
 |--------------|--------------------------------------------|
-| ADVENT.COW   | Adventure game program source              |
-| ADVENT.SUB   | Submit file to build ADVENT                |
-| ADVENT?.TXT  | Adventure game program resource            |
-| ADVMAIN.COW  | Adventure game program source              |
-| RAND.AS      | Assembler Library File                     |
-| COWBE.COM    |                                            |
-| COWFE.COM    | RomWBW specific (Memory Manage) version    |
-| COWLINK.COM  |                                            |
-| DYNMSORT.COW | demonstrates a sort algorithm              |
-| DYNMSORT.SUB | Submit file to build DYNMSORT              |
-| HEXDUMP.COW  | a simple hex dump utility, purely a Cowgol |
-| HEXDUMP.SUB  | Submit file to build HEXDUMP               |
-| HMERGES.C    | C Library File                             |
-| XRND.AS      | Assembler Library File                     |
-| -            | -                                          |
-
-NOTE : The above is incomplete
+| $EXEC.COM    | HiTech C batch processor which launches the Cowgol toolchain executables |
+| ADVENT.COW   | Adventure game program source |
+| ADVENT.SUB   | SUBMIT file to build Adventure game |
+| ADVENT?.TXT  | Adventure game program resources |
+| ADVMAIN.COW  | Adventure game program source |
+| ADVTRAV.COW  | Adventure game component source |
+| ARGV.COH     | Cowgol include file providing command line argument processing |
+| C.LIB        | Hi-Tech C runtime library |
+| CGEN.COM     | HiTech C compiler pass 2 |
+| COMMFILE.COH | Include file providing file I/O |
+| COMMON.COH   | Include file providing common functions |
+| COWBE.COM    | Cowgol back end which builds the cowgol object files (optimized) |
+| COWFE.COM    | Cowgol front end which parses the source file (optimized) |
+| COWFIX.COM   | Interface to Z80AS -- performs code optimizations |
+| COWGOL.COH   | Include file providing standard Cowgol functions |
+| COWGOL.COM   | Interprets the command line and generates $EXEC run requests (a variant of HiTech C.COM) |
+| COWGOL.COO   | Cowgol object file with ??? |
+| COWGOL.LIB   | ??? |
+| COWGOLC.COH  | Cowgol include file providing ??? |
+| COWLINK.COM  | Cowgol linker which binds all the cowgol object files and outputs a Z80 assembler file (optimized) |
+| CPP.COM      | HiTech C pre-processor, modified to accept // style comments |
+| DYNMSORT.COW | Sort algorithm sample program source |
+| DYNMSORT.SUB | SUBMIT file to build DYNMSORT sample application |
+| FACT.COW     | Factorial computation sample program source |
+| FILE.COH     | Include file providing CP/M file processing support |
+| FILEIO.COH   | Include file providing CP/M file processing support |
+| HEXDUMP.COW  | Hex file dump sample  source |
+| HEXDUMP.SUB  | SUBMIT file to build HEXDUMP sample program |
+| LIBBASIC.COH | Include file providing ??? |
+| LIBBIOS.COH  | Include file providing ??? |
+| LIBCONIO.COH | Include file providing console I/O |
+| LIBFP.COH    | Include file providing floating point support |
+| LIBR.COM     | HiTech object file librarian |
+| LIBSTR.COH   | Include file providing string functions |
+| LINK.COM     | HiTech linker which builds the final executable from object and library files |
+| MALLOC.COH   | Include file providing dynamic memory management functions |
+| MERGES.C     | Merge sort sample function C language source |
+| MISC.COH     | Include file providing miscellaneous functions |
+| MISC.COO     | Miscellaneous functions object file |
+| MISC.COW     | Miscellaneous functions source file |
+| OPTIM.COM    | HiTech C compiler optimizer |
+| P1.COM       | HiTech C compiler first pass |
+| RAND.AS      | Pseudo-random number generator source in assembly language |
+| RANFILE.COH  | Include file providing random file access functions |
+| RANFILE.COO  | Random file access functions object file |
+| RANFILE.COW  | Random file access functions source file |
+| README.TXT   | Cowgol disk image release notes |
+| SEQFILE.COH  | Include file providing sequential file access functions |
+| SEQFILE.COO  | Sequential file access functions object file |
+| SEQFILE.COW  | Sequential file access functions source file |
+| STDCOW.COH   | Include file providing standard library functions |
+| STRING.COH   | Include file providing string functions |
+| STRING.COO   | String functions object file |
+| STRING.COW   | String functions source file |
+| STRINGS.COH  | Include file implementing string functions |
+| TESTAS.COW   | Assembly language interface sample program source |
+| TESTAS.SUB   | SUBMIT file to build TESTAS sample program |
+| Z80AS.COM    | Z80 assembler which assembles the output of COWFIX and other Z80 source files (see <https://github.com/Laci1953/Z80AS>) |
 
 ## Microsoft Fortran 80 (Fortran)
 
@@ -1114,12 +1155,12 @@ Zork 1 through 3, Planetfall and Hitchhiker's Guide to the Galaxy.
 Nemesis and Dungeon Master is a Rogue-like game released in 1981. It is playable
 on a text terminal using ASCII graphics to represent the dungeon. Only a few
 thousand copies of the game were ever made, making it very rare. See
-[http://crpgaddict.blogspot.com/2019/03/game-322-nemesis-1981.html]
+<http://crpgaddict.blogspot.com/2019/03/game-322-nemesis-1981.html>
 
 Colossal Cave Adventure is a CP/M port of the 1976 classic game originally
 written by Will Crowther for the PDP-10 mainframe. See
-[https://en.wikipedia.org/wiki/Colossal_Cave_Adventure] and
-[https://if50.substack.com/p/1976-adventure]
+<https://en.wikipedia.org/wiki/Colossal_Cave_Adventure> and
+<https://if50.substack.com/p/1976-adventure>
 
 The following files are found in
 
@@ -1144,13 +1185,32 @@ which produce programs for  execution  in  embedded  systems
 without an operating system.
 
 This is the Mar 21, 2023 update 17 released by Tony Nicholson who currently
-maintains HI-TECH C at [https://github.com/agn453/HI-TECH-Z80-C]
+maintains HI-TECH C at <https://github.com/agn453/HI-TECH-Z80-C>
 
 The manual is available in the Doc/Language directory,
 HI-TECH Z80 C Compiler Manual.txt
 
 A good blog post about the HI-TECH C Compiler is available at
-[https://techtinkering.com/2008/10/22/installing-the-hi-tech-z80-c-compiler-for-cpm]
+<https://techtinkering.com/2008/10/22/installing-the-hi-tech-z80-c-compiler-for-cpm>
+
+User area 1 contains another complete copy of the HI-TECH C Compiler.
+It is identical to the copy in user area 0 except for the following files
+which were enhanced by Ladislau Szilagyi from his GitHub Repository at
+<https://github.com/Laci1953/HiTech-C-compiler-enhanced>.  The files
+take advantage of additional banked memory using the RomWBW HBIOS API.
+As such, they require RomWBW to operate.  They should be compatible with
+all CP/M and compatible operations systems provided in RomWBW.
+
+The enhanced files are:
+
+- CGEN.COM
+- CPP.COM
+- OPTIM.COM
+- P1.COM
+- ZAS.COM (replaced with Z80AS)
+
+A thread discussing this enhanced version of HI-TECH C is found at
+<https://groups.google.com/g/rc2014-z80/c/sBCCIpOnnGg>.
 
 The following files are found in
 
@@ -1170,7 +1230,7 @@ NOTE : The above is incomplete
 The collection of MSX ROMs (2 disks) as provided by Les Bird.  
 These ROMs are "run" by using the
 appropriate variant of Les' MSX8 ROM loader.  You can download the
-loader binaries from [https://github.com/lesbird/MSX8].  You will need
+loader binaries from <https://github.com/lesbird/MSX8>.  You will need
 appropriate hardware to run the loader.
 
 Please review the file ROMLIST.TXT for information on the current
@@ -1206,7 +1266,7 @@ The manual can be found in the Docs/Language directory,
 Turbo_Pascal_Version_3.0_Reference_Manual_1986.pdf
 
 A good overview of using Turbo Pascal in CP/M is available at
-[https://techtinkering.com/2013/03/05/turbo-pascal-a-great-choice-for-programming-under-cpm]
+<https://techtinkering.com/2013/03/05/turbo-pascal-a-great-choice-for-programming-under-cpm>
 
 The following files are found in
 
@@ -1358,10 +1418,10 @@ The manual(s) are available in the Doc/Language directory,
 * Z80DIS User Manual (1985).pdf
 
 A run through of using the assembler is available at
-[https://8bitlabs.ca/Posts/2023/05/20/learning-z80-asm]
+<https://8bitlabs.ca/Posts/2023/05/20/learning-z80-asm>
 
 And another shorter, but shows linker usage guide
-[https://pollmyfinger.wordpress.com/2022/01/10/modular-retro-z80-assembly-language-programming-using-slr-systems-z80asm-and-srlnk/]
+<https://pollmyfinger.wordpress.com/2022/01/10/modular-retro-z80-assembly-language-programming-using-slr-systems-z80asm-and-srlnk/>
 
 The following files are found in
 

Source/Doc/Hardware.md

@@ -40,14 +40,19 @@ KIO refers to a Zilog specific Serial/Parallel Counter/Timer (Z84C90).
 The RCBus Z180 & Z280 require a separate RAM/ROM memory module. There are two types
 of these modules, you must pick the correct ROM for your type of memory module:
 
-* The RCBus Z180 & Z280 require a separate RAM/ROM memory module. There are two types
-  of these modules, you must pick the correct ROM for your type of memory module:
-* The second type of RAM/ROM module has no bank switching logic – this is called
-  (“Native”) because the CPU itself provides the bank switching logic.
+* The first type of RAM/ROM module includes Z2 style memory bank
+  switching on the memory module itself.  This is called "External" (ext)
+  because the bank switching is external from the CPU itself.
+
+* The second type of RAM/ROM module has no bank switching logic on the
+  memory module.  Bank switching is implemented via the Z180 or Z280
+  MMU – this is called “Native” (nat) because the CPU itself provides
+  the bank switching logic.
 
 Only Z180 and Z280 CPUs have the ability to do bank switching in the
 CPU, so the ext/nat selection only applies to them.  Z80 CPUs have no
-built-in bank switching logic, so they are always configured for
+built-in bank switching logic, so they always require a RAM/ROM module
+with Z2 style bank switching and the ROMs are always configured for
 external bank switching.
 
 `\clearpage`{=latex}
@@ -106,26 +111,26 @@ Others
 
 | **Description**                                             | **Bus**  | **ROM Image File**          | **Baud Rate** |
 |-------------------------------------------------------------|----------|-----------------------------|--------------:|
-| [Dyno Z180 SBC]^6^                                          | Dyno     | DYNO_std.rom                |         38400 |
-| [EP Mini-ITX Z180]^11^                                      | UEXT     | EPITX_std.rom               |        115200 |
-| [eZ80 for RCBus Module]^13^, 512K RAM/ROM                   | RCBus    | RCEZ80_std.rom              |        115200 |
-| [Genesis Z180 System]^12^                                   | STD      | GMZ180_std.rom              |        115200 |
-| [Heath H8 Z80 System]^10^                                   | H8       | HEATH_std.rom               |        115200 |
-| [NABU w/ RomWBW Option Board]^10^                           | NABU     | NABU_std.rom                |        115200 |
-| [S100 Computers Z180 SBC]^9^                                | S100     | S100_std.rom                |         57600 |
-| [S100 Computers FPGA Z80 SBC]^9^                            | S100     | FZ80_std.rom                |          9600 |
-| [UNA Hardware BIOS]^3^                                      | -        | UNA_std.rom                 |             - |
-| [Z80-Retro SBC]^8^                                          | -        | Z80RETRO_std.rom            |         38400 |
-| [Z180 Mark IV SBC]^3^                                       | ECB      | MK4_std.rom                 |         38400 |
+| [Dyno Z180 SBC]^2^                                          | Dyno     | DYNO_std.rom                |         38400 |
+| [EP Mini-ITX Z180]^6^                                       | UEXT     | EPITX_std.rom               |        115200 |
+| [eZ80 for RCBus Module]^8^, 512K RAM/ROM                    | RCBus    | RCEZ80_std.rom              |        115200 |
+| [Genesis Z180 System]^7^                                    | STD      | GMZ180_std.rom              |        115200 |
+| [Heath H8 Z80 System]^5^                                    | H8       | HEATH_std.rom               |        115200 |
+| [NABU w/ RomWBW Option Board]^5^                            | NABU     | NABU_std.rom                |        115200 |
+| [S100 Computers Z180 SBC]^4^                                | S100     | S100_std.rom                |         57600 |
+| [S100 Computers FPGA Z80 SBC]^4^                            | S100     | FZ80_std.rom                |          9600 |
+| [UNA Hardware BIOS]^1^                                      | -        | UNA_std.rom                 |             - |
+| [Z80-Retro SBC]^3^                                          | -        | Z80RETRO_std.rom            |         38400 |
+| [Z180 Mark IV SBC]^1^                                       | ECB      | MK4_std.rom                 |         38400 |
 
-| ^3^Designed by John Coffman
-| ^6^Designed by Steve Garcia
-| ^8^Designed by Peter Wilson
-| ^9^Designed by John Monahan
-| ^10^Designed by Les Bird
-| ^11^Designed by Alan Cox
-| ^12^Designed by Doug Jackson
-| ^13^Designed by Dean Netherton
+| ^1^Designed by John Coffman
+| ^2^Designed by Steve Garcia
+| ^3^Designed by Peter Wilson
+| ^4^Designed by John Monahan
+| ^5^Designed by Les Bird
+| ^6^Designed by Alan Cox
+| ^7^Designed by Doug Jackson
+| ^8^Designed by Dean Netherton
 
 `\clearpage`{=latex}
 
@@ -136,6 +141,11 @@ devices and peripherals that are on-board or frequently used with
 each platform.  If the device or peripheral is not detected at boot, 
 the ROM will simply bypass support appropriately.
 
+Each ROM will support a single memory manager.  This is determined
+by the build configuration and is not dynamically selected.  The use
+of the term Memory Manager is generally synonymous with Memory
+Management Unit (MMU).
+
 In some cases, support for multiple hardware components with potentially
 conflicting resource usage are handled by a single ROM image.  It is up
 to the user to ensure that no conflicting hardware is in use.
@@ -2269,6 +2279,7 @@ the active platform and configuration.
 | VDU       | MC6845 Family Video Display Controller (*)             |
 | VGA       | HD6445CP4-based Video Display Controller               |
 | VRC       | VGARC Video Display Controller                         |
+| XOSERA    | XOSERA FPGA-based Video Display Controller             |
 
 Note:
 

Source/Doc/Introduction.md

@@ -41,7 +41,7 @@ Supported hardware features of RomWBW include:
 * Banked memory services for several banking designs
 * Disk drivers for RAM, ROM, Floppy, IDE ATA/ATAPI, CF, SD, USB, Zip, Iomega
 * Serial drivers including UART (16550-like), ASCI, ACIA, SIO
-* Video drivers including TMS9918, SY6545, MOS8563, HD6445
+* Video drivers including TMS9918, SY6545, MOS8563, HD6445, Xosera
 * Keyboard (PS/2) drivers via VT8242 or PPI interfaces
 * Real time clock drivers including DS1302, BQ4845
 * Support for CP/NET networking using Wiznet, MT011 or Serial
@@ -324,6 +324,10 @@ please let me know if I missed you!
 
 * Les Bird has contributed support for the NABU w/ Option Board
 
+* Rob Gowin created an online documentation site via MkDocs, and
+  contributed a driver for the Xosera FPGA-based video
+  controller.
+
 `\clearpage`{=latex}
 
 ## Related Projects

Source/Doc/Makefile

@@ -18,6 +18,10 @@ include $(TOOLS)/Makefile.inc
 
 all :: deploy
 
+clean ::
+	rm -rf mkdocs
+	rm -rf site
+
 %.tmp : %.md
 	gpp -o $@ -U "$$" "$$" "{" "}{" "}$$" "{" "}" "@@@" "" -M "$$" "$$" "{" "}{" "}$$" "{" "}" $<
 
@@ -31,11 +35,16 @@ all :: deploy
 	pandoc $< -f markdown -t dokuwiki -s -o $@ --default-image-extension=pdf
 
 %.gfm : %.tmp
-	pandoc $< -f markdown -t gfm-yaml_metadata_block -s -o $@ --default-image-extension=pdf
+	pandoc $< -f markdown -t gfm-yaml_metadata_block -s -o $@ --default-image-extension=svg
 
 %.txt : %.tmp
 	pandoc $< -f markdown -t plain -s -o $@ --default-image-extension=pdf
 
+mkdocs/%.md : %.md
+	-mkdir -p mkdocs
+	gpp -DGFM -U "$$" "$$" "{" "}{" "}$$" "{" "}" "@@@" "" -M "$$" "$$" "{" "}{" "}$$" "{" "}" $< \
+	    | pandoc -f markdown -t gfm-yaml_metadata_block -s -o $@ --default-image-extension=svg
+
 deploy :
 	cp Introduction.gfm      "../../ReadMe.md"
 	cp Introduction.txt      "../../ReadMe.txt"
@@ -45,3 +54,10 @@ deploy :
 	cp Applications.pdf      "../../Doc/RomWBW Applications.pdf"
 	cp Catalog.pdf           "../../Doc/RomWBW Disk Catalog.pdf"
 	cp Hardware.pdf          "../../Doc/RomWBW Hardware.pdf"
+
+deploy_mkdocs : mkdocs/Introduction.md mkdocs/UserGuide.md mkdocs/SystemGuide.md mkdocs/Applications.md \
+                mkdocs/Catalog.md mkdocs/Hardware.md mkdocs/ReadMe.md
+	mkdir -p mkdocs/UserGuide/Graphics mkdocs/SystemGuide/Graphics
+	mv mkdocs/ReadMe.md mkdocs/README.md
+	cp Graphics/*.svg        mkdocs/UserGuide/Graphics
+	cp Graphics/*.svg        mkdocs/SystemGuide/Graphics

Source/Doc/SystemGuide.md

@@ -142,6 +142,14 @@ currently selected.  The upper 32KB is "fixed".  This area of memory
 is never swapped out and is used to contain software and operating
 systems that must remain in the Z80 address space.
 
+Throughout this document, this mechanism of selecting banks of memory
+into the lower 32K is referred to as memory management.  Achieving
+this functionality requires some type of hardware which is generally
+referred to as the system's Memory Management Unit (MMU).  RomWBW
+supports a variety of MMUs -- but they all perform the same function
+of swapping in/out banks of memory in the lower 32K of CPU address
+space.
+
 Figure 4.1 depicts the memory layout for a system running the CP/M
 operating system.  Applications residing in TPA invoke BDOS services
 of CP/M, BDOS invokes the custom CBIOS APIs, and finally CBIOS
@@ -290,6 +298,62 @@ Common Bank:
 It is a fixed mapping that is never changed in normal RomWBW operation
 hence the name "Common".
 
+## Memory Managers
+
+The following hardware memory managers are supported by RomWBW.  The
+operation of these memory managers is not documented here -- please
+refer to the documentation of your hardware provider for that.
+
+Z2:
+
+: Memory memory manager introduced by Sergey Kiselv in the Zeta 2 SBC.
+Popular in many RCBus systems.
+
+Z180:
+
+: Memory manager built into the Z180 CPU
+
+Z280:
+
+: Memory manager built into the Z280 CPU
+
+ZRC:
+
+: Memory manager onboard the ZRC series of computers by Bill Shen.
+
+SBC:
+
+: Memory manager onboard the N8VEM SBC series of computers by
+Andrew Lynch.
+
+MBC:
+
+: Memory manager onboard the Nhyodyne computer system by Andrew Lynch.
+
+N8:
+
+: Memory manager onboard the N8 SBC computer by Andrew Lynch.
+
+EZ512:
+
+: Memory manager onboard the EaZy80-512 Z80 CPU Module by Bill Shen.
+
+RPH:
+
+: Memory manager onboard the Rhyophyre computer system by Andrew Lynch.
+
+The memory manager used is determined by the configuration choices
+that are part of a RomWBW build process.  A given ROM can only have a
+single memory manager -- it is not selected dynamically.
+
+The configuration variable `MEMMGR` sets the memory mannager used by
+the ROM build.  It must be set to one of the above memory manager
+types.  For example, for the Z2 memory manager, `MEMMGR` should be set
+to `MM_Z2`.
+
+Note that the term memory manager (MM) and memory management unit (MMU)
+are used interchangeably in the documentation and code.
+
 # Disk Layout
 
 ## Floppy Disk Layout
@@ -1700,14 +1764,17 @@ All video units are assigned a Device Type ID which indicates
 the specific hardware device driver that handles the unit.  The table
 below enumerates their values.
 
-| **Device Type** | **ID** | **Description**                          | **Driver** |
-|-----------------|-------:|------------------------------------------|------------|
-| VDADEV_VDU      | 0x00   | MC6845 Family Video Display Controller   | vdu.asm    |
-| VDADEV_CVDU     | 0x01   | MC8563-based Video Display Controller    | cvdu.asm   |
-| VDADEV_GDC      | 0x02   | uPD7220 Video Display Controller         | gdc.asm    |
-| VDADEV_TMS      | 0x03   | TMS9918/38/58 Video Display Controller   | tms.asm    |
-| VDADEV_VGA      | 0x04   | HD6445CP4-based Video Display Controller | vga.asm    |
-| VDADEV_VRC      | 0x05   | VGARC                                    | vrc.asm    |
+| **Device Type** | **ID** | **Description**                            | **Driver** |
+|-----------------|-------:|--------------------------------------------|------------|
+| VDADEV_VDU      | 0x00   | MC6845 Family Video Display Controller     | vdu.asm    |
+| VDADEV_CVDU     | 0x01   | MC8563-based Video Display Controller      | cvdu.asm   |
+| VDADEV_GDC      | 0x02   | uPD7220 Video Display Controller           | gdc.asm    |
+| VDADEV_TMS      | 0x03   | TMS9918/38/58 Video Display Controller     | tms.asm    |
+| VDADEV_VGA      | 0x04   | HD6445CP4-based Video Display Controller   | vga.asm    |
+| VDADEV_VRC      | 0x05   | VGARC                                      | vrc.asm    |
+| VDADEV_EF       | 0x06   | EF9345                                     | ef.asm     |
+| VDADEV_FV       | 0x07   | S100 FPGA VGA                              | fv.asm     |
+| VDADEV_XOSERA   | 0x08   | Xosera FPGA-based Video Display Controller | xosera.asm |
 
 Depending on the capabilities of the hardware, the use of colors and
 attributes may or may not be supported. If the hardware does not support

Source/Doc/UserGuide.md

@@ -3163,7 +3163,7 @@ floppy disk and hard disk images.
 | TUNE            | Play .PT2, .PT3, .MYM audio files.                                 |
 | INTTEST         | Test interrupt vector hooking.                                     |
 
-# Real Time Clock
+# Real Time Clock & Date/Time Stamping
 
 RomWBW supports a variety of real time clock hardware.  If your
 system has this hardware, then it will be able to maintain the

Source/Doc/mkdocs.yml

@@ -0,0 +1,16 @@
+site_name: RomWBW Documentation V3.6
+repo_url: https://github.com/wwarthen/RomWBW
+edit_uri: ""
+docs_dir: mkdocs
+nav:
+  - Introduction: Introduction.md
+  - User Guide: UserGuide.md
+  - System Guide: SystemGuide.md
+  - Applications: Applications.md
+  - Catalog: Catalog.md
+  - Hardware: Hardware.md
+theme:
+  name: mkdocs
+  color_mode: auto
+  user_color_mode_toggle: true
+  navigation_depth: 3

Source/HBIOS/Build.cmd

@@ -17,8 +17,8 @@ set CPMDIR80=%TOOLS%/cpm/
 
 ::
 :: This PowerShell script validates the build variables passed in.  If
-:: necessary, the user is prmopted to pick the variables.  It then creates
-:: an include file that is imbedded in the HBIOS assembly (build.inc).
+:: necessary, the user is prompted to pick the variables.  It then creates
+:: an include file that is embedded in the HBIOS assembly (build.inc).
 :: It also creates a batch command file that sets environment variables
 :: for use by the remainder of this batch file (build_env.cmd).
 ::
@@ -97,7 +97,6 @@ call :asm nascom || exit /b
 call :asm game || exit /b
 call :asm usrrom || exit /b
 call :asm updater || exit /b
-call :asm imgpad2 || exit /b
 
 :: Sysconf builds as both BIN and COM files
 tasm -t%CPUType% -g3 -fFF -dROMWBW sysconf.asm sysconf.bin sysconf_bin.lst || exit /b
@@ -106,30 +105,32 @@ tasm -t%CPUType% -g3 -fFF -dCPM sysconf.asm sysconf.com sysconf_com.lst || exit
 ::
 :: Create additional ROM bank images by assembling components into
 :: 32K chunks which can be concatenated later.  Note that
-:: osimg_small is a special case because it is 20K in size.  This
+:: appboot is a special case because it is 20K in size.  This
 :: image is subsequently used to generate the .com loadable file.
 ::
 
-copy /b romldr.bin + dbgmon.bin + ..\zsdos\zsys_wbw.bin + ..\cpm22\cpm_wbw.bin osimg.bin || exit /b
-copy /b ..\Forth\camel80.bin + nascom.bin + ..\tastybasic\src\tastybasic.bin + game.bin + eastaegg.bin + %NETBOOT% + updater.bin + sysconf.bin + usrrom.bin osimg1.bin || exit /b
+copy /b romldr.bin + dbgmon.bin + ..\zsdos\zsys_wbw.bin + ..\cpm22\cpm_wbw.bin rom1.bin || exit /b
+copy /b ..\Forth\camel80.bin + nascom.bin + ..\tastybasic\src\tastybasic.bin + game.bin + eastaegg.bin + %NETBOOT% + updater.bin + sysconf.bin + usrrom.bin rom2.bin || exit /b
 
 if %Platform%==S100 (
     zxcc slr180 -s100mon/fh
     zxcc mload25 -s100mon || exit /b
-    copy /b s100mon.com osimg2.bin || exit /b
+    copy /b s100mon.com rom3.bin || exit /b
 ) else (
-    copy /b imgpad2.bin osimg2.bin || exit /b
+    copy nul rom3.bin
 )
 
-copy /b romldr.bin + dbgmon.bin + ..\zsdos\zsys_wbw.bin osimg_small.bin || exit /b
+copy /b romldr.bin + dbgmon.bin + ..\zsdos\zsys_wbw.bin appboot.bin || exit /b
 
 ::
 :: Inject one byte checksum at the last byte of all 4 ROM bank image files.
-:: This means that computing a checksum over any of the 32K osimg banks
-:: should yield a result of zero.
+:: This means that computing a checksum over any of the 32K rom banks
+:: should yield a result of zero.  Any bank image file that is not
+:: 32K will be automatically normalized to 32K by the srec_cat
+:: formula (extended or truncated)!!!
 ::
 
-for %%f in (hbios_rom.bin osimg.bin osimg1.bin osimg2.bin) do (
+for %%f in (hbios_rom.bin rom1.bin rom2.bin rom3.bin) do (
   "%TOOLS%\srecord\srec_cat.exe" %%f -Binary -Crop 0 0x7FFF -Checksum_Negative_Big_Endian 0x7FFF 1 1 -o %%f -Binary || exit /b
 )
 
@@ -150,13 +151,13 @@ for %%f in (hbios_rom.bin osimg.bin osimg1.bin osimg2.bin) do (
 ::
 
 if %ROMSize% gtr 0 (
-    copy /b hbios_rom.bin + osimg.bin + osimg1.bin + osimg2.bin + ..\RomDsk\rom%ROMDiskSize%_wbw.dat %ROMName%.rom || exit /b
-    copy /b hbios_rom.bin + osimg.bin + osimg1.bin + osimg2.bin %ROMName%.upd || exit /b
-    copy /b hbios_app.bin + osimg_small.bin %ROMName%.com || exit /b
+    copy /b hbios_rom.bin + rom1.bin + rom2.bin + rom3.bin + ..\RomDsk\rom%ROMDiskSize%_wbw.dat %ROMName%.rom || exit /b
+    copy /b hbios_rom.bin + rom1.bin + rom2.bin + rom3.bin %ROMName%.upd || exit /b
+    copy /b hbios_app.bin + appboot.bin %ROMName%.com || exit /b
 ) else (
-    copy /b hbios_rom.bin + osimg.bin + osimg1.bin + osimg2.bin  + ..\RomDsk\rom%RAMDiskSize%_wbw.dat %ROMName%.rom || exit /b
-    copy /b hbios_rom.bin + osimg.bin + osimg1.bin + osimg2.bin %ROMName%.upd || exit /b
-    copy /b hbios_app.bin + osimg_small.bin %ROMName%.com || exit /b
+    copy /b hbios_rom.bin + rom1.bin + rom2.bin + rom3.bin  + ..\RomDsk\rom%RAMDiskSize%_wbw.dat %ROMName%.rom || exit /b
+    copy /b hbios_rom.bin + rom1.bin + rom2.bin + rom3.bin %ROMName%.upd || exit /b
+    copy /b hbios_app.bin + appboot.bin %ROMName%.com || exit /b
 )
 
 ::
@@ -187,14 +188,14 @@ call :asm dbgmon || exit /b
 call :asm romldr || exit /b
 
 :: Create the OS bank
-copy /b romldr.bin + dbgmon.bin + ..\zsdos\zsys_una.bin + ..\cpm22\cpm_una.bin osimg.bin || exit /b
+copy /b romldr.bin + dbgmon.bin + ..\zsdos\zsys_una.bin + ..\cpm22\cpm_una.bin rom2.bin || exit /b
 
 :: Copy OS Bank and ROM Disk image files to output
-copy /b osimg.bin ..\..\Binary\UNA_WBW_SYS.bin || exit /b
+copy /b rom2.bin ..\..\Binary\UNA_WBW_SYS.bin || exit /b
 copy /b ..\RomDsk\rom%ROMDiskSize%_una.dat ..\..\Binary\UNA_WBW_ROM%ROMDiskSize%.bin || exit /b
 
 :: Create the final ROM image
-copy /b ..\UBIOS\UNA-BIOS.BIN + osimg.bin + ..\UBIOS\FSFAT.BIN + ..\RomDsk\rom%ROMDiskSize%_una.dat %ROMName%.rom || exit /b
+copy /b ..\UBIOS\UNA-BIOS.BIN + rom2.bin + ..\UBIOS\FSFAT.BIN + ..\RomDsk\rom%ROMDiskSize%_una.dat %ROMName%.rom || exit /b
 
 :: Copy to output
 copy %ROMName%.rom ..\..\Binary || exit /b

Source/HBIOS/Config/RCZ80_xosera.asm

@@ -0,0 +1,54 @@
+;
+;==================================================================================================
+;   ROMWBW CUSTOM USER BUILD SETTINGS EXAMPLE FOR RCBUS Z80
+;==================================================================================================
+;
+; THIS FILE IS AN EXAMPLE OF A CUSTOM USER SETTINGS FILE.  THESE
+; SETTINGS OVERRIDE THE DEFAULT SETTINGS OF THE INHERITED FILES AS
+; DESIRED BY A USER.
+;
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
+;
+; cfg_MASTER.asm			- MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
+;     |
+;     +-> Config/<plt>_std.asm		- BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
+;         |
+;         +-> Config/<plt>_<cust>.asm	- USER: CUSTOM USER BUILD SETTINGS
+;
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; THIS FILE EXEMPLIFIES THE IDEAL WAY TO CREATE A USER SPECIFIC BUILD
+; CONFIGURATION.  NOTICE THAT IT INCLUDES THE DEFAULT BUILD SETTINGS
+; FILE AND OVERRIDES SOME DESIRED SETTINGS.
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
+;
+; THIS FILE ENABLES THE XOSERA DRIVER WITH A BASE ADDRESS Of 0XE0
+; AND DISPLAY SIZE OF 80 COLUMNS X 30 ROWS
+;
+#INCLUDE "Config/RCZ80_std.asm"		; INHERIT FROM OFFICIAL BUILD SETTINGS
+;
+XOSENABLE	.SET	TRUE		; XOSERA: ENABLE XOSERA VIDEO DRIVERS (XOSERA.ASM)
+XOS_BASE	.SET	$20		; XOSERA: I/O BASE ADDRESS (REQUIRES 32 BYTES)
+XOSSIZ		.SET	V80X30		; XOSERA: DISPLAY FORMAT [V80X30|V80X60]
+;
+AUTOCON		.SET	FALSE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
+VDAEMU_SERKBD	.SET	$0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD

Source/HBIOS/Makefile

@@ -1,7 +1,7 @@
 
 MOREDIFF = game.bin hbios_rom.bin nascom.bin usrrom.bin \
-	dbgmon.bin hbios_app.bin imgpad2.bin osimg1.bin osimg2.bin romldr.bin \
-	eastaegg.bin hbios_img.bin osimg.bin game.bin updater.bin usrrom.bin
+	dbgmon.bin hbios_app.bin imgpad2.bin rom2.bin rom3.bin romldr.bin \
+	eastaegg.bin hbios_img.bin rom1.bin game.bin updater.bin usrrom.bin
 
 DEST = ../../Binary
 TOOLS =../../Tools
@@ -58,37 +58,37 @@ ROMNAME=${ROM_PLATFORM}_${ROM_CONFIG}
 # $(info TASM=$(TASM))
 
 $(OBJECTS) : $(ROMDEPS)
-	@cat romldr.bin dbgmon.bin ../ZSDOS/zsys_$(BIOS).bin ../CPM22/cpm_$(BIOS).bin >osimg.bin
-	cat romldr.bin dbgmon.bin ../ZSDOS/zsys_$(BIOS).bin >osimg_small.bin
+	@cat romldr.bin dbgmon.bin ../ZSDOS/zsys_$(BIOS).bin ../CPM22/cpm_$(BIOS).bin >rom1.bin
+	cat romldr.bin dbgmon.bin ../ZSDOS/zsys_$(BIOS).bin >appboot.bin
 	if [ $(ROM_PLATFORM) = DUO ] ; then \
 		cat netboot-duo.mod >netboot.mod ; \
 	else \
 		cat netboot-mt.mod >netboot.mod  ; \
 	fi
 	if [ $(ROM_PLATFORM) != UNA ] ; then \
-		cat camel80.bin nascom.bin tastybasic.bin game.bin eastaegg.bin netboot.mod updater.bin sysconf.bin usrrom.bin >osimg1.bin ; \
+		cat camel80.bin nascom.bin tastybasic.bin game.bin eastaegg.bin netboot.mod updater.bin sysconf.bin usrrom.bin >rom2.bin ; \
 		if [ $(ROM_PLATFORM) = S100 ] ; then \
-			cat s100mon.bin >osimg2.bin ; \
+			cat s100mon.bin >rom3.bin ; \
 		else \
-			cat imgpad2.bin >osimg2.bin ; \
+			>rom3.bin ; \
 		fi ; \
-		for f in hbios_rom.bin osimg.bin osimg1.bin osimg2.bin ; do \
+		for f in hbios_rom.bin rom1.bin rom2.bin rom3.bin ; do \
 			srec_cat $$f -Binary -Crop 0 0x7FFF -Checksum_Negative_Big_Endian 0x7FFF 1 1 -o $$f -Binary ; \
 		done \
 	fi
 	if [ $(ROM_PLATFORM) = UNA ] ; then \
-		cp osimg.bin $(DEST)/UNA_WBW_SYS.bin ; \
+		cp rom1.bin $(DEST)/UNA_WBW_SYS.bin ; \
 		cp ../RomDsk/rom$(ROMDISKSIZE)_una.dat $(DEST)/UNA_WBW_ROM$(ROMDISKSIZE).bin ; \
-		cat ../UBIOS/UNA-BIOS.BIN osimg.bin ../UBIOS/FSFAT.BIN ../RomDsk/rom$(ROMDISKSIZE)_una.dat >$(ROMNAME).rom ; \
+		cat ../UBIOS/UNA-BIOS.BIN rom1.bin ../UBIOS/FSFAT.BIN ../RomDsk/rom$(ROMDISKSIZE)_una.dat >$(ROMNAME).rom ; \
 	else \
 		if [ $(ROMSIZE) -gt 0 ] ; then \
-			cat hbios_rom.bin osimg.bin osimg1.bin osimg2.bin ../RomDsk/rom$(ROMDISKSIZE)_wbw.dat >$(ROMNAME).rom ; \
-			cat hbios_rom.bin osimg.bin osimg1.bin osimg2.bin >$(ROMNAME).upd ; \
-			cat hbios_app.bin osimg_small.bin > $(ROMNAME).com ; \
+			cat hbios_rom.bin rom1.bin rom2.bin rom3.bin ../RomDsk/rom$(ROMDISKSIZE)_wbw.dat >$(ROMNAME).rom ; \
+			cat hbios_rom.bin rom1.bin rom2.bin rom3.bin >$(ROMNAME).upd ; \
+			cat hbios_app.bin appboot.bin > $(ROMNAME).com ; \
 		else \
-			cat hbios_rom.bin osimg.bin osimg1.bin osimg2.bin ../RomDsk/rom$(RAMDISKSIZE)_wbw.dat >$(ROMNAME).rom ; \
-			cat hbios_rom.bin osimg.bin osimg1.bin osimg2.bin >$(ROMNAME).upd ; \
-			cat hbios_app.bin osimg_small.bin > $(ROMNAME).com ; \
+			cat hbios_rom.bin rom1.bin rom2.bin rom3.bin ../RomDsk/rom$(RAMDISKSIZE)_wbw.dat >$(ROMNAME).rom ; \
+			cat hbios_rom.bin rom1.bin rom2.bin rom3.bin >$(ROMNAME).upd ; \
+			cat hbios_app.bin appboot.bin > $(ROMNAME).com ; \
 		fi \
 	fi
 

Source/HBIOS/cfg_DUO.asm

@@ -96,6 +96,8 @@ CTCOSC		.SET	(7372800/8)	; CTC CLOCK FREQUENCY
 ;
 PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
 PCFBASE		.SET	$56		; PCF8584 BASE I/O ADDRESS
+PCFCLK		.SET	PCFCLK_12	; PCF CLOCK BASE: PCFCLK_[3|443|6|8|12]
+PCFTRNS		.SET	PCFTRNS_90	; PCF TRANSFER SPEED: PCFTRNS_[90|45|11|15]
 ;
 EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;

Source/HBIOS/cfg_DYNO.asm

@@ -97,7 +97,6 @@ CTCBASE		.SET	$88		; CTC BASE I/O ADDRESS
 CTCTIMER	.SET	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
 PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
 EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;

Source/HBIOS/cfg_EPITX.asm

@@ -92,7 +92,6 @@ CTCBASE		.SET	$88		; CTC BASE I/O ADDRESS
 CTCTIMER	.SET	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
 PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
 EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;

Source/HBIOS/cfg_EZZ80.asm

@@ -95,7 +95,6 @@ CTCTIMCH	.SET	3		; TIMER CHANNEL (0-3)
 CTCOSC		.SET	CPUOSC		; CTC CLOCK FREQUENCY
 ;
 PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
 EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;

Source/HBIOS/cfg_FZ80.asm

@@ -95,7 +95,6 @@ CTCTIMCH	.SET	3		; TIMER CHANNEL (0-3)
 CTCOSC		.SET	CPUOSC		; CTC CLOCK FREQUENCY
 ;
 PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
 EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;

Source/HBIOS/cfg_GMZ180.asm

@@ -91,7 +91,6 @@ CTCBASE		.SET	$88		; CTC BASE I/O ADDRESS
 CTCTIMER	.SET	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
 PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
 EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;

Source/HBIOS/cfg_HEATH.asm

@@ -95,7 +95,6 @@ CTCTIMCH	.SET	3		; TIMER CHANNEL (0-3)
 CTCOSC		.SET	CPUOSC		; CTC CLOCK FREQUENCY
 ;
 PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
 EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;

Source/HBIOS/cfg_MASTER.asm

@@ -128,6 +128,8 @@ CTCOSC		.EQU	614400		; CTC CLOCK FREQUENCY
 ;
 PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
 PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+PCFCLK		.EQU	PCFCLK_12	; PCF CLOCK BASE: PCFCLK_[3|443|6|8|12]
+PCFTRNS		.EQU	PCFTRNS_90	; PCF TRANSFER SPEED: PCFTRNS_[90|45|11|15]
 ;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
@@ -309,6 +311,9 @@ VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
 FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+XOSENABLE	.EQU	FALSE		; XOSERA: ENABLE XOSERA VIDEO DRIVERS (XOSERA.ASM)
+XOS_BASE	.EQU	$20		; XOSERA: I/O BASE ADDRESS (REQUIRES 32 BYTES)
+XOSSIZ		.EQU	V80X30		; XOSERA: DISPLAY FORMAT [V80X30|V80X60]
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK

Source/HBIOS/cfg_MBC.asm

@@ -92,7 +92,6 @@ CTCTIMCH	.SET	3		; TIMER CHANNEL (0-3)
 CTCOSC		.SET	(4915200/8)	; CTC CLOCK FREQUENCY
 ;
 PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
 EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;

Source/HBIOS/cfg_MK4.asm

@@ -97,7 +97,6 @@ CTCBASE		.SET	$B0		; CTC BASE I/O ADDRESS
 CTCTIMER	.SET	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
 PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
 EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;

Source/HBIOS/cfg_MON.asm

@@ -92,7 +92,6 @@ CTCTIMCH	.SET	3		; TIMER CHANNEL (0-3)
 CTCOSC		.SET	CPUOSC		; CTC CLOCK FREQUENCY
 ;
 PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
 EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;

Source/HBIOS/cfg_N8.asm

@@ -99,7 +99,6 @@ CTCBASE		.SET	$B0		; CTC BASE I/O ADDRESS
 CTCTIMER	.SET	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
 PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
 EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;

Source/HBIOS/cfg_NABU.asm

@@ -95,7 +95,6 @@ CTCTIMCH	.SET	3		; TIMER CHANNEL (0-3)
 CTCOSC		.SET	CPUOSC		; CTC CLOCK FREQUENCY
 ;
 PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
 EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;

Source/HBIOS/cfg_RCEZ80.asm

@@ -93,7 +93,6 @@ CTCTIMCH	.SET	3		; TIMER CHANNEL (0-3)
 CTCOSC		.SET	CPUOSC		; CTC CLOCK FREQUENCY
 ;
 PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
 EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;

Source/HBIOS/cfg_RCZ180.asm

@@ -97,7 +97,6 @@ CTCBASE		.SET	$88		; CTC BASE I/O ADDRESS
 CTCTIMER	.SET	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
 PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
 EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;

Source/HBIOS/cfg_RCZ280.asm

@@ -97,7 +97,6 @@ CTCBASE		.SET	$88		; CTC BASE I/O ADDRESS
 CTCTIMER	.SET	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
 PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
 EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;

Source/HBIOS/cfg_RCZ80.asm

@@ -96,6 +96,8 @@ CTCOSC		.SET	CPUOSC		; CTC CLOCK FREQUENCY
 ;
 PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
 PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
+PCFCLK		.SET	PCFCLK_8	; PCF CLOCK BASE: PCFCLK_[3|443|6|8|12]
+PCFTRNS		.SET	PCFTRNS_90	; PCF TRANSFER SPEED: PCFTRNS_[90|45|11|15]
 ;
 EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;

Source/HBIOS/cfg_RPH.asm

@@ -97,7 +97,6 @@ CTCBASE		.SET	$B0		; CTC BASE I/O ADDRESS
 CTCTIMER	.SET	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
 PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
 EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;

Source/HBIOS/cfg_S100.asm

@@ -97,7 +97,6 @@ CTCBASE		.SET	$88		; CTC BASE I/O ADDRESS
 CTCTIMER	.SET	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
 PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
 EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;

Source/HBIOS/cfg_SBC.asm

@@ -92,7 +92,6 @@ CTCTIMCH	.SET	3		; TIMER CHANNEL (0-3)
 CTCOSC		.SET	614400		; CTC CLOCK FREQUENCY
 ;
 PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
 EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;

Source/HBIOS/cfg_SCZ180.asm

@@ -97,7 +97,6 @@ CTCBASE		.SET	$88		; CTC BASE I/O ADDRESS
 CTCTIMER	.SET	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
 PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
 EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;

Source/HBIOS/cfg_Z80RETRO.asm

@@ -95,7 +95,6 @@ CTCTIMCH	.SET	1		; TIMER CHANNEL (0-3)
 CTCOSC		.SET	7372800		; CTC CLOCK FREQUENCY
 ;
 PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
 EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;

Source/HBIOS/cfg_ZETA.asm

@@ -84,7 +84,6 @@ KIOBASE		.SET	$80		; KIO BASE I/O ADDRESS
 CTCENABLE	.SET	FALSE		; ENABLE ZILOG CTC SUPPORT
 ;
 PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
 EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;

Source/HBIOS/cfg_ZETA2.asm

@@ -95,7 +95,6 @@ CTCTIMCH	.SET	1		; TIMER CHANNEL (0-3)
 CTCOSC		.SET	921600		; CTC CLOCK FREQUENCY
 ;
 PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
 EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;

Source/HBIOS/ds7rtc.asm

@@ -418,12 +418,12 @@ DS7_CLP:LD	C,(HL)
 	RET
 ;
 DS7_CLKTBL:
-	.DB	04H, 00111111B, '/'
-	.DB	05H, 00011111B, '/'
-	.DB	06H, 11111111B, ' '
-	.DB	02H, 00011111B, ':'
-	.DB	01H, 01111111B, ':'
-	.DB	00H, 01111111B, 00H
+	.DB	04H, 00111111B, '/'	; DD: 31
+	.DB	05H, 00011111B, '/'	; MM: 12
+	.DB	06H, 11111111B, ' '	; YY: 99
+	.DB	02H, 01111111B, ':'	; SS: 59
+	.DB	01H, 01111111B, ':'	; MM: 59
+	.DB	00H, 00111111B, 00H	; HH: 24
 ;
 DS7_BCD:PUSH	HL
 	LD      HL,DS7_BUF     	; READ VALUE FROM

Source/HBIOS/dsrtc.asm

@@ -482,6 +482,7 @@ DSRTC_DETECT:
 DSRTC_DETECT1:
 	PUSH	AF			; SAVE STATUS
 	LD	A,(DSRTC_TEMP)		; GET SAVED VALUE
+	LD	E,A			; TO E
 	LD	C,30			; NVRAM INDEX 30
 	CALL	DSRTC_SETBYT		; SAVE IT
 	POP	AF			; RECOVER STATUS

Source/HBIOS/hbios.asm

@@ -522,8 +522,9 @@ HB_HCB_END	.EQU	$
 ; THE FOLLOWING CODE IS RELOCATED TO THE TOP OF MEMORY TO HANDLE INVOCATION DISPATCHING
 ;
 HB_PROXY_BEG	.EQU	$
+HBX_IMG		.EQU	$		; LOC OF HBX IMAGE IN HBIOS IMAGE BANK
 ;
-	.FILL	(HBX_IMG - $)		; FILL TO START OF PROXY IMAGE START
+;;;	.FILL	(HBX_IMG - $)		; FILL TO START OF PROXY IMAGE START
 	.ORG	HBX_LOC			; ADJUST FOR RELOCATION
 ;
 ; MEMORY LAYOUT:
@@ -3954,6 +3955,9 @@ HB_PCINITTBL:
 #IF (PIO_4P | PIO_ZP)
 	.DW	PIO_PREINIT
 #ENDIF
+#IF (XOSENABLE)
+	.DW	XOS_PREINIT
+#ENDIF
 ;
 HB_PCINITTBLLEN	.EQU	(($ - HB_PCINITTBL) / 2)
 ;
@@ -4089,6 +4093,9 @@ HB_INITTBL:
 #IF (SCONENABLE)
 	.DW	SCON_INIT
 #ENDIF
+#IF (XOSENABLE)
+	.DW     XOS_INIT
+#ENDIF
 #IF (LPTENABLE)
 	.DW	LPT_INIT
 #ENDIF
@@ -6210,7 +6217,7 @@ SYS_SETCPUSPD:
 ;
 	LD	A,L			; CLK SPD TO ACCUM
 	CP	$FF			; NO CHANGE?
-	JR	Z,SYS_SETCPUSPD3	; DONE IF SO
+	JR	Z,SYS_SETCPUSPD_OK	; DONE IF SO
 	LD	C,%00000000		; HALF SPEED
 	CP	0
 	JR	Z,SYS_SETCPUSPD1
@@ -6222,12 +6229,12 @@ SYS_SETCPUSPD1:
 	LD	A,(HB_RTCVAL)
 	AND	~%00001000		; CLEAR SPEED BIT
 	OR	C			; IMPLEMENT NEW SPEED BIT
-#IF (PLATFORM == PLT_SBC)
+  #IF (PLATFORM == PLT_SBC)
 	; SBC SPEED BIT IS INVERTED, ADJUST IT
 	LD	A,C
 	XOR	%00001000
 	LD	C,A
-#ENDIF
+  #ENDIF
 	LD	(HB_RTCVAL),A		; SAVE IN SHADOW REGISTER
 	OUT	(RTCIO),A		; UPDATE HARDWARE REGISTER
 ;
@@ -6255,15 +6262,11 @@ SYS_SETCPUSPD2:
 	ADC	A,C			; C -> A; ADD CF FOR ROUNDING
 	LD	(CB_CPUMHZ),A		; SAVE IT
 ;
-#IF (CPUFAM != CPU_EZ80)
+  #IF (CPUFAM != CPU_EZ80)
 	;  REINIT DELAY ROUTINE
 	LD	A,(CB_CPUMHZ)		; CPU SPEED TO ACCUM AND INIT
 	CALL	DELAY_INIT		; .. SPEED COMPENSATED DELAY
-#ENDIF
-;
-SYS_SETCPUSPD3:
-	XOR	A
-	RET
+  #ENDIF
 #ENDIF
 ;
 #IF (PLATFORM == PLT_HEATH)
@@ -6302,14 +6305,11 @@ SYS_SETCPUSPD2:
 	ADC	A,C			; C -> A; ADD CF FOR ROUNDING
 	LD	(CB_CPUMHZ),A		; SAVE IT
 ;
-#IF (CPUFAM != CPU_EZ80)
+  #IF (CPUFAM != CPU_EZ80)
 	;  REINIT DELAY ROUTINE
 	LD	A,(CB_CPUMHZ)		; CPU SPEED TO ACCUM AND INIT
 	CALL	DELAY_INIT		; .. SPEED COMPENSATED DELAY
-#ENDIF
-;
-	XOR	A			; SIGNAL SUCCESS
-	RET
+  #ENDIF
 #ENDIF
 ;
 #IF (CPUFAM == CPU_Z180)
@@ -6441,11 +6441,11 @@ SYS_SETCPUSPD4:
 	LD	A,L			; WORKING VALUE TO A
 	OUT0	(Z180_DCNTL),A		; IMPLEMENT NEW VALUE
 ;
-#IF (CPUFAM != CPU_EZ80)
+  #IF (CPUFAM != CPU_EZ80)
 	;  REINIT DELAY ROUTINE
 	LD	A,(CB_CPUMHZ)		; CPU SPEED TO ACCUM AND INIT
 	CALL	DELAY_INIT		; .. SPEED COMPENSATED DELAY
-#ENDIF
+  #ENDIF
 ;
   #IF ((INTMODE == 2) & (Z180_TIMER))
 	; THE Z180 TIMER IS BASED ON CPU SPEED.  SO HERE
@@ -6473,10 +6473,16 @@ SYS_SETCPUSPD4:
 	LD	IY,ASCI1_CFG
 	CALL	ASCI_INITDEV
   #ENDIF
+#ENDIF
+;
+SYS_SETCPUSPD_OK:
+;
+	LD	B,BF_DSKYEVENT
+	LD	C,DSKY_EVT_CPUSPD
+	CALL	DSKY_DISPATCH
 ;
 	XOR	A
 	RET
-#ENDIF
 ;
 SYS_SETCPUSPD_ERR:
 	OR	$FF			; NOT SUPPORTED
@@ -8803,7 +8809,6 @@ PS_SDLPT	.TEXT	"LPT$"
 PS_SDESPCON	.TEXT	"ESPCON$"
 PS_SDESPSER	.TEXT	"ESPSER$"
 PS_SDSCON	.TEXT	"SCON$"
-PS_SDEF		.TEXT	"EF$"
 PS_SDSSER	.TEXT	"SSER$"
 PS_SDEZ80	.TEXT	"EZ80$"
 ;
@@ -8832,6 +8837,7 @@ PS_VDVGA	.TEXT	"VGA$"
 PS_VDVRC	.TEXT	"VRC$"
 PS_VDEF		.TEXT	"EF$"
 PS_VDFV		.TEXT	"FV$"
+PS_VDXOSERA	.TEXT	"XOSERA$"
 ;
 ; VIDEO TYPE STRINGS
 ;
@@ -8980,6 +8986,15 @@ SIZ_INTRTC	.EQU	$ - ORG_INTRTC
 		MEMECHO	" bytes.\n"
 #ENDIF
 ;
+#IF (DS7RTCENABLE)
+ORG_DS7RTC	.EQU	$
+  #INCLUDE "ds7rtc.asm"
+SIZ_DS7RTC	.EQU	$ - ORG_DS7RTC
+		.ECHO	"DS7RTC occupies "
+		.ECHO	SIZ_DS7RTC
+		.ECHO	" bytes.\n"
+#ENDIF
+;
 #IF (RP5RTCENABLE)
 ORG_RP5RTC	.EQU	$
   #INCLUDE "rp5rtc.asm"
@@ -9160,6 +9175,15 @@ SIZ_FV	.EQU	$ - ORG_FV
 		MEMECHO	" bytes.\n"
 #ENDIF
 ;
+#IF (XOSENABLE)
+ORG_XOS	.EQU	$
+  #INCLUDE "xosera.asm"
+SIZ_XOS	.EQU	$ - ORG_XOS
+		MEMECHO "XOS occupies "
+		MEMECHO SIZ_XOS
+		MEMECHO " bytes.\n"
+#ENDIF
+;
 #IF (DMAENABLE)
 ORG_DMA	.EQU	$
 #INCLUDE "dma.asm"

Source/HBIOS/hbios.inc

@@ -450,6 +450,7 @@ VDADEV_VGA	.EQU	$04		; ECB VGA3 - HITACHI HD6445
 VDADEV_VRC	.EQU	$05		; VGARC
 VDADEV_EF	.EQU	$06		; EF9345
 VDADEV_FV	.EQU	$07		; S100 FPGA VGA
+VDADEV_XOSERA	.EQU	$08		; XOSERA RCBUS
 ;
 ; SOUND DEVICE IDS
 ;

Source/HBIOS/layout.inc

@@ -1,146 +1,224 @@
 ;
-; The was extracted out of STD.ASM, so can be included
-; in BIOS apps that are NOT in HBIOS directory!
+;==================================================================================================
+;   ROMWBW CPU MEMORY AND ROM BANK LAYOUT DEFINITIONS
+;==================================================================================================
 ;
-; =============
-; MEMORY LAYOUT
-; =============
+; THIS FILE DEFINES THE MEMORY LAYOUT OF THE CPU ADDRESS SPACE AND
+; THE LAYOUT OF CODE IMAGES IN ROM.  THIS FILE IS INTENDED TO BE
+; INCLUDED IN SOURCE FILES AS NEEDED TO ADAPT TO THE ROMWBW BUILD
+; CONFIGURATION.
 ;
-SYS_SIZ		.EQU	$3000			; COMBINED SIZE OF SYSTEM AREA (OS + HBIOS PROXY)
-HBBUF_SIZ	.EQU	1024			; INVARIANT HBIOS PHYSICAL DISK BUFFER, 1K
-HBX_SIZ		.EQU	$200			; HBIOS PROXY SIZE (SUBJECT TO CHANGE)
-CPM_SIZ		.EQU	SYS_SIZ - HBX_SIZ	; NET SIZE OF ALL OS COMPONENTS (EXCLUDING HBIOS PROXY)
-CCP_SIZ		.EQU	$800			; INVARIANT SIZE OF CCP
-BDOS_SIZ	.EQU	$E00			; INVARIANT SIZE OF BDOS
-CBIOS_SIZ	.EQU	CPM_SIZ - CCP_SIZ - BDOS_SIZ	; CBIOS IS THE REMAINDER
+; THE FIRST 4 BANKS OF ROMWBW ROMS CONTAIN ROMWBW SOFTWARE COMPONENTS.
+; THE REMAINING BANKS ARE USED AS ROM DISK CONTENTS.
+;
+;   ROM BANK SUMMARY
+;   ----------------
+;
+;   ROM BANK	BANK ID		DESCRIPTION
+;   --------	--------	----------------------------------------
+;   0 (ROM0)	BID_BOOT	HBIOS KERNEL (HBIOS.ASM)
+;   1 (ROM1)	BID_IMG0	MONITOR, BOOT LOADER, ROM OS IMAGES
+;   2 (ROM2)	BID_IMG1	ROM APPLICATIONS
+;   3 (ROM3)	BID_IMG2	ROM UTILITIES
+;
+;--------------------------------------------------------------------------------------------------
+; CPU ADDRESS SPACE MEMORY LAYOUT
+;--------------------------------------------------------------------------------------------------
 ;
 MEMTOP		.EQU	$10000			; INVARIANT TOP OF Z80 ADDRESSABLE MEMORY
 BNKTOP		.EQU	$8000			; BANK MEMORY BARRIER
 ;
-HBX_IMG		.EQU	$200			; LOC OF HBX IMAGE IN HBIOS IMAGE BANK
+HBX_SIZ		.EQU	$200			; HBIOS PROXY SIZE (SUBJECT TO CHANGE)
+HBX_LOC		.EQU	MEMTOP - HBX_SIZ	; RUNNING LOCATION OF HBIOS PROXY
 ;
-HBBUF_END	.EQU	BNKTOP			; END OF PHYSICAL DISK BUFFER IN HBIOS
-HBBUF_LOC	.EQU	HBBUF_END - HBBUF_SIZ	; START OF PHYSICAL DISK BUFFER
-HBX_END		.EQU	MEMTOP			; END OF HBIOS PROXY
-HBX_LOC		.EQU	HBX_END - HBX_SIZ	; START OF HBIOS PROXY
-CPM_END		.EQU	HBX_LOC			; END OF CPM COMPONENTS (INCLUDING CBIOS)
-CPM_LOC		.EQU	CPM_END - CPM_SIZ	; START OF CPM COMPONENTS
-CBIOS_END	.EQU	HBX_LOC			; END OF CBIOS
-CBIOS_LOC	.EQU	CBIOS_END - CBIOS_SIZ	; START OF CBIOS
+CPM_LOC		.EQU	$D000			; START OF CPM COMPONENTS
+CPM_SIZ		.EQU	HBX_LOC - CPM_LOC	; NET SIZE OF ALL OS COMPONENTS (EXCLUDING HBIOS PROXY)
+;
+CCP_SIZ		.EQU	$0800			; INVARIANT SIZE OF CCP
+BDOS_SIZ	.EQU	$0E00			; INVARIANT SIZE OF BDOS
+CBIOS_SIZ	.EQU	CPM_SIZ - CCP_SIZ - BDOS_SIZ	; REMAINDER IS CBIOS SIZE
+;
+CBIOS_LOC	.EQU	HBX_LOC - CBIOS_SIZ	; START OF CBIOS
+BDOS_LOC	.EQU	CBIOS_LOC - BDOS_SIZ	; START OF BDOS
+CCP_LOC		.EQU	BDOS_LOC - CCP_SIZ	; START OF CCP
 ;
 CPM_ENT		.EQU	CBIOS_LOC		; CPM ENTRY POINT (IN CBIOS)
 ;
-CPM_IMGSIZ	.EQU	$3000
+; THE SIZE OF THE CPM IMAGE STORED ON A ROM BANK IS GREATER THAN THE
+; SIZE TO BE LOADED.  THE FORMER INCLUDES HBIOS SPACE AND THE LATTER
+; DOES NOT.  USE CPM_IMGSIZ WHEN REFERRING TO IMAGE SIZE STORED ON ROM.
+CPM_IMGSIZ	.EQU	$3000			; CPM IMAGE SIZE ON ROM
 ;
-; =============================
-; ROM BANK 0    (hbios_rom.bin)
-; =============================
+;--------------------------------------------------------------------------------------------------
+; ROM BANK 0 (BID_BOOT) LAYOUT (ROM0.BIN)
+;--------------------------------------------------------------------------------------------------
 ;
-; See hbios.asm for content of Bank 0
+; SEE HBIOS.ASM FOR CONTENT OF BANK 0
 ;
-; =============================
-; ROM BANK 1 LAYOUT (osimg.bin)
-; =============================
+;--------------------------------------------------------------------------------------------------
+; ROM BANK 1 (BID_IMG0) LAYOUT (ROM1.BIN)
+;--------------------------------------------------------------------------------------------------
 ;
-LDR_LOC		.EQU	$0000			; ROM LOADER
-LDR_SIZ		.EQU	$1000
-LDR_END		.EQU	LDR_LOC +LDR_SIZ
-LDR_IMGLOC	.EQU	$0000
+BNK_NXTLOC	.EQU	$0000			; RESET TO START OF BANK
+BNK_CUR		.EQU	1			; THIS IS ROM BANK 1 (BID_IMG0)
 ;
-MON_LOC		.EQU	$EE00			; LOCATION OF MONITOR FOR RUNNING SYSTEM
+LDR_BNK		.EQU	BNK_CUR
+LDR_LOC		.EQU	$0000			; RUNNING LOCATION OF BOOT LOADER
+LDR_SIZ		.EQU	$1000			; SIZE OF BOOT LOADER BINARY IMAGE
+LDR_END		.EQU	LDR_LOC + LDR_SIZ	; ENDING ADDRESS OF RUNNING BOOT LOADER
+LDR_IMGLOC	.EQU	BNK_NXTLOC		; LOCATION OF BINARY LOAD IMAGE IN BANK
+BNK_NXTLOC	.SET	LDR_IMGLOC + LDR_SIZ	; IMG LOC OF NEXT COMPONENT
+;
+MON_BNK		.EQU	BNK_CUR
+MON_LOC		.EQU	$EE00			; RUNNING LOCATION OF MONITOR
 MON_SIZ		.EQU	$1000			; SIZE OF MONITOR BINARY IMAGE
-MON_END		.EQU	MON_LOC + MON_SIZ	; END OF MONITOR
-MON_IMGLOC	.EQU	LDR_IMGLOC + LDR_SIZ
+MON_END		.EQU	MON_LOC + MON_SIZ	; ENDING ADDRESS OF RUNNING MONITOR
+MON_IMGLOC	.EQU	BNK_NXTLOC		; LOCATION OF BINARY LOAD IMAGE IN BANK
+BNK_NXTLOC	.SET	MON_IMGLOC + MON_SIZ	; IMG LOC OF NEXT COMPONENT
 ;
-ZSYS_IMGLOC	.EQU	MON_IMGLOC + MON_SIZ	; ZSDOS / Z-System
+ZSYS_BNK	.EQU	BNK_CUR
+ZSYS_LOC	.EQU	CPM_LOC			; RUNNING LOCATION OF ZSYSTEM
+ZSYS_SIZ	.EQU	CPM_SIZ			; SIZE OF ZSYSTEM BINARY IMAGE
+ZSYS_END	.EQU	ZSYS_LOC + ZSYS_SIZ	; ENDING ADDRESS OF RUNNING ZSYSTEM
+ZSYS_IMGLOC	.EQU	BNK_NXTLOC		; LOCATION OF BINARY LOAD IMAGE IN BANK
+ZSYS_IMGSIZ	.EQU	CPM_IMGSIZ		; SIZE OF LOAD IMAGE IN BANK
+BNK_NXTLOC	.SET	ZSYS_IMGLOC + ZSYS_IMGSIZ	; IMG LOC OF NEXT COMPONENT
 ;
-CPM_IMGLOC	.EQU	ZSYS_IMGLOC + CPM_IMGSIZ ; CP/M 2.2
+CPM22_BNK	.EQU	BNK_CUR
+CPM22_LOC	.EQU	CPM_LOC			; RUNNING LOCATION OF CPM 2.2
+CPM22_SIZ	.EQU	CPM_SIZ                 ; SIZE OF CPM 2.2 BINARY IMAGE
+CPM22_END	.EQU	CPM22_LOC + CPM22_SIZ   ; ENDING ADDRESS OF RUNNING CPM 2.2
+CPM22_IMGLOC	.EQU	BNK_NXTLOC		; LOCATION OF BINARY LOAD IMAGE IN BANK
+CPM22_IMGSIZ	.EQU	CPM_IMGSIZ		; SIZE OF LOAD IMAGE IN BANK
+BNK_NXTLOC	.SET	CPM22_IMGLOC + CPM22_IMGSIZ	; IMG LOC OF NEXT COMPONENT
 ;
-BNK1_IMGEND	.EQU	CPM_IMGLOC + CPM_IMGSIZ	; END OF BANK
-BNK1_REMAIN	.EQU	BNKTOP - BNK1_IMGEND	; REMAINING
+BNK1_LEN	.EQU	BNK_NXTLOC		; SIZE OF BANK CONTENTS
+BNK1_SLACK	.EQU	BNKTOP - BNK_NXTLOC	; REMAINING BANK SPACE
 ;
-; ==============================
-; ROM BANK 2 LAYOUT (osimg1.bin)
-; ==============================
+;--------------------------------------------------------------------------------------------------
+; ROM BANK 2 (BID_IMG1) LAYOUT (ROM2.BIN)
+;--------------------------------------------------------------------------------------------------
+;
+BNK_NXTLOC	.SET	$0000			; RESET TO START OF BANK
+BNK_CUR		.SET	2			; THIS IS ROM BANK 2 (BID_IMG1)
 ;
 ; NOTE FOLLOWING ARE COPY/PASTED INTO camel80.azm !!!!!!!!
+FTH_BNK		.EQU	BNK_CUR
 FTH_LOC		.EQU	$0200			; CAMEL FORTH
 FTH_SIZ		.EQU	$1700
 FTH_END		.EQU	FTH_LOC + FTH_SIZ
-FTH_IMGLOC	.EQU	$0000
-
+FTH_IMGLOC	.EQU	BNK_NXTLOC		; LOCATION OF BINARY LOAD IMAGE IN BANK
+BNK_NXTLOC	.SET	FTH_IMGLOC + FTH_SIZ	; IMG LOC OF NEXT COMPONENT
+;
+BAS_BNK		.EQU	BNK_CUR
 BAS_LOC		.EQU	$0200			; NASCOM BASIC
 BAS_SIZ		.EQU	$2000
 BAS_END		.EQU	BAS_LOC + BAS_SIZ
-BAS_IMGLOC	.EQU	FTH_IMGLOC + FTH_SIZ
+BAS_IMGLOC	.EQU	BNK_NXTLOC		; LOCATION OF BINARY LOAD IMAGE IN BANK
+BNK_NXTLOC	.SET	BAS_IMGLOC + BAS_SIZ	; IMG LOC OF NEXT COMPONENT
 ;
 ; NOTE FOLLOWING ARE COPY/PASTED INTO tastybasic.asm !!!!!!!!
+TBC_BNK		.EQU	BNK_CUR
 TBC_LOC		.EQU	$0A00			; TASTYBASIC
 TBC_SIZ		.EQU	$0A00
 TBC_END		.EQU	TBC_LOC + TBC_SIZ
-TBC_IMGLOC	.EQU	BAS_IMGLOC + BAS_SIZ
+TBC_IMGLOC	.EQU	BNK_NXTLOC		; LOCATION OF BINARY LOAD IMAGE IN BANK
+BNK_NXTLOC	.SET	TBC_IMGLOC + TBC_SIZ	; IMG LOC OF NEXT COMPONENT
 ;
+GAM_BNK		.EQU	BNK_CUR
 GAM_LOC		.EQU	$0200			; GAME 2048
 GAM_SIZ		.EQU	$0900
 GAM_END		.EQU	GAM_LOC + GAM_SIZ
-GAM_IMGLOC	.EQU	TBC_IMGLOC + TBC_SIZ
+GAM_IMGLOC	.EQU	BNK_NXTLOC		; LOCATION OF BINARY LOAD IMAGE IN BANK
+BNK_NXTLOC	.SET	GAM_IMGLOC + GAM_SIZ	; IMG LOC OF NEXT COMPONENT
 ;
+EGG_BNK		.EQU	BNK_CUR
 EGG_LOC		.EQU	$F000			; EASTER EGG
 EGG_SIZ		.EQU	$0200
 EGG_END		.EQU	EGG_LOC + EGG_SIZ
-EGG_IMGLOC	.EQU	GAM_IMGLOC + GAM_SIZ
+EGG_IMGLOC	.EQU	BNK_NXTLOC		; LOCATION OF BINARY LOAD IMAGE IN BANK
+BNK_NXTLOC	.SET	EGG_IMGLOC + EGG_SIZ	; IMG LOC OF NEXT COMPONENT
 ;
+NET_BNK		.EQU	BNK_CUR
 NET_LOC		.EQU	$0100			; NETWORK BOOT
 NET_SIZ		.EQU	$1000
 NET_END		.EQU	NET_LOC + NET_SIZ
-NET_IMGLOC	.EQU	EGG_IMGLOC + EGG_SIZ
+NET_IMGLOC	.EQU	BNK_NXTLOC		; LOCATION OF BINARY LOAD IMAGE IN BANK
+BNK_NXTLOC	.SET	NET_IMGLOC + NET_SIZ	; IMG LOC OF NEXT COMPONENT
 ;
+UPD_BNK		.EQU	BNK_CUR
 UPD_LOC		.EQU	$0200			; ROM UPDATER
 UPD_SIZ		.EQU	$0D00
 UPD_END		.EQU	UPD_LOC + UPD_SIZ
-UPD_IMGLOC	.EQU	NET_IMGLOC + NET_SIZ
+UPD_IMGLOC	.EQU	BNK_NXTLOC		; LOCATION OF BINARY LOAD IMAGE IN BANK
+BNK_NXTLOC	.SET	UPD_IMGLOC + UPD_SIZ	; IMG LOC OF NEXT COMPONENT
 ;
+NVR_BNK		.EQU	BNK_CUR
 NVR_LOC		.EQU	$0100			; NVRAM CONFIG
 NVR_SIZ		.EQU	$0800
 NVR_END		.EQU	NVR_LOC + NVR_SIZ
-NVR_IMGLOC	.EQU	UPD_IMGLOC + UPD_SIZ
+NVR_IMGLOC	.EQU	BNK_NXTLOC		; LOCATION OF BINARY LOAD IMAGE IN BANK
+BNK_NXTLOC	.SET	NVR_IMGLOC + NVR_SIZ	; IMG LOC OF NEXT COMPONENT
 ;
+USR_BNK		.EQU	BNK_CUR
 USR_LOC		.EQU	$0200			; USER
 USR_SIZ		.EQU	$0200
 USR_END		.EQU	USR_LOC + USR_SIZ
-USR_IMGLOC	.EQU	NVR_IMGLOC + NVR_SIZ
+USR_IMGLOC	.EQU	BNK_NXTLOC		; LOCATION OF BINARY LOAD IMAGE IN BANK
+BNK_NXTLOC	.SET	USR_IMGLOC + USR_SIZ	; IMG LOC OF NEXT COMPONENT
 ;
-BNK2_IMGEND	.EQU	USR_IMGLOC + USR_SIZ	; END OF BANK
-BNK2_REMAIN	.EQU	BNKTOP - BNK2_IMGEND	; REMAINING
+BNK2_LEN	.EQU	BNK_NXTLOC		; SIZE OF BANK CONTENTS
+BNK2_SLACK	.EQU	BNKTOP - BNK_NXTLOC	; REMAINING BANK SPACE
 ;
-; ==============================
-; ROM BANK 3 LAYOUT (osimg2.bin)
-; ==============================
+;--------------------------------------------------------------------------------------------------
+; ROM BANK 3 (BID_IMG2) LAYOUT (ROM3.BIN)
+;--------------------------------------------------------------------------------------------------
 ;
-; not defined here, see build files
-; optionally contains S100 monitor
+BNK_NXTLOC	.SET	$0000			; RESET TO START OF BANK
+BNK_CUR		.SET	3			; THIS IS ROM BANK 3 (BID_IMG2)
 ;
-; =================
+HWMON_BNK	.EQU	BNK_CUR
+HWMON_LOC	.EQU	$E000
+HWMON_SIZ	.EQU	$2000
+HWMON_END	.EQU	HWMON_LOC + HWMON_SIZ
+HWMON_IMGLOC	.EQU	BNK_NXTLOC		; LOCATION OF BINARY LOAD IMAGE IN BANK
+BNK_NXTLOC	.SET	HWMON_IMGLOC + HWMON_SIZ	; IMG LOC OF NEXT COMPONENT
+;
+FONTS_BNK	.EQU	BNK_CUR
+;;;FONTS_LOC	.EQU	$E000
+FONTS_SIZ	.EQU	$2000
+;;;FONTS_END	.EQU	FONTS_LOC + FONTS_SIZ
+FONTS_IMGLOC	.EQU	BNK_NXTLOC		; LOCATION OF BINARY LOAD IMAGE IN BANK
+BNK_NXTLOC	.SET	FONTS_IMGLOC + FONTS_SIZ	; IMG LOC OF NEXT COMPONENT
+;
+BNK3_LEN	.EQU	BNK_NXTLOC		; SIZE OF BANK CONTENTS
+BNK3_SLACK	.EQU	BNKTOP - BNK_NXTLOC	; REMAINING BANK SPACE
+;
+;--------------------------------------------------------------------------------------------------
 ;
 #IFDEF BNKINFO
+;
 	.ECHO "-------------------------------\n"
-	.ECHO "ROM BANK INFO  \tLENGTH \tREMAIN \n"
+	.ECHO "ROM BANK INFO  \tLENGTH \tSLACK \n"
 	.ECHO "---------------\t-------\t-------\n"
-	.ECHO "BANK1 BID_IMG0 \t" \ .ECHO BNK1_IMGEND \ .ECHO "\t" \ .ECHO BNK1_REMAIN \ .ECHO "\n"
-	.ECHO "BANK2 BID_IMG1 \t" \ .ECHO BNK2_IMGEND \ .ECHO "\t" \ .ECHO BNK2_REMAIN \ .ECHO "\n"
+	.ECHO "BANK1 BID_IMG0 \t" \ .ECHO BNK1_LEN \ .ECHO "\t" \ .ECHO BNK1_SLACK \ .ECHO "\n"
+	.ECHO "BANK2 BID_IMG1 \t" \ .ECHO BNK2_LEN \ .ECHO "\t" \ .ECHO BNK2_SLACK \ .ECHO "\n"
+	.ECHO "BANK3 BID_IMG2 \t" \ .ECHO BNK3_LEN \ .ECHO "\t" \ .ECHO BNK3_SLACK \ .ECHO "\n"
 	.ECHO "-------------------------------\n"
 ;
-  #IF (BNK1_IMGEND > BNKTOP)
-	.ECHO	"*** BANK 1 IS TOO BIG!!!\n"
+  #IF (BNK1_LEN > BNKTOP)
+	.ECHO	"*** ROM BANK 1 IS TOO BIG!!!\n"
 	!!!	; FORCE AN ASSEMBLY ERROR IF BANK SIZE EXCEEDS SPACE
   #ENDIF
-  #IF (BNK2_IMGEND > BNKTOP)
-	.ECHO	"*** BANK 2 IS TOO BIG!!!\n"
+;
+  #IF (BNK2_LEN > BNKTOP)
+	.ECHO	"*** ROM BANK 2 IS TOO BIG!!!\n"
+	!!!	; FORCE AN ASSEMBLY ERROR IF BANK SIZE EXCEEDS SPACE
+  #ENDIF
+;
+  #IF (BNK3_LEN > BNKTOP)
+	.ECHO	"*** ROM BANK 3 IS TOO BIG!!!\n"
 	!!!	; FORCE AN ASSEMBLY ERROR IF BANK SIZE EXCEEDS SPACE
   #ENDIF
 ;
 #ENDIF
-
-
-
-

Source/HBIOS/lcd.asm

@@ -90,21 +90,7 @@ LCD_PREINIT:
 	LD	DE,LCD_STR_XPU
 	CALL	LCD_OUTDS
 ;
-	; "12.345 MHz" RIGHT JUSTIFIED
-	LD	HL,$010A		; ROW 2, COL 10
-	CALL	LCD_GOTORC
-	LD	HL,(CB_CPUKHZ)
-	PUSH	HL
-	LD	BC,10000		; 10 MHZ
-	SBC	HL,BC			; SUBTRACT
-	JR	NC,LCD_PREINIT1
-	LD	A,' '			; EXTRA PAD
-	CALL	LCD_OUTD
-LCD_PREINIT1:
-	POP	HL
-	CALL	LCD_PRTD3M		; PRINT AS DECIMAL WITH 3 DIGIT MANTISSA
-	LD	DE,LCD_STR_MHZ
-	CALL	LCD_OUTDS
+	CALL	LCD_EVT_CPUSPD
 ;
 	; THIRD LINE
 	LD	HL,$0200		; ROW 2, COL 0
@@ -228,7 +214,22 @@ LCD_EVENT:
 ; CPU SPEED CHANGE
 ;
 LCD_EVT_CPUSPD:
-	XOR	A
+	; "12.345 MHz" RIGHT JUSTIFIED
+	LD	HL,$010A		; ROW 2, COL 10
+	CALL	LCD_GOTORC
+	LD	HL,(CB_CPUKHZ)
+	PUSH	HL
+	LD	BC,10000		; 10 MHZ
+	SBC	HL,BC			; SUBTRACT
+	JR	NC,LCD_PREINIT1
+	LD	A,' '			; EXTRA PAD
+	CALL	LCD_OUTD
+LCD_PREINIT1:
+	POP	HL
+	CALL	LCD_PRTD3M		; PRINT AS DECIMAL WITH 3 DIGIT MANTISSA
+	LD	DE,LCD_STR_MHZ
+	CALL	LCD_OUTDS
+;
 	RET
 ;
 ; FORMAT: "Disk #99  R:12345678"
@@ -342,16 +343,23 @@ LCD_DELAY:
 	CALL	DELAY			; 16US
 	JP	DELAY			; 16US, TOTAL 48US
 ;
+; DELAY USED DURING NORMAL I/O
+; REQUIRED FOR HIGH SPEED CPU OPERATION
+;
+#DEFINE LCD_XDELAY EX (SP),HL \ EX (SP),HL
+;
 ; SEND FUNCTION CODE IN A
 ;
 LCD_OUTF:
 	PUSH	AF			; SAVE CODE
 LCD_OUTF1:
+	LCD_XDELAY
 	EZ80_IO
 	IN	A,(LCD_STAT)		; GET STATUS
 	AND	$80			; ISOLATE BUSY FLAG
 	JR	NZ,LCD_OUTF1		; LOOP TILL NOT BUSY
 	POP	AF			; RECOVER CODE
+	LCD_XDELAY
 	EZ80_IO
 	OUT	(LCD_FUNC),A		; SEND IT
 	RET				; DONE
@@ -372,11 +380,13 @@ LCD_OUTFS:
 LCD_OUTD:
 	PUSH	AF			; SAVE BYTE
 LCD_OUTD1:
+	LCD_XDELAY
 	EZ80_IO
 	IN	A,(LCD_STAT)		; GET STATUS
 	AND	$80			; ISOLATE BUSY FLAG
 	JR	NZ,LCD_OUTD1		; LOOP TILL NOT BUSY
 	POP	AF			; RECOVER BYTE
+	LCD_XDELAY
 	EZ80_IO
 	OUT	(LCD_DATA),A		; SEND IT
 	RET				; DONE
@@ -408,11 +418,13 @@ LCD_OUTDS:
 ; GET DATA BYTE INTO A
 ;
 LCD_IND:
+	LCD_XDELAY
 	EZ80_IO
 	IN	A,(LCD_STAT)		; GET STATUS
 	AND	$80			; ISOLATE BUSY FLAG
 	JR	NZ,LCD_IND		; LOOP TILL NOT BUSY
 	POP	AF			; RECOVER BYTE
+	LCD_XDELAY
 	EZ80_IO
 	IN	A,(LCD_DATA)		; GET IT
 	RET				; DONE
@@ -483,10 +495,9 @@ LCD_INIT_SEQ:
 	.DB	$00			; TERMINATOR
 ;
 LCD_STR_BAN	.DB	"RomWBW v", BIOSVER, 0
-LCD_STR_CFG	.DB	"Build: ", CONFIG, 0
+LCD_STR_CFG	.DB	CONFIG, 0
 LCD_STR_IO	.DB	"Disk #", 0
 LCD_STR_XPU	.DB	" CPU",0
-;;;LCD_STR_SPD	.DB	"12.345",0
 LCD_STR_MHZ	.DB	" MHz",0
 ;
 LCD_CPU		.DW	LCD_CPU_Z80
@@ -498,8 +509,8 @@ LCD_CPU		.DW	LCD_CPU_Z80
 ;
 LCD_CPU_Z80	.DB	"Z80",0
 LCD_CPU_Z180	.DB	"Z180",0
-LCD_CPU_Z180K	.DB	"Z180-K",0
-LCD_CPU_Z180N	.DB	"Z180-N",0
+LCD_CPU_Z180K	.DB	"Z180K",0
+LCD_CPU_Z180N	.DB	"Z180N",0
 LCD_CPU_Z280	.DB	"Z280",0
 LCD_CPU_EZ80	.DB	"eZ80",0
 ;

Source/HBIOS/lpt.asm

@@ -95,10 +95,18 @@ LPT_INIT:
 	LD	IY,LPT_CFG		; POINT TO START OF CFG TABLE
 LPT_INIT0:
 	PUSH	BC			; SAVE LOOP CONTROL
+	CALL	LPT_PRTCFG		; PRINT CONFIG
 	CALL	LPT_INITUNIT		; HAND OFF TO UNIT INIT CODE
 	POP	BC			; RESTORE LOOP CONTROL
 ;
-	LD	A,(IY+1)		; GET THE LPT TYPE DETECTED
+	JR	Z,LPT_INIT1		; IF DETECTED, CONTINUE INIT
+	CALL	PC_SPACE		; FORMATTING
+	LD	DE,LPT_STR_NOLPT	; NO LPT MESSAGE
+	CALL	WRITESTR		; DISPLAY IT
+	JR	LPT_INIT2		; AND LOOP AS NEEDED
+;
+LPT_INIT1:
+	LD	A,(IY+1)		; GET THE LPT TYPE
 	OR	A			; SET FLAGS
 	JR	Z,LPT_INIT2		; SKIP IT IF NOTHING FOUND
 ;
@@ -107,7 +115,6 @@ LPT_INIT0:
 	POP	DE			; ... TO DE
 	LD	BC,LPT_FNTBL		; BC := FUNCTION TABLE ADDRESS
 	CALL	NZ,CIO_ADDENT		; ADD ENTRY IF LPT FOUND, BC:DE
-	CALL	LPT_PRTCFG		; PRINT IF NOT ZERO
 	POP	BC			; RESTORE LOOP CONTROL
 ;
 LPT_INIT2:
@@ -123,9 +130,7 @@ LPT_INIT3:
 ;
 LPT_INITUNIT:
 	CALL	LPT_DETECT		; DETERMINE LPT TYPE
-	LD	(IY+1),A		; SAVE IN CONFIG TABLE
-	OR	A			; SET FLAGS
-	RET	Z			; ABORT IF NOTHING THERE
+	RET	NZ			; ABORT IF NOTHING THERE
 ;
 	; UPDATE WORKING LPT DEVICE NUM
 	LD	HL,LPT_DEV		; POINT TO CURRENT DEVICE NUM
@@ -326,15 +331,7 @@ LPT_DETECT:
 ;
 LPT_DETECT:
 	LD	C,(IY+3)		; BASE PORT ADDRESS
-	CALL	LPT_DETECT2		; CHECK IT
-	JR	Z,LPT_DETECT1		; FOUND IT, RECORD IT
-	LD	A,LPTMODE_NONE		; NOTHING FOUND
-	RET				; DONE
-;
-LPT_DETECT1:
-	; LPT FOUND, RECORD IT
-	LD	A,LPTMODE_SPP		; RETURN CHIP TYPE
-	RET				; DONE
+	JR	LPT_DETECT2		; CHECK IT
 ;
 LPT_DETECT2:
 	; LOOK FOR LPT AT BASE PORT ADDRESS IN C
@@ -394,20 +391,13 @@ LPT_DETECT:
 	CALL	PRTHEXBYTE
   #ENDIF
 	CP	$A5			; CHECK FOR TEST VALUE
-	JR	Z,LPT_DETECT1		; FOUND IT
-	LD	A,LPTMODE_NONE		; NOT FOUND
-	RET
-;
-LPT_DETECT1:
-	; LPT FOUND, RECORD IT
-	LD	A,LPTMODE_MG014		; RETURN CHIP TYPE
-	RET				; DONE
+	RET				; ZF SET IF DETECTED
 #ENDIF
 ;
 #IF (LPTMODE == LPTMODE_S100)
 LPT_DETECT:
 	; PORT ALWAYS EXISTS ON FPGA
-	LD	A,LPTMODE_S100		; RETURN CHIP TYPE
+	XOR	A			; SIGNAL SUCCESS
 	RET				; DONE
 #ENDIF
 ;
@@ -417,7 +407,7 @@ LPT_PRTCFG:
 	; ANNOUNCE PORT
 	CALL	NEWLINE			; FORMATTING
 	PRTS("LPT$")			; FORMATTING
-	LD	A,(IY)			; DEVICE NUM
+	LD	A,(IY+2)		; DEVICE NUM
 	CALL	PRTDECB			; PRINT DEVICE NUM
 	PRTS(": IO=0x$")		; FORMATTING
 	LD	A,(IY+3)		; GET BASE PORT
@@ -452,11 +442,13 @@ LPT_TYPE_MAP:
 		.DW	LPT_STR_MG014
 		.DW	LPT_STR_S100
 ;
-LPT_STR_NONE	.DB	"<NOT PRESENT>$"
+LPT_STR_NONE	.DB	"???$"
 LPT_STR_SPP	.DB	"SPP$"
 LPT_STR_MG014	.DB	"MG014$"
 LPT_STR_S100	.DB	"S100$"
 ;
+LPT_STR_NOLPT	.DB	"NOT PRESENT$"
+;
 ; WORKING VARIABLES
 ;
 LPT_DEV		.DB	0		; DEVICE NUM USED DURING INIT
@@ -468,7 +460,7 @@ LPT_CFG:
 LPT0_CFG:
 	; LPT MODULE A CONFIG
 	.DB	0			; DEVICE NUMBER (SET DURING INIT)
-	.DB	0			; LPT TYPE (SET DURING INIT)
+	.DB	LPTMODE			; LPT MODE
 	.DB	0			; MODULE ID
 	.DB	LPT0BASE		; BASE PORT
 	.DW	0			; LINE CONFIGURATION
@@ -494,7 +486,7 @@ LPT_CFGSIZ	.EQU	$ - LPT_CFG	; SIZE OF ONE CFG TABLE ENTRY
 LPT1_CFG:
 	; LPT MODULE B CONFIG
 	.DB	0			; DEVICE NUMBER (SET DURING INIT)
-	.DB	0			; LPT TYPE (SET DURING INIT)
+	.DB	LPTMODE			; LPT MODE
 	.DB	1			; MODULE ID
 	.DB	LPT1BASE		; BASE PORT
 	.DW	0			; LINE CONFIGURATION

Source/HBIOS/md.asm

@@ -359,6 +359,7 @@ MD_RDSECF:				; CALLED FROM MD_RW
 					; SAVE THE 4K LBA FOR FUTURE CHECKS
 ;
 	CALL	MD_CALBAS		; SETUP BANK AND SECTOR
+	RET	NZ			; RETURN IF ERROR
 ;
 	LD	IX,MD_F4KBUF		; SET DESTINATION ADDRESS
 	LD	HL,MD_FREAD_R		; PUT ROUTINE TO CALL
@@ -467,7 +468,18 @@ MD_CALBAS:
 	CALL	PRTHEXWORD		; DISPLAY BANK AND
 	CALL	PC_SPACE		; SECTOR RESULT
 #ENDIF
-
+;
+	; CHECK FOR ACCESS BEYOND AVAILABLE ROM BANKS
+	LD	A,B			; BANK ID TO ACCUM
+	SUB	BID_ROMD0		; ZERO OFFSET
+	CP	ROMD_BNKS		; CHECK FOR OUT OF BOUNDS
+	JR	C,MD_CALBAS1		; IF NOT, CONTINUE
+	LD	A,ERR_IO		; ELSE SIGNAL IO ERROR
+	OR	A			; SET FLAGS
+	RET				; AND RETURN
+;
+MD_CALBAS1:
+	XOR	A			; SIGNAL SUCCESS
 	RET
 ;
 ; WRITE FLASH
@@ -485,6 +497,7 @@ MD_WRSECF:				; CALLED FROM MD_RW
 	LD	(MD_LBA4K),BC		; SAVE 4K LBA
 ;
 	CALL	MD_CALBAS		; SETUP BANK AND SECTOR
+	RET	NZ			; RETURN ON ERROR
 ;
 	LD	IX,MD_F4KBUF		; SET DESTINATION ADDRESS
 	LD	HL,MD_FREAD_R		; PUT ROUTINE TO CALL
@@ -566,6 +579,12 @@ MD_FBAS		.DW	$FFFF		; BANK AND SECTOR
 ;
 MD_RDSEC:
 	CALL	MD_IOSETUP		; SETUP FOR MEMORY COPY
+	CP	$FF			; ERROR?
+	JR	NZ,MD_RDSEC1		; IF NOT, CONTINUE
+	LD	A,ERR_IO		; SIGNAL IO ERROR
+	OR	A			; SET FLAGS
+	RET				; AND DONE
+MD_RDSEC1:
 #IF (MDTRACE >= 2)
 	LD	(MD_SRC),HL
 	LD	(MD_DST),DE
@@ -597,6 +616,12 @@ MD_RDSEC:
 ;
 MD_WRSEC:
 	CALL	MD_IOSETUP		; SETUP FOR MEMORY COPY
+	CP	$FF			; ERROR?
+	JR	NZ,MD_WRSEC1		; IF NOT, CONTINUE
+	LD	A,ERR_IO		; SIGNAL IO ERROR
+	OR	A			; SET FLAGS
+	RET				; AND DONE
+MD_WRSEC1:
 	EX	DE,HL			; SWAP SRC/DEST FOR WRITE
 #IF (MDTRACE >= 2)
 	LD	(MD_SRC),HL
@@ -682,13 +707,21 @@ MD_IOSETUP:
 	JR	Z,MD_IOSETUP2		; DO ROM DRIVE, ELSE FALL THRU FOR RAM DRIVE
 ;
 MD_IOSETUP1:	; ROM
+	CP	ROMD_BNKS		; WITHIN AVAILABLE ROM DISK BANKS?
+	JR	NC,MD_IOSETUP3		; HANDLE OUT OF BOUNDS
 	ADD	A,BID_ROMD0
 	RET
 ;
 MD_IOSETUP2:	; RAM
+	CP	RAMD_BNKS		; WITHIN AVAILABLE RAM DISK BANKS?
+	JR	NC,MD_IOSETUP3		; HANDLE OUT OF BOUNDS
 	ADD	A,BID_RAMD0
 	RET
 ;
+MD_IOSETUP3:
+	OR	$FF			; SIGNAL ERROR
+	RET				; DONE
+;
 ;
 ;
 #IF (MDTRACE >= 2)

Source/HBIOS/pcf.asm

@@ -66,26 +66,10 @@ PCF_BB		.EQU  00000001B
 ; |  12MHz  |       |        |       |         |        | 90Khz | 120Khz |   138Khz  |  150Khz |
 ; +----------------------------------------------------------------------------------+---------+
 ;
-; CLOCK CHIP FREQUENCIES
+; SEE STD.ASM FOR DEFINITIONS OF PCFCLK AND PCFTRNS VALUES
 ;
-PCF_CLK3   	.EQU	000H
-PCF_CLK443 	.EQU	010H
-PCF_CLK6   	.EQU	014H
-PCF_CLK8   	.EQU	018H
-PCF_CLK12  	.EQU	01CH
-;
-; TRANSMISSION FREQUENCIES
-;
-PCF_TRNS90 	.EQU	000H	;  90 kHz */
-PCF_TRNS45 	.EQU	001H	;  45 kHz */
-PCF_TRNS11 	.EQU	002H	;  11 kHz */
-PCF_TRNS15 	.EQU	003H	; 1.5 kHz */
-;
-; BELOW VARIABLES CONTROL PCF CLOCK DIVISOR PROGRAMMING
-; HARD-CODED FOR NOW
-;
-PCF_CLK	  	.EQU	PCF_CLK12
-PCF_TRNS	.EQU	PCF_TRNS90
+PCF_CLK	  	.EQU	PCFCLK
+PCF_TRNS	.EQU	PCFTRNS
 ;
 ; TIMEOUT AND DELAY VALUES (ARBITRARY)
 ;

Source/HBIOS/romldr.asm

@@ -1553,7 +1553,7 @@ s100mon1:
 	; Launch S100 Monitor from ROM Bank 3
 	call	ldelay			; wait for UART buf to empty
 	di				; suspend interrupts
-	ld	a,BID_IMG2		; S100 monitor bank
+	ld	a,HWMON_BNK		; S100 monitor bank
 	ld	ix,0			; execution resumes here
 	jp	HB_BNKCALL		; do it
 ;
@@ -2629,31 +2629,32 @@ ra_ent		.equ	12
 ;
 ra_tbl:
 ;
-;      Name	  Key	   Dsky	  Bank	    Src	         Dest	    Size     Entry
-;      ---------  -------  -----  --------  -----        -------  -------  ----------
-ra_ent(str_mon,	  'M',	   KY_CL, BID_IMG0, MON_IMGLOC,  MON_LOC, MON_SIZ, MON_SERIAL)
-ra_entsiz	.equ	$ - ra_tbl
-#if (BIOS == BIOS_WBW)
-  #if (PLATFORM == PLT_S100)
-ra_ent(str_smon,  'S',	   $FF,	  bid_cur , $8000,       $8000,   $0001,   s100mon)
-  #endif
-#endif
-ra_ent(str_cpm22, 'C',	   KY_BK, BID_IMG0, CPM_IMGLOC,  CPM_LOC, CPM_SIZ, CPM_ENT)
-ra_ent(str_zsys,  'Z',	   KY_FW, BID_IMG0, ZSYS_IMGLOC, CPM_LOC, CPM_SIZ, CPM_ENT)
-#if (BIOS == BIOS_WBW)
-ra_ent(str_bas,	  'B',	   KY_DE, BID_IMG1, BAS_IMGLOC,  BAS_LOC, BAS_SIZ, BAS_LOC)
-ra_ent(str_tbas,  'T',	   KY_EN, BID_IMG1, TBC_IMGLOC,  TBC_LOC, TBC_SIZ, TBC_LOC)
-ra_ent(str_fth,	  'F',	   KY_EX, BID_IMG1, FTH_IMGLOC,  FTH_LOC, FTH_SIZ, FTH_LOC)
-ra_ent(str_play,  'P',	   $FF,	  BID_IMG1, GAM_IMGLOC,  GAM_LOC, GAM_SIZ, GAM_LOC)
-ra_ent(str_net,   'N',	   $FF,	  BID_IMG1, NET_IMGLOC,  NET_LOC, NET_SIZ, NET_LOC)
-ra_ent(str_upd,   'X',	   $FF,	  BID_IMG1, UPD_IMGLOC,  UPD_LOC, UPD_SIZ, UPD_LOC)
-ra_ent(str_nvr,   'W'+$80, $FF,	  BID_IMG1, NVR_IMGLOC,  NVR_LOC, NVR_SIZ, NVR_LOC)
-ra_ent(str_user,  'U',	   $FF,	  BID_IMG1, USR_IMGLOC,  USR_LOC, USR_SIZ, USR_LOC)
+;      Name	  Key	   Dsky	  Bank	     Src	   Dest	    Size     Entry
+;      ---------  -------  -----  --------   -----         -------  -------  ----------
+ra_ent(str_mon,	  'M',	   KY_CL, MON_BNK,   MON_IMGLOC,   MON_LOC, MON_SIZ, MON_SERIAL)
+ra_entsiz	.equ	$ - ra_tbl                         
+#if (BIOS == BIOS_WBW)                                     
+  #if (PLATFORM == PLT_S100)                               
+ra_ent(str_smon,  'S',	   $FF,	  bid_cur,   $8000,        $8000,   $0001,   s100mon)
+  #endif                                                   
+#endif                                                     
+ra_ent(str_cpm22, 'C',	   KY_BK, CPM22_BNK, CPM22_IMGLOC, CPM_LOC, CPM_SIZ, CPM_ENT)
+ra_ent(str_zsys,  'Z',	   KY_FW, ZSYS_BNK,  ZSYS_IMGLOC,  CPM_LOC, CPM_SIZ, CPM_ENT)
+#if (BIOS == BIOS_WBW)                                     
+ra_ent(str_bas,	  'B',	   KY_DE, BAS_BNK,   BAS_IMGLOC,   BAS_LOC, BAS_SIZ, BAS_LOC)
+ra_ent(str_tbas,  'T',	   KY_EN, TBC_BNK,   TBC_IMGLOC,   TBC_LOC, TBC_SIZ, TBC_LOC)
+ra_ent(str_fth,	  'F',	   KY_EX, FTH_BNK,   FTH_IMGLOC,   FTH_LOC, FTH_SIZ, FTH_LOC)
+ra_ent(str_play,  'P',	   $FF,	  GAM_BNK,   GAM_IMGLOC,   GAM_LOC, GAM_SIZ, GAM_LOC)
+ra_ent(str_net,   'N',	   $FF,	  NET_BNK,   NET_IMGLOC,   NET_LOC, NET_SIZ, NET_LOC)
+ra_ent(str_upd,   'X',	   $FF,	  UPD_BNK,   UPD_IMGLOC,   UPD_LOC, UPD_SIZ, UPD_LOC)
+ra_ent(str_nvr,   'W'+$80, $FF,	  NVR_BNK,   NVR_IMGLOC,   NVR_LOC, NVR_SIZ, NVR_LOC)
+ra_ent(str_user,  'U',	   $FF,	  USR_BNK,   USR_IMGLOC,   USR_LOC, USR_SIZ, USR_LOC)
 #endif
 #if (DSKYENABLE)
-ra_ent(str_dsky,  'Y'+$80, KY_GO, BID_IMG0, MON_IMGLOC,  MON_LOC, MON_SIZ, MON_DSKY)
+ra_ent(str_dsky,  'Y'+$80, KY_GO, MON_BNK,   MON_IMGLOC,   MON_LOC, MON_SIZ, MON_DSKY)
 #endif
-ra_ent(str_egg,	  'E'+$80, $FF,   BID_IMG1, EGG_IMGLOC,  EGG_LOC, EGG_SIZ, EGG_LOC)
+ra_ent(str_egg,	  'E'+$80, $FF,   EGG_BNK,   EGG_IMGLOC,   EGG_LOC, EGG_SIZ, EGG_LOC)
+;
 		.dw	0		; table terminator
 ;
 ra_tbl_app:
@@ -2665,6 +2666,7 @@ ra_ent(str_zsys,  'Z',	   KY_FW, bid_cur,  ZSYS_IMGLOC, CPM_LOC, CPM_SIZ, CPM_EN
 #if (DSKYENABLE)
 ra_ent(str_dsky,  'Y'+$80, KY_GO, bid_cur,  MON_IMGLOC,  MON_LOC, MON_SIZ, MON_DSKY)
 #endif
+;
 		.dw	0		; table terminator
 ;
 str_mon		.db	"Monitor",0

Source/HBIOS/rp5rtc.asm

@@ -136,7 +136,7 @@ RP5RTC_DETECT:
 
 RP5RTC_DETECT1:
 	PUSH	AF			; SAVE STATUS
-	LD	A, L			; GET SAVED VALUE
+	LD	E, L			; GET SAVED VALUE
 	LD	C, 0 			; NVRAM INDEX 0
 	CALL	RP5RTC_SETBYT		; SAVE IT
 	POP	AF			; RECOVER STATUS

Source/HBIOS/std.asm

@@ -327,6 +327,21 @@ SYQMODE_NONE	.EQU	0		; NONE
 SYQMODE_SPP	.EQU	1		; IBM PC STANDARD PAR PORT (SPP)
 SYQMODE_MG014	.EQU	2		; RCBUS MG014 STYLE INTERFACE
 ;
+; PCF CLOCK CHIP FREQUENCIES
+;
+PCFCLK_3   	.EQU	$00		;  3    MHz 
+PCFCLK_443 	.EQU	$10            ;  4.43 MHz
+PCFCLK_6   	.EQU	$14            ;  6    MHz 
+PCFCLK_8   	.EQU	$18            ;  8    MHz 
+PCFCLK_12  	.EQU	$1C            ; 12    MHz 
+;
+; PCF TRANSMISSION FREQUENCIES
+;
+PCFTRNS_90 	.EQU	$00		; 90   KHZ
+PCFTRNS_45 	.EQU	$01		; 45   KHZ
+PCFTRNS_11 	.EQU	$02		; 11   KHZ
+PCFTRNS_15 	.EQU	$03		;  1.5 KHZ
+;
 ; GDC MONITOR SELECTIONS
 ;
 GDCMON_NONE	.EQU	0
@@ -866,8 +881,8 @@ ROMD_BNKS	.SET	0
 ;										-- TYPICAL --
 BID_BOOT	.EQU	BID_ROM0 + 0	; BOOT BANK				0x00
 BID_IMG0	.EQU	BID_ROM0 + 1	; ROM LOADER AND FIRST IMAGES BANK	0x01
-BID_IMG1	.EQU	BID_ROM0 + 2	; SECOND IMAGES BANK		 	0x02
-BID_IMG2	.EQU	BID_ROM0 + 3	; RESERVED				0x03
+BID_IMG1	.EQU	BID_ROM0 + 2	; ROM APPS IMAGES BANK		 	0x02
+BID_IMG2	.EQU	BID_ROM0 + 3	; ROM UTILITIES IMAGES BANK		0x03
 BID_ROMD0	.EQU	BID_ROM0 + 4	; FIRST ROM DRIVE BANK			0x04
 BID_BIOS	.EQU	BID_RAM0 + 0	; HBIOS BANK				0x80
 BID_RAMD0	.EQU	BID_RAM0 + 1	; FIRST RAM DRIVE BANK			0x81
@@ -884,8 +899,8 @@ BID_COM		.EQU	BID_RAMN - 0	; COMMON BANK, UPPER 32K		0x8F
 ;										-- TYPICAL --
 BID_BOOT	.EQU	BID_RAM0 + 0	; BOOT BANK				0x80
 BID_IMG0	.EQU	BID_RAM0 + 1	; ROM LOADER AND FIRST IMAGES BANK	0x81
-BID_IMG1	.EQU	BID_RAM0 + 2	; SECOND IMAGES BANK		 	0x82
-BID_IMG2	.EQU	BID_RAM0 + 3	; RESERVED				0x83
+BID_IMG1	.EQU	BID_RAM0 + 2	; ROM APPS IMAGES BANK		 	0x82
+BID_IMG2	.EQU	BID_RAM0 + 3	; ROM UTILITIES IMAGES BANK		0x83
 BID_RAMD0	.EQU	BID_RAM0 + 4	; FIRST RAM DRIVE BANK			0x84
 BID_APP0	.EQU	BID_RAMD0 + RAMD_BNKS	; FIRST APP BANK		0x89
 BID_BUF		.EQU	BID_RAMN - 3	; OS BUFFERS (CP/M3)			0x8C
@@ -1078,8 +1093,8 @@ INT_PIO1B	.EQU	12	; ZILOG PIO 1, CHANNEL B
 #ENDIF
 
 
-#DEFINE IVT(INTX) HB_IVT+(INTX * 4)+1
-#DEFINE VEC(INTX) INTX*2
+#DEFINE IVT(INTX) HB_IVT + (INTX * 4) + 1
+#DEFINE VEC(INTX) INTX * 2
 
 ;
 ; SET DEFAULT CSIO SPEED (INTERNAL CLOCK, SLOW AS POSSIBLE)

Source/Images/Build.cmd

@@ -21,6 +21,7 @@ call BuildDisk.cmd aztecc fd wbw_fd144 || exit /b
 call BuildDisk.cmd hitechc fd wbw_fd144 || exit /b
 call BuildDisk.cmd tpascal fd wbw_fd144 || exit /b
 call BuildDisk.cmd bascomp fd wbw_fd144 || exit /b
+call BuildDisk.cmd cobol fd wbw_fd144 || exit /b
 call BuildDisk.cmd fortran fd wbw_fd144 || exit /b
 call BuildDisk.cmd games fd wbw_fd144 || exit /b
 call BuildDisk.cmd cowgol fd wbw_fd144 || exit /b
@@ -43,6 +44,7 @@ call BuildDisk.cmd aztecc hd wbw_hd512 || exit /b
 call BuildDisk.cmd hitechc hd wbw_hd512 || exit /b
 call BuildDisk.cmd tpascal hd wbw_hd512 || exit /b
 call BuildDisk.cmd bascomp hd wbw_hd512 || exit /b
+call BuildDisk.cmd cobol hd wbw_hd512 || exit /b
 call BuildDisk.cmd fortran hd wbw_hd512 || exit /b
 call BuildDisk.cmd games hd wbw_hd512 || exit /b
 call BuildDisk.cmd cowgol hd wbw_hd512 || exit /b
@@ -70,6 +72,7 @@ call BuildDisk.cmd aztecc hd wbw_hd1k || exit /b
 call BuildDisk.cmd hitechc hd wbw_hd1k || exit /b
 call BuildDisk.cmd tpascal hd wbw_hd1k || exit /b
 call BuildDisk.cmd bascomp hd wbw_hd1k || exit /b
+call BuildDisk.cmd cobol hd wbw_hd1k || exit /b
 call BuildDisk.cmd fortran hd wbw_hd1k || exit /b
 call BuildDisk.cmd games hd wbw_hd1k || exit /b
 call BuildDisk.cmd cowgol hd wbw_hd1k || exit /b
@@ -83,3 +86,4 @@ copy hd1k_prefix.dat ..\..\Binary\ || exit /b
 echo.
 echo Building Combo Disk (1024 directory entry format) Image...
 copy /b hd1k_prefix.dat + ..\..\Binary\hd1k_cpm22.img + ..\..\Binary\hd1k_zsdos.img + ..\..\Binary\hd1k_nzcom.img + ..\..\Binary\hd1k_cpm3.img + ..\..\Binary\hd1k_zpm3.img + ..\..\Binary\hd1k_ws4.img ..\..\Binary\hd1k_combo.img || exit /b
+

Source/Images/Makefile

@@ -8,7 +8,7 @@ FDIMGS = fd144_cpm22.img fd144_zsdos.img fd144_nzcom.img \
 	fd144_z3plus.img \
 	fd144_z80asm.img fd144_aztecc.img fd144_hitechc.img \
 	fd144_bascomp.img fd144_fortran.img fd144_games.img \
-	fd144_tpascal.img fd144_cowgol.img
+	fd144_tpascal.img fd144_cowgol.img fd144_cobol.img
 HD512IMGS = hd512_cpm22.img hd512_zsdos.img hd512_nzcom.img \
 	hd512_cpm3.img hd512_zpm3.img hd512_ws4.img
 HD512XIMGS = hd512_z80asm.img hd512_aztecc.img hd512_hitechc.img \
@@ -16,7 +16,7 @@ HD512XIMGS = hd512_z80asm.img hd512_aztecc.img hd512_hitechc.img \
 	hd512_tpascal.img hd512_dos65.img hd512_qpm.img \
 	hd512_z3plus.img \
 	hd512_cowgol.img hd512_msxroms1.img hd512_msxroms2.img \
-	hd512_blank.img
+	hd512_cobol.img  hd512_blank.img
 HD1KIMGS = hd1k_cpm22.img hd1k_zsdos.img hd1k_nzcom.img \
 	hd1k_cpm3.img hd1k_zpm3.img hd1k_ws4.img
 HD1KXIMGS = hd1k_z80asm.img hd1k_aztecc.img hd1k_hitechc.img \
@@ -24,7 +24,7 @@ HD1KXIMGS = hd1k_z80asm.img hd1k_aztecc.img hd1k_hitechc.img \
 	hd1k_tpascal.img hd1k_qpm.img \
 	hd1k_z3plus.img \
 	hd1k_cowgol.img hd1k_msxroms1.img hd1k_msxroms2.img \
-	hd1k_blank.img
+	hd1k_cobol.img hd1k_blank.img
 HD1KXIMGS += hd1k_bp.img
 
 HD512PREFIX =

Source/Images/d_cobol/Readme.txt

@@ -0,0 +1,15 @@
+===== Microsoft COBOL-80 Compiler v.4.01 =====
+
+This is Microsoft's is Microsoft's COBOL-80, which runs on the 8080/Z-80/8085, 
+brings the world's most widely used computer programming language to the 
+microcomputer user. COBOL-80 is comparable to COBOL systems found on mini-
+computers and large mainframes. Consequently, it greatly enhances the
+usefulness of microcomputers because it gives users access to the
+incredibly large number of programs already written in COBOL. Because
+COBOL-80 is a standard, COBOL programs written on other computers may
+be run easily on 8080, z-80 or 8085 systems. 
+
+
+The user manual is available in the Doc/Language directory,
+Microsoft_COBOL-80_Manuals_1878.pdf
+