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21 lines
855 B
21 lines
855 B
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; ZETA 2 HARDWARE DEFINITIONS
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;
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#DEFINE PLATFORM_NAME "ZETA V2"
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SBC_BASE .EQU $60 ; I/O BASE ADDRESS FOR ONBOARD PERIPHERALS
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;
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MPGSEL_0 .EQU SBC_BASE + $18 ; BANK_0 PAGE SELECT REGISTER (WRITE ONLY)
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MPGSEL_1 .EQU SBC_BASE + $19 ; BANK_1 PAGE SELECT REGISTER (WRITE ONLY)
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MPGSEL_2 .EQU SBC_BASE + $1A ; BANK_2 PAGE SELECT REGISTER (WRITE ONLY)
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MPGSEL_3 .EQU SBC_BASE + $1B ; BANK_3 PAGE SELECT REGISTER (WRITE ONLY)
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MPGENA .EQU SBC_BASE + $1C ; PAGING ENABLE REGISTER - BIT 0 = 1 (WRITE ONLY)
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;
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RTC .EQU SBC_BASE + $10 ; ADDRESS OF RTC LATCH AND INPUT PORT
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PPIBASE .EQU SBC_BASE + $00 ; PPI 82C55 I/O IS DECODED TO PORT 60-67
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;
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CTCBASE .EQU $20 ; CTC BASE I/O ADDRESS
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CTCA .EQU CTCBASE + 0 ; CTC CHANNEL A
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CTCB .EQU CTCBASE + 1 ; CTC CHANNEL B
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CTCC .EQU CTCBASE + 2 ; CTC CHANNEL C
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CTCD .EQU CTCBASE + 3 ; CTC CHANNEL D
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