mirror of
https://github.com/wwarthen/RomWBW.git
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52 lines
1.4 KiB
Plaintext
52 lines
1.4 KiB
Plaintext
SUBTTL "PRECLOCK.LIB - Test for Clock Tick - 12/12/88"
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;---------------------------------------------------------------
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; Read clock and wait for seconds to roll - watchdog protected
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; Enter with: DE pointing to relocated clock read routine
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; HL pointing to base of high module
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TSTRD: JR TSTRD0 ; Jump around address store
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DEFW TSTRD ; Org location of the code
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TSTRD0: LD (CKCLK+1),DE ; Patch GETTIM address in
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CALL CKCLK ; Get time to start with
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DEC A ; WBW: 1 -> 0
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JR NZ,BAD ; WBW: NO GOOD
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LD A,(HL) ; Get seconds
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CP 60H ; Check for valid digit
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JR NC,BAD ; >= 60h
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LD BC,0 ; Set watchdog
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TST0: DEC BC ; One less remaining...
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LD A,B
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OR C
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RET Z ; Exit w/cy clear if timed out
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PUSH BC ; Save watchdog
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LD B,MHZ ; insure good at up to 25mhz
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TST1: EX (SP),HL ; ..under absolute worst case
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EX (SP),HL
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DJNZ TST1 ; waste time (41t/loop)
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CALL CKCLK ; Read the clock
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POP BC ; Restore watchdog
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LD A,(HL)
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SUB E ; New - old
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DAA
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JR Z,TST0 ; If no action, try again
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JR NC,TST2 ; New > old
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ADD A,60H ; Adjust for seconds rollover
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DAA
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TST2: SUB 2 ; Allow 2 sec tolerance
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DAA
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RET C ; Cy set is good
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BAD: OR A ; Cy clear is bad
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RET
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LOCBUF: DEFS 6
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; Set registers and read the clock
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CKCLK: LD HL,0000 ; Set up in beginning
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PUSH HL ; Go to this address
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LD C,00 ; Tell the clock we are reading
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LD HL,LOCBUF
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RET
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