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Add Heathkit H8 support. Front panel generates interrupts at 500Hz to update the LEDs and read the front panel keypad.

work
Les Bird 1 year ago
parent
8e0af1720a
commit
03e34a54d4
4 changed files with 876 additions and 162 deletions
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  1. 41
      Source/HBIOS/Config/HEATH_std.asm
  2. 32
      Source/HBIOS/cfg_heath.asm
  3. 927
      Source/HBIOS/h8p.asm
  4. 32
      Source/HBIOS/hbios.asm

41
Source/HBIOS/Config/HEATH_std.asm
View File

@ -26,44 +26,3 @@
; ;
#include "cfg_heath.asm" #include "cfg_heath.asm"
; ;
CPUOSC .SET 7372800 ; CPU OSC FREQ IN MHZ
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
;
DSKYENABLE .SET TRUE ; ENABLES DSKY FUNCTIONALITY
H8PENABLE .SET TRUE ; ENABLES HEATH H8 FRONT PANEL
;
FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS
FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES
;
DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
;
UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
ACIAENABLE .SET TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
;
LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
;
TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
MKYENABLE .SET FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
;
AY38910ENABLE .SET FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER
AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER
;
FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
;
IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_PIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|USR]
SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY
IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
;
PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)

32
Source/HBIOS/cfg_heath.asm
View File

@ -1,6 +1,6 @@
; ;
;================================================================================================== ;==================================================================================================
; ROMWBW 3.X CONFIGURATION DEFAULTS FOR RCBUS Z80
; ROMWBW 3.X CONFIGURATION DEFAULTS FOR HEATHKIT Z80
;================================================================================================== ;==================================================================================================
; ;
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM ; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@ -11,7 +11,7 @@
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS ; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
; FOR THE PLATFORM. ; FOR THE PLATFORM.
; ;
#DEFINE PLATFORM_NAME "RCBus", " [", CONFIG, "]"
#DEFINE PLATFORM_NAME "HEATHKIT", " [", CONFIG, "]"
; ;
#INCLUDE "hbios.inc" #INCLUDE "hbios.inc"
; ;
@ -29,7 +29,7 @@ AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
; ;
CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
CPUOSC .EQU 7372800 ; CPU OSC FREQ IN MHZ
CPUOSC .EQU 16384000 ; CPU OSC FREQ IN MHZ
INTMODE .EQU 1 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) INTMODE .EQU 1 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
DEFSERCFG .EQU SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) DEFSERCFG .EQU SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
; ;
@ -72,7 +72,7 @@ WDOGIO .EQU $6E ; WATCHDOG REGISTER ADR
FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS
FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS
FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED
FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
FPLED_DSKACT .EQU FALSE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES
FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES
FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED
@ -85,13 +85,13 @@ LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS
LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
; ;
DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY
DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
DSKYDSKACT .EQU FALSE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI
PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259) PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI
PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL
H8PENABLE .EQU TRUE ; ENABLES HEATH H8 FRONT PANEL
; ;
BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE
SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE
@ -105,7 +105,7 @@ KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
; ;
DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCENABLE .EQU FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W] DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
; ;
@ -146,7 +146,7 @@ DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
; ;
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTCNT .EQU 2 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
UARTCNT .EQU 4 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
@ -155,9 +155,9 @@ UART0BASE .EQU $E8 ; UART 0: REGISTERS BASE ADR
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
UART1BASE .EQU $E0 ; UART 1: REGISTERS BASE ADR UART1BASE .EQU $E0 ; UART 1: REGISTERS BASE ADR
UART1CFG .EQU DEFSERCFG ; UART 1: SERIAL LINE CONFIG UART1CFG .EQU DEFSERCFG ; UART 1: SERIAL LINE CONFIG
UART2BASE .EQU $FF ; UART 2: REGISTERS BASE ADR
UART2BASE .EQU $D8 ; UART 2: REGISTERS BASE ADR
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
UART3BASE .EQU $FF ; UART 3: REGISTERS BASE ADR
UART3BASE .EQU $D0 ; UART 3: REGISTERS BASE ADR
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
@ -172,7 +172,7 @@ ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
; ;
Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
; ;
ACIAENABLE .EQU TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
ACIADEBUG .EQU FALSE ; ACIA: ENABLE DEBUG OUTPUT ACIADEBUG .EQU FALSE ; ACIA: ENABLE DEBUG OUTPUT
ACIACNT .EQU 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2) ACIACNT .EQU 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
ACIA0BASE .EQU $80 ; ACIA 0: REGISTERS BASE ADR ACIA0BASE .EQU $80 ; ACIA 0: REGISTERS BASE ADR
@ -184,7 +184,7 @@ ACIA1CLK .EQU CPUOSC ; ACIA 1: OSC FREQ IN HZ
ACIA1DIV .EQU 1 ; ACIA 1: SERIAL CLOCK DIVIDER ACIA1DIV .EQU 1 ; ACIA 1: SERIAL CLOCK DIVIDER
ACIA1CFG .EQU DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM) ACIA1CFG .EQU DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM)
; ;
SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
@ -212,7 +212,7 @@ CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
TMSMODE .EQU TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] TMSMODE .EQU TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
TMS80COLS .EQU FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
TMS80COLS .EQU TRUE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
@ -225,7 +225,7 @@ MDRAM .EQU TRUE ; MD: ENABLE RAM DISK
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM
; ;
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDENABLE .EQU TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
@ -257,7 +257,7 @@ IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER
IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER
; ;
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDEENABLE .EQU TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
PPIDE0BASE .EQU $20 ; PPIDE 0: PPI REGISTERS BASE ADR PPIDE0BASE .EQU $20 ; PPIDE 0: PPI REGISTERS BASE ADR
@ -337,7 +337,7 @@ SNMODE .EQU SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
; ;
AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
AYMODE .EQU AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
AYMODE .EQU AYMODE_MSX ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
; ;
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
; ;

927
Source/HBIOS/h8p.asm
View File

@ -12,8 +12,31 @@
; +--10--+ 80 ; +--10--+ 80
; ;
; ;
DEVECHO "H8P: IO=??"
;DEVECHO 0
H8PKEYNONE .EQU $FF ; NONE
H8PKEY0 .EQU $FE
H8PKEY1 .EQU $FC
H8PKEY2 .EQU $FA
H8PKEY3 .EQU $F8
H8PKEY4 .EQU $F6
H8PKEY5 .EQU $F4
H8PKEY6 .EQU $F2
H8PKEY7 .EQU $F0
H8PKEY8 .EQU $EF
H8PKEY9 .EQU $CF
H8PKEYPLUS .EQU $AF ; PLUS
H8PKEYMINUS .EQU $8F ; MINUS
H8PKEYMUL .EQU $6F ; MULTIPLY
H8PKEYDIV .EQU $4F ; DIVIDE
H8PKEYNUM .EQU $2F ; NUMBER
H8PKEYDOT .EQU $0F ; DOT
;
H8P_TICCNT .EQU $FFEA ; TICCNT AT $FFEA IS COPIED DOWN TO $000B FOR HEATH COMPATIBILITY
H8P_SPEED .EQU $FFEC ; SPEED CONTROL VALUE IS STORED HERE
H8P_SPDIO .EQU $30
H8FPIO .EQU $F0
;
DEVECHO "H8P: IO="
DEVECHO H8FPIO
DEVECHO "\n" DEVECHO "\n"
; ;
;__H8P_PREINIT_______________________________________________________________________________________ ;__H8P_PREINIT_______________________________________________________________________________________
@ -24,144 +47,856 @@
; HARDWARE RESET PRIOR TO ROMWBW CONSOLE INITIALIZATION ; HARDWARE RESET PRIOR TO ROMWBW CONSOLE INITIALIZATION
; ;
H8P_PREINIT: H8P_PREINIT:
LD A,(DSKY_DISPACT) ; DSKY DISPATCHER ALREADY SET?
OR A ; SET FLAGS
RET NZ ; IF ALREADY ACTIVE, ABORT
;
; REGISTER DRIVER WITH HBIOS
LD BC,H8P_DISPATCH
CALL DSKY_SETDISP
LD HL,H8P_INTR
CALL HB_ADDIM1
; ;
RET RET
; ;
;__H8P_INIT__________________________________________________________________________________________ ;__H8P_INIT__________________________________________________________________________________________
; ;
; DISPLAY DSKY INFO ON ROMWBW CONSOLE
; DISPLAY H8 FRONT PANEL INFO ON ROMWBW CONSOLE
;____________________________________________________________________________________________________ ;____________________________________________________________________________________________________
; ;
H8P_INIT: H8P_INIT:
CALL NEWLINE ; FORMATTING CALL NEWLINE ; FORMATTING
PRTS("H8P:$") ; DRIVER TAG
PRTS("H8FP:$") ; FORMATTING
; ;
RET ; DONE
PRTS(" IO=0x$") ; FORMATTING
LD A,H8FPIO ; GET BASE PORT
CALL PRTHEXBYTE ; PRINT BASE PORT
; ;
; DSKY DEVICE FUNCTION DISPATCH ENTRY
; A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR
; B: FUNCTION (IN)
RET ; DONE
; ;
H8P_DISPATCH:
LD A,B ; GET REQUESTED FUNCTION
AND $0F ; ISOLATE SUB-FUNCTION
JP Z,H8P_RESET ; RESET DSKY HARDWARE
DEC A
JP Z,H8P_STAT ; GET KEYPAD STATUS
DEC A
JP Z,H8P_GETKEY ; READ A KEY FROM THE KEYPAD
DEC A
JP Z,H8P_SHOWHEX ; DISPLAY A 32-BIT BINARY VALUE IN HEX
DEC A
JP Z,H8P_SHOWSEG ; DISPLAY SEGMENTS
DEC A
JP Z,H8P_KEYLEDS ; SET KEYPAD LEDS
DEC A
JP Z,H8P_STATLED ; SET STATUS LED
DEC A
JP Z,H8P_BEEP ; BEEP DSKY SPEAKER
DEC A
JP Z,H8P_DEVICE ; DEVICE INFO
SYSCHKERR(ERR_NOFUNC)
; H8 FRONT PANEL INTERRUPT
;
H8P_INTR:
LD (H8P_BCVAL),BC
LD (H8P_DEVAL),DE
LD (H8P_HLVAL),HL
LD HL,(H8P_TICCNT) ; 2MS TIC COUNTER
INC HL
LD (H8P_TICCNT),HL
CALL H8P_TIMER ; UP TIMER
CALL H8P_STAT ; CHECK KEYPAD PRESS
CALL H8P_GETSEGIDX ; SEGMENT INDEX IN (C)
CALL H8P_HORN
OR C
OUT (H8FPIO),A ; CLEAR INTERRUPT AND SET LED IDX
LD C,A
LD A,(H8P_FPENA)
OR A
LD A,$FF
CALL NZ,H8P_GETSEGPAT
OUT (H8FPIO+1),A ; SET LED PATTERN
;
CALL H8P_KEYPAD
LD A,(H8P_STTIMER)
INC A
AND $1F ; UPDATE LEDS EVERY 32 TICKS
LD (H8P_STTIMER),A
CALL Z,H8P_HDLSTATE
LD A,(H8P_HBTICK) ; ROMWBW TIMER
INC A
LD (H8P_HBTICK),A
CP 10
RET NZ
CALL HB_TICK
XOR A
LD (H8P_HBTICK),A
INC A ; INTERRUPT HANDLED
RET RET
; ;
; RESET DSKY -- CLEAR DISPLAY AND KEYPAD FIFO
; HANDLE FRONT PANEL SPEAKER SOUNDS
;
H8P_HORN:
LD HL,(H8P_HORNDUR)
LD A,H
OR L
LD A,$D0 ; HORN OFF
RET Z
DEC HL
LD (H8P_HORNDUR),HL
LD A,$50 ; HORN ON
RET
; ;
H8P_RESET:
XOR A ; SIGNAL SUCCESS
; HANDLE UP-TIME TIMER
;
H8P_TIMER:
LD HL,(H8P_ONESEC)
DEC HL
LD (H8P_ONESEC),HL
LD A,H
OR L
RET NZ
LD HL,(H8P_UPTIME)
INC HL
LD (H8P_UPTIME),HL
LD HL,500
LD (H8P_ONESEC),HL
CALL H8P_TIMER1
LD A,(H8P_STATE)
OR A
CALL Z,H8P_TIMER2
RET
; ADVANCE DIGITS
H8P_TIMER1:
LD C,9
LD HL,H8P_UPTDIG+8
CALL H8P_ADVDIG
RET
; SHOW DIGITS
H8P_TIMER2:
LD DE,H8P_UPTDIG+8
LD HL,H8P_SEGBUF+8
LD C,9
H8P_TIMER3:
PUSH BC
PUSH HL
LD A,C
CP 7
JR Z,H8P_TIMER4
CP 4
JR Z,H8P_TIMER4
JR H8P_TIMER5
H8P_TIMER4:
LD A,$80
JR H8P_TIMER6
H8P_TIMER5:
LD HL,H8P_DIGMAP
LD A,(DE)
LD C,A
LD B,0
ADD HL,BC
LD A,(HL)
H8P_TIMER6:
POP HL
LD (HL),A
DEC HL
DEC DE
POP BC
DEC C
JR NZ,H8P_TIMER3
RET
H8P_ADVDIG:
LD A,(HL) ; 000.000.00X
INC A
LD (HL),A
CP 10 ; 0-9
RET NZ
LD (HL),0
DEC HL
LD A,(HL) ; 000.000.0X0
INC A
LD (HL),A
CP 6 ; 0-5
RET NZ
LD (HL),0
DEC HL
DEC HL
LD A,(HL) ; 000.00X.000
INC A
LD (HL),A
CP 10 ; 0-9
RET NZ
LD (HL),0
DEC HL
LD A,(HL) ; 000.0X0.000
INC A
LD (HL),A
CP 6 ; 0-5
RET NZ
LD (HL),0
DEC HL
DEC HL
LD A,(HL) ; 00X.000.000
INC A
LD (HL),A
CP 10 ; 0-9
RET NZ
LD (HL),0
DEC HL
LD A,(HL) ; 0X0.000.000
INC A
LD (HL),A
CP 10 ; 0-9
RET NZ
LD (HL),0
DEC HL
LD A,(HL) ; X00.000.000
INC A
LD (HL),A
CP 10 ; 0-9
RET NZ
LD (HL),0
RET RET
; ;
; CHECK FOR KEY PRESS, SAVE RAW VALUE, RETURN STATUS
; CHECK FOR KEY PRESS, SAVE RAW VALUE
; ;
H8P_STAT: H8P_STAT:
XOR A ; ZERO KEYS PENDING (FOR NOW)
IN A,(H8FPIO)
LD (H8P_KEYBUF),A
RET RET
; ;
; WAIT FOR A DSKY KEYPRESS AND RETURN
; GET KEY AND RESET KEYBUF
; ;
H8P_GETKEY: H8P_GETKEY:
; PUT KEY VALUE IN REGISTER E
XOR A ; SIGNAL SUCCESS
LD A,(H8P_KEYBUF)
RET RET
; ;
; DISPLAY HEX VALUE FROM DE:HL
;
H8P_SHOWHEX:
LD BC,DSKY_HEXBUF ; POINT TO HEX BUFFER
CALL ST32 ; STORE 32-BIT BINARY THERE
LD HL,DSKY_HEXBUF ; FROM: BINARY VALUE (HL)
LD DE,DSKY_BUF ; TO: SEGMENT BUFFER (DE)
CALL DSKY_BIN2SEG ; CONVERT
LD HL,DSKY_BUF ; POINT TO SEGMENT BUFFER
; AND FALL THRU TO DISPLAY IT
;
; DISPLAY BYTE VALUES POINTED TO BY DE. THE INCOMING BYTES ARE IN
; THE STANDARD ROMWBW SEGMENT ENCODING AND MUST BE TRANSLATED TO THE
; HEATH ENCODING (SEE ICM.ASM FOR EXAMPLE):
;
H8P_KEYPAD:
CALL H8P_GETKEY
LD C,A
LD A,(H8P_LSTKEY)
CP C
RET Z
LD A,C
LD (H8P_LSTKEY),A
CP H8PKEYNONE
RET Z
LD HL,$04
LD (H8P_HORNDUR),HL
CP H8PKEYDIV ; / KEY (ALTER)
JP Z,H8P_KEYPADALT
CP H8PKEYMUL ; * KEY (CANCEL)
JP Z,H8P_KEYPADCAN
CP H8PKEYNUM ; MEM KEY
JP Z,H8P_KEYPADMEM
CP H8PKEYDOT ; REG KEY
JP Z,H8P_KEYPADREG
CP H8PKEY9
JP Z,H8P_KEYPAD9
CP H8PKEY8
JP Z,H8P_KEYPAD8
CP H8PKEY7
JP Z,H8P_KEYPAD7
CP H8PKEY6
JP Z,H8P_KEYPAD6
CP H8PKEY5
JP Z,H8P_KEYPAD5
CP H8PKEY4
JP Z,H8P_KEYPAD4
CP H8PKEY3
JP Z,H8P_KEYPAD3
CP H8PKEY2
JP Z,H8P_KEYPAD2
CP H8PKEY1
JP Z,H8P_KEYPAD1
CP H8PKEY0
JP Z,H8P_KEYPAD0
CP H8PKEYPLUS
JP Z,H8P_KEYPADPLUS
CP H8PKEYMINUS
JP Z,H8P_KEYPADMINUS
RET
; RESET TIMER
H8P_KEYPADALT:
LD A,(H8P_FPENA)
OR A
RET Z
LD A,(H8P_STATE)
OR A
RET NZ
XOR A
LD C,9
LD HL,H8P_UPTDIG
H8P_KEYPADALTL:
LD (HL),A
INC HL
DEC C
JR NZ,H8P_KEYPADALTL
RET
; ENABLE FRONT PANEL DISPLAY
H8P_KEYPADCAN:
LD A,(H8P_FPENA)
CPL
LD (H8P_FPENA),A
RET
; SET MEM STATE
H8P_KEYPADMEM:
LD A,2
LD (H8P_STATE),A
LD (H8P_MEMENTER),A
XOR A
LD (H8P_MEMADRIDX),A
CALL H8P_UPDMEMLOC
RET
; SET REG STATE
H8P_KEYPADREG:
LD A,1
LD (H8P_STATE),A
XOR A
LD (H8P_MEMENTER),A
RET
; NOTHING
H8P_KEYPAD9:
; RET
; TIMER
H8P_KEYPAD8:
LD A,(H8P_STATE)
CP 2
RET Z
LD A,0
LD (H8P_STATE),A
RET
; SPEED CONTROL
H8P_KEYPAD7:
LD A,(H8P_STATE)
CP 2 ; MEM MODE
LD A,7
JP Z,H8P_KEYPADDIG
LD A,3
LD (H8P_STATE),A
RET
; PC (OUT)
H8P_KEYPAD6:
LD A,(H8P_STATE)
CP 2 ; MEM MODE
LD A,6
JP Z,H8P_KEYPADDIG
LD A,5
LD (H8P_REGNUM),A
RET
; HL (IN)
H8P_KEYPAD5:
LD A,(H8P_STATE)
CP 2 ; MEM MODE
LD A,5
JP Z,H8P_KEYPADDIG
LD A,3
LD (H8P_REGNUM),A
RET
; DE
H8P_KEYPAD4:
LD A,(H8P_STATE)
CP 2 ; MEM MODE
LD A,4
JP Z,H8P_KEYPADDIG
LD A,2
LD (H8P_REGNUM),A
RET
; BC
H8P_KEYPAD3:
LD A,(H8P_STATE)
CP 2 ; MEM MODE
LD A,3
JP Z,H8P_KEYPADDIG
LD A,1
LD (H8P_REGNUM),A
RET
; AF
H8P_KEYPAD2:
LD A,(H8P_STATE)
CP 2 ; MEM MODE
LD A,2
JP Z,H8P_KEYPADDIG
LD A,0
LD (H8P_REGNUM),A
RET
; SP
H8P_KEYPAD1:
LD A,(H8P_STATE)
CP 2 ; MEM MODE
LD A,1
JP Z,H8P_KEYPADDIG
LD A,4
LD (H8P_REGNUM),A
RET
; NOTHING
H8P_KEYPAD0:
LD A,(H8P_STATE)
CP 2 ; MEM MODE
JP NZ,H8P_KEYPAD8
LD A,0
;
H8P_KEYPADDIG:
LD C,A
LD A,(H8P_MEMENTER)
OR A
JR Z,H8P_KEYPADDIG1
LD A,(H8P_MEMADRIDX)
OR A
CALL Z,H8P_SETDIG0
DEC A
CALL Z,H8P_SETDIG1
DEC A
CALL Z,H8P_SETDIG2
DEC A
CALL Z,H8P_SETDIG3
DEC A
CALL Z,H8P_SETDIG4
DEC A
CALL Z,H8P_SETDIG5
CALL H8P_UPDMEMLOC
; NEXT MEMORY ADR INDEX
LD A,(H8P_MEMADRIDX)
INC A
LD (H8P_MEMADRIDX),A
CP 6
RET NZ
XOR A
LD (H8P_MEMADRIDX),A
RET
; CHECK FOR IN/OUT TO PORT
H8P_KEYPADDIG1:
LD A,C
CP 5 ; IN PORT
JR Z,H8P_KEYPADINP
CP 6 ; OUT PORT
JR Z,H8P_KEYPADOUT
RET
H8P_KEYPADINP:
LD BC,(H8P_MEMLOC)
IN A,(C)
LD B,A
LD (H8P_MEMLOC),BC
JP H8P_UPDMEMLOC
H8P_KEYPADOUT:
LD BC,(H8P_MEMLOC)
LD A,B
OUT (C),A
RET
H8P_UPDMEMLOC:
LD BC,H8P_MEMLOC
LD HL,H8P_SEGBUF
CALL H8P_FILLOCT
RET
; C=VAL
H8P_SETDIG0:
LD HL,(H8P_MEMLOC)
LD B,H
CALL H8P_SETOCTH
LD H,A
LD (H8P_MEMLOC),HL
LD A,$FF
RET
H8P_SETDIG1:
LD HL,(H8P_MEMLOC)
LD B,H
CALL H8P_SETOCTM
LD H,A
LD (H8P_MEMLOC),HL
LD A,$FF
RET
H8P_SETDIG2:
LD HL,(H8P_MEMLOC)
LD B,H
CALL H8P_SETOCTL
LD H,A
LD (H8P_MEMLOC),HL
LD A,$FF
RET
H8P_SETDIG3:
LD HL,(H8P_MEMLOC)
LD B,L
CALL H8P_SETOCTH
LD L,A
LD (H8P_MEMLOC),HL
LD A,$FF
RET
H8P_SETDIG4:
LD HL,(H8P_MEMLOC)
LD B,L
CALL H8P_SETOCTM
LD L,A
LD (H8P_MEMLOC),HL
LD A,$FF
RET
H8P_SETDIG5:
LD HL,(H8P_MEMLOC)
LD B,L
CALL H8P_SETOCTL
LD L,A
LD (H8P_MEMLOC),HL
XOR A
LD (H8P_MEMENTER),A
LD A,$FF
RET
H8P_SETDIGD:
LD A,(H8P_MEMVAL)
PUSH AF
CALL H8P_GETOCTH
LD (H8P_SEGBUF+6),A
POP AF
PUSH AF
CALL H8P_GETOCTM
LD (H8P_SEGBUF+7),A
POP AF
CALL H8P_GETOCTL
LD (H8P_SEGBUF+8),A
RET
; MEM/SPEED INCREASE
H8P_KEYPADPLUS:
LD A,(H8P_STATE)
CP 3
JR Z,H8P_KEYPADPLUS3
CP 2
RET NZ
LD HL,(H8P_MEMLOC)
INC HL
LD (H8P_MEMLOC),HL
JP H8P_UPDMEMLOC
H8P_KEYPADPLUS3:
LD A,(H8P_SPEED)
OR A
RET Z
DEC A
LD (H8P_SPEED),A
OUT (H8P_SPDIO),A
RET
; MEM/SPEED DECREASE
H8P_KEYPADMINUS:
LD A,(H8P_STATE)
CP 3
JR Z,H8P_KEYPADMINUS3
CP 2
RET NZ
LD HL,(H8P_MEMLOC)
DEC HL
LD (H8P_MEMLOC),HL
JP H8P_UPDMEMLOC
H8P_KEYPADMINUS3:
LD A,(H8P_SPEED)
CP 3
RET Z
INC A
LD (H8P_SPEED),A
OUT (H8P_SPDIO),A
RET
; ;
; From: To:
; +--01--+ +--02--+
; 20 02 40 04
; +--40--+ +--01--+
; 10 04 20 08
; +--08--+ 80 +--10--+ 80
; HANDLE FRONT PANEL STATE
; ;
H8P_SHOWSEG:
XOR A ; SIGNAL SUCCESS
H8P_HDLSTATE:
LD A,(H8P_STATE)
OR A
RET Z ; UP-TIME TIMER
DEC A
JP Z,H8P_HDLREG ; SHOWING REGISTER VALUES
DEC A
JP Z,H8P_HDLMEM ; SHOWING MEMORY LOCATION VALUE
DEC A
JP Z,H8P_HDLSPD ; MODIFYING SPEED
RET RET
; ;
; UPDATE KEY LEDS (H8 HAS NONE)
H8P_HDLREG:
LD A,(H8P_REGNUM)
LD HL,H8P_REGAF
OR A
JP Z,H8P_HDLREGAF
DEC A
LD HL,H8P_REGBC
JP Z,H8P_HDLREGBC
DEC A
LD HL,H8P_REGDE
JP Z,H8P_HDLREGDE
DEC A
LD HL,H8P_REGHL
JP Z,H8P_HDLREGHL
DEC A
LD HL,H8P_REGSP
JP Z,H8P_HDLREGSP
DEC A
LD HL,H8P_REGPC
JP Z,H8P_HDLREGPC
RET
H8P_HDLREGAF:
CALL H8P_UPDLEDS
LD HL,HBX_INTSTK
DEC HL
LD A,(HL) ; (HL)=AF LOW
LD (H8P_AFVAL),A
DEC HL
LD A,(HL) ; (HL)=AF HIGH
LD (H8P_AFVAL+1),A
LD BC,H8P_AFVAL
LD HL,H8P_SEGBUF
JP H8P_FILLOCT
H8P_HDLREGBC:
LD BC,H8P_BCVAL
CALL H8P_FILLOCT
JP H8P_UPDLEDS
H8P_HDLREGDE:
LD BC,H8P_DEVAL
CALL H8P_FILLOCT
JP H8P_UPDLEDS
H8P_HDLREGHL:
CALL H8P_UPDLEDS
LD HL,(HBX_INT_SP)
LD A,(HL)
LD (H8P_HLVAL),A
INC HL
LD A,(HL)
LD (H8P_HLVAL+1),A
LD BC,H8P_HLVAL
LD HL,H8P_SEGBUF
JP H8P_FILLOCT
H8P_HDLREGSP:
LD BC,HBX_INT_SP
CALL H8P_FILLOCT
JP H8P_UPDLEDS
H8P_HDLREGPC:
CALL H8P_UPDLEDS
LD HL,(HBX_INT_SP) ; (HL)=HL LOW
INC HL ; (HL)=HL HIGH
INC HL ; (HL)=PC LOW
LD A,(HL)
LD (H8P_PCVAL),A
INC HL ; (HL)=PC HIGH
LD A,(HL)
LD (H8P_PCVAL+1),A
LD BC,H8P_PCVAL
LD HL,H8P_SEGBUF
JP H8P_FILLOCT
H8P_HDLMEM:
CALL H8P_SETDIGD
RET
H8P_HDLSPD:
LD HL,H8P_SPD16
LD A,(H8P_SPEED)
OR A
JR Z,H8P_UPDLEDS
LD HL,H8P_SPD08
DEC A
JR Z,H8P_UPDLEDS
LD HL,H8P_SPD04
DEC A
JR Z,H8P_UPDLEDS
LD HL,H8P_SPD02
H8P_UPDLEDS:
LD C,9
LD DE,H8P_SEGBUF
H8P_UPDLEDS1:
LD A,(HL)
INC HL
LD (DE),A
INC DE
DEC C
JR NZ,H8P_UPDLEDS1
RET
; ;
H8P_KEYLEDS:
XOR A ; SIGNAL SUCCESS
H8P_GETSEGIDX:
LD A,(H8P_SEGIDX)
DEC A
LD (H8P_SEGIDX),A
LD C,A
RET NZ
LD A,9
LD (H8P_SEGIDX),A
LD C,A
RET RET
; ;
; SET STATUS LEDS BASED ON BITS IN E
; A = SEG IDX
; ;
H8P_STATLED:
XOR A ; SIGNAL SUCCESS
RET
; +--02--+
; 40 04
; +--01--+
; 20 08
; +--10--+ 80
; ;
; BEEP THE SPEAKER ON THE H8P
H8P_GETSEGPAT:
LD A,C
AND $0F ; IDX=1 THRU 9
DEC A
LD C,A
LD B,0
LD HL,H8P_SEGBUF
ADD HL,BC
LD E,(HL)
LD A,(H8P_MEMENTER)
OR A
JR Z,H8P_GETSEGPATX
LD A,(H8P_MEMADRIDX)
CP C
JR NZ,H8P_GETSEGPATX
LD A,$80
OR E
LD E,A
H8P_GETSEGPATX:
LD A,E
CPL
RET
; BC=MEMLOC, HL=LED BUFFER
H8P_FILLOCT:
PUSH HL
INC BC ; POINT TO HIGH BYTE
LD A,(BC)
CALL H8P_GETOCTH
LD (HL),A
INC HL
LD A,(BC)
CALL H8P_GETOCTM
LD (HL),A
INC HL
LD A,(BC)
CALL H8P_GETOCTL
LD (HL),A
INC HL
DEC BC ; POINT TO LOW BYTE
LD A,(BC)
CALL H8P_GETOCTH
LD (HL),A
INC HL
LD A,(BC)
CALL H8P_GETOCTM
LD (HL),A
INC HL
LD A,(BC)
CALL H8P_GETOCTL
LD (HL),A
POP HL
RET
; HIGH OCTAL BITS
H8P_GETOCTH:
AND $C0
RRA
RRA
RRA
RRA
RRA
RRA
JR H8P_GETOCTX
; MEDIUM OCTAL BITS
H8P_GETOCTM:
AND $38
RRA
RRA
RRA
JR H8P_GETOCTX
; LOW OCTAL BITS
H8P_GETOCTL:
AND $07
H8P_GETOCTX:
PUSH HL
LD E,A
LD D,0
LD HL,H8P_DIGMAP
ADD HL,DE
LD A,(HL) ; VALUE CONVERTED TO LED SEGMENT PATTERN
POP HL
RET
; B=CURVAL, C=NEWVAL
H8P_SETOCTH:
LD A,C
AND $03
RLA
RLA
RLA
RLA
RLA
RLA
LD C,A
LD A,B
AND $3F
OR C
RET
H8P_SETOCTM:
LD A,C
AND $07
RLA
RLA
RLA
LD C,A
LD A,B
AND $C7
OR C
RET
H8P_SETOCTL:
LD A,C
AND $07
LD C,A
LD A,B
AND $F8
OR C
CALL H8P_BEEP
RET
; ;
H8P_BEEP: H8P_BEEP:
POP BC
XOR A ; SIGNAL SUCCESS
PUSH HL
LD HL,16
LD (H8P_HORNDUR),HL
POP HL
RET RET
; ;
; DEVICE INFORMATION ; DEVICE INFORMATION
; ;
H8P_DEVICE: H8P_DEVICE:
LD D,DSKYDEV_H8P ; D := DEVICE TYPE
; LD D,DSKYDEV_H8P ; D := DEVICE TYPE
LD E,0 ; E := PHYSICAL DEVICE NUMBER LD E,0 ; E := PHYSICAL DEVICE NUMBER
LD H,0 ; H := MODE LD H,0 ; H := MODE
LD L,0 ; L := BASE I/O ADDRESS
LD L,H8FPIO ; L := BASE I/O ADDRESS
XOR A ; SIGNAL SUCCESS XOR A ; SIGNAL SUCCESS
RET RET
; ;
;_KEYMAP_TABLE_____________________________________________________________________________________________________________
;
H8P_KEYMAP: ; *** NEEDS TO BE UPDATED ***
; POS $00 $01 $02 $03 $04 $05 $06 $07
; KEY [0] [1] [2] [3] [4] [5] [6] [7]
.DB $0D, $04, $0C, $14, $03, $0B, $13, $02
;
; POS $08 $09 $0A $0B $0C $0D $0E $0F
; KEY [8] [9] [A] [B] [C] [D] [E] [F]
.DB $0A, $12, $01, $09, $11, $00, $08, $10
; DIGITS TO LED PATTERNS
; +--02--+
; 40 04
; +--01--+
; 20 08
; +--10--+ 80
; ;
; POS $10 $11 $12 $13 $14 $15 $16 $17
; KEY [FW] [BK] [CL] [EN] [DE] [EX] [GO] [BO]
.DB $05, $15, $1D, $1C, $1B, $1A, $19, $18
; POS $18 $19 $1A $1B
; KEY [F4] [F3] [F2] [F1]
.DB $23, $22, $21, $20
H8P_DIGMAP:
; 0 1 2 3 4 5 6 7
.DB $7E, $0C, $37, $1F, $4D, $5B, $7B, $0E
; 8 9 A B C D E F
.DB $7F, $5F, $6F, $79, $72, $3D, $73, $63
;
H8P_REGNUM:
.DB 0
H8P_REGAF:
.DB $00, $00, $00, $00, $00, $00, $00, $6F, $63
H8P_REGBC:
.DB $00, $00, $00, $00, $00, $00, $00, $79, $72
H8P_REGDE:
.DB $00, $00, $00, $00, $00, $00, $00, $3D, $73
H8P_REGHL:
.DB $00, $00, $00, $00, $00, $00, $00, $6D, $70
H8P_REGSP:
.DB $00, $00, $00, $00, $00, $00, $00, $5B, $67
H8P_REGPC:
.DB $00, $00, $00, $00, $00, $00, $00, $67, $72
H8P_SPD16:
.DB $00, $00, $00, $00, $0C, $7B, $5B, $67, $3D
H8P_SPD08:
.DB $00, $00, $00, $00, $00, $7F, $5B, $67, $3D
H8P_SPD04:
.DB $00, $00, $00, $00, $00, $4D, $5B, $67, $3D
H8P_SPD02:
.DB $00, $00, $00, $00, $00, $37, $5B, $67, $3D
H8P_MEMADRIDX:
.DB 0
H8P_MEMENTER:
.DB 0
H8P_AFVAL:
.DW 0
H8P_BCVAL:
.DW 0
H8P_DEVAL:
.DW 0
H8P_HLVAL:
.DW 0
H8P_PCVAL:
.DW 0
;
H8P_STATE:
.DB 00
H8P_STTIMER:
.DB 00
H8P_FPENA:
.DB $FF
H8P_SEGIDX:
.DB 09
H8P_HBTICK:
.DB 00
H8P_KEYBUF:
.DB 00
H8P_LSTKEY:
.DB 00
H8P_SEGBUF:
.DB $FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF
H8P_HORNDUR:
.DW $0080
H8P_ONESEC:
.DW 500
H8P_UPTIME:
.DW 0
H8P_UPTDIG:
.DB 0,0,0,0,0,0,0,0,0

32
Source/HBIOS/hbios.asm
View File

@ -1045,6 +1045,22 @@ HBX_PPSP .EQU $ - 2
; ;
#IF (MEMMGR != MM_Z280) #IF (MEMMGR != MM_Z280)
; ;
; HEATH FRONT PANEL WORK SPACE (4 BYTES)
;
#IF (H8PENABLE)
H8P_MEMLOC:
.DW 0
H8P_MEMVAL:
.DB 0
H8P_MEMCPY:
LD HL,(H8P_TICCNT)
LD ($000B),HL
LD HL,(H8P_MEMLOC)
LD A,(HL)
LD (H8P_MEMVAL),A
RET
#ENDIF
;
HBX_INTSTKSIZ .EQU $FF00 - $ HBX_INTSTKSIZ .EQU $FF00 - $
MEMECHO "HBIOS INT STACK space: " MEMECHO "HBIOS INT STACK space: "
MEMECHO HBX_INTSTKSIZ MEMECHO HBX_INTSTKSIZ
@ -1188,6 +1204,10 @@ HBX_RETI:
; ;
LD A,(HB_CURBNK) ; GET PRE-INT BANK LD A,(HB_CURBNK) ; GET PRE-INT BANK
CALL HBX_BNKSEL ; SELECT IT CALL HBX_BNKSEL ; SELECT IT
;
#IF (H8PENABLE)
CALL H8P_MEMCPY
#ENDIF
; ;
; RESTORE STATE ; RESTORE STATE
POP IY ; RESTORE IY POP IY ; RESTORE IY
@ -2262,9 +2282,6 @@ HB_CPU1:
#IF (PKDENABLE) #IF (PKDENABLE)
CALL PKD_PREINIT CALL PKD_PREINIT
#ENDIF #ENDIF
#IF (H8PENABLE)
CALL H8P_PREINIT
#ENDIF
; ;
; ANNOUNCE OURSELVES ON DSKY ; ANNOUNCE OURSELVES ON DSKY
LD HL,MSG_HBVER + 5 LD HL,MSG_HBVER + 5
@ -2282,6 +2299,9 @@ HB_CPU1:
LD B,BF_DSKYSHOWSEG LD B,BF_DSKYSHOWSEG
CALL DSKY_DISPATCH CALL DSKY_DISPATCH
#ENDIF #ENDIF
#IF (H8PENABLE)
CALL H8P_PREINIT
#ENDIF
; ;
FPLEDS(DIAG_05) FPLEDS(DIAG_05)
; ;
@ -3679,9 +3699,9 @@ HB_INITTBL:
#IF (PKDENABLE) #IF (PKDENABLE)
.DW PKD_INIT .DW PKD_INIT
#ENDIF #ENDIF
#IF (H8PENABLE)
#ENDIF
#IF (H8PENABLE)
.DW H8P_INIT .DW H8P_INIT
#ENDIF
#ENDIF #ENDIF
#IF (PLATFORM == PLT_NABU) #IF (PLATFORM == PLT_NABU)
.DW NABU_INIT .DW NABU_INIT
@ -7935,6 +7955,7 @@ SIZ_PKD .EQU $ - ORG_PKD
MEMECHO SIZ_PKD MEMECHO SIZ_PKD
MEMECHO " bytes.\n" MEMECHO " bytes.\n"
#ENDIF #ENDIF
#ENDIF
; ;
#IF (H8PENABLE) #IF (H8PENABLE)
ORG_H8P .EQU $ ORG_H8P .EQU $
@ -7944,7 +7965,6 @@ SIZ_H8P .EQU $ - ORG_H8P
MEMECHO SIZ_H8P MEMECHO SIZ_H8P
MEMECHO " bytes.\n" MEMECHO " bytes.\n"
#ENDIF #ENDIF
#ENDIF
; ;
#IF (PLATFORM == PLT_NABU) #IF (PLATFORM == PLT_NABU)
ORG_NABU .EQU $ ORG_NABU .EQU $

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