Browse Source

CPU Speed Change API

- Moved the CPU speed changing mechanism into the HBIOS as an API call.
- Added support for CPU speed changing on Z180 platforms.
patch
Wayne Warthen 4 years ago
parent
commit
21a38aed6e
  1. BIN
      Doc/ROM Applications.pdf
  2. BIN
      Doc/RomWBW Applications.pdf
  3. BIN
      Doc/RomWBW Architecture.pdf
  4. BIN
      Doc/RomWBW Disk Catalog.pdf
  5. BIN
      Doc/RomWBW Getting Started.pdf
  6. 42
      ReadMe.md
  7. 32
      ReadMe.txt
  8. 152
      Source/Apps/Test/cpuspd/cpuspd.asm
  9. 37
      Source/Doc/Architecture.md
  10. 16
      Source/HBIOS/API.txt
  11. 2
      Source/HBIOS/cfg_dyno.asm
  12. 2
      Source/HBIOS/cfg_ezz80.asm
  13. 2
      Source/HBIOS/cfg_master.asm
  14. 2
      Source/HBIOS/cfg_mbc.asm
  15. 2
      Source/HBIOS/cfg_mk4.asm
  16. 2
      Source/HBIOS/cfg_n8.asm
  17. 2
      Source/HBIOS/cfg_rcz180.asm
  18. 2
      Source/HBIOS/cfg_rcz280.asm
  19. 2
      Source/HBIOS/cfg_rcz80.asm
  20. 2
      Source/HBIOS/cfg_sbc.asm
  21. 2
      Source/HBIOS/cfg_scz180.asm
  22. 4
      Source/HBIOS/cfg_una.asm
  23. 2
      Source/HBIOS/cfg_zeta.asm
  24. 2
      Source/HBIOS/cfg_zeta2.asm
  25. 120
      Source/HBIOS/hbios.asm
  26. 18
      Source/HBIOS/hbios.inc
  27. 30
      Source/HBIOS/std.asm
  28. 2
      Source/ver.inc
  29. 2
      Source/ver.lib

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Doc/ROM Applications.pdf

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Doc/RomWBW Applications.pdf

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Doc/RomWBW Architecture.pdf

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Doc/RomWBW Disk Catalog.pdf

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Doc/RomWBW Getting Started.pdf

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42
ReadMe.md

@ -3,7 +3,7 @@ author: "Wayne Warthen (mailto:wwarthen@gmail.com)"
classoption:
- oneside
colorlinks: true
date: 03 Jan 2022
date: 26 Jan 2022
documentclass: book
fontfamily: helvet
fontsize: 12pt
@ -44,7 +44,7 @@ toc-depth: 1
## Z80/Z180 System Software
Version 3.1 Pre-release
03 Jan 2022
26 Jan 2022
Wayne Warthen <wwarthen@gmail.com>
@ -1100,7 +1100,7 @@ through the normal startup process just like it was started from ROM.
However, your ROM has not been updated and the next time you boot your
system, it will revert to the system image contained in ROM.
# Upgrading via Flash Utility
## Upgrading via Flash Utility
If you do not have easy access to a ROM programmer, it is usually
possible to reprogram your system ROM using the FLASH utility from Will
@ -1142,7 +1142,7 @@ To confirm your ROM chip has been successfully updated, restart your
system and boot an operating system from ROM. Do not boot from a disk
device yet. Review the boot messages to see if any issues have occurred.
# Upgrading via XModem Flash Updater
## Upgrading via XModem Flash Updater
Similar to using the Flash utility, the system ROM can be updated or
upgraded through the ROM based updater utility. This works by by
@ -1157,7 +1157,7 @@ file.
More information can be found in the ROM Applications document.
# Post Update System Image and Application update process
## Post Upgrade System Image and Application Update Process
Once you are satisfied that the ROM is working well, you will need to
update the system images and RomWBW custom applications on your disk
@ -1226,21 +1226,20 @@ system on your disk.
After this is done, you will need to use `SYSCOPY` to place the ZPM3
loader image on the boot tracks of all ZPM3 boot disks/slices. The
loader image is called `CPMLDR.SYS`. You must then copy (at a
loader image is called `ZPMLDR.SYS`. You must then copy (at a
minimum) `CPM3.SYS`, `ZCCP.COM`, `ZINSTAL.ZPM`, and `STARTZPM.COM`
onto the disk/slice. Assuming you copied the ZPM3 boot files onto
your RAM disk at A:, you would use:
A>B:SYSCOPY C:=CPMLDR.SYS
A>B:SYSCOPY C:=ZPMLDR.SYS
A>B:COPY CPM3.SYS C:
A>B:COPY ZCCP.COM C:
A>B:COPY ZINSTAL.ZPM C:
A>B:COPY STARTZPM.COM C:
You may be wondering if the references to `CPMLDR.SYS` and
`CPM3.SYS` are typos. They are not. ZPM3 uses the same loader image
as CPM3. The ZPM3 main system code file is called `CPM3.SYS` which
is the same name as CP/M 3 uses, but the file contents are not the
You may be wondering if the reference to `CPM3.SYS` is a typo. It is
not. The ZPM3 main system code file is called `CPM3.SYS` which is
the same name as CP/M 3 uses, but the file contents are not the
same.
Finally, if you have copies of any of the RomWBW custom applications on
@ -1272,7 +1271,7 @@ images.
- FAT.COM
- TUNE.COM
# System Update
## System Update
If the system running ROMWBW utilizes the SST39SF040 Flash chip then it
is possible to do a System Update in place of a System Upgrade in some
@ -1298,9 +1297,9 @@ extension “.rom” and be 512Kb or 1024Kb in size.
Transferring and flashing the System Update is accomplished in the same
manner as described above in *Upgrading* with the required difference
being that the flash application needs to be directed to complete a
partial flash using the /p command line switch.
partial flash using the /P command line switch.
`E>flash write rom.upd /p`
`E>FLASH WRITE ROM.UPD /P`
# RomWBW Distribution
@ -1318,8 +1317,8 @@ file describing the contents in detail. In summary, these directories
are:
| Application | Description |
|-------------|-----------------------------------------------------------------------------------------------------------------------------------------|
| Binary | The final output files of the build process are placed here. Most importantly, are the ROM images with the file names ending in “.rom”. |
|-------------|-------------------------------------------------------------------------------------------------------------------------------------|
| Binary | The final output files of the build process are placed here. Most importantly, the ROM images with the file names ending in “.rom”. |
| Doc | Contains various detailed documentation including the operating systems, RomWBW architecture, etc. |
| Source | Contains the source code files used to build the software and ROM images. |
| Tools | Contains the MS Windows programs that are used by the build process or that may be useful in setting up your system. |
@ -1343,10 +1342,11 @@ applications are no longer provided.
driver.
- Ed Brindley contributed some of the code that supports the RC2014
platform.
- Phil Summers contributed Forth and BASIC in ROM, the AY-3-8910 sound
driver as well as a long list of general code enhancements.
- Phil Summers contributed the Forth and BASIC adaptations in ROM, the
AY-3-8910 sound driver as well as a long list of general code
enhancements.
- Phillip Stevens contributed support for FreeRTOS.
- Curt Mayer contributed the Linux / MacOS build process.
- Curt Mayer contributed the original Linux / MacOS build process.
- UNA BIOS and FDISK80 are the products of John Coffman.
- FLASH4 is a product of Will Sowerbutts.
- CLRDIR is a product of Max Scane.
@ -1379,8 +1379,8 @@ accordance with the intentions and/or licensing of their creators.
If anyone feels their work is being used outside of it’s intended
licensing, please notify:
Wayne Warthen
wwarthen@gmail.com
> Wayne Warthen
> wwarthen@gmail.com
RomWBW is an aggregate work. It is composed of many individual,
standalone programs that are distributed as a whole to function as a

32
ReadMe.txt

@ -1,6 +1,6 @@
RomWBW Getting Started
Wayne Warthen (mailto:wwarthen@gmail.com)
03 Jan 2022
26 Jan 2022
@ -17,7 +17,7 @@ RomWBW
Z80/Z180 System Software
Version 3.1 Pre-release
03 Jan 2022
26 Jan 2022
Wayne Warthen wwarthen@gmail.com
@ -1154,7 +1154,7 @@ file.
More information can be found in the ROM Applications document.
Post Update System Image and Application update process
Post Upgrade System Image and Application Update Process
Once you are satisfied that the ROM is working well, you will need to
update the system images and RomWBW custom applications on your disk
@ -1222,21 +1222,20 @@ system on your disk.
After this is done, you will need to use SYSCOPY to place the ZPM3
loader image on the boot tracks of all ZPM3 boot disks/slices. The
loader image is called CPMLDR.SYS. You must then copy (at a minimum)
loader image is called ZPMLDR.SYS. You must then copy (at a minimum)
CPM3.SYS, ZCCP.COM, ZINSTAL.ZPM, and STARTZPM.COM onto the
disk/slice. Assuming you copied the ZPM3 boot files onto your RAM
disk at A:, you would use:
A>B:SYSCOPY C:=CPMLDR.SYS
A>B:SYSCOPY C:=ZPMLDR.SYS
A>B:COPY CPM3.SYS C:
A>B:COPY ZCCP.COM C:
A>B:COPY ZINSTAL.ZPM C:
A>B:COPY STARTZPM.COM C:
You may be wondering if the references to CPMLDR.SYS and CPM3.SYS
are typos. They are not. ZPM3 uses the same loader image as CPM3.
The ZPM3 main system code file is called CPM3.SYS which is the same
name as CP/M 3 uses, but the file contents are not the same.
You may be wondering if the reference to CPM3.SYS is a typo. It is
not. The ZPM3 main system code file is called CPM3.SYS which is the
same name as CP/M 3 uses, but the file contents are not the same.
Finally, if you have copies of any of the RomWBW custom applications on
your hard disk, you need to update them with the latest copies. The
@ -1292,9 +1291,9 @@ extension “.rom” and be 512Kb or 1024Kb in size.
Transferring and flashing the System Update is accomplished in the same
manner as described above in Upgrading with the required difference
being that the flash application needs to be directed to complete a
partial flash using the /p command line switch.
partial flash using the /P command line switch.
E>flash write rom.upd /p
E>FLASH WRITE ROM.UPD /P
RomWBW Distribution
@ -1314,8 +1313,8 @@ are:
Application Description
------------- ------------------------------------------------------------
Binary The final output files of the build process are placed here.
Most importantly, are the ROM images with the file names
ending in “.rom”.
Most importantly, the ROM images with the file names ending
in “.rom”.
Doc Contains various detailed documentation including the
operating systems, RomWBW architecture, etc.
@ -1346,10 +1345,11 @@ applications are no longer provided.
driver.
- Ed Brindley contributed some of the code that supports the RC2014
platform.
- Phil Summers contributed Forth and BASIC in ROM, the AY-3-8910 sound
driver as well as a long list of general code enhancements.
- Phil Summers contributed the Forth and BASIC adaptations in ROM, the
AY-3-8910 sound driver as well as a long list of general code
enhancements.
- Phillip Stevens contributed support for FreeRTOS.
- Curt Mayer contributed the Linux / MacOS build process.
- Curt Mayer contributed the original Linux / MacOS build process.
- UNA BIOS and FDISK80 are the products of John Coffman.
- FLASH4 is a product of Will Sowerbutts.
- CLRDIR is a product of Max Scane.

152
Source/Apps/Test/cpuspd/cpuspd.asm

@ -10,8 +10,6 @@
;
#include "../../../HBIOS/hbios.inc"
;
cpumhz .equ 8 ; for time delay calculations (not critical)
;
; General operational equates (should not requre adjustment)
;
stksiz .equ $40 ; Working stack size
@ -20,23 +18,6 @@ rtc_port .equ $70 ; RTC latch port adr
;
restart .equ $0000 ; CP/M restart vector
bdos .equ $0005 ; BDOS invocation vector
;
; primary hardware platforms
;
plt_sbc .equ 1 ; SBC ECB Z80 SBC
plt_zeta .equ 2 ; ZETA Z80 SBC
plt_zeta2 .equ 3 ; ZETA Z80 V2 SBC
plt_n8 .equ 4 ; N8 (HOME COMPUTER) Z180 SBC
plt_mk4 .equ 5 ; MARK IV
plt_una .equ 6 ; UNA BIOS
plt_rcz80 .equ 7 ; RC2014 W/ Z80
plt_rcz180 .equ 8 ; RC2014 W/ Z180
plt_ezz80 .equ 9 ; EASY Z80
plt_scz180 .equ 10 ; SCZ180
plt_dyno .equ 11 ; DYNO MICRO-ATX MOTHERBOARD
plt_rcz280 .equ 12 ; RC2014 W/ Z280
plt_mbc .equ 13 ; MULTI BOARD COMPUTER
;
;=======================================================================
;
@ -68,63 +49,84 @@ main:
;
; Get HBIOS platform ID
;
;
; Get platform id from RomWBW HBIOS
ld b,BF_SYSVER ; HBIOS VER function 0xF1
ld c,0 ; Required reserved value
rst 08 ; Do it, L := Platform ID
ld a,l ; Move to A
;
cp plt_sbc
jr set_spd
cp plt_mbc
jr set_spd
jp err_not_sup ; Platform not supported
;
set_spd:
; Use first char of FCB for speed selection
ld a,($5D)
cp ' '
jr z,show_spd
and $5F ; make upper case
cp 'F' ; fast
jr z,set_fast
cp 'H' ; high
jr z,set_fast
cp 'S' ; slow
jr z,set_slow
cp 'L' ; low
jr z,set_slow
cp 'D' ; double
jr z,set_dbl
cp 'F' ; full
jr z,set_full
cp 'H' ; half
jr z,set_half
jr usage
;
set_slow:
ld a,(HB_RTCVAL)
and ~%00001000
set_half:
ld l,0
jr new_spd
;
set_fast:
ld a,(HB_RTCVAL)
or %00001000
set_full:
ld l,1
jr new_spd
;
set_dbl:
ld l,2
jr new_spd
;
new_spd:
ld (HB_RTCVAL),a
out (rtc_port),a
ld b,BF_SYSSET
ld c,BF_SYSSET_CPUSPD
rst 08
jp nz,err_not_sup
call show_spd
xor a
ret
;
show_spd:
ld a,(HB_RTCVAL)
and %00001000
ld b,BF_SYSGET
ld c,BF_SYSGET_CPUSPD
rst 08
jp nz,err_not_sup
push de
ld a,l
ld de,str_slow
cp 0
jr z,show_spd1
ld de,str_full
cp 1
jr z,show_spd1
ld de,str_dbl
cp 2
jr z,show_spd1
ld de,str_fast
jr show_spd2
jp err_invalid
show_spd1:
ld de,str_slow
show_spd2:
call crlf2
call prtstr
pop hl
;
ld a,h ; memory wait states
cp $FF
jr z,show_spd2
call crlf
ld de,str_spacer
call prtstr
call prtdecb
ld de,str_memws
call prtstr
;
show_spd2:
ld a,l
cp $FF
jr z,show_spd3
call crlf
ld de,str_spacer
call prtstr
call prtdecb
ld de,str_iows
call prtstr
;
show_spd3:
ret
;
usage:
@ -139,6 +141,9 @@ usage:
err_not_sup:
ld de,str_err_not_sup
jr err_ret
err_invalid:
ld de,str_err_invalid
jr err_ret
;
err_ret:
call crlf2
@ -346,36 +351,21 @@ addhla:
inc h
ret
;
; Delay ~10ms
;
delay:
push af
push de
ld de,625 ; 10000us/16us
delay0:
ld a,(cpuscl)
delay1:
dec a
jr nz,delay1
dec de
ld a,d
or e
jp nz,delay0
pop de
pop af
ret
;
;
;
;=======================================================================
; Constants
;=======================================================================
;
str_banner .db "RomWBW CPU Speed Selector v0.1, 25-Jan-2022",0
str_slow .db " CPU speed is SLOW",0
str_fast .db " CPU speed is FAST",0
str_err_not_sup .db " ERROR: Platform not supported!",0
str_usage .db " Usage: CPUSPD [F|S]",0
str_banner .db "RomWBW CPU Speed Selector v0.2, 26-Jan-2022",0
str_spacer .db " ",0
str_slow .db " CPU speed is HALF",0
str_full .db " CPU speed is FULL",0
str_dbl .db " CPU speed is DOUBLE",0
str_memws .db " Memory Wait State(s)",0
str_iows .db " I/O Wait State(s)",0
str_err_not_sup .db " ERROR: Platform or configuration not supported!",0
str_err_invalid .db " ERROR: Invalid configuration!",0
str_usage .db " Usage: CPUSPD [Half|Full|Double]",0
;
;=======================================================================
; Working data
@ -385,8 +375,6 @@ stksav .dw 0 ; stack pointer saved at start
.fill stksiz,0 ; stack
stack .equ $ ; stack top
;
cpuscl .db cpumhz - 2
;
;=======================================================================
;
.end

37
Source/Doc/Architecture.md

@ -1959,6 +1959,23 @@ lookup.
| D: BIOS Bank ID
| E: User Bank ID
#### SYSGET Subfunction 0xF3 -- Get CPU Speed (CPUSPD)
| _Entry Parameters_
| BC: 0xF8F3
| _Returned Values_
| A: Status (0=OK, else error)
| L: Clock Mult (0:Half, 1:Full, 2: Double)
| D: Memory Wait States
| E: I/O Wait States
This function will return the running CPU speed attributes of a system.
Note that it is frequently impossible to tell if a system is capable
of dynamic speed changes. This function returns it's best guess.
If either of the wait state settings is unknown, the function will
return 0xFF.
### Function 0xF9 -- System Set (SYSSET)
| _Entry Parameters_
@ -2002,6 +2019,26 @@ available along with the registers/information used as input.
| _Returned Values_
| A: Status (0=OK, else error)
#### SYSSET Subfunction 0xF3 -- Set CPU Speed (CPUSPD)
| _Entry Parameters_
| BC: 0xF9F3
| L: Clock Mult (0:Half, 1:Full, 2: Double)
| D: Memory Wait States
| E: I/O Wait States
| _Returned Values_
| A: Status (0=OK, else error)
This function will modify the running CPU speed attributes of a system.
Note that it is frequently impossible to tell if a system is capable
of dynamic speed changes. This function makes the changes blindly.
You can specify 0xFF for either of the wait state settings to have them
left alone.
In the case of the Z180, the SIO port buad rate is derived from the CPU
speed. So, when the speed is changed the baud rate will change.
### Function 0xFA -- System Peek (SYSPEEK)
| _Entry Parameters_

16
Source/HBIOS/API.txt

@ -102,7 +102,7 @@ GET ($F8):
DE=CPU Speed in KHz
MEMINFO ($F1):
BC=Function/Subfunction A=Result
BC=FuSnction/Subfunction A=Result
D=# ROM Banks
E=# RAM Banks
@ -111,6 +111,13 @@ GET ($F8):
D=BIOS Bank Id
E=User Bank Id
CPUSPD ($F3):
BC=Function/Subfunction A=Result
L=Clock Mult (0:Half, 1:Full, 2: Double)
D=Memory Wait States
E=I/O Wait States
SET ($F9):
BC=Function/Subfunction A=Result
@ -127,6 +134,13 @@ SET ($F9):
DE=Boot Volume (Disk Unit/Slice)
L=Boot Bank Id
CPUSPD ($F3):
BC=Function/Subfunction A=Result
L=Clock Mult (0:Half, 1:Full, 2: Double)
D=Memory Wait States
E=I/O Wait States
PEEK ($FA):
B=Function A=Result
D=Bank E=Byte Value

2
Source/HBIOS/cfg_dyno.asm

@ -13,6 +13,8 @@
;
#DEFINE PLATFORM_NAME "DYNO"
;
#INCLUDE "hbios.inc"
;
PLATFORM .EQU PLT_DYNO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]

2
Source/HBIOS/cfg_ezz80.asm

@ -13,6 +13,8 @@
;
#DEFINE PLATFORM_NAME "EASYZ80"
;
#INCLUDE "hbios.inc"
;
PLATFORM .EQU PLT_EZZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]

2
Source/HBIOS/cfg_master.asm

@ -10,6 +10,8 @@
;
#DEFINE PLATFORM_NAME "ROMWBW"
;
#INCLUDE "hbios.inc"
;
PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]

2
Source/HBIOS/cfg_mbc.asm

@ -13,6 +13,8 @@
;
#DEFINE PLATFORM_NAME "Multi Board Computer"
;
#INCLUDE "hbios.inc"
;
PLATFORM .EQU PLT_MBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]

2
Source/HBIOS/cfg_mk4.asm

@ -13,6 +13,8 @@
;
#DEFINE PLATFORM_NAME "MARK IV"
;
#INCLUDE "hbios.inc"
;
PLATFORM .EQU PLT_MK4 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]

2
Source/HBIOS/cfg_n8.asm

@ -13,6 +13,8 @@
;
#DEFINE PLATFORM_NAME "N8"
;
#INCLUDE "hbios.inc"
;
PLATFORM .EQU PLT_N8 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]

2
Source/HBIOS/cfg_rcz180.asm

@ -13,6 +13,8 @@
;
#DEFINE PLATFORM_NAME "RC2014"
;
#INCLUDE "hbios.inc"
;
PLATFORM .EQU PLT_RCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]

2
Source/HBIOS/cfg_rcz280.asm

@ -13,6 +13,8 @@
;
#DEFINE PLATFORM_NAME "RC2014"
;
#INCLUDE "hbios.inc"
;
PLATFORM .EQU PLT_RCZ280 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
CPUFAM .EQU CPU_Z280 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]

2
Source/HBIOS/cfg_rcz80.asm

@ -13,6 +13,8 @@
;
#DEFINE PLATFORM_NAME "RC2014"
;
#INCLUDE "hbios.inc"
;
PLATFORM .EQU PLT_RCZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]

2
Source/HBIOS/cfg_sbc.asm

@ -13,6 +13,8 @@
;
#DEFINE PLATFORM_NAME "SBC"
;
#INCLUDE "hbios.inc"
;
PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]

2
Source/HBIOS/cfg_scz180.asm

@ -13,6 +13,8 @@
;
#DEFINE PLATFORM_NAME "SCZ180"
;
#INCLUDE "hbios.inc"
;
PLATFORM .EQU PLT_SCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]

4
Source/HBIOS/cfg_una.asm

@ -13,7 +13,9 @@
;
#DEFINE PLATFORM_NAME "UNA"
;
PLATFORM .EQU PLT_UNA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
#INCLUDE "../UBIOS/ubios.inc"
;
;PLATFORM .EQU PLT_UNA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
BIOS .EQU BIOS_UNA ; HARDWARE BIOS: BIOS_[WBW|UNA]
;
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE

2
Source/HBIOS/cfg_zeta.asm

@ -13,6 +13,8 @@
;
#DEFINE PLATFORM_NAME "ZETA"
;
#INCLUDE "hbios.inc"
;
PLATFORM .EQU PLT_ZETA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; BIOS_[WBW|UNA]: HARDWARE BIOS

2
Source/HBIOS/cfg_zeta2.asm

@ -13,6 +13,8 @@
;
#DEFINE PLATFORM_NAME "ZETA V2"
;
#INCLUDE "hbios.inc"
;
PLATFORM .EQU PLT_ZETA2 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]

120
Source/HBIOS/hbios.asm

@ -3714,6 +3714,8 @@ SYS_GET:
JP Z,SYS_GETMEMINFO
CP BF_SYSGET_BNKINFO
JP Z,SYS_GETBNKINFO
CP BF_SYSGET_CPUSPD
JP Z,SYS_GETCPUSPD
CALL SYSCHK
LD A,ERR_NOFUNC ; SIGNAL ERROR
OR A ; SET FLAGS
@ -3802,6 +3804,61 @@ SYS_GETBNKINFO:
XOR A
RET
;
; GET SYSTEM CPU SPEED ORMANCE ATTRIBUTES
; RETURNS:
; L: CLOCK MULT (0:HALF, 1:FULL, 2: DOUBLE)
; D: MEMORY WAIT STATES
; E: I/O WAIT STATES
;
SYS_GETCPUSPD:
;
#IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_MBC))
LD A,(HB_RTCVAL)
BIT 3,A
LD L,0 ; ASSUME HALF SPEED
JR Z,SYS_GETCPUSPD1
LD L,1
SYS_GETCPUSPD1:
LD DE,$FFFF ; UNKNOWN WAIT STATES
XOR A
RET
#ENDIF
;
#IF (CPUFAM == CPU_Z180)
IN0 A,(Z180_CMR) ; GET CLOCK MULTIPLIER
RLCA ; ROTATE BIT TO BIT 0
AND %00000001 ; ISOLATE IT
LD H,A ; SAVE IN H
IN0 A,(Z180_CCR) ; GET CLOCK CONTROL
RLCA ; ROTATE BIT TO BIT 0
AND %00000001 ; ISOLATE IT
LD L,A ; SAVE IN L
XOR A ; CLEAR ACCUM
ADD A,H ; ADD IN CMR BIT
ADD A,L ; ADD IN CCR BIT
LD L,A ; SAVE RESULT IN L
;
; DCNTL = MMII????
IN0 A,(Z180_DCNTL) ; GET WAIT STATES
RLCA ; ROTATE MEM WS BITS
RLCA ; ... TO LOW BITS
PUSH AF ; SAVE FOR NOW
AND %00000011 ; ISOLATE BITS
LD D,A ; PUT IN D
POP AF ; RECOVER A
RLCA ; ROTATE I/O WS BITS
RLCA ; ... TO LOW BITS
AND %00000011 ; ISOLATE BITS
INC A ; ADD 1 FOR BUILT-IN WS
LD E,A ; PUT IN E
;
XOR A
RET
#ENDIF
;
OR $FF
RET
;
; GET SERIAL UNIT COUNT
;
SYS_GETCIOCNT:
@ -3932,6 +3989,8 @@ SYS_SET:
JR Z,SYS_SETSECS
CP BF_SYSSET_BOOTINFO
JR Z,SYS_SETBOOTINFO
CP BF_SYSSET_CPUSPD
JR Z,SYS_SETCPUSPD
CALL SYSCHK
LD A,ERR_NOFUNC ; SIGNAL ERROR
OR A ; SET FLAGS
@ -3973,6 +4032,67 @@ SYS_SETSECS:
XOR A
RET
;
; SET SYSTEM CPU SPEED ATTRIBUTES
; ON ENTRY:
; L: CLOCK MULT (0:HALF, 1:FULL, 2: DOUBLE)
; D: MEMORY WAIT STATES
; E: I/O WAIT STATES
;
SYS_SETCPUSPD:
;
#IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_MBC))
;
; WAIT STATE SETTINGS ARE IGNORED FOR Z80
;
LD A,L ; CLK SPD TO ACCUM
LD C,%00000000 ; HALF SPEED
CP 0
JR Z,SYS_SETCPUSPD1
LD C,%00001000 ; FULL SPEED
CP 1
JR Z,SYS_SETCPUSPD1
JR SYS_SETCPUSPD_ERR ; SPD NOT SUPPORTED
SYS_SETCPUSPD1:
LD A,(HB_RTCVAL)
AND ~%00001000 ; CLEAR SPEED BIT
OR C ; IMPLEMENT NEW SPEED BIT
LD (HB_RTCVAL),A ; SAVE IN SHADOW REGISTER
OUT (RTCIO),A ; UPDATE HARDWARE REGISTER
XOR A
RET
#ENDIF
;
#IF (CPUFAM == CPU_Z180)
LD A,L ; CLK SPD TO ACCUM
LD B,0 ; B HAS BIT FOR CMR
LD C,0 ; C HAS BIT FOR CCR
CP 2 ; DOUBLE SPEED?
JR C,SYS_SETCPUSPD1
LD B,%10000000
SYS_SETCPUSPD1:
CP 1
JR C,SYS_SETCPUSPD2
LD C,%10000000
SYS_SETCPUSPD2:
;
IN0 A,(Z180_CMR)
AND ~%10000000
OR B
OUT0 (Z180_CMR),A
;
IN0 A,(Z180_CCR)
AND ~%10000000
OR C
OUT0 (Z180_CCR),A
;
XOR A
RET
#ENDIF
;
SYS_SETCPUSPD_ERR:
OR $FF ; NOT SUPPORTED
RET
;
; RETURN A BYTE OF MEMORY FROM SPECIFIED BANK
; ENTRY: D=BANK ID, HL=ADDRESS
; RETURN: E=BYTE VALUE

18
Source/HBIOS/hbios.inc

@ -108,10 +108,12 @@ BF_SYSGET_BOOTINFO .EQU $E0 ; GET BOOT INFORMATION
BF_SYSGET_CPUINFO .EQU $F0 ; GET CPU INFORMATION
BF_SYSGET_MEMINFO .EQU $F1 ; GET MEMORY CAPACTITY INFO
BF_SYSGET_BNKINFO .EQU $F2 ; GET BANK ASSIGNMENT INFO
BF_SYSGET_CPUSPD .EQU $F3 ; GET CLOCK SPEED & WAIT STATES
;
BF_SYSSET_TIMER .EQU $D0 ; SET TIMER VALUE
BF_SYSSET_SECS .EQU $D1 ; SET SECONDS VALUE
BF_SYSSET_BOOTINFO .EQU $E0 ; SET BOOT INFORMATION
BF_SYSSET_CPUSPD .EQU $F3 ; SET CLOCK SPEED & WAIT STATES
;
BF_SYSINT_INFO .EQU $00 ; GET INTERRUPT SYSTEM INFO
BF_SYSINT_GET .EQU $10 ; GET INT VECTOR ADDRESS
@ -119,6 +121,22 @@ BF_SYSINT_SET .EQU $20 ; SET INT VECTOR ADDRESS
;
CIO_CONSOLE .EQU $80 ; CIO UNIT NUM FOR CUR CON
;
; PRIMARY HARDWARE PLATFORMS
;
PLT_SBC .EQU 1 ; SBC ECB Z80 SBC
PLT_ZETA .EQU 2 ; ZETA Z80 SBC
PLT_ZETA2 .EQU 3 ; ZETA Z80 V2 SBC
PLT_N8 .EQU 4 ; N8 (HOME COMPUTER) Z180 SBC
PLT_MK4 .EQU 5 ; MARK IV
PLT_UNA .EQU 6 ; UNA BIOS
PLT_RCZ80 .EQU 7 ; RC2014 W/ Z80
PLT_RCZ180 .EQU 8 ; RC2014 W/ Z180
PLT_EZZ80 .EQU 9 ; EASY Z80
PLT_SCZ180 .EQU 10 ; SCZ180
PLT_DYNO .EQU 11 ; DYNO MICRO-ATX MOTHERBOARD
PLT_RCZ280 .EQU 12 ; RC2014 W/ Z280
PLT_MBC .EQU 13 ; MULTI BOARD COMPUTER
;
; HBIOS GLOBAL ERROR RETURN VALUES
;
ERR_NONE .EQU 0 ; SUCCESS

30
Source/HBIOS/std.asm

@ -42,22 +42,6 @@ DL_INFO .EQU 16 ; HBIOS DISPLAYS INFORMATIONAL MESSAGES
DL_DETAIL .EQU 20 ; HBIOS DISPLAYS DETAILED DIAGNOSTIC MESSAGES
DL_VERBOSE .EQU 24 ; HBIOS DISPLAYS ANYTHING IT KNOWS HOW TO
;
; PRIMARY HARDWARE PLATFORMS
;
PLT_SBC .EQU 1 ; SBC ECB Z80 SBC
PLT_ZETA .EQU 2 ; ZETA Z80 SBC
PLT_ZETA2 .EQU 3 ; ZETA Z80 V2 SBC
PLT_N8 .EQU 4 ; N8 (HOME COMPUTER) Z180 SBC
PLT_MK4 .EQU 5 ; MARK IV
PLT_UNA .EQU 6 ; UNA BIOS
PLT_RCZ80 .EQU 7 ; RC2014 W/ Z80
PLT_RCZ180 .EQU 8 ; RC2014 W/ Z180
PLT_EZZ80 .EQU 9 ; EASY Z80
PLT_SCZ180 .EQU 10 ; SCZ180
PLT_DYNO .EQU 11 ; DYNO MICRO-ATX MOTHERBOARD
PLT_RCZ280 .EQU 12 ; RC2014 W/ Z280
PLT_MBC .EQU 13 ; MULTI BOARD COMPUTER
;
; CPU TYPES
;
CPU_NONE .EQU 0 ; NO CPU TYPE DEFINED
@ -416,15 +400,6 @@ SPD_LOW .EQU 2 ; PLATFORM CAN CHANGE SPEED, STARTS LOW
;
#INCLUDE "build.inc" ; INCLUDE USER CONFIG, ADD VARIANT, TIMESTAMP, & ROMSIZE
;
#IF (BIOS == BIOS_WBW)
#INCLUDE "hbios.inc"
#ENDIF
;
#IF (BIOS == BIOS_UNA)
#INCLUDE "../UBIOS/ubios.inc"
#ENDIF
;
;
; INCLUDE Z180 REGISTER DEFINITIONS
;
#IF (BIOS == BIOS_WBW)
@ -713,16 +688,15 @@ INT_PIO1B .EQU 12 ; ZILOG PIO 1, CHANNEL B
#DEFINE VEC(INTX) INTX*2
#ENDIF
;
; SET DEFAULT CSIO SPEED (INTERNAL CLOCK, SLOW AS POSSIBLE)
; DIV 1280, 14KHZ @ 18MHZ CLK
;
#IF (BIOS == BIOS_WBW)
#IF (CPUFAM == CPU_Z180)
Z180_CNTR_DEF .EQU $06 ; DEFAULT VALUE FOR Z180 CSIO CONFIG
#ENDIF
#ENDIF
;
; HELPER MACROS
;

2
Source/ver.inc

@ -2,4 +2,4 @@
#DEFINE RMN 1
#DEFINE RUP 1
#DEFINE RTP 0
#DEFINE BIOSVER "3.1.1-pre.150"
#DEFINE BIOSVER "3.1.1-pre.151"

2
Source/ver.lib

@ -3,5 +3,5 @@ rmn equ 1
rup equ 1
rtp equ 0
biosver macro
db "3.1.1-pre.150"
db "3.1.1-pre.151"
endm

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