Browse Source

User Defined SD Interface

Integrated code from Lanea to allow for an easy way to define a custom SD Card interface.  CSMODE_USR is not yet complete or tested!
patch v3.1.1-pre.184
Wayne Warthen 3 years ago
parent
commit
73b0a3d941
  1. 1
      Doc/ChangeLog.txt
  2. BIN
      Doc/ROM Applications.pdf
  3. BIN
      Doc/RomWBW Applications.pdf
  4. BIN
      Doc/RomWBW Architecture.pdf
  5. BIN
      Doc/RomWBW Disk Catalog.pdf
  6. BIN
      Doc/RomWBW Getting Started.pdf
  7. 100
      ReadMe.md
  8. 4
      ReadMe.txt
  9. 2
      Source/HBIOS/cfg_dyno.asm
  10. 2
      Source/HBIOS/cfg_ezz80.asm
  11. 2
      Source/HBIOS/cfg_master.asm
  12. 2
      Source/HBIOS/cfg_mbc.asm
  13. 2
      Source/HBIOS/cfg_mk4.asm
  14. 2
      Source/HBIOS/cfg_rcz180.asm
  15. 2
      Source/HBIOS/cfg_rcz280.asm
  16. 2
      Source/HBIOS/cfg_rcz80.asm
  17. 2
      Source/HBIOS/cfg_rph.asm
  18. 2
      Source/HBIOS/cfg_sbc.asm
  19. 2
      Source/HBIOS/cfg_scz180.asm
  20. 2
      Source/HBIOS/cfg_zeta.asm
  21. 2
      Source/HBIOS/cfg_zeta2.asm
  22. 58
      Source/HBIOS/sd.asm
  23. 1
      Source/HBIOS/std.asm
  24. 2
      Source/ver.inc
  25. 2
      Source/ver.lib

1
Doc/ChangeLog.txt

@ -64,6 +64,7 @@ Version 3.1.1
- WBW: Add support for "romless" booting
- L?N: Fixes for ZCPR-D&J (buffer overflow, default drive/user)
- J?P: Add support for DS1501 RTC
- LLS: Added a user defined mode for SD Card interfaces (not complete)
Version 3.1
-----------

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Doc/ROM Applications.pdf

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Doc/RomWBW Applications.pdf

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Doc/RomWBW Architecture.pdf

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Doc/RomWBW Disk Catalog.pdf

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Doc/RomWBW Getting Started.pdf

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100
ReadMe.md

@ -3,7 +3,7 @@
## Z80/Z180 System Software
Version 3.1 Pre-release
05 Nov 2022
10 Dec 2022
Wayne Warthen <wwarthen@gmail.com>
@ -748,13 +748,13 @@ most stable and you are less likely to encounter problems.
### Notes
- You can change media, but it must be done while at the OS command
prompt and you **must** warm start CP/M by pressing ctrl-c. This is
a CP/M 2.2 constraint and is well documented in the DRI manuals.
prompt and you **must** warm start CP/M by pressing ctrl-c. This is a
CP/M 2.2 constraint and is well documented in the DRI manuals.
- The original versions of DDT, DDTZ, and ZSID used the RST 38 vector
which conflicts with interrupt mode 1 use of this vector. The DDT,
DDTZ, and ZSID applications in RomWBW have been modified to use RST
30 to avoid this issue.
DDTZ, and ZSID applications in RomWBW have been modified to use RST 30
to avoid this issue.
- Z-System applications will not run under CP/M 2.2. For example, the
`LDDS` date stamper will not run.
@ -775,14 +775,13 @@ Manual.pdf”).
### Notes
- Although most CP/M 2.2 applications will run under Z-System, some
may not work as expected. The best example is PIP which is not aware
of the ZSDOS paths and will fail in some scenarios (use `COPY`
instead).
- Although most CP/M 2.2 applications will run under Z-System, some may
not work as expected. The best example is PIP which is not aware of
the ZSDOS paths and will fail in some scenarios (use `COPY` instead).
- Although ZSDOS can recognize a media change in some cases, it will
not always work. You should only change media at a command prompt
and be sure to warm start the OS with a ctrl-c.
- Although ZSDOS can recognize a media change in some cases, it will not
always work. You should only change media at a command prompt and be
sure to warm start the OS with a ctrl-c.
## NZCOM Automatic Z-System
@ -821,18 +820,17 @@ tracks. `CPMLDR.SYS` chain loads `CPM3.SYS`.
### Notes
- The `DATE` command cannot yet be used to **set** the RTC. The RTC is
used to read the current date/time for file stamping, etc. You can
use the `RTC` app to set the RTC clock.
used to read the current date/time for file stamping, etc. You can use
the `RTC` app to set the RTC clock.
- The `COPYSYS` command described in the DRI CP/M 3 documentation is
not provided with RomWBW. The RomWBW `SYSCOPY` command is used
instead.
- The `COPYSYS` command described in the DRI CP/M 3 documentation is not
provided with RomWBW. The RomWBW `SYSCOPY` command is used instead.
- Although CP/M 3 is generally able to run CP/M 2.2 programs, this is
not universally true. This is especially true of the utility
programs included with the operating system. For example, the
`SUBMIT` program of CP/M 3 is completely different from the `SUBMIT`
program of CP/M 2.2.
not universally true. This is especially true of the utility programs
included with the operating system. For example, the `SUBMIT` program
of CP/M 3 is completely different from the `SUBMIT` program of CP/M
2.2.
## Simeon Cran’s ZPM3
@ -845,13 +843,13 @@ tracks of the disk.
### Notes
- `ZPMLDR` is equivalent to CPMLDR. Both are included. Previously,
ZPMLDR had issues that prevented it from properly booting RomWBW
ZPM3. However, those issues have been resolved.
ZPMLDR had issues that prevented it from properly booting RomWBW ZPM3.
However, those issues have been resolved.
- The ZPM operating system is contained in the file called CPM3.SYS
which is confusing, but this is as intended by the ZPM3
distribution. I believe it was done this way to make it easier for
users to transition from CP/M 3 to ZPM3.
which is confusing, but this is as intended by the ZPM3 distribution.
I believe it was done this way to make it easier for users to
transition from CP/M 3 to ZPM3.
## FreeRTOS
@ -1148,8 +1146,8 @@ system on your disk.
- **CP/M 2.2**
Boot to CP/M 2.2 from ROM, then use `SYSCOPY` to update the system
image on **all** CP/M 2.2 boot disks/slices. The CP/M 2.2 system
image is called CPM.SYS and is found on the ROM disk. For example:
image on **all** CP/M 2.2 boot disks/slices. The CP/M 2.2 system image
is called CPM.SYS and is found on the ROM disk. For example:
`B>SYSCOPY C:=CPM.SYS`
@ -1163,10 +1161,9 @@ system on your disk.
- **NZCOM**
NZCOM runs on top of either CP/M 2.2 or ZSDOS. By default, the
RomWBW disk image for NZCOM uses ZSDOS. Follow the corresponding
procedure above to update the system image on the NZCOM boot
disks/slices.
NZCOM runs on top of either CP/M 2.2 or ZSDOS. By default, the RomWBW
disk image for NZCOM uses ZSDOS. Follow the corresponding procedure
above to update the system image on the NZCOM boot disks/slices.
- **CP/M 3**
@ -1175,12 +1172,11 @@ system on your disk.
constraints. You will need to transfer the files to your system from
the RomWBW distribution directory Binary\CPM3.
After this is done, you will need to use `SYSCOPY` to place the CP/M
3 loader image on the boot tracks of all CP/M 3 boot disks/slices.
The loader image is called `CPMLDR.SYS`. You must then copy (at a
minimum) `CPM3.SYS` and `CCP.COM` onto the disk/slice. Assuming you
copied the CP/M 3 boot files onto your RAM disk at A:, you would
use:
After this is done, you will need to use `SYSCOPY` to place the CP/M 3
loader image on the boot tracks of all CP/M 3 boot disks/slices. The
loader image is called `CPMLDR.SYS`. You must then copy (at a minimum)
`CPM3.SYS` and `CCP.COM` onto the disk/slice. Assuming you copied the
CP/M 3 boot files onto your RAM disk at A:, you would use:
A>B:SYSCOPY C:=CPMLDR.SYS
A>B:COPY CPM3.SYS C:
@ -1188,17 +1184,17 @@ system on your disk.
- **ZPM3**
ZPM3 uses a multi-step boot process involving multiple files. The
ZPM3 boot files are not included on the ROM disk due to space
constraints. You will need to transfer the files to your system from
the RomWBW distribution directory Binary\ZPM3.
ZPM3 uses a multi-step boot process involving multiple files. The ZPM3
boot files are not included on the ROM disk due to space constraints.
You will need to transfer the files to your system from the RomWBW
distribution directory Binary\ZPM3.
After this is done, you will need to use `SYSCOPY` to place the ZPM3
loader image on the boot tracks of all ZPM3 boot disks/slices. The
loader image is called `ZPMLDR.SYS`. You must then copy (at a
minimum) `CPM3.SYS`, `ZCCP.COM`, `ZINSTAL.ZPM`, and `STARTZPM.COM`
onto the disk/slice. Assuming you copied the ZPM3 boot files onto
your RAM disk at A:, you would use:
loader image is called `ZPMLDR.SYS`. You must then copy (at a minimum)
`CPM3.SYS`, `ZCCP.COM`, `ZINSTAL.ZPM`, and `STARTZPM.COM` onto the
disk/slice. Assuming you copied the ZPM3 boot files onto your RAM disk
at A:, you would use:
A>B:SYSCOPY C:=ZPMLDR.SYS
A>B:COPY CPM3.SYS C:
@ -1207,9 +1203,8 @@ system on your disk.
A>B:COPY STARTZPM.COM C:
You may be wondering if the reference to `CPM3.SYS` is a typo. It is
not. The ZPM3 main system code file is called `CPM3.SYS` which is
the same name as CP/M 3 uses, but the file contents are not the
same.
not. The ZPM3 main system code file is called `CPM3.SYS` which is the
same name as CP/M 3 uses, but the file contents are not the same.
Finally, if you have copies of any of the RomWBW custom applications on
your hard disk, you need to update them with the latest copies. The
@ -1319,8 +1314,8 @@ applications are no longer provided.
- FLASH4 is a product of Will Sowerbutts.
- CLRDIR is a product of Max Scane.
- Tasty Basic is a product of Dimitri Theulings.
- Dean Netherton contributed the sound driver interface and the
SN76489 sound driver.
- Dean Netherton contributed the sound driver interface and the SN76489
sound driver.
- The RomWBW Disk Catalog document was produced by Mykl Orders.
Contributions of all kinds to RomWBW are very welcome.
@ -1372,8 +1367,7 @@ All contributions to RomWBW are subject to this license.
The best way to get assistance with RomWBW or any aspect of the
RetroBrew Computers projects is via the community forums:
- [RetroBrew Computers
Forum](https://www.retrobrewcomputers.org/forum/)
- [RetroBrew Computers Forum](https://www.retrobrewcomputers.org/forum/)
- [RC2014 Google
Group](https://groups.google.com/forum/#!forum/rc2014-z80)
- [retro-comp Google

4
ReadMe.txt

@ -1,6 +1,6 @@
RomWBW Getting Started
Wayne Warthen (mailto:wwarthen@gmail.com)
05 Nov 2022
10 Dec 2022
@ -17,7 +17,7 @@ RomWBW
Z80/Z180 System Software
Version 3.1 Pre-release
05 Nov 2022
10 Dec 2022
Wayne Warthen wwarthen@gmail.com

2
Source/HBIOS/cfg_dyno.asm

@ -174,7 +174,7 @@ PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT]
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

2
Source/HBIOS/cfg_ezz80.asm

@ -211,7 +211,7 @@ PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT]
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

2
Source/HBIOS/cfg_master.asm

@ -279,7 +279,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_NONE ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT]
SDMODE .EQU SDMODE_NONE ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

2
Source/HBIOS/cfg_mbc.asm

@ -208,7 +208,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT]
SDMODE .EQU SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

2
Source/HBIOS/cfg_mk4.asm

@ -207,7 +207,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
;
SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_MK4 ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT]
SDMODE .EQU SDMODE_MK4 ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

2
Source/HBIOS/cfg_rcz180.asm

@ -224,7 +224,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT]
SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .EQU 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

2
Source/HBIOS/cfg_rcz280.asm

@ -239,7 +239,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT]
SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .EQU 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

2
Source/HBIOS/cfg_rcz80.asm

@ -228,7 +228,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT]
SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .EQU 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

2
Source/HBIOS/cfg_rph.asm

@ -209,7 +209,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT]
SDMODE .EQU SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
SDPPIBASE .EQU RPH_PPI0 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

2
Source/HBIOS/cfg_sbc.asm

@ -208,7 +208,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT]
SDMODE .EQU SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

2
Source/HBIOS/cfg_scz180.asm

@ -219,7 +219,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
;
SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT]
SDMODE .EQU SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

2
Source/HBIOS/cfg_zeta.asm

@ -152,7 +152,7 @@ PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT]
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

2
Source/HBIOS/cfg_zeta2.asm

@ -163,7 +163,7 @@ PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT]
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

58
Source/HBIOS/sd.asm

@ -128,6 +128,7 @@ SD_CLK .EQU %00000010 ; RTC:1 IS CLOCK
SD_DI .EQU %00000001 ; RTC:0 IS DATA IN (CARD <- CPU)
SD_DO .EQU %10000000 ; RTC:7 IS DATA OUT (CARD -> CPU)
SD_IOBASE .EQU SD_OPRREG ; IOBASE
SD_INVCS .EQU FALSE ; INVERT CS
;
RTCDEF .SET RTCDEF | SD_OPRDEF ; SET DEFAULT IN HBIOS MAINLINE
#ENDIF
@ -143,6 +144,7 @@ SD_CLK .EQU %00000010 ; RTC:1 IS CLOCK
SD_DI .EQU %00000001 ; RTC:0 IS DATA IN (CARD <- CPU)
SD_DO .EQU %01000000 ; RTC:6 IS DATA OUT (CARD -> CPU)
SD_IOBASE .EQU SD_OPRREG ; IOBASE
SD_INVCS .EQU FALSE ; INVERT CS
;
RTCDEF .SET RTCDEF | SD_OPRDEF ; SET DEFAULT IN HBIOS MAINLINE
#ENDIF
@ -156,6 +158,7 @@ SD_CS0 .EQU %00000100 ; RTC:2 IS SELECT
SD_CNTR .EQU Z180_CNTR
SD_TRDR .EQU Z180_TRDR
SD_IOBASE .EQU SD_OPRREG ; IOBASE
SD_INVCS .EQU FALSE ; INVERT CS
;
RTCDEF .SET RTCDEF | SD_OPRDEF ; SET DEFAULT IN HBIOS MAINLINE
#ENDIF
@ -174,6 +177,7 @@ SD_CLK .EQU %00000010 ; PPIC:1 IS CLOCK
SD_DI .EQU %00000001 ; PPIC:0 IS DATA IN (CARD <- CPU)
SD_DO .EQU %10000000 ; PPIB:7 IS DATA OUT (CARD -> CPU)
SD_IOBASE .EQU SD_PPIBASE ; IOBASE
SD_INVCS .EQU TRUE ; INVERT CS
#ENDIF
;
#IF (SDMODE == SDMODE_UART)
@ -187,6 +191,7 @@ SD_CLK .EQU %00000100 ; UART MCR:2 IS CLOCK
SD_DI .EQU %00000001 ; UART MCR:0 IS DATA IN (CARD <- CPU)
SD_DO .EQU %00100000 ; UART MSR:5 IS DATA OUT (CARD -> CPU)
SD_IOBASE .EQU UARTIOB ; IOBASE
SD_INVCS .EQU TRUE ; INVERT CS
#ENDIF
;
#IF (SDMODE == SDMODE_DSD) ; DUAL SD
@ -201,6 +206,7 @@ SD_CLK .EQU %00000010 ; RTC:1 IS CLOCK
SD_DI .EQU %00000001 ; RTC:6 IS DATA IN (CARD <- CPU)
SD_DO .EQU %00000001 ; RTC:0 IS DATA OUT (CARD -> CPU)
SD_IOBASE .EQU SD_OPRREG ; IOBASE
SD_INVCS .EQU FALSE ; INVERT CS
#ENDIF
;
#IF (SDMODE == SDMODE_MK4) ; MARK IV (CSIO STYLE INTERFACE)
@ -211,6 +217,7 @@ SD_CS0 .EQU %00000100 ; SELECT ACTIVE
SD_CNTR .EQU Z180_CNTR
SD_TRDR .EQU Z180_TRDR
SD_IOBASE .EQU SD_OPRREG ; IOBASE
SD_INVCS .EQU FALSE ; INVERT CS
#ENDIF
;
#IF (SDMODE == SDMODE_SC) ; SC
@ -223,6 +230,7 @@ SD_CS1 .EQU %00001000 ; RTC:3 IS SELECT FOR SECONDARY SPI CARD
SD_CNTR .EQU Z180_CNTR
SD_TRDR .EQU Z180_TRDR
SD_IOBASE .EQU SD_OPRREG ; IOBASE
SD_INVCS .EQU TRUE ; INVERT CS
;
RTCDEF .SET RTCDEF | SD_OPRDEF ; SET DEFAULT IN HBIOS MAINLINE
#ENDIF
@ -270,6 +278,30 @@ SD_CS0 .EQU %00100000 ; IN/OUT:SD_OPREG:5 = CS2, SDCARD2 CS, IN=1 Card present
SD_CS1 .EQU %00010000 ; IN/OUT:SD_OPREG:4 = CS1, SDCARD1 CS, IN=1 Card present
#ENDIF
SD_IOBASE .EQU SD_BASE ; IOBASE
SD_INVCS .EQU FALSE ; INVERT CS
#ENDIF
;
;
#IF (SDMODE == SDMODE_USR) ; USER DEFINED HARDWARE CONFIGURATION
;
; THIS MODE IS INTENDED TO ALLOW A USER TO EASILY CONFIGURE A CUSTOM
; SD CARD INTERFACE. IT IS NOT YET COMPLETE OR TESTED AND PROBABLY DOES
; NOT YET WORK.
;
SD_DEVMAX .EQU 2 ; NUMBER OF PHYSICAL UNITS (SOCKETS)
SD_IOBASE .EQU $01 ; IO BASE ADDRESS FOR SD INTERFACE
SD_OPRREG .EQU SD_IOBASE ; OUTPUT PORT (OUTPUT: CS, CLK, DIN)
SD_OPRDEF .EQU %00000101 ; OUTPUT PORT DEFAULT STATE
SD_OPRMSK .EQU %00001111 ; OUTPUT PORT MASK
SD_INPREG .EQU SD_IOBASE ; INPUT REGISTER
SD_CS0 .EQU %00001000 ; SELECT
SD_CLK .EQU %00000100 ; CLOCK
SD_DI .EQU %00000010 ; DATA IN (CARD <- CPU) MOSI
SD_DO .EQU %00000001 ; DATA OUT (CARD -> CPU) MISO
SD_CINIT .EQU TRUE ; INITIALIZE OUTPUT PORT
SD_DDR .EQU $03 ; DATA DIRECTION REGISTER
SD_DDRVAL .EQU %00001101 ; DATA DIRECTION REGISTER VALUE
SD_INVCS .EQU FALSE ; INVERT CS
#ENDIF
;
#IF (SD_DEVCNT > SD_DEVMAX)
@ -477,6 +509,13 @@ SD_INIT:
LD A,SD_BASE
CALL PRTHEXBYTE
#ENDIF
;
#IF (SDMODE == SDMODE_USR)
PRTS(" MODE=USER$")
PRTS(" IO=0x$")
LD A,SD_IOBASE
CALL PRTHEXBYTE
#ENDIF
;
CALL SD_PROBE ; CHECK FOR HARDWARE
JR Z,SD_INIT00 ; CONTINUE IF PRESENT
@ -1695,6 +1734,22 @@ SD_SETUP:
LD (SD_OPRVAL),A ; RECORD THE WORKING VALLUE
OUT (SD_OPRREG),A ; OPRREG == SIO_MCR
#ENDIF
;
#IF (SDMODE == SDMODE_USR)
#IF (SD_CINIT == TRUE)
LD A,(SD_OPRMSK) ; GET OUTPUT PORT MASK
CPL ; INVERT ACCUMULATOR
LD C,A ; SAVE IT FOR LATER
LD A,(SD_DDR) ; GET DATA DIRECTION REGISTER VALUE
AND C ; ZERO ALL INTERESTING BITS
OR (SD_DDRVAL) ; ADD OUR VALUE
LD (SD_DDR),A ; WRITE IT
#ENDIF
;
LD A,SD_OPRDEF
LD (SD_OPRVAL),A
OUT (SD_OPRREG),A
#ENDIF
;
XOR A
RET
@ -1766,7 +1821,8 @@ SD_SELECT1:
;
SD_SELECT2:
; ADJUST BIT(S) FOR INTERFACES USING INVERTED CS BITS
#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC))
;#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC))
#IF (SD_INVCS)
#IF ((SDMODE == SDMODE_SC) & (SD_DEVCNT > 1))
XOR SD_CS0 | SD_CS1
#ELSE

1
Source/HBIOS/std.asm

@ -181,6 +181,7 @@ SDMODE_DSD .EQU 6 ; DUAL SD
SDMODE_MK4 .EQU 7 ; MARK IV
SDMODE_SC .EQU 8 ; SC (Steve Cousins)
SDMODE_MT .EQU 9 ; MT (Shift register SPI WIZNET for RC2014)
SDMODE_USR .EQU 10 ; USER DEFINED (in sd.asm) (NOT COMPLETE)
;
; AY SOUND CHIP MODE SELECTIONS
;

2
Source/ver.inc

@ -2,4 +2,4 @@
#DEFINE RMN 1
#DEFINE RUP 1
#DEFINE RTP 0
#DEFINE BIOSVER "3.1.1-pre.183"
#DEFINE BIOSVER "3.1.1-pre.184"

2
Source/ver.lib

@ -3,5 +3,5 @@ rmn equ 1
rup equ 1
rtp equ 0
biosver macro
db "3.1.1-pre.183"
db "3.1.1-pre.184"
endm

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