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ez80: ported fd.asm driver

master
Dean Netherton 2 years ago
parent
55d8c6ce7d
commit
9898309f29
6 changed files with 110 additions and 64 deletions
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  1. 8
      Source/HBIOS/Config/RCEZ80_std.asm
  2. 6
      Source/HBIOS/cfg_rcez80.asm
  3. 26
      Source/HBIOS/ez80instr.inc
  4. 34
      Source/HBIOS/fd.asm
  5. 36
      Source/HBIOS/hbios.asm
  6. 16
      Source/HBIOS/sn76489.asm

8
Source/HBIOS/Config/RCEZ80_std.asm
View File

@ -26,7 +26,7 @@
;
#include "cfg_rcez80.asm"
;
CPUOSC .SET 24000000 ; CPU OSC FREQ IN MHZ
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ
;
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
;
@ -52,7 +52,7 @@ AY38910ENABLE .SET FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER
AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER
;
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
;
IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
@ -67,7 +67,3 @@ PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
EZ80UARTENABLE .SET TRUE ; EZ80 UART: ENABLE EZ80 UART0 DRIVER (EZ80UART.ASM)
EZ80RTCENABLE .SET TRUE ; EZ80 ON CHIP RTC
EZ80TIMER .SET EZ80TMR_INT ; EZ80: TIMER TICK MODEL: EZ80TMR_[INT|FIRM]
EZ80_IO_FREQ .SET 5250
EZ80_MEM_FREQ .SET 8000
EZ80_ASSIGN .EQU 1 ; 0 -> USE FREQ, 1 -> USE CYCLES
EZ80_IO_CYCLES .EQU 5 ; EZ80 CYCLES FOR IO (1-15)

6
Source/HBIOS/cfg_rcez80.asm
View File

@ -46,11 +46,11 @@ MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
;
; BUS TIMING FOR PAGED MEMORY ACCESS (CS3)
EZ80_MEM_CYCLES .EQU 3 ; EZ80 CYCLES FOR MEMORY (1-15)
EZ80_MEM_FREQ .EQU 8000 ; CALCULATE APPROPRIATE BUS CYCLES TO ACHIVE APPOX BUS FREQUENCY
EZ80_MEM_FREQ .EQU 16000 ; CALCULATE APPROPRIATE BUS CYCLES TO ACHIVE APPOX BUS FREQUENCY
;
; BUS TIMING FOR EXTERNAL I/O ACCESS (CS2)
EZ80_IO_CYCLES .EQU 3 ; EZ80 CYCLES FOR IO (1-15)
EZ80_IO_FREQ .EQU 8000 ; CALCULATE APPROPRIATE BUS CYCLES TO ACHIVE APPOX BUS FREQUENCY
EZ80_IO_CYCLES .EQU 4 ; EZ80 CYCLES FOR IO (1-15)
EZ80_IO_FREQ .EQU 5250 ; CALCULATE APPROPRIATE BUS CYCLES TO ACHIVE APPOX BUS FREQUENCY
;
; SELECT CYCLES, OR CALCULATE CYCLES BASED ON DESIRED FREQUENCY
EZ80_ASSIGN .EQU 0 ; 0 -> USE FREQ, 1 -> USE CYCLES

26
Source/HBIOS/ez80instr.inc
View File

@ -33,13 +33,14 @@
#DEFINE EZ80_TMR_SET_SECONDS LD A, 2 \ LD B, 3 \ EZ80_FN
#DEFINE EZ80_TMR_GET_FREQTICK LD A, 2 \ LD B, 4 \ EZ80_FN
#DEFINE EZ80_TMR_SET_FREQTICK LD A, 2 \ LD B, 5 \ EZ80_FN
#DEFINE EZ80_TMR_DELAY_START LD A, 2 \ LD B, 6 \ EZ80_FN
#DEFINE EZ80_TMR_DELAY_WAIT LD A, 2 \ LD B, 7 \ EZ80_FN
#DEFINE EZ80_TMR_THROTTLE_START LD A, 2 \ LD B, 6 \ EZ80_FN
#DEFINE EZ80_TMR_THROTTLE_WAIT LD A, 2 \ LD B, 7 \ EZ80_FN
#DEFINE EZ80_TMR_INT_DISABLE LD A, 2 \ LD B, 8 \ EZ80_FN
#DEFINE EZ80_TMR_INT_ENABLE LD A, 2 \ LD B, 9 \ EZ80_FN
#DEFINE EZ80_TMR_IS_TICK_ISR LD A, 2 \ LD B, 10 \ EZ80_FN
#DEFINE EZ80_TMR_DELAY LD A, 2 \ LD B, 11 \ EZ80_FN
#DEFINE EZ80_DELAY_START(p,store) \
#DEFINE EZ80_THROTTLE_START(p,store) \
#DEFCONT \ PUSH AF
#DEFCONT \ PUSH BC
#DEFCONT \ PUSH HL
@ -51,7 +52,7 @@
#DEFCONT \ POP BC
#DEFCONT \ POP AF
#DEFINE EZ80_DELAY_WAIT(p,store) \
#DEFINE EZ80_THROTTLE_WAIT(p,store) \
#DEFCONT \ PUSH AF
#DEFCONT \ PUSH BC
#DEFCONT \ PUSH HL
@ -106,12 +107,25 @@
IO_SEGMENT .EQU $FF ; THE UPPER 8-BIT ADDRESS FOR I/O
#DEFINE OUT_NN_A(addr) \
#DEFCONT \ PUSH BC
#DEFCONT \ LD BC, IO_SEGMENT << 8 | addr
#DEFCONT \ OUT (C), A
#DEFCONT \ POP BC
#DEFINE IN_A_NN(addr) \
#DEFCONT \ LD A, IO_SEGMENT
#DEFCONT \ IN A, (addr)
#ELSE
#DEFINE EZ80_IO
#DEFINE EZ80_DELAY_START(p,store)
#DEFINE EZ80_DELAY_WAIT(p,store)
#DEFINE EZ80_THROTTLE_START(p,store)
#DEFINE EZ80_THROTTLE_WAIT(p,store)
IO_SEGMENT .EQU $FF ; THE UPPER 8-BIT ADDRESS FOR I/O
#DEFINE OUT_NN_A(addr) OUT (addr), A
#DEFINE IN_A_NN(addr) IN A, (addr)
#ENDIF

34
Source/HBIOS/fd.asm
View File

@ -883,15 +883,15 @@ FD_DETECT:
LD (FST_DOR),A ; AND PUT IN SHADOW REGISTER
CALL FC_RESETFDC ; RESET FDC
IN A,(FDC_MSR) ; READ MSR
IN_A_NN(FDC_MSR) ; READ MSR
;CALL PC_SPACE ; *DEBUG*
;CALL PRTHEXBYTE ; *DEBUG*
CP $D0 ; SPECIAL CASE: DATA PENDING?
JR NZ,FD_DETECT1 ; NOPE, MOVE ALONG
IN A,(FDC_DATA) ; SWALLOW THE PENDING DATA
IN_A_NN(FDC_DATA) ; SWALLOW THE PENDING DATA
CALL DLY32 ; SETTLE
IN A,(FDC_MSR) ; ... AND REREAD THE STATUS
IN_A_NN(FDC_MSR) ; ... AND REREAD THE STATUS
;CALL PC_SPACE ; *DEBUG*
;CALL PRTHEXBYTE ; *DEBUG*
@ -902,7 +902,7 @@ FD_DETECT1:
; WE HAVE SEEN AN FDC THAT NEEDS A SECOND READ TO GET
; DESIRED VALUE, SO TRY ONE MORE TIME
CALL DLY32 ; WAIT A BIT
IN A,(FDC_MSR) ; ... AND REREAD THE STATUS
IN_A_NN(FDC_MSR) ; ... AND REREAD THE STATUS
;CALL PC_SPACE ; *DEBUG*
;CALL PRTHEXBYTE ; *DEBUG*
CP $80 ; CHECK FOR CORRECT VALUE
@ -1452,7 +1452,7 @@ FC_SETUPSPECIFY:
;
FC_SETDOR:
LD (FST_DOR),A
OUT (FDC_DOR),A
OUT_NN_A(FDC_DOR)
#IF (FDTRACE >= 3)
CALL NEWLINE
LD DE,FDSTR_DOR
@ -1471,7 +1471,7 @@ FC_SETDOR:
;
FC_SETDCR
LD (FST_DCR),A
OUT (FDC_DCR),A
OUT_NN_A(FDC_DCR)
#IF (FDTRACE >= 3)
CALL NEWLINE
LD DE,FDSTR_DCR
@ -1644,11 +1644,11 @@ FOP:
LD B,0 ; B IS LOOP COUNTER
FOP_CLR1:
CALL DELAY ; FDC MAY TAKE UP TO 12us TO UPDATE MSR
IN A,(FDC_MSR) ; GET STATUS
IN_A_NN(FDC_MSR) ; GET STATUS
AND 0C0H ; ISOLATE HIGH NIBBLE, RQM/DIO/NDM/CB
CP 0C0H ; LOOKING FOR RQM=1, DIO=1, BYTES PENDING
JR NZ,FOP_CMD1 ; NO BYTES PENDING, GO TO NEXT PHASE
IN A,(FDC_DATA) ; GET THE PENDING BYTE AND DISCARD
IN_A_NN(FDC_DATA) ; GET THE PENDING BYTE AND DISCARD
DJNZ FOP_CLR1
JP FOP_TOFDCRDY ; OTHERWISE, TIMEOUT
;
@ -1664,7 +1664,7 @@ FOP_CMD2: ; START OF LOOP TO SEND NEXT BYTE
FOP_CMD4: ; START OF STATUS LOOP, WAIT FOR FDC TO BE READY FOR BYTE
CALL DELAY ; FDC MAY TAKE UP TO 12us TO UPDATE MSR
IN A,(FDC_MSR) ; READ MAIN STATUS REGISTER
IN_A_NN(FDC_MSR) ; READ MAIN STATUS REGISTER
AND 0C0H ; ISOLATE RQM/DIO
CP 080H ; LOOKING FOR RQM=1, DIO=0 (FDC READY FOR A BYTE)
JR Z,FOP_CMD6 ; GOOD, GO TO SEND BYTE
@ -1675,7 +1675,7 @@ FOP_CMD4: ; START OF STATUS LOOP, WAIT FOR FDC TO BE READY FOR BYTE
FOP_CMD6: ; SEND NEXT BYTE
LD A,(HL) ; POINT TO NEXT BYTE TO SEND
OUT (FDC_DATA),A ; PUSH IT TO FDC
OUT_NN_A(FDC_DATA) ; PUSH IT TO FDC
INC HL ; INCREMENT POINTER FOR NEXT TIME
DEC D ; DECREMENT NUM BYTES LEFT TO SEND
JR NZ,FOP_CMD2 ; DO NEXT BYTE
@ -1706,7 +1706,7 @@ FXR_NULL:
LD BC,$7000 ; LOOP COUNTER, $7000 * 16us = ~485ms
FXR_NULL1:
CALL DELAY ; FDC MAY TAKE UP TO 12us TO UPDATE MSR
IN A,(FDC_MSR) ; GET MSR
IN_A_NN(FDC_MSR) ; GET MSR
AND 0E0H ; ISOLATE RQM/DIO/NDM
CP 0C0H ; WE WANT RQM=1,DIO=1,NDM=0 (READY TO READ A BYTE W/ EXEC INACTIVE)
JP Z,FOP_RES ; EXEC DONE, EXIT CLEAN W/O PULSING TC
@ -1737,13 +1737,13 @@ FXR_READ:
LD (FCD_TO),A ; INIT TIMEOUT COUNTER
FXRR1 LD C,0 ; OUTER LOOP TIMEOUT COUNTER
FXRR2: LD B,0 ; SETUP FOR 256 ITERATIONS
FXRR3: IN A,(FDC_MSR) ; GET MSR
FXRR3: IN_A_NN(FDC_MSR) ; GET MSR
CP 0F0H ; WE WANT RQM=1,DIO=1,NDM=1,BUSY=1 (READY TO RECEIVE A BYTE W/ EXEC ACTIVE)
JR Z,FXRR4 ; GOT IT, DO BYTE READ
DJNZ FXRR3 ; NOT READY, LOOP IF COUNTER NOT ZERO
JR FXRR5 ; COUNTER ZERO, GO TO OUTER LOOP LOGIC
FXRR4: IN A,(FDC_DATA) ; GET PENDING BYTE
FXRR4: IN_A_NN(FDC_DATA) ; GET PENDING BYTE
LD (HL),A ; STORE IT IN BUFFER
INC HL ; INCREMENT THE BUFFER POINTER
DEC DE ; DECREMENT BYTE COUNT
@ -1780,13 +1780,13 @@ FXR_WRITE:
LD (FCD_TO),A
FXRW1 LD C,0 ; OUTER LOOP TIMEOUT COUNTER
FXRW2: LD B,0 ; SETUP FOR 256 ITERATIONS
FXRW3: IN A,(FDC_MSR) ; GET MSR
FXRW3: IN_A_NN(FDC_MSR) ; GET MSR
CP 0B0H ; WE WANT RQM=1,DIO=0,NDM=1,BUSY=1 (READY TO SEND A BYTE W/ EXEC ACTIVE)
JR Z,FXRW4 ; GOT IT, DO BYTE WRITE
DJNZ FXRW3 ; NOT READY, LOOP IF COUNTER NOT ZERO
JR FXRW5 ; COUNTER ZERO, GO TO OUTER LOOP LOGIC
FXRW4: LD A,(HL) ; GET NEXT BYTE TO WRITE
OUT (FDC_DATA),A ; WRITE IT
OUT_NN_A(FDC_DATA) ; WRITE IT
INC HL ; INCREMENT THE BUFFER POINTER
DEC DE ; DECREMENT LOOP COUNTER
LD A,D
@ -1830,7 +1830,7 @@ FOP_RES0:
FOP_RES1:
CALL DELAY ; FDC MAY TAKE UP TO 12us TO UPDATE MSR
IN A,(FDC_MSR) ; READ MAIN STATUS REGISTER
IN_A_NN(FDC_MSR) ; READ MAIN STATUS REGISTER
AND 0F0H ; ISOLATE RQM/DIO/EXEC/BUSY
CP 0D0H ; LOOKING FOR RQM/DIO/BUSY
JR Z,FOP_RES2 ; GOOD, GO TO RECEIVE BYTE
@ -1848,7 +1848,7 @@ FOP_RES2: ; PROCESS NEXT PENDING BYTE
LD A,FRB_SIZ ; GET BUF SIZE
CP D ; REACHED MAX?
JR Z,FOP_BUFMAX ; HANDLE BUF MAX/EXIT
IN A,(FDC_DATA) ; GET THE BYTE
IN_A_NN(FDC_DATA) ; GET THE BYTE
LD (HL),A ; SAVE VALUE
INC HL ; INCREMENT BUF POS
INC D ; INCREMENT BYTES RECEIVED

36
Source/HBIOS/hbios.asm
View File

@ -2846,6 +2846,42 @@ PSCNX .EQU $ + 1
DJNZ PSCN1
;
#ENDIF
#IF (CPUFAM == CPU_EZ80)
;
;--------------------------------------------------------------------------------------------------
; DELAY LOOP TEST CALIBRATION
;--------------------------------------------------------------------------------------------------
;
; IF ENABLED, THE GPIO PCBx PINS OF THE EZ80 WILL BE TOGGLED AT 'DELAY' RATE
; CAN BE USED TO VERIFY DELAY WORKS SUFFICIENT FOR DIFFERENT EZ80 CLOCK SPEEDS
; AND BUS CYCLES
;
#IF FALSE
PC_DR: .equ $009E
PC_DDR: .equ $009F
; ENABLE PC5 GPIO AS OUTPUT
LD BC, PC_DDR
XOR A
OUT (C), A
PUSH AF
LD BC, PC_DR
LD D, 0
LOOP:
POP AF
OUT (C), A
CPL
PUSH AF
LD DE, 2
CALL VDELAY
JR LOOP
#ENDIF
#ENDIF
;
;--------------------------------------------------------------------------------------------------
; CPU SPEED DETECTION ALIGNMENT TEST

16
Source/HBIOS/sn76489.asm
View File

@ -118,28 +118,28 @@ SN7_VOLUME_OFF:
LD A, CHANNEL_0_SILENT
LD BC, SN76489_PORT16_LEFT
EZ80_DELAY_START(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
EZ80_THROTTLE_START(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
OUT (C), A
LD BC, SN76489_PORT16_RIGHT
OUT (C), A
LD A, CHANNEL_1_SILENT
LD BC, SN76489_PORT16_LEFT
EZ80_DELAY_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
EZ80_THROTTLE_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
OUT (C), A
LD BC, SN76489_PORT16_RIGHT
OUT (C), A
LD A, CHANNEL_2_SILENT
LD BC, SN76489_PORT16_LEFT
EZ80_DELAY_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
EZ80_THROTTLE_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
OUT (C), A
LD BC, SN76489_PORT16_RIGHT
OUT (C), A
LD A, CHANNEL_3_SILENT
LD BC, SN76489_PORT16_LEFT
EZ80_DELAY_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
EZ80_THROTTLE_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
OUT (C), A
LD BC, SN76489_PORT16_RIGHT
OUT (C), A
@ -200,7 +200,7 @@ SN7_PLAY:
AUDTRACE_D
AUDTRACE_CR
EZ80_DELAY_START(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
EZ80_THROTTLE_START(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
LD A, (SN7_PENDING_PERIOD + 1)
CP $FF
@ -311,7 +311,7 @@ SN7_APPLY_VOL: ; APPLY VOLUME TO BOTH LEFT AND RIGHT CHANNELS
#ENDIF
LD BC, SN76489_PORT16_LEFT
EZ80_DELAY_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
EZ80_THROTTLE_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
#IF ((SN76489CHNOUT == SNCHAN_BOTH) | (SN76489CHNOUT == SNCHAN_LEFT))
OUT (C), A
#ENDIF
@ -364,7 +364,7 @@ SN7_APPLY_PRD:
#ENDIF
LD BC, SN76489_PORT16_LEFT
EZ80_DELAY_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
EZ80_THROTTLE_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
#IF ((SN76489CHNOUT == SNCHAN_BOTH) | (SN76489CHNOUT == SNCHAN_LEFT))
OUT (C), A
#ENDIF
@ -408,7 +408,7 @@ SN7_APPLY_PRD:
#ENDIF
LD BC, SN76489_PORT16_LEFT
EZ80_DELAY_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
EZ80_THROTTLE_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
#IF ((SN76489CHNOUT == SNCHAN_BOTH) | (SN76489CHNOUT == SNCHAN_LEFT))
OUT (C), A
#ENDIF

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