31b2192f22
Implemented a shadow copy of the RTC port value to enable multiple drivers to share the port without causing side effects to other drivers that use other bits of the RTC port.
450 lines
14 KiB
NASM
450 lines
14 KiB
NASM
; The purpose of this file is to define generic symbols and to include
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; The purpose of this file is to define generic symbols and to include
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; the appropriate std-*.inc file to bring in platform specifics.
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; There are several classes of systems supported by SBC.
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; 1. SBC Z80 SBC (v1 or v2) w/ ECB interface
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; 2. ZETA Standalone Z80 SBC w/ SBC compatibility
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; 3. ZETA2 Second version of ZETA with enhanced memory bank switching
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; 4. N8 MSX-compatible Z180 SBC w/ onboard video and sound
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; 5. MK4 Mark IV Z180 based SBC w/ ECB interface
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; 6. UNA Any Z80/Z180 computer with UNA BIOS
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; 7. RCZ80 RC2014 based system with 512K banked RAM/ROM card
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; 8. RCZ180 RC2014 based system with Z180 CPU
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; 9. EZZ80 Easy Z80, Z80 SBC w/ RC2014 bus and CTC
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; All the classes require certain generic definitions, and these are
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; defined here prior to the inclusion of platform specific .inc files.
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; It is unfortunate, but all the possible config items must be defined
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; here because the config gets read before the specific std-*.inc's
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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; INCLUDE VERSION
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;
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#INCLUDE "ver.inc" ; ADD BIOSVER
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;
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FALSE .EQU 0
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TRUE .EQU ~FALSE
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;
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; DEBUGGNG OPTIONS
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;
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USENONE .EQU 0 ; NO DEBUG
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USEXIO .EQU 1 ; BASIC SERIAL DRIVER
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USEMIO .EQU 2 ; MEMORY BUFFER DRIVER
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WBWDEBUG .EQU USENONE
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;
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; PRIMARY HARDWARE PLATFORMS
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;
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PLT_SBC .EQU 1 ; SBC ECB Z80 SBC
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PLT_ZETA .EQU 2 ; ZETA Z80 SBC
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PLT_ZETA2 .EQU 3 ; ZETA Z80 V2 SBC
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PLT_N8 .EQU 4 ; N8 (HOME COMPUTER) Z180 SBC
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PLT_MK4 .EQU 5 ; MARK IV
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PLT_UNA .EQU 6 ; UNA BIOS
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PLT_RCZ80 .EQU 7 ; RC2014 W Z80
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PLT_RCZ180 .EQU 8 ; RC2014 W/ Z180
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PLT_EZZ80 .EQU 9 ; EASY Z80
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;
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#IF (PLATFORM != PLT_UNA)
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#INCLUDE "hbios.inc"
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#ENDIF
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;
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; MEMORY MANAGERS
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;
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MM_NONE .EQU 0
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MM_SBC .EQU 1 ; ORIGINAL N8VEM/RBC Z80 SBC BANKED MEMORY
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MM_Z2 .EQU 2 ; 16K X 4 BANKED MEMORY INTRODUCED ON ZETA2
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MM_N8 .EQU 3 ; Z180 CUSTOMIZED FOR N8 MEMORY EXTENSIONS
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MM_Z180 .EQU 4 ; Z180 NATIVE MEMORY MANAGER
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;
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; BOOT STYLE
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;
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BT_MENU .EQU 1 ; WAIT FOR MENU SELECTION AT LOADER PROMPT
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BT_AUTO .EQU 2 ; AUTO SELECT BOOT_DEFAULT AFTER BOOT_TIMEOUT
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;
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; FLOPPY DISK MEDIA SELECTIONS (ID'S MUST BE INDEX OF ENTRY IN FCD_TBL)
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;
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FDM720 .EQU 0 ; 3.5" FLOPPY, 720KB, 2 SIDES, 80 TRKS, 9 SECTORS
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FDM144 .EQU 1 ; 3.5" FLOPPY, 1.44MB, 2 SIDES, 80 TRKS, 18 SECTORS
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FDM360 .EQU 2 ; 5.25" FLOPPY, 360KB, 2 SIDES, 40 TRKS, 9 SECTORS
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FDM120 .EQU 3 ; 5.25" FLOPPY, 1.2MB, 2 SIDES, 80 TRKS, 15 SECTORS
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FDM111 .EQU 4 ; 8" FLOPPY, 1.11MB, 2 SIDES, 74 TRKS, 15 SECTORS
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;
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; MEDIA ID VALUES
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;
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MID_NONE .EQU 0
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MID_MDROM .EQU 1
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MID_MDRAM .EQU 2
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MID_RF .EQU 3
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MID_HD .EQU 4
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MID_FD720 .EQU 5
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MID_FD144 .EQU 6
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MID_FD360 .EQU 7
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MID_FD120 .EQU 8
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MID_FD111 .EQU 9
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;
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; DS RTC MODE SELECTIONS
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;
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DSRTCMODE_NONE .EQU 0 ; NO DSRTC
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DSRTCMODE_STD .EQU 1 ; ORIGINAL DSRTC CIRCUIT (SBC, ZETA, MK4)
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DSRTCMODE_MFPIC .EQU 2 ; MF/PIC VARIANT
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;
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; SIO MODE SELECTIONS
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;
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SIOMODE_NONE .EQU 0
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SIOMODE_RC .EQU 1 ; RC2014 SIO MODULE (SPENCER OWEN)
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SIOMODE_SMB .EQU 2 ; RC2014 SIO MODULE (SCOTT BAKER)
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SIOMODE_ZP .EQU 3 ; ECB-ZILOG PERIPHERALS BOARD
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SIOMODE_EZZ80 .EQU 4 ; EASY Z80 ON-BOARD SIO/0
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;
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; TYPE OF CONSOLE BELL TO USE
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;
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CONBELL_NONE .EQU 0
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CONBELL_PSG .EQU 1
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CONBELL_IOBIT .EQU 2
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;
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; FD MODE SELECTIONS
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;
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FDMODE_NONE .EQU 0
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FDMODE_DIO .EQU 1 ; DISKIO V1
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FDMODE_ZETA .EQU 2 ; ZETA
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FDMODE_ZETA2 .EQU 3 ; ZETA V2
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FDMODE_DIDE .EQU 4 ; DUAL IDE
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FDMODE_N8 .EQU 5 ; N8
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FDMODE_DIO3 .EQU 6 ; DISKIO V3
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FDMODE_RCSMC .EQU 7 ; RC2014 SMC 9266 @ $40 (SCOTT BAKER)
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FDMODE_RCWDC .EQU 8 ; RC2014 WDC 37C65 @ $40 (SCOTT BAKER)
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;
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; IDE MODE SELECTIONS
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;
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IDEMODE_NONE .EQU 0
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IDEMODE_DIO .EQU 1 ; DISKIO V1
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IDEMODE_DIDE .EQU 2 ; DUAL IDE
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IDEMODE_MK4 .EQU 3 ; MARK IV ONBOARD IDE (8 BIT)
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IDEMODE_RC .EQU 4 ; RC2014 CF MODULE (8 BIT) @ $10 (SPENCER OWEN)
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IDEMODE_SMB .EQU 5 ; RC2014 IDE MODULE (8 BIT) @ $E0 (SCOTT BAKER)
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;
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; PPIDE MODE SELECTIONS
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;
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PPIDEMODE_NONE .EQU 0
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PPIDEMODE_SBC .EQU 1 ; STANDARD SBC PARALLEL PORT
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PPIDEMODE_DIO3 .EQU 2 ; DISKIO V3 PARALLEL PORT
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PPIDEMODE_MFP .EQU 3 ; MULTIFUNCTION / PIC
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PPIDEMODE_N8 .EQU 4 ; MULTIFUNCTION / PIC
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PPIDEMODE_RC .EQU 5 ; RC2014 PPIDE MODULE @ $20 (ED BRINDLEY)
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;
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; SD MODE SELECTIONS
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;
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SDMODE_NONE .EQU 0
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SDMODE_JUHA .EQU 1 ; JUHA MINI BOARD
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SDMODE_N8 .EQU 2 ; N8-2511, UNMODIFIED
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SDMODE_CSIO .EQU 3 ; N8-2312 OR N8-2511 MODIFIED
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SDMODE_PPI .EQU 4 ; PPISD MINI BOARD
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SDMODE_UART .EQU 5 ; SD INTERFACE VIA UART
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SDMODE_DSD .EQU 6 ; DUAL SD
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SDMODE_MK4 .EQU 7 ; MARK IV
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SDMODE_SC126 .EQU 8 ; SC126
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;
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; SERIAL DEVICE CONFIGURATION CONSTANTS
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;
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SER_DATA5 .EQU 0 << 0
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SER_DATA6 .EQU 1 << 0
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SER_DATA7 .EQU 2 << 0
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SER_DATA8 .EQU 3 << 0
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;
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SER_PARNONE .EQU 0 << 3
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SER_PARODD .EQU 1 << 3
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SER_PAREVEN .EQU 3 << 3
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SER_PARMARK .EQU 5 << 3
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SER_PARSPACE .EQU 7 << 3
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;
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SER_STOP1 .EQU 0 << 2
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SER_STOP2 .EQU 1 << 2
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;
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; SERIAL BAUD RATES ENCODED AS V = 75 * 2^X * 3^Y
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; AND STORED AS 5 BITS: YXXXX
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;
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SER_BAUD75 .EQU $00 << 8
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SER_BAUD150 .EQU $01 << 8
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SER_BAUD300 .EQU $02 << 8
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SER_BAUD600 .EQU $03 << 8
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SER_BAUD1200 .EQU $04 << 8
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SER_BAUD2400 .EQU $05 << 8
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SER_BAUD4800 .EQU $06 << 8
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SER_BAUD9600 .EQU $07 << 8
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SER_BAUD19200 .EQU $08 << 8
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SER_BAUD38400 .EQU $09 << 8
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SER_BAUD76800 .EQU $0A << 8
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SER_BAUD153600 .EQU $0B << 8
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SER_BAUD307200 .EQU $0C << 8
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SER_BAUD614400 .EQU $0D << 8
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SER_BAUD1228800 .EQU $0E << 8
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SER_BAUD2457600 .EQU $0F << 8
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SER_BAUD225 .EQU $10 << 8
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SER_BAUD450 .EQU $11 << 8
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SER_BAUD900 .EQU $12 << 8
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SER_BAUD1800 .EQU $13 << 8
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SER_BAUD3600 .EQU $14 << 8
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SER_BAUD7200 .EQU $15 << 8
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SER_BAUD14400 .EQU $16 << 8
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SER_BAUD28800 .EQU $17 << 8
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SER_BAUD57600 .EQU $18 << 8
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SER_BAUD115200 .EQU $19 << 8
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SER_BAUD230400 .EQU $1A << 8
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SER_BAUD460800 .EQU $1B << 8
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SER_BAUD921600 .EQU $1C << 8
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SER_BAUD1843200 .EQU $1D << 8
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SER_BAUD3686400 .EQU $1E << 8
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SER_BAUD7372800 .EQU $1F << 8
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;
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SER_XON .EQU 1 << 6
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SER_DTR .EQU 1 << 7
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SER_RTS .EQU 1 << 13
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;
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SER_75_8N1 .EQU SER_BAUD75 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_150_8N1 .EQU SER_BAUD150 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_300_8N1 .EQU SER_BAUD300 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_600_8N1 .EQU SER_BAUD600 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_1200_8N1 .EQU SER_BAUD1200 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_2400_8N1 .EQU SER_BAUD2400 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_4800_8N1 .EQU SER_BAUD4800 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_9600_8N1 .EQU SER_BAUD9600 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_19200_8N1 .EQU SER_BAUD19200 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_38400_8N1 .EQU SER_BAUD38400 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_76800_8N1 .EQU SER_BAUD76800 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_153600_8N1 .EQU SER_BAUD153600 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_307200_8N1 .EQU SER_BAUD307200 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_614400_8N1 .EQU SER_BAUD614400 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_1228800_8N1 .EQU SER_BAUD1228800 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_2457600_8N1 .EQU SER_BAUD2457600 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_225_8N1 .EQU SER_BAUD225 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_450_8N1 .EQU SER_BAUD450 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_900_8N1 .EQU SER_BAUD900 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_1800_8N1 .EQU SER_BAUD1800 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_3600_8N1 .EQU SER_BAUD3600 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_7200_8N1 .EQU SER_BAUD7200 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_14400_8N1 .EQU SER_BAUD14400 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_28800_8N1 .EQU SER_BAUD28800 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_57600_8N1 .EQU SER_BAUD57600 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_115200_8N1 .EQU SER_BAUD115200 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_230400_8N1 .EQU SER_BAUD230400 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_460800_8N1 .EQU SER_BAUD460800 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_921600_8N1 .EQU SER_BAUD921600 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_1843200_8N1 .EQU SER_BAUD1843200 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_3686400_8N1 .EQU SER_BAUD3686400 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_7372800_8N1 .EQU SER_BAUD7372800 | SER_DATA8 | SER_PARNONE | SER_STOP1
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;
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; ECB-VDU MODES
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;
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V80X24 .EQU 0
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V80X25 .EQU 1
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V80X30 .EQU 2
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V80X25B .EQU 3
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V80X24B .EQU 4
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;
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; KEYBOARD LAYOUTS
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;
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KBD_US .EQU 0 ; US ENGLISH
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KBD_DE .EQU 1 ; GERMAN
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;
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; INTERRUPT VECTOR TABLE ENTRY OFFSETS (Z180 COMPATIBLE)
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;
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IVT_INT1 .EQU 0
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IVT_INT2 .EQU 2
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IVT_TIM0 .EQU 4
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IVT_TIM1 .EQU 6
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IVT_DMA0 .EQU 8
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IVT_DMA1 .EQU 10
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IVT_CSIO .EQU 12
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IVT_SER0 .EQU 14
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IVT_SER1 .EQU 16
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IVT_PIO0 .EQU 18
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IVT_PIO1 .EQU 20
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IVT_PIO2 .EQU 22
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IVT_PIO3 .EQU 24
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;
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#INCLUDE "build.inc" ; INCLUDE USER CONFIG, ADD VARIANT, TIMESTAMP, & ROMSIZE
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;
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#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
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#DEFINE CPU_Z180
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#ELSE
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#DEFINE CPU_Z80
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#ENDIF
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;
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; SET PLATFORM NAME STRING
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;
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#IF (PLATFORM == PLT_SBC)
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#DEFINE PLATFORM_NAME "SBC"
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#ENDIF
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#IF (PLATFORM == PLT_ZETA)
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#DEFINE PLATFORM_NAME "ZETA"
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#ENDIF
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#IF (PLATFORM == PLT_ZETA2)
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#DEFINE PLATFORM_NAME "ZETA V2"
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#ENDIF
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#IF (PLATFORM == PLT_N8)
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#DEFINE PLATFORM_NAME "N8"
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#ENDIF
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#IF (PLATFORM == PLT_MK4)
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#DEFINE PLATFORM_NAME "MARK IV"
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#ENDIF
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#IF (PLATFORM == PLT_UNA)
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#DEFINE PLATFORM_NAME "UNA"
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#ENDIF
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#IF (PLATFORM == PLT_RCZ80)
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#DEFINE PLATFORM_NAME "RC2014"
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#ENDIF
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#IF (PLATFORM == PLT_RCZ180)
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#DEFINE PLATFORM_NAME "RC2014"
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#ENDIF
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#IF (PLATFORM == PLT_EZZ80)
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#DEFINE PLATFORM_NAME "EASY"
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#ENDIF
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;
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; INCLUDE PLATFORM SPECIFIC HARDWARE DEFINITIONS
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;
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#IF (PLATFORM == PLT_SBC)
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#INCLUDE "plt_sbc.inc"
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#ENDIF
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;
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#IF (PLATFORM == PLT_ZETA)
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#INCLUDE "plt_zeta.inc"
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#ENDIF
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;
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#IF (PLATFORM == PLT_ZETA2)
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#INCLUDE "plt_zeta2.inc"
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#ENDIF
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;
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#IF (PLATFORM == PLT_N8)
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#INCLUDE "plt_n8.inc"
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#ENDIF
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;
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#IF (PLATFORM == PLT_MK4)
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#INCLUDE "plt_mk4.inc"
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#ENDIF
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;
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#IF (PLATFORM == PLT_UNA)
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#INCLUDE "plt_una.inc"
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#ENDIF
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;
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#IF (PLATFORM == PLT_RCZ80)
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#INCLUDE "plt_rcz80.inc"
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#ENDIF
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;
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#IF (PLATFORM == PLT_RCZ180)
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#INCLUDE "plt_rcz180.inc"
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#ENDIF
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;
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#IF (PLATFORM == PLT_EZZ80)
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#INCLUDE "plt_ezz80.inc"
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#ENDIF
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;
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; SETUP DEFAULT CPU SPEED VALUES
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;
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CPUKHZ .EQU CPUOSC / 1000 ; CPU FREQ IN KHZ
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;
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#IFDEF CPU_Z180
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#IF (Z180_CLKDIV == 0)
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CPUKHZ .SET CPUKHZ / 2 ; ADJUST FOR HALF SPEED OPERATION
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#ENDIF
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#IF (Z180_CLKDIV == 2)
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CPUKHZ .SET CPUKHZ * 2 ; ADJUST FOR DOUBLE SPEED OPERATION
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#ENDIF
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#ENDIF
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;
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CPUMHZ .EQU CPUKHZ / 1000 ; CPU FREQ IN MHZ
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;
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; MEMORY BANK CONFIGURATION
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;
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#IF (PLATFORM == PLT_UNA)
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BID_ROM0 .EQU $0000
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BID_RAM0 .EQU $8000
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#ELSE
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BID_ROM0 .EQU $00
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BID_RAM0 .EQU $80
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#ENDIF
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BID_ROMN .EQU (BID_ROM0 + ((ROMSIZE / 32) - 1))
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BID_RAMN .EQU (BID_RAM0 + ((RAMSIZE / 32) - 1))
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BID_BOOT .EQU BID_ROM0 ; BOOT BANK
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;BID_BIOSIMG .EQU BID_ROM0 + 1 ; BIOS IMAGE BANK
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;BID_OSIMG .EQU BID_ROM0 + 2 ; ROM LOADER AND IMAGES BANK
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BID_IMG0 .EQU BID_ROM0 + 1 ; ROM LOADER AND FIRST IMAGES BANK
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BID_IMG1 .EQU BID_ROM0 + 2 ; SECOND IMAGES BANK
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BID_FSFAT .EQU BID_ROM0 + 3 ; FAT FILESYSTEM DRIVER BANK
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BID_ROMD0 .EQU BID_ROM0 + 4 ; FIRST ROM DRIVE BANK
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BID_ROMDN .EQU BID_ROMN ; LAST ROM DRIVE BANK
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BID_RAMD0 .EQU BID_RAM0 ; FIRST RAM DRIVE BANK
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BID_RAMDN .EQU BID_RAMN - 4 ; LAST RAM DRIVE BANK
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BID_AUX .EQU BID_RAMN - 3 ; AUX BANK (BPBIOS, ETC.)
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BID_BIOS .EQU BID_RAMN - 2 ; BIOS BANK
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BID_USR .EQU BID_RAMN - 1 ; USER BANK (CP/M TPA, ETC.)
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BID_COM .EQU BID_RAMN ; COMMON BANK, UPPER 32K
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;
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; MEMORY LAYOUT
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;
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SYS_SIZ .EQU $3000 ; COMBINED SIZE OF SYSTEM AREA (OS + HBIOS PROXY)
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HBBUF_SIZ .EQU 1024 ; INVARIANT HBIOS PHYSICAL DISK BUFFER, 1K
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HBX_SIZ .EQU $200 ; HBIOS PROXY SIZE (SUBJECT TO CHANGE)
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CPM_SIZ .EQU SYS_SIZ - HBX_SIZ ; NET SIZE OF ALL OS COMPONENTS (EXCLUDING HBIOS PROXY)
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CCP_SIZ .EQU $800 ; INVARIANT SIZE OF CCP
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|
BDOS_SIZ .EQU $E00 ; INVARIANT SIZE OF BDOS
|
|
CBIOS_SIZ .EQU CPM_SIZ - CCP_SIZ - BDOS_SIZ ; CBIOS IS THE REMAINDER
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|
|
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MEMTOP .EQU $10000 ; INVARIANT TOP OF Z80 ADDRESSABLE MEMORY
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BNKTOP .EQU $8000 ; BANK MEMORY BARRIER
|
|
|
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HBX_IMG .EQU $200 ; LOC OF HBX IMAGE IN HBIOS IMAGE BANK
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|
|
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HBBUF_END .EQU BNKTOP ; END OF PHYSICAL DISK BUFFER IN HBIOS
|
|
HBBUF_LOC .EQU HBBUF_END - HBBUF_SIZ ; START OF PHYSICAL DISK BUFFER
|
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HBX_END .EQU MEMTOP ; END OF HBIOS PROXY
|
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HBX_LOC .EQU HBX_END - HBX_SIZ ; START OF HBIOS PROXY
|
|
CPM_END .EQU HBX_LOC ; END OF CPM COMPONENTS (INCLUDING CBIOS)
|
|
CPM_LOC .EQU CPM_END - CPM_SIZ ; START OF CPM COMPONENTS
|
|
CBIOS_END .EQU HBX_LOC ; END OF CBIOS
|
|
CBIOS_LOC .EQU CBIOS_END - CBIOS_SIZ ; START OF CBIOS
|
|
|
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CPM_ENT .EQU CBIOS_LOC ; CPM ENTRY POINT (IN CBIOS)
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|
|
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LDR_SIZ .EQU $0E00
|
|
|
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MON_LOC .EQU $C000 ; LOCATION OF MONITOR FOR RUNNING SYSTEM
|
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MON_SIZ .EQU $1000 ; SIZE OF MONITOR BINARY IMAGE
|
|
MON_END .EQU MON_LOC + MON_SIZ ; END OF MONITOR
|
|
|
|
BAS_LOC .EQU $0200 ; NASCOM BASIC
|
|
BAS_SIZ .EQU $2000
|
|
BAS_END .EQU BAS_LOC + BAS_SIZ
|
|
|
|
TBC_LOC .EQU $0A00 ; TASTYBASIC
|
|
TBC_SIZ .EQU $0900
|
|
TBC_END .EQU TBC_LOC + TBC_SIZ
|
|
|
|
EGG_LOC .EQU $0A00 ; EASTER EGG
|
|
EGG_SIZ .EQU $0200
|
|
EGG_END .EQU EGG_LOC + EGG_SIZ
|
|
|
|
FTH_LOC .EQU $0200 ; CAMEL FORTH
|
|
FTH_SIZ .EQU $1700
|
|
FTH_END .EQU FTH_LOC + FTH_SIZ
|
|
|
|
MON_DSKY .EQU MON_LOC + (0 * 3) ; MONITOR ENTRY (DSKY)
|
|
MON_SERIAL .EQU MON_LOC + (1 * 3) ; MONITOR ENTRY (SERIAL PORT)
|
|
;
|
|
; HELPER MACROS
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|
;
|
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#DEFINE PRTC(C) CALL PRTCH \ .DB C ; PRINT CHARACTER C TO CONSOLE - PRTC('X')
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#DEFINE PRTS(S) CALL PRTSTRD \ .TEXT S ; PRINT STRING S TO CONSOLE - PRTD("HELLO")
|
|
#DEFINE PRTX(X) CALL PRTSTRI \ .DW X ; PRINT STRING AT ADDRESS X TO CONSOLE - PRTI(STR_HELLO)
|
|
;
|
|
#DEFINE XIO_PRTC(C) CALL XIO_PRTCH \ .DB C ; PRINT CHARACTER C TO CONSOLE - PRTC('X')
|
|
#DEFINE XIO_PRTS(S) CALL XIO_PRTSTRD \ .DB S ; PRINT STRING S TO CONSOLE - PRTD("HELLO")
|
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#DEFINE XIO_PRTX(X) CALL XIO_PRTSTRI \ .DW X ; PRINT STRING AT ADDRESS X TO CONSOLE - PRTI(STR_HELLO)
|