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87 lines
3.4 KiB
87 lines
3.4 KiB
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; Z280 CPU CONTROL REGISTERS (VIA LDCTL)
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Z280_MSR .EQU $00 ; MASTER STATUS REG
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Z280_ISR .EQU $16 ; INTERRUPT STATUS REG
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Z280_VPR .EQU $06 ; INT/TRAP VECT PTR REG
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Z280_IOPR .EQU $08 ; I/O PAGE REG
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Z280_BTIR .EQU $FF ; BUS TIMING & INIT REG
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Z280_BTCR .EQU $02 ; BUS TIMING & CONTROL REG
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Z280_SLR .EQU $04 ; STACK LIMIT REG
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Z280_TCR .EQU $10 ; TRAP CONTROL REG
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Z280_CCR .EQU $12 ; CACHE CONTROL REG
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Z280_LAR .EQU $14 ; LOCAL ADDRESS REG
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; Z280 PAGE $FF REGSISTER ADDRESSES
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Z280_RRR .EQU $E8 ; Z280 REFRESH RATE REG
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Z280_MMUMCR .EQU $F0 ; Z280 MMU MASTER CONTROL REG
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Z280_MMUPDRPTR .EQU $F1 ; Z280 MMU PDR POINTER REG
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Z280_MMUINV .EQU $F2 ; Z280 MMU INVALIDATION PORT
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Z280_MMUBLKMOV .EQU $F4 ; Z280 MMU BLOCK MOVE PORT
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Z280_MMUPDR .EQU $F5 ; Z280 MMU PDR PORT
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Z280_DMA0_DSTL .EQU $00 ; DMA0 DESTINATION ADDRESS LOW
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Z280_DMA0_DSTH .EQU $01 ; DMA0 DESTINATION ADDRESS HIGH
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Z280_DMA0_SRCL .EQU $02 ; DMA0 SOURCE ADDRESS LOW
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Z280_DMA0_SRCH .EQU $03 ; DMA0 SOURCE ADDRESS HIGH
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Z280_DMA0_CNT .EQU $04 ; DMA0 COUNT
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Z280_DMA0_TDR .EQU $05 ; DMA0 TRANSACTION DESCRIPTION REG
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Z280_DMA1_DSTL .EQU $08 ; DMA1 DESTINATION ADDRESS LOW
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Z280_DMA1_DSTH .EQU $09 ; DMA1 DESTINATION ADDRESS HIGH
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Z280_DMA1_SRCL .EQU $0A ; DMA1 SOURCE ADDRESS LOW
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Z280_DMA1_SRCH .EQU $0B ; DMA1 SOURCE ADDRESS HIGH
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Z280_DMA1_CNT .EQU $0C ; DMA1 COUNT
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Z280_DMA1_TDR .EQU $0D ; DMA1 TRANSACTION DESCRIPTION REG
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Z280_DMA2_DSTL .EQU $10 ; DMA2 DESTINATION ADDRESS LOW
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Z280_DMA2_DSTH .EQU $11 ; DMA2 DESTINATION ADDRESS HIGH
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Z280_DMA2_SRCL .EQU $12 ; DMA2 SOURCE ADDRESS LOW
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Z280_DMA2_SRCH .EQU $13 ; DMA2 SOURCE ADDRESS HIGH
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Z280_DMA2_CNT .EQU $14 ; DMA2 COUNT
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Z280_DMA2_TDR .EQU $15 ; DMA2 TRANSACTION DESCRIPTION REG
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Z280_DMA3_DSTL .EQU $18 ; DMA3 DESTINATION ADDRESS LOW
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Z280_DMA3_DSTH .EQU $19 ; DMA3 DESTINATION ADDRESS HIGH
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Z280_DMA3_SRCL .EQU $1A ; DMA3 SOURCE ADDRESS LOW
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Z280_DMA3_SRCH .EQU $1B ; DMA3 SOURCE ADDRESS HIGH
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Z280_DMA3_CNT .EQU $1C ; DMA3 COUNT
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Z280_DMA3_TDR .EQU $1D ; DMA3 TRANSACTION DESCRIPTION REG
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; Z280 PAGE $FE REGSISTER ADDRESSES
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Z280_UARTCFG .EQU $10 ; UART CONFIG REG
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Z280_UARTXCTL .EQU $12 ; UART TRANSMIT CONTROL/STATUS REG
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Z280_UARTRCTL .EQU $14 ; UART RECEIVE CONTROL/STATUS REG
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Z280_UARTRECV .EQU $16 ; UART RECEIVE DATA REG
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Z280_UARTXMIT .EQU $18 ; UART TRANSMIT DATA REG
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Z280_CT0_CFG .EQU $E0 ; COUNTER/TIMER 0 CONFIG REG
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Z280_CT0_CMDST .EQU $E1 ; COUNTER/TIMER 0 COMMAND/STATUS REG
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Z280_CT0_TC .EQU $E2 ; COUNTER/TIMER 0 TIME CONSTANT
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Z280_CT0_CT .EQU $E3 ; COUNTER/TIMER 0 COUNT TIME
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Z280_CT1_CFG .EQU $E8 ; COUNTER/TIMER 1 CONFIG REG
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Z280_CT1_CMDST .EQU $E9 ; COUNTER/TIMER 1 COMMAND/STATUS REG
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Z280_CT1_TC .EQU $EA ; COUNTER/TIMER 1 TIME CONSTANT
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Z280_CT1_CT .EQU $EB ; COUNTER/TIMER 1 COUNT TIME
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Z280_CT2_CFG .EQU $F8 ; COUNTER/TIMER 2 CONFIG REG
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Z280_CT2_CMDST .EQU $F9 ; COUNTER/TIMER 2 COMMAND/STATUS REG
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Z280_CT2_TC .EQU $FA ; COUNTER/TIMER 2 TIME CONSTANT
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Z280_CT2_CT .EQU $FB ; COUNTER/TIMER 2 COUNT TIME
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; Z280 INSTRUCTIONS (INCOMPLETE, JUST THE ONES USED)
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.ADDINSTR PCACHE "" 65ED 2 NOP 1
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.ADDINSTR LDCTL (C),HL 6EED 2 NOP 1
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.ADDINSTR LDCTL HL,(C) 66ED 2 NOP 1
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.ADDINSTR IM 3 4EED 2 NOP 1
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.ADDINSTR LDCTL USP,HL 8FED 2 NOP 1
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.ADDINSTR LDCTL IY,(C) 66EDFD 3 NOP 1
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.ADDINSTR LDCTL (C),IY 6EEDFD 3 NOP 1
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.ADDINSTR MULTU A,* F9EDFD 4 NOP 1
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.ADDINSTR LD2 HL,(HL) 26ED 2 NOP 1
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.ADDINSTR LD2 (HL),DE 1EED 2 NOP 1
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