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Add SC126 Platform

pull/48/head
Wayne Warthen 7 years ago
parent
38820a4f89
commit
09044d1959
36 changed files with 460 additions and 147 deletions
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  1. 3
      Doc/ChangeLog.txt
  2. 2
      ReadMe.txt
  3. 10
      Source/Apps/RTC.asm
  4. 76
      Source/Apps/Tune/Tune.asm
  5. 129
      Source/Apps/XM/xmhb.180
  6. 2
      Source/CBIOS/ver.inc
  7. 16
      Source/HBIOS/Build.ps1
  8. 6
      Source/HBIOS/Config/SC126_std.asm
  9. 29
      Source/HBIOS/ay.asm
  10. 1
      Source/HBIOS/cfg_ezz80.asm
  11. 2
      Source/HBIOS/cfg_mk4.asm
  12. 2
      Source/HBIOS/cfg_n8.asm
  13. 1
      Source/HBIOS/cfg_rcz180.asm
  14. 1
      Source/HBIOS/cfg_rcz80.asm
  15. 2
      Source/HBIOS/cfg_sbc.asm
  16. 115
      Source/HBIOS/cfg_sc126.asm
  17. 11
      Source/HBIOS/dbgmon.asm
  18. 2
      Source/HBIOS/dsrtc.asm
  19. 26
      Source/HBIOS/hbios.asm
  20. 2
      Source/HBIOS/plt_ezz80.inc
  21. 2
      Source/HBIOS/plt_mk4.inc
  22. 2
      Source/HBIOS/plt_n8.inc
  23. 2
      Source/HBIOS/plt_rcz180.inc
  24. 2
      Source/HBIOS/plt_rcz80.inc
  25. 2
      Source/HBIOS/plt_sbc.inc
  26. 12
      Source/HBIOS/plt_sc126.inc
  27. 1
      Source/HBIOS/plt_una.inc
  28. 3
      Source/HBIOS/plt_zeta.inc
  29. 2
      Source/HBIOS/plt_zeta2.inc
  30. 22
      Source/HBIOS/romldr.asm
  31. 2
      Source/HBIOS/sd.asm
  32. 81
      Source/HBIOS/std.asm
  33. 20
      Source/HBIOS/tms.asm
  34. 4
      Source/HBIOS/uart.asm
  35. 10
      Source/HBIOS/util.asm
  36. 2
      Source/HBIOS/ver.inc

3
Doc/ChangeLog.txt
View File

@ -7,6 +7,9 @@ Version 2.9.2
- WBW: Support two SIO modules w/ auto-detection
- PMS: Support ECB USB-FIFO board
- WBW: Fixed ASSIGN issue with incorrect DPB selection
- WBW: Add RC2014 Z180 AY sound support to TUNE app
- WBW: Add RC2014 AY sound support to AY driver
- WBW: Add SC126 platform
Version 2.9.1
-------------

2
ReadMe.txt
View File

@ -7,7 +7,7 @@
***********************************************************************
Wayne Warthen (wwarthen@gmail.com)
Version 2.9.2-pre.3, 2019-08-07
Version 2.9.2-pre.4, 2019-08-11
https://www.retrobrewcomputers.org/
RomWBW is a ROM-based implementation of CP/M-80 2.2 and Z-System for

10
Source/Apps/RTC.asm
View File

@ -21,6 +21,8 @@
;
;[2019/06/21] v1.3 Finalized RC2014 Z180 support.
;
;[2019/08/11] v1.4 Support SC126 platform.
;
;
; Constants
;
@ -34,6 +36,7 @@ PORT_N8 .EQU $88 ; RTC port for N8
PORT_MK4 .EQU $8A ; RTC port for MK4
PORT_RCZ80 .EQU $C0 ; RTC port for RC2014
PORT_RCZ180 .EQU $0C ; RTC port for RC2014
PORT_SC126 .EQU $0C ; RTC port for SBC126
PORT_EZZ80 .EQU $C0 ; RTC port for EZZ80 (actually does not have one!!!)
BDOS .EQU 5 ; BDOS invocation vector
@ -1078,6 +1081,10 @@ HINIT:
LD DE,PLT_RCZ180
CP $08 ; RC2014 w/ Z180
JR Z,RTC_INIT2
LD C,PORT_SC126
LD DE,PLT_SC126
CP $0A ; SC126
JR Z,RTC_INIT2
;LD C,PORT_EZZ80
;LD DE,PLT_EZZ80
;CP $09 ; Easy Z80
@ -1545,7 +1552,7 @@ TESTING_BIT_DELAY_OVER:
RTC_HELP_MSG:
.DB 0Ah, 0Dh ; line feed and carriage return
.TEXT "RTC: Version 1.3"
.TEXT "RTC: Version 1.4"
.DB 0Ah, 0Dh ; line feed and carriage return
.TEXT "Commands: E)xit T)ime st(A)rt S)et R)aw L)oop C)harge N)ocharge D)elay I)nit G)et P)ut B)oot H)elp"
.DB 0Ah, 0Dh ; line feed and carriage return
@ -1668,6 +1675,7 @@ PLT_N8 .TEXT ", N8 RTC Latch Port 0x88\r\n$"
PLT_MK4 .TEXT ", Mark 4 RTC Latch Port 0x8A\r\n$"
PLT_RCZ80 .TEXT ", RC2014 Z80 RTC Module Latch Port 0xC0\r\n$"
PLT_RCZ180 .TEXT ", RC2014 Z180 RTC Module Latch Port 0x0C\r\n$"
PLT_SC126 .TEXT ", SC126 Z180 RTC Module Latch Port 0x0C\r\n$"
PLT_EZZ80 .TEXT ", Easy Z80 RTC Module Latch Port 0xC0\r\n$"
;

76
Source/Apps/Tune/Tune.asm
View File

@ -83,12 +83,18 @@ TYPMYM .EQU 3 ; FILTYP value for MYM sound file
; Use platform id to derive port addresses
LD A,L ; Platform ID is still in L from above
LD C,L ; Save platform id in C for now
LD HL,$D0D8 ; For RC2014, RSEL=D8, RDAT=D0
LD DE,MSGRC ; Message for RC2014 platform
CP 7 ; RC2014?
LD HL,$D0D8 ; For RC2014 Z80, RSEL=D8, RDAT=D0
LD DE,MSGRCZ80 ; Message for RC2014 Z80 platform
CP 7 ; RC2014 Z80?
JR Z,_SETP ; If so, set ports
LD DE,MSGEZ ; Message for Easy Z80 platform
CP 9 ; Easy Z80?
LD HL,$6068 ; For RC2014 Z180, RSEL=D8, RDAT=D0
LD DE,MSGRCZ180 ; Message for RC2014 Z180 platform
CP 8 ; RC2014 Z80?
JR Z,_SETP ; If so, set ports
LD DE,MSGSC126 ; Message for SC126 Z180 platform
CP 10 ; SC126?
JR Z,_SETP ; If so, same ports as RC2014
LD HL,$9D9C ; For N8, RSEL=9C, RDAT=9D
LD DE,MSGN8 ; Message for N8 platform
@ -590,37 +596,39 @@ ERR2: ; without the string
CALL CRLF ; print newline
JP 0 ; fast exit
QDLY .DW 0 ; quark delay factor
WMOD .DB 0 ; delay mode, non-zero to use timer
DCSAV .DB 0 ; for saving Z180 DCNTL value
DMA .DW 0 ; Working DMA
FILTYP .DB 0 ; Sound file type (TYPPT2, TYPPT3, TYPMYM)
TMP .DB 0 ; work around use of undocumented Z80
PORTS:
RSEL .DB 0 ; Register selection port
RDAT .DB 0 ; Register data port
MSGBAN .DB "Tune Player for RomWBW v2.0, 28-Jan-2018",0
MSGUSE .DB "Copyright (C) 2018, Wayne Warthen, GNU GPL v3",13,10
.DB "PTxPlayer Copyright (C) 2004-2007 S.V.Bulba",13,10
.DB "MYMPlay by Marq/Lieves!Tuore",13,10,13,10
.DB "Usage: TUNE <filename>.[PT2|PT3|MYM]",0
MSGBIO .DB "Incompatible BIOS or version, "
.DB "HBIOS v", '0' + RMJ, ".", '0' + RMN, " required",0
MSGHW .DB "Hardware error, sound chip not detected!",0
MSGNAM .DB "Sound filename invalid (must be .PT2, .PT3, or .MYM)",0
MSGFIL .DB "Sound file not found!",0
MSGSIZ .DB "Sound file too large to load!",0
MSGRC .DB "RC2014 w/ Ed Brindley Sound Module",0
MSGEZ .DB "Easy Z80 w/ Ed Brindley Sound Module",0
MSGN8 .DB "RetroBrew N8 Onboard Sound System",0
MSGSCG .DB "RetroBrew SCG ECB Adapter Sound System",0
MSGTIM .DB ", timer mode",0
MSGDLY .DB ", delay mode",0
MSGPLY .DB "Playing...",0
MSGEND .DB " Done",0
QDLY .DW 0 ; quark delay factor
WMOD .DB 0 ; delay mode, non-zero to use timer
DCSAV .DB 0 ; for saving Z180 DCNTL value
DMA .DW 0 ; Working DMA
FILTYP .DB 0 ; Sound file type (TYPPT2, TYPPT3, TYPMYM)
TMP .DB 0 ; work around use of undocumented Z80
PORTS:
RSEL .DB 0 ; Register selection port
RDAT .DB 0 ; Register data port
MSGBAN .DB "Tune Player for RomWBW v2.1, 11-Aug-2019",0
MSGUSE .DB "Copyright (C) 2019, Wayne Warthen, GNU GPL v3",13,10
.DB "PTxPlayer Copyright (C) 2004-2007 S.V.Bulba",13,10
.DB "MYMPlay by Marq/Lieves!Tuore",13,10,13,10
.DB "Usage: TUNE <filename>.[PT2|PT3|MYM]",0
MSGBIO .DB "Incompatible BIOS or version, "
.DB "HBIOS v", '0' + RMJ, ".", '0' + RMN, " required",0
MSGHW .DB "Hardware error, sound chip not detected!",0
MSGNAM .DB "Sound filename invalid (must be .PT2, .PT3, or .MYM)",0
MSGFIL .DB "Sound file not found!",0
MSGSIZ .DB "Sound file too large to load!",0
MSGRCZ80 .DB "RC2014 Z80 w/ Ed Brindley Sound Module",0
MSGRCZ180 .DB "RC2014 Z180 w/ Ed Brindley Sound Module",0
MSGSC126 .DB "SC126 Z180 w/ Ed Brindley Sound Module",0
MSGEZ .DB "Easy Z80 w/ Ed Brindley Sound Module",0
MSGN8 .DB "RetroBrew N8 Onboard Sound System",0
MSGSCG .DB "RetroBrew SCG ECB Adapter Sound System",0
MSGTIM .DB ", timer mode",0
MSGDLY .DB ", delay mode",0
MSGPLY .DB "Playing...",0
MSGEND .DB " Done",0
;
;===============================================================================
; PTx Player Routines

129
Source/Apps/XM/xmhb.180
View File

@ -135,6 +135,8 @@ MINIT1:
JR Z,ARCINIT ; Handle RC2014 w/ Z180
CP 9 ; Check for Easy Z80
JR Z,RCINIT ; Treat same as RC2014 for now
CP 10 ; Check for SC126 w/ Z180
JR Z,ARCINIT ; Handle SC126 w/ Z180
;
; Check for Z180 which implies ASCI serial port
LD DE,00202H ; D := 2, E := 2
@ -152,6 +154,17 @@ MINIT2:
JR MINIT3 ; Complete the initialization
;
RCINIT:
;; RC2014, use SIO
;; Suppress interrupts
;LD A,01H ; WR1
;OUT (S_CTLP),A ; Select WR1
;XOR A ; No interrupts
;OUT (S_CTLP),A ; Do it
;; Setup JP table
;LD HL,SIO_JPTBL ; HBIOS jump table address
;LD DE,SIO ; HBIOS console notification string
;JR MINIT3 ; Complete the initialization
; RC2014, use HBIOS calls
LD HL,1250 ; Smaller receive loop tiemout scalar
LD (RCVSCL),HL ; ... to compensate for BIOS overhead
@ -232,11 +245,12 @@ PLTID DB 0 ; Platform ID
CPUSPD DB 10 ; CPU speed in MHz
RCVSCL DW 2800 ; RECV loop timeout scalar
;
RBC DB "RBC, 06-Jun-2018$"
RBC DB "RBC, 11-Aug-2019$"
;
UART DB ", UART0$"
ASCI DB ", ASCI0$"
ASCIRC DB ", ASCI0 (RC2014)$"
SIO DB ", SIO$"
COMX DB ", COM0$"
;
UBTAG DB " [UNA]$"
@ -251,6 +265,15 @@ BIOERR DB 13, 10, 13, 10, "++ Unknown BIOS ++", 13, 10, "$"
; Uninitialize modem
;
UNINIT:
LD A,(BIOID)
CP 1 ; Is HBIOS?
RET NZ ; If not, just return
; Reset character device 0
LD B,04H ; HBIOS CIOINIT function 0x04
LD C,0 ; Unit = 0
LD DE,-1 ; Reset w/ current settings
RST 08 ; Do it
RET ; not initialized, so no 'UN-INITIALIZE'
;
;-----------------------------------------------------------------------
@ -318,7 +341,7 @@ U_SENDR:
;
;-----------------------------------------------------------------------
;
; Test and rep;ort carrier status, Z set if carrier present
; Test and report carrier status, Z set if carrier present
;
U_CAROK:
XOR A ; not used, always indicate present
@ -433,7 +456,7 @@ A_SENDR:
;
;-----------------------------------------------------------------------
;
; Test and rep;ort carrier status, Z set if carrier present
; Test and report carrier status, Z set if carrier present
;
A_CAROK:
XOR A ; not used, always indicate present
@ -538,7 +561,7 @@ AR_SENDR:
;
;-----------------------------------------------------------------------
;
; Test and rep;ort carrier status, Z set if carrier present
; Test and report carrier status, Z set if carrier present
;
AR_CAROK:
XOR A ; not used, always indicate present
@ -566,7 +589,7 @@ AR_RCVRDY:
AND A_FRME | A_OVRE | A_PARE ; isolate line err bits
LD B,A ; save err status in B
; Z180 ASCI ports will stall if there are errors.
; Z8S180 Rev. N ASCI ports will stall if there are line errors.
; Error bits are NOT cleared by merely reading
; the status register. Below, bit 3 of ASCI
; control register is written with a zero to
@ -605,6 +628,100 @@ AR_SPEED:
;=======================================================================
;=======================================================================
;
; Standard RBC Projects SIO port @ 80H
;
;=======================================================================
;=======================================================================
;
; SIO port constants
;
S_BASE EQU 80H ; SIO base port
S_DATP EQU S_BASE + 1 ; data in port
S_DATO EQU S_BASE + 1 ; data out port
S_CTLP EQU S_BASE + 0 ; control/status port
S_SNDB EQU 04H ; bit to test for send ready
S_SNDR EQU 04H ; value when ready to send
S_RCVB EQU 01H ; bit to test for receive ready
S_RCVR EQU 01H ; value when ready to receive
;
; Following jump table is dynamically patched into real jump
; table at program startup. See MINIT above. Note that only a
; subset of the jump table is overlaid (SENDR to SPEED).
;
SIO_JPTBL:
JP S_SENDR ; send character (via pop psw)
JP S_CAROK ; test for carrier
JP S_MDIN ; receive data byte
JP S_GETCHR ; get character from modem
JP S_RCVRDY ; check receive ready
JP S_SNDRDY ; check send ready
JP S_SPEED ; get speed value for file transfer time
;
;-----------------------------------------------------------------------
;
; Send character on top of stack
;
S_SENDR:
POP AF ; get character to send from stack
OUT (S_DATO),A ; send to port
RET
;
;-----------------------------------------------------------------------
;
; Test and report carrier status, Z set if carrier present
;
S_CAROK:
XOR A ; not used, always indicate present
RET
;
;-----------------------------------------------------------------------
;
; Get a character (assume character ready has already been tested)
;
S_MDIN:
S_GETCHR:
IN A,(S_DATP) ; read character from port
RET
;
;-----------------------------------------------------------------------
;
; Test for character ready to receive, Z = ready
; Error code returned in A register
; *** Error code does not seem to be used ***
;
S_RCVRDY:
;XOR A
;OUT (S_CTLP),A ; select WR0
IN A,(S_CTLP) ; get status
AND S_RCVB ; isolate ready bit
CP S_RCVR ; test it (set flags)
LD A,0 ; report no line errors
RET
;
;-----------------------------------------------------------------------
;
; Test for ready to send a character, Z = ready
;
S_SNDRDY:
;XOR A
;OUT (S_CTLP),A ; select WR0
IN A,(S_CTLP) ; get status
AND S_SNDB ; isolate ready bit
CP S_SNDR ; test it (set flags)
LD A,0 ; report no line errors
RET
;
;-----------------------------------------------------------------------
;
; Report baud rate (index into SPTBL returned in register A)
;
S_SPEED:
LD A,8 ; arbitrarily return 9600 baud
RET
;
;=======================================================================
;=======================================================================
;
; HBIOS CONSOLE (COM0:)
;
; Will be used for all RC2014 systems
@ -645,7 +762,7 @@ HB_SENDR:
;
;-----------------------------------------------------------------------
;
; Test and rep;ort carrier status, Z set if carrier present
; Test and report carrier status, Z set if carrier present
;
HB_CAROK:
XOR A ; not used, always indicate present

2
Source/CBIOS/ver.inc
View File

@ -2,4 +2,4 @@
#DEFINE RMN 9
#DEFINE RUP 2
#DEFINE RTP 0
#DEFINE BIOSVER "2.9.2-pre.3"
#DEFINE BIOSVER "2.9.2-pre.4"

16
Source/HBIOS/Build.ps1
View File

@ -19,17 +19,23 @@ param([string]$Platform = "", [string]$Config = "", [string]$RomSize = "512", [s
# setup mechanism so that multiple configuration are not needed. When building for UNA, the pre-built
# UNA BIOS is simply imbedded, it is not built here.
#
$PlatformListZ80 = "SBC", "ZETA", "ZETA2", "RCZ80", "EZZ80", "UNA"
$PlatformListZ180 = "N8", "MK4", "RCZ180", "SC126"
#
# Establish the build platform. It may have been passed in on the command line. Validate
# $Platform and loop requesting a new value as long as it is not valid. The valid platform
# names are just hard-coded for now.
#
$PlatformList = $PlatformListZ80 + $PlatformListZ180
$Prompt = "Platform ["
ForEach ($PlatformName in $PlatformList) {$Prompt += $PlatformName + "|"}
$Prompt = $Prompt.Substring(0, $Prompt.Length - 1) + "]"
$Platform = $Platform.ToUpper()
while ($true)
{
if (($Platform -eq "SBC") -or ($Platform -eq "ZETA") -or ($Platform -eq "ZETA2") -or ($Platform -eq "RCZ80") -or ($Platform -eq "EZZ80") -or ($Platform -eq "RCZ180") -or ($Platform -eq "N8") -or ($Platform -eq "MK4") -or ($Platform -eq "UNA")) {break}
$Platform = (Read-Host -prompt "Platform [SBC|ZETA|ZETA2|RCZ80|EZZ80|RCZ180|N8|MK4|UNA]").Trim().ToUpper()
if ($PlatformList -contains $Platform) {break}
$Platform = (Read-Host -prompt $Prompt).Trim().ToUpper()
}
#
@ -66,7 +72,8 @@ while ($true)
# TASM should be invoked with the proper CPU type. Below, the CPU type is inferred
# from the platform.
#
if (($Platform -eq "N8") -or ($Platform -eq "MK4") -or ($Platform -eq "RCZ180")) {$CPUType = "180"} else {$CPUType = "80"}
#if (($Platform -eq "N8") -or ($Platform -eq "MK4") -or ($Platform -eq "RCZ180") -or ($Platform -eq "SC126")) {$CPUType = "180"} else {$CPUType = "80"}
if ($PlatformListZ180 -contains $Platform) {$CPUType = "180"} else {$CPUType = "80"}
#
# The $RomName variable determines the name of the image created by the script. By default,
@ -107,7 +114,7 @@ if ($Platform -eq "UNA") {$CBiosFile = '../CBIOS/cbios_una.bin'} else {$CBiosFil
$RomApps = "assign","fdu","format","mode","osldr","rtc","survey","syscopy","sysgen","talk","timer","xm","inttest"
""
"Building ${RomName}: ${ROMSize}KB ROM configuration ${Config} for Z${CPUType}..."
"Building ${RomName} ${ROMSize}KB ROM configuration ${Config} for Z${CPUType}..."
""
# Current date/time is queried here to be subsequently imbedded in image
@ -146,7 +153,6 @@ Function Concat($InputFileList, $OutputFile)
PLATFORM .EQU PLT_${Platform} ; HARDWARE PLATFORM
ROMSIZE .EQU ${ROMSize} ; SIZE OF ROM IN KB
;
;#INCLUDE "${PlatformConfigFile}"
#INCLUDE "${ConfigFile}"
;
"@ | Out-File "build.inc" -Encoding ASCII

6
Source/HBIOS/Config/RCZ180_sc126.asm → Source/HBIOS/Config/SC126_std.asm
View File

@ -3,14 +3,12 @@
; SC126
;==================================================================================================
;
#include "cfg_rcz180.asm"
#include "cfg_sc126.asm"
;
Z180_CLKDIV .SET 1 ; 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .SET 0 ; MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 1 ; ADD (0-3) I/O WAIT STATES ABOVE 1 W/S BUILT-IN
;
DIAGPORT .SET $0D ; DIAGNOSTIC PORT ADDRESS
;
CPUOSC .SET 18432000 ; CPU OSC FREQ
DEFSERCFG .SET SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG
;
@ -25,8 +23,6 @@ IDEENABLE .SET TRUE ; TRUE FOR IDE DEVICE SUPPORT (CF MODULE)
IDEMODE .SET IDEMODE_RC ; TYPE OF CF MODULE: IDEMODE_RC, IDEMODE_SMB
PPIDEENABLE .SET FALSE ; TRUE FOR PPIDE DEVICE SUPPORT (PPIDE MODULE)
;
DSRTCENABLE .SET TRUE ; DS-1302 CLOCK DRIVER
;
SDENABLE .SET TRUE ; TRUE FOR SD SUPPORT
SDMODE .SET SDMODE_SC126 ; SDMODE_JUHA, SDMODE_CSIO, SDMODE_UART, SDMODE_PPI, SDMODE_DSD
SDTRACE .SET 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)

29
Source/HBIOS/ay.asm
View File

@ -4,15 +4,28 @@
; WILL ALSO WORK WITH YM2149
;======================================================================
;
#IF (PLATFORM == PLT_N8)
AY_RSEL .EQU N8_PSG+0
AY_RDAT .EQU N8_PSG+1
AY_ACR .EQU N8_DEFACR
#ELSE
#IF (AYMODE == AYMODE_SCG)
AY_RSEL .EQU $9A
AY_RDAT .EQU $9B
AY_ACR .EQU $9C
#ENDIF
;
#IF (AYMODE == AYMODE_N8)
AY_RSEL .EQU N8_PSG+0
AY_RDAT .EQU N8_PSG+1
AY_ACR .EQU N8_DEFACR
#ENDIF
;
#IF (AYMODE == AYMODE_RCZ80)
AY_RSEL .EQU $D8
AY_RDAT .EQU $D0
#ENDIF
;
#IF (AYMODE == AYMODE_RCZ180)
AY_RSEL .EQU $68
AY_RDAT .EQU $60
#ENDIF
;
AY_R0CHAP .EQU $00
AY_R1CHAP .EQU $01
AY_R2CHBP .EQU $02
@ -81,7 +94,7 @@ AY_BEEP:
;
AY_WRTPSG:
HB_DI
#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
#IF (CPUFAM == CPU_Z180)
IN0 A,(Z180_DCNTL) ; GET WAIT STATES
PUSH AF ; SAVE VALUE
OR %00110000 ; FORCE SLOW OPERATION (I/O W/S=3)
@ -91,7 +104,7 @@ AY_WRTPSG:
OUT (AY_RSEL),A
LD A,E
OUT (AY_RDAT),A
#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
#IF (CPUFAM == CPU_Z180)
POP AF ; GET SAVED DCNTL VALUE
OUT0 (Z180_DCNTL),A ; AND RESTORE IT
#ENDIF
@ -101,7 +114,9 @@ AY_WRTPSG:
; CHECK THERE IS A DEVICE PRESENT
;
AY_PROBE:
#IF ((AYMODE == AYMODE_SCG) | (AYMODE == AYMODE_N8))
LD A,$FF
OUT (AY_ACR),A ; INIT AUX CONTROL REG
#ENDIF
XOR A
RET

1
Source/HBIOS/cfg_ezz80.asm
View File

@ -57,6 +57,7 @@ VGAENABLE .EQU FALSE ; TRUE FOR VGA VIDEO/KBD SUPPORT
;
SPKENABLE .EQU FALSE ; TRUE FOR RTC LATCH IOBIT SOUND
AYENABLE .EQU FALSE ; TRUE FOR AY PSG SOUND
AYMODE .EQU AYMODE_RCZ80 ; AYMODE_[SCG/N8/RCZ80/RCZ180]
;
MDENABLE .EQU TRUE ; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENABLED)
MDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE)

2
Source/HBIOS/cfg_mk4.asm
View File

@ -38,10 +38,12 @@ VDUENABLE .EQU FALSE ; TRUE FOR VDU BOARD SUPPORT
CVDUENABLE .EQU FALSE ; TRUE FOR CVDU BOARD SUPPORT
NECENABLE .EQU FALSE ; TRUE FOR uPD7220 BOARD SUPPORT
TMSENABLE .EQU FALSE ; TRUE FOR N8 (TMS9918) VIDEO/KBD SUPPORT
TMSMODE .EQU TMSMODE_SCG ; TMSMODE_[SCG/N8]
VGAENABLE .EQU FALSE ; TRUE FOR VGA VIDEO/KBD SUPPORT
;
SPKENABLE .EQU FALSE ; TRUE FOR RTC LATCH IOBIT SOUND
AYENABLE .EQU FALSE ; TRUE FOR AY PSG SOUND
AYMODE .EQU AYMODE_SCG ; AYMODE_[SCG/N8/RCZ80/RCZ180]
;
MDENABLE .EQU TRUE ; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENABLED)
MDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE)

2
Source/HBIOS/cfg_n8.asm
View File

@ -38,10 +38,12 @@ VDUENABLE .EQU FALSE ; TRUE FOR VDU BOARD SUPPORT
CVDUENABLE .EQU FALSE ; TRUE FOR CVDU BOARD SUPPORT
NECENABLE .EQU FALSE ; TRUE FOR uPD7220 BOARD SUPPORT
TMSENABLE .EQU TRUE ; TRUE FOR N8 (TMS9918) VIDEO/KBD SUPPORT
TMSMODE .EQU TMSMODE_N8 ; TMSMODE_[SCG/N8]
VGAENABLE .EQU FALSE ; TRUE FOR VGA VIDEO/KBD SUPPORT
;
SPKENABLE .EQU FALSE ; TRUE FOR RTC LATCH IOBIT SOUND
AYENABLE .EQU TRUE ; TRUE FOR AY PSG SOUND
AYMODE .EQU AYMODE_N8 ; AYMODE_[SCG/N8/RCZ80/RCZ180]
;
MDENABLE .EQU TRUE ; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENABLED)
MDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE)

1
Source/HBIOS/cfg_rcz180.asm
View File

@ -57,6 +57,7 @@ VGAENABLE .EQU FALSE ; TRUE FOR VGA VIDEO/KBD SUPPORT
;
SPKENABLE .EQU FALSE ; TRUE FOR RTC LATCH IOBIT SOUND
AYENABLE .EQU FALSE ; TRUE FOR AY PSG SOUND
AYMODE .EQU AYMODE_RCZ180 ; AYMODE_[SCG/N8/RCZ80/RCZ180]
;
MDENABLE .EQU TRUE ; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENABLED)
MDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE)

1
Source/HBIOS/cfg_rcz80.asm
View File

@ -70,6 +70,7 @@ VGAENABLE .EQU FALSE ; TRUE FOR VGA VIDEO/KBD SUPPORT
;
SPKENABLE .EQU FALSE ; TRUE FOR RTC LATCH IOBIT SOUND
AYENABLE .EQU FALSE ; TRUE FOR AY PSG SOUND
AYMODE .EQU AYMODE_RCZ80 ; AYMODE_[SCG/N8/RCZ80/RCZ180]
;
MDENABLE .EQU TRUE ; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENABLED)
MDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE)

2
Source/HBIOS/cfg_sbc.asm
View File

@ -49,11 +49,13 @@ VDUENABLE .EQU FALSE ; TRUE FOR VDU BOARD SUPPORT
CVDUENABLE .EQU FALSE ; TRUE FOR CVDU BOARD SUPPORT
NECENABLE .EQU FALSE ; TRUE FOR uPD7220 BOARD SUPPORT
TMSENABLE .EQU FALSE ; TRUE FOR N8 (TMS9918) VIDEO/KBD SUPPORT
TMSMODE .EQU TMSMODE_SCG ; TMSMODE_[SCG/N8]
VGAENABLE .EQU FALSE ; TRUE FOR VGA VIDEO/KBD SUPPORT
VDUSIZ .EQU V80X25 ; VDU DISPLAY FORMAT V80X24, V80X25, V80X30
;
SPKENABLE .EQU FALSE ; TRUE FOR RTC LATCH IOBIT SOUND
AYENABLE .EQU FALSE ; TRUE FOR AY PSG SOUND
AYMODE .EQU AYMODE_SCG ; AYMODE_[SCG/N8/RCZ80/RCZ180]
;
MDENABLE .EQU TRUE ; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENABLED)
MDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE)

115
Source/HBIOS/cfg_sc126.asm
View File

@ -0,0 +1,115 @@
;
;==================================================================================================
; ROMWBW 2.X CONFIGURATION DEFAULTS FOR SC126
;==================================================================================================
;
; BUILD CONFIGURATION OPTIONS
;
CPUOSC .EQU 18432000 ; CPU OSC FREQ
MEMMGR .EQU MM_Z180 ; MM_NONE, MM_SBC, MM_Z2, MM_N8, MM_Z180
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!!
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE)
INTMODE .EQU 2 ; 0=NONE, 1=INT MODE 1, 2=INT MODE 2
DIAGENABLE .EQU TRUE ; TRUE FOR DIAGNOSTIC CODE PORT OUTPUT
DIAGPORT .EQU $0D ; DIAGNOSTIC PORT ADDRESS
;
CRTACT .EQU FALSE ; CRT ACTIVATION AT STARTUP
VDAEMU .EQU EMUTYP_ANSI ; DEFAULT VDA EMULATION (EMUTYP_TTY, EMUTYP_ANSI, ...)
;
DSKYENABLE .EQU FALSE ; TRUE FOR DSKY SUPPORT (DO NOT COMBINE WITH PPIDE)
;
HTIMENABLE .EQU FALSE ; TRUE FOR SIMH TIMER SUPPORT
SIMRTCENABLE .EQU FALSE ; SIMH CLOCK DRIVER
DSRTCENABLE .EQU TRUE ; DS-1302 CLOCK DRIVER
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTCMODE_STD, DSRTCMODE_MFPIC
DSRTCCHG .EQU FALSE ; DS-1302 CONFIGURE CHARGE ON (TRUE) OR OFF (FALSE)
;
ASCIENABLE .EQU TRUE ; TRUE FOR Z180 ASCI SUPPORT
UARTENABLE .EQU FALSE ; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
UARTOSC .EQU 1843200 ; UART OSC FREQUENCY
ACIAENABLE .EQU FALSE ; TRUE FOR MOTOROLA 6850 ACIA SUPPORT
;
SIOENABLE .EQU TRUE ; TRUE FOR ZILOG SIO SUPPORT
SIODEBUG .EQU FALSE ; PS
SIOCNT .EQU 2 ; 1 OR 2 SIO CHIPS (EACH CHIP HAS 2 CHANNELS)
SIO0MODE .EQU SIOMODE_RC ; TYPE OF FIRST SIO TO DETECT: SIOMODE_RC/SMB/ZP/EZZ80
SIO0BASE .EQU $80 ; IO PORT ADDRESS BASE FOR FIRST SIO CHIP
SIO0ACLK .EQU 7372800 ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
SIO0ADIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
SIO0ACFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG
SIO0BCLK .EQU 7372800 ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
SIO0BDIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
SIO0BCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG
SIO1MODE .EQU SIOMODE_RC ; TYPE OF SECOND SIO TO DETECT: SIOMODE_RC, SIOMODE_SMB
SIO1BASE .EQU $84 ; IO PORT ADDRESS BASE FOR SECOND SIO CHIP
SIO1ACLK .EQU 7372800 ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
SIO1ADIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
SIO1ACFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG
SIO1BCLK .EQU 7372800 ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
SIO1BDIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
SIO1BCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG
;
VDUENABLE .EQU FALSE ; TRUE FOR VDU BOARD SUPPORT
CVDUENABLE .EQU FALSE ; TRUE FOR CVDU BOARD SUPPORT
NECENABLE .EQU FALSE ; TRUE FOR uPD7220 BOARD SUPPORT
TMSENABLE .EQU FALSE ; TRUE FOR N8 (TMS9918) VIDEO/KBD SUPPORT
VGAENABLE .EQU FALSE ; TRUE FOR VGA VIDEO/KBD SUPPORT
;
SPKENABLE .EQU FALSE ; TRUE FOR RTC LATCH IOBIT SOUND
AYENABLE .EQU FALSE ; TRUE FOR AY PSG SOUND
AYMODE .EQU AYMODE_RCZ180 ; AYMODE_[SCG/N8/RCZ80/RCZ180]
;
MDENABLE .EQU TRUE ; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENABLED)
MDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE)
;
FDENABLE .EQU FALSE ; TRUE FOR FLOPPY SUPPORT
FDMODE .EQU FDMODE_RCWDC ; FDMODE_DIO, FDMODE_ZETA, FDMODE_DIDE, FDMODE_N8, FDMODE_DIO3
FDTRACE .EQU 1 ; 0=SILENT, 1=FATAL ERRORS, 2=ALL ERRORS, 3=EVERYTHING (ONLY RELEVANT IF FDENABLE = TRUE)
FDMEDIA .EQU FDM144 ; FDM720, FDM144, FDM360, FDM120 (ONLY RELEVANT IF FDENABLE = TRUE)
FDMEDIAALT .EQU FDM720 ; ALTERNATE MEDIA TO TRY, SAME CHOICES AS ABOVE (ONLY RELEVANT IF FDMAUTO = TRUE)
FDMAUTO .EQU TRUE ; SELECT BETWEEN MEDIA OPTS ABOVE AUTOMATICALLY
;
RFENABLE .EQU FALSE ; TRUE FOR RAM FLOPPY SUPPORT
;
IDEENABLE .EQU FALSE ; TRUE FOR IDE SUPPORT
IDEMODE .EQU IDEMODE_RC ; IDEMODE_DIO, IDEMODE_DIDE, IDEMODE_RC
IDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
IDE8BIT .EQU TRUE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
;
PPIDEENABLE .EQU FALSE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_RC ; PPIDEMODE_SBC, PPPIDEMODE_DIO3, PPIDEMODE_MFP, PPIDEMODE_N8, PPIDEMODE_RC
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
;
SDENABLE .EQU TRUE ; TRUE FOR SD SUPPORT
SDMODE .EQU SDMODE_SC126 ; SDMODE_JUHA, SDMODE_CSIO, SDMODE_UART, SDMODE_PPI, SDMODE_DSD
SDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
SDCSIOFAST .EQU FALSE ; TABLE-DRIVEN BIT INVERTER
;
PRPENABLE .EQU FALSE ; TRUE FOR PROPIO SUPPORT
;
PPPENABLE .EQU FALSE ; TRUE FOR PARPORTPROP SUPPORT
PPPSDENABLE .EQU TRUE ; TRUE FOR PARPORTPROP SD SUPPORT
PPPSDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPPENABLE = TRUE)
PPPCONENABLE .EQU TRUE ; TRUE FOR PROPIO CONSOLE SUPPORT (PS/2 KBD & VGA VIDEO)
;
HDSKENABLE .EQU FALSE ; TRUE FOR SIMH HDSK SUPPORT
;
TERMENABLE .EQU FALSE ; TERM PSEUDO DEVICE, WILL BE ENABLED IF A VDA IS ENABLED
;
BOOTTYPE .EQU BT_MENU ; BT_MENU (WAIT FOR KEYPRESS), BT_AUTO (BOOT_DEFAULT AFTER BOOT_TIMEOUT SECS)
BOOT_TIMEOUT .EQU 20 ; APPROX TIMEOUT IN SECONDS FOR AUTOBOOT, 0 FOR IMMEDIATE
BOOT_DEFAULT .EQU 'Z' ; SELECTION TO INVOKE AT TIMEOUT
;
; 18.432MHz OSC @ FULL SPEED
;
Z180_CLKDIV .EQU 1 ; 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .EQU 0 ; MEMORY WAIT STATES (0-3)
Z180_IOWAIT .EQU 1 ; ADD (0-3) I/O WAIT STATES ABOVE 1 W/S BUILT-IN
;
PIO_4P .EQU FALSE ; TRUE FOR ECB-4PIO PIO SUPPORT
PIO_ZP .EQU FALSE ; TRUE FOR ECB-ZILOG PERIPHERALS BOARD
PPI_SBC .EQU FALSE ; TRUE FOR SBC V2 8255 (IF NOT BEING USED FOR PPIDE)
;
UFENABLE .EQU FALSE ; TRUE FOR ECB USB-FIFO SUPPORT

11
Source/HBIOS/dbgmon.asm
View File

@ -111,15 +111,18 @@ SERIALCMDLOOP:
;_____________________________________________________________________________
;
INITIALIZE:
#IF (PLATFORM == PLT_UNA)
#IF (BIOS == BIOS_UNA)
; INSTALL UNA INVOCATION VECTOR FOR RST 08
LD A,$C3 ; JP INSTRUCTION
LD (8),A ; STORE AT 0x0008
LD HL,($FFFE) ; UNA ENTRY VECTOR
LD (9),HL ; STORE AT 0x0009
#ELSE
#ENDIF
#IF (BIOS == BIOS_WBW)
CALL DELAY_INIT
#ENDIF
RET
;
;__BOOT_______________________________________________________________________
@ -128,7 +131,7 @@ INITIALIZE:
;_____________________________________________________________________________
;
BOOT:
#IF (PLATFORM == PLT_UNA)
#IF (BIOS == BIOS_UNA)
LD BC,$01FB ; UNA FUNC = SET BANK
LD DE,0 ; ROM BANK 0
CALL $FFFD ; DO IT (RST 08 NOT SAFE HERE)
@ -737,7 +740,7 @@ PRTSTRH:
LD HL,TXT_MINIHELP
JP PRTSTR
;
#IF (PLATFORM == PLT_UNA)
#IF (BIOS == BIOS_UNA)
;
;__COUT_______________________________________________________________________
;

2
Source/HBIOS/dsrtc.asm
View File

@ -71,7 +71,7 @@
; D4 WR RTC_CE RTC_CE -- RTC_CE RTC_CE RTC_CE
; D3 WR NC SPK /RTC_CE NC NC /SPI_CS2
; D2 WR NC CLKHI RTC_CLK SPI_CS SPI_CS /SPI_CS1
; D1 WR -- -- RTC_WE SPI_CLK NC FS
; D1 WR -- -- RTC_WE SPI_CLK NC FS
; D0 WR -- -- RTC_OUT SPI_DI NC I2C_SCL
;
; D7 RD -- -- -- -- -- I2C_SDA

26
Source/HBIOS/hbios.asm
View File

@ -743,7 +743,7 @@ HB_START:
;
LD SP,HBX_LOC ; SETUP INITIAL STACK JUST BELOW HBIOS PROXY
;
#IFDEF CPU_Z180
#IF (CPUFAM == CPU_Z180)
; SET BASE FOR CPU IO REGISTERS
LD A,Z180_BASE
OUT0 (Z180_ICR),A
@ -947,7 +947,7 @@ HB_START1: ; BNKCALL ARRIVES HERE, BUT NOW RUNNING IN RAM BANK
;
LD HL,0 ; L = 0 MEANS Z80
;
#IFDEF CPU_Z180
#IF (CPUFAM == CPU_Z180)
;
; TEST FOR ORIGINAL Z180 USING MLT
LD DE,$0506 ; 5 X 6
@ -980,7 +980,7 @@ HB_CPU1:
;
CALL HB_CPUSPD ; CPU SPEED DETECTION
;
#IFDEF CPU_Z180
#IF (CPUFAM == CPU_Z180)
;
; SET DESIRED WAIT STATES
LD A,0 + (Z180_MEMWAIT << 6) | (Z180_IOWAIT << 4)
@ -1141,7 +1141,7 @@ PSCNX .EQU $ + 1
LD A,HBX_IVT >> 8 ; SETUP HI BYTE OF IVT ADDRESS
LD I,A ; ... AND PLACE IT IN I REGISTER
#IFDEF CPU_Z180
#IF (CPUFAM == CPU_Z180)
; SETUP Z180 IVT
XOR A ; SETUP LO BYTE OF IVT ADDRESS
OUT0 (Z180_IL),A ; ... AND PLACE IN Z180 IL REGISTER
@ -1282,7 +1282,7 @@ PSCNX .EQU $ + 1
;
#ENDIF
;
#IFDEF CPU_Z180
#IF (CPUFAM == CPU_Z180)
;
#IF (INTMODE == 2)
;
@ -1354,7 +1354,7 @@ HB_PCPU:
CALL PRTD3M ; PRINT AS DECIMAL WITH 3 DIGIT MANTISSA
PRTS("MHz$")
;
#IFDEF CPU_Z180
#IF (CPUFAM == CPU_Z180)
PRTS(" IO=0x$")
LD A,Z180_BASE
CALL PRTHEXBYTE
@ -1363,7 +1363,7 @@ HB_PCPU:
; DISPLAY CPU CONFIG
;
CALL NEWLINE
#IFDEF CPU_Z180
#IF (CPUFAM == CPU_Z180)
LD A,Z180_MEMWAIT
#ELSE
LD A,0
@ -1371,7 +1371,7 @@ HB_PCPU:
CALL PRTDECB
CALL PRTSTRD
.TEXT " MEM W/S, $"
#IFDEF CPU_Z180
#IF (CPUFAM == CPU_Z180)
LD A,Z180_IOWAIT + 1
#ELSE
LD A,1
@ -2356,7 +2356,7 @@ TEMPCNT .DB 250
;
HB_TIMINT2:
;
#IFDEF CPU_Z180
#IF (CPUFAM == CPU_Z180)
; ACK/RESET Z180 TIMER INTERRUPT
IN0 A,(Z180_TCR)
IN0 A,(Z180_TMDR0L)
@ -2841,7 +2841,7 @@ HB_CPUSPD:
RET NZ
;
HB_CPUSPD1:
#IFDEF CPU_Z180
#IF (CPUFAM == CPU_Z180)
; USE MEM W/S = 2 AND I/O W/S = 3 FOR TEST
IN0 A,(Z180_DCNTL)
PUSH AF
@ -2858,7 +2858,7 @@ HB_CPUSPD1:
LD (HB_CURSEC),A ; SAVE NEW VALUE
CALL HB_WAITSEC ; WAIT FOR SECONDS TICK
;
#IFDEF CPU_Z180
#IF (CPUFAM == CPU_Z180)
; RESTORE W/S SETTINGS FROM BEFORE TEST
POP AF
OUT0 (Z180_DCNTL),A
@ -2893,7 +2893,7 @@ HB_WAITSEC:
LD DE,0 ; INIT LOOP COUNTER
HB_WAITSEC1:
;
#IFDEF CPU_Z80
#IF (CPUFAM == CPU_Z80)
; LOOP TARGET IS 4000 T-STATES, SO CPU FREQ IN KHZ = LOOP COUNT * 4
CALL DLY32
CALL DLY16
@ -2904,7 +2904,7 @@ HB_WAITSEC1:
INC HL ; 6 TSTATES
#ENDIF
;
#IFDEF CPU_Z180
#IF (CPUFAM == CPU_Z180)
; LOOP TARGET IS 4000 T-STATES, SO CPU FREQ IN KHZ = LOOP COUNT * 4
CALL DLY2
ADD IX,BC ; 10 + 4 = 14 TSTATES

2
Source/HBIOS/plt_ezz80.inc
View File

@ -1,6 +1,8 @@
;
; EASY Z80 HARDWARE DEFINITIONS
;
#DEFINE PLATFORM_NAME "EASYZ80"
;
MPGSEL_0 .EQU $78 ; BANK_0 PAGE SELECT REGISTER (WRITE ONLY)
MPGSEL_1 .EQU $79 ; BANK_1 PAGE SELECT REGISTER (WRITE ONLY)
MPGSEL_2 .EQU $7A ; BANK_2 PAGE SELECT REGISTER (WRITE ONLY)

2
Source/HBIOS/plt_mk4.inc
View File

@ -1,6 +1,8 @@
;
; MARK IV HARDWARE DEFINITIONS
;
#DEFINE PLATFORM_NAME "MARK IV"
;
RAMBIAS .EQU 512 ; RAM STARTS AT 512K
;
MK4_BASE .EQU $80 ; I/O BASE ADDRESS FOR ONBOARD PERIPHERALS

2
Source/HBIOS/plt_n8.inc
View File

@ -1,6 +1,8 @@
;
; N8 HARDWARE DEFINITIONS
;
#DEFINE PLATFORM_NAME "N8"
;
RAMBIAS .EQU 0 ; RAM STARTS AT 0K
;
N8_BASE .EQU $80 ; I/O BASE ADDRESS FOR ONBOARD PERIPHERALS

2
Source/HBIOS/plt_rcz180.inc
View File

@ -1,6 +1,8 @@
;
; RC2014 Z180 HARDWARE DEFINITIONS
;
#DEFINE PLATFORM_NAME "RC2014"
;
RAMBIAS .EQU 512 ; RAM STARTS AT 512K
;
MPGSEL_0 .EQU $78 ; BANK_0 PAGE SELECT REGISTER (WRITE ONLY)

2
Source/HBIOS/plt_rcz80.inc
View File

@ -1,6 +1,8 @@
;
; RC2014 HARDWARE DEFINITIONS
;
#DEFINE PLATFORM_NAME "RC2014"
;
MPGSEL_0 .EQU $78 ; BANK_0 PAGE SELECT REGISTER (WRITE ONLY)
MPGSEL_1 .EQU $79 ; BANK_1 PAGE SELECT REGISTER (WRITE ONLY)
MPGSEL_2 .EQU $7A ; BANK_2 PAGE SELECT REGISTER (WRITE ONLY)

2
Source/HBIOS/plt_sbc.inc
View File

@ -1,6 +1,8 @@
;
; SBC HARDWARE DEFINITIONS
;
#DEFINE PLATFORM_NAME "SBC"
;
SBC_BASE .EQU $60 ; I/O BASE ADDRESS FOR ONBOARD PERIPHERALS
;
#IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_ZETA))

12
Source/HBIOS/plt_sc126.inc
View File

@ -0,0 +1,12 @@
;
; SC126 Z180 HARDWARE DEFINITIONS
;
#DEFINE PLATFORM_NAME "SC126"
;
RAMBIAS .EQU 512 ; RAM STARTS AT 512K
;
RTC .EQU $0C ; ADDRESS OF RTC LATCH AND INPUT PORT
;
Z180_BASE .EQU $C0 ; I/O BASE ADDRESS FOR INTERNAL Z180 REGISTERS
;
#INCLUDE "z180.inc"

1
Source/HBIOS/plt_una.inc
View File

@ -1,3 +1,4 @@
;
; UNA HARDWARE DEFINITIONS
;
#DEFINE PLATFORM_NAME "UNA"

3
Source/HBIOS/plt_zeta.inc
View File

@ -1,6 +1,9 @@
;
; ZETA HARDWARE DEFINITIONS
;
;
#DEFINE PLATFORM_NAME "ZETA"
;
SBC_BASE .EQU $60 ; I/O BASE ADDRESS FOR ONBOARD PERIPHERALS
;
; BIT 7 OF MPCL_ROM SELECTS ROM/RAM (0=ROM, 1=RAM)

2
Source/HBIOS/plt_zeta2.inc
View File

@ -1,6 +1,8 @@
;
; ZETA 2 HARDWARE DEFINITIONS
;
#DEFINE PLATFORM_NAME "ZETA V2"
;
SBC_BASE .EQU $60 ; I/O BASE ADDRESS FOR ONBOARD PERIPHERALS
;
MPGSEL_0 .EQU SBC_BASE + $18 ; BANK_0 PAGE SELECT REGISTER (WRITE ONLY)

22
Source/HBIOS/romldr.asm
View File

@ -45,7 +45,7 @@ BID_CUR .EQU -1 ; SPECIAL BANK ID VALUE INDICATES CURRENT BANK
;
JP $100 ; RST 0: JUMP TO BOOT CODE
.FILL (008H - $),0FFH
#IF (PLATFORM == PLT_UNA)
#IF (BIOS == BIOS_UNA)
JP $FFFD ; RST 8: INVOKE UBIOS FUNCTION
#ELSE
JP HB_INVOKE ; RST 8: INVOKE HBIOS FUNCTION
@ -61,7 +61,7 @@ BID_CUR .EQU -1 ; SPECIAL BANK ID VALUE INDICATES CURRENT BANK
.FILL (030H - $),0FFH
RET ; RST 30
.FILL (038H - $),0FFH
#IF (PLATFORM == PLT_UNA)
#IF (BIOS == BIOS_UNA)
RETI ; RETURN W/ INTS DISABLED
#ELSE
#IF (INTMODE == 1)
@ -92,11 +92,11 @@ BID_CUR .EQU -1 ; SPECIAL BANK ID VALUE INDICATES CURRENT BANK
;
START: LD SP,BL_STACK ; SETUP STACK
;
#IF (PLATFORM != PLT_UNA)
#IF (BIOS == BIOS_WBW)
CALL DELAY_INIT ; INIT DELAY FUNCTIONS
#ENDIF
;
#IF (PLATFORM == PLT_UNA)
#IF (BIOS == BIOS_UNA)
; ; COPY UNA BIOS PAGE ZERO TO USER BANK, LEAVE USER BANK ACTIVE
; LD BC,$01FB ; UNA FUNC = SET BANK
; LD DE,BID_BIOS ; UBIOS_PAGE (SEE PAGES.INC)
@ -334,7 +334,7 @@ MATX:
MENU_S: MENU_L("~Monitor$ ", "M", KY_CL, MON_SERIAL, 1000h, MON_LOC, MON_SIZ, BID_CUR, BID_USR, "Monitor$ ")
MENU_1: MENU_L("~CP/M$ ", "C", KY_BK, CPM_ENT, 2000h, CPM_LOC, CPM_SIZ, BID_CUR, BID_USR, "CP/M 80 v2.2$")
MENU_L("~Z-System$", "Z", KY_FW, CPM_ENT, 5000h, CPM_LOC, CPM_SIZ, BID_CUR, BID_USR, "ZSDOS v1.1$ ")
#IF (PLATFORM != PLT_UNA)
#IF (BIOS == BIOS_WBW)
MENU_L("~Forth$ ", "F", KY_EX, FTH_LOC, 0000h, FTH_LOC, FTH_SIZ, BID_IMG1, BID_USR, "Camel Forth$ ")
MENU_L("~BASIC$ ", "B", KY_DE, BAS_LOC, 1700h, BAS_LOC, BAS_SIZ, BID_IMG1, BID_USR, "Nascom BASIC$")
MENU_L("~T-BASIC$ ", "T", KY_EN, TBC_LOC, 3700h, TBC_LOC, TBC_SIZ, BID_IMG1, BID_USR, "Tasty BASIC$ ")
@ -396,7 +396,7 @@ GOROM1: LD E,(HL) ; (1) EXEC ADR
PUSH DE ; (5) SRC/DEST BANKS
DJNZ GOROM1 ; LOOP TILL DONE
;
#IF (PLATFORM == PLT_UNA)
#IF (BIOS == BIOS_UNA)
;
; NOTE: UNA HAS NO INTERBANK MEMORY COPY, SO WE CAN ONLY LOAD
; IMAGES FROM THE CURRENT BANK. A SIMPLE LDIR IS USED TO
@ -487,7 +487,7 @@ GOBOOTDISK:
LD DE,STR_BOOTDISK1 ; DISK BOOT MESSAGE
CALL WRITESTR ; PRINT IT
;
#IF (PLATFORM == PLT_UNA)
#IF (BIOS == BIOS_UNA)
LD A,(BL_BOOTID) ; GET BOOT DEVICE ID
LD B,A ; MOVE TO B
;
@ -594,7 +594,7 @@ GOBOOTDISK:
RRCA ; ... BY DIVIDING MSB BY TWO
LD (BL_COUNT),A ; ... AND SAVE IT
;
#IF (PLATFORM == PLT_UNA)
#IF (BIOS == BIOS_UNA)
;
; READ OS IMAGE INTO MEMORY
LD C,$42 ; UNA FUNC: READ SECTORS
@ -676,7 +676,7 @@ DB_ERR:
LD DE,STR_BOOTERR
JP MENU
;
#IF (PLATFORM == PLT_UNA)
#IF (BIOS == BIOS_UNA)
;
; PRINT LIST OF ALL DRIVES UNDER UNA
;
@ -886,7 +886,7 @@ MSG_GO .DB $DB,$9D,$00,$00,$00,$80,$80,$80 ; "Go... "
; CONSOLE CHARACTER I/O HELPER ROUTINES (REGISTERS PRESERVED)
;==================================================================================================
;
#IF (PLATFORM != PLT_UNA)
#IF (BIOS == BIOS_WBW)
;
; OUTPUT CHARACTER FROM A
;
@ -951,7 +951,7 @@ CST:
;
#ENDIF
;
#IF (PLATFORM == PLT_UNA)
#IF (BIOS == BIOS_UNA)
;
; OUTPUT CHARACTER FROM A
;

2
Source/HBIOS/sd.asm
View File

@ -197,7 +197,7 @@ SD_TRDR .EQU Z180_TRDR
#IF (SDMODE == SDMODE_SC126) ; SC126
SD_DEVCNT .EQU 1 ; NUMBER OF PHYSICAL UNITS (SOCKETS)
SD_OPRREG .EQU RTC ; USES RTC LATCHES FOR OPERATION
SD_OPRDEF .EQU %00001100 ; QUIESCENT STATE (DEASSERT /CS1 & /CS2)
SD_OPRDEF .EQU %00001100 ; QUIESCENT STATE (/CS1 & /CS2 DEASSERTED)
SD_CS .EQU %00000100 ; RTC:2 IS SELECT FOR PRIMARY SPI CARD
SD_CNTR .EQU Z180_CNTR
SD_TRDR .EQU Z180_TRDR

81
Source/HBIOS/std.asm
View File

@ -12,6 +12,7 @@
; 7. RCZ80 RC2014 based system with 512K banked RAM/ROM card
; 8. RCZ180 RC2014 based system with Z180 CPU
; 9. EZZ80 Easy Z80, Z80 SBC w/ RC2014 bus and CTC
; 10. SC126 SC126 Z180 based system
; All the classes require certain generic definitions, and these are
; defined here prior to the inclusion of platform specific .inc files.
@ -46,11 +47,25 @@ PLT_UNA .EQU 6 ; UNA BIOS
PLT_RCZ80 .EQU 7 ; RC2014 W Z80
PLT_RCZ180 .EQU 8 ; RC2014 W/ Z180
PLT_EZZ80 .EQU 9 ; EASY Z80
PLT_SC126 .EQU 10 ; SC126
;
#IF (PLATFORM != PLT_UNA)
#IF (BIOS == BIOS_WBW)
#INCLUDE "hbios.inc"
#ENDIF
;
; CPU TYPES
;
CPU_NONE .EQU 0 ; NO CPU TYPE DEFINED
CPU_Z80 .EQU 1 ; Z80 FAMILY
CPU_Z180 .EQU 2 ; Z180 FAMILY
CPU_Z280 .EQU 3 ; Z280 FAMILY
;
; BIOS MODE
;
BIOS_NONE .EQU 0 ; NO BIOS TYPE DEFINED
BIOS_WBW .EQU 1 ; ROMWBW HBIOS
BIOS_UNA .EQU 2 ; UNA UBIOS
;
; MEMORY MANAGERS
;
MM_NONE .EQU 0
@ -153,6 +168,20 @@ SDMODE_DSD .EQU 6 ; DUAL SD
SDMODE_MK4 .EQU 7 ; MARK IV
SDMODE_SC126 .EQU 8 ; SC126
;
; SOUND CHIP MODE SELECTIONS
;
AYMODE_NONE .EQU 0
AYMODE_N8 .EQU 1 ; N8 BUILT-IN SOUND
AYMODE_SCG .EQU 2 ; SCG ECB BOARD
AYMODE_RCZ80 .EQU 3 ; RC2014 SOUND MODULE BY ED BRINDLEY ON Z80
AYMODE_RCZ180 .EQU 4 ; RC2014 SOUND MODULE BY ED BRINDLEY ON Z180
;
; TMS VIDEO MODE SELECTIONS
;
TMSMODE_NONE .EQU 0
TMSMODE_SCG .EQU 1 ; SCG ECB BOARD
TMSMODE_N8 .EQU 2 ; N8 BUILT-IN VIDEO
;
; SERIAL DEVICE CONFIGURATION CONSTANTS
;
SER_DATA5 .EQU 0 << 0
@ -264,40 +293,16 @@ FORCECON .EQU 0 ; DEFAULT IS TO FOLLOW NORMAL SEQUENCE
;
#INCLUDE "build.inc" ; INCLUDE USER CONFIG, ADD VARIANT, TIMESTAMP, & ROMSIZE
;
#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
#DEFINE CPU_Z180
#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180) | (PLATFORM == PLT_SC126))
CPUFAM .EQU CPU_Z180
#ELSE
#DEFINE CPU_Z80
CPUFAM .EQU CPU_Z80
#ENDIF
;
; SET PLATFORM NAME STRING
;
#IF (PLATFORM == PLT_SBC)
#DEFINE PLATFORM_NAME "SBC"
#ENDIF
#IF (PLATFORM == PLT_ZETA)
#DEFINE PLATFORM_NAME "ZETA"
#ENDIF
#IF (PLATFORM == PLT_ZETA2)
#DEFINE PLATFORM_NAME "ZETA V2"
#ENDIF
#IF (PLATFORM == PLT_N8)
#DEFINE PLATFORM_NAME "N8"
#ENDIF
#IF (PLATFORM == PLT_MK4)
#DEFINE PLATFORM_NAME "MARK IV"
#ENDIF
#IF (PLATFORM == PLT_UNA)
#DEFINE PLATFORM_NAME "UNA"
#ENDIF
#IF (PLATFORM == PLT_RCZ80)
#DEFINE PLATFORM_NAME "RC2014"
#ENDIF
#IF (PLATFORM == PLT_RCZ180)
#DEFINE PLATFORM_NAME "RC2014"
#ENDIF
#IF (PLATFORM == PLT_EZZ80)
#DEFINE PLATFORM_NAME "EASY"
BIOS .EQU BIOS_UNA
#ELSE
BIOS .EQU BIOS_WBW
#ENDIF
;
; INCLUDE PLATFORM SPECIFIC HARDWARE DEFINITIONS
@ -338,11 +343,15 @@ FORCECON .EQU 0 ; DEFAULT IS TO FOLLOW NORMAL SEQUENCE
#INCLUDE "plt_ezz80.inc"
#ENDIF
;
#IF (PLATFORM == PLT_SC126)
#INCLUDE "plt_sc126.inc"
#ENDIF
;
; SETUP DEFAULT CPU SPEED VALUES
;
CPUKHZ .EQU CPUOSC / 1000 ; CPU FREQ IN KHZ
;
#IFDEF CPU_Z180
#IF (CPUFAM == CPU_Z180)
#IF (Z180_CLKDIV == 0)
CPUKHZ .SET CPUKHZ / 2 ; ADJUST FOR HALF SPEED OPERATION
#ENDIF
@ -355,10 +364,12 @@ CPUMHZ .EQU CPUKHZ / 1000 ; CPU FREQ IN MHZ
;
; MEMORY BANK CONFIGURATION
;
#IF (PLATFORM == PLT_UNA)
#IF (BIOS == BIOS_UNA)
BID_ROM0 .EQU $0000
BID_RAM0 .EQU $8000
#ELSE
#ENDIF
;
#IF (BIOS == BIOS_WBW)
BID_ROM0 .EQU $00
BID_RAM0 .EQU $80
#ENDIF
@ -437,7 +448,7 @@ MON_SERIAL .EQU MON_LOC + (1 * 3) ; MONITOR ENTRY (SERIAL PORT)
;
#IF (INTMODE == 2)
#IFDEF CPU_Z180
#IF (CPUFAM == CPU_Z180)
; Z180-BASED SYSTEMS

20
Source/HBIOS/tms.asm
View File

@ -14,7 +14,7 @@
; TMS DRIVER - CONSTANTS
;======================================================================
;
#IF (PLATFORM == PLT_N8)
#IF (TMSMODE == TMSMODE_N8)
TMS_DATREG .EQU N8_BASE + $18 ; READ/WRITE DATA
TMS_CMDREG .EQU N8_BASE + $19 ; READ STATUS / WRITE REG SEL
@ -24,7 +24,9 @@ TMS_PPIB .EQU N8_BASE + $05 ; PPI PORT B
TMS_PPIC .EQU N8_BASE + $06 ; PPI PORT C
TMS_PPIX .EQU N8_BASE + $07 ; PPI CONTROL PORT
#ELSE
#ENDIF
#IF (TMSMODE == TMSMODE_SCG)
TMS_DATREG .EQU $98 ; READ/WRITE DATA
TMS_CMDREG .EQU $99 ; READ STATUS / WRITE REG SEL
@ -45,7 +47,7 @@ TERMENABLE .SET TRUE ; INCLUDE TERMINAL PSEUDODEVICE DRIVER
; TMS_IODELAY IS USED TO ADD RECOVERY TIME TO TMS9918 ACCESSES
; IF YOU SEE SCREEN CORRUPTION, ADJUST THIS!!!
;
#IF (PLATFORM == PLT_N8)
#IF (TMSMODE == TMSMODE_N8)
; BELOW WAS TUNED FOR N8 AT 18MHZ WITH 3 IO WAIT STATES
#DEFINE TMS_IODELAY NOP \ NOP \ NOP \ NOP \ NOP \ NOP \ NOP \ NOP
#ELSE
@ -58,14 +60,12 @@ TERMENABLE .SET TRUE ; INCLUDE TERMINAL PSEUDODEVICE DRIVER
;======================================================================
;
TMS_INIT:
#IF (PLATFORM != PLT_N8)
#IF (TMSMODE == TMSMODE_SCG)
LD A,$FF
OUT (TMS_ACR),A ; INIT AUX CONTROL REG
#ENDIF
;
#IF (PLATFORM == PLT_N8)
LD IY,TMS_IDAT ; POINTER TO INSTANCE DATA
#ENDIF
;
CALL NEWLINE ; FORMATTING
PRTS("TMS: IO=0x$")
@ -83,7 +83,7 @@ TMS_INIT1:
CALL TMS_CRTINIT ; SETUP THE TMS CHIP REGISTERS
CALL TMS_LOADFONT ; LOAD FONT DATA FROM ROM TO TMS STRORAGE
CALL TMS_VDARES
#IF (PLATFORM == PLT_N8)
#IF (TMSMODE == TMSMODE_N8)
CALL PPK_INIT ; INITIALIZE KEYBOARD DRIVER
#ENDIF
;
@ -118,7 +118,7 @@ TMS_FNTBL:
.DW TMS_VDAFIL
.DW TMS_VDACPY
.DW TMS_VDASCR
#IF (PLATFORM == PLT_N8)
#IF (TMSMODE == TMSMODE_N8)
.DW PPK_STAT
.DW PPK_FLUSH
.DW PPK_READ
@ -238,8 +238,6 @@ TMS_VDASCR2:
XOR A
RET
#IF (PLATFORM != PLT_N8)
; DUMMY FUNCTIONS BELOW BECAUSE SCG BOARD HAS NO
; KEYBOARD INTERFACE
@ -255,8 +253,6 @@ TMS_READ:
LD E,26 ; RETURN <SUB> (CTRL-Z)
XOR A ; SIGNAL SUCCESS
RET
#ENDIF
;
;======================================================================
; TMS DRIVER - PRIVATE DRIVER FUNCTIONS

4
Source/HBIOS/uart.asm
View File

@ -569,7 +569,6 @@ UART_DEV .DB 0 ; DEVICE NUM USED DURING INIT
; UART PORT TABLE
;
UART_CFG:
;#IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_ZETA) | (PLATFORM == PLT_ZETA2))
#IF (UARTSBC)
; SBC/ZETA ONBOARD SERIAL PORT
.DB 0 ; DEVICE NUMBER (UPDATED DURING INIT)
@ -579,7 +578,6 @@ UART_CFG:
.DW DEFSERCFG ; LINE CONFIGURATION
.FILL 2,$FF ; FILLER
#ENDIF
;#IF (PLATFORM == PLT_SBC) | (PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4))
#IF (UARTCAS)
; CASSETTE INTERFACE SERIAL PORT
.DB 0 ; DEVICE NUMBER (UPDATED DURING INIT)
@ -589,7 +587,6 @@ UART_CFG:
.DW SER_300_8N1 ; LINE CONFIGURATION
.FILL 2,$FF ; FILLER
#ENDIF
;#IF (PLATFORM == PLT_SBC)
#IF (UARTMFP)
; MF/PIC SERIAL PORT
.DB 0 ; DEVICE NUMBER (UPDATED DURING INIT)
@ -599,7 +596,6 @@ UART_CFG:
.DW DEFSERCFG ; LINE CONFIGURATION
.FILL 2,$FF ; FILLER
#ENDIF
;#IF (PLATFORM == PLT_SBC) | (PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4))
#IF (UART4)
; 4UART SERIAL PORT A
.DB 0 ; DEVICE NUMBER (UPDATED DURING INIT)

10
Source/HBIOS/util.asm
View File

@ -517,7 +517,7 @@ BYTE2BCD1:
POP BC
RET
#IF (PLATFORM != PLT_UNA)
#IF (BIOS == BIOS_WBW)
#IFDEF USEDELAY
@ -543,7 +543,7 @@ DELAY: ; 17TS (FROM INVOKING CALL) |
DELAY1: ; |
; --- LOOP = ((CPUSCL * 16) - 5) TS ------------+ |
DEC A ; 4TS | |
#IFDEF CPU_Z180 ; | |
#IF (CPUFAM == CPU_Z180) ; | |
OR A ; +4TS FOR Z180 | |
#ENDIF ; | |
JR NZ,DELAY1 ; 12TS (NZ) / 7TS (Z) | |
@ -574,7 +574,7 @@ VDELAY: ; 17TS (FROM INVOKING CALL) |
; | |
VDELAY1: ; | |
; --- INNER LOOP = ((CPUSCL * 16) - 5) TS ------+ | |
#IFDEF CPU_Z180 ; | | |
#IF (CPUFAM == CPU_Z180) ; | | |
OR A ; +4TS FOR Z180 | | |
#ENDIF ; | | |
DEC A ; 4TS | | |
@ -582,7 +582,7 @@ VDELAY1: ; | |
; ----------------------------------------------+ | |
; | |
DEC DE ; 6TS | |
#IFDEF CPU_Z180 ; | |
#IF (CPUFAM == CPU_Z180) ; | |
OR A ; +4TS FOR Z180 | |
#ENDIF ; | |
LD A,D ; 4TS | |
@ -610,7 +610,7 @@ LDELAY:
; CPU SCALER := MAX(1, (PHIMHZ - 2))
;
DELAY_INIT:
#IF (PLATFORM == PLT_UNA)
#IF (BIOS == BIOS_UNA)
LD C,$F8 ; UNA BIOS GET PHI FUNCTION
RST 08 ; RETURNS SPEED IN HZ IN DE:HL
LD B,4 ; DIVIDE MHZ IN DE:HL BY 100000H

2
Source/HBIOS/ver.inc
View File

@ -2,4 +2,4 @@
#DEFINE RMN 9
#DEFINE RUP 2
#DEFINE RTP 0
#DEFINE BIOSVER "2.9.2-pre.3"
#DEFINE BIOSVER "2.9.2-pre.4"

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