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@ -205,18 +205,19 @@ SD_TRDR .EQU Z180_TRDR |
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#ENDIF |
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; |
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#IF (SDMODE == SDMODE_MT) ; MT shift register for RC2014 (ref SDMODE_CSIO) |
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SD_DEVCNT .EQU 2 ; NUMBER OF PHYSICAL UNITS (SOCKETS) |
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SD_OPRREG .EQU %00011110 ; Dedicated base address $1C |
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SD_OPRDEF .EQU %00000000 ; QUIESCENT STATE |
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SD_BASE .EQU %01011100 ; Dedicated base address $5C |
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SD_DEVCNT .EQU 1 ; NUMBER OF PHYSICAL UNITS (SOCKETS) |
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SD_OPRREG .EQU SD_BASE+2 ; SD CHIP SELECTOR |
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SD_OPRDEF .EQU %00100000 ; QUIESCENT STATE |
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SD_CD0 .EQU %00000001 ; IN/OUT:SD_OPREG:0 = CD0, PMOD pull CD0 low |
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SD_CD1 .EQU %00000010 ; IN:SD_OPREG:1 = CD1, IN=0 Card detect switch |
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SD_CD2 .EQU %00000100 ; IN:SD_OPREG:2 = CD2, IN=0 Card detect switch |
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SD_CS0 .EQU %00001000 ; IN/OUT:SD_OPREG:3 = CS0, PMOD SPI CS |
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SD_CS0 .EQU %00010000 ; IN/OUT:SD_OPREG:3 = CS0, PMOD SPI CS |
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SD_CS1 .EQU %00010000 ; IN/OUT:SD_OPREG:4 = CS1, SDCARD1 CS, IN=1 Card present |
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SD_CS2 .EQU %00100000 ; IN/OUT:SD_OPREG:5 = CS2, SDCARD2 CS, IN=1 Card present |
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SD_WRTR .EQU %00011100 ; Write data and transfer |
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SD_RDTR .EQU %00011101 ; Read data and transfer |
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SD_RDNTR .EQU %00011100 ; Read data and NO transfer |
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SD_CS2 .EQU %00010000 ; IN/OUT:SD_OPREG:5 = CS2, SDCARD2 CS, IN=1 Card present |
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SD_WRTR .EQU %01011100 ; Write data and transfer |
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SD_RDTR .EQU %01011101 ; Read data and transfer |
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SD_RDNTR .EQU %01011100 ; Read data and NO transfer |
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#ENDIF |
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; |
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; SD CARD COMMANDS |
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@ -580,10 +581,10 @@ SD_PROBE: |
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LD A,SD_OPRDEF |
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OUT (SD_OPRREG),A ; MAKE SURE CONTROL REGISTER IS CLEARED |
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; TEST WITH PMOD NOT CONNECTED |
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IN A,(SD_OPRREG) |
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AND SD_CD0+SD_CS0 ; ISOLATE CD0 AND CS0 |
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CP SD_CD0+SD_CS0 ; BOTH SHOULD BE HIGH |
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JR NZ,SD_PROBE_FAIL ; FAIL IF NOT |
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; IN A,(SD_OPRREG) |
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; AND SD_CD0+SD_CS0 ; ISOLATE CD0 AND CS0 |
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; CP SD_CD0+SD_CS0 ; BOTH SHOULD BE HIGH |
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; JR NZ,SD_PROBE_FAIL ; FAIL IF NOT |
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; TEST CD0 |
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; LD A,SD_CD0 ; D1=DNP CANNOT TEST |
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; OUT (SD_OPRREG),A |
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@ -597,17 +598,20 @@ SD_PROBE: |
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; AND SD_CS0 |
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; JR NZ,SD_PROBE_FAIL ; FAIL IF NOT PULLED LOW |
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; TEST CS1 |
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LD A,SD_CS1 |
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OUT (SD_OPRREG),A |
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IN A,(SD_OPRREG) |
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AND SD_CS1 |
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JR NZ,SD_PROBE_FAIL ; FAIL IF NOT PULLED LOW |
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; TEST CS2 |
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LD A,SD_CS2 |
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OUT (SD_OPRREG),A |
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IN A,(SD_OPRREG) |
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AND SD_CS2 |
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JR NZ,SD_PROBE_FAIL ; FAIL IF NOT PULLED LOW |
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; LD A,SD_CS1 |
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; OUT (SD_OPRREG),A |
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; IN A,(SD_OPRREG) |
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; AND SD_CS1 |
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; JR NZ,SD_PROBE_FAIL ; FAIL IF NOT PULLED LOW |
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; ; TEST CS2 |
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; LD A,SD_CS2 |
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; OUT (SD_OPRREG),A |
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; IN A,(SD_OPRREG) |
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; AND SD_CS2 |
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; JR NZ,SD_PROBE_FAIL ; FAIL IF NOT PULLED LOW |
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LD A,SD_OPRDEF |
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OUT (SD_OPRREG),A ; MAKE SURE CONTROL REGISTER IS CLEARED |
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#ENDIF |
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; |
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XOR A ; SIGNAL SUCCESS |
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