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Merge pull request #34 from wwarthen/master

SDMODE_MT Updates
pull/50/head
b1ackmai1er 6 years ago
committed by GitHub
parent
commit
8c8c09097d
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  1. 50
      Source/HBIOS/sd.asm

50
Source/HBIOS/sd.asm

@ -205,18 +205,19 @@ SD_TRDR .EQU Z180_TRDR
#ENDIF
;
#IF (SDMODE == SDMODE_MT) ; MT shift register for RC2014 (ref SDMODE_CSIO)
SD_DEVCNT .EQU 2 ; NUMBER OF PHYSICAL UNITS (SOCKETS)
SD_OPRREG .EQU %00011110 ; Dedicated base address $1C
SD_OPRDEF .EQU %00000000 ; QUIESCENT STATE
SD_BASE .EQU %01011100 ; Dedicated base address $5C
SD_DEVCNT .EQU 1 ; NUMBER OF PHYSICAL UNITS (SOCKETS)
SD_OPRREG .EQU SD_BASE+2 ; SD CHIP SELECTOR
SD_OPRDEF .EQU %00100000 ; QUIESCENT STATE
SD_CD0 .EQU %00000001 ; IN/OUT:SD_OPREG:0 = CD0, PMOD pull CD0 low
SD_CD1 .EQU %00000010 ; IN:SD_OPREG:1 = CD1, IN=0 Card detect switch
SD_CD2 .EQU %00000100 ; IN:SD_OPREG:2 = CD2, IN=0 Card detect switch
SD_CS0 .EQU %00001000 ; IN/OUT:SD_OPREG:3 = CS0, PMOD SPI CS
SD_CS0 .EQU %00010000 ; IN/OUT:SD_OPREG:3 = CS0, PMOD SPI CS
SD_CS1 .EQU %00010000 ; IN/OUT:SD_OPREG:4 = CS1, SDCARD1 CS, IN=1 Card present
SD_CS2 .EQU %00100000 ; IN/OUT:SD_OPREG:5 = CS2, SDCARD2 CS, IN=1 Card present
SD_WRTR .EQU %00011100 ; Write data and transfer
SD_RDTR .EQU %00011101 ; Read data and transfer
SD_RDNTR .EQU %00011100 ; Read data and NO transfer
SD_CS2 .EQU %00010000 ; IN/OUT:SD_OPREG:5 = CS2, SDCARD2 CS, IN=1 Card present
SD_WRTR .EQU %01011100 ; Write data and transfer
SD_RDTR .EQU %01011101 ; Read data and transfer
SD_RDNTR .EQU %01011100 ; Read data and NO transfer
#ENDIF
;
; SD CARD COMMANDS
@ -580,10 +581,10 @@ SD_PROBE:
LD A,SD_OPRDEF
OUT (SD_OPRREG),A ; MAKE SURE CONTROL REGISTER IS CLEARED
; TEST WITH PMOD NOT CONNECTED
IN A,(SD_OPRREG)
AND SD_CD0+SD_CS0 ; ISOLATE CD0 AND CS0
CP SD_CD0+SD_CS0 ; BOTH SHOULD BE HIGH
JR NZ,SD_PROBE_FAIL ; FAIL IF NOT
; IN A,(SD_OPRREG)
; AND SD_CD0+SD_CS0 ; ISOLATE CD0 AND CS0
; CP SD_CD0+SD_CS0 ; BOTH SHOULD BE HIGH
; JR NZ,SD_PROBE_FAIL ; FAIL IF NOT
; TEST CD0
; LD A,SD_CD0 ; D1=DNP CANNOT TEST
; OUT (SD_OPRREG),A
@ -597,17 +598,20 @@ SD_PROBE:
; AND SD_CS0
; JR NZ,SD_PROBE_FAIL ; FAIL IF NOT PULLED LOW
; TEST CS1
LD A,SD_CS1
OUT (SD_OPRREG),A
IN A,(SD_OPRREG)
AND SD_CS1
JR NZ,SD_PROBE_FAIL ; FAIL IF NOT PULLED LOW
; TEST CS2
LD A,SD_CS2
OUT (SD_OPRREG),A
IN A,(SD_OPRREG)
AND SD_CS2
JR NZ,SD_PROBE_FAIL ; FAIL IF NOT PULLED LOW
; LD A,SD_CS1
; OUT (SD_OPRREG),A
; IN A,(SD_OPRREG)
; AND SD_CS1
; JR NZ,SD_PROBE_FAIL ; FAIL IF NOT PULLED LOW
; ; TEST CS2
; LD A,SD_CS2
; OUT (SD_OPRREG),A
; IN A,(SD_OPRREG)
; AND SD_CS2
; JR NZ,SD_PROBE_FAIL ; FAIL IF NOT PULLED LOW
LD A,SD_OPRDEF
OUT (SD_OPRREG),A ; MAKE SURE CONTROL REGISTER IS CLEARED
#ENDIF
;
XOR A ; SIGNAL SUCCESS

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