mirror of https://github.com/wwarthen/RomWBW.git
Wayne Warthen
1 year ago
committed by
GitHub
GitHub
55 changed files with 2166 additions and 133 deletions
@ -0,0 +1,4 @@ |
|||
{ |
|||
"files.trimTrailingWhitespace": false, |
|||
"files.eol": "\r\n" |
|||
} |
|||
@ -0,0 +1,48 @@ |
|||
FROM ubuntu:jammy-20240111 as basebuilder |
|||
|
|||
# This docker file can be used to build a tool chain docker image for building RomWBW images. |
|||
|
|||
# Tested on a ubuntu host and on Windows un WSL (with docker desktop) |
|||
|
|||
# First build the docker image (will b) |
|||
# docker build --progress plain -t romwbw-chain . |
|||
|
|||
# After you have built the above image (called romwbw-chain), you can use it to compile and build the RomWBW images |
|||
# as per the standard make scripts within RomWBW. |
|||
# Start a new terminal, cd to where you have clone RomWBW, and then run this command: |
|||
# docker run -v ${PWD}:/src/ --privileged=true -u $(id -u ${USER}):$(id -g ${USER}) -it romwbw-chain:latest |
|||
|
|||
# you can now compile and build the required images: |
|||
|
|||
# cd Tools && make |
|||
# cd Source && make # at least once to build many common units |
|||
# cd Source && make rom ROM_PLATFORM=RCEZ80 ROM_CONFIG=std |
|||
|
|||
# when finish, type 'exit' to return to back to your standard terminal session |
|||
|
|||
LABEL Maintainer="Dean Netherton" \ |
|||
Description="spike to use clang for ez80 target" |
|||
|
|||
ENV DEBIAN_FRONTEND=noninteractive |
|||
|
|||
|
|||
RUN dpkg --add-architecture i386 |
|||
RUN sed -i 's/http:\/\/archive\.ubuntu\.com\/ubuntu/http:\/\/au.archive.ubuntu.com\/ubuntu/g' /etc/apt/sources.list |
|||
RUN apt update -y |
|||
RUN apt dist-upgrade -y |
|||
RUN apt install -y --no-install-recommends cmake lzip ca-certificates mtools build-essential dos2unix libboost-all-dev texinfo texi2html libxml2-dev subversion bison flex zlib1g-dev m4 git wget dosfstools curl |
|||
|
|||
RUN mkdir work |
|||
WORKDIR /work |
|||
|
|||
FROM basebuilder as main |
|||
|
|||
LABEL Maintainer="Dean Netherton" \ |
|||
Description="spike to build RomWBW" |
|||
|
|||
RUN mkdir /src |
|||
WORKDIR /src/ |
|||
|
|||
RUN apt install -y --no-install-recommends build-essential libncurses-dev srecord bsdmainutils |
|||
|
|||
RUN adduser --disabled-password --gecos "" builder |
|||
@ -0,0 +1,82 @@ |
|||
; |
|||
;================================================================================================== |
|||
; ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS EZ80 |
|||
;================================================================================================== |
|||
; |
|||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM |
|||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS |
|||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. |
|||
; |
|||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: |
|||
; |
|||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS |
|||
; | |
|||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM |
|||
; | |
|||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD |
|||
; | |
|||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS |
|||
; |
|||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW |
|||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE |
|||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY |
|||
; OVERRIDE THESE SETTINGS AS DESIRED. |
|||
; |
|||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT |
|||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE |
|||
; MODIFIED. |
|||
; |
|||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE |
|||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY |
|||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT |
|||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). |
|||
; |
|||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE |
|||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST |
|||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. |
|||
; |
|||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE |
|||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). |
|||
; |
|||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE |
|||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT |
|||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". |
|||
; |
|||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT |
|||
; |
|||
#INCLUDE "cfg_RCEZ80.asm" |
|||
; |
|||
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ |
|||
; |
|||
FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS |
|||
FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES |
|||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP |
|||
VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD |
|||
;; |
|||
TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) |
|||
TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] |
|||
TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 |
|||
TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) |
|||
VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) |
|||
EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) |
|||
; |
|||
FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) |
|||
FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] |
|||
; |
|||
IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) |
|||
; |
|||
PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) |
|||
; |
|||
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) |
|||
SDMODE .SET SDMODE_PIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80] |
|||
SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY |
|||
PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) |
|||
; |
|||
LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) |
|||
; |
|||
IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) |
|||
; |
|||
SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER |
|||
; |
|||
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER |
|||
AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] |
|||
@ -0,0 +1,428 @@ |
|||
; |
|||
;================================================================================================== |
|||
; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: RCZE80 |
|||
;================================================================================================== |
|||
; |
|||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM |
|||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, |
|||
; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN |
|||
; THE CONFIG DIRECTORY UNDER THIS DIRECTORY. |
|||
; |
|||
; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE |
|||
; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A |
|||
; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY. |
|||
; |
|||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: |
|||
; |
|||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS |
|||
; | |
|||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM |
|||
; | |
|||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD |
|||
; | |
|||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS |
|||
; |
|||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW |
|||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE |
|||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY |
|||
; OVERRIDE THESE SETTINGS AS DESIRED. |
|||
; |
|||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT |
|||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE |
|||
; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE |
|||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY |
|||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT |
|||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). |
|||
; |
|||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE |
|||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST |
|||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. |
|||
; |
|||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE |
|||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT |
|||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". |
|||
; |
|||
#DEFINE PLATFORM_NAME "RCBus", " [", CONFIG, "]" |
|||
; |
|||
#INCLUDE "cfg_MASTER.asm" |
|||
; |
|||
PLATFORM .SET PLT_RCEZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] |
|||
CPUFAM .SET CPU_EZ80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] |
|||
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] |
|||
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE |
|||
HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) |
|||
USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION |
|||
TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) |
|||
; |
|||
BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE |
|||
BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT |
|||
AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT |
|||
; |
|||
CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO |
|||
CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW |
|||
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ |
|||
INTMODE .SET 1 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) |
|||
DEFSERCFG .SET SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) |
|||
; |
|||
RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) |
|||
ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) |
|||
APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) |
|||
MEMMGR .SET MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] |
|||
MPGSEL_0 .SET $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) |
|||
MPGSEL_1 .SET $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) |
|||
MPGSEL_2 .SET $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) |
|||
MPGSEL_3 .SET $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) |
|||
MPGENA .SET $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) |
|||
; |
|||
RTCIO .SET $C0 ; RTC LATCH REGISTER ADR |
|||
; |
|||
KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT |
|||
KIOBASE .SET $80 ; KIO BASE I/O ADDRESS |
|||
; |
|||
CTCENABLE .SET TRUE ; ENABLE ZILOG CTC SUPPORT |
|||
CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT |
|||
CTCBASE .SET $88 ; CTC BASE I/O ADDRESS |
|||
CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER |
|||
CTCMODE .SET CTCMODE_TIM16 ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256] |
|||
CTCPRE .SET 256 ; PRESCALE CONSTANT (1-256) |
|||
CTCPRECH .SET 2 ; PRESCALE CHANNEL (0-3) |
|||
CTCTIMCH .SET 3 ; TIMER CHANNEL (0-3) |
|||
CTCOSC .SET CPUOSC ; CTC CLOCK FREQUENCY |
|||
; |
|||
PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER |
|||
PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS |
|||
; |
|||
EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION |
|||
; |
|||
SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES |
|||
SKZDIV .SET DIV_1 ; UART CLK (CLK2) DIVIDER FOR Z80-512K |
|||
; |
|||
WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] |
|||
WDOGIO .SET $6E ; WATCHDOG REGISTER ADR |
|||
; |
|||
FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS |
|||
FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS |
|||
FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED |
|||
FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS |
|||
FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES |
|||
FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES |
|||
FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED |
|||
; |
|||
DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING |
|||
; |
|||
LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED) |
|||
LEDMODE .SET LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU] |
|||
LEDPORT .SET $0E ; STATUS LED PORT ADDRESS |
|||
LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED |
|||
; |
|||
DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY |
|||
DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY |
|||
ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) |
|||
ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI |
|||
PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259) |
|||
PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI |
|||
PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) |
|||
H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL |
|||
LCDENABLE .SET TRUE ; ENABLE LCD DISPLAY |
|||
LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER |
|||
LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY |
|||
GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD |
|||
; |
|||
BOOTCON .SET 0 ; BOOT CONSOLE DEVICE |
|||
SECCON .SET $FF ; SECONDARY CONSOLE DEVICE |
|||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP |
|||
VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] |
|||
VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD |
|||
ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] |
|||
KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] |
|||
MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] |
|||
; |
|||
DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) |
|||
DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W] |
|||
DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) |
|||
; |
|||
DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) |
|||
DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS |
|||
; |
|||
BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) |
|||
BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS |
|||
; |
|||
INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) |
|||
; |
|||
RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) |
|||
; |
|||
HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT |
|||
SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) |
|||
; |
|||
DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) |
|||
DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] |
|||
; |
|||
DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) |
|||
; |
|||
SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) |
|||
SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG |
|||
SSERSTATUS .SET $FF ; SSER: STATUS PORT |
|||
SSERDATA .SET $FF ; SSER: DATA PORT |
|||
SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK |
|||
SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED |
|||
SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK |
|||
SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED |
|||
; |
|||
DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) |
|||
DUARTCNT .SET 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) |
|||
DUART0BASE .SET $A0 ; DUART 0: BASE ADDRESS OF CHIP |
|||
DUART0ACFG .SET DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG |
|||
DUART0BCFG .SET DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG |
|||
DUART1BASE .SET $40 ; DUART 1: BASE ADDRESS OF CHIP |
|||
DUART1ACFG .SET DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG |
|||
DUART1BCFG .SET DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG |
|||
; |
|||
UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) |
|||
UARTCNT .SET 4 ; UART: NUMBER OF CHIPS TO DETECT (1-8) |
|||
UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ |
|||
UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 |
|||
UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD |
|||
UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD |
|||
UART0BASE .SET $80 ; UART 0: REGISTERS BASE ADR |
|||
UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG |
|||
UART1BASE .SET $88 ; UART 1: REGISTERS BASE ADR |
|||
UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG |
|||
UART2BASE .SET $A0 ; UART 2: REGISTERS BASE ADR |
|||
UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG |
|||
UART3BASE .SET $A8 ; UART 3: REGISTERS BASE ADR |
|||
UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG |
|||
UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR |
|||
UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG |
|||
UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR |
|||
UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG |
|||
UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR |
|||
UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG |
|||
UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR |
|||
UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG |
|||
; |
|||
ASCIENABLE .SET FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) |
|||
; |
|||
Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) |
|||
; |
|||
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) |
|||
ACIADEBUG .SET FALSE ; ACIA: ENABLE DEBUG OUTPUT |
|||
ACIACNT .SET 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2) |
|||
ACIA0BASE .SET $80 ; ACIA 0: REGISTERS BASE ADR |
|||
ACIA0CLK .SET CPUOSC ; ACIA 0: OSC FREQ IN HZ |
|||
ACIA0DIV .SET 1 ; ACIA 0: SERIAL CLOCK DIVIDER |
|||
ACIA0CFG .SET DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM) |
|||
ACIA1BASE .SET $40 ; ACIA 1: REGISTERS BASE ADR |
|||
ACIA1CLK .SET CPUOSC ; ACIA 1: OSC FREQ IN HZ |
|||
ACIA1DIV .SET 1 ; ACIA 1: SERIAL CLOCK DIVIDER |
|||
ACIA1CFG .SET DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM) |
|||
; |
|||
SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) |
|||
SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT |
|||
SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) |
|||
SIOCNT .SET 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP |
|||
SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 |
|||
SIO0MODE .SET SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] |
|||
SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR |
|||
SIO0ACLK .SET CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 |
|||
SIO0ACFG .SET DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG |
|||
SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE |
|||
SIO0BCLK .SET CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 |
|||
SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG |
|||
SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE |
|||
SIO1MODE .SET SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] |
|||
SIO1BASE .SET $84 ; SIO 1: REGISTERS BASE ADR |
|||
SIO1ACLK .SET CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 |
|||
SIO1ACFG .SET DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG |
|||
SIO1ACTCC .SET -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE |
|||
SIO1BCLK .SET CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 |
|||
SIO1BCFG .SET DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG |
|||
SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE |
|||
; |
|||
XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG |
|||
; |
|||
VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) |
|||
CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) |
|||
GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) |
|||
TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) |
|||
TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] |
|||
TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 |
|||
TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) |
|||
VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) |
|||
VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) |
|||
SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) |
|||
EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) |
|||
FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) |
|||
; |
|||
MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) |
|||
MDROM .SET TRUE ; MD: ENABLE ROM DISK |
|||
MDRAM .SET TRUE ; MD: ENABLE RAM DISK |
|||
MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM |
|||
; |
|||
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) |
|||
FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] |
|||
FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) |
|||
FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) |
|||
FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS |
|||
FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] |
|||
FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] |
|||
; |
|||
RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER |
|||
; |
|||
IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) |
|||
IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH |
|||
IDE0MODE .SET IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] |
|||
IDE0BASE .SET $10 ; IDE 0: IO BASE ADDRESS |
|||
IDE0DATLO .SET $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O |
|||
IDE0DATHI .SET $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O |
|||
IDE0A8BIT .SET TRUE ; IDE 0A (MASTER): 8 BIT XFER |
|||
IDE0B8BIT .SET TRUE ; IDE 0B (MASTER): 8 BIT XFER |
|||
IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] |
|||
IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS |
|||
IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O |
|||
IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O |
|||
IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER |
|||
IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER |
|||
IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] |
|||
IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS |
|||
IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O |
|||
IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O |
|||
IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER |
|||
IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER |
|||
; |
|||
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) |
|||
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP |
|||
PPIDE0BASE .SET $20 ; PPIDE 0: PPI REGISTERS BASE ADR |
|||
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER |
|||
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER |
|||
PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR |
|||
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER |
|||
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER |
|||
PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR |
|||
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER |
|||
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER |
|||
; |
|||
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) |
|||
SDMODE .SET SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM] |
|||
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE |
|||
SDCNT .SET 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY |
|||
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE |
|||
SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 |
|||
; |
|||
CHENABLE .SET TRUE ; CH: ENABLE CH375/376 USB SUPPORT |
|||
CHTRACE .SET 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
CHUSBTRACE .SET 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
CHSDTRACE .SET 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
CHCNT .SET 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2) |
|||
CH0BASE .SET $3E ; CH 0: BASE I/O ADDRESS |
|||
CH0USBENABLE .SET TRUE ; CH 0: ENABLE USB DISK |
|||
CH0SDENABLE .SET FALSE ; CH 0: ENABLE SD DISK |
|||
CH1BASE .SET $3C ; CH 1: BASE I/O ADDRESS |
|||
CH1USBENABLE .SET TRUE ; CH 1: ENABLE USB DISK |
|||
CH1SDENABLE .SET FALSE ; CH 1: ENABLE SD DISK |
|||
; |
|||
PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) |
|||
PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT |
|||
PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT |
|||
; |
|||
PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) |
|||
; |
|||
ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) |
|||
; |
|||
HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) |
|||
; |
|||
PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) |
|||
PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP |
|||
PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR |
|||
PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR |
|||
; |
|||
LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) |
|||
LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] |
|||
LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) |
|||
LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
LPT0BASE .SET $0C ; LPT 0: REGISTERS BASE ADR |
|||
LPT1BASE .SET $00 ; LPT 1: REGISTERS BASE ADR |
|||
; |
|||
PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) |
|||
PPACNT .SET 1 ; PPA: NUMBER OF PPA DEVICES (1-2) |
|||
PPATRACE .SET 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
PPAMODE .SET PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014] |
|||
PPA0BASE .SET LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA |
|||
PPA1BASE .SET LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA |
|||
; |
|||
IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) |
|||
IMMCNT .SET 1 ; IMM: NUMBER OF IMM DEVICES (1-2) |
|||
IMMTRACE .SET 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
IMMMODE .SET IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014] |
|||
IMM0BASE .SET LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM |
|||
IMM1BASE .SET LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM |
|||
; |
|||
SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) |
|||
SYQCNT .SET 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2) |
|||
SYQTRACE .SET 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
SYQMODE .SET IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014] |
|||
SYQ0BASE .SET LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ |
|||
SYQ1BASE .SET LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ |
|||
; |
|||
PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD |
|||
PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) |
|||
PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP |
|||
; |
|||
UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) |
|||
; |
|||
SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER |
|||
AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER |
|||
SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD |
|||
SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO] |
|||
; |
|||
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER |
|||
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD |
|||
AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] |
|||
; |
|||
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) |
|||
; |
|||
DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) |
|||
DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS |
|||
DMAMODE .SET DMAMODE_RC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) |
|||
; |
|||
YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER |
|||
VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) |
|||
|
|||
; EZ80 SETTINGS |
|||
; |
|||
EZ80TMR_NONE .SET 0 ; DO NOT USE ON-BOARD TIMER TO GENERATE TICKS |
|||
EZ80TMR_INT .SET 1 ; MARSHALL TIMER TICK INTERRUPTS FROM EZ80 TO HBIOS |
|||
EZ80TMR_FIRM .SET 2 ; DELEGATE SYS TIMER HBIOS CALL TO EZ80 FIRMWARE (TIMER TICK INTS DISABLED) |
|||
|
|||
EZ80UARTENABLE .SET TRUE ; EZ80 UART: ENABLE EZ80 UART0 DRIVER (EZ80UART.ASM) |
|||
EZ80RTCENABLE .SET TRUE ; EZ80 ON CHIP RTC |
|||
EZ80TIMER .SET EZ80TMR_FIRM ; EZ80: TIMER TICK MODEL: EZ80TMR_[INT|FIRM] |
|||
EZ80IOBASE .SET $FF ; EZ80 I/O BASE ADDRESS FOR EXTERNAL IO |
|||
|
|||
; BUS TIMING FOR PAGED MEMORY ACCESS (CS3) |
|||
EZ80_MEM_CYCLES .SET 3 ; MEMORY BUS CYCLES (1-15) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CYCLES |
|||
EZ80_MEM_MIN_NS .SET 100 ; CALCULATE AT BOOT TIME THE REQUIRED W/S OR B/C, IF EZ80_WSMD_TYP = EZ80WSMD_CALC |
|||
EZ80_MEM_WS .SET 5 ; MEMORY WAIT STATES (0-7) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_WAIT |
|||
EZ80_MEM_MIN_WS .SET 0 ; MINIMUM WAIT STATES TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CALC |
|||
|
|||
; BUS TIMING FOR EXTERNAL I/O ACCESS (CS2) |
|||
EZ80_IO_CYCLES .SET 4 ; IO BUS CYCLES (1-15) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CYCLES |
|||
EZ80_IO_WS .SET 5 ; IO WAIT STATES (0-7) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_WAIT |
|||
EZ80_IO_MIN_NS .SET 320 ; CALCULATE AT BOOT TIME THE REQUIRED W/S OR B/C, IF EZ80_WSMD_TYP = EZ80WSMD_CALC |
|||
EZ80_IO_MIN_WS .SET 6 ; MINIMUM WAIT STATES TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CALC |
|||
|
|||
; APPLY CYCLES, W/S OR CALCULATE CYCLES BASED ON DESIRED PERIOD |
|||
EZ80_WSMD_TYP .EQU EZ80WSMD_CALC ; BUS WAIT STATE CONFIG: EZ80WSMD_[CALC|CYCLES|WAIT] |
|||
; |
|||
; BUS TIMING FOR ON CHIP ROM |
|||
; |
|||
EZ80_FLSH_WS .SET 1 ; WAIT STATES FOR ON CHIP FLASH (0-7) |
|||
EZ80_FLSH_MIN_NS .SET 60 ; MINIMUM WAIT STATES TO APPLY TO ON-CHIP FLASH, IF EZ80_WSMD_TYP = EZ80WSMD_CALC |
|||
EZ80_FWSMD_TYP .SET EZ80WSMD_CALC ; WAIT STATE TYPE: EZ80RMMD_[CALC|WAIT] (CYCLES NOT ALLOWED) |
|||
@ -0,0 +1,256 @@ |
|||
; |
|||
;================================================================================================== |
|||
; RCBUS EZ80 CPU DRIVER |
|||
;================================================================================================== |
|||
; |
|||
; Driver code designed for the RCBus eZ80 CPU Module. |
|||
; The driver expects the eZ80 firmware to manage the initial booting of the system. |
|||
; Details for the platform and the software for the on-chip firmware can be found at: |
|||
; https://github.com/dinoboards/rc2014-ez80 |
|||
; |
|||
; Although the eZ80 firmware is booted before HBIOS, the eZ80 CPU driver is still required |
|||
; to communicate with the firmware to perform a number of initialisation tasks. |
|||
; See also the associated ez80 platform drivers (ez80rtc, ez80systmr, ez80uart). |
|||
; |
|||
; The driver 'exports' two key functions: |
|||
; 1. EZ80_PREINIT - This function is called by the HBIOS boot code to initialise the eZ80 firmware. |
|||
; 2. EZ80_RPT_TIMINGS - This function is called by the HBIOS boot code to report the platform timings. |
|||
; |
|||
; EZ80_PREINIT performs the following: |
|||
; 1. Exchange platform version numbers |
|||
; 2. Retrieve CPU Frequency |
|||
; 3. Set Memory and I/O Bus Timings |
|||
; 4. Set Timer Tick Frequency |
|||
; |
|||
|
|||
EZ80_PREINIT: |
|||
EZ80_TMR_INT_DISABLE() |
|||
|
|||
; PROVIDE THE EZ80 FIRMWARE WITH PLATFORM CONFIGUATIONS |
|||
LD C, 1 ; RomWBW'S ASSIGNED CODE |
|||
LD D, RMJ |
|||
LD E, RMN |
|||
LD H, RUP |
|||
LD L, RTP |
|||
|
|||
EZ80_UTIL_VER_EXCH() |
|||
; TODO: MAP THE FIRMWARE CPU TO HBIOS (eZ80 ONLY HAS ONE CPU TYPE AS OF NOW) |
|||
LD A, 5 |
|||
LD (HB_CPUTYPE),A |
|||
|
|||
; DETECT IF USING ALT-FIRMWARE |
|||
LD A, C |
|||
AND $80 |
|||
LD (EZ80_ALT_FIRM), A |
|||
LD (EZ80_PLT_VERSION), HL |
|||
LD (EZ80_PLT_VERSION+2), DE |
|||
|
|||
EXX |
|||
LD A, C |
|||
LD (EZ80_BUILD_DATE), A ; DAY |
|||
LD A, D |
|||
LD (EZ80_BUILD_DATE+1), A ; MONTH |
|||
LD A, E |
|||
LD (EZ80_BUILD_DATE+2), A ; YEAR |
|||
|
|||
EZ80_UTIL_GET_CPU_FQ() |
|||
LD A, E |
|||
LD (CB_CPUMHZ), A |
|||
LD (CB_CPUKHZ), HL |
|||
LD (HB_CPUOSC), HL |
|||
|
|||
#IF (EZ80_FWSMD_TYP == EZ80WSMD_WAIT) |
|||
LD L, EZ80_FLSH_WS |
|||
EZ80_UTIL_FLSHWS_SET() |
|||
LD A, L |
|||
LD (EZ80_PLT_FLSHWS), A |
|||
#ENDIF |
|||
|
|||
#IF (EZ80_FWSMD_TYP == EZ80WSMD_CALC) |
|||
LD HL, EZ80_FLSH_MIN_NS |
|||
LD E, 0 |
|||
EZ80_CPY_EHL_TO_UHL |
|||
EZ80_UTIL_FLSHFQ_SET() |
|||
LD A, L |
|||
LD (EZ80_PLT_FLSHWS), A |
|||
#ENDIF |
|||
|
|||
|
|||
#IF (EZ80_WSMD_TYP == EZ80WSMD_CYCLES) |
|||
LD L, EZ80_MEM_CYCLES |
|||
OR $80 |
|||
EZ80_UTIL_MEMTM_SET() |
|||
LD A, L |
|||
LD (EZ80_PLT_MEMWS), A |
|||
|
|||
LD L, EZ80_IO_CYCLES |
|||
OR $80 |
|||
EZ80_UTIL_IOTM_SET() |
|||
LD A, L |
|||
LD (EZ80_PLT_IOWS), A |
|||
|
|||
RET |
|||
#ENDIF |
|||
|
|||
#IF (EZ80_WSMD_TYP == EZ80WSMD_CALC) |
|||
LD HL, EZ80_MEM_MIN_NS |
|||
LD E, 0 |
|||
EZ80_CPY_EHL_TO_UHL |
|||
LD E, EZ80_MEM_MIN_WS |
|||
EZ80_UTIL_MEMTMFQ_SET |
|||
LD A, L |
|||
LD (EZ80_PLT_MEMWS), A |
|||
|
|||
LD HL, EZ80_IO_MIN_NS |
|||
LD E, 0 |
|||
EZ80_CPY_EHL_TO_UHL |
|||
LD E, EZ80_IO_MIN_WS |
|||
EZ80_UTIL_IOTMFQ_SET |
|||
|
|||
LD A, L |
|||
LD (EZ80_PLT_IOWS), A |
|||
#ENDIF |
|||
#IF (EZ80_WSMD_TYP == EZ80WSMD_WAIT) |
|||
LD L, EZ80_MEM_WS |
|||
EZ80_UTIL_MEMTM_SET() |
|||
LD A, L |
|||
LD (EZ80_PLT_MEMWS), A |
|||
|
|||
LD L, EZ80_IO_WS |
|||
EZ80_UTIL_IOTM_SET() |
|||
LD A, L |
|||
LD (EZ80_PLT_IOWS), A |
|||
#ENDIF |
|||
|
|||
LD C, TICKFREQ |
|||
EZ80_TMR_SET_FREQTICK |
|||
|
|||
RET |
|||
|
|||
EZ80_RPT_TIMINGS: |
|||
LD A, (EZ80_PLT_MEMWS) |
|||
BIT 7, A |
|||
JR NZ, EZ80_RPT_MCYC |
|||
|
|||
CALL PRTDECB |
|||
CALL PRTSTRD |
|||
.TEXT " MEM W/S, $" |
|||
JR EZ80_RPT_IOTIMING |
|||
|
|||
EZ80_RPT_MCYC: |
|||
AND $7F |
|||
CALL PRTDECB |
|||
CALL PRTSTRD |
|||
.TEXT " MEM B/C, $" |
|||
|
|||
EZ80_RPT_IOTIMING: |
|||
LD A, (EZ80_PLT_IOWS) |
|||
BIT 7, A |
|||
JR NZ, EZ80_RPT_ICYC |
|||
|
|||
CALL PRTDECB |
|||
CALL PRTSTRD |
|||
.TEXT " I/O W/S, $" |
|||
JR EZ80_RPT_FSH_TIMINGS |
|||
|
|||
EZ80_RPT_ICYC: |
|||
AND $7F |
|||
CALL PRTDECB |
|||
CALL PRTSTRD |
|||
.TEXT " I/O B/C, $" |
|||
|
|||
EZ80_RPT_FSH_TIMINGS: |
|||
LD A, (EZ80_PLT_FLSHWS) |
|||
CALL PRTDECB |
|||
CALL PRTSTRD |
|||
.TEXT " FSH W/S$" |
|||
RET |
|||
|
|||
EZ80_RPT_FIRMWARE: |
|||
CALL PRTSTRD |
|||
.TEXT "\r\neZ80 Firmware: $" |
|||
|
|||
LD A, (EZ80_PLT_VERSION+3) ; MAJOR VERSION NUMBER |
|||
CALL PRTDECB |
|||
CALL PC_PERIOD |
|||
LD A, (EZ80_PLT_VERSION+2) ; MINOR VERSION NUMBER |
|||
CALL PRTDECB |
|||
CALL PC_PERIOD |
|||
LD A, (EZ80_PLT_VERSION+1) ; REVISION NUMBER |
|||
CALL PRTDECB |
|||
CALL PC_PERIOD |
|||
LD A, (EZ80_PLT_VERSION) ; PATCH NUMBER |
|||
CALL PRTDECB |
|||
|
|||
CALL PRTSTRD |
|||
.TEXT " 20$" |
|||
LD A, (EZ80_BUILD_DATE+2) ; YEAR |
|||
CALL PRTDECB |
|||
CALL PC_DASH |
|||
LD A, (EZ80_BUILD_DATE+1) ; MONTH |
|||
CALL PC_LEADING_ZERO |
|||
CALL PRTDECB |
|||
CALL PC_DASH |
|||
LD A, (EZ80_BUILD_DATE) ; DAY |
|||
CALL PC_LEADING_ZERO |
|||
CALL PRTDECB |
|||
|
|||
LD A, (EZ80_ALT_FIRM) |
|||
OR A |
|||
RET Z |
|||
CALL PRTSTRD |
|||
.TEXT " (ALT)$" |
|||
RET |
|||
|
|||
PC_LEADING_ZERO: |
|||
CP 10 |
|||
RET NC |
|||
|
|||
PUSH AF |
|||
LD A, '0' |
|||
JP PC_PRTCHR |
|||
|
|||
PC_DASH: |
|||
PUSH AF |
|||
LD A, '-' |
|||
JP PC_PRTCHR |
|||
|
|||
EZ80_PLT_MEMWS: |
|||
.DB EZ80_MEM_WS |
|||
EZ80_PLT_IOWS: |
|||
.DB EZ80_IO_WS |
|||
EZ80_PLT_FLSHWS: |
|||
.DB EZ80_FLSH_WS |
|||
|
|||
EZ80_PLT_VERSION: |
|||
.DB 0, 0, 0, 0 |
|||
|
|||
EZ80_ALT_FIRM: |
|||
.DB 0 |
|||
|
|||
EZ80_BUILD_DATE: |
|||
.DB 0, 0, 0 ; DAY, MONTH, YEAR |
|||
|
|||
; ez80 helper functions/instructions |
|||
|
|||
_EZ80_CPY_EHL_TO_UHL: |
|||
PUSH IX |
|||
PUSH AF |
|||
.DB $5B, $DD, $21, $00, $00, $00 ; LD.LIL IX, 0 |
|||
.DB $49, $DD, $39 ; ADD.L IX, SP |
|||
.DB $49, $E5 ; PUSH.L HL |
|||
.DB $5B, $DD, $73, $FF ; LD.LIL (IX-1), E |
|||
.DB $49, $E1 ; POP.L HL |
|||
POP AF |
|||
POP IX |
|||
RET |
|||
|
|||
_EZ80_CPY_UHL_TO_EHL: |
|||
PUSH IX |
|||
.DB $5B, $DD, $21, $00, $00, $00 ; LD.LIL IX, 0 |
|||
.DB $49, $DD, $39 ; ADD.L IX, SP |
|||
.DB $49, $E5 ; PUSH.L HL |
|||
.DB $5B, $DD, $5E, $FF ; LD.LIL E, (IX-1) |
|||
.DB $49, $E1 ; POP.L HL |
|||
POP IX |
|||
RET |
|||
@ -0,0 +1,138 @@ |
|||
; |
|||
;================================================================================================== |
|||
; HELPER MACROS FOR TARGETING EZ80 CPU INSTRUCTIONS |
|||
;================================================================================================== |
|||
|
|||
; |
|||
; EMIT PREFIX REQUIRED BY EZ80 TO ENSURE CORRECT 16 BIT IO OPERATION |
|||
; |
|||
#IF (CPUFAM == CPU_EZ80) |
|||
; RST.L $08 |
|||
#DEFINE EZ80_IO .DB $49, $CF |
|||
; RST.L $10 |
|||
#DEFINE EZ80_FN .DB $49, $D7 |
|||
|
|||
#DEFINE EZ80_UTIL_VER_EXCH XOR A \ LD B, 0 \ EZ80_FN |
|||
#DEFINE EZ80_UTIL_SET_BUSTM XOR A \ LD B, 3 \ EZ80_FN |
|||
#DEFINE EZ80_UTIL_SET_BUSFQ XOR A \ LD B, 4 \ EZ80_FN |
|||
#DEFINE EZ80_UTIL_GET_CPU_FQ XOR A \ LD B, 5 \ EZ80_FN |
|||
#DEFINE EZ80_UTIL_DEBUG XOR A \ LD B, 7 \ EZ80_FN |
|||
#DEFINE EZ80_UTIL_MEMTM_SET XOR A \ LD B, 8 \ EZ80_FN |
|||
#DEFINE EZ80_UTIL_IOTM_SET XOR A \ LD B, 9 \ EZ80_FN |
|||
#DEFINE EZ80_UTIL_MEMTM_GET XOR A \ LD B, 10 \ EZ80_FN |
|||
#DEFINE EZ80_UTIL_IOTM_GET XOR A \ LD B, 11 \ EZ80_FN |
|||
#DEFINE EZ80_UTIL_MEMTMFQ_SET XOR A \ LD B, 12 \ EZ80_FN |
|||
#DEFINE EZ80_UTIL_IOTMFQ_SET XOR A \ LD B, 13 \ EZ80_FN |
|||
#DEFINE EZ80_UTIL_FLSHWS_SET XOR A \ LD B, 14 \ EZ80_FN |
|||
#DEFINE EZ80_UTIL_FLSHWS_GET XOR A \ LD B, 15 \ EZ80_FN |
|||
#DEFINE EZ80_UTIL_FLSHFQ_SET XOR A \ LD B, 16 \ EZ80_FN |
|||
|
|||
#DEFINE EZ80_RTC_INIT LD A, 1 \ LD B, 0 \ EZ80_FN |
|||
#DEFINE EZ80_RTC_GET_TIME LD A, 1 \ LD B, 1 \ EZ80_FN |
|||
#DEFINE EZ80_RTC_SET_TIME LD A, 1 \ LD B, 2 \ EZ80_FN |
|||
|
|||
#DEFINE EZ80_TMR_GET_TICKS LD A, 2 \ LD B, 0 \ EZ80_FN |
|||
#DEFINE EZ80_TMR_GET_SECONDS LD A, 2 \ LD B, 1 \ EZ80_FN |
|||
#DEFINE EZ80_TMR_SET_TICKS LD A, 2 \ LD B, 2 \ EZ80_FN |
|||
#DEFINE EZ80_TMR_SET_SECONDS LD A, 2 \ LD B, 3 \ EZ80_FN |
|||
#DEFINE EZ80_TMR_GET_FREQTICK LD A, 2 \ LD B, 4 \ EZ80_FN |
|||
#DEFINE EZ80_TMR_SET_FREQTICK LD A, 2 \ LD B, 5 \ EZ80_FN |
|||
#DEFINE EZ80_TMR_THROTTLE_START LD A, 2 \ LD B, 6 \ EZ80_FN |
|||
#DEFINE EZ80_TMR_THROTTLE_WAIT LD A, 2 \ LD B, 7 \ EZ80_FN |
|||
#DEFINE EZ80_TMR_INT_DISABLE LD A, 2 \ LD B, 8 \ EZ80_FN |
|||
#DEFINE EZ80_TMR_INT_ENABLE LD A, 2 \ LD B, 9 \ EZ80_FN |
|||
#DEFINE EZ80_TMR_IS_TICK_ISR LD A, 2 \ LD B, 10 \ EZ80_FN |
|||
#DEFINE EZ80_TMR_DELAY LD A, 2 \ LD B, 11 \ EZ80_FN |
|||
|
|||
#DEFINE EZ80_THROTTLE_START(p,store) \ |
|||
#DEFCONT \ PUSH AF |
|||
#DEFCONT \ PUSH BC |
|||
#DEFCONT \ PUSH HL |
|||
#DEFCONT \ LD A, 2 |
|||
#DEFCONT \ LD BC, (6 * 256) + p |
|||
#DEFCONT \ EZ80_FN |
|||
#DEFCONT \ LD (store), HL |
|||
#DEFCONT \ POP HL |
|||
#DEFCONT \ POP BC |
|||
#DEFCONT \ POP AF |
|||
|
|||
#DEFINE EZ80_THROTTLE_WAIT(p,store) \ |
|||
#DEFCONT \ PUSH AF |
|||
#DEFCONT \ PUSH BC |
|||
#DEFCONT \ PUSH HL |
|||
#DEFCONT \ LD A, 2 |
|||
#DEFCONT \ LD BC, (7 * 256) + p |
|||
#DEFCONT \ LD HL, (store) |
|||
#DEFCONT \ EZ80_FN |
|||
#DEFCONT \ LD (store), HL |
|||
#DEFCONT \ POP HL |
|||
#DEFCONT \ POP BC |
|||
#DEFCONT \ POP AF |
|||
|
|||
#DEFINE EZ80_UART_IN LD A, 3 \ LD B, 0 \ EZ80_FN |
|||
#DEFINE EZ80_UART_OUT LD A, 3 \ LD B, 1 \ EZ80_FN |
|||
#DEFINE EZ80_UART_IN_STAT LD A, 3 \ LD B, 2 \ EZ80_FN |
|||
#DEFINE EZ80_UART_OUT_STAT LD A, 3 \ LD B, 3 \ EZ80_FN |
|||
#DEFINE EZ80_UART_CONFIG LD A, 3 \ LD B, 4 \ EZ80_FN |
|||
#DEFINE EZ80_UART_QUERY LD A, 3 \ LD B, 5 \ EZ80_FN |
|||
#DEFINE EZ80_UART_RESET LD A, 3 \ LD B, 6 \ EZ80_FN |
|||
|
|||
#DEFINE RET.L .DB $49 \ RET |
|||
|
|||
#DEFINE IN0_A(p) .DB $ED,$38,p |
|||
#DEFINE IN0_B(p) .DB $ED,$00,p |
|||
#DEFINE IN0_C(p) .DB $ED,$08,p |
|||
#DEFINE IN0_D(p) .DB $ED,$10,p |
|||
#DEFINE IN0_E(p) .DB $ED,$18,p |
|||
#DEFINE IN0_H(p) .DB $ED,$20,p |
|||
#DEFINE IN0_L(p) .DB $ED,$28,p |
|||
|
|||
#DEFINE OUT0_A(p) .DB $ED,$39,p |
|||
#DEFINE OUT0_B(p) .DB $ED,$01,p |
|||
#DEFINE OUT0_C(p) .DB $ED,$09,p |
|||
#DEFINE OUT0_D(p) .DB $ED,$11,p |
|||
#DEFINE OUT0_E(p) .DB $ED,$19,p |
|||
#DEFINE OUT0_H(p) .DB $ED,$21,p |
|||
#DEFINE OUT0_L(p) .DB $ED,$29,p |
|||
|
|||
#DEFINE LDHLMM.LIL(Mmn) \ |
|||
#defcont \ .DB $5B |
|||
#defcont \ LD HL, Mmn |
|||
#defcont \ .DB (Mmn >> 16) & $FF |
|||
|
|||
#DEFINE LDBCMM.LIL(Mmn) \ |
|||
#defcont \ .DB $5B |
|||
#defcont \ LD BC, Mmn |
|||
#defcont \ .DB (Mmn >> 16) & $FF |
|||
|
|||
#DEFINE SBCHLBC.LIL \ |
|||
#defcont \ .DB $49 |
|||
#defcont \ SBC HL, BC |
|||
|
|||
IO_SEGMENT .EQU $FF ; THE UPPER 8-BIT ADDRESS FOR I/O |
|||
|
|||
#DEFINE OUT_NN_A(addr) \ |
|||
#DEFCONT \ PUSH BC |
|||
#DEFCONT \ LD BC, IO_SEGMENT << 8 | addr |
|||
#DEFCONT \ OUT (C), A |
|||
#DEFCONT \ POP BC |
|||
|
|||
#DEFINE IN_A_NN(addr) \ |
|||
#DEFCONT \ LD A, IO_SEGMENT |
|||
#DEFCONT \ IN A, (addr) |
|||
|
|||
#define EZ80_CPY_EHL_TO_UHL CALL _EZ80_CPY_EHL_TO_UHL |
|||
#define EZ80_CPY_UHL_TO_EHL CALL _EZ80_CPY_UHL_TO_EHL |
|||
|
|||
#ELSE |
|||
#DEFINE EZ80_IO |
|||
|
|||
#DEFINE EZ80_THROTTLE_START(p,store) |
|||
#DEFINE EZ80_THROTTLE_WAIT(p,store) |
|||
|
|||
IO_SEGMENT .EQU $FF ; THE UPPER 8-BIT ADDRESS FOR I/O |
|||
|
|||
#DEFINE OUT_NN_A(addr) OUT (addr), A |
|||
#DEFINE IN_A_NN(addr) IN A, (addr) |
|||
|
|||
#ENDIF |
|||
@ -0,0 +1,168 @@ |
|||
; |
|||
;================================================================================================== |
|||
; EZ80 ON-CHIP RTC DRIVER |
|||
;================================================================================================== |
|||
; |
|||
EZ80RTC_BUFSIZ .EQU 6 ; SIX BYTE BUFFER (YYMMDDHHMMSS) |
|||
; |
|||
; RTC DEVICE INITIALIZATION ENTRY |
|||
|
|||
EZ80RTC_INIT: |
|||
; display driver install message |
|||
; delegate init function to firmware |
|||
; install dispatcher |
|||
; dispatch local routine that delgates to firmware routines |
|||
|
|||
LD A, (RTC_DISPACT) ; RTC DISPATCHER ALREADY SET? |
|||
OR A ; SET FLAGS |
|||
RET NZ ; IF ALREADY ACTIVE, ABORT |
|||
|
|||
CALL NEWLINE ; FORMATTING |
|||
PRTS("EZ80 RTC: POWERED $") |
|||
|
|||
EZ80_RTC_INIT() |
|||
JR Z, RTC_POWERED |
|||
|
|||
PUSH AF |
|||
PRTS("NOT POWERED$") |
|||
POP AF |
|||
RET |
|||
|
|||
RTC_POWERED: |
|||
; DISPLAY CURRENT TIME |
|||
LD HL, EZ80RTC_BCDBUF_EXT ; POINT TO BCD BUF EXTENDED |
|||
EZ80_RTC_GET_TIME() |
|||
|
|||
LD HL, EZ80RTC_BCDBUF ; POINT TO BCD BUF |
|||
CALL PRTDT ; DISPLAY THIS TIME |
|||
; |
|||
LD BC, EZ80RTC_DISPATCH |
|||
CALL RTC_SETDISP |
|||
; |
|||
XOR A ; SIGNAL SUCCESS |
|||
RET |
|||
|
|||
; |
|||
; RTC DEVICE FUNCTION DISPATCH ENTRY |
|||
; A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR |
|||
; B: FUNCTION (IN) |
|||
; |
|||
EZ80RTC_DISPATCH: |
|||
LD A,B ; GET REQUESTED FUNCTION |
|||
AND $0F ; ISOLATE SUB-FUNCTION |
|||
JP Z,EZ80RTC_GETTIM ; GET TIME |
|||
DEC A |
|||
JP Z,EZ80RTC_SETTIM ; SET TIME |
|||
DEC A |
|||
JP Z,EZ80RTC_GETBYT ; GET NVRAM BYTE VALUE |
|||
DEC A |
|||
JP Z,EZ80RTC_SETBYT ; SET NVRAM BYTE VALUE |
|||
DEC A |
|||
JP Z,EZ80RTC_GETBLK ; GET NVRAM DATA BLOCK VALUES |
|||
DEC A |
|||
JP Z,EZ80RTC_SETBLK ; SET NVRAM DATA BLOCK VALUES |
|||
DEC A |
|||
JP Z,EZ80RTC_GETALM ; GET ALARM |
|||
DEC A |
|||
JP Z,EZ80RTC_SETALM ; SET ALARM |
|||
DEC A |
|||
JP Z,EZ80RTC_DEVICE ; REPORT RTC DEVICE INFO |
|||
SYSCHKERR(ERR_NOFUNC) |
|||
RET |
|||
; |
|||
; RTC GET TIME |
|||
; A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR |
|||
; HL: DATE/TIME BUFFER (OUT) |
|||
; BUFFER FORMAT IS BCD: YYMMDDHHMMSS |
|||
; 24 HOUR TIME FORMAT IS ASSUMED |
|||
; |
|||
EZ80RTC_GETTIM: |
|||
PUSH HL |
|||
LD HL, EZ80RTC_BCDBUF_EXT ; POINT TO BCD BUF EXTENDED |
|||
EZ80_RTC_GET_TIME() ; (HL) <- TIME |
|||
|
|||
LD A, BID_BIOS ; COPY FROM BIOS BANK |
|||
LD (HB_SRCBNK), A ; SET IT |
|||
LD A, (HB_INVBNK) ; COPY TO CURRENT USER BANK |
|||
LD (HB_DSTBNK), A ; SET IT |
|||
LD HL, EZ80RTC_BCDBUF ; SOURCE ADR |
|||
POP DE ; DEST ADR |
|||
LD BC, EZ80RTC_BUFSIZ ; LENGTH |
|||
CALL HB_BNKCPY ; COPY THE CLOCK DATA |
|||
|
|||
XOR A ; SIGNAL SUCCESS |
|||
RET |
|||
; |
|||
; |
|||
; RTC SET TIME |
|||
; A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR |
|||
; HL: DATE/TIME BUFFER (IN) |
|||
; BUFFER FORMAT IS BCD: YYMMDDHHMMSSWW |
|||
; 24 HOUR TIME FORMAT IS ASSUMED |
|||
; |
|||
EZ80RTC_SETTIM: |
|||
; COPY TO BCD BUF |
|||
LD A,(HB_INVBNK) ; COPY FROM CURRENT USER BANK |
|||
LD (HB_SRCBNK),A ; SET IT |
|||
LD A,BID_BIOS ; COPY TO BIOS BANK |
|||
LD (HB_DSTBNK),A ; SET IT |
|||
LD DE,EZ80RTC_BCDBUF ; DEST ADR |
|||
LD BC,EZ80RTC_BUFSIZ ; LENGTH |
|||
CALL HB_BNKCPY ; COPY THE RPC DATA |
|||
|
|||
LD HL, EZ80RTC_BCDBUF_EXT ; POINT TO BCD BUF EXTENDED |
|||
LD (HL), $20 ; CENTURY NOT SUPPORT BY HBIOS |
|||
EZ80_RTC_SET_TIME() ; (HL) -> SYSTEM TIME |
|||
|
|||
XOR A ; SIGNAL SUCCESS |
|||
RET |
|||
; |
|||
; RTC GET NVRAM BYTE |
|||
; C: INDEX |
|||
; E: VALUE (OUTPUT) |
|||
; A:0 IF OK, ERR_RANGE IF OUT OF RANGE |
|||
; |
|||
EZ80RTC_GETBYT: |
|||
SYSCHKERR(ERR_NOTIMPL) |
|||
; XOR A ; SIGNAL SUCCESS |
|||
RET ; AND RETURN |
|||
|
|||
|
|||
; RTC SET NVRAM BYTE |
|||
; C: INDEX |
|||
; E: VALUE |
|||
; A:0 IF OK, ERR_RANGE IF OUT OF RANGE |
|||
; |
|||
EZ80RTC_SETBYT: |
|||
SYSCHKERR(ERR_NOTIMPL) |
|||
; XOR A ; SIGNAL SUCCESS |
|||
RET |
|||
|
|||
EZ80RTC_GETBLK: |
|||
EZ80RTC_SETBLK: |
|||
EZ80RTC_GETALM: |
|||
EZ80RTC_SETALM: |
|||
SYSCHKERR(ERR_NOTIMPL) |
|||
RET |
|||
; |
|||
; REPORT RTC DEVICE INFO |
|||
; |
|||
EZ80RTC_DEVICE: |
|||
LD D, RTCDEV_EZ80 ; D := DEVICE TYPE |
|||
LD E, 0 ; E := PHYSICAL DEVICE NUMBER |
|||
LD HL, 00 ; H := 0, DRIVER HAS NO MODES, L := 0, NO I/O ADDRESS |
|||
XOR A ; SIGNAL SUCCESS |
|||
RET |
|||
|
|||
|
|||
; REGISTER EXTRACTED VALUES |
|||
; |
|||
EZ80RTC_BCDBUF_EXT: |
|||
EZ80RTC_CN .DB 20 ; CENTURY |
|||
EZ80RTC_BCDBUF: |
|||
EZ80RTC_YR .DB 24 |
|||
EZ80RTC_MO .DB 01 |
|||
EZ80RTC_DT .DB 01 |
|||
EZ80RTC_HH .DB 00 |
|||
EZ80RTC_MM .DB 00 |
|||
EZ80RTC_SS .DB 00 |
|||
@ -0,0 +1,86 @@ |
|||
; |
|||
;================================================================================================== |
|||
; EZ80 50/60HZ TIMER TICK DRIVER |
|||
;================================================================================================== |
|||
; |
|||
; Configuration options: |
|||
; EZ80TIMER: |
|||
; 0 -> No timer tick interrupts MARSHALLED to HBIOS. |
|||
; HBIOS System calls SYS_GETTIMER, SYS_GETSECS, SYS_SETTIMER, SYS_SETSECS are implemented here and DELEGATED to eZ80 firmware functions |
|||
; 1 -> Timer tick interrupts MARSHALLED to HBIOS. |
|||
; HBIOS System calls SYS_GETTIMER, SYS_GETSECS, SYS_SETTIMER, SYS_SETSECS are implemented within HBIOS |
|||
; |
|||
|
|||
#IF (EZ80TIMER == EZ80TMR_INT) |
|||
EZ80_TMR_INIT: |
|||
CALL NEWLINE ; FORMATTING |
|||
PRTS("EZ80 TIMER: INTERRUPTS ENABLED$") |
|||
|
|||
LD HL,EZ80_TMR_INT ; GET INT VECTOR |
|||
CALL HB_ADDIM1 ; ADD TO IM1 CALL LIST |
|||
|
|||
EZ80_TMR_INT_ENABLE() ; INSTALL TIMER HOOK |
|||
RET |
|||
|
|||
EZ80_TMR_INT: |
|||
EZ80_TMR_IS_TICK_ISR() |
|||
RET Z ; NOT A EZ80 TIMER TICK |
|||
|
|||
CALL HB_TIMINT ; RETURN NZ - HANDLED |
|||
OR $FF |
|||
RET |
|||
#ENDIF |
|||
#IF (EZ80TIMER == EZ80TMR_FIRM) |
|||
|
|||
EZ80_TMR_INIT: |
|||
CALL NEWLINE ; FORMATTING |
|||
PRTS("EZ80 TIMER: FIRMWARE$") |
|||
RET |
|||
; ----------------------------------------------- |
|||
; Implementation of HBIOS SYS TIMER functions to |
|||
; delegate to eZ80 firmware functions |
|||
|
|||
; GET TIMER |
|||
; RETURNS: |
|||
; DE:HL: TIMER VALUE (32 BIT) |
|||
; |
|||
SYS_GETTIMER: |
|||
EZ80_TMR_GET_TICKS() |
|||
RET |
|||
; |
|||
; GET SECONDS |
|||
; RETURNS: |
|||
; DE:HL: SECONDS VALUE (32 BIT) |
|||
; C: NUM TICKS WITHIN CURRENT SECOND |
|||
; |
|||
SYS_GETSECS: |
|||
EZ80_TMR_GET_SECONDS() |
|||
|
|||
EZ80_CPY_UHL_TO_EHL ; E:HL{15:0} <- HL{23:0} |
|||
LD D, 0 |
|||
RET |
|||
; |
|||
; SET TIMER |
|||
; ON ENTRY: |
|||
; DE:HL: TIMER VALUE (32 BIT) |
|||
; |
|||
SYS_SETTIMER: |
|||
EZ80_CPY_EHL_TO_UHL ; HL{23:0} <- E:HL{15:0} |
|||
EZ80_TMR_SET_TICKS() |
|||
RET |
|||
; |
|||
; SET SECS |
|||
; ON ENTRY: |
|||
; DE:HL: SECONDS VALUE (32 BIT) |
|||
; |
|||
SYS_SETSECS: |
|||
EZ80_CPY_EHL_TO_UHL ; HL{23:0} <- E:HL{15:0} |
|||
|
|||
EZ80_TMR_SET_SECONDS() |
|||
RET |
|||
|
|||
#ENDIF |
|||
#IF (EZ80TIMER == EZ80TMR_NONE) |
|||
EZ80_TMR_INIT: |
|||
RET |
|||
#ENDIF |
|||
@ -0,0 +1,323 @@ |
|||
; |
|||
;================================================================================================== |
|||
; eZ80 UART DRIVER (SERIAL PORT) |
|||
;================================================================================================== |
|||
; |
|||
; |
|||
; Supported Line Characteristics are encoded as follows in the DE register pair: |
|||
; |
|||
; | **Bits** | **Characteristic** | |
|||
; |---------:|----------------------------------------| |
|||
; | 15-14 | Reserved (set to 0) | |
|||
; | 13 | RTS (Not implemented) | |
|||
; | 12-8 | Baud Rate* (see below) | |
|||
; | 7 | DTR (Not implemented) | |
|||
; | 6 | XON/XOFF Flow Control (not implemented)| |
|||
; | 5 | Stick Parity (not implemented) | |
|||
; | 4 | Even Parity (set for true) | |
|||
; | 3 | Parity Enable (set for true) | |
|||
; | 2 | Stop Bits (0-> 1 BIT, 1-> 2 BITS) | |
|||
; | 1-0 | Data Bits (5-8 encoded as 0-3) | |
|||
; |
|||
; * The 5-bit Baud Rate value (V) is encoded as V = 75 * 2^X * 3^Y. The |
|||
; bits are defined as YXXXX. |
|||
; |
|||
; STICK & EVEN & PARITY -> MARK PARITY -> NOT SUPPORTED |
|||
; STICK & !EVEN & PARITY -> SPACE PARITY -> NOT SUPPORTED |
|||
; THEREFORE, MARK PARITY WILL BE INTERPRETED AS EVEN PARITY |
|||
; AND SPACE PARITY WILL BE INTERPRETED AS ODD PARITY |
|||
|
|||
UART0_LSR .EQU $C5 |
|||
UART0_THR .EQU $C0 |
|||
UART0_RBR .EQU $C0 |
|||
|
|||
LSR_THRE .EQU $20 |
|||
LSR_DR .EQU $01 |
|||
|
|||
EZUART_PREINIT: |
|||
LD BC, EZUART_FNTBL |
|||
LD DE, EZUART_CFG |
|||
CALL CIO_ADDENT |
|||
LD (EZUART_ID), A |
|||
|
|||
XOR A |
|||
RET |
|||
|
|||
EZUART_INIT: |
|||
CALL NEWLINE ; FORMATTING |
|||
PRTS("EZ80 UART: UART0$") |
|||
|
|||
XOR A |
|||
RET |
|||
; |
|||
; ### Function 0x00 -- Character Input (CIOIN) |
|||
; |
|||
; Read and return a Character (E). If no character(s) are available in the |
|||
; input buffer, this function will wait indefinitely. The returned Status |
|||
; (A) is a standard HBIOS result code. |
|||
; |
|||
; Outputs: |
|||
; E: Character |
|||
; A: Status (0-OK, else error) |
|||
; |
|||
EZUART_IN: |
|||
EZ80_UART_IN() ; CHAR RETURNED IN E |
|||
RET |
|||
; |
|||
; ### Function 0x01 -- Character Output (CIOOUT) |
|||
; |
|||
; Send the Character (E). If there is no space available in the unit's output |
|||
; buffer, the function will wait indefinitely. The returned Status (A) is a |
|||
; standard HBIOS result code. |
|||
; |
|||
; Inputs: |
|||
; E: Character |
|||
; |
|||
; Outputs: |
|||
; A: Status (0-OK, else error) |
|||
; |
|||
EZUART_OUT: |
|||
EZ80_UART_OUT() |
|||
RET |
|||
; |
|||
; ### Function 0x02 -- Character Input Status (CIOIST) |
|||
; |
|||
; Return the count of Characters Pending (A) in the input buffer. |
|||
; |
|||
; The value returned in register A is used as both a Status (A) code and |
|||
; the return value. Negative values (bit 7 set) indicate a standard HBIOS |
|||
; result (error) code. Otherwise, the return value represents the number |
|||
; of characters in the input buffer. |
|||
; |
|||
; Outputs: |
|||
; A: Status / Characters Pending |
|||
; |
|||
EZUART_IST: |
|||
EZ80_UART_IN_STAT() |
|||
RET |
|||
; |
|||
; ### Function 0x03 -- Character Output Status (CIOOST) |
|||
; |
|||
; Return the status of the output FIFO. 0 means the output FIFO is full and |
|||
; no more characters can be sent. 1 means the output FIFO is not full and at |
|||
; least one character can be sent. Negative values (bit 7 set) indicate a |
|||
; standard HBIOS result (error) code. |
|||
; |
|||
; Outputs |
|||
; A: Status (0 -> Full, 1 -> OK to send, < 0 -> HBIOS error code) |
|||
; |
|||
EZUART_OST: |
|||
EZ80_UART_OUT_STAT() |
|||
RET |
|||
|
|||
BAUD_RATE .EQU 115200 |
|||
; |
|||
; ### Function 0x04 -- Character I/O Initialization (CIOINIT) |
|||
; |
|||
; Apply the requested line Characteristics in (DE). The definition of the |
|||
; line characteristics value is described above. If DE contains -1 (0xFFFF), |
|||
; then the input and output buffers will be flushed and reset. |
|||
; The Status (A) is a standard HBIOS result code. |
|||
; |
|||
; Inputs: |
|||
; DE: Line Characteristics |
|||
; |
|||
; Outputs: |
|||
; A: Status (0-OK, else error) |
|||
; |
|||
EZUART_INITDEV: |
|||
LD A, D |
|||
CP E |
|||
JR NZ, NOT_RESET |
|||
CP $FF |
|||
JR NZ, NOT_RESET |
|||
|
|||
EZ80_UART_RESET() |
|||
RET |
|||
|
|||
NOT_RESET: |
|||
PUSH DE ; SAVE LINE CHARACTERISTICS |
|||
LD A, D |
|||
AND $1F ; ISOLATE ENCODED BAUD RATE |
|||
LD L, A ; PUT IN L |
|||
LD H, 0 ; H IS ALWAYS ZERO |
|||
LD DE, 75 ; BAUD RATE DECODE CONSTANT |
|||
CALL DECODE ; DE:HL := BAUD RATE |
|||
|
|||
EZ80_CPY_EHL_TO_UHL ; HL{23:0} <- E:HL{15:0} |
|||
|
|||
POP DE ; RESTORE REQUESTED LINE CHARACTERISTICS |
|||
LD A, E |
|||
AND 3 ; MASK FOR DATA BITS |
|||
RLCA |
|||
RLCA |
|||
RLCA ; SHIFT TO BITS 4:3 |
|||
LD D, A ; SAVE INTO D |
|||
|
|||
BIT 2, E ; STOP BITS (1 OR 2) |
|||
JR Z, ISKIP1 |
|||
SET 2, D ; APPLY TO D |
|||
ISKIP1: |
|||
|
|||
BIT 3, E ; PARITY ENABLE |
|||
JR Z, ISKIP2 |
|||
SET 1, D ; APPLY TO D |
|||
ISKIP2: |
|||
|
|||
BIT 4, E ; EVEN PARITY |
|||
JR Z, ISKIP3 |
|||
SET 0, D ; APPLY TO D |
|||
ISKIP3: |
|||
|
|||
; D NOW CONTAINS THE LINE CONTROL BITS AS PER EZ80 FUNCTION |
|||
|
|||
EZ80_UART_CONFIG() |
|||
RET |
|||
|
|||
#DEFINE TRANSLATE(nnn,rrr) \ |
|||
#defcont \ LDBCMM.LIL(nnn) |
|||
#defcont \ SBCHLBC.LIL |
|||
#defcont \ JR NC, $+7 |
|||
#defcont \ LD D, rrr |
|||
#defcont \ JP uart_query_end |
|||
; |
|||
; ### Function 0x05 -- Character I/O Query (CIOQUERY) |
|||
; |
|||
; Returns the current Line Characteristics (DE). The definition of the line |
|||
; characteristics value is described above. The returned status (A) is a |
|||
; standard HBIOS result code. |
|||
; |
|||
; As the eZ80 UART driver supports more than the defined HBIOS baud rates, the |
|||
; returned baud rate may be an approximation of the actual baud rate. |
|||
; |
|||
; Outputs: |
|||
; DE: Line Characteristics |
|||
; A: Status (0-OK, else error) |
|||
; |
|||
EZUART_QUERY: |
|||
EZ80_UART_QUERY() |
|||
; HL{23:0} := BAUD RATE |
|||
; D = LINE CONTROL BITS |
|||
PUSH DE ; SAVE D |
|||
|
|||
OR A |
|||
; HL24 bit has the baud rate, we need to convert to the 5 bit representation? |
|||
TRANSLATE(112, 00000b) ; BAUDRATE=75 (BETWEEN 0 AND 112) |
|||
TRANSLATE(187-112, 00001b) ; BAUDRATE=150 (BETWEEN 113 AND 187) |
|||
TRANSLATE(262-187, 10000b) ; BAUDRATE=225 (BETWEEN 188 AND 262) |
|||
TRANSLATE(375-262, 00010b) ; BAUDRATE=300 (BETWEEN 263 AND 375) |
|||
TRANSLATE(525-375, 10001b) ; BAUDRATE=450 (BETWEEN 376 AND 525) |
|||
TRANSLATE(750-525, 00011b) ; BAUDRATE=600 (BETWEEN 526 AND 750) |
|||
TRANSLATE(1050-750, 10010b) ; BAUDRATE=900 (BETWEEN 751 AND 1050) |
|||
TRANSLATE(1500-1050, 00100b) ; BAUDRATE=1200 (BETWEEN 1051 AND 1500) |
|||
TRANSLATE(2100-1500, 10011b) ; BAUDRATE=1800 (BETWEEN 1501 AND 2100) |
|||
TRANSLATE(3000-2100, 00101b) ; BAUDRATE=2400 (BETWEEN 2101 AND 3000) |
|||
TRANSLATE(4200-3000, 10100b) ; BAUDRATE=3600 (BETWEEN 3001 AND 4200) |
|||
TRANSLATE(6000-4200, 00110b) ; BAUDRATE=4800 (BETWEEN 4201 AND 6000) |
|||
TRANSLATE(8400-6000, 10101b) ; BAUDRATE=7200 (BETWEEN 6001 AND 8400) |
|||
TRANSLATE(12000-8400, 00111b) ; BAUDRATE=9600 (BETWEEN 8401 AND 12000) |
|||
TRANSLATE(16800-12000, 10110b) ; BAUDRATE=14400 (BETWEEN 12001 AND 16800) |
|||
TRANSLATE(24000-16800, 01000b) ; BAUDRATE=19200 (BETWEEN 16801 AND 24000) |
|||
TRANSLATE(33600-24000, 10111b) ; BAUDRATE=28800 (BETWEEN 24001 AND 33600) |
|||
TRANSLATE(48000-33600, 01001b) ; BAUDRATE=38400 (BETWEEN 33601 AND 48000) |
|||
TRANSLATE(67200-48000, 11000b) ; BAUDRATE=57600 (BETWEEN 48001 AND 67200) |
|||
TRANSLATE(96000-67200, 01010b) ; BAUDRATE=76800 (BETWEEN 67201 AND 96000) |
|||
TRANSLATE(134400-96000, 11001b) ; BAUDRATE=115200 (BETWEEN 96001 AND 134400) |
|||
TRANSLATE(192000-134400, 01011b) ; BAUDRATE=153600 (BETWEEN 134401 AND 192000) |
|||
TRANSLATE(268800-192000, 11010b) ; BAUDRATE=230400 (BETWEEN 192001 AND 268800) |
|||
TRANSLATE(384000-268800, 01100b) ; BAUDRATE=307200 (BETWEEN 268801 AND 384000) |
|||
TRANSLATE(537600-384000, 11011b) ; BAUDRATE=460800 (BETWEEN 384001 AND 537600) |
|||
TRANSLATE(768000-537600, 01101b) ; BAUDRATE=614400 (BETWEEN 537601 AND 768000) |
|||
TRANSLATE(1075200-768000, 11100b) ; BAUDRATE=921600 (BETWEEN 768001 AND 1075200) |
|||
TRANSLATE(1536000-1075200, 01110b) ; BAUDRATE=1228800 (BETWEEN 1075201 AND 1536000) |
|||
TRANSLATE(2150400-1536000, 11101b) ; BAUDRATE=1843200 (BETWEEN 1536001 AND 2150400) |
|||
TRANSLATE(3072000-2150400, 01111b) ; BAUDRATE=2457600 (BETWEEN 2150401 AND 3072000) |
|||
TRANSLATE(5529600-3072000, 11110b) ; BAUDRATE=3686400 (BETWEEN 3072001 AND 5529600) |
|||
|
|||
LD D, 11111b ; BAUDRATE=7372800 (>=5529601) |
|||
uart_query_end: |
|||
|
|||
POP BC ; B = LINE CONTROL BITS |
|||
|
|||
; Convert from line control settings from: |
|||
; |
|||
; B{0:1} = Parity (00 -> NONE, 01 -> NONE, 10 -> ODD, 11 -> EVEN) |
|||
; B{2} = Stop Bits (0 -> 1, 1 -> 2) |
|||
; B{3:4} = Data Bits (00 -> 5, 01 -> 6, 10 -> 7, 11 -> 8) |
|||
; B{5:5} = Hardware Flow Control CTS (0 -> OFF, 1 -> ON) |
|||
; |
|||
; to |
|||
; |
|||
; E{7} = TODO: DTR |
|||
; E{6} = NOT IMPLEMENTED: XON/XOFF Flow Control |
|||
; E{5} = NOT SUPPORTED: Stick Parity (set for true) |
|||
; E{4} = Even Parity (set for true) |
|||
; E{3} = Parity Enable (set for true) |
|||
; E{2} = Stop Bits (set for true) |
|||
; E{1:0} = Data Bits (5-8 encoded as 0-3) |
|||
|
|||
XOR A |
|||
OR 3 << 3 ; ISOLATE DATA BITS |
|||
AND B ; MASK IN DATA BITS |
|||
|
|||
RRCA ; SHIFT TO BITS 1:0 |
|||
RRCA |
|||
RRCA |
|||
LD H, A ; H{1:0} DATA BITS |
|||
|
|||
BIT 2, B ; STOP BITS |
|||
JR Z, SKIP1 |
|||
SET 2, H ; APPLY TO H |
|||
|
|||
SKIP1: |
|||
BIT 1, B ; PARITY ENABLE |
|||
JR Z, SKIP2 |
|||
SET 3, H ; APPLY TO H |
|||
|
|||
SKIP2: |
|||
BIT 0, B ; EVEN PARITY |
|||
JR Z, SKIP3 |
|||
SET 4, H ; APPLY TO H |
|||
|
|||
SKIP3: |
|||
LD E, H |
|||
XOR A |
|||
RET |
|||
; |
|||
; ### Function 0x06 -- Character I/O Device (CIODEVICE) |
|||
; |
|||
; Returns device information. The status (A) is a standard HBIOS result |
|||
; code. |
|||
; |
|||
; Outputs |
|||
; A: Status (0 - OK) |
|||
; C: Device Attribute (0 - RS/232) |
|||
; D: Device Type (CIODEV_EZ80UART) |
|||
; E: Physical Device Number |
|||
; H: Device Mode (0) |
|||
; L: Device I/O Base Address - Not Supported (0) |
|||
; |
|||
EZUART_DEVICE: |
|||
LD D, CIODEV_EZ80UART ; D := DEVICE TYPE |
|||
LD E, (IY) ; E := PHYSICAL UNIT |
|||
LD C, 0 ; C := DEVICE TYPE, 0x00 IS RS-232 |
|||
LD HL, 0 ; H := MODE, L := BASE I/O ADDRESS |
|||
|
|||
XOR A ; SIGNAL SUCCESS |
|||
RET |
|||
|
|||
EZUART_CFG: |
|||
EZUART_ID: .DB 0 |
|||
|
|||
|
|||
EZUART_FNTBL: |
|||
.DW EZUART_IN |
|||
.DW EZUART_OUT |
|||
.DW EZUART_IST |
|||
.DW EZUART_OST |
|||
.DW EZUART_INITDEV |
|||
.DW EZUART_QUERY |
|||
.DW EZUART_DEVICE |
|||
#IF (($ - EZUART_FNTBL) != (CIO_FNCNT * 2)) |
|||
.ECHO "*** INVALID EZUART FUNCTION TABLE ***\n" |
|||
#ENDIF |
|||
Loading…
Reference in new issue