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https://github.com/wwarthen/RomWBW.git
synced 2026-02-06 14:11:48 -06:00
XModem Enhancements
Added dynamic CPU speed adaptation to XModem
This commit is contained in:
@@ -70,7 +70,7 @@ STX EQU 02H ; 'Start of header' for 1024 byte blocks
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;
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; Conditional equates - change to suit your system, then assemble
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;
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MHZ EQU 4 ; Clock speed, use integer (2,4,5,8, etc.)
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MHZ EQU 10 ; Clock speed, use integer (2,4,5,8, etc.)
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CPM3 EQU NO ; Yes, if operating in CP/M v3.0 environment
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STOPBIT EQU NO ; No, if using 1 stop bit, yes if using 2
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BYEBDOS EQU NO ; Yes, if using BYE338-up, BYE501-up, or NUBYE
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@@ -817,6 +817,7 @@ BADROP: POP PSW ; Restore stack
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ALLSET: CALL GETCHR
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CALL GETCHR
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CALL MINIT
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STA CPUMHZ ; WBW: Update CPU speed from MINIT in A
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;
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; Jump to appropriate function
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;
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@@ -3458,7 +3459,11 @@ RECVDG: CALL GETCHR
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CALL GETCHR
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;
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RECV: PUSH D ; Save 'DE' regs.
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MVI E,MHZ ; Get the clock speed
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;WBW BEGIN: Use dynamic CPU speed
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; MVI E,MHZ ; Get the clock speed
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LDA CPUMHZ ; Get the clock speed
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MOV E,A ; Put speed in E
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;WBW END
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XRA A ; Clear the 'A' reg.
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;
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MSLOOP: ADD B ; Number of seconds
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@@ -3546,14 +3551,27 @@ CARCK2: LDA OPTSAV ; Get option
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; Delay - 100 millisecond delay.
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;
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DELAY: PUSH B ; Save 'BC'
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LXI B,MHZ*4167 ; Value for 100 ms. delay
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;
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; WBW BEGIN: Use dynamic CPU speed
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; Loop below is 105TS on Z80 and 96TS on Z180
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; Approx 1024 iter per 100ms per MHz
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; Loop time below extended to accommodate CPU speeds up to 64MHz
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; LXI B,MHZ*4167 ; Value for 100 ms. delay
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; Init BC w/ CPU MHz * 1024
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LDA CPUMHZ ; CPU MHz to A
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RLC ; * 2
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RLC ; * 2, A now has MHz * 4
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MOV B,A ; Use as high byte
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MVI C,0 ; Zero low byte, BC now has MHz * 1024
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; WBW END
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DELAY2: DCX B ; Update count
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MOV A,B ; Get MSP byte
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ORA C ; Count = zero?
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JNZ DELAY2 ; If not, continue
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CALL DELAY3 ; WBW: Extend loop time
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CALL DELAY3 ; WBW: Extend loop time
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CALL DELAY3 ; WBW: Extend loop time
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POP B ; Restore 'BC'
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RET ; Return to CARCK1
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DELAY3: RET ; Return to CARCK1
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;
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;-----------------------------------------------------------------------
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;
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@@ -3933,9 +3951,16 @@ INPUT: PUSH H ; Save current values
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PUSH D
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PUSH B
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;
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INPUT1: LXI D,1200 ; Outer loop count (about 2 minutes)
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; WBW BEGIN: Use dynamic CPU speed
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;INPUT1: LXI D,1200 ; Outer loop count (about 2 minutes)
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;;
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;INPUT2: LXI B,MHZ*100 ; Roughly 100 ms.
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INPUT1: LXI D,468 ; Outer loop count (about 2 minutes)
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;
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INPUT2: LXI B,MHZ*100 ; Roughly 100 ms.
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INPUT2: LDA CPUMHZ ; CPU MHz to A
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MOV B,A ; Put in B
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MVI C,0 ; Zero C, BC is now CPU MHz * 256, ~256ms
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; WBW END
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;
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INPUT3: PUSH D ; Save the outer delay count
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PUSH B ; Save the inner delay count
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@@ -5614,6 +5639,7 @@ MSGFLG: DB 0 ; Message upload flag
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SAVEHL: DW 0 ; Saves TBUF command line address
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TOTERR: DW 0 ; Total errors for transmission attempt
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VRECNO: DW 0 ; Virtual record # in 128 byte records
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CPUMHZ: DW MHZ ; WBW: CPU speed in MHz, *word value*
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;
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EOFLG: DB 0 ; 'EOF' flag (1=yes)
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EOFCTR: DB 0 ; EOF send counter
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@@ -65,8 +65,10 @@ MINIT:
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MLT DE
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BIT 2,E ; bit 2 wil be set if mlt happend
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LD HL,U_JPTBL ; assume Z80 (UART)
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LD A,10 ; assume 10MHz CPU in case of Z80
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JR Z,MINIT2 ; yes, Z80, do vector copy
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LD HL,A_JPTBL ; otherwise Z180 (ASCI)
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LD A,20 ; assume 20MHz CPU in case of Z180
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;
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MINIT2:
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; Copy real vectors into active jump table
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@@ -74,7 +76,37 @@ MINIT2:
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LD BC,7 * 3 ; copy 7 3-byte entries
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LDIR
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;
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RET ; no initialization required
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; Check for UNA (UBIOS)
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LD A,(0FFFDH) ; fixed location of UNA API vector
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CP 0C3H ; jp instruction?
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JR NZ,MINIT3 ; if not, not UNA
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LD HL,(0FFFEH) ; get jp address
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LD A,(HL) ; get byte at target address
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CP 0FDH ; first byte of UNA push ix instruction
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JR NZ,MINIT3 ; if not, not UNA
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INC HL ; point to next byte
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LD A,(HL) ; get next byte
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CP 0E5H ; second byte of UNA push ix instruction
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JR NZ,MINIT3 ; if not, not UNA
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;
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; Get CPU speed from UNA
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LD C,0F8H ; UNA BIOS Get PHI function
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RST 08 ; Returns speed in Hz in DE:HL
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LD A,E ; Hack to get approx speed in MHz
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SRL A ; ... by dividing by 1,048,576
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SRL A ; ...
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SRL A ; ...
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SRL A ; ...
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INC A ; Fix up for value truncation
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RET ; done
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;
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MINIT3:
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; Not UNA, use HBIOS for CPU speed lookup
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LD B,0F8H ; HBIOS SYSGET function 0xF8
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LD C,0F0H ; CPUINFO subfunction 0xF0
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RST 08 ; do it, L := CPU speed in MHz
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LD A,L ; move it to A
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RET ; done
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;
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;-----------------------------------------------------------------------
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;
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