Improve sd.asm SD Card Compatibility

- PIO mode of sd.asm driver modified to setup shadow register (Issue #352). - Relocated Z280 IVT to improve space utilization in HBIOS bank.
Preliminary Support for ESP32 Nhyodyne Module
2026-02-07 06:53:13 -06:00 · 2023-07-17 14:52:14 -07:00 · 2023-07-10 13:16:24 -07:00 · 2023-07-09 12:38:48 -07:00
29 changed files with 589 additions and 177 deletions
--- a/Doc/ChangeLog.txt
+++ b/Doc/ChangeLog.txt
@@ -15,6 +15,7 @@ Version 3.3
 - JBL: Added RCZ80 configuration for ColecoVision
 - WBW: Support for Z180 running interrupt mode 1
 - WBW: Preliminary support for S100 Computers Z180
+- WBW: Preliminary support for Dan Werner's ESP32 MBC Module

 Version 3.2.1
 -------------
--- a/Source/HBIOS/Config/MBC_std.asm
+++ b/Source/HBIOS/Config/MBC_std.asm
@@ -49,6 +49,8 @@ PKDENABLE	.SET	TRUE		; ENABLES DSKY NG PKD DRIVER (8259)
 UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 ;UARTCFG	.SET	UARTCFG | SER_RTS
 ;
+ESPENABLE	.SET	TRUE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 LPTENABLE	.SET	TRUE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
 ;
 CVDUMON		.SET	CVDUMON_CGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
--- a/Source/HBIOS/Config/RCZ280_zz80mb.asm
+++ b/Source/HBIOS/Config/RCZ280_zz80mb.asm
@@ -28,7 +28,7 @@
 ;
 #include "cfg_rcz280.asm"
 ;
-CPUOSC		.SET	12000000	; CPU OSC FREQ IN MHZ
+CPUOSC		.SET	24000000	; CPU OSC FREQ IN MHZ
 INTMODE		.SET	3		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
--- a/Source/HBIOS/Config/S100_std.asm
+++ b/Source/HBIOS/Config/S100_std.asm
@@ -40,8 +40,6 @@ ASCIENABLE	.SET	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 ;
-ASCI0CFG	.SET	SER_57600_8N1	; ASCI 1: SERIAL LINE CONFIG
-;
 IDEENABLE	.SET	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
 SDENABLE	.SET	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
--- a/Source/HBIOS/cfg_duo.asm
+++ b/Source/HBIOS/cfg_duo.asm
@@ -232,6 +232,8 @@ PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 HDSKTRACE	.EQU	1		; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 ;
--- a/Source/HBIOS/cfg_dyno.asm
+++ b/Source/HBIOS/cfg_dyno.asm
@@ -243,6 +243,8 @@ PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
--- a/Source/HBIOS/cfg_master.asm
+++ b/Source/HBIOS/cfg_master.asm
@@ -305,6 +305,9 @@ PPPSDENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
 PPPSDTRACE	.EQU	1		; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 PPPCONENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+ESPCONENABLE	.EQU	TRUE		; ESP: ENABLE ESP32 CONSOLE IO DRIVER VIDEO/KBD SUPPORT
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 HDSKTRACE	.EQU	1		; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 ;
--- a/Source/HBIOS/cfg_mbc.asm
+++ b/Source/HBIOS/cfg_mbc.asm
@@ -229,6 +229,9 @@ PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+ESPCONENABLE	.EQU	TRUE		; ESP: ENABLE ESP32 CONSOLE IO DRIVER VIDEO/KBD SUPPORT
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 HDSKTRACE	.EQU	1		; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 ;
--- a/Source/HBIOS/cfg_mk4.asm
+++ b/Source/HBIOS/cfg_mk4.asm
@@ -243,6 +243,8 @@ PPPSDENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
 PPPSDTRACE	.EQU	1		; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 PPPCONENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
--- a/Source/HBIOS/cfg_n8.asm
+++ b/Source/HBIOS/cfg_n8.asm
@@ -241,6 +241,8 @@ PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
--- a/Source/HBIOS/cfg_rcz180.asm
+++ b/Source/HBIOS/cfg_rcz180.asm
@@ -249,6 +249,8 @@ PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
--- a/Source/HBIOS/cfg_rcz280.asm
+++ b/Source/HBIOS/cfg_rcz280.asm
@@ -253,6 +253,8 @@ PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
--- a/Source/HBIOS/cfg_rcz80.asm
+++ b/Source/HBIOS/cfg_rcz80.asm
@@ -247,6 +247,8 @@ PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
--- a/Source/HBIOS/cfg_rph.asm
+++ b/Source/HBIOS/cfg_rph.asm
@@ -230,6 +230,8 @@ PRPCONENABLE	.EQU	FALSE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
--- a/Source/HBIOS/cfg_s100.asm
+++ b/Source/HBIOS/cfg_s100.asm
@@ -30,7 +30,7 @@ CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_57600_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
@@ -243,6 +243,8 @@ PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
--- a/Source/HBIOS/cfg_sbc.asm
+++ b/Source/HBIOS/cfg_sbc.asm
@@ -228,6 +228,8 @@ PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 HDSKTRACE	.EQU	1		; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 ;
--- a/Source/HBIOS/cfg_scz180.asm
+++ b/Source/HBIOS/cfg_scz180.asm
@@ -243,6 +243,8 @@ PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
--- a/Source/HBIOS/cfg_z80retro.asm
+++ b/Source/HBIOS/cfg_z80retro.asm
@@ -203,6 +203,8 @@ PPPSDENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
 PPPSDTRACE	.EQU	1		; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 PPPCONENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
--- a/Source/HBIOS/cfg_zeta.asm
+++ b/Source/HBIOS/cfg_zeta.asm
@@ -174,6 +174,8 @@ PPPSDENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
 PPPSDTRACE	.EQU	1		; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 PPPCONENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
--- a/Source/HBIOS/cfg_zeta2.asm
+++ b/Source/HBIOS/cfg_zeta2.asm
@@ -185,6 +185,8 @@ PPPSDENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
 PPPSDTRACE	.EQU	1		; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 PPPCONENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
--- a/Source/HBIOS/esp.asm
+++ b/Source/HBIOS/esp.asm
@@ -0,0 +1,298 @@
+;
+;==================================================================================================
+; ESP32 DRIVER
+;
+; SUPPORTS DAN WERNER'S NHYODYNE (MBC) ESP32 MODULE
+; https://github.com/danwerner21/nhyodyne/tree/main/Z80ESP
+;==================================================================================================
+;
+; TODO:
+;
+ESP_IOBASE	.EQU	$9C
+ESP_0_IO	.EQU	ESP_IOBASE + 0
+ESP_1_IO	.EQU	ESP_IOBASE + 1
+ESP_STAT	.EQU	ESP_IOBASE + 2
+;
+; ESP  STATUS PORT
+; MSB XX S S S S S S
+;        | | | | | +- ESP0 READY OUTPUT
+;        | | | | +--- ESP0 BUSY
+;        | | | +----- ESP0 SPARE
+;        | | +------- ESP1 READY OUTPUT
+;        | +--------- ESP1 BUSY
+;        +----------- ESP1 SPARE
+;
+ESP_0_RDY	.EQU	%00000001
+ESP_0_BUSY	.EQU	%00000010
+ESP_0_SPARE	.EQU	%00000100
+ESP_1_RDY	.EQU	%00001000
+ESP_1_BUSY	.EQU	%00010000
+ESP_1_SPARE	.EQU	%00100000
+;
+; COMMAND OPCODES
+;
+ESP_CMD_NOP	.EQU	0		; NO OP
+ESP_CMD_COUT	.EQU	1		; CHAR OUT
+ESP_CMD_SOUT	.EQU	2		; STRING OUT
+ESP_CMD_KIN	.EQU	3		; KEY IN
+ESP_CMD_KST	.EQU	4		; KBD BUF STATUS
+ESP_CMD_DISC	.EQU	$FF		; DISCOVER
+;
+; GLOBAL ESP INITIALIZATION
+;
+ESP_INIT:
+;
+	CALL	NEWLINE			; FORMATTING
+	PRTS("ESP: IO=0x$")
+	LD	A,ESP_IOBASE
+	CALL	PRTHEXBYTE
+;
+	CALL	ESP_DETECT
+	LD	DE,ESP_STR_NOHW
+	JP	NZ,WRITESTR
+;
+	; PRINT FIRMWARE VERSION
+	PRTS(" F/W=$")
+	CALL	ESP_PRTVER
+;
+	CALL	ESPCON_INIT		; CONSOLE INITIALIZATION
+;
+	RET
+;
+;==================================================================================================
+; ESP32 INTERFACE FUNCTIONS
+;==================================================================================================
+;
+ESP_DETECT:
+	CALL	ESP_CLR			; CLEAR ANY PENDING DATA
+	RET	NZ			; IF FAILS, ASSUME NOT PRESENT
+	LD	A,ESP_CMD_DISC		; DISCOVER COMMAND
+	CALL	ESP_OUT			; SEND IT
+	LD	DE,10			; DELAY 160US
+	CALL	VDELAY			; ... TO ENSURE OUTPUT RDY SET
+	IN	A,(ESP_STAT)		; GET STATUS
+	AND	ESP_0_RDY		; ISOLATE OUTPUT READY BIT
+	XOR	ESP_0_RDY		; INVERT SO 0=FOUND
+	RET				; DONE
+;
+; CLEAR ESP INPUT QUEUE
+;
+ESP_CLR:
+	LD	B,0			; MAX CHARS TO READ
+ESP_CLR0:
+	CALL	ESP_WTNBSY		; WAIT TILL NOT BUSY
+	IN	A,(ESP_STAT)		; GET STATUS
+	AND	ESP_0_RDY		; IS THERE MORE DATA?
+	RET	Z			; IF NOT, DONE
+	IN	A,(ESP_0_IO)		; GET CHAR
+	DJNZ	ESP_CLR0		; LOOP TILL DONE
+	OR	$FF			; SIGNAL FAILURE
+	RET
+;
+; PRINT ESP VERSION STRING TO CONSOLE
+;
+ESP_PRTVER:
+	CALL	ESP_CLR			; CLEAR ANY PENDING DATA
+	LD	A,ESP_CMD_DISC		; DISCOVER COMMAND
+	CALL	ESP_OUT			; SEND IT
+	CALL	ESP_WTRDY		; WAIT FOR READY TO OUTPUT
+ESP_PRTVER1:
+	CALL	ESP_WTNBSY		; WAIT TILL NOT BUSY
+	IN	A,(ESP_STAT)		; GET STATUS
+	AND	ESP_0_RDY		; ISOLATE OUTPUT READY BIT
+	RET	Z			; DONE IF NOTHING READY
+	CALL	ESP_IN			; GET NEXT CHAR
+	CALL	COUT			; PRINT CHAR
+	JR	ESP_PRTVER1		; LOOP
+;
+; SEND BYTE TO ESP
+;
+ESP_OUT:
+	PUSH	AF			; SAVE VALUE
+	CALL	ESP_WTNBSY		; WAIT TILL NOT BUSY
+	POP	AF			; POP VALUE
+	OUT	(ESP_0_IO),A		; SEND CHARACTER
+	JR	ESP_WTBSY		; RETURN VIA WTBSY
+;
+; GET BYTE FROM ESP (BLOCKING)
+;
+ESP_INWAIT:
+	CALL	ESP_WTNBSY		; WAIT TILL NOT BUSY
+	CALL	ESP_WTRDY		; WAIT FOR READY TO OUTPUT
+	; FALL THRU (GET CHAR VIA ESP_IN)
+;
+; GET BYTE FROM ESP (NON BLOCKING)
+;
+ESP_IN:
+	CALL	ESP_WTNBSY		; WAIT TILL NOT BUSY
+ESP_IN1:	
+	IN	A,(ESP_0_IO)		; GET BYTE
+	PUSH	AF			; SAVE VALUE
+	CALL	ESP_WTBSY		; WAIT TILL BUSY
+	POP	AF			; RESTORE VALUE
+	RET				; AND RETURN
+;
+; WAIT FOR ESP TO BE NOT BUSY
+;
+ESP_WTNBSY:
+	LD	B,0			; MAX TRIES
+ESP_WTNBSY1:	
+	IN	A,(ESP_STAT)		; GET STATUS
+	AND	ESP_0_BUSY		; IS ESP BUSY?
+	RET	Z			; RETURN IF NOT BUSY
+	DJNZ	ESP_WTNBSY1		; ELSE LOOP
+	OR	$FF			; SIGNAL TIMEOUT
+	RET				; AND RETURN
+;
+; WAIT FOR ESP TO BE BUSY
+;
+ESP_WTBSY:
+	LD	B,20			; MAX TRIES
+ESP_WTBSY1:	
+	IN	A,(ESP_STAT)		; GET STATUS
+	AND	ESP_0_BUSY		; IS ESP BUSY?
+	XOR	ESP_0_BUSY		; INVERT
+	RET	Z			; RETURN IF BUSY
+	DJNZ	ESP_WTBSY1		; ELSE LOOP
+	OR	$FF			; SIGNAL TIMEOUT
+	RET				; AND RETURN
+;
+; WAIT FOR ESP TO BE READY TO OUTPUT
+;
+ESP_WTRDY:
+	LD	B,0			; MAX TRIES
+ESP_WTRDY1:
+	IN	A,(ESP_STAT)		; GET STATUS
+	AND	ESP_0_RDY		; IS ESP READY TO OUTPUT
+	XOR	ESP_0_RDY		; INVERT, 0=READY
+	RET	Z			; RETURN IF READY
+	DJNZ	ESP_WTRDY1		; ELSE LOOP
+	OR	$FF			; SIGNAL TIMEOUT
+	RET				; AND RETURN
+;
+;
+;
+ESP_STR_NOHW		.TEXT	" NOT PRESENT$"
+ESP_STR_UPGRADE		.TEXT	" !!!UPGRADE REQUIRED!!!$"
+;
+;==================================================================================================
+; ESP32 CONSOLE DRIVER
+;==================================================================================================
+;
+;
+ESPCON_ROWS	.EQU	25		; VGA DISPLAY ROWS
+ESPCON_COLS	.EQU	80		; VGA DISPLAY COLS
+;
+;
+;
+ESPCON_INIT:
+;
+	CALL	NEWLINE
+	PRTS("ESPCON:$")
+;
+	; DISPLAY CONSOLE DIMENSIONS
+	CALL	PC_SPACE
+	LD	A,ESPCON_COLS
+	CALL	PRTDECB
+	LD	A,'X'
+	CALL	COUT
+	LD	A,ESPCON_ROWS
+	CALL	PRTDECB
+	CALL	PRTSTRD
+	.TEXT	" TEXT (ANSI)$"
+;
+; ADD OURSELVES TO CIO DISPATCH TABLE
+;
+	LD	D,0			; PHYSICAL UNIT IS ZERO
+	LD	E,CIODEV_ESPCON		; DEVICE TYPE
+	LD	BC,ESPCON_FNTBL		; BC := FUNCTION TABLE ADDRESS
+	CALL	CIO_ADDENT		; ADD ENTRY, A := UNIT ASSIGNED
+	LD	(HCB + HCB_CRTDEV),A	; SET OURSELVES AS THE CRT DEVICE
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; DRIVER FUNCTION TABLE
+;
+ESPCON_FNTBL:
+	.DW	ESPCON_IN
+	.DW	ESPCON_OUT
+	.DW	ESPCON_IST
+	.DW	ESPCON_OST
+	.DW	ESPCON_INITDEV
+	.DW	ESPCON_QUERY
+	.DW	ESPCON_DEVICE
+#IF (($ - ESPCON_FNTBL) != (CIO_FNCNT * 2))
+	.ECHO	"*** INVALID ESPCON FUNCTION TABLE ***\n"
+#ENDIF
+;
+;
+;
+ESPCON_IN:
+	CALL	ESPCON_IST
+	JR	Z,ESPCON_IN
+	LD	A,ESP_CMD_KIN		; KBD INPUT
+	CALL	ESP_OUT			; SEND CMD OPCODE
+	CALL	ESP_INWAIT		; GET KEY
+	LD	E,A			; PUT IN E
+	XOR	A			; SIGNAL SUCCES
+	RET				; AND DONE
+;
+;
+;
+ESPCON_IST:
+	LD	A,ESP_CMD_KST		; KBD BUF STATUS
+	CALL	ESP_OUT			; SEND CMD OPCODE
+	CALL	ESP_INWAIT		; GET BUF SIZE
+	OR	A			; SET FLAGS
+	RET	Z			; AND DONE
+	OR	A
+	RET
+;
+;
+;
+ESPCON_OUT:
+	PUSH	DE
+	LD	A,ESP_CMD_COUT		; CHAR OUT OPCODE
+	CALL	ESP_OUT
+	POP	DE
+	LD	A,E
+	CALL	ESP_OUT			; SEND CHAR VALUE
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+;
+;
+ESPCON_OST:
+	OR	$FF			; SIGNAL OUTPUT QUEUE READY
+	RET				; RETURN
+;
+;
+;
+ESPCON_INITDEV:
+	SYSCHKERR(ERR_NOTIMPL)
+	RET
+;
+;
+;
+ESPCON_QUERY:
+	LD	DE,0
+	LD	HL,0
+	XOR	A
+	RET
+;
+;
+;
+ESPCON_DEVICE:
+	LD	D,CIODEV_ESPCON		; D := DEVICE TYPE
+	LD	E,0			; E := DEVICE NUM, ALWAYS 0
+	LD	C,$BF			; C := DEVICE TYPE, 0xBF IS PROP TERM
+	LD	H,0			; H := 0, DRIVER HAS NO MODES
+	LD	L,ESP_IOBASE		; L := BASE I/O ADDRESS
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+;=============================================================================
+; DATA STORAGE
+;=============================================================================
+;
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -2772,6 +2772,7 @@ HB_WDZ:
 ;
 	LD	A,(CB_CONDEV)		; GET CURRENT CONSOLE
 	LD	(HB_NEWCON),A		; AND INIT NEW CONSOLE VAR
+;
 #IF CRTACT
 ;
 ; BIOS IS CONFIGURED TO AUTO ACTIVATE CRT DEVICE.  FIRST,
@@ -2795,11 +2796,6 @@ HB_WDZ:
 ;
 #ENDIF
 ;
-; THIS IS A GOOD PLACE TO DETERMINE IF FRONT PANEL HARDWARE REALLY
-; EXISTS.
-;
-	CALL	FP_DETECT
-;
 #IF (FPSW_ENABLE)
 ;
 ; IF WE HAVE FRONT PANEL SWITCHES, THIS IS THE RIGHT PLACE TO HANDLE
@@ -2813,8 +2809,9 @@ HB_WDZ:
 	LD	A,FPSW_IO
 	CALL	PRTHEXBYTE
 ;
-	; THE EXISTENCE OF THE FP WAS TESTED EARLIER.  IF IT DOESN'T
-	; EXIST, BAIL OUT.
+	CALL	FP_DETECT
+;
+	; IF FP DOESN'T EXIST, BAIL OUT.
 	LD	A,(FPSW_ACTIVE)		; GET FP EXISTENCE FLAG
 	OR	A			; SET FLAGS
 	JR	NZ,HB_FP1		; IF WE HAVE ONE, CONTINUE
@@ -3286,6 +3283,9 @@ HB_INITTBL:
 #IF (PPPENABLE)
 	.DW	PPP_INIT
 #ENDIF
+#IF (ESPENABLE)
+	.DW	ESP_INIT
+#ENDIF
 ;
 HB_INITTBLLEN	.EQU	(($ - HB_INITTBL) / 2)
 ;
@@ -5111,6 +5111,99 @@ SYS_INTSET1:
 	RET				; DONE
 ;
 ;==================================================================================================
+;   Z280 INTERRUPT VECTOR TABLE
+;==================================================================================================
+;
+#IF (MEMMGR == MM_Z280)
+;
+	; THE Z280 IVT MUST BE ON A 4K BOUNDARY.  IT HAS BEEN LOCATED
+	; HERE IN AN EFFORT TO MINIMIZE WASTED SPACE.  THERE SHOULD BE
+	; A LITTLE LESS THAN 4K OF CODE ABOVE.
+;
+Z280_IVT_SLACK	.EQU	$1000 - ($ & $FFF)
+		.ECHO	"Z280 IVT SLACK occupies "
+		.ECHO	Z280_IVT_SLACK
+		.ECHO	" bytes.\n"
+		;.FILL	$1000 - ($ & $FFF)	; MUST BE 4K ALIGNED!
+		.FILL	Z280_IVT_SLACK		; MUST BE 4K ALIGNED!
+;
+Z280_IVT:
+	.DW	0, 0			; RESERVED
+	.DW	0			; NMI MSR
+	.DW	0			; NMI VECTOR
+	.DW	$0000			; INT A MSR
+	.DW	Z280_BADINT		; INT A VECTOR
+	.DW	$0000			; INT B MSR
+	.DW	Z280_BADINT		; INT B VECTOR
+	.DW	$0000			; INT C MSR
+	.DW	Z280_BADINT		; INT C VECTOR
+	.DW	$0000			; COUNTER/TIMER 0 MSR
+	.DW	Z280_BADINT		; COUNTER/TIMER 0 VECTOR
+	.DW	$0000			; COUNTER/TIMER 1 MSR
+	.DW	Z280_BADINT		; COUNTER/TIMER 1 VECTOR
+	.DW	0, 0			; RESERVED
+	.DW	$0000			; COUNTER/TIMER 2 MSR
+	.DW	Z280_BADINT		; COUNTER/TIMER 2 VECTOR
+	.DW	$0000			; DMA CHANNEL 0 MSR
+	.DW	Z280_BADINT		; DMA CHANNEL 0 VECTOR
+	.DW	$0000			; DMA CHANNEL 1 MSR
+	.DW	Z280_BADINT		; DMA CHANNEL 1 VECTOR
+	.DW	$0000			; DMA CHANNEL 2 MSR
+	.DW	Z280_BADINT		; DMA CHANNEL 2 VECTOR
+	.DW	$0000			; DMA CHANNEL 3 MSR
+	.DW	Z280_BADINT		; DMA CHANNEL 3 VECTOR
+	.DW	$0000			; UART RECEIVER MSR
+	.DW	Z280_BADINT		; UART RECEIVER VECTOR
+	.DW	$0000			; UART TRANSMITTER MSR
+	.DW	Z280_BADINT		; UART TRANSMITTER VECTOR
+	.DW	$0000			; SINGLE STEP TRAP MSR
+	.DW	Z280_SSTEP		; SINGLE STEP TRAP VECTOR
+	.DW	$0000			; BREAK ON HALT TRAP MSR
+	.DW	Z280_BRKHLT		; BREAK ON HALT TRAP VECTOR
+	.DW	$0000			; DIVISION EXCEPTION TRAP MSR
+	.DW	Z280_DIVEXC		; DIVISION EXCEPTION TRAP VECTOR
+	.DW	$0000			; STACK OVERFLOW WARNING TRAP MSR
+	.DW	Z280_STKOVR		; STACK OVERFLOW WARNING TRAP VECTOR
+	.DW	$0000			; ACCESS VIOLATION TRAP MSR
+	.DW	Z280_ACCVIO		; ACCESS VIOLATION TRAP VECTOR
+	.DW	$0000			; SYSTEM CALL TRAP MSR
+	.DW	Z280_SYSCALL		; SYSTEM CALL TRAP VECTOR
+	.DW	$0000			; PRIVILEGED INSTRUCTION TRAP MSR
+	.DW	Z280_PRIVINST		; PRIVILEGED INSTRUCTION TRAP VECTOR
+	.DW	$0000			; EPU <- MEMORY EXTENDED INSTRUCTION TRAP MSR
+	.DW	$0000			; EPU <- MEMORY EXTENDED INSTRUCTION TRAP VECTOR
+	.DW	$0000			; MEMORY <- EPU EXTENDED INSTRUCTION TRAP MSR
+	.DW	$0000			; MEMORY <- EPU EXTENDED INSTRUCTION TRAP VECTOR
+	.DW	$0000			; A <- EPU EXTENDED INSTRUCTION TRAP MSR
+	.DW	$0000			; A <- EPU EXTENDED INSTRUCTION TRAP VECTOR
+	.DW	$0000			; EPU INTERNAL OPERATION EXTENDED INSTRUCTION TRAP MSR
+	.DW	$0000			; EPU INTERNAL OPERATION EXTENDED INSTRUCTION TRAP VECTOR
+	.DW	0, 0			; RESERVED
+	.DW	0, 0			; RESERVED
+	; PROGRAM COUNTER VALUES FOR NMI/INTA (16)
+	.DW	HBX_IV00
+	.DW	HBX_IV01
+	.DW	HBX_IV02
+	.DW	HBX_IV03
+	.DW	HBX_IV04
+	.DW	HBX_IV05
+	.DW	HBX_IV06
+	.DW	HBX_IV07
+	.DW	HBX_IV08
+	.DW	HBX_IV09
+	.DW	HBX_IV0A
+	.DW	HBX_IV0B
+	.DW	HBX_IV0C
+	.DW	HBX_IV0D
+	.DW	HBX_IV0E
+	.DW	HBX_IV0F
+	; THE REMAINDER OF THE Z280 IVT IS TRUNCATED HERE BECAUSE IT
+	; TAKES A BUNCH OF SPACE AND IS NOT USED.  WE SUPPORT ONLY
+	; 16 VECTORED INTERRUPTS AND THEY MUST BE CONNECTED TO INTA.
+;
+#ENDIF
+;
+;==================================================================================================
 ;   GLOBAL HBIOS FUNCTIONS
 ;==================================================================================================
 ;
@@ -5670,94 +5763,6 @@ HB_ALLOC1:
 HB_TMPSZ	.DW	0
 HB_TMPREF	.DW	0
 ;
-;==================================================================================================
-;   Z280 INTERRUPT VECTOR TABLE
-;==================================================================================================
-;
-#IF (MEMMGR == MM_Z280)
-;
-	; THE Z280 IVT MUST BE ON A 4K BOUNDARY.  IT HAS BEEN LOCATED
-	; HERE IN AN EFFORT TO MINIMIZE WASTED SPACE.  THERE SHOULD BE
-	; A LITTLE LESS THAN 4K OF CODE ABOVE.
-;
-	.FILL	$1000 - ($ & $FFF)	; MUST BE 4K ALIGNED!
-;
-Z280_IVT:
-	.DW	0, 0			; RESERVED
-	.DW	0			; NMI MSR
-	.DW	0			; NMI VECTOR
-	.DW	$0000			; INT A MSR
-	.DW	Z280_BADINT		; INT A VECTOR
-	.DW	$0000			; INT B MSR
-	.DW	Z280_BADINT		; INT B VECTOR
-	.DW	$0000			; INT C MSR
-	.DW	Z280_BADINT		; INT C VECTOR
-	.DW	$0000			; COUNTER/TIMER 0 MSR
-	.DW	Z280_BADINT		; COUNTER/TIMER 0 VECTOR
-	.DW	$0000			; COUNTER/TIMER 1 MSR
-	.DW	Z280_BADINT		; COUNTER/TIMER 1 VECTOR
-	.DW	0, 0			; RESERVED
-	.DW	$0000			; COUNTER/TIMER 2 MSR
-	.DW	Z280_BADINT		; COUNTER/TIMER 2 VECTOR
-	.DW	$0000			; DMA CHANNEL 0 MSR
-	.DW	Z280_BADINT		; DMA CHANNEL 0 VECTOR
-	.DW	$0000			; DMA CHANNEL 1 MSR
-	.DW	Z280_BADINT		; DMA CHANNEL 1 VECTOR
-	.DW	$0000			; DMA CHANNEL 2 MSR
-	.DW	Z280_BADINT		; DMA CHANNEL 2 VECTOR
-	.DW	$0000			; DMA CHANNEL 3 MSR
-	.DW	Z280_BADINT		; DMA CHANNEL 3 VECTOR
-	.DW	$0000			; UART RECEIVER MSR
-	.DW	Z280_BADINT		; UART RECEIVER VECTOR
-	.DW	$0000			; UART TRANSMITTER MSR
-	.DW	Z280_BADINT		; UART TRANSMITTER VECTOR
-	.DW	$0000			; SINGLE STEP TRAP MSR
-	.DW	Z280_SSTEP		; SINGLE STEP TRAP VECTOR
-	.DW	$0000			; BREAK ON HALT TRAP MSR
-	.DW	Z280_BRKHLT		; BREAK ON HALT TRAP VECTOR
-	.DW	$0000			; DIVISION EXCEPTION TRAP MSR
-	.DW	Z280_DIVEXC		; DIVISION EXCEPTION TRAP VECTOR
-	.DW	$0000			; STACK OVERFLOW WARNING TRAP MSR
-	.DW	Z280_STKOVR		; STACK OVERFLOW WARNING TRAP VECTOR
-	.DW	$0000			; ACCESS VIOLATION TRAP MSR
-	.DW	Z280_ACCVIO		; ACCESS VIOLATION TRAP VECTOR
-	.DW	$0000			; SYSTEM CALL TRAP MSR
-	.DW	Z280_SYSCALL		; SYSTEM CALL TRAP VECTOR
-	.DW	$0000			; PRIVILEGED INSTRUCTION TRAP MSR
-	.DW	Z280_PRIVINST		; PRIVILEGED INSTRUCTION TRAP VECTOR
-	.DW	$0000			; EPU <- MEMORY EXTENDED INSTRUCTION TRAP MSR
-	.DW	$0000			; EPU <- MEMORY EXTENDED INSTRUCTION TRAP VECTOR
-	.DW	$0000			; MEMORY <- EPU EXTENDED INSTRUCTION TRAP MSR
-	.DW	$0000			; MEMORY <- EPU EXTENDED INSTRUCTION TRAP VECTOR
-	.DW	$0000			; A <- EPU EXTENDED INSTRUCTION TRAP MSR
-	.DW	$0000			; A <- EPU EXTENDED INSTRUCTION TRAP VECTOR
-	.DW	$0000			; EPU INTERNAL OPERATION EXTENDED INSTRUCTION TRAP MSR
-	.DW	$0000			; EPU INTERNAL OPERATION EXTENDED INSTRUCTION TRAP VECTOR
-	.DW	0, 0			; RESERVED
-	.DW	0, 0			; RESERVED
-	; PROGRAM COUNTER VALUES FOR NMI/INTA (16)
-	.DW	HBX_IV00
-	.DW	HBX_IV01
-	.DW	HBX_IV02
-	.DW	HBX_IV03
-	.DW	HBX_IV04
-	.DW	HBX_IV05
-	.DW	HBX_IV06
-	.DW	HBX_IV07
-	.DW	HBX_IV08
-	.DW	HBX_IV09
-	.DW	HBX_IV0A
-	.DW	HBX_IV0B
-	.DW	HBX_IV0C
-	.DW	HBX_IV0D
-	.DW	HBX_IV0E
-	.DW	HBX_IV0F
-	; THE REMAINDER OF THE Z280 IVT IS TRUNCATED HERE BECAUSE IT
-	; TAKES A BUNCH OF SPACE AND IS NOT USED.  WE SUPPORT ONLY
-	; 16 VECTORED INTERRUPTS AND THEY MUST BE CONNECTED TO INTA.
-;
-#ENDIF
-;
 ; Z280 BANK SELECTION (CALLED FROM PROXY)
 ;
 #IF (MEMMGR == MM_Z280)
@@ -6434,6 +6439,15 @@ SIZ_PPP		.EQU	$ - ORG_PPP
 		.ECHO	" bytes.\n"
 #ENDIF
 ;
+#IF (ESPENABLE)
+ORG_ESP		.EQU	$
+  #INCLUDE "esp.asm"
+SIZ_ESP		.EQU	$ - ORG_ESP
+		.ECHO	"ESP occupies "
+		.ECHO	SIZ_ESP
+		.ECHO	" bytes.\n"
+#ENDIF
+;
 #IF (MDENABLE)
 ORG_MD		.EQU	$
  #INCLUDE "md.asm"
@@ -7104,7 +7118,7 @@ PS_PRTSC1:
 	RET
 ;
 PS_PRTSC2:
-	PRTS("PropTerm$")		; ASSUME PROPELLER
+	PRTS("Term Module$")
 	CALL	PC_COMMA
 	PRTS("ANSI$")
 	RET
@@ -7343,6 +7357,7 @@ PS_SDUF		.TEXT	"UF$"
 PS_SDDUART	.TEXT	"DUART$"
 PS_SDZ2U	.TEXT	"Z2U$"
 PS_SDLPT	.TEXT	"LPT$"
+PS_SDESPCON	.TEXT	"ESPCON$"
 ;
 ; CHARACTER SUB TYPE STRINGS
 ;
--- a/Source/HBIOS/hbios.inc
+++ b/Source/HBIOS/hbios.inc
@@ -313,6 +313,7 @@ CIODEV_UF	.EQU	$80
 CIODEV_DUART	.EQU	$90
 CIODEV_Z2U	.EQU	$A0
 CIODEV_LPT	.EQU	$B0
+CIODEV_ESPCON	.EQU	$C0
 ;
 ; SUB TYPES OF CHAR DEVICES
 ;
--- a/Source/HBIOS/ppp.asm
+++ b/Source/HBIOS/ppp.asm
@@ -4,7 +4,6 @@
 ;==================================================================================================
 ;
 ; TODO:
-;   1) ADD SUPPORT FOR DSKY
 ;
 PPP_IO		.EQU	PPPBASE + 0	; PPP DATA I/O (PPI PORT A)
 PPP_CTL		.EQU	PPPBASE + 2	; PPP CTL LINES (PPI PORT C)
--- a/Source/HBIOS/prp.asm
+++ b/Source/HBIOS/prp.asm
@@ -4,7 +4,6 @@
 ;==================================================================================================
 ;
 ; TODO:
-;   1) ADD SUPPORT FOR DSKY
 ;
 PRP_IOBASE	.EQU	$A8
 ;
--- a/Source/HBIOS/s100mon.z80
+++ b/Source/HBIOS/s100mon.z80
@@ -16,14 +16,13 @@
 ; The CPU is configured to run at the most conservative settings.
 ; PHI at 1/2 XTAL input, +3 memory wait states, and +3 I/O wait states.
 ;
-; Serial port baud rate divisor is programmed to 480, so the baud rate
-; will be PHI / 480, so nominally 19,200 baud.  See below for CNTLB
-; value to use for 57,600 baud.  Line characteristics are set to
+; Serial port baud rate divisor is programmed to a 57,600 baud rate
+; with PHI at 9.2MHz.  Line characteristics are set to
 ; 8 data bits, 1 stop bit, no parity.
 ;
 ; The initialization code relocates the internal Z180 CPU registers
 ; to start at C0H.  This is not a requirement of the code, but I
-; thought it might be helpful for testing external devices that are
+; thought it might be helpful for testing S100 bus external devices that are
 ; more likely to be located at the lower I/O addresses.
 ;
 ; The submit file (xxx2.sub) contains:-
@@ -40,7 +39,7 @@
 ; I:
 ;
 ; Use the "r" SIMH command to move SLR180.COM file across to the I: Drive 
-; Also "r" the XXX0.SUB file across to the I: drive (one time only)
+; Also "r" the XXX2.SUB file across to the I: drive (one time only)
 ; Note I already have these files on the Altair I: drive you are using here.
 ;
 ; Then....
@@ -48,8 +47,9 @@
 ;
 ; Ignore the SLR assembler error about the load address being less than 100H
 ;
-; The .HEX file will have a start address of F000H. It must reside in the ROM starting
-; at 0H. With the Wellon VP 290 Programmer:-
+; The .HEX file will have a start address of 0000H. It must reside in the ROM starting
+; at 0H. For the "ROM" I use the Microchip SST39F040 chip type
+; With the Wellon VP 290 Programmer:-
 ;
 ; To Buffer Address (HEX) 	
 ; For File Address (Hex) 0000 <------
@@ -59,12 +59,18 @@
 ; To Buffer Mode Normal
 ; From File Mode Normal
 ;
+;
+;----------------------------------------------------------------------------------------
+;
 ;	V0.0	5/10/2023			;Initial boot code supplied by Wayne Warthen
 ;	V0.1	5/18/2023			;First addition of S100 bus Z80 Master.Z80 monitor code.
 ;       V0.11   6/5/2023                        ;Menu to test S100 bus signals & set Baud Rate
 ;	V0.2	7/4/2023			;Remove baud rate option, add date,time, start IDE
 ;	V0.21	7/6/2023			;Cleaned up IDE drive section
-
+;	V0.22	7/6/2023			;Added default NMI and INT0 interrupt traps
+;	V0.23	7/7/2023			;Better use of ESC character for data entry aborts
+;	V0.24	7/8/2023			;Added Master/Slave S100 bus request ("W" CMD)
+;
 ;--------------------------------- Port equates used throughout the monitor ---------------
 ;
 ;
@@ -92,11 +98,12 @@ NAK		EQU	15H
 FALSE		EQU	0
 TRUE		EQU	NOT FALSE

-DIAGNOSTIC_MODE EQU	FALSE
 ST8C4		EQU	TRUE		;TRUE if S100_Parallel_IO Board.  False if IMSAI PIO Board	
 IOBYTE		EQU	075H		;IOBYTE PORT ON Z180 CPU Board (74H-77H or 64H-67H. Set with K8)
 SOUT_PORT	EQU	074H		;Onboard port to control sOUT signal to S100 bus.

+NMI_VECTOR	EQU	66H		;Default NMI Vector location
+INT0_VECTOR	EQU	38H		;Default INT0 vector location

 ;-------------- PROPELLER CONSOLE_IO (OR SD SYSTEMS VIDIO BOARD) FOR CONSOLE INPUT & OUTPUT
 CONSOLE_STATUS	EQU	0H	
@@ -370,17 +377,9 @@ CNTLB0_VALUE	equ     00H                     ; For setting final baud rate from
 	; register base I/O address is zero, so initially, ICR is
 	; at 3FH.
 	
-	ld	a,z180_base
+	ld	a,z180_base		; C0H
 	out0	(3Fh),a			; at reset, icr is at 3FH

-IF DIAGNOSTIC_MODE
-;	*** Test point #1 ***
-;
-	ld	a,'@'			; Put an '@' character on the S100 bus Propeller Console board
-	out0	(1),a			; if present/hooked up as a diagnostic
-;
-ENDIF
-					
 	xor	a			; Disable refresh (not really required)
 	out0	(z180_rcr),a
 					; To make PHI=Osc Input, set bit 7 of CCR
@@ -413,16 +412,6 @@ ENDIF
 					; Confirm RAM is working by pushing a value on the stack, then
 					; popping the value to a different register and writing it to the
 					; diagnostic LEDs
-IF DIAGNOSTIC_MODE
-;	*** Test point #2 ***
-;
-	ld	b,'#'			; value to B
-	push	bc			; push it
-	pop	af			; pop into A
-	out0	(1),a			; Show all is OK if we have a Propeller IO board present
-;
-ENDIF
-					; Copy monitor to RAM at F000H
 ;
 	ld	hl,mon_img
 	ld	de,mon_start
@@ -440,7 +429,7 @@ jp	mon_start
 	DB	0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
 	DB	0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
 	DB	0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
-	Db	0,0
+	Db	0,0,0,0
 	
 ; Jump to monitor!!!
 ;
@@ -457,14 +446,38 @@ mon_img	equ	$			; start of monitor image
 ;
 	.phase	mon_start		; running location for monitor
 ;
-IF DIAGNOSTIC_MODE
-;	*** Test point #3 ***
-;
-	ld	a,'$'			
-	out	(1),a			; Show all is OK if we have a Propeller IO board present
-;
-ENDIF					; Configure the ASCI0 port see the above equates table
+		JP	OVER_VECTORS		
+	
+CON_OUT:	JP	ZCO				;0E003H, Interrupt/BIOS routines are counting on these locations
+CON_STAT:	JP	ZCSTS				;0E006H, never changing
+CON_IN:		JP	ZCI				;0E009H
+SEND_STRING:	JP	PRINT_STRING			;0E00CH
+MONITOR_NMI	JP	DEFAULT_NMI			;0E00FH
+MONITOR_INTO	JP	DEFAULT_INT0			;0E012H

+DEFAULT_NMI:	
+	PUSH	AF
+	PUSH	BC
+	PUSH	HL
+	LD	HL,NMI_MSG
+	CALL	PRINT_STRING
+	POP	HL
+	POP	BC
+	POP	AF
+	RETI
+
+DEFAULT_INT0:	
+	PUSH	AF
+	PUSH	BC
+	PUSH	HL
+	LD	HL,INT0_MSG
+	CALL	PRINT_STRING
+	POP	HL
+	POP	BC
+	POP	AF
+	RETI
+	
+OVER_VECTORS:
 	ld	a,64h			; xmit enable, rcv enable, 8 data bits, no parity
 	out0	(z180_cntla0),a
 	ld	a,CNTLB0_VALUE		; 20H, Baud=19,200 @ 9.2 MHz
@@ -472,9 +485,8 @@ ENDIF					; Configure the ASCI0 port see the above equates table
 	ld	a,60h			; dcd0 disable, cts0 disable
 	out0	(z180_asext0),a
 ;
-					; Delay after ASCI setup (should not be needed)
 ;
-	ld	b,0
+	ld	b,0			; Delay after ASCI setup (should not be needed)
 	djnz	$
 	djnz	$
 ;
@@ -485,16 +497,6 @@ ENDIF					; Configure the ASCI0 port see the above equates table
 	ld	a,10h			; first physical bank of RAM
 	call	bnksel			; do it
 ;
-IF DIAGNOSTIC_MODE
-;	*** Test point #4 ***
-;
-	ld	a,'%'			; value to A
-	ld	(0000h),a		; save at cpu address 0000H
-	xor	a			; clear accum
-	ld	a,(0000h)		; load value to A
-	out	(1),a			; Show all is OK if we have a Propeller IO board present
-
-ENDIF
 					; *** Add code as desired to setup Z180 zero page ***
 ;
 					; At this point RAM is mapped to entire CPU address space.  This is
@@ -506,7 +508,7 @@ ENDIF
 ;
 BEGIN0:	JP	BEGIN			;JUMP OVER COMMAND TABLE

-TBL:	DW  FLUSH			;"@"  SEND FF to LaserJet printer
+TBL:	DW  FLUSH			;"@"  SEND FF to LaserJet printer      
 	DW  MEMMAP			;"A"  DISPLAY A MAP OF MEMORY
 	DW  BOOT			;	"B"  SWITCH CONTROL TO 68000 CPU 
 	DW  NOT_DONE			;	"C"  BOOT IN CP/M FROM 8" DISK WITH WITH ZFDC FDC 
@@ -529,7 +531,7 @@ TBL:	DW  FLUSH			;"@"  SEND FF to LaserJet printer
 	DW  TYPE			;"T"  TYPE ASCII PRESENT IN MEMORY  (Same as D cmd except ASCII
 	DW  HALT_CPU			;"U"  SPARE
 	DW  VERIFY			;"V"  COMPARE MEMORY
-	DW  SWITCH_8086			;	"W"  INPUT Port ED (switched in 8086/80286)
+	DW  SWITCH_8086			;"W"  INPUT Port ED (switched in 8086/80286)
 	DW  XMODEM			;"X"  DOWNLOAD A FILE FROM PC VIA XMODEM TO THIS S100 SYSTEM
 	DW  IDE_SETUP			;"Y"  IDE Menu for CF Card Board
 	DW  SIZE			;"Z"  FIND HIGHEST R/W RAM
@@ -613,7 +615,24 @@ ENDIF
 	LD	HL,CR_SMSG_SP		;lets V-Stamp chip get baud rate
 	CALL	SPEAK$		
 	
+	LD	HL,NMI_VECTOR		;Set default NMI vector jump at 66H in RAM
+	LD	A,0C3H
+	LD	(HL),A
+	INC	HL
+	LD	DE,DEFAULT_NMI
+	LD	(HL),E
+	INC	HL
+	LD	(HL),D
 	
+	LD	HL,INT0_VECTOR		;Set default INT0 vector jump at 38H in RAM
+	LD	A,0C3H
+	LD	(HL),A
+	INC	HL
+	LD	DE,DEFAULT_INT0
+	LD	(HL),E
+	INC	HL
+	LD	(HL),D
+
 					
 ;-------THIS IS THE START ON THE MAIN MONITOR LOOP--------------------------------

@@ -626,7 +645,7 @@ ZSTART:	LD	DE,ZSTART
 	CALL	ZCO

 STARO:	CALL	TI			; Main loop. Monitor will stay here until cmd.
-	cp	ESC			; escape?
+	CP	ESC			; escape?
 	jp	z,echoz			; done if so
 	AND	7FH
 	JR	Z,STARO
@@ -1050,6 +1069,8 @@ SF2E3:	LD	A,(HL)
 	CALL	PCHK
 	RET	C
 	JR	Z,SF2FC
+	CP	ESC			;Abort if ESC
+	JP	Z,ESC_ABORT
 	CP	5FH
 	JR	Z,SF305
 	PUSH	HL
@@ -1070,7 +1091,6 @@ SF305:	DEC	HL



-
 ;-------------------------- F COMMAND FILL A BLOCK OF MEMORY WITH A VALUE ------------------------

 FILL:	CALL	EXPR3
@@ -1101,11 +1121,13 @@ QUERY:	CALL	PCHK
 	LD	C,'*'
 	JP	ZCO			;WILL ABORT IF NOT 'I' OR 'O'

+
 IN_PORT:
 	LD	C,1			;IN Port
 	CALL	HEXSP
 	POP	BC
 	IN	A,(C)
+	CALL	ZSPACE
 	JP	ZBITS
 ;
 OUT_PORT:
@@ -1115,15 +1137,35 @@ OUT_PORT:
 	OUT	(C),E
 	RET

-
-
 ;-------------------------- U COMMAND     HALT the Z180 CPU ---------------------------------

 HALT_CPU:	
 	LD	HL,HALT_MSG
 	CALL	PRINT_STRING		;Print message up to '$'
 	HALT
+
+
+;-------------------------- W COMMAND     Switch control of S100 Bus to slave CPU (eg 8086) ---------------------------------
+
+SWITCH_8086:				; "W"  INPUT Port ED (switched in 8086/80286)
+					;Note currently the S100 slave switch ports overlaps with the Z180 internal ports
+					
+	LD	HL,SLAVE_MSG		;Send before we switch internal ports
+	CALL	PRINT_STRING
 	
+	ld	a,00H			;Move back to the defauly Z180 base register port (00H)
+	out0	(0FFH),a		;icr is currently at FFH
+
+	IN0	A,(SW_TMA0)		;THIS SWITCHES CPU'S with no block Move
+	NOP				;Z80 WILL BE HELD HERE
+	NOP
+	LD	A,01			;Utilize the more specific circuit on the V2-SMB
+	OUT0	(SW_TMAX),A		;Make sure its bit 0
+	NOP
+	NOP
+	NOP
+	JP	BEGIN0			;If we get back control
+

 ;------THIS IS THE MAIN ROUTINE TO GET THE TIME DATA FROM THE CMOS-RTC Chip on the MSDOS Support Board 

@@ -2337,8 +2379,12 @@ HL_ONLY:

 ;PRINT A SPACE

-ZSPACE:	LD	C,SPACE
+ZSPACE:	PUSH	AF
+	PUSH	BC
+	LD	C,SPACE
 	CALL	ZCO
+	POP	BC
+	POP	AF
 	RET

 ;CONVERT HEX TO ASCII
@@ -2384,6 +2430,9 @@ ZGET_HL:
 EXPR1:	LD	C,01H
 HEXSP:	LD	HL,0000
 EX0:	CALL	TI
+	CP	ESC
+	JR	NZ,EX1
+	JP	ESC_ABORT		;ABORT BACK TO MAIN LOOP
 EX1:	LD	B,A
 	CALL	NIBBLE
 	JR	C,EX2X
@@ -2409,6 +2458,15 @@ EXF:	LD	C,01H
 	LD	HL,0000H
 	JR	EX1

+ESC_ABORT:
+	LD	C,BELL
+	CALL	ZCO
+	CALL	ZCRLF
+	POP	AF			;BALANCE UP STACK
+	JP	ZSTART
+	
+	
+	
 ;RANGE TEST ROUTINE CARRY SET = RANGE EXCEEDED

 HILOX:	CALL	CCHK
@@ -2624,7 +2682,6 @@ XMEMMAP:				; "N"  Display extended memory Segment:Address
 UP8086:					; "O"  SWITCH CONTROL TO 8088, 8086 or 80286. 
 HBOOTCPM:				; "P"  BOOT IN CPM FROM IDE HARD DISK
 SPARE:					; "U"  SPARE
-SWITCH_8086:				; "W"  INPUT Port ED (switched in 8086/80286)
 ;XMODEM:				; "X"  DOWNLOAD A FILE FROM PC VIA XMODEM TO THIS S100 SYSTEM
 ZBOOT

@@ -2940,15 +2997,16 @@ bnksel:



-SIGNON_MSG:	DB	BELL		
-		DB	'Z180 ROM MONITOR (V0.21) @ E000H (J.Monahan,7/6/2023)$'	
+SIGNON_MSG:	DB	BELL,CR,LF		
+		DB	'Z180 ROM MONITOR (V0.24) @ E000H (J.Monahan,7/8/2023)$'	

-MENUMSG:	DB	'A=Memmap   B=         C=CP/M(F)  D=Disp  E=Echo   F=Fill  G=Goto',CR,LF
-		DB	'H=Date     I=Time     J=RAM Test K=Menu  L=CPM(V) M=Move  N=S100 Menu',CR,LF
-		DB	'O=         P=CPM(IDE) QI,O=Port  R=Ports S=Subs   T=Type  U=Halt ',CR,LF 
-		DB	'V=Verify   W=Port EDH X=XModem   Y=IDE   Z=Top    @=Flush Printer'
+MENUMSG:	DB	'A=Memmap   B=Boot      C=CP/M(F)  D=Disp  E=Echo   F=Fill  G=Goto',CR,LF
+		DB	'H=Date     I=Time      J=RAM Test K=Menu  L=CPM(V) M=Move  N=S100 Menu',CR,LF
+		DB	'O=         P=CPM(IDE)  QI,O=Port  R=Ports S=Subs   T=Type  U=Halt ',CR,LF 
+		DB	'V=Verify   W=Bus Req   X=XModem   Y=IDE   Z=Top    @=Flush Printer'
 		DB	CR,LF,LF,'$'
-SMSG_SP:	DB	'THE Z180 ROM MONITOR VERSION 0.1$'
+		
+SMSG_SP:	DB	'THE Z180 ROM MONITOR VERSION 0.24$'

 TOP_RAM_MSG	DB	'Top of RAM=$'
 SP_MSG		DB	'H  SP=$'
@@ -3024,7 +3082,9 @@ GET_DMA_MSG	DB	'Enter RAM location for sector data (xxxxH) = $'
 Write_Sure:	DB	'Warning: this will change data on the drive, '
 		DB	'are you sure? (Y/N)...$'
 msgwr:		DB	'Sec. Write OK',CR,LF,'$'
-
+NMI_MSG:	DB	'NMI Activated',CR,LF,'$'	;0E00FH
+INT0_MSG:	DB	'INT0 Activated',CR,LF,'$'	;0E01FH
+SLAVE_MSG	DB	BELL,'Activate Master/Slave switch',CR,LF,'$'



--- a/Source/HBIOS/sd.asm
+++ b/Source/HBIOS/sd.asm
@@ -9,14 +9,14 @@
 ;	- TEST XC CARD TYPE DETECTION
 ;	- TRY TO GET INIT TO FAIL, REMOVE DELAYS AT START OF GOIDLE?
 ;
-;----------------------------------------------------------------------------------------------
-; SD Signal	Active	JUHA	N8	CSIO	PPI	UART	DSD	MK4	SC	MT
-; ------------	------- ------- ------- ------- ------- ------- ------- -------	-------	-------
-; CS (DAT3)	LO ->	RTC:2	RTC:2	RTC:2	~PC:4	~MCR:3	OPR:2	SD:2	~RTC:2/3OPR:4/5
-; CLK		HI ->	RTC:1	RTC:1	CSIO	PC:1	~MCR:2	OPR:1	CSIO	CSIO	SPI
-; DI (CMD)	HI ->	RTC:0	RTC:0	CSIO	PC:0	~MCR:0	OPR:0	CSIO	CSIO	SPI
-; DO (DAT0)	HI ->	RTC:7	RTC:6	CSIO	PB:7	~MSR:5	OPR:0	CSIO	CSIO	SPI
-;----------------------------------------------------------------------------------------------
+;-----------------------------------------------------------------------------------------------------
+; SD Signal	Active	JUHA	N8	CSIO	PPI	UART	DSD	MK4	SC	MT     PIO
+; ------------	------- ------- ------- ------- ------- ------- ------- -------	-------	--------------
+; CS (DAT3)	LO ->	RTC:2	RTC:2	RTC:2	~PC:4	~MCR:3	OPR:2	SD:2	~RTC:2/3OPR:4/5~OPR:3
+; CLK		HI ->	RTC:1	RTC:1	CSIO	PC:1	~MCR:2	OPR:1	CSIO	CSIO	SPI    OPR:4
+; DI (CMD)	HI ->	RTC:0	RTC:0	CSIO	PC:0	~MCR:0	OPR:0	CSIO	CSIO	SPI    OPR:0
+; DO (DAT0)	HI ->	RTC:7	RTC:6	CSIO	PB:7	~MSR:5	OPR:0	CSIO	CSIO	SPI    OPR:7
+;-----------------------------------------------------------------------------------------------------
 ;
 ; CS = CHIP SELECT (AKA DAT3 FOR NON-SPI MODE)
 ; CLK = CLOCK
@@ -167,6 +167,7 @@ RTCDEF		.SET	RTCDEF | SD_OPRDEF	; SET DEFAULT IN HBIOS MAINLINE
 SD_DEVMAX	.EQU	1		; NUMBER OF PHYSICAL UNITS (SOCKETS)
 SD_PPIBASE	.EQU	SDPPIBASE	; BASE IO PORT FOR PPI
 SD_PPIB		.EQU	SDPPIBASE + 1	; PPI PORT B (INPUT: DOUT)
+SD_PPIB		.EQU	SDPPIBASE + 1	; PPI PORT B (INPUT: DOUT)
 SD_PPIC		.EQU	SDPPIBASE + 2	; PPI PORT C (OUTPUT: CS, CLK, DIN)
 SD_PPIX		.EQU	SDPPIBASE + 3	; PPI CONTROL PORT
 SD_OPRREG	.EQU	SD_PPIC		; PPI PORT C IS OPR REG
@@ -298,7 +299,10 @@ SD_INVCS	.EQU	FALSE		; INVERT CS
 SD_DEVMAX	.EQU	1		; NUMBER OF PHYSICAL UNITS (SOCKETS)
 SD_IOBASE	.EQU	$69		; IO BASE ADDRESS FOR SD INTERFACE
 SD_OPRREG	.EQU	SD_IOBASE	; OUTPUT PORT (OUTPUT: CS, CLK, DIN)
-SD_OPRDEF	.EQU	%11111111	; OUTPUT PORT DEFAULT STATE
+;--- WBW
+;SD_OPRDEF	.EQU	%11111111	; OUTPUT PORT DEFAULT STATE
+SD_OPRDEF	.EQU	%11101111	; OUTPUT PORT DEFAULT STATE
+;---
 SD_INPREG	.EQU	SD_IOBASE	; INPUT REGISTER
 SD_CS0		.EQU	%00001000	; SELECT
 SD_CLK		.EQU	%00010000	; CLOCK
@@ -1801,6 +1805,7 @@ SD_SETUP:
 ;
 #IF (SDMODE == SDMODE_PIO)
 	LD	A,SD_OPRDEF		; All output bits high
+	LD	(SD_OPRVAL),A		; WBW
 	OUT	(SD_OPRREG),A
 	LD	A,$CF			; Port B mode 3
 	OUT	(SD_DDR),A
--- a/Source/ver.inc
+++ b/Source/ver.inc
@@ -2,7 +2,7 @@
 #DEFINE	RMN	3
 #DEFINE	RUP	0
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.3.0-dev.31"
+#DEFINE BIOSVER	"3.3.0-dev.35"
 #define rmj	RMJ
 #define rmn	RMN
 #define rup	RUP
--- a/Source/ver.lib
+++ b/Source/ver.lib
@@ -3,5 +3,5 @@ rmn	equ	3
 rup	equ	0
 rtp	equ	0
 biosver	macro
-	db	"3.3.0-dev.31"
+	db	"3.3.0-dev.35"
 	endm
Author	SHA1	Message	Date
Wayne Warthen	faaba69554	Improve sd.asm SD Card Compatibility - PIO mode of sd.asm driver modified to setup shadow register (Issue #352). - Relocated Z280 IVT to improve space utilization in HBIOS bank.	2023-07-17 14:52:14 -07:00
Wayne Warthen	0395bba4f5	Preliminary Support for ESP32 Nhyodyne Module - Initial console support for Dan Werner's ESP32 Module	2023-07-10 13:16:24 -07:00
Wayne Warthen	14ac7a917b	Upgrade s100mon to Latest - Incorporated latest S100 Board Monitor code from John Monahan	2023-07-09 12:38:48 -07:00