Device Type ID Reorganization

Driver Device Type ID's have been stored in the upper nibble. However, running out of ID's, I have changed them to occupy the entire byte. This is a breaking change, so I have updated the minor version number to maintain integrity between components. So, v3.3 will never become a stable release and I am moving directly to v3.4.
Bump Version
2026-02-06 22:43:15 -06:00 · 2023-10-05 18:08:52 -07:00 · 2023-10-05 15:33:41 -07:00 · 2023-10-05 15:04:26 -07:00 · 2023-10-05 10:14:30 -07:00 · 2023-10-04 16:54:34 -07:00
228 changed files with 8885 additions and 1318 deletions
--- a/Binary/ReadMe.txt
+++ b/Binary/ReadMe.txt
@@ -39,8 +39,8 @@ image for the Mark IV with the standard configuration. If a custom
 configuration called "custom" is created and built, a new file called 
 MK4_custom.rom will be added to this directory.

-Documentation of the pre-built ROM Images is contained in the 
-RomList.txt file in this directory.
+Documentation of the pre-built ROM Images is contained in
+"RomWBW User Guide.pdf" in the Doc directory.

 ROM Firmware Update Images (<plt>_<cfg>.upd)
 -------------------------------------
--- a/Doc/ChangeLog.txt
+++ b/Doc/ChangeLog.txt
@@ -1,3 +1,8 @@
+Version 3.4
+-----------
+NOTE: Changes require HBIOS/CBIOS/Apps sync, version bump to 3.4 to ensure integrity
+- WBW: Device type number moved from upper nibble to full byte
+
 Version 3.3
 -----------
 - WBW: Support Front Panel switches
@@ -15,6 +20,14 @@ Version 3.3
 - JBL: Added RCZ80 configuration for ColecoVision
 - WBW: Support for Z180 running interrupt mode 1
 - WBW: Preliminary support for S100 Computers Z180
+- WBW: Preliminary support for Dan Werner's ESP32 MBC Module
+- WBW: Early support for Duodyne base system (CPU/UART/ROM/RAM/RTC/SPK)
+- M?C: Fixed XM to allow specifying HBIOS port for send operations
+- WBW: Fix S100 Z180 LED operation (credit to Jay Cotton for finding this issue)
+- WBW: QPM system image is now combined with current CBIOS during build
+- WBW: Added framework for Heath platform
+- WBW: Support for USB Disks via CH375/CH376
+- D?J: Support for Raspberry Pi build process

 Version 3.2.1
 -------------
--- a/Applications.pdf
+++ b/Applications.pdf
--- a/Catalog.pdf
+++ b/Catalog.pdf
--- a/Errata.pdf
+++ b/Errata.pdf
--- a/Applications.pdf
+++ b/Applications.pdf
--- a/Doc/RomWBW
+++ b/Doc/RomWBW
--- a/Doc/RomWBW
+++ b/Doc/RomWBW
--- a/ReadMe.md
+++ b/ReadMe.md
@@ -3,7 +3,7 @@
 **RomWBW ReadMe** \
 Version 3.3 \
 Wayne Warthen  ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \
-07 Jul 2023
+05 Oct 2023

 # Overview

--- a/ReadMe.txt
+++ b/ReadMe.txt
@@ -1,6 +1,6 @@
 RomWBW ReadMe
 Wayne Warthen (wwarthen@gmail.com)
-07 Jul 2023
+05 Oct 2023



--- a/Source/Apps/FDU/fdu.doc
+++ b/Source/Apps/FDU/fdu.doc
@@ -153,7 +153,8 @@ JP2 (/FAULT) shorted, JP3 (MINI): 2-3, JP4 (/DC/RDY): 2-3.

 The RCBus Scott Baker WDC-based floppy module should be jumpered
 for I/O base address 0x50 (SV1: 11-12), JP1 (/DACK): 1-2,
-JP2 (TC): 2-3.
+JP2 (TC): 2-3.  Note that pin 1 of JPX jumpers is toward the bottom
+of the board.

 The RCBus FDC by Alan Cox (Etched Pixels) needs to be strapped
 for base I/O address 0x48.
--- a/Source/Apps/Test/DMAmon/dmamon.asm
+++ b/Source/Apps/Test/DMAmon/dmamon.asm
@@ -12,12 +12,26 @@ DMAMODE_Z180	.EQU	2		; Z180 INTEGRATED DMA
 DMAMODE_Z280	.EQU	3		; Z280 INTEGRATED DMA
 DMAMODE_RC	.EQU	4		; RCBUS Z80 DMA
 DMAMODE_MBC	.EQU	5		; MBC
-DMAMODE_VDG	.EQU	6		; VELESOFT DATAGEAR
+DMAMODE_DUO	.EQU	6		; DUO
+DMAMODE_VDG	.EQU	7		; VELESOFT DATAGEAR
+;
+DMAMODE		.EQU	DMAMODE_DUO	; SELECT DMA DEVICE FOR TESTING
+;
+;==================================================================================================
+; SOME DEFAULT PLATFORM CONFIGURATIONS
+;==================================================================================================
 ;
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_MBC	; SELECT DMA DEVICE FOR TESTING
+DMALATCH	.EQU	DMABASE+1	; DMA: DMA LATCH ADDRESS
 DMAIOTST	.EQU	$68		; AN OUTPUT PORT FOR TESTING - 16C450 SERIAL OUT
 ;
+#IF (DMAMODE==DMAMODE_DUO)
+DMABASE		.SET	$40		; DMA: DMA0 BASE ADDRESS
+DMALATCH	.SET	$43		; DMA: DMA LATCH ADDRESS
+DMAIOTST	.SET	$58		; AN OUTPUT PORT FOR TESTING - 16C450 SERIAL OUT
+;DMAIOTST	.SET	$94		; AN ALT OUTPUT PORT FOR TESTING - RTC/SPEAKER/LEDS PORT
+#ENDIF
+;
 ;==================================================================================================
 ; HELPER MACROS AND EQUATES
 ;==================================================================================================
@@ -113,7 +127,7 @@ MAIN:
 	LD	SP,STACK		; STACK
 ;
 	call	PRTSTRD			; WELCOME
-	.db	"\n\rDMA Monitor V3\n\r$"
+	.db	"\n\rDMA Monitor V3.1\n\r$"
 ;
 #IF (INTENABLE)
 ;
@@ -122,6 +136,8 @@ MAIN:
 	ld	de,$A000
 	ld	bc,hsiz
 	ldir
+	ld	a,(dmaport)
+	ld	(int_dmaport),a
 ;
 	; Install interrupt vector (RomWBW specific!!!)
 	ld	hl,int		; pointer to my interrupt handler
@@ -156,17 +172,17 @@ MENULP1:
 	CP	'N'
 	JP	Z,DMATST_N		; MEMORY COPY ITER
 	CP	'0'
-	JP	Z,DMATST_01
+	JP	Z,DMATST_0		; PULSE DMA PORT
+	CP	'1'
+	JP	Z,DMATST_1		; PULSE LATCH PORT
 	CP	'O'
 	JP	Z,DMATST_O
-#IF !(DMAMODE==DMAMODE_VDG)
-	CP	'1'
-	JP	Z,DMATST_01
 	CP	'R'
 	JP	Z,DMATST_R		; TOGGLE RESET
 	CP	'Y'
-	JP	Z,DMATST_Y		; TOGGLE READY
-#ENDIF
+	JP	Z,DMATST_Y
+	cp	'L'
+	jp	z,DMACFG_L		; SET LATCH PORT
 	cp	'S'
 	jp	z,DMACFG_S		; SET PORT
 	cp	'V'
@@ -197,12 +213,20 @@ DMABYE:
 ;
 DMACFG_S:
 	call	PRTSTRD
-	.db	"\n\rSet port address\n\rPort:$"
+	.db	"\n\rSet DMA port address\n\rPort:$"
 	call	HEXIN
 	ld	hl,dmaport
 	ld	(hl),a
-	inc	hl
-	inc	a
+#IF (INTENABLE)
+	ld	(int_dmaport),a
+#ENDIF
+	jp	MENULP
+;
+DMACFG_L:
+	call	PRTSTRD
+	.db	"\n\rSet Latch port address\n\rPort:$"
+	call	HEXIN
+	ld	hl,dmalach
 	ld	(hl),a
 	jp	MENULP
 ;
@@ -234,11 +258,17 @@ DMATST_N:
 	CALL	DMAMemTestIter
 	JP	MENULP
 ;
-DMATST_01:
+DMATST_0:
 	call	PRTSTRD
-	.db	"\n\rPerforming Port Selection Test\n\r$"
-	CALL	DMA_Port01
-	JP	MENULP
+	.db	"\n\rPerforming DMA Port Selection Test\n\r$"
+	CALL	DMA_Port0
+	ret
+
+DMATST_1:
+	call	PRTSTRD
+	.db	"\n\rPerforming Latch Port Selection Test\n\r$"
+	CALL	DMA_Port1
+	ret
 ;
 DMATST_O:
 	call	PRTSTRD
@@ -255,7 +285,7 @@ DMATST_D:
 DMATST_Y:
 	call	PRTSTRD
 	.db	"\n\rPerforming Ready Bit Test\n\r$"
-	CALL	DMA_ReadyT
+	CALL	DMA_ReadyY
 	JP	MENULP
 ;
 DMATST_R:
@@ -289,6 +319,10 @@ DISPM:	call	PRTSTRD
 	.db	", Port=0x$"
 	LD	A,(dmaport)		; DISPLAY
 	CALL	PRTHEXBYTE		; DMA PORT
+	call	PRTSTRD
+	.db	", Latch Port=0x$"
+	ld	A,(dmalach)
+	CALL	PRTHEXBYTE		; DMA PORT
 ;
 #IF (INTENABLE)
 ;
@@ -351,7 +385,7 @@ DMA_INIT:
 	CALL	PRTHEXBYTE
 ;
 #IF !(DMAMODE==DMAMODE_VDG)
-	ld	a,(dmautil)
+	ld	a,(dmalach)
 	ld	c,a
 	LD	A,DMA_FORCE
 	out	(c),a			; force ready off
@@ -369,7 +403,8 @@ DMA_INIT:
 ;
 	ld	hl,DMACode		; program the
 	ld	b,DMACode_Len		; dma command
-	ld	c,DMABASE		; block
+	ld	a,(dmaport)
+	ld	c,a		; block
 ;
 	di
 	otir				; load dma
@@ -417,6 +452,7 @@ DMA_DEV_STR:
 	.TEXT	"Z280$"
 	.TEXT	"RCBUS$"
 	.TEXT	"MBC$"
+	.TEXT	"DUODYNE$"
 	.TEXT	"DATAGEAR$"
 ;
 DMA_SPD_STR:
@@ -479,11 +515,12 @@ DMACFG_V:
 ;==================================================================================================
 ;
 DMABUF	.TEXT	"0123456789abcdef"
+;DMABUF	.DB	$04,$00,$04,$00,$04,$00,$04,$00,$04,$00,$04,$00,$04,$00,$04,$00,$00,$00,$00 ; SPEAKER
 ;
 DMA_ReadyO:
 	call	PRTSTRD
 	.db	"\r\nOutputing string to port 0x$"
-	ld	a,DMAIOTST
+	ld	a,(tstport)
 	call	PRTHEXBYTE
 	call	NEWLINE
 ;
@@ -491,7 +528,7 @@ DMA_ReadyO:
 IOLoop:	push	bc
 	call	NEWLINE
 	ld	hl,DMABUF
-	ld	a,DMAIOTST
+	ld	a,(tstport)
 	ld	bc,16
 ;
 	call	DMAOTIR
@@ -502,16 +539,17 @@ IOLoop:	push	bc
 	ret
 ;
 ;==================================================================================================
-; PULSE PORT (COMMON ROUTINE WHERE A CONTAINS THE ASCII PORT OFFSET)
+; PULSE PORT
 ;==================================================================================================
 ;
-DMA_Port01:
+DMA_Port0:
+	ld	a,(dmaport)
+	jr	DMA_Port
+DMA_Port1:
+	ld	a,(dmalach)
+DMA_Port:
 	call	PRTSTRD
 	.db	"\r\nPulsing port 0x$"
-	sub	'0'			; Calculate
-	ld	c,a
-	ld	a,(dmaport)		; Port to
-	add	a,c
 	call	PRTHEXBYTE
 	call	NEWLINE
 	ld	c,a			; toggle
@@ -543,12 +581,9 @@ dlylp:	dec	bc
 ; TOGGLE READY BIT
 ;==================================================================================================
 ;
-DMA_ReadyT:
+DMA_ReadyY:
 	call	NEWLINE
-#IF !(DMAMODE==DMAMODE_VDG)
-
-#ENDIF
-	ld	a,(dmautil)
+	ld	a,(dmalach)
 	ld	c,a			; toggle
 	ld	b,$20			; loop counter
 portlp2:push	bc
@@ -558,14 +593,12 @@ portlp2:push	bc
 	.db	": ON$"
 	call	delay
 	ld	a,$FF
-;	ld	c,DMABASE+1
 	out	(c),a
 	call	PRTSTRD
 	.db	" -> OFF$"
 	call	delay
 	call	PRTSTRD
 	.db	"\r               \r$"
-;	ld	c,DMABASE+1
 	ld	a,0
 	out	(c),a
 	pop	bc
@@ -605,9 +638,9 @@ DMAMemMove1:
 ;
 DMAMemMove2:
 ;
-;	LD	HL,$8400	; PLANT
-;	LD	A,$00		; BAD
-;	LD	(HL),A		; SEED
+	;LD	HL,$8400	; PLANT
+	;LD	A,$00		; BAD
+	;LD	(HL),A		; SEED
 ;
 	LD	A,$AA		; CHECK COPY SUCCESSFULL
 	LD	HL,$8000
@@ -615,6 +648,14 @@ DMAMemMove2:
 NXTCMP:	CPI
 	JP	PO,CMPOK
 	JR	Z,NXTCMP
+
+	DEC	HL
+	CALL	PRTHEXWORDHL
+	LD	A,' '
+	CALL	COUT
+	LD	A,(HL)
+	CALL	PRTHEXBYTE
+	
 	RET			; RET W/ ZF CLEAR
 ;
 CMPOK:
@@ -1167,10 +1208,10 @@ CST:
 	RET
 ;
 USEINT	.DB	FALSE		; USE INTERRUPTS FLAG
-counter	.dw	0	
 dmaport	.db	DMABASE
-dmautil	.db	DMABASE+1
+dmalach	.db	DMALATCH
 dmaxfer	.db	DMA_XMODE
+tstport	.db	DMAIOTST
 dmavbs	.db	0
 SAVSTK:	.DW	2
 	.FILL	64
@@ -1187,11 +1228,16 @@ reladr	.equ	$		; relocation start adr
 	.org	$A000		; code will run here
 ;
 int:
+	;LD	E,'.'			; OUTPUT CHAR TO E
+	;LD	C,CIO_CONSOLE		; CONSOLE UNIT TO C
+	;LD	B,BF_CIOOUT		; HBIOS FUNC: OUTPUT CHAR
+	;CALL	$FFF0			; HBIOS OUTPUTS CHARACTER
+
 	; According to the DMA doc, you must issue
 	; a DMA_DISABLE command prior to a
 	; DMA_REINIT_STATUS_BYTE command to avoid a
 	; potential race condition.
-	ld	a,(dmaport)
+	ld	a,(int_dmaport)
 	ld	c,a
 	ld	a,DMA_DISABLE
 	out	(c),a
@@ -1211,6 +1257,11 @@ int:
 	or	$ff		; signal int handled
 	ret
 ;
+; data referred to in handler must reside in high mem
+;
+int_dmaport	.db	0	; hi mem copy of dmaport
+counter		.dw	0	; interrupt counter
+;
 hsiz	.equ	$ - $A000	; size of handler to relocate
 ;
 	.org	reladr + hsiz
--- a/Source/Apps/Test/I2C/Build.cmd
+++ b/Source/Apps/Test/I2C/Build.cmd
@@ -8,6 +8,8 @@ set TASMTABS=%TOOLS%\tasm32
 tasm -t180 -g3 -fFF i2cscan.asm i2cscan.com i2cscan.lst || exit /b
 tasm -t180 -g3 -fFF rtcds7.asm rtcds7.com rtcds7.lst || exit /b
 tasm -t180 -g3 -fFF i2clcd.asm i2clcd.com i2clcd.lst || exit /b
+tasm -t80 -g3 -ff srom.asm srom.com srom.lst || exit /b

 copy /Y i2c*.com ..\..\..\..\Binary\Apps\Test\ || exit /b
 copy /Y rtcds7*.com ..\..\..\..\Binary\Apps\Test\ || exit /b
+copy /Y srom.com ..\..\..\..\Binary\Apps\Test\ || exit /b
--- a/Source/Apps/Test/I2C/Makefile
+++ b/Source/Apps/Test/I2C/Makefile
@@ -1,4 +1,4 @@
-OBJECTS = i2cscan.com rtcds7.com i2clcd.com
+OBJECTS = i2cscan.com rtcds7.com i2clcd.com srom.com
 DEST = ../../../../Binary/Apps/Test/
 TOOLS = ../../../../Tools

--- a/Source/Apps/Test/I2C/i2cscan.asm
+++ b/Source/Apps/Test/I2C/i2cscan.asm
@@ -5,12 +5,13 @@
 ; MARCO MACCAFERRI, HTTPS://WWW.MACCASOFT.COM
 ; HBIOS VERSION BY PHIL SUMMERS (B1ACKMAILER) DIFFICULTLEVELHIGH@GMAIL.COM
 ;
-PCF	.EQU	1
-P8X180	.EQU	0
-SC126	.EQU	0
-SC137	.EQU	0
+PCFECB		.EQU	0
+PCFDUO		.EQU	1
+P8X180		.EQU	0
+SC126		.EQU	0
+SC137		.EQU	0
 ;
-#IF (PCF)
+#IF (PCFECB)
 I2C_BASE 	.EQU  	0F0H
 PCF_ID   	.EQU  	0AAH
 CPU_CLK	 	.EQU  	12
@@ -20,6 +21,16 @@ PCF_RS1  	.EQU  	PCF_RS0+1
 PCF_OWN	 	.EQU  	(PCF_ID >> 1)        	; PCF'S ADDRESS IN SLAVE MODE
 #ENDIF
 ;
+#IF (PCFDUO)
+I2C_BASE 	.EQU  	056H
+PCF_ID   	.EQU  	0AAH
+CPU_CLK	 	.EQU  	12
+;
+PCF_RS0  	.EQU  	I2C_BASE
+PCF_RS1  	.EQU  	PCF_RS0+1
+PCF_OWN	 	.EQU  	(PCF_ID >> 1)        	; PCF'S ADDRESS IN SLAVE MODE
+#ENDIF
+;
 #IF (P8X180)
 I2C_BASE	.EQU	0A0h
 _sda		.EQU	0
@@ -153,8 +164,11 @@ lp5f:	ld	a,(addr)	; next address
 	jp	0

 signon:	.db	"I2C Bus Scanner"
-#IF (PCF)
-	.DB	" - PCF8584"
+#IF (PCFECB)
+	.DB	" - PCF8584 (ECB)"
+#ENDIF
+#IF (PCFDUO)
+	.DB	" - PCF8584 (Duodyne)"
 #ENDIF
 #IF (SC126)
 	.DB	" - SC126"
@@ -219,7 +233,7 @@ _cout:				; character
 	ret

 ;-----------------------------------------------------------------------------
-#IF (PCF)
+#IF (PCFECB | PCFDUO)
 _i2c_start:
 PCF_START:
        LD     A,PCF_START_  
@@ -418,7 +432,7 @@ PCF_PINFAIL 	.DB	"PIN FAIL$"
 PCF_BBFAIL	.DB	"BUS BUSY$"
 ;
 ;-----------------------------------------------------------------------------
-#IF (PCF)
+#IF (PCFECB | PCFDUO)
 _i2c_stop:  
 PCF_STOP: 
 	LD   	A,PCF_STOP_	; issue 
--- a/Source/Apps/Test/I2C/srom.asm
+++ b/Source/Apps/Test/I2C/srom.asm
--- a/Source/Apps/XM/xmdm125.asm
+++ b/Source/Apps/XM/xmdm125.asm
@@ -720,12 +720,17 @@ NOBYE:	LXI	H,FCB+1		; Get primary option
 ; Send option processor
 ; Single option: "K"	- force 1k mode
 ;
-	INX	H		; Look for a 'K'
+	CALL	SNDOPC
+	CALL	SNDOPC
+	JMP	ALLSET
+SNDOPC:INX	H		; Look for an option
 	MOV	A,M
 	CPI	' '		; Is it a space?
-	JZ	ALLSET		; Then we're ready to send...
-	CPI	'K'
-	JNZ	OPTERR		; "K" is the only setable 2nd option
+	JNZ	CHKK
+	POP	PSW
+	JMP	ALLSET
+CHKK:	CPI	'K'
+	JNZ	CHK6TH		; If it's not K it should be a port number
 	LDA	MSPEED
 	CPI	MINKSP		; If less than MINKSP bps, ignore 1k
 	JC	ALLSET		; Request
@@ -733,7 +738,7 @@ NOBYE:	LXI	H,FCB+1		; Get primary option
 	STA	KFLAG		; First, force us to 1K mode
 	CALL	ILPRT
 	DB	'(1k protocol selected)',CR,LF,0
-	JMP	ALLSET		; That's it for send...
+	RET		; That's it for send...
 ;
 ; Receive option processor
 ; 3 or 4 options: "X"	- disable auto-protocol select
@@ -5789,4 +5794,4 @@ BDPTOS	EQU	83		; Print Time on System
 	 ENDIF			; BYEBDOS
 ;
 	END
-
+
--- a/Source/Apps/assign.asm
+++ b/Source/Apps/assign.asm
@@ -31,6 +31,7 @@
 ;   2022-02-28 [WBW] Use HBIOS to swap banks under CP/M 3
 ;                    Use CPM3 BDOS direct BIOS call to get DRVTBL adr
 ;   2023-06-19 [WBW] Update for revised DIODEVICE API
+;   2023-09-19 [WBW] Added CHUSB & CHSD device support
 ;_______________________________________________________________________________
 ;
 ; ToDo:
@@ -1065,10 +1066,6 @@ drvmap1:	; loop through device table looking for a match
 drvmap2:	
 	; convert index to device type id
 	ld	a,c		; index to accum
-	rlca			; move it to upper nibble
-	rlca			; ...
-	rlca			; ...
-	rlca			; ...
 	ld	(device),a	; save as device id
 ;
 	; loop thru hbios units looking for device type/unit match
@@ -1308,10 +1305,6 @@ prtdev:
 	rst	08		; call hbios, D := device, E := unit
 	push	de		; save results
 	ld	a,d		; device to A
-	rrca			; isolate high nibble (device)
-	rrca			;   ...
-	rrca			;   ...
-	rrca			;   ... into low nibble
 	and	$0F		; mask out undesired bits
 	push	hl		; save HL
 	add	a,a		; multiple A by two for word table
@@ -1920,8 +1913,8 @@ dev09	.db	"HDSK",0
 dev10	.db	"PPA",0
 dev11	.db	"IMM",0
 dev12	.db	"SYQ",0
-dev13	.equ	devunk
-dev14	.equ	devunk
+dev13	.db	"CHUSB",0
+dev14	.db	"CHSD",0
 dev15	.equ	devunk
 ;
 devcnt	.equ	10		; 10 devices defined
@@ -1942,10 +1935,10 @@ stack	.equ	$		; stack top
 ; Messages
 ;
 indent	.db	"   ",0
-msgban1	.db	"ASSIGN v1.6 for RomWBW CP/M ",0
+msgban1	.db	"ASSIGN v1.7 for RomWBW CP/M ",0
 msg22	.db	"2.2",0
 msg3	.db	"3",0
-msbban2	.db	", 16-Jun-2023",0
+msbban2	.db	", 19-Sep-2023",0
 msghb	.db	" (HBIOS Mode)",0
 msgub	.db	" (UBIOS Mode)",0
 msgban3	.db	"Copyright 2021, Wayne Warthen, GNU GPL v3",0
--- a/Source/Apps/rtc.asm
+++ b/Source/Apps/rtc.asm
@@ -51,7 +51,7 @@ PORT_DYNO	.EQU	$0C		; RTC port for DYNO
 PORT_RCZ280	.EQU	$C0		; RTC port for RCZ280
 PORT_MBC	.EQU	$70		; RTC port for MBC
 PORT_RPH	.EQU	$84		; RTC port for RHYOPHYRE
-PORT_DUO	.EQU	$70		; RTC port for DUODYNE
+PORT_DUO	.EQU	$94		; RTC port for DUODYNE


 BDOS		.EQU	5		; BDOS invocation vector
@@ -1140,7 +1140,7 @@ HINIT:
 ;
 	LD	C,PORT_DUO
 	LD	DE,PLT_DUO
-	CP	13		; DUODYNE
+	CP	17		; DUODYNE
 	JP	Z,RTC_INIT2
 ;
 	; Unknown platform
--- a/Source/BPBIOS/diskdefs
+++ b/Source/BPBIOS/diskdefs
@@ -310,6 +310,32 @@ diskdef wbw_rom1024
  os 2.2
 end

+# RomWBW 512KB RAM (256KB reserved, 256KB RAM Disk)
+
+diskdef wbw_ram512
+  seclen 512
+  tracks 8
+  sectrk 64
+  blocksize 2048
+  maxdir 256
+  skew 0
+  boottrk 0
+  os 2.2
+end
+
+# RomWBW 1024KB RAM (256KB reserved, 768KB RAM Disk)
+
+diskdef wbw_ram1024
+  seclen 512
+  tracks 24
+  sectrk 64
+  blocksize 2048
+  maxdir 256
+  skew 0
+  boottrk 0
+  os 2.2
+end
+
 # RomWBW 720K floppy media

 diskdef wbw_fd720
--- a/Source/BuildShared.cmd
+++ b/Source/BuildShared.cmd
@@ -4,6 +4,7 @@ setlocal
 pushd HDIAG && call Build || exit /b & popd
 pushd CBIOS && call Build || exit /b & popd
 pushd CPM22 && call Build || exit /b & popd
+pushd QPM && call Build || exit /b & popd
 pushd ZCPR && call Build || exit /b & popd
 pushd ZCPR-DJ && call Build || exit /b & popd
 pushd ZSDOS && call Build || exit /b & popd
--- a/Source/CBIOS/cbios.asm
+++ b/Source/CBIOS/cbios.asm
@@ -2529,24 +2529,21 @@ MD_INIT:
 ; UDPATE THE RAM/ROM DPB STRUCTURES BASED ON HARDWARE
 ;
 #IFDEF PLTWBW
-	; TODO: HANDLE DISABLED RAM/ROM DISK BETTER.
-	; IF RAM OR ROM DISK ARE DISABLED, BELOW WILL STILL
-	; TRY TO ADJUST THE DPB BASED ON RAM BANK CALCULATIONS.
-	; IT SHOULD NOT MATTER BECAUSE THE DPB SHOULD NEVER BE
-	; USED.  IT WOULD BE BETTER TO GET RAMD0/ROMD0 AND
-	; RAMDN/ROMDN FROM THE HCB AND USE THOSE TO CALC THE
-	; DPB ADJUSTMENT.  IF DN-D0=0, BYPASS ADJUSTMENT.
-	LD	A,(HCB + HCB_ROMBANKS)	; ROM BANK COUNT
-	SUB	4		; REDUCE BANK COUNT BY RESERVED PAGES
-	LD	IX,DPB_ROM	; ADDRESS OF DPB
-	CALL	MD_INIT1	; FIX IT UP
+	; NOTE: ROM AND/OR RAM DISK MAY NOT BE ACTIVE, BUT WE GO
+	; AHEAD AND UPDATE BOTH DPBS ANYWAY.  IT CAUSES NO HARM SINCE
+	; INACTIVE RAM/ROM DISK WILL NEVER BE ACCESSED.
 ;
-	LD	A,(HCB + HCB_RAMBANKS)	; RAM BANK COUNT
-	SUB	8		; REDUCE BANK COUNT BY RESERVED PAGES
-	LD	IX,DPB_RAM	; ADDRESS OF DPB
-	CALL	MD_INIT1	; FIX IT UP
+	; ROM DISK
+	LD	A,(HCB + HCB_ROMD_BNKS)	; ROM DISK SIZE IN BANKS
+	LD	IX,DPB_ROM		; ADDRESS OF DPB
+	CALL	MD_INIT1		; FIX IT UP
 ;
-	JR	MD_INIT4	; DONE
+	; RAM DISK
+	LD	A,(HCB + HCB_RAMD_BNKS)	; RAM DISK SIZE IN BANKS
+	LD	IX,DPB_RAM		; ADDRESS OF DPB
+	CALL	MD_INIT1		; FIX IT UP
+;	
+	JR	MD_INIT4		; DONE
 ;
 MD_INIT1:
 ;
@@ -3349,10 +3346,6 @@ DEVUNK		.DB	"UNK$"
 	RST	08		; CALL HBIOS
 	LD	A,D		; RESULTANT DEVICE TYPE
 	PUSH	DE		; NEED TO SAVE UNIT NUMBER (IN E)
-	RRCA			; ROTATE DEVICE
-	RRCA			; ... BITS
-	RRCA			; ... INTO
-	RRCA			; ... LOWEST 4 BITS
 	AND	$0F		; ISOLATE DEVICE BITS
 	ADD	A,A		; MULTIPLY BY TWO FOR WORD TABLE
 	LD	HL,DEVTBL	; POINT TO START OF DEVICE NAME TABLE
@@ -3394,8 +3387,8 @@ DEV09	.DB	"HDSK$"
 DEV10	.DB	"PPA$"
 DEV11	.DB	"IMM$"
 DEV12	.DB	"SYQ$"
-DEV13	.EQU	DEVUNK
-DEV14	.EQU	DEVUNK
+DEV13	.DB	"CHUSB$"
+DEV14	.DB	"CHSD$"
 DEV15	.EQU	DEVUNK
 ;
 #ENDIF
--- a/Source/CPM3/diskio.z80
+++ b/Source/CPM3/diskio.z80
@@ -355,38 +355,30 @@ dpb$hdnew:	; 8MB Hard Disk Drive (new format)
 ;		called for first time initialization.

 dsk$init:
-	; TODO: Handle disabled RAM/ROM disk better.
-	; If RAM or ROM disk are disabled, below will still
-	; try to adjust the DPB based on RAM bank calculations.
-	; It should not matter because the DPB should never be
-	; used.  It would be better to get RAMD0/ROMD0 and
-	; RAMDN/ROMDN from the HCB and use those to calc the
-	; DPB adjustment.  If DN-D0=0, bypass adjustment.
-	ld	b,0FAh			; HBIOS Peek Function
-	ld	a,(@hbbio)		; HBIOS bank id
-	ld	d,a			; ... goes in D
-	ld	hl,10Ch			; Offset 10Ch is ROM bank cnt
-	rst	08			; Call HBIOS, value in E
-	ld	a,e			; move count to accum
-	sub	4			; reduce by # reserved banks
-	ld	ix,dpb$rom		; address of DPB
-	call	dsk$init1		; fix it up
-	
-	ld	b,0FAh			; HBIOS Peek Function
-	ld	a,(@hbbio)		; HBIOS bank id
-	ld	d,a			; ... goes in D
-	ld	hl,10Bh			; Offset 10Bh is RAM bank cnt
-	rst	08			; Call HBIOS, value in E
-	ld	a,e			; move count to accum
-	sub	8			; reduce by # reserved banks
-	ld	ix,dpb$ram		; address of DPB
-	call	dsk$init1		; fix it up

+	; NOTE: ROM and/or RAM disk may not be active, but we go
+	; ahead and update both DPBs anyway.  It causes no harm since
+	; inactive RAM/ROM disk will never be accessed.
+
+	ld	hl,1DFh			; ROM disk bank cnt in HCB
+	ld	ix,dpb$rom		; address of ROM Disk DPB
+	call	dsk$init1		; fix it up
+	ld	hl,1DDh			; RAM dsik bank cnt in HCB
+	ld	ix,dpb$ram		; address of RAM Disk DPB
+	call	dsk$init1		; fix it up
 	ret				; done

 dsk$init1:
+	; Get bank count of RAM/ROM disk
+	ld	b,0FAh			; HBIOS Peek Function
+	ld	a,(@hbbio)		; HBIOS bank id
+	ld	d,a			; ... goes in D
+	rst	08			; Call HBIOS, value in E
+	;ld	a,e			; move count to accum
+
 	; Setup HL with bank count
-	ld	l,a			; lsb
+	;ld	l,a			; lsb
+	ld	l,e			; lsb
 	ld	h,0			; msb is always zero

 	; Update EXM field
--- a/Source/CPM3/genbnk.dat
+++ b/Source/CPM3/genbnk.dat
@@ -8,12 +8,12 @@ MEMTOP   = FD
 BNKSWT   = Y
 COMBAS   = 80
 LERROR   = Y
-NUMSEGS  = 04
+NUMSEGS  = 02
 MEMSEG00 = 01,17,00
 MEMSEG01 = 0E,72,02
 MEMSEG02 = 01,7F,03
-MEMSEG03 = 01,7F,04
-MEMSEG04 = 01,7F,05
+MEMSEG03 = 00,C0,04
+MEMSEG04 = 00,C0,05
 MEMSEG05 = 00,C0,06
 MEMSEG06 = 00,C0,07
 MEMSEG07 = 00,C0,08
@@ -25,38 +25,38 @@ MEMSEG0C = 00,C0,0D
 MEMSEG0D = 00,C0,0E
 MEMSEG0E = 00,C0,0F
 MEMSEG0F = 00,C0,10
-HASHDRVA = Y
-HASHDRVB = Y
-HASHDRVC = Y
-HASHDRVD = Y
-HASHDRVE = Y
-HASHDRVF = Y
-HASHDRVG = Y
-HASHDRVH = Y
-HASHDRVI = Y
-HASHDRVJ = Y
-HASHDRVK = Y
-HASHDRVL = Y
-HASHDRVM = Y
-HASHDRVN = Y
-HASHDRVO = Y
-HASHDRVP = Y
-ALTBNKSA = Y
-ALTBNKSB = Y
-ALTBNKSC = Y
-ALTBNKSD = Y
-ALTBNKSE = Y
-ALTBNKSF = Y
-ALTBNKSG = Y
-ALTBNKSH = Y
-ALTBNKSI = Y
-ALTBNKSJ = Y
-ALTBNKSK = Y
-ALTBNKSL = Y
-ALTBNKSM = Y
-ALTBNKSN = Y
-ALTBNKSO = Y
-ALTBNKSP = Y
+HASHDRVA = N
+HASHDRVB = N
+HASHDRVC = N
+HASHDRVD = N
+HASHDRVE = N
+HASHDRVF = N
+HASHDRVG = N
+HASHDRVH = N
+HASHDRVI = N
+HASHDRVJ = N
+HASHDRVK = N
+HASHDRVL = N
+HASHDRVM = N
+HASHDRVN = N
+HASHDRVO = N
+HASHDRVP = N
+ALTBNKSA = N
+ALTBNKSB = N
+ALTBNKSC = N
+ALTBNKSD = N
+ALTBNKSE = N
+ALTBNKSF = N
+ALTBNKSG = N
+ALTBNKSH = N
+ALTBNKSI = N
+ALTBNKSJ = N
+ALTBNKSK = N
+ALTBNKSL = N
+ALTBNKSM = N
+ALTBNKSN = N
+ALTBNKSO = N
+ALTBNKSP = N
 NDIRRECA = 08
 NDIRRECB = 00
 NDIRRECC = 00
--- a/Source/CPM3/genres.dat
+++ b/Source/CPM3/genres.dat
@@ -8,7 +8,7 @@ MEMTOP   = FD
 BNKSWT   = N
 COMBAS   = 00
 LERROR   = Y
-NUMSEGS  = 03
+NUMSEGS  = 01
 MEMSEG00 = 00,80,00
 MEMSEG01 = 00,C0,02
 MEMSEG02 = 00,C0,03
--- a/Source/CPM3/move.z80
+++ b/Source/CPM3/move.z80
@@ -65,12 +65,11 @@ xbnkmov:
 ; ------------	--------------	-------
 ; COMMON	BID_COM		8Fh
 ; 0: OS/BUFS	BID_USR         8Eh
-;		BID_BIOS	8Dh	
-; 1: TPA	BID_AUX		8Ch
-; 2: BUFS	BID_AUX-1	8Bh
-; 3: BUFS	BID_AUX-2	8Ah
-; 4: BUFS	BID_AUX-3	89h
-; 5: BUFS	BID_AUX-4	88h
+; 1: TPA	BID_AUX		8Dh
+; 2: BUFS	BID_AUX-1	8Ch
+; 3: BUFS	BID_AUX-2	8Bh
+; 4: BUFS	BID_AUX-3	8Ah
+; 5: BUFS	BID_AUX-4	89h
 ;
 ; N.B., Below BID_AUX is considered RAM disk bank.  Need to
 ; make sure RAM disk is kept small enough to stay below
@@ -80,17 +79,13 @@ xbnkmov:
 ; to adjust for real size of RAM in system
 ;
 ?bnkxlt:
-	or	a
-	jr	z,bank0
-	neg			; 2 -> -2
-	add	a,8Dh		; 8Dh - 2 = 8Bh
-@hbbio	equ	$ - 1		; BID_BIOS
-	ret
-bank0:
-	ld	a,8Eh		; 0 -> 8Eh
+	neg			; ex: 2 -> -2
+	add	a,8Eh		; ex: 8Eh - 2 = 8Ch
@hbusr	equ	$ - 1		; BID_USR
 	ret
-	
+
+@hbbio	db	0		; BID_BIOS
+
 movtyp	db	0		; non-zero for interbank move

 movbnks:
--- a/Source/Clean.cmd
+++ b/Source/Clean.cmd
@@ -4,6 +4,7 @@ setlocal
 pushd HDIAG && call Clean.cmd & popd
 pushd Apps && call Clean.cmd & popd
 pushd CPM22 && call Clean.cmd & popd
+pushd QPM && call Clean.cmd & popd
 pushd ZCPR && call Clean.cmd & popd
 pushd ZCPR-DJ && call Clean.cmd & popd
 pushd ZSDOS && call Clean.cmd & popd
--- a/Source/Doc/SystemGuide.md
+++ b/Source/Doc/SystemGuide.md
@@ -390,17 +390,20 @@ below enumerates these values.
 | **Device Type** | **ID** | **Description**                          | **Driver** |
 |-----------------|-------:|------------------------------------------|------------|
 | CIODEV_UART     | 0x00   | 16C550 Family Serial Interface           | uart.asm   |
-| CIODEV_ASCI     | 0x10   | Z180 Built-in Serial Ports               | asci.asm   |
-| CIODEV_TERM     | 0x20   | Terminal                                 | ansi.asm   |
-| CIODEV_PRPCON   | 0x30   | PropIO Serial Console Interface          | prp.asm    |
-| CIODEV_PPPCON   | 0x40   | ParPortProp Serial Console Interface     | ppp.asm    |
-| CIODEV_SIO      | 0x50   | Zilog Serial Port Interface              | sio.asm    |
-| CIODEV_ACIA     | 0x60   | MC68B50 Asynchronous Interface           | acia.asm   |
-| CIODEV_PIO      | 0x70   | Zilog Parallel Interface Controller      | pio.asm    |
-| CIODEV_UF       | 0x80   | FT232H-based ECB USB FIFO                | uf.asm     |
-| CIODEV_DUART    | 0x90   | SCC2681 Family Dual UART                 | duart.asm  |
-| CIODEV_Z2U      | 0xA0   | Zilog Z280 Built-in Serial Ports         | z2u.asm    |
-| CIODEV_LPT      | 0xB0   | Parallel I/O Controller                  | lpt.asm    |
+| CIODEV_ASCI     | 0x01   | Z180 Built-in Serial Ports               | asci.asm   |
+| CIODEV_TERM     | 0x02   | Terminal                                 | ansi.asm   |
+| CIODEV_PRPCON   | 0x03   | PropIO Serial Console Interface          | prp.asm    |
+| CIODEV_PPPCON   | 0x04   | ParPortProp Serial Console Interface     | ppp.asm    |
+| CIODEV_SIO      | 0x05   | Zilog Serial Port Interface              | sio.asm    |
+| CIODEV_ACIA     | 0x06   | MC68B50 Asynchronous Interface           | acia.asm   |
+| CIODEV_PIO      | 0x07   | Zilog Parallel Interface Controller      | pio.asm    |
+| CIODEV_UF       | 0x08   | FT232H-based ECB USB FIFO                | uf.asm     |
+| CIODEV_DUART    | 0x09   | SCC2681 Family Dual UART                 | duart.asm  |
+| CIODEV_Z2U      | 0x0A   | Zilog Z280 Built-in Serial Ports         | z2u.asm    |
+| CIODEV_LPT      | 0x0B   | Parallel I/O Controller                  | lpt.asm    |
+| CIODEV_ESPCON   | 0x0B   | ESP32 VGA Console                        | esp.asm    |
+| CIODEV_ESPSER   | 0x0B   | ESP32 Serial Port                        | esp.asm    |
+| CIODEV_SCON     | 0x0B   | S100 Console                             | scon.asm   |

 Character devices can usually be configured with line characteristics
 such as speed, framing, etc. A word value (16 bit) is used to describe
@@ -568,15 +571,20 @@ below enumerates there values.
 | **Device Type** | **ID** | **Description**                          | **Driver** |
 |-----------------|-------:|------------------------------------------|------------|
 | DIODEV_MD       | 0x00   | Memory Disk                              | md.asm     |
-| DIODEV_FD       | 0x10   | Floppy Disk                              | fd.asm     |
-| DIODEV_RF       | 0x20   | RAM Floppy                               | rf.asm     |
-| DIODEV_IDE      | 0x30   | IDE Disk                                 | ide.asm    |
-| DIODEV_ATAPI    | 0x40   | ATAPI Disk (not implemented)             |            |
-| DIODEV_PPIDE    | 0x50   | PPIDE Disk                               | ppide.asm  |
-| DIODEV_SD       | 0x60   | SD Card                                  | sd.asm     |
-| DIODEV_PRPSD    | 0x70   | PropIO SD Card                           | prp.asm    |
-| DIODEV_PPPSD    | 0x80   | ParPortProp SD Card                      | ppp.asm    |
-| DIODEV_HDSK     | 0x90   | SIMH HDSK Disk                           | hdsk.asm   |
+| DIODEV_FD       | 0x01   | Floppy Disk                              | fd.asm     |
+| DIODEV_RF       | 0x02   | RAM Floppy                               | rf.asm     |
+| DIODEV_IDE      | 0x03   | IDE Disk                                 | ide.asm    |
+| DIODEV_ATAPI    | 0x04   | ATAPI Disk (not implemented)             |            |
+| DIODEV_PPIDE    | 0x05   | PPIDE Disk                               | ppide.asm  |
+| DIODEV_SD       | 0x06   | SD Card                                  | sd.asm     |
+| DIODEV_PRPSD    | 0x07   | PropIO SD Card                           | prp.asm    |
+| DIODEV_PPPSD    | 0x08   | ParPortProp SD Card                      | ppp.asm    |
+| DIODEV_HDSK     | 0x09   | SIMH HDSK Disk                           | hdsk.asm   |
+| DIODEV_PPA      | 0x0A   | Iomega PPA Disk                          | ppa.asm    |
+| DIODEV_IMM      | 0x0B   | Iomega IMM Disk                          | imm.asm    |
+| DIODEV_SYQ      | 0x0C   | Syquest Sparq Disk                       | syq.asm    |
+| DIODEV_CHUSB    | 0x0D   | CH375/376 USB Disk                       | ch.asm     |
+| DIODEV_CHSD     | 0x0E   | CH375/376 SD Card                        | ch.asm     |

 A fixed set of media types are defined. The currently defined media 
 types identifiers are listed below. Each driver will support one or
@@ -878,11 +886,11 @@ unit.  The table below enumerates these values.
 | **Device Type** | **ID** | **Description**                          | **Driver** |
 |-----------------|-------:|------------------------------------------|------------|
 | RTCDEV_DS       | 0x00   | Maxim DS1302 Real-Time Clock w/ NVRAM    | dsrtc.asm  |
-| RTCDEV_BQ       | 0x10   | BQ4845P Real Time Clock                  | bqrtc.asm  |
-| RTCDEV_SIMH     | 0x20   | SIMH Simulator Real-Time Clock           | simrtc.asm |
-| RTCDEV_INT      | 0x30   | Interrupt-based Real Time Clock          | intrtc.asm |
-| RTCDEV_DS7      | 0x40   | Maxim DS1307 PCF I2C RTC w/ NVRAM        | ds7rtc.asm |
-| RTCDEV_RP5      | 0x50   | Ricoh RPC01A Real-Time Clock w/ NVRAM    | rp5rtc.asm |
+| RTCDEV_BQ       | 0x01   | BQ4845P Real Time Clock                  | bqrtc.asm  |
+| RTCDEV_SIMH     | 0x02   | SIMH Simulator Real-Time Clock           | simrtc.asm |
+| RTCDEV_INT      | 0x03   | Interrupt-based Real Time Clock          | intrtc.asm |
+| RTCDEV_DS7      | 0x04   | Maxim DS1307 PCF I2C RTC w/ NVRAM        | ds7rtc.asm |
+| RTCDEV_RP5      | 0x05   | Ricoh RPC01A Real-Time Clock w/ NVRAM    | rp5rtc.asm |

 The time functions to get and set the time (RTCGTM and RTCSTM) require a
 6 byte date/time buffer in the following format. Each byte is BCD 
@@ -1021,8 +1029,8 @@ unit.  The table below enumerates these values.

 | **Device Type** | **ID** | **Description**                          | **Driver** |
 |-----------------|-------:|------------------------------------------|------------|
-| DSKYDEV_ICM     | 0x00   | Original ICM7218 based DSKY              | icm.asm    |
-| DSKYDEV_PKD     | 0x10   | Next Gen Intel P8279 based DSKY          | pkd.asm    |
+| DSKYDEV_ICM     | 0x01   | Original ICM7218 based DSKY              | icm.asm    |
+| DSKYDEV_PKD     | 0x02   | Next Gen Intel P8279 based DSKY          | pkd.asm    |

 When segment display function encodes the display data in a byte per
 character format.  Currently, all segment displays are exactly
@@ -1214,10 +1222,11 @@ below enumerates there values.
 | **Device Type** | **ID** | **Description**                          | **Driver** |
 |-----------------|-------:|------------------------------------------|------------|
 | VDADEV_VDU      | 0x00   | MC6845 Family Video Display Controller   | vdu.asm    |
-| VDADEV_CVDU     | 0x10   | MC8563-based Video Display Controller    | cvdu.asm   |
-| VDADEV_GDC      | 0x20   | uPD7220 Video Display Controller         | gdc.asm    |
-| VDADEV_TMS      | 0x30   | TMS9918/38/58 Video Display Controller   | tms.asm    |
-| VDADEV_VGA      | 0x40   | HD6445CP4-based Video Display Controller | vga.asm    |
+| VDADEV_CVDU     | 0x01   | MC8563-based Video Display Controller    | cvdu.asm   |
+| VDADEV_GDC      | 0x02   | uPD7220 Video Display Controller         | gdc.asm    |
+| VDADEV_TMS      | 0x03   | TMS9918/38/58 Video Display Controller   | tms.asm    |
+| VDADEV_VGA      | 0x04   | HD6445CP4-based Video Display Controller | vga.asm    |
+| VDADEV_VRC      | 0x05   | VGARC                                    | vrc.asm    |

 Depending on the capabilities of the hardware, the use of colors and
 attributes may or may not be supported. If the hardware does not support
@@ -1629,9 +1638,9 @@ below enumerates these values.
 | **Device Type** | **ID** | **Description**                              | **Driver**  |
 |-----------------|-------:|----------------------------------------------|-------------|
 | SNDDEV_SN76489  | $00    | SN76489 Programmable Sound Generator         | sn76489.asm |
-| SNDDEV_AY38910  | $10    | AY-3-8910/YM2149 Programmable Sound Generator| ay38910.asm |
-| SNDDEV_BITMODE  | $20    | Bit-bang Speaker                             | spk.asm     |
-| SNDDEV_YM2612   | $30    | YM2612 Programmable Sound Generator          | ym2612.asm  |
+| SNDDEV_AY38910  | $01    | AY-3-8910/YM2149 Programmable Sound Generator| ay38910.asm |
+| SNDDEV_BITMODE  | $02    | Bit-bang Speaker                             | spk.asm     |
+| SNDDEV_YM2612   | $03    | YM2612 Programmable Sound Generator          | ym2612.asm  |

 The Sound functions defer the actual programming of the sound chip
 until the SNDPLAY function is called.  You will call the volume
--- a/Source/Doc/UserGuide.md
+++ b/Source/Doc/UserGuide.md
@@ -58,8 +58,9 @@ produced by these developer communities:

 General features include:

+* Z80 Family CPUs including Z80, Z180, and Z280
 * Banked memory services for several banking designs
-* Disk drivers for RAM, ROM, Floppy, IDE, CF, and SD
+* Disk drivers for RAM, ROM, Floppy, IDE ATA/ATAPI, CF, SD, Zip, Iomega
 * Serial drivers including UART (16550-like), ASCI, ACIA, SIO
 * Video drivers including TMS9918, SY6545, MOS8563, HD6445
 * Keyboard (PS/2) drivers via VT8242 or PPI interfaces
@@ -195,6 +196,7 @@ below, **carefully** pick the appropriate ROM image for your hardware.
 | [Small Computer SC131 Z180 Pocket Computer]^5^                 | -       | SCZ180_sc131.rom   | 115200        |
 | [Small Computer SC140 Z180 CPU Module]^5^                      | Z50     | SCZ180_sc140.rom   | 115200        |
 | [Small Computer SC503 Z180 CPU Module]^5^                      | Z50     | SCZ180_sc503.rom   | 115200        |
+| [Small Computer SC700 Z180 CPU Module]^5^                      | RCBus   | SCZ180_sc700.rom   | 115200        |
 | [Dyno Z180 SBC]^6^                                             | Dyno    | DYNO_std.rom       | 38400         |
 | [Nhyodyne Z80 MBC]^1^                                          | MBC     | MBC_std.rom        | 38400         |
 | [Rhyophyre Z180 SBC]^1^                                        | -       | RPH_std.rom        | 38400         |
@@ -204,6 +206,7 @@ below, **carefully** pick the appropriate ROM image for your hardware.
 | [Z80-Retro SBC]^8^                                             | -       | Z80RETRO_std.rom   | 38400         |
 | [S100 Computers Z180]^9^                                       | S100    | S100_std.rom       | 38400         |
 | [Duodyne Z80 System]^1^                                        | Duo     | DUO_std.rom        | 38400         |
+| [Heath H8 Z80 System]                                          | H8      | HEATH_std.rom      | 115200        |

 | ^1^Designed by Andrew Lynch
 | ^2^Designed by Sergey Kiselev
@@ -1297,7 +1300,7 @@ is considered the "legacy" disk layout for RomWBW.

 RomWBW has subsequently been enhanced to support the concept of
 partitioning.  The partition mechanism is entirely compliant with Master
- Boot Record (MBR) Partition Tables introduced by IBM for the PC.  The
+Boot Record (MBR) Partition Tables introduced by IBM for the PC.  The
 Wikipedia article on the
 [Master Boot Record](https://en.wikipedia.org/wiki/Master_boot_record)
 is excellent if you are not familiar with them.  This is considered the
@@ -1400,6 +1403,38 @@ Directory Entries".  In this case, the value is 1024 which implies that
 this drive is located on a modern (hd1k) disk layout.  If the value
 was 512, it would indicate a legacy (hd512) disk layout.

+## Hard Disk Capacity
+
+Although RomWBW can support many CP/M filesystem slices on a single
+hard disk, you are still constrained by the physical capacity of the
+actual hard disk.  In most scenarios, RomWBW does not prevent you
+from attempting to use more slices than will fit on your hard disk
+device.  If you attempt to do so, disk I/O errors will be reported.
+
+The exact number of CP/M filesystem slices that will fit on your 
+specific physical hard disk can be determined as follows:
+
+- For hd512 disk layouts, it is slices * 8,320KB.
+- For hd1k disk layouts, it is 1024KB + (slices * 8192KB).  Since
+  1024KB is exactly 1MB, it is equivalent to say 1MB + (slices * 8MB).
+
+**WARNING**: In this document KB means 1024 bytes and MB means 1048576 
+bytes (frequently expressed as KiB and MiB in modern terminology).
+In general, hard disk capacities use KB to mean 1000 bytes and MB
+to mean 1,000,000 bytes.
+
+As an example, hardware distributors frequently supply a "64MB"
+CF Card with a RomWBW system.  Such a hard disk probably has
+less than 62.5MB of actual space (using the RomWBW definition that
+1MB is 1048576 bytes).  Such a drive will not support 8 slices.  It
+will support 7 slices just fine because 7 * 8,320KB = 58.24MB (hd512)
+or 1024KB + (7 * 8192MB) = 57MB (hd1k).
+
+The cost of high capacity CF and SD Cards has become very reasonable.
+I highly recommend upgrading to 1GB or greater media.  This size will
+support all features of the RomWBW Combo Disk Image with 64 slices
+and a 384MB FAT filesystem (see [Combo Hard Disk Image]).
+
 # Disk Content Preparation

 With some understanding of how RomWBW presents disk space to the
@@ -1507,20 +1542,20 @@ command prompt.

 ### Hard Disk Images

-Keeping in mind that a RomWBW hard disk (including CF /SD Cards)
+Keeping in mind that a RomWBW hard disk (including CF/SD Cards)
 allows you to have multiple slices (CP/M filesystems), there are a
 couple ways to image hard disk media.  The easiest approach is to 
 use the "combo" disk image.  This image is already prepared
 with 6 slices containing 5 ready-to-run OSes and a slice with
-the WordStar application.  Alternatively, you can create your own
+the WordStar application files.  Alternatively, you can create your own
 hard disk image with the specific slice contents you choose.

 #### Combo Hard Disk Image

 The combo disk image is essentially just a single image that has several
-of the individual filesystem images already concatenated together. The 
-combo disk image contains the following 6 slices in the positions 
-indicated:
+ of the individual filesystem images (slices) already concatenated 
+together. The combo disk image contains the following 6 slices in the 
+positions indicated:

 | **Slice** | **Description**                                                  |
 |-----------|------------------------------------------------------------------|
@@ -1534,7 +1569,50 @@ indicated:
 You will notice that there are actually 2 combo disk images in the 
 distribution.  One for an hd512 disk layout (hd512_combo.img) and one 
 for an hd1k disk layout (hd1k_combo.img). Simply use the image file that
-corresponds to your desired hard disk layout.
+corresponds to your desired hard disk layout.  Review the information
+in [Hard Disk Layouts] if you need more information of the disk layout
+options.
+
+Although the combo disk images contain only 6 slices of content, they
+reserve space to store 64 CP/M filesystem slices as well as a
+single 384MB FAT filesystem.  Keep in mind that the slices beyond the
+first 6 are not yet initialized.  You will need to use the `CLRDIR`
+application to initialize them before their first use.  Likewise, the
+pre-allocated FAT partition must still be formatted using `FAT FORMAT`
+in order to actually use it (see [FAT Filesystem Preparation]).
+Alternatively, the FAT partition can be formatted on a modern computer.
+
+The combo disk image layout was designed to fit well on a 1GB hard disk.
+The 64 CP/M slices (approximately 512MB) and 384MB FAT filesystem all 
+fit well within a 1GB hard disk.  This size choice was a bit arbitrary, 
+but based on the idea that a 1GB CF or SD Card is easy and cheap to 
+acquire.  It is fine if your hard disk is smaller than 1GB.  It just 
+means that it will not be possible to use the pre-allocated FAT 
+filesystem partition and any CP/M filesystem slices that don't fit.  You
+will get I/O errors if you attempt to access an area beyond the end of
+the physical hard disk.
+
+**WARNING**:Your hard disk may be too small to contain the full 64
+CP/M filesystem slices.  The true number of CP/M filesystem slices that
+will fit on your specific physical hard disk can be calculated as
+described in [Hard Disk Capacity].
+
+For RomWBW systems with a single hard disk (typical), you will notice 
+that the OS will pre-allocate 8 drive letters to the hard disk.  If the 
+combo disk image is being used, only the first 6 drive letters 
+(typically C: - H:) will have any content because the combo disk image 
+only provides 6 slices. The subsequent drives (typically I: - J:) will 
+have no content and will not be pre-initialized.  If you want to use any
+slices beyond the first 6 on the hard disk, then you must initialize 
+them using `CLRDIR` first.
+
+A great way to maintain your own data on a hard disk is to put this
+data in slices beyond the first 6.  By doing so, you can always
+"reimage" your drive with the combo image without overlaying the data
+stored in the slices beyond the first 6.  Just be very careful to use
+the same combo image layout (hd512 or hd1k) as you used originally.
+Also remember to calculate the maximum number of slices your hard disk
+will support and do not exceed this number.

 #### Custom Hard Disk Image

@@ -2143,10 +2221,36 @@ regarding the RomWBW adaptation and customizations.

 #### Boot Disk

-There is no RomWBW-specific boot disk creation procedure.  QP/M
-comes with a QINSTALL which is used to install QPM over an existing
-CP/M 2 installation or to update an existing QPM disk.  `QINSTALL.COM`
-is included with the RomWBW distribution.
+
+To create or update a bootable QP/M Z-System disk, a special process
+is required.  QP/M is not provided in source format.  You are expected
+to install QP/M over an existing CP/M installation using the
+`QINSTALL.COM` application.
+
+To update an existing QP/M boot disk with the latest RomWBW CBIOS, you
+must use 2 steps: apply the generic CP/M system track, then reinstall
+the QP/M components.  To do this, you can perform the following steps:
+
+1. Boot to the existing QP/M disk.  At this point, drive A should be
+   the QP/M disk that you wish to update.  You may receive a warning
+   about CBIOS/HBIOS version mismatch.
+
+1. Use RomWBW `SYSCOPY` to place the stock RomWBW CP/M OS image
+   onto the system tracks of the QP/M boot disk:
+   
+   `SYSCOPY A:=x:CPM.SYS`
+   
+   where x is the drive letter of your ROM Disk.
+
+1. Run `QINSTALL` to overlay the QP/M OS components on your
+   QP/M boot disk.
+
+**WARNING**: `QINSTALL` has no mechanism for retaining previous
+non-default settings.  Any previous non-default settings you
+previously made with `QINSTALL` will need to be reapplied.  The
+pre-built RomWBW QP/M disk image includes a couple of specific
+non-default settings to optimize use with RomWBW.  Please review the
+notes in the ReadMe.txt file in Source/Images/d_qpm.

 #### Notes

@@ -2154,6 +2258,9 @@ is included with the RomWBW distribution.
  on the QPM binary distribution and has been minimally customized
  for RomWBW.

+- When booted, the QPM startup banner will indicate CP/M 2.2.  This
+  is because QPM uses the CP/M 2.2 CBIOS code.
+
 - QINSTALL is used to customize QPM.  It is included on the
  disk image.  You should review the notes in the ReadMe.txt
  file in Source/Images/d_qpm before making changes.
@@ -2308,26 +2415,35 @@ This application understands both FAT filesystems as well as CP/M filesystems.
 * Long filenames are not supported.  Files with long filenames will
  show up with their names truncated into the older 8.3 convention.
 * A FAT filesystem can be located on floppy or hard disk media.  For
-  hard disk media, the FAT filesystem must be located within a valid
-  FAT partition.
+  hard disk media, a valid FAT Filesystem partition must exist.
+* Note that CP/M (and compatible) OSes do not support all of the
+  filename characters that a modern computer does.  The following
+  characters are **not permitted** in a CP/M filename:
+
+  `< > . , ; : = ? * [ ] _ % | ( ) / \`
  
+  The FAT application does not auto-rename files when it encounters
+  invalid filenames.  It will just issue an error and quit.
+  Additionally, the error message is not very clear about the problem.
+
 ## FAT Filesystem Preparation

 In general, you can create media formatted with a FAT filesystem on
 your RomWBW computer or on your modern computer.  We will only be
 discussing the RomWBW-based approach here.

-In the case of a floppy disk, you can use the `FAT` application to
-format the floppy disk.  For example, if your floppy disk is on RomWBW
-disk unit 2, you could use `FAT FORMAT 2:`.  This will overwrite the
-floppy with a FAT filesystem and all previous contents will be lost.
-Once formatted this way, the floppy disk can be used in a floppy drive
-attached to a modern computer or it can be used on RomWBW using the
+In the case of a floppy disk, you can use the `FAT` application to 
+format the floppy disk.  The floppy disk must already be physically 
+formatted using RomWBW FDU or equivalent.  If your floppy disk is on 
+RomWBW disk unit 2, you could use `FAT FORMAT 2:`.  This will overwrite 
+the floppy with a FAT filesystem and all previous contents will be lost.
+Once formatted this way, the floppy disk can be used in a floppy drive 
+attached to a modern computer or it can be used on RomWBW using the 
 other `FAT` tool commands.

 In the case of hard disk media, it is necessary to have a FAT
 partition.  If you prepared your RomWBW hard disk media using the
-disk image process, then this partition will already be present and
+disk image process, then this partition will already be defined and
 you do not need to recreate it.  This default FAT partition is located
 at approximately 512MB from the start of your disk and it is 384MB in
 size.  So, your hard disk media must be 1GB or greater to use this
@@ -2375,8 +2491,13 @@ If your RomWBW system has multiple disk drives/slots, you can also just
 create a disk with your modern computer that is a dedicated FAT 
 filesystem disk.  You can use your modern computer to format the disk 
 (floppy, CF Card, SD Card, etc.), then insert the disk in your RomWBW 
-computer and access if using `FAT` based on its RomWBW unit number.
+computer and access it using `FAT` based on its RomWBW unit number.

+**WARNING**: Microsoft Windows will sometimes suggest reformatting
+partitions that it does not recognize.  If you are prompted to format
+a partition of your SD/CF Card when inserting the card into a Windows
+computer, you probably want to select Cancel.
+  
 ## FAT Application Usage

 Complete instructions for the `FAT` application are found in $doc_apps$.
@@ -3777,6 +3898,31 @@ the RomWBW HBIOS configuration.

 `\clearpage`{=latex}

+### Small Computer SC700 Z180 CPU Module
+
+|                   |                  |
+|-------------------|------------------|
+| ROM Image Files   | SCZ180_sc700.rom |
+| Console Baud Rate | 115200           |
+| Interrupts        | Mode 2           |
+
+ - CPU speed is detected at startup if DS1302 RTC is active
+   - Otherwise 18.432 MHz assumed
+ - System timer is generated by Z180 CPU
+ - Hardware auto-detected:
+   - DS1302 RTC
+   - Z180 ASCI Serial Ports
+   - SIO Serial Interface Module
+   - EP Dual UART Serial Interface Module
+   - WDC Floppy Disk Controller w/ 3.5" HD Drives
+   - IDE Hard Disk Interface Module
+   - PPIDE Hard Disk Interface Module
+   - Onboard SD Card Interface
+ - Use of Interrupt Mode 2 requires proper IEI/IEO configuration
+   for all peripherals generating interrupts
+
+`\clearpage`{=latex}
+
 ### Dyno Z180 SBC

 |                   |                |
@@ -3953,26 +4099,38 @@ the RomWBW HBIOS configuration.
 |-------------------|---------------|
 | ROM Image File    | DUO_std.rom   |
 | Console Baud Rate | 38400         |
-| Interrupts        | None          |
+| Interrupts        | Mode 2        |

 - CPU speed is detected at startup if DS1302 RTC is active
   - Otherwise 8.000 MHz assumed
 - System timer is generated by CTC if available
 - Hardware auto-detected:
   - DS1302 RTC
-   - Zilog CTC
   - Zilog DMA Module
   - UART Serial Adapter
-   - SIO Serial Interface
-   - LPT Printer Interface
-   - Zilog Parallel Interface
-   - CVDU Display Adapter
-   - TMS9938/58 Display Adapter
-   - PS/2 Keyboard Interface
-   - AY-3-8910/YM2149 Sound Module
-   - Floppy Disk Controller w/ 3.5" HD Drives
-   - PPIDE Hard Disk Interface
- - Interrupts may be enabled in build options
+
+`\clearpage`{=latex}
+
+### Heath H8 Z80 System
+
+|                   |               |
+|-------------------|---------------|
+| ROM Image File    | HEATH_std.rom |
+| Console Baud Rate | 115200        |
+| Interrupts        | Mode 1        |
+
+ - CPU speed is detected at startup if DS1302 RTC is active
+   - Otherwise 7.3728 MHz assumed
+ - Hardware auto-detected:
+   - DS1302 RTC
+   - ACIA Serial Interface Module
+   - SIO Serial Interface Module
+   - EP Dual UART Serial Interface Module
+   - WDC Floppy Disk Controller w/ 3.5" HD Drives
+   - IDE Hard Disk Interface Module
+   - PPIDE Hard Disk Interface Module
+ - Serial baud rate is usually determined by hardware for ACIA and
+   SIO interfaces

 `\clearpage`{=latex}

@@ -3998,7 +4156,7 @@ may be discovered by RomWBW in your system.
 | FD        | Disk     | 8272 or compatible Floppy Disk Controller              |
 | GDC       | Video    | uPD7220 Video Display Controller                       |
 | HDSK      | Disk     | SIMH Simulator Hard Disk                               |
-| IDE       | Disk     | IDE/ATA Hard Disk Interface                            |
+| IDE       | Disk     | IDE/ATA/ATAPI Hard Disk Interface                      |
 | ICM       | DsKy     | ICM7218-based Display/Keypad on PPI                    |
 | IMM       | Disk     | IMM Zip Drive on PPI                                   |
 | INTRTC    | RTC      | Interrupt-based Real Time Clock                        |
@@ -4010,7 +4168,7 @@ may be discovered by RomWBW in your system.
 | I2C       | System   | I2C Interface                                          |
 | PIO       | Char     | Zilog Parallel Interface Controller                    |
 | PKD       | DsKy     | P8279-based Display/Keypad on PPI                      |
-| PPIDE     | Disk     | 8255 IDE/ATA Hard Disk Interface                       |
+| PPIDE     | Disk     | 8255 IDE/ATA/ATAPI Hard Disk Interface                 |
 | PPA       | Disk     | PPA Zip Drive on PPI                                   |
 | PPK       | Kbd      | Matrix Keyboard                                        |
 | PPPSD     | Disk     | ParPortProp SD Card Interface                          |
--- a/Source/HBIOS/Bank
+++ b/Source/HBIOS/Bank
@@ -0,0 +1,74 @@
+ROM Bank Layout
+
+Bank ID		Module		Start	Size
+------		------		------	------
+0x00		hbios		0x0000	0x8000
+		<end>		0x8000
+
+0x01		loader		0x0000	0x1000
+		dbgmon		0x1000	0x2000
+		cpm22		0x2000	0x3000
+		zsys		0x5000	0x3000
+		<end>		0x8000
+
+0x02		forth		0x0000	0x1700
+		basic		0x1700	0x2000
+		tbasic		0x3700	0x0900
+		game		0x4000	0x0900
+		egg		0x4900	0x0200
+		netboot         0x4B00	0x1000
+		updater         0x5B00	0x0D00
+		usrrom		0x6800	0x1800
+		<end>		0x8000
+
+0x03		imgpad2		0x0000	0x8000
+		<end>		0x8000
+
+0x04 - N	ROM Disk Data
+
+
+RAM Bank Layout
+
+Bank ID         Usage
+-------         ------
+0x80            RomWBW HBIOS
+0x81-0x8B       RAM Disk Data
+0x8C		CP/M 3 Buffers
+0x8D            CP/M 3 OS
+0x8E            User TPA
+0x8F            Common
+
+
+ROMless Bank Layout
+
+Bank ID         Usage
+-------         ------
+0x80            RomWBW HBIOS
+0x81		Loader, DbgMon, CP/M 2.2, ZSDOS
+0x82		ROM Apps
+0x83		More ROM Apps
+0x84-0x8B       RAM Disk Data
+0x8C		CP/M 3 Buffers
+0x8D            CP/M 3 OS
+0x8E            User TPA
+0x8F            Common
+
+
+ROMless Tiny Bank Layout (128K)
+NOTE: no ROM Apps, no CP/M 3 support, no RAM disk
+
+Bank ID         Usage
+-------         ------
+0x80            RomWBW HBIOS
+0x81		Loader, DbgMon, CP/M 2.2, ZSDOS
+0x82            User TPA
+0x83            Common
+
+Disk Image Sizes
+
+Image Size	ROM System	ROMless System
+----------	----------	--------------
+1024K		896K		768K
+512		384K		256K
+256		128K		0K
+128 (tiny)	n/a		0K
--- a/Source/HBIOS/Build.cmd
+++ b/Source/HBIOS/Build.cmd
@@ -110,10 +110,8 @@ copy /b romldr.bin + dbgmon.bin + ..\zsdos\zsys_wbw.bin osimg_small.bin || exit
 :: should yield a result of zero.
 ::

-if %ROMSize% gtr 0 (
-    for %%f in (hbios_rom.bin osimg.bin osimg1.bin osimg2.bin) do (
-      "%TOOLS%\srecord\srec_cat.exe" %%f -Binary -Crop 0 0x7FFF -Checksum_Negative_Big_Endian 0x7FFF 1 1 -o %%f -Binary || exit /b
-    )
+for %%f in (hbios_rom.bin osimg.bin osimg1.bin osimg2.bin) do (
+  "%TOOLS%\srecord\srec_cat.exe" %%f -Binary -Crop 0 0x7FFF -Checksum_Negative_Big_Endian 0x7FFF 1 1 -o %%f -Binary || exit /b
 )

 ::
@@ -137,8 +135,8 @@ if %ROMSize% gtr 0 (
    copy /b hbios_rom.bin + osimg.bin + osimg1.bin + osimg2.bin %ROMName%.upd || exit /b
    copy /b hbios_app.bin + osimg_small.bin %ROMName%.com || exit /b
 ) else (
-    copy /b hbios_rom.bin + osimg_small.bin %ROMName%.rom || exit /b
-    copy /b hbios_rom.bin + osimg_small.bin %ROMName%.upd || exit /b
+    copy /b hbios_rom.bin + osimg.bin + osimg1.bin + osimg2.bin  + ..\RomDsk\ram%ROMSize%_wbw.dat %ROMName%.rom || exit /b
+    copy /b hbios_rom.bin + osimg.bin + osimg1.bin + osimg2.bin %ROMName%.upd || exit /b
    copy /b hbios_app.bin + osimg_small.bin %ROMName%.com || exit /b
 )

@@ -222,16 +220,19 @@ call Build RCZ280 ext || exit /b
 call Build RCZ280 nat || exit /b
 call Build RCZ280 zz80mb || exit /b
 call Build RCZ280 zzrc || exit /b
+call Build RCZ280 zzrc_ram || exit /b
 call Build SCZ180 sc126 || exit /b
 call Build SCZ180 sc130 || exit /b
 call Build SCZ180 sc131 || exit /b
 call Build SCZ180 sc140 || exit /b
 call Build SCZ180 sc503 || exit /b
+call Build SCZ180 sc700 || exit /b
 call Build DYNO std || exit /b
 call Build UNA std || exit /b
 call Build RPH std || exit /b
 call Build Z80RETRO std || exit /b
 call Build S100 std || exit /b
 call Build DUO std || exit /b
+call Build HEATH std || exit /b

 goto :eof
--- a/Source/HBIOS/Build.ps1
+++ b/Source/HBIOS/Build.ps1
@@ -27,7 +27,7 @@ $ErrorAction = 'Stop'
 # UNA BIOS is simply imbedded, it is not built here.
 #

-$PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "Z80RETRO", "DUO", "UNA"
+$PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "Z80RETRO", "DUO", "UNA", "HEATH"
 $PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO", "RPH", "S100"
 $PlatformListZ280 = "RCZ280"

--- a/Source/HBIOS/Build.sh
+++ b/Source/HBIOS/Build.sh
@@ -19,6 +19,7 @@ if [ "${ROM_PLATFORM}" == "dist" ] ; then
 	ROM_PLATFORM="RCZ280"; ROM_CONFIG="nat"; bash Build.sh
 	ROM_PLATFORM="RCZ280"; ROM_CONFIG="zz80mb"; bash Build.sh
 	ROM_PLATFORM="RCZ280"; ROM_CONFIG="zzrc"; bash Build.sh
+	ROM_PLATFORM="RCZ280"; ROM_CONFIG="zzrc_ram"; bash Build.sh
 #	ROM_PLATFORM="RCZ80"; ROM_CONFIG="mt"; bash Build.sh
 #	ROM_PLATFORM="RCZ80"; ROM_CONFIG="duart"; bash Build.sh
 	ROM_PLATFORM="RCZ80"; ROM_CONFIG="std"; bash Build.sh
@@ -38,11 +39,13 @@ if [ "${ROM_PLATFORM}" == "dist" ] ; then
 	ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc131"; bash Build.sh
 	ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc140"; bash Build.sh
 	ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc503"; bash Build.sh
+	ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc700"; bash Build.sh
 	ROM_PLATFORM="S100"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="UNA"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="Z80RETRO"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="ZETA"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="ZETA2"; ROM_CONFIG="std"; bash Build.sh
+	ROM_PLATFORM="HEATH"; ROM_CONFIG="std"; bash Build.sh
 	exit
 fi

--- a/Source/HBIOS/Config/DUO_std.asm
+++ b/Source/HBIOS/Config/DUO_std.asm
@@ -29,30 +29,20 @@
 CPUOSC		.SET	8000000		; CPU OSC FREQ IN MHZ
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
-INTMODE		.SET	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 ;
-DMAENABLE	.SET	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+;;;DMAENABLE	.SET	TRUE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 ;
-BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
-;
-CPUSPDDEF	.SET	SPD_LOW		; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+BATCOND		.SET	TRUE		; ENABLE LOW BATTERY WARNING MESSAGE
 ;
 ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
 RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ;
-MDFFENABLE	.SET	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+PCFENABLE	.SET	TRUE		; ENABLE PCF8584 I2C CONTROLLER
 ;
-DSKYENABLE	.SET	TRUE		; ENABLES DSKY FUNCTIONALITY
-ICMENABLE	.SET	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
-PKDENABLE	.SET	TRUE		; ENABLES DSKY NG PKD DRIVER (8259)
+MDFFENABLE	.SET	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
 UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 ;UARTCFG	.SET	UARTCFG | SER_RTS
 ;
-LPTENABLE	.SET	TRUE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
-;
-CVDUMON		.SET	CVDUMON_CGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
-;
-FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-;
-PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+ESPENABLE	.SET	TRUE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
--- a/Source/HBIOS/Config/HEATH_std.asm
+++ b/Source/HBIOS/Config/HEATH_std.asm
@@ -0,0 +1,69 @@
+;
+;==================================================================================================
+;   HEATH H8 Z80 STANDARD CONFIGURATION
+;==================================================================================================
+;
+; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
+; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
+; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
+; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
+; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
+; YOUR FILE IN THE BUILD PROCESS.
+;
+; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
+; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
+; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
+; SETTINGS.
+;
+; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
+; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
+; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
+; DIRECTORIES ABOVE THIS ONE).
+;
+#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
+;
+#include "cfg_rcz80.asm"
+;
+CPUOSC		.SET	7372800		; CPU OSC FREQ IN MHZ
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+;
+DSKYENABLE	.SET	TRUE		; ENABLES DSKY FUNCTIONALITY
+H8PENABLE	.SET	TRUE		; ENABLES HEATH H8 FRONT PANEL
+;
+FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+;
+DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
+UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+ACIAENABLE	.SET	TRUE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+;
+LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+;
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
+MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+;
+AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
+AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+;
+FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
+;
+IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.SET	SDMODE_PIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|USR]
+SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY
+IMMENABLE	.SET	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+;
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
--- a/Source/HBIOS/Config/MBC_std.asm
+++ b/Source/HBIOS/Config/MBC_std.asm
@@ -49,6 +49,8 @@ PKDENABLE	.SET	TRUE		; ENABLES DSKY NG PKD DRIVER (8259)
 UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 ;UARTCFG	.SET	UARTCFG | SER_RTS
 ;
+ESPENABLE	.SET	TRUE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 LPTENABLE	.SET	TRUE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
 ;
 CVDUMON		.SET	CVDUMON_CGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
--- a/Source/HBIOS/Config/MK4_std.asm
+++ b/Source/HBIOS/Config/MK4_std.asm
@@ -47,7 +47,7 @@ VGAENABLE	.SET	TRUE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_DIDE	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_DIDE	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
--- a/Source/HBIOS/Config/RCZ180_ext.asm
+++ b/Source/HBIOS/Config/RCZ180_ext.asm
@@ -58,7 +58,7 @@ AYMODE		.SET	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LI
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
--- a/Source/HBIOS/Config/RCZ180_nat.asm
+++ b/Source/HBIOS/Config/RCZ180_nat.asm
@@ -57,7 +57,7 @@ AYMODE		.SET	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LI
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
--- a/Source/HBIOS/Config/RCZ280_ext.asm
+++ b/Source/HBIOS/Config/RCZ280_ext.asm
@@ -56,7 +56,7 @@ AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LIN
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
--- a/Source/HBIOS/Config/RCZ280_nat.asm
+++ b/Source/HBIOS/Config/RCZ280_nat.asm
@@ -56,7 +56,7 @@ AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LIN
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
--- a/Source/HBIOS/Config/RCZ280_zz80mb.asm
+++ b/Source/HBIOS/Config/RCZ280_zz80mb.asm
@@ -28,7 +28,7 @@
 ;
 #include "cfg_rcz280.asm"
 ;
-CPUOSC		.SET	12000000	; CPU OSC FREQ IN MHZ
+CPUOSC		.SET	24000000	; CPU OSC FREQ IN MHZ
 INTMODE		.SET	3		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
@@ -37,8 +37,7 @@ FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
 ;
 MEMMGR		.SET	MM_Z280		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 ;
-RAMLOC		.SET	23		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
-RAMBIAS		.SET	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMBIAS		.SET	8192		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 ;
 Z280_MEMLOWAIT	.SET	0		; Z280: LOW 8MB MEMORY WAIT STATES (0-3)
 Z280_MEMHIWAIT	.SET	0		; Z280: HIGH 8MB MEMORY WAIT STATES (0-3)
@@ -62,7 +61,7 @@ AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LIN
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
--- a/Source/HBIOS/Config/RCZ280_zzrc.asm
+++ b/Source/HBIOS/Config/RCZ280_zzrc.asm
@@ -39,10 +39,7 @@ MEMMGR		.SET	MM_Z280		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 ;
 RAMSIZE		.SET	256		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.SET	256		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE_CHK	.SET	256		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
-;
-RAMLOC		.SET	18		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
-RAMBIAS		.SET	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMBIAS		.SET	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 ;
 Z280_MEMLOWAIT	.SET	0		; Z280: LOW 8MB MEMORY WAIT STATES (0-3)
 Z280_MEMHIWAIT	.SET	0		; Z280: HIGH 8MB MEMORY WAIT STATES (0-3)
@@ -70,7 +67,7 @@ AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LIN
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
--- a/Source/HBIOS/Config/RCZ280_zzrc_ram.asm
+++ b/Source/HBIOS/Config/RCZ280_zzrc_ram.asm
@@ -0,0 +1,77 @@
+;
+;==================================================================================================
+;   RCBUS Z280 STANDARD CONFIGURATION (NATIVE Z280 MMU W/ LINEAR MEMORY ON ZZRC)
+;==================================================================================================
+;
+; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
+; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
+; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
+; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
+; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
+; YOUR FILE IN THE BUILD PROCESS.
+;
+; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
+; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
+; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
+; SETTINGS.
+;
+; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
+; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
+; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
+; DIRECTORIES ABOVE THIS ONE).
+;
+#DEFINE PLATFORM_NAME "ZZRC", " [", CONFIG, "]"
+;
+#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
+;
+#include "cfg_rcz280.asm"
+;
+CPUOSC		.SET	14745600	; CPU OSC FREQ IN MHZ
+INTMODE		.SET	3		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+;
+FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+;
+MEMMGR		.SET	MM_Z280		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
+;
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.SET	0		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+RAMBIAS		.SET	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+;
+Z280_MEMLOWAIT	.SET	0		; Z280: LOW 8MB MEMORY WAIT STATES (0-3)
+Z280_MEMHIWAIT	.SET	0		; Z280: HIGH 8MB MEMORY WAIT STATES (0-3)
+Z280_IOWAIT	.SET	1		; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+Z280_INTWAIT	.SET	0		; Z280: INT ACK WAIT STATUS (0-3)
+;
+MDROM		.SET	FALSE		; MD: ENABLE ROM DISK
+MDRAM		.SET	TRUE		; MD: ENABLE RAM DISK
+;
+Z2UENABLE	.SET	TRUE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+Z2UOSC		.SET	(CPUOSC / 8)	; Z2U: OSC FREQUENCY IN MHZ
+Z2U0HFC		.SET	TRUE		; Z2U0: ENABLE HARDWARE FLOW CONTROL
+UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+;
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
+MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+VRCENABLE	.SET	TRUE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+;
+AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
+AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+;
+FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
+;
+IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY
+;
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
--- a/Source/HBIOS/Config/RCZ80_easy.asm
+++ b/Source/HBIOS/Config/RCZ80_easy.asm
@@ -41,6 +41,7 @@ WDOGIO		.SET	$6F		; WATCHDOG REGISTER ADR
 ;
 DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+INTRTCENABLE	.SET	TRUE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
 CTCENABLE	.SET	TRUE		; ENABLE ZILOG CTC SUPPORT
 CTCTIMER	.SET	TRUE		; ENABLE CTC PERIODIC TIMER
@@ -69,7 +70,7 @@ AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LIN
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
--- a/Source/HBIOS/Config/RCZ80_jbl.asm
+++ b/Source/HBIOS/Config/RCZ80_jbl.asm
@@ -69,7 +69,7 @@ AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LIN
 SN76489ENABLE	.SET	TRUE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
--- a/Source/HBIOS/Config/RCZ80_kio.asm
+++ b/Source/HBIOS/Config/RCZ80_kio.asm
@@ -66,7 +66,7 @@ AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LIN
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
--- a/Source/HBIOS/Config/RCZ80_skz.asm
+++ b/Source/HBIOS/Config/RCZ80_skz.asm
@@ -61,7 +61,7 @@ AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LIN
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
--- a/Source/HBIOS/Config/RCZ80_std.asm
+++ b/Source/HBIOS/Config/RCZ80_std.asm
@@ -54,7 +54,7 @@ AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LIN
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
--- a/Source/HBIOS/Config/RCZ80_tiny.asm
+++ b/Source/HBIOS/Config/RCZ80_tiny.asm
@@ -75,7 +75,7 @@ AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LIN
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 IDE0BASE	.SET	$90		; IDE 0: IO BASE ADDRESS
--- a/Source/HBIOS/Config/RCZ80_zrc.asm
+++ b/Source/HBIOS/Config/RCZ80_zrc.asm
@@ -53,7 +53,7 @@ AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LIN
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
--- a/Source/HBIOS/Config/RCZ80_zrc_ram.asm
+++ b/Source/HBIOS/Config/RCZ80_zrc_ram.asm
@@ -34,7 +34,7 @@ CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
 FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
 ;
-RAMSIZE		.SET	2048		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.SET	0		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
 MEMMGR		.SET	MM_ZRC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
 ;
@@ -57,7 +57,7 @@ AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LIN
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
--- a/Source/HBIOS/Config/S100_std.asm
+++ b/Source/HBIOS/Config/S100_std.asm
@@ -27,20 +27,17 @@
 #include "cfg_s100.asm"
 ;
 CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
+CRTACT		.SET	TRUE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
 Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
-Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
-Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+Z180_MEMWAIT	.SET	1		; Z180: MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.SET	2		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 ;
 DSRTCENABLE	.SET	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 INTRTCENABLE	.SET	TRUE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
-UARTENABLE	.SET	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 ASCIENABLE	.SET	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
-ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
-SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
-;
-ASCI0CFG	.SET	SER_57600_8N1	; ASCI 1: SERIAL LINE CONFIG
+SCONENABLE	.SET	TRUE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 ;
 IDEENABLE	.SET	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
--- a/Source/HBIOS/Config/SBC_std.asm
+++ b/Source/HBIOS/Config/SBC_std.asm
@@ -45,7 +45,7 @@ VGAENABLE	.SET	TRUE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_DIO3	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_DIO3	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
--- a/Source/HBIOS/Config/SCZ180_sc126.asm
+++ b/Source/HBIOS/Config/SCZ180_sc126.asm
@@ -59,7 +59,7 @@ AYMODE		.SET	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LI
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
--- a/Source/HBIOS/Config/SCZ180_sc130.asm
+++ b/Source/HBIOS/Config/SCZ180_sc130.asm
@@ -60,7 +60,7 @@ AYMODE		.SET	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LI
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
--- a/Source/HBIOS/Config/SCZ180_sc140.asm
+++ b/Source/HBIOS/Config/SCZ180_sc140.asm
@@ -54,7 +54,7 @@ AYMODE		.SET	AYMODE_LINC	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
--- a/Source/HBIOS/Config/SCZ180_sc503.asm
+++ b/Source/HBIOS/Config/SCZ180_sc503.asm
@@ -54,7 +54,7 @@ AYMODE		.SET	AYMODE_LINC	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
--- a/Source/HBIOS/Config/SCZ180_sc700.asm
+++ b/Source/HBIOS/Config/SCZ180_sc700.asm
@@ -0,0 +1,71 @@
+;
+;==================================================================================================
+;   SC700 STANDARD CONFIGURATION
+;==================================================================================================
+;
+; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
+; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
+; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
+; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
+; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
+; YOUR FILE IN THE BUILD PROCESS.
+;
+; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
+; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
+; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
+; SETTINGS.
+;
+; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
+; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
+; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
+; DIRECTORIES ABOVE THIS ONE).
+;
+#DEFINE PLATFORM_NAME "Small Computer SC700", " [", CONFIG, "]"
+;
+#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
+;
+#include "cfg_scz180.asm"
+;
+CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+;
+Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
+Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+;
+LEDENABLE	.SET	TRUE		; ENABLE STATUS LED (SINGLE LED)
+LEDPORT		.SET	$0E		; STATUS LED PORT ADDRESS
+;
+FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.SET	$00		; FP: PORT ADDRESS FOR FP LEDS
+;
+DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+INTRTCENABLE	.SET	TRUE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+;
+UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+ASCIENABLE	.SET	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+;
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
+MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+;
+AY38910ENABLE	.SET	TRUE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
+AYMODE		.SET	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+;
+FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+;
+IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+SDENABLE	.SET	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.SET	SDMODE_SC	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
+;
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
--- a/Source/HBIOS/Config/ZETA2_std.asm
+++ b/Source/HBIOS/Config/ZETA2_std.asm
@@ -35,7 +35,7 @@ UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 UARTSBC		.SET	TRUE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_ZETA2	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_ZETA2	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
 SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
--- a/Source/HBIOS/Config/ZETA_std.asm
+++ b/Source/HBIOS/Config/ZETA_std.asm
@@ -35,7 +35,7 @@ UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 UARTSBC		.SET	TRUE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_ZETA	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_ZETA	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
 SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
--- a/Source/HBIOS/Makefile
+++ b/Source/HBIOS/Makefile
@@ -67,11 +67,9 @@ $(OBJECTS) : $(ROMDEPS)
 		else \
 			cat imgpad2.bin >osimg2.bin ; \
 		fi ; \
-		if [ $(ROMSIZE) -gt 0 ] ; then \
-			for f in hbios_rom.bin osimg.bin osimg1.bin osimg2.bin ; do \
-				srec_cat $$f -Binary -Crop 0 0x7FFF -Checksum_Negative_Big_Endian 0x7FFF 1 1 -o $$f -Binary ; \
-			done \
-		fi \
+		for f in hbios_rom.bin osimg.bin osimg1.bin osimg2.bin ; do \
+			srec_cat $$f -Binary -Crop 0 0x7FFF -Checksum_Negative_Big_Endian 0x7FFF 1 1 -o $$f -Binary ; \
+		done \
 	fi
 	if [ $(ROM_PLATFORM) = UNA ] ; then \
 		cp osimg.bin $(DEST)/UNA_WBW_SYS.bin ; \
@@ -83,8 +81,8 @@ $(OBJECTS) : $(ROMDEPS)
 			cat hbios_rom.bin osimg.bin osimg1.bin osimg2.bin >$(ROMNAME).upd ; \
 			cat hbios_app.bin osimg_small.bin > $(ROMNAME).com ; \
 		else \
-			cat hbios_rom.bin osimg_small.bin > $(ROMNAME).rom ; \
-			cat hbios_rom.bin osimg_small.bin > $(ROMNAME).upd ; \
+			cat hbios_rom.bin osimg.bin osimg1.bin osimg2.bin >$(ROMNAME).rom ; \
+			cat hbios_rom.bin osimg.bin osimg1.bin osimg2.bin >$(ROMNAME).upd ; \
 			cat hbios_app.bin osimg_small.bin > $(ROMNAME).com ; \
 		fi \
 	fi
--- a/Source/HBIOS/ROM
+++ b/Source/HBIOS/ROM
@@ -1,27 +0,0 @@
-RomWBW ROM Layout Notes
-
-Bank		Module		Start	Size
------		------		------	------		
-0		hbios		0x0000	0x8000
-		<end>		0x8000
-
-1		loader		0x0000	0x1000
-		dbgmon		0x1000	0x2000
-		cpm22		0x2000	0x3000
-		zsys		0x5000	0x3000
-		<end>		0x8000        
-
-2		forth		0x0000	0x1700
-		basic		0x1700	0x2000
-		tbasic		0x3700	0x0900
-		game		0x4000	0x0900
-		egg		0x4900	0x0200
-		netboot         0x4B00	0x1000
-		updater         0x5B00	0x0D00
-		usrrom		0x6800	0x1800
-		<end>		0x8000
-
-3		imgpad2		0x0000	0x8000
-		<end>		0x8000
-
-4-N		ROM Disk Data
--- a/Source/HBIOS/cfg_duo.asm
+++ b/Source/HBIOS/cfg_duo.asm
@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW 2.X CONFIGURATION DEFAULTS FOR DUODYNE
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR DUODYNE
 ;==================================================================================================
 ;
 ; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_DUO		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
+PLATFORM	.EQU	PLT_DUO		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -26,28 +26,27 @@ TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
 BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
 BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
 ;
-CPUSPDCAP	.EQU	SPD_HILO	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
-CPUSPDDEF	.EQU	SPD_LOW		; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.EQU	SPD_UNSUP	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	8000000		; CPU OSC FREQ IN MHZ
-INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
 MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
-MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
-MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
+MPGSEL_0	.EQU	$50		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_1	.EQU	$51		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_2	.EQU	$52		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_3	.EQU	$53		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
+MPGENA		.EQU	$54		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ;
-RTCIO		.EQU	$70		; RTC LATCH REGISTER ADR
+RTCIO		.EQU	$94		; RTC LATCH REGISTER ADR
 ;
 KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
 KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
 ;
-CTCENABLE	.EQU	TRUE		; ENABLE ZILOG CTC SUPPORT
+CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
 CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$B0		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	TRUE		; ENABLE CTC PERIODIC TIMER
@@ -57,6 +56,9 @@ CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	(4915200/8)	; CTC CLOCK FREQUENCY
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$56		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -65,7 +67,7 @@ WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
 FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
 FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
-FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPLED_DSKACT	.EQU	FALSE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
 FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
 FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
 ;
@@ -83,6 +85,7 @@ ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
 PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
@@ -123,13 +126,13 @@ UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
 UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
-UARTDUAL	.EQU	TRUE		; UART: AUTO-DETECT DUAL UART
+UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
@@ -137,7 +140,7 @@ Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 ;
 ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ;
-SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
@@ -154,16 +157,17 @@ XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 VDUSIZ		.EQU	V80X25		; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
-CVDUENABLE	.EQU	TRUE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 CVDUMODE	.EQU	CVDUMODE_MBC	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
 CVDUMON		.EQU	CVDUMON_CGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
 GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
-TMSENABLE	.EQU	TRUE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
 TMSMODE		.EQU	TMSMODE_MBC	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -225,6 +229,18 @@ SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$BE		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.EQU	$FF		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -232,10 +248,13 @@ PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+ESPCONENABLE	.EQU	TRUE		; ESP: ENABLE ESP32 CONSOLE IO DRIVER VIDEO/KBD SUPPORT
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 HDSKTRACE	.EQU	1		; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 ;
-PIOENABLE	.EQU	TRUE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
 PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
 PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
 PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
@@ -289,10 +308,9 @@ AYMODE		.EQU	AYMODE_MBC	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|
 ;
 SPKENABLE	.EQU	TRUE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
-DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
-DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_MBC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAENABLE	.EQU	TRUE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.EQU	$40		; DMA: DMA BASE ADDRESS
+DMAMODE		.EQU	DMAMODE_DUO	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
-
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
--- a/Source/HBIOS/cfg_dyno.asm
+++ b/Source/HBIOS/cfg_dyno.asm
@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW 2.X CONFIGURATION DEFAULTS FOR DYNO
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR DYNO
 ;==================================================================================================
 ;
 ; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_DYNO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
+PLATFORM	.EQU	PLT_DYNO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,10 +34,8 @@ DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
 MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
-RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
-RAMBIAS		.EQU	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
@@ -60,6 +58,9 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -79,7 +80,14 @@ LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|RTC]
 LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
 LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
-DSKYENABLE	.EQU	FALSE		; ENABLES DSKY (DO NOT COMBINE WITH PPIDE)
+DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
@@ -126,7 +134,7 @@ UARTENABLE	.EQU	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
@@ -176,6 +184,7 @@ TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MS
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -236,6 +245,8 @@ SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -243,6 +254,8 @@ PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
@@ -277,7 +290,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
--- a/Source/HBIOS/cfg_heath.asm
+++ b/Source/HBIOS/cfg_heath.asm
@@ -0,0 +1,321 @@
+;
+;==================================================================================================
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR RCBUS Z80
+;==================================================================================================
+;
+; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
+; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
+; UNDER THIS DIRECTORY.
+;
+; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
+; FOR THE PLATFORM.
+;
+#DEFINE PLATFORM_NAME "RCBus", " [", CONFIG, "]"
+;
+#INCLUDE "hbios.inc"
+;
+PLATFORM	.EQU	PLT_HEATH	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+;
+BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+;
+CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.EQU	7372800		; CPU OSC FREQ IN MHZ
+INTMODE		.EQU	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;
+RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
+MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
+;
+RTCIO		.EQU	$C0		; RTC LATCH REGISTER ADR
+;
+KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+;
+CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
+CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
+CTCMODE		.EQU	CTCMODE_TIM16	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
+CTCPRE		.EQU	256		; PRESCALE CONSTANT (1-256)
+CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
+CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
+CTCOSC		.EQU	CPUOSC		; CTC CLOCK FREQUENCY
+;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
+SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+SKZDIV		.EQU	DIV_1		; UART CLK (CLK2) DIVIDER FOR Z80-512K
+;
+WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+WDOGIO		.EQU	$6E		; WATCHDOG REGISTER ADR
+;
+FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+;
+DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+;
+LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
+LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|RTC]
+LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
+LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+;
+DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+;
+BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYENABLE	.EQU	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+;
+DSRTCENABLE	.EQU	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
+DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+;
+DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+;
+BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+;
+INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+;
+RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
+HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+;
+DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+;
+DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+DUARTCNT	.EQU	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
+DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
+DUART0ACFG	.EQU	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
+DUART0BCFG	.EQU	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
+DUART1BASE	.EQU	$40		; DUART 1: BASE ADDRESS OF CHIP
+DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
+DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
+;
+UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
+UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
+UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
+UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
+UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
+UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+;
+ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+;
+Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+;
+ACIAENABLE	.EQU	TRUE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+ACIADEBUG	.EQU	FALSE		; ACIA: ENABLE DEBUG OUTPUT
+ACIACNT		.EQU	1		; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
+ACIA0BASE	.EQU	$80		; ACIA 0: REGISTERS BASE ADR
+ACIA0CLK	.EQU	CPUOSC		; ACIA 0: OSC FREQ IN HZ
+ACIA0DIV	.EQU	1		; ACIA 0: SERIAL CLOCK DIVIDER
+ACIA0CFG	.EQU	DEFSERCFG	; ACIA 0: SERIAL LINE CONFIG  (SEE STD.ASM)
+ACIA1BASE	.EQU	$40		; ACIA 1: REGISTERS BASE ADR
+ACIA1CLK	.EQU	CPUOSC		; ACIA 1: OSC FREQ IN HZ
+ACIA1DIV	.EQU	1		; ACIA 1: SERIAL CLOCK DIVIDER
+ACIA1CFG	.EQU	DEFSERCFG	; ACIA 1: SERIAL LINE CONFIG  (SEE STD.ASM)
+;
+SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.EQU	CPUOSC		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
+SIO1ACLK	.EQU	CPUOSC		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1ACFG	.EQU	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
+SIO1ACTCC	.EQU	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1BCLK	.EQU	CPUOSC		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1BCFG	.EQU	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
+SIO1BCTCC	.EQU	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+;
+XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+;
+VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
+TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+;
+MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+;
+FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+;
+RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+;
+IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.EQU	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT		.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.EQU	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE0BASE	.EQU	$10		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.EQU	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.EQU	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.EQU	TRUE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.EQU	TRUE		; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.EQU	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE1BASE	.EQU	$00		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.EQU	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.EQU	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.EQU	TRUE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.EQU	TRUE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.EQU	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE2BASE	.EQU	$00		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.EQU	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.EQU	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.EQU	TRUE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.EQU	TRUE		; IDE 2B (MASTER): 8 BIT XFER
+;
+PPIDEENABLE	.EQU	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.EQU	$20		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1BASE	.EQU	$00		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE2BASE	.EQU	$00		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+;
+SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+;
+PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+;
+PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
+HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+;
+LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTMODE		.EQU	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTCNT		.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
+LPTTRACE	.EQU	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+LPT0BASE	.EQU	$0C		; LPT 0: REGISTERS BASE ADR
+LPT1BASE	.EQU	$00		; LPT 1: REGISTERS BASE ADR
+;
+PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
+PPACNT		.EQU	1		; PPA: NUMBER OF PPA DEVICES (1-2)
+PPATRACE	.EQU	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPAMODE		.EQU	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
+PPA0BASE	.EQU	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
+PPA1BASE	.EQU	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
+;
+IMMENABLE	.EQU	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+IMMCNT		.EQU	1		; IMM: NUMBER OF IMM DEVICES (1-2)
+IMMTRACE	.EQU	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IMMMODE		.EQU	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
+IMM0BASE	.EQU	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
+IMM1BASE	.EQU	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
+;
+SYQENABLE	.EQU	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
+SYQCNT		.EQU	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
+SYQTRACE	.EQU	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SYQMODE		.EQU	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
+SYQ0BASE	.EQU	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQ1BASE	.EQU	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
+;
+PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+;
+UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+;
+SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
+SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
+;
+AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
+AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
+;
+SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+;
+DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.EQU	DMAMODE_RC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
+;
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
--- a/Source/HBIOS/cfg_master.asm
+++ b/Source/HBIOS/cfg_master.asm
@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW 2.X CONFIGURATION MASTER
+;   ROMWBW 3.X CONFIGURATION MASTER
 ;==================================================================================================
 ;
 ; THIS FILE IS *NOT* A REAL CONFIGURATION FILE.	 IT IS A MASTER TEMPLATE FILE
@@ -12,7 +12,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
+PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -31,10 +31,8 @@ DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
 MEMMGR		.EQU	MM_NONE		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
-RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
-RAMBIAS		.EQU	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
@@ -87,6 +85,9 @@ CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	614400		; CTC CLOCK FREQUENCY
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -115,6 +116,7 @@ ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
 PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
@@ -162,7 +164,7 @@ UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
@@ -233,6 +235,7 @@ TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -294,6 +297,18 @@ SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$BE		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.EQU	$FF		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -305,6 +320,9 @@ PPPSDENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
 PPPSDTRACE	.EQU	1		; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 PPPCONENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+ESPCONENABLE	.EQU	TRUE		; ESP: ENABLE ESP32 CONSOLE IO DRIVER VIDEO/KBD SUPPORT
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 HDSKTRACE	.EQU	1		; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 ;
@@ -364,7 +382,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
--- a/Source/HBIOS/cfg_mbc.asm
+++ b/Source/HBIOS/cfg_mbc.asm
@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW 2.X CONFIGURATION DEFAULTS FOR MBC
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR MBC
 ;==================================================================================================
 ;
 ; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_MBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
+PLATFORM	.EQU	PLT_MBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,6 @@ DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
 MEMMGR		.EQU	MM_MBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
@@ -54,6 +53,9 @@ CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	(4915200/8)	; CTC CLOCK FREQUENCY
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -80,6 +82,7 @@ ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
 PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
@@ -120,7 +123,7 @@ UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
@@ -161,6 +164,7 @@ TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -222,6 +226,8 @@ SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -229,6 +235,9 @@ PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+ESPCONENABLE	.EQU	TRUE		; ESP: ENABLE ESP32 CONSOLE IO DRIVER VIDEO/KBD SUPPORT
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 HDSKTRACE	.EQU	1		; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 ;
@@ -288,8 +297,7 @@ SPKENABLE	.EQU	TRUE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_MBC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_MBC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
-
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
--- a/Source/HBIOS/cfg_mk4.asm
+++ b/Source/HBIOS/cfg_mk4.asm
@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW 2.X CONFIGURATION FOR MARK IV
+;   ROMWBW 3.X CONFIGURATION FOR MARK IV
 ;==================================================================================================
 ;
 ; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_MK4		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
+PLATFORM	.EQU	PLT_MK4		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,10 +34,8 @@ DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
 MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
-RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
-RAMBIAS		.EQU	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 ;
 Z180_BASE	.EQU	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
 Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
@@ -60,6 +58,9 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$B0		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -86,6 +87,7 @@ ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
 PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
@@ -126,7 +128,7 @@ UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	TRUE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
@@ -172,6 +174,7 @@ TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -232,6 +235,8 @@ SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	TRUE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -243,6 +248,8 @@ PPPSDENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
 PPPSDTRACE	.EQU	1		; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 PPPCONENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
@@ -286,7 +293,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_ECB	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_ECB	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER 
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
--- a/Source/HBIOS/cfg_n8.asm
+++ b/Source/HBIOS/cfg_n8.asm
@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW 2.X CONFIGURATION FOR N8
+;   ROMWBW 3.X CONFIGURATION FOR N8
 ;==================================================================================================
 ;
 ; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_N8		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
+PLATFORM	.EQU	PLT_N8		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,10 +34,8 @@ DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
 MEMMGR		.EQU	MM_N8		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 RAMBIAS		.EQU	0		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
-RAMLOC		.EQU	0		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
 ;
 Z180_BASE	.EQU	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
 Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
@@ -62,6 +60,9 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$B0		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -88,6 +89,7 @@ ICMPPIBASE	.EQU	N8_PPI0		; BASE I/O ADDRESS OF ICM PPI
 PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	N8_PPI0		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
@@ -128,7 +130,7 @@ UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	TRUE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
@@ -174,6 +176,7 @@ TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -234,6 +237,8 @@ SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -241,6 +246,8 @@ PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
@@ -279,7 +286,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER 
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
--- a/Source/HBIOS/cfg_rcz180.asm
+++ b/Source/HBIOS/cfg_rcz180.asm
@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW 2.X CONFIGURATION DEFAULTS FOR RCBUS Z180 CPU
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR RCBUS Z180 CPU
 ;==================================================================================================
 ;
 ; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
+PLATFORM	.EQU	PLT_RCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,10 +34,8 @@ DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
 MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
-RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
-RAMBIAS		.EQU	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
@@ -60,6 +58,9 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -85,7 +86,14 @@ LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|RTC]
 LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
 LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
-DSKYENABLE	.EQU	FALSE		; ENABLES DSKY (DO NOT COMBINE WITH PPIDE)
+DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
@@ -132,7 +140,7 @@ UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
@@ -182,6 +190,7 @@ TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MS
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -242,6 +251,18 @@ SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$BE		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.EQU	$FF		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -249,6 +270,8 @@ PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
@@ -303,7 +326,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
--- a/Source/HBIOS/cfg_rcz280.asm
+++ b/Source/HBIOS/cfg_rcz280.asm
@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW 2.X CONFIGURATION DEFAULTS FOR RCBUS Z280 CPU
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR RCBUS Z280 CPU
 ;==================================================================================================
 ;
 ; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RCZ280	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
+PLATFORM	.EQU	PLT_RCZ280	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
 CPUFAM		.EQU	CPU_Z280	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,10 +34,8 @@ DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
 MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
-RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
-RAMBIAS		.EQU	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
@@ -60,6 +58,9 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -79,7 +80,14 @@ LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|RTC]
 LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
 LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
-DSKYENABLE	.EQU	FALSE		; ENABLES DSKY (DO NOT COMBINE WITH PPIDE)
+DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
@@ -126,7 +134,7 @@ UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
@@ -186,6 +194,7 @@ TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MS
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -246,6 +255,18 @@ SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$BE		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.EQU	$FF		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -253,6 +274,8 @@ PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
@@ -307,7 +330,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z280	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_Z280	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
--- a/Source/HBIOS/cfg_rcz80.asm
+++ b/Source/HBIOS/cfg_rcz80.asm
@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW 2.X CONFIGURATION DEFAULTS FOR RCBUS Z80
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR RCBUS Z80
 ;==================================================================================================
 ;
 ; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RCZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
+PLATFORM	.EQU	PLT_RCZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,6 @@ DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
 MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
@@ -57,6 +56,9 @@ CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	CPUOSC		; CTC CLOCK FREQUENCY
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -78,7 +80,14 @@ LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|RTC]
 LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
 LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
-DSKYENABLE	.EQU	FALSE		; ENABLES DSKY (DO NOT COMBINE WITH PPIDE)
+DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
@@ -125,7 +134,7 @@ UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
@@ -180,6 +189,7 @@ TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MS
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -240,6 +250,18 @@ SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$BE		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.EQU	$FF		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -247,6 +269,8 @@ PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
@@ -301,7 +325,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_RC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_RC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
--- a/Source/HBIOS/cfg_rph.asm
+++ b/Source/HBIOS/cfg_rph.asm
@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW 2.X CONFIGURATION FOR RHYOPHYRE
+;   ROMWBW 3.X CONFIGURATION FOR RHYOPHYRE
 ;==================================================================================================
 ;
 ; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RPH		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
+PLATFORM	.EQU	PLT_RPH		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	TRUE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,10 +34,8 @@ DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
 MEMMGR		.EQU	MM_RPH		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 RAMBIAS		.EQU	0		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
-RAMLOC		.EQU	0		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
 ;
 Z180_BASE	.EQU	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
 Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
@@ -60,6 +58,9 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$B0		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -84,8 +85,9 @@ DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
 ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
 ICMPPIBASE	.EQU	RPH_PPI0	; BASE I/O ADDRESS OF ICM PPI
 PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
-PKDPPIBASE	.EQU	RPH_PPI0		; BASE I/O ADDRESS OF PKD PPI
+PKDPPIBASE	.EQU	RPH_PPI0	; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
@@ -126,7 +128,7 @@ UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
@@ -163,6 +165,7 @@ TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -223,6 +226,8 @@ SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	FALSE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -230,6 +235,8 @@ PRPCONENABLE	.EQU	FALSE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
@@ -250,7 +257,7 @@ PIO4BASE	.EQU	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIOZBASE	.EQU	$88		; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
 PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
-PIOSBASE	.EQU	RPH_PPI0		; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
+PIOSBASE	.EQU	RPH_PPI0	; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
 ;
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 FIFO_BASE	.EQU	$0C		; UF: REGISTERS BASE ADR
@@ -268,7 +275,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
--- a/Source/HBIOS/cfg_s100.asm
+++ b/Source/HBIOS/cfg_s100.asm
@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW 2.X CONFIGURATION DEFAULTS FOR S100 Z180
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR S100 Z180
 ;==================================================================================================
 ;
 ; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_S100	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
+PLATFORM	.EQU	PLT_S100	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -30,14 +30,12 @@ CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_57600_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
 MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
-RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
-RAMBIAS		.EQU	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
@@ -46,8 +44,8 @@ MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ;
 Z180_BASE	.EQU	$C0		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
 Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
-Z180_MEMWAIT	.EQU	0		; Z180: MEMORY WAIT STATES (0-3)
-Z180_IOWAIT	.EQU	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+Z180_MEMWAIT	.EQU	1		; Z180: MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.EQU	2		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 Z180_TIMER	.EQU	TRUE		; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
 ;
 RTCIO		.EQU	$0C		; RTC LATCH REGISTER ADR
@@ -60,6 +58,9 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -74,12 +75,19 @@ FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
 ;
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
-LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
+LEDENABLE	.EQU	TRUE		; ENABLES STATUS LED (SINGLE LED)
 LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|RTC]
 LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
 LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
-DSKYENABLE	.EQU	FALSE		; ENABLES DSKY (DO NOT COMBINE WITH PPIDE)
+DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
@@ -122,11 +130,11 @@ DUART1BASE	.EQU	$40		; DUART 1: BASE ADDRESS OF CHIP
 DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
 DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
 ;
-UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTENABLE	.EQU	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
@@ -145,7 +153,7 @@ Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 ;
 ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ;
-SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
@@ -176,6 +184,7 @@ TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MS
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -236,6 +245,8 @@ SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -243,6 +254,8 @@ PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
@@ -297,7 +310,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
--- a/Source/HBIOS/cfg_sbc.asm
+++ b/Source/HBIOS/cfg_sbc.asm
@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW 2.X CONFIGURATION DEFAULTS FOR SBC
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR SBC
 ;==================================================================================================
 ;
 ; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
+PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,6 @@ DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
 MEMMGR		.EQU	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
@@ -54,6 +53,9 @@ CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	614400		; CTC CLOCK FREQUENCY
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -80,6 +82,7 @@ ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
 PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
@@ -120,7 +123,7 @@ UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	TRUE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	TRUE		; UART: AUTO-DETECT MF/PIC UART
@@ -161,6 +164,7 @@ TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -221,6 +225,8 @@ SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -228,6 +234,8 @@ PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 HDSKTRACE	.EQU	1		; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 ;
@@ -267,7 +275,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_ECB	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_ECB	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
--- a/Source/HBIOS/cfg_scz180.asm
+++ b/Source/HBIOS/cfg_scz180.asm
@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW 2.X CONFIGURATION DEFAULTS FOR SC Z180 VARIANTS (SC126, SC130, ETC.)
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR SC Z180 VARIANTS (SC126, SC130, ETC.)
 ;==================================================================================================
 ;
 ; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_SCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
+PLATFORM	.EQU	PLT_SCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,10 +34,8 @@ DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
 MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
-RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
-RAMBIAS		.EQU	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
@@ -60,6 +58,9 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -79,7 +80,14 @@ LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|RTC]
 LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
 LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
-DSKYENABLE	.EQU	FALSE		; ENABLES DSKY (DO NOT COMBINE WITH PPIDE)
+DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
@@ -126,7 +134,7 @@ UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
@@ -176,6 +184,7 @@ TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MS
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -236,6 +245,18 @@ SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$BE		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.EQU	$FF		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -243,6 +264,8 @@ PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
@@ -297,7 +320,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
--- a/Source/HBIOS/cfg_una.asm
+++ b/Source/HBIOS/cfg_una.asm
@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW 2.X CONFIGURATION DEFAULTS FOR UNA
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR UNA
 ;==================================================================================================
 ;
 ; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -15,7 +15,7 @@
 ;
 #INCLUDE "../UBIOS/ubios.inc"
 ;
-;PLATFORM	.EQU	PLT_UNA		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
+;PLATFORM	.EQU	PLT_UNA		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_UNA	; HARDWARE BIOS: BIOS_[WBW|UNA]
 ;
--- a/Source/HBIOS/cfg_z80retro.asm
+++ b/Source/HBIOS/cfg_z80retro.asm
@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW 2.X CONFIGURATION DEFAULTS FOR SIMPLE Z80 RETRO
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR SIMPLE Z80 RETRO
 ;==================================================================================================
 ;
 ; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_Z80RETRO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
+PLATFORM	.EQU	PLT_Z80RETRO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,6 @@ DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
 MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 MPGSEL_0	.EQU	$60		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$61		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
@@ -57,6 +56,9 @@ CTCPRECH	.EQU	0		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	1		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	7372800		; CTC CLOCK FREQUENCY
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -83,6 +85,7 @@ ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
 PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
@@ -118,7 +121,7 @@ UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
@@ -163,6 +166,7 @@ TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|M
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -195,6 +199,8 @@ SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
@@ -203,6 +209,8 @@ PPPSDENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
 PPPSDTRACE	.EQU	1		; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 PPPCONENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
@@ -228,7 +236,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
--- a/Source/HBIOS/cfg_zeta.asm
+++ b/Source/HBIOS/cfg_zeta.asm
@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW 2.X CONFIGURATION DEFAULTS FOR ZETA V1
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR ZETA V1
 ;==================================================================================================
 ;
 ; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_ZETA	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
+PLATFORM	.EQU	PLT_ZETA	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; BIOS_[WBW|UNA]: HARDWARE BIOS
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,6 @@ DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
 MEMMGR		.EQU	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
@@ -46,6 +45,9 @@ KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
 ;
 CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -72,6 +74,7 @@ ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
 PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
@@ -133,6 +136,7 @@ TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|M
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -166,6 +170,8 @@ SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
@@ -174,6 +180,8 @@ PPPSDENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
 PPPSDTRACE	.EQU	1		; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 PPPCONENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
@@ -199,7 +207,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
--- a/Source/HBIOS/cfg_zeta2.asm
+++ b/Source/HBIOS/cfg_zeta2.asm
@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW 2.X CONFIGURATION DEFAULTS FOR ZETA V2
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR ZETA V2
 ;==================================================================================================
 ;
 ; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_ZETA2	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
+PLATFORM	.EQU	PLT_ZETA2	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,6 @@ DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
 MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
@@ -57,6 +56,9 @@ CTCPRECH	.EQU	0		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	1		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	921600		; CTC CLOCK FREQUENCY
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -83,6 +85,7 @@ ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
 PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
@@ -118,7 +121,7 @@ UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
@@ -144,6 +147,7 @@ TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|M
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -177,6 +181,8 @@ SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
@@ -185,6 +191,8 @@ PPPSDENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
 PPPSDTRACE	.EQU	1		; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 PPPCONENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
 ;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
@@ -210,7 +218,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
 YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
--- a/Source/HBIOS/ch.asm
+++ b/Source/HBIOS/ch.asm
--- a/Source/HBIOS/dma.asm
+++ b/Source/HBIOS/dma.asm
@@ -2,6 +2,18 @@
 ; Z80 DMA DRIVER
 ;==================================================================================================
 ;
+#IF ((DMAMODE == DMAMODE_ECB) | (DMAMODE == DMAMODE_MBC))
+DMA_IO		.EQU	DMABASE
+DMA_CTL		.EQU	DMABASE + 1
+DMA_USEHALF	.EQU	TRUE
+#ENDIF
+;
+#IF (DMAMODE == DMAMODE_DUO)
+DMA_IO		.EQU	DMABASE
+DMA_CTL		.EQU	DMABASE + 3
+DMA_USEHALF	.EQU	FALSE
+#ENDIF
+;
 DMA_CONTINUOUS			.equ 	%10111101	; + Pulse
 DMA_BYTE			.equ 	%10011101	; + Pulse
 DMA_BURST 			.equ	%11011101	; + Pulse
@@ -30,21 +42,18 @@ DMA_FORCE			.EQU	0
 ; DMA CLOCK SPEED CONTROL - OPTION TO SWITCH TO HALF CLOCK SPEED. MOST SYSTEMS NEED THIS.
 ;==================================================================================================
 ;
-DMA_USEHALF			.equ	TRUE	; USE CLOCK DIVIDER
-;
-#IF (DMA_USEHALF & (DMAMODE=DMAMODE_MBC))
-#DEFINE DMAIOHALF LD A,(HB_RTCVAL) \ AND ~%00001000 \ OUT (RTCIO),A
-#DEFINE DMAIOFULL PUSH AF \ LD A,(HB_RTCVAL) \ OUT (RTCIO),A \ POP AF
-#ENDIF
-;
-#IF (DMA_USEHALF & (DMAMODE=DMAMODE_ECB))
-#DEFINE DMAIOHALF LD A,(HB_RTCVAL) \ OR %00001000 \ OUT (RTCIO),A 
-#DEFINE DMAIOFULL PUSH AF \ LD A,(HB_RTCVAL) \ OUT (RTCIO),A \ POP AF
-#ENDIF
-;
-#IF (!DMA_USEHALF)
-#DEFINE DMAIOHALF \;
-#DEFINE DMAIOFULL \;
+#IF (DMA_USEHALF)
+  #IF (DMAMODE=DMAMODE_MBC)
+    #DEFINE DMAIOHALF LD A,(HB_RTCVAL) \ AND ~%00001000 \ OUT (RTCIO),A
+    #DEFINE DMAIOFULL PUSH AF \ LD A,(HB_RTCVAL) \ OUT (RTCIO),A \ POP AF
+  #ENDIF
+  #IF (DMAMODE=DMAMODE_ECB)
+    #DEFINE DMAIOHALF LD A,(HB_RTCVAL) \ OR %00001000 \ OUT (RTCIO),A 
+    #DEFINE DMAIOFULL PUSH AF \ LD A,(HB_RTCVAL) \ OUT (RTCIO),A \ POP AF
+  #ENDIF
+#ELSE
+  #DEFINE DMAIOHALF \;
+  #DEFINE DMAIOFULL \;
 #ENDIF
 ;
 ;==================================================================================================
@@ -54,11 +63,11 @@ DMA_USEHALF			.equ	TRUE	; USE CLOCK DIVIDER
 DMA_INIT:
 	CALL	NEWLINE
 	PRTS("DMA: IO=0x$")		; announce
-	LD	A, DMABASE
+	LD	A, DMA_IO
 	CALL	PRTHEXBYTE
 ;
 	LD	A,DMA_FORCE
-	out	(DMABASE+1),a		; force ready off
+	out	(DMA_CTL),a		; force ready off
 ;
 	DMAIOHALF
 ;
@@ -67,7 +76,7 @@ DMA_INIT:
 ;
 	ld	hl,DMACode		; program the
 	ld	b,DMACode_Len		; dma command
-	ld	c,DMABASE		; block
+	ld	c,DMA_IO		; block
 ;
 	di
 	otir				; load dma
@@ -103,31 +112,31 @@ DMA_FAIL_FLAG:
 ;==================================================================================================
 ;
 DMAProbe:
-	ld	a,DMA_RESET	
-	out	(DMABASE),a
-	ld	a,%01111101 		; R0-Transfer mode, A -> B, start address follows
-	out	(DMABASE),a
+	ld	a,DMA_RESET		; $C3
+	out	(DMA_IO),a
+	ld	a,%01111101 		; R0-Transfer mode, A -> B, start address follows $7D
+	out	(DMA_IO),a
 	ld	a,$cc
-	out	(DMABASE),a
+	out	(DMA_IO),a
 	ld	a,$dd
-	out	(DMABASE),a
+	out	(DMA_IO),a
 	ld	a,$e5
-	out	(DMABASE),a
+	out	(DMA_IO),a
 	ld	a,$1a
-	out	(DMABASE),a
-	ld	a,DMA_LOAD
-	out	(DMABASE),a
+	out	(DMA_IO),a
+	ld	a,DMA_LOAD		; $CF
+	out	(DMA_IO),a
 ;
-	ld	a,DMA_READ_MASK_FOLLOWS	; set up
-	out	(DMABASE),a		; for 
-	ld	a,%00011000		; register
-	out	(DMABASE),a		; read
-	ld	a,DMA_START_READ_SEQUENCE
-	out	(DMABASE),a
+	ld	a,DMA_READ_MASK_FOLLOWS	; set up ; $BB
+	out	(DMA_IO),a		; for 
+	ld	a,%00011000		; register $18
+	out	(DMA_IO),a		; read
+	ld	a,DMA_START_READ_SEQUENCE	; $A7
+	out	(DMA_IO),a
 ;
-	in	a,(DMABASE)		; read in 
+	in	a,(DMA_IO)		; read in 
 	ld	c,a			; address
-	in	a,(DMABASE)
+	in	a,(DMA_IO)
 	ld	b,a
 ;
 	xor	a			; is it
@@ -165,7 +174,7 @@ DMALDIR:
 ;
 	ld	hl,DMACopy		; program the
 	ld	b,DMACopy_Len		; dma command
-	ld	c,DMABASE		; block
+	ld	c,DMA_IO		; block
 ;
 	DMAIOHALF
 ;
@@ -174,8 +183,8 @@ DMALDIR:
 	ei
 ;
 	ld	a,DMA_READ_STATUS_BYTE	; check status
-	out	(DMABASE),a		; of transfer
-	in	a,(DMABASE)		; set non-zero
+	out	(DMA_IO),a		; of transfer
+	in	a,(DMA_IO)		; set non-zero
 	and	%00111011		; if failed
 	sub	%00011011

@@ -211,7 +220,7 @@ DMAOTIR:
 ;
 	ld	hl,DMAOutCode		; program the
 	ld	b,DMAOut_Len		; dma command
-	ld	c,DMABASE		; block
+	ld	c,DMA_IO		; block
 ;
 	DMAIOHALF

@@ -220,8 +229,8 @@ DMAOTIR:
 	ei
 ;
 	ld	a,DMA_READ_STATUS_BYTE	; check status
-	out	(DMABASE),a		; of transfer
-	in	a,(DMABASE)		; set non-zero
+	out	(DMA_IO),a		; of transfer
+	in	a,(DMA_IO)		; set non-zero
 	and	%00111011		; if failed
 	sub	%00011011
 ;
@@ -262,7 +271,7 @@ DMAINIR:
 ;
 	ld	hl,DMAInCode		; program the
 	ld	b,DMAIn_Len		; dma command
-	ld	c,DMABASE		; block
+	ld	c,DMA_IO		; block
 ;
 	DMAIOHALF
 ;
@@ -271,8 +280,8 @@ DMAINIR:
 	ei
 ;
 	ld	a,DMA_READ_STATUS_BYTE	; check status
-	out	(DMABASE),a		; of transfer
-	in	a,(DMABASE)		; set non-zero
+	out	(DMA_IO),a		; of transfer
+	in	a,(DMA_IO)		; set non-zero
 	and	%00111011		; if failed
 	sub	%00011011
 ;
@@ -306,31 +315,31 @@ DMAIn_Len 	.equ	$-DMAInCode
 ;
 DMARegDump:
 	ld	a,DMA_READ_MASK_FOLLOWS
-	out	(DMABASE),a
+	out	(DMA_IO),a
 	ld	a,%01111110
-	out	(DMABASE),a
+	out	(DMA_IO),a
 	ld	a,DMA_START_READ_SEQUENCE
-	out	(DMABASE),a
+	out	(DMA_IO),a
 ;
-	in	a,(DMABASE)
+	in	a,(DMA_IO)
 	ld	c,a
-	in	a,(DMABASE)
+	in	a,(DMA_IO)
 	ld	b,a
 	call	PRTHEXWORD
 	ld	a,':'
 	call	COUT
 ;
-	in	a,(DMABASE)
+	in	a,(DMA_IO)
 	ld	c,a
-	in	a,(DMABASE)
+	in	a,(DMA_IO)
 	ld	b,a
 	call	PRTHEXWORD
 	ld	a,':'
 	call	COUT
 ;
-	in	a,(DMABASE)
+	in	a,(DMA_IO)
 	ld	c,a
-	in	a,(DMABASE)
+	in	a,(DMA_IO)
 	ld	b,a
 	call	PRTHEXWORD
 ;
--- a/Source/HBIOS/ds7rtc.asm
+++ b/Source/HBIOS/ds7rtc.asm
@@ -5,6 +5,11 @@
 ;
 ;==================================================================================================
 ;
+#IF (!PCFENABLE)
+	.ECHO	"*** DS7 DRIVER REQUIRES PCF DRIVER.  SET PCFENABLE!!!\n"
+	!!!	; FORCE AN ASSEMBLY ERROR
+#ENDIF
+;
 DS7_OUT		.EQU	10000000B		; SELECT SQUARE WAVE FUNCTION
 DS7_SQWE	.EQU	00010000B		; ENABLE SQUARE WAVE OUTPUT
 DS7_RATE	.EQU	00000000B		; SET 1HZ OUPUT
@@ -31,6 +36,7 @@ DS7_CTL		.EQU	(DS7_OUT | DS7_SQWE | DS7_RATE)
 ; 12HR MODE IS CURRENTLY ASSUMED
 ;
 DS7RTC_INIT:
+	CALL	NEWLINE			; Formatting
 	PRTS("DS1307: $")		; ANNOUNCE DRIVER
 ;
 	LD	A,(PCF_FAIL_FLAG)	; CHECK IF THE
--- a/Source/HBIOS/dsrtc.asm
+++ b/Source/HBIOS/dsrtc.asm
@@ -145,6 +145,8 @@ DSRTC_PREINIT:
 	;OR	DSRTC_IDLE		; SET OUR IDLE BITS
 	;LD	(DSRTC_OPRVAL),A	; SAVE IT
 ;
+	XOR	A			; ZERO
+	LD	(DSRTC_STAT),A		; CLEAR STATUS
 	CALL	DSRTC_DETECT		; HARDWARE DETECTION
 	LD	(DSRTC_STAT),A		; SAVE RESULT
 	RET	NZ			; ABORT IF ERROR
--- a/Source/HBIOS/esp.asm
+++ b/Source/HBIOS/esp.asm
@@ -0,0 +1,700 @@
+;
+;==================================================================================================
+; ESP32 DRIVER
+;
+; SUPPORTS DAN WERNER'S NHYODYNE (MBC) ESP32 MODULE
+; https://github.com/danwerner21/nhyodyne/tree/main/Z80ESP
+;==================================================================================================
+;
+; TODO:
+; - CLEAR CONSOLE SCREEN AT INITIALIZATION
+; - INITIALIZE BAUD/MODE OF SERIAL INTERFACES AT INITIALIZATION?
+;
+ESP_IOBASE	.EQU	$9C
+ESP_0_IO	.EQU	ESP_IOBASE + 0
+ESP_1_IO	.EQU	ESP_IOBASE + 1
+ESP_STAT	.EQU	ESP_IOBASE + 2
+;
+; ESP   STATUS PORT
+; MSB X X S S S S S S
+;         | | | | | +- ESP0 READY OUTPUT
+;         | | | | +--- ESP0 BUSY
+;         | | | +----- ESP0 SPARE
+;         | | +------- ESP1 READY OUTPUT
+;         | +--------- ESP1 BUSY
+;         +----------- ESP1 SPARE
+;
+ESP_0_RDY	.EQU	%00000001
+ESP_0_BUSY	.EQU	%00000010
+ESP_0_SPARE	.EQU	%00000100
+ESP_1_RDY	.EQU	%00001000
+ESP_1_BUSY	.EQU	%00010000
+ESP_1_SPARE	.EQU	%00100000
+;
+; COMMAND OPCODES
+;
+ESP_CMD_NOP	.EQU	0		; NO OP/SYNC
+ESP_CMD_SYNC	.EQU	0		; NO OP/SYNC
+ESP_0_CMD_COUT	.EQU	1		; CHAR OUT
+ESP_0_CMD_CSTR	.EQU	2		; STRING OUT
+ESP_0_CMD_KIN	.EQU	3		; KEY IN
+ESP_0_CMD_KST	.EQU	4		; KBD BUF STATUS
+ESP_CMD_SBAUD	.EQU	6		; SET SERIAL BAUD RATE
+ESP_CMD_SMODE	.EQU	7		; SET SERIAL LINE MODE
+ESP_CMD_SOUT	.EQU	8		; SERIAL BYTE OUT
+ESP_CMD_SIN	.EQU	10		; SERIAL BYTE IN
+ESP_CMD_SST	.EQU	11		; SERIAL INPUT STATUS
+ESP_CMD_DISC	.EQU	$FF		; DISCOVER
+;
+; ESP CONFIG TABLE ENTRY OFFSETS
+;
+ESP_CFG_DEV	.EQU	0		; DEVICE NUMBER
+ESP_CFG_IO	.EQU	1		; ESP I/O PORT
+ESP_CFG_ST	.EQU	2		; ESP STATUS PORT
+ESP_CFG_RDYMSK	.EQU	3		; ESP READY MASK
+ESP_CFG_BSYMSK	.EQU	4		; ESP BUSY MASK
+;
+; GLOBAL ESP INITIALIZATION
+;
+ESP_INIT:
+;
+	CALL	NEWLINE			; FORMATTING
+	PRTS("ESP: IO=0x$")
+	LD	A,ESP_IOBASE
+	CALL	PRTHEXBYTE
+;
+	XOR	A			; ZERO ACCUM
+	LD	(ESP_PRES),A		; CLEAR MODULE PRESENCE BITS
+;
+	; DETECT FIRST ESP32 MODULE
+	PRTS(" A=$")
+	LD	IY,ESPSER0_CFG
+	CALL	ESP_DETECT
+	JR	Z,ESP_INIT1		; FOUND
+	LD	DE,ESP_STR_NOHW
+	CALL	WRITESTR
+	JR	ESP_INIT2
+;
+ESP_INIT1:
+	CALL	ESP_PRTVER
+
+	LD	A,(ESP_PRES)
+	SET	0,A
+	LD	(ESP_PRES),A
+
+;
+ESP_INIT2:
+	; DETECT SECOND ESP32 MODULE
+	PRTS(" B=$")
+	LD	IY,ESPSER1_CFG
+	CALL	ESP_DETECT
+	JR	Z,ESP_INIT3		; FOUND
+	LD	DE,ESP_STR_NOHW
+	CALL	WRITESTR
+	JR	ESP_INIT4
+;
+ESP_INIT3:
+	CALL	ESP_PRTVER
+
+	LD	A,(ESP_PRES)
+	SET	1,A
+	LD	(ESP_PRES),A
+
+;
+ESP_INIT4:
+	; INITIALIZE FIRST MODULE CHILD DRIVERS
+	LD	A,(ESP_PRES)
+	BIT	0,A
+	JR	Z,ESP_INIT5
+	LD	IY,ESPSER0_CFG
+	CALL	ESPSER_INIT		; SERIAL INITIALIZATION
+	LD	IY,ESPCON0_CFG
+	CALL	ESPCON_INIT		; CONSOLE INITIALIZATION
+;
+ESP_INIT5:
+	; INITIALIZE SECOND MODULE CHILD DRIVERS
+	LD	A,(ESP_PRES)
+	BIT	1,A
+	JR	Z,ESP_INIT6
+	LD	IY,ESPSER1_CFG
+	CALL	ESPSER_INIT		; SERIAL INITIALIZATION
+;
+ESP_INIT6:
+	RET
+;
+;==================================================================================================
+; ESP32 INTERFACE FUNCTIONS
+;==================================================================================================
+;
+ESP_DETECT:
+	; TRY TO DETECT IF PORT IS FLOATING AND
+	; FAIL DETECTION IF SO
+	LD	C,(IY+ESP_CFG_ST)	; ESP STATUS PORT
+	IN	A,(C)			; READ IT
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	AND	%11100000		; ISOLATE TOP 3 BITS
+	CP	$00			; ALWAYS ZERO IF PRESENT
+	RET	NZ			; ABORT ON FAILURE
+;
+	; ESP32 PROCESSOR MAY TAKE A FEW SECONDS TO START UP, SO
+	; HERE WE WAIT FOR BUSY TO CLEAR WITH ABOUT A 5 SECOND TIMEOUT
+	LD	B,0			; LOOP UP TO 256 TIMES
+	LD	C,(IY+ESP_CFG_ST)	; ESP STATUS PORT
+ESP_DETECT1:
+	IN	A,(C)			; GET STATUS
+	AND	(IY+ESP_CFG_BSYMSK)	; IS ESP BUSY?
+	JR	Z,ESP_DETECT2		; MOVE ALONG IF NOT BUSY
+	LD	DE,1500			; 1500 * 16US = 24MS
+	CALL	VDELAY			; DELAY
+	DJNZ	ESP_DETECT1		; LOOP
+	OR	$FF			; SIGNAL FAILURE
+	RET				; DONE
+;
+ESP_DETECT2:
+	CALL 	ESP_SYNC
+	;LD	A,B			; *DEBUG*
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CALL	ESP_CLR			; CLEAR ANY PENDING DATA
+	LD	A,ESP_CMD_DISC		; DISCOVER COMMAND
+	CALL	ESP_OUT			; SEND IT
+;
+	; LOOK FOR SIGNATURE STARTING WITH "ESP"
+	CALL	ESP_INWAIT		; ATTEMPT TO GET CHAR
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CP	'E'
+	RET	NZ
+	CALL	ESP_INWAIT		; ATTEMPT TO GET CHAR
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CP	'S'
+	RET	NZ
+	CALL	ESP_INWAIT		; ATTEMPT TO GET CHAR
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CP	'P'
+	RET
+;
+; CLEAR ESP INPUT QUEUE
+;
+ESP_CLR:
+;	LD	B,0			; MAX CHARS TO READ   /Removed DDW
+;ESP_CLR0:   /Removed DDW
+	CALL	ESP_WTNBSY		; WAIT TILL NOT BUSY
+	RET	NZ			; BAIL OUT IF TIMEOUT
+	IN	A,(ESP_STAT)		; GET STATUS
+	AND	(IY+ESP_CFG_RDYMSK)	; IS THERE MORE DATA?
+	RET	Z			; IF NOT, DONE
+	LD	C,(IY+ESP_CFG_IO)	; ESP I/O PORT
+	IN	A,(C)			; GET BYTE
+	JP 	ESP_CLR
+;	DJNZ	ESP_CLR0		; LOOP TILL DONE /Removed DDW
+;	OR	$FF			; SIGNAL FAILURE /Removed DDW
+;	RET /Removed DDW
+
+;
+; RE-SYNC ESP  (added DDW)
+;
+ESP_SYNC:
+	LD	B,0				; sync count -- WORST CASE  PERFORMACE COULD BE IMPROVED BY REDUCING THIS VALUE
+ESP_SYNC0:
+	PUSH 	BC
+	LD	A,ESP_CMD_SYNC		; Sync ESP
+	CALL	ESP_OUT			; SEND CMD OPCODE
+	POP 	BC
+	DJNZ	ESP_SYNC0		; LOOP TILL DONE
+	RET
+;
+; PRINT ESP VERSION STRING TO CONSOLE
+;
+ESP_PRTVER:
+	CALL 	ESP_SYNC
+	CALL	ESP_CLR			; CLEAR ANY PENDING DATA
+	;LD	DE,1000			; SMALL DELAY HERE
+	;CALL	VDELAY			; ... SEEMS TO HELP RELIABILITY
+	LD	A,ESP_CMD_DISC		; DISCOVER COMMAND
+	CALL	ESP_OUT			; SEND IT
+	CALL	ESP_WTRDY		; WAIT FOR READY TO OUTPUT
+ESP_PRTVER1:
+	CALL	ESP_WTNBSY		; WAIT TILL NOT BUSY
+	IN	A,(ESP_STAT)		; GET STATUS
+	AND	(IY+ESP_CFG_RDYMSK)	; ISOLATE OUTPUT READY BIT
+	RET	Z			; DONE IF NOTHING READY
+	CALL	ESP_IN			; GET NEXT CHAR
+	CALL	COUT			; PRINT CHAR
+	JR	ESP_PRTVER1		; LOOP
+;
+; SEND BYTE TO ESP
+;
+ESP_OUT:
+	PUSH	AF			; SAVE VALUE
+	CALL	ESP_WTNBSY		; WAIT TILL NOT BUSY
+	POP	AF			; POP VALUE
+	LD	C,(IY+ESP_CFG_IO)	; ESP I/O PORT
+	OUT	(C),A			; SEND BYTE
+	JR	ESP_WTBSY		; RETURN VIA WTBSY
+;
+; GET BYTE FROM ESP (BLOCKING)
+;
+ESP_INWAIT:
+	CALL	ESP_WTNBSY		; WAIT TILL NOT BUSY
+	CALL	ESP_WTRDY		; WAIT FOR READY TO OUTPUT
+	JP 		ESP_IN1			; Added DDW
+;
+; GET BYTE FROM ESP (NON BLOCKING)
+;
+ESP_IN:
+	CALL	ESP_WTNBSY		; WAIT TILL NOT BUSY
+ESP_IN1:
+	LD	C,(IY+ESP_CFG_IO)	; ESP I/O PORT
+	IN	A,(C)			; GET BYTE
+	PUSH	AF			; SAVE VALUE
+	CALL	ESP_WTBSY		; WAIT TILL BUSY
+	POP	AF			; RESTORE VALUE
+	RET				; AND RETURN
+;
+; WAIT FOR ESP TO BE NOT BUSY
+;
+ESP_WTNBSY:
+	LD	B,0			; MAX TRIES
+	;PUSH	HL			; SAVE HL
+	;LD	HL,0			; MAX TRIES
+ESP_WTNBSY1:
+	LD	C,(IY+ESP_CFG_ST)	; ESP STATUS PORT
+	IN	A,(C)			; GET STATUS
+	AND	(IY+ESP_CFG_BSYMSK)	; IS ESP BUSY?
+	RET	Z			; RETURN IF NOT BUSY
+	;JR	Z,ESP_WTNBSY_Z		; RETURN IF NOT BUSY
+	DJNZ	ESP_WTNBSY1		; ELSE LOOP
+	;DEC	HL			; DEC LOOP COUNTER
+	;LD	A,H			; CHECK FOR
+	;OR	L			; ... TIMEOUT
+	;JR	NZ,ESP_WTNBSY1		; LOOP AS NEEDED
+	;CALL	PC_ASTERISK		; *DEBUG*
+	OR	$FF			; SIGNAL TIMEOUT
+;ESP_WTNBSY_Z:
+	;POP	HL			; RECOVER HL
+	RET				; AND RETURN
+;
+; WAIT FOR ESP TO BE BUSY
+;
+ESP_WTBSY:
+	LD	B,3			; MAX TRIES
+ESP_WTBSY1:
+	LD	C,(IY+ESP_CFG_ST)	; ESP STATUS PORT
+	IN	A,(C)			; GET STATUS
+	XOR	$FF			; INVERT SO 0=BUSY
+	AND	(IY+ESP_CFG_BSYMSK)	; IS ESP BUSY?
+	RET	Z			; RETURN IF BUSY
+	DJNZ	ESP_WTBSY1		; ELSE LOOP
+	OR	$FF			; SIGNAL TIMEOUT
+	RET				; AND RETURN
+;;;;
+;;;; WAIT FOR ESP TO BE READY TO OUTPUT
+;;;;
+;;;ESP_WTRDY:
+;;;	PUSH	HL			; SAVE HL
+;;;	LD	HL,0			; MAX TRIES
+;;;ESP_WTRDY1:
+;;;	LD	C,(IY+ESP_CFG_ST)	; ESP STATUS PORT
+;;;	IN	A,(C)			; GET STATUS
+;;;	XOR	$FF			; INVERT SO 0=READY
+;;;	AND	(IY+ESP_CFG_RDYMSK)	; IS ESP READY TO OUTPUT
+;;;	JR	Z,ESP_WTRDY_Z		; RETURN IF READY
+;;;	DEC	HL			; DEC LOOP COUNTER
+;;;	LD	A,H			; CHECK FOR
+;;;	OR	L			; ... TIMEOUT
+;;;	JR	NZ,ESP_WTRDY1		; LOOP AS NEEDED
+;;;	CALL	PC_PERIOD		; *DEBUG*
+;;;	OR	$FF			; SIGNAL TIMEOUT
+;;;ESP_WTRDY_Z:
+;;;	POP	HL			; RECOVER HL
+;;;	RET				; AND RETURN
+;
+; WAIT FOR ESP TO BE READY TO OUTPUT
+;
+ESP_WTRDY:
+	LD	B,0			; MAX TRIES
+ESP_WTRDY1:
+	LD	C,(IY+ESP_CFG_ST)	; ESP STATUS PORT
+	IN	A,(C)			; GET STATUS
+	XOR	$FF			; INVERT SO 0=READY
+	AND	(IY+ESP_CFG_RDYMSK)	; IS ESP READY TO OUTPUT
+	RET	Z			; RETURN IF READY
+	DJNZ	ESP_WTRDY1		; ELSE LOOP
+	;CALL	PC_PERIOD		; *DEBUG*
+	CALL 	ESP_SYNC 		; SOMETHING WENT WRONG, ENSURE SYNC (Added DDW)
+	OR	$FF			; SIGNAL TIMEOUT
+	RET				; AND RETURN
+;
+;
+;
+ESP_PRES		.DB	0	; MODULE PRESENCE BITS
+;
+ESP_STR_NOHW		.TEXT	"NOT PRESENT$"
+ESP_STR_UPGRADE		.TEXT	"!!!UPGRADE REQUIRED!!!$"
+;
+;==================================================================================================
+; ESP32 CONSOLE DRIVER
+;==================================================================================================
+;
+;
+ESPCON_ROWS	.EQU	25		; VGA DISPLAY ROWS
+ESPCON_COLS	.EQU	80		; VGA DISPLAY COLS
+;
+;
+;
+ESPCON_INIT:
+	LD	A,(ESPCON_DEVCNT)	; GET ESPCON PHYSICAL DEVICE COUNT
+	LD	(IY+ESP_CFG_DEV),A	; SAVE PHYSICAL UNIT NUMBER
+	INC	A			; UPDATE COUNT
+	LD	(ESPCON_DEVCNT),A	; SAVE COUNT
+;
+; ADD OURSELVES TO CIO DISPATCH TABLE
+;
+	LD	BC,ESPCON_FNTBL		; BC := FUNCTION TABLE ADDRESS
+	PUSH	IY			; COPY CONFIG ENTRY PTR
+	POP	DE			; ... TO DE
+	CALL	CIO_ADDENT		; ADD ENTRY, A := UNIT ASSIGNED
+	LD	(HCB + HCB_CRTDEV),A	; SET OURSELVES AS THE CRT DEVICE
+;
+; ANNOUNCE OURSLEVES
+;
+	CALL	NEWLINE			; FORMATTING
+	PRTS("ESPCON$")			; NAME
+	LD	A,(IY+ESP_CFG_DEV)	; GET PHYSICAL UNIT NUMBER
+	CALL	PRTDECB			; UNIT STILL IN A FROM ABOVE
+	CALL	PC_COLON		; FORMATTING
+;
+	; DISPLAY CONSOLE DIMENSIONS
+	CALL	PC_SPACE
+	LD	A,ESPCON_COLS
+	CALL	PRTDECB
+	LD	A,'X'
+	CALL	COUT
+	LD	A,ESPCON_ROWS
+	CALL	PRTDECB
+	CALL	PRTSTRD
+	.TEXT	" TEXT (ANSI)$"
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; DRIVER FUNCTION TABLE
+;
+ESPCON_FNTBL:
+	.DW	ESPCON_IN
+	.DW	ESPCON_OUT
+	.DW	ESPCON_IST
+	.DW	ESPCON_OST
+	.DW	ESPCON_INITDEV
+	.DW	ESPCON_QUERY
+	.DW	ESPCON_DEVICE
+#IF (($ - ESPCON_FNTBL) != (CIO_FNCNT * 2))
+	.ECHO	"*** INVALID ESPCON FUNCTION TABLE ***\n"
+#ENDIF
+;
+;
+;
+ESPCON_IN:
+	CALL	ESPCON_IST
+	JR	Z,ESPCON_IN
+	LD	A,ESP_0_CMD_KIN		; KBD INPUT
+	CALL	ESP_OUT			; SEND CMD OPCODE
+	CALL	ESP_INWAIT		; GET KEY
+	LD	E,A			; PUT IN E
+	XOR	A			; SIGNAL SUCCES
+	RET				; AND DONE
+;
+;
+;
+ESPCON_IST:
+	CALL	ESP_CLR			; CLEAR ANY PENDING DATA (Added DDW)
+	LD	A,ESP_0_CMD_KST		; KBD BUF STATUS
+	CALL	ESP_OUT			; SEND CMD OPCODE
+	CALL	ESP_INWAIT		; GET BUF SIZE
+	OR	A			; SET FLAGS
+	RET	Z			; AND DONE
+	OR	A
+	RET
+;
+;
+;
+ESPCON_OUT:
+	PUSH	DE
+	LD	A,ESP_0_CMD_COUT	; CHAR OUT OPCODE
+	CALL	ESP_OUT
+	POP	DE
+	LD	A,E
+	CALL	ESP_OUT			; SEND CHAR VALUE
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+;
+;
+ESPCON_OST:
+	XOR	A			; ZERO ACCUM
+	INC	A			; ACCUM := 1 TO SIGNAL 1 BUFFER POSITION
+	RET				; RETURN
+;
+;
+;
+ESPCON_INITDEV:
+	CALL 	ESP_CLR
+	CALL 	ESP_SYNC
+;	SYSCHKERR(ERR_NOTIMPL)  Removed DDW
+	RET
+;
+;
+;
+ESPCON_QUERY:
+	LD	DE,0
+	LD	HL,0
+	XOR	A
+	RET
+;
+;
+;
+ESPCON_DEVICE:
+	LD	D,CIODEV_ESPCON		; D := DEVICE TYPE
+	LD	E,(IY+ESP_CFG_DEV)	; E := DEVICE NUM
+	LD	C,$BF			; C := DEVICE TYPE, 0xBF IS PROP TERM
+	LD	H,0			; H := 0, DRIVER HAS NO MODES
+	LD	L,(IY+ESP_CFG_IO)	; L := BASE I/O ADDRESS
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; ESPCON CONFIGURATION
+;
+ESPCON_CFG:
+ESPCON0_CFG:
+	.DB	0				; DEVICE NUMBER (UPDATED DURING INIT)
+	.DB	ESP_0_IO			; ESP DATA PORT
+	.DB	ESP_STAT			; ESP STATUS PORT
+	.DB	ESP_0_RDY			; ESP READY BIT MASK
+	.DB	ESP_0_BUSY			; ESP BUSY BIT MASK
+;
+;
+;
+ESPCON_DEVCNT	.DB	0			; ESPCON DEVICES COUNT
+;
+;==================================================================================================
+; ESP32 SERIAL DRIVER
+;==================================================================================================
+;
+ESPSER_LINECFG		.EQU	SER_115200_8N1
+;
+ESPSER_CFG_LINE		.EQU	5
+;
+;
+;
+ESPSER_INIT:
+	LD	A,(ESPSER_DEVCNT)	; GET ESPSER PHYSICAL DEVICE COUNT
+	LD	(IY+ESP_CFG_DEV),A	; SAVE PHYSICAL UNIT NUMBER
+	INC	A			; UPDATE COUNT
+	LD	(ESPSER_DEVCNT),A	; SAVE COUNT
+;
+; ADD OURSELVES TO CIO DISPATCH TABLE
+;
+	LD	BC,ESPSER_FNTBL		; BC := FUNCTION TABLE ADDRESS
+	PUSH	IY			; COPY CONFIG ENTRY PTR
+	POP	DE			; ... TO DE
+	CALL	CIO_ADDENT		; ADD ENTRY, A := UNIT ASSIGNED
+;
+; ANNOUNCE OURSLEVES
+;
+	CALL	NEWLINE			; FORMATTING
+	PRTS("ESPSER$")			; NAME
+	LD	A,(IY+ESP_CFG_DEV)	; GET PHYSICAL UNIT NUMBER
+	CALL	PRTDECB			; UNIT STILL IN A FROM ABOVE
+	CALL	PC_COLON		; FORMATTING
+;
+	PRTS(" MODE=$")				; FORMATTING
+	LD	E,(IY+ESPSER_CFG_LINE+0)	; FIRST CONFIG BYTE TO E
+	LD	D,(IY+ESPSER_CFG_LINE+1)	; SECOND CONFIG BYTE TO D
+	CALL	PS_PRTSC0			; PRINT CONFIG
+;
+; TODO: PRINT SERIAL CONFIG
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; DRIVER FUNCTION TABLE
+;
+ESPSER_FNTBL:
+	.DW	ESPSER_IN
+	.DW	ESPSER_OUT
+	.DW	ESPSER_IST
+	.DW	ESPSER_OST
+	.DW	ESPSER_INITDEV
+	.DW	ESPSER_QUERY
+	.DW	ESPSER_DEVICE
+#IF (($ - ESPSER_FNTBL) != (CIO_FNCNT * 2))
+	.ECHO	"*** INVALID ESPSER FUNCTION TABLE ***\n"
+#ENDIF
+;
+;
+;
+ESPSER_IN:
+	CALL	ESPSER_IST
+	JR	Z,ESPSER_IN
+	LD	A,ESP_CMD_SIN		; SERIAL INPUT
+	CALL	ESP_OUT			; SEND CMD OPCODE
+	CALL	ESP_INWAIT		; GET KEY
+	LD	E,A			; PUT IN E
+	XOR	A			; SIGNAL SUCCES
+	RET				; AND DONE
+;
+;
+;
+ESPSER_IST:
+	CALL	ESP_CLR			; CLEAR ANY PENDING DATA (Added DDW)
+	LD	A,ESP_CMD_SST		; SERIAL STATUS
+	CALL	ESP_OUT			; SEND CMD OPCODE
+	CALL	ESP_INWAIT		; GET BUF SIZE
+	OR	A			; SET FLAGS
+	RET	Z			; AND DONE
+	OR	A
+	RET
+;
+;
+;
+ESPSER_OUT:
+	PUSH	DE
+	LD	A,ESP_CMD_SOUT		; CHAR OUT OPCODE
+	CALL	ESP_OUT
+	POP	DE
+	LD	A,E
+	CALL	ESP_OUT			; SEND CHAR VALUE
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+;
+;
+ESPSER_OST:
+	XOR	A			; ZERO ACCUM
+	INC	A			; ACCUM := 1 TO SIGNAL 1 BUFFER POSITION
+	RET				; RETURN
+;
+;
+;
+ESPSER_INITDEV:
+	CALL 	ESP_CLR
+	CALL 	ESP_SYNC
+	PUSH	DE			; SAVE INCOMING CONFIG WORD
+;
+	; XLATE NEW LINE MODE INTO C
+	LD	A,E
+	AND	%00111111		; ISOLATE MODE BITS
+	LD	C,0			; 8N1 = 0
+	CP	SER_DATA8 | SER_PARNONE | SER_STOP1
+	JR	Z,ESPSER_INITDEV1	; IF MATCH, DO IT
+	INC	C			; 8E1 = 1
+	CP	SER_DATA8 | SER_PAREVEN | SER_STOP1
+	JR	Z,ESPSER_INITDEV1	; IF MATCH, DO IT
+	INC	C			; 8O1 = 2
+	CP	SER_DATA8 | SER_PARODD | SER_STOP1
+	JR	Z,ESPSER_INITDEV1	; IF MATCH, DO IT
+	INC	C			; 7N1 = 3
+	CP	SER_DATA7 | SER_PARNONE | SER_STOP1
+	JR	Z,ESPSER_INITDEV1	; IF MATCH, DO IT
+	INC	C			; 7E1 = 4
+	CP	SER_DATA7 | SER_PAREVEN | SER_STOP1
+	JR	Z,ESPSER_INITDEV1	; IF MATCH, DO IT
+	INC	C			; 7O1 = 5
+	CP	SER_DATA7 | SER_PARODD | SER_STOP1
+	JR	Z,ESPSER_INITDEV1	; IF MATCH, DO IT
+	JR	NZ,ESPSER_INITDEV_ERR	; ELSE FAIL
+;
+ESPSER_INITDEV1:
+	; DECODE NEW BAUD RATE INTO DE:HL
+	LD	H,0
+	LD	A,D
+	AND	%00011111
+	LD	L,A
+	LD	DE,75
+	PUSH	BC			; SAVE NEW LINE MODE
+	CALL	DECODE			; DE:HL IS DECODED BAUD RATE
+	POP	BC			; RESTORE NEW LINE MODE
+	JR	NZ,ESPSER_INITDEV_ERR	; IF ERROR, FAIL
+;
+	; PROGRAM NEW LINE MODE
+	PUSH	BC
+	LD	A,ESP_CMD_SMODE
+	CALL	ESP_OUT
+	POP	BC
+	LD	A,C
+	;CALL	PRTHEXBYTE
+	;CALL	LDELAY
+	CALL	ESP_OUT
+;
+	; PROGRAM NEW BAUD RATE
+	LD	A,ESP_CMD_SBAUD
+	CALL	ESP_OUT
+	LD	A,L
+	CALL	ESP_OUT
+	LD	A,H
+	CALL	ESP_OUT
+	LD	A,E
+	CALL	ESP_OUT
+	LD	A,D
+	CALL	ESP_OUT
+;
+	; SAVE NEW LINE CONFIG WORD
+	POP	DE				; RESTORE CONFIG WORD
+	LD	(IY+ESPSER_CFG_LINE+0),E	; FIRST CONFIG BYTE
+	LD	(IY+ESPSER_CFG_LINE+1),D	; SECOND CONFIG BYTE
+;
+	XOR	A
+	RET
+;
+ESPSER_INITDEV_ERR:
+	POP	DE			; THROW AWAY CONFIG WORD ON STACK
+	OR	$FF
+	RET
+;
+;
+;
+ESPSER_QUERY:
+	LD	E,(IY+ESPSER_CFG_LINE+0)	; FIRST CONFIG BYTE TO E
+	LD	D,(IY+ESPSER_CFG_LINE+1)	; SECOND CONFIG BYTE TO D
+	LD	HL,0
+	XOR	A
+	RET
+;
+;
+;
+ESPSER_DEVICE:
+	LD	D,CIODEV_ESPSER		; D := DEVICE TYPE
+	LD	E,(IY+ESP_CFG_DEV)	; E := DEVICE NUM
+	LD	C,$00			; C := DEVICE TYPE, 0x00 IS RS-232
+	LD	H,0			; H := 0, DRIVER HAS NO MODES
+	LD	L,(IY+ESP_CFG_IO)	; L := BASE I/O ADDRESS
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; ESPSER CONFIGURATION
+;
+ESPSER_CFG:
+ESPSER0_CFG:
+	.DB	0				; DEVICE NUMBER (UPDATED DURING INIT)
+	.DB	ESP_0_IO			; ESP DATA PORT
+	.DB	ESP_STAT			; ESP STATUS PORT
+	.DB	ESP_0_RDY			; ESP READY BIT MASK
+	.DB	ESP_0_BUSY			; ESP BUSY BIT MASK
+	.DW	ESPSER_LINECFG			; LINE CONFIGURATION
+
+;
+ESPSER1_CFG:
+	.DB	0				; DEVICE NUMBER (UPDATED DURING INIT)
+	.DB	ESP_1_IO			; ESP DATA PORT
+	.DB	ESP_STAT			; ESP STATUS PORT
+	.DB	ESP_1_RDY			; ESP READY BIT MASK
+	.DB	ESP_1_BUSY			; ESP BUSY BIT MASK
+	.DW	ESPSER_LINECFG			; LINE CONFIGURATION
+;
+;
+;
+ESPSER_DEVCNT	.DB	0			; ESPSER DEVICES COUNT
--- a/Source/HBIOS/fd.asm
+++ b/Source/HBIOS/fd.asm
@@ -811,19 +811,27 @@ FD_DETECT:
 	IN	A,(FDC_MSR)	; READ MSR
 	;CALL	PC_SPACE	; *DEBUG*
 	;CALL	PRTHEXBYTE	; *DEBUG*
-	CP	$80
-	JR	Z,FD_DETECT1	; $80 IS OK
-	CP	$D0
-	JR	Z,FD_DETECT1	; $D0 IS OK
-	RET			; NOPE, ABORT WITH ZF=NZ
-;
-FD_DETECT1:
-	CALL	DLY32		; WAIT A BIT FOR FDC
-	IN	A,(FDC_MSR)	; READ MSR AGAIN
+	
+	CP	$D0		; SPECIAL CASE: DATA PENDING?
+	JR	NZ,FD_DETECT1	; NOPE, MOVE ALONG
+	IN	A,(FDC_DATA)	; SWALLOW THE PENDING DATA
+	CALL	DLY32		; SETTLE
+	IN	A,(FDC_MSR)	; ... AND REREAD THE STATUS
 	;CALL	PC_SPACE	; *DEBUG*
 	;CALL	PRTHEXBYTE	; *DEBUG*
-	CP	$80
-	RET			; $80 OK, ELSE NOT PRESENT
+
+FD_DETECT1:
+	CP	$80		; WE EXPECT $80
+	RET	Z		; IF SO, ALL DONE
+
+	; WE HAVE SEEN AN FDC THAT NEEDS A SECOND READ TO GET
+	; DESIRED VALUE, SO TRY ONE MORE TIME
+	CALL	DLY32		; WAIT A BIT
+	IN	A,(FDC_MSR)	; ... AND REREAD THE STATUS
+	;CALL	PC_SPACE	; *DEBUG*
+	;CALL	PRTHEXBYTE	; *DEBUG*
+	CP	$80		; CHECK FOR CORRECT VALUE
+	RET			; RETURN WITH ZF ACCORDING TO RESULT
 ;
 ; UNIT INITIALIZATION
 ;
--- a/Source/HBIOS/h8p.asm
+++ b/Source/HBIOS/h8p.asm
@@ -0,0 +1,162 @@
+;
+;==================================================================================================
+; HEATH H8 FRONT PANEL (DISPLAY AND KEYBOARD) ROUTINES
+;==================================================================================================
+;
+; LED SEGMENTS (BIT VALUES)
+;
+;	+--02--+
+;	40    04
+;	+--01--+
+;	20    08
+;	+--10--+  80
+;
+;__H8P_PREINIT_______________________________________________________________________________________
+;
+;  CONFIGURE AND RESET PANEL
+;____________________________________________________________________________________________________
+;
+; HARDWARE RESET PRIOR TO ROMWBW CONSOLE INITIALIZATION
+;
+H8P_PREINIT:
+	LD	A,(DSKY_DISPACT)	; DSKY DISPATCHER ALREADY SET?
+	OR	A			; SET FLAGS
+	RET	NZ			; IF ALREADY ACTIVE, ABORT
+;
+	; REGISTER DRIVER WITH HBIOS
+	LD	BC,H8P_DISPATCH
+	CALL	DSKY_SETDISP
+;
+	RET
+;
+;__H8P_INIT__________________________________________________________________________________________
+;
+;  DISPLAY DSKY INFO ON ROMWBW CONSOLE
+;____________________________________________________________________________________________________
+;
+H8P_INIT:
+	CALL	NEWLINE			; FORMATTING
+	PRTS("H8P:$")			; DRIVER TAG
+;
+	RET				; DONE
+;
+; DSKY DEVICE FUNCTION DISPATCH ENTRY
+;   A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR
+;   B: FUNCTION (IN)
+;
+H8P_DISPATCH:
+	LD	A,B			; GET REQUESTED FUNCTION
+	AND	$0F			; ISOLATE SUB-FUNCTION
+	JP	Z,H8P_RESET		; RESET DSKY HARDWARE
+	DEC	A	
+	JP	Z,H8P_STAT		; GET KEYPAD STATUS
+	DEC	A	
+	JP	Z,H8P_GETKEY		; READ A KEY FROM THE KEYPAD
+	DEC	A	
+	JP	Z,H8P_SHOWHEX		; DISPLAY A 32-BIT BINARY VALUE IN HEX
+	DEC	A	
+	JP	Z,H8P_SHOWSEG		; DISPLAY SEGMENTS
+	DEC	A	
+	JP	Z,H8P_KEYLEDS		; SET KEYPAD LEDS
+	DEC	A	
+	JP	Z,H8P_STATLED		; SET STATUS LED
+	DEC	A	
+	JP	Z,H8P_BEEP		; BEEP DSKY SPEAKER
+	DEC	A
+	JP	Z,H8P_DEVICE		; DEVICE INFO
+	SYSCHKERR(ERR_NOFUNC)
+	RET
+;
+; RESET DSKY -- CLEAR DISPLAY AND KEYPAD FIFO
+;
+H8P_RESET:
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+;  CHECK FOR KEY PRESS, SAVE RAW VALUE, RETURN STATUS
+;
+H8P_STAT:
+	XOR	A			; ZERO KEYS PENDING (FOR NOW)
+	RET
+;
+;  WAIT FOR A DSKY KEYPRESS AND RETURN
+;
+H8P_GETKEY:
+	; PUT KEY VALUE IN REGISTER E
+	XOR	A			; SIGNAL SUCCESS	
+	RET
+;
+; DISPLAY HEX VALUE FROM DE:HL
+;
+H8P_SHOWHEX:
+	LD	BC,DSKY_HEXBUF		; POINT TO HEX BUFFER
+	CALL	ST32			; STORE 32-BIT BINARY THERE
+	LD	HL,DSKY_HEXBUF		; FROM: BINARY VALUE (HL)
+	LD	DE,DSKY_BUF		; TO: SEGMENT BUFFER (DE)
+	CALL	DSKY_BIN2SEG		; CONVERT
+	LD	HL,DSKY_BUF		; POINT TO SEGMENT BUFFER
+	; AND FALL THRU TO DISPLAY IT
+;
+; DISPLAY BYTE VALUES POINTED TO BY DE.  THE INCOMING BYTES ARE IN
+; THE STANDARD ROMWBW SEGMENT ENCODING AND MUST BE TRANSLATED TO THE
+; HEATH ENCODING (SEE ICM.ASM FOR EXAMPLE):
+;
+;
+;	From:		To:
+;	+--01--+	+--02--+
+;	20    02	40    04
+;	+--40--+	+--01--+
+;	10    04	20    08
+;	+--08--+  80	+--10--+  80
+;
+H8P_SHOWSEG:
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; UPDATE KEY LEDS (H8 HAS NONE)
+;
+H8P_KEYLEDS:
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; SET STATUS LEDS BASED ON BITS IN E
+;
+H8P_STATLED:
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; BEEP THE SPEAKER ON THE H8P
+;
+H8P_BEEP:
+	POP	BC
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; DEVICE INFORMATION
+;
+H8P_DEVICE:
+	LD	D,DSKYDEV_H8P		; D := DEVICE TYPE
+	LD	E,0			; E := PHYSICAL DEVICE NUMBER
+	LD	H,0			; H := MODE
+	LD	L,0			; L := BASE I/O ADDRESS
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+;_KEYMAP_TABLE_____________________________________________________________________________________________________________
+;
+H8P_KEYMAP:	; *** NEEDS TO BE UPDATED ***
+	; POS	$00  $01  $02  $03  $04  $05  $06  $07
+	; KEY   [0]  [1]  [2]  [3]  [4]  [5]  [6]  [7]
+	.DB	$0D, $04, $0C, $14, $03, $0B, $13, $02
+;
+	; POS	$08  $09  $0A  $0B  $0C  $0D  $0E  $0F
+	; KEY   [8]  [9]  [A]  [B]  [C]  [D]  [E]  [F]
+	.DB	$0A, $12, $01, $09, $11, $00, $08, $10
+;
+	; POS	$10  $11  $12  $13  $14  $15  $16  $17
+	; KEY   [FW] [BK] [CL] [EN] [DE] [EX] [GO] [BO]
+	.DB	$05, $15, $1D, $1C, $1B, $1A, $19, $18
+
+	; POS	$18  $19  $1A  $1B
+	; KEY   [F4] [F3] [F2] [F1]
+	.DB	$23, $22, $21, $20
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -88,61 +88,49 @@ MODCNT	.SET	MODCNT + 1
 	!!!	; FORCE AN ASSEMBLY ERROR
 #ENDIF
 ;
-; SOME HARDWARE REQUIRES A SPECIFIC ROMSIZE (NOTABLY ZZRCC) OR THE
-; RESULTING BUILD IMAGES WILL BE CORRUPT.  ROMSIZE_CHK IS SPECIFIED
-; IN THE CONFIG FILE AND IS VERIFIED AGAINST THE ROMSIZE BEING USED
-; BY THE BUILD.  A ROMSIZE_CHK VALUE OF 0 INDICATES THE VERIFICATION
-; IS DISABLED (WHICH IT USUALLY IS).
-;
-#IF (ROMSIZE_CHK != 0) & (ROMSIZE != ROMSIZE_CHK)
-	.ECHO	"*** ERROR: ROMSIZE VALUE VERIFICATION FAILURE.\n"
-	.ECHO	"THIS CONFIGURATION REQUIRES A ROMSIZE OF " \ .ECHO ROMSIZE_CHK \ .ECHO ".\n"
-	.ECHO	"BUILD IS USING A ROMSIZE OF " \ .ECHO ROMSIZE \ .ECHO ".\n"
-	.ECHO	"SEE COMMENTS IN HBIOS.ASM.\n"
-	!!!	; FORCE AN ASSEMBLY ERROR
-#ENDIF
-;
 ;
 ;
 #IF (FPLED_ENABLE)
-#DEFINE	DIAG(N)	PUSH AF
-  #DEFCONT \	LD A,N
-;  #DEFCONT \	OUT (DIAGPORT),A
-  #DEFCONT \	CALL	FP_SETLEDS
-  #DEFCONT \	POP AF
+  #DEFINE DIAG(N)	PUSH AF
+  #DEFCONT \		LD A,N
+;  #DEFCONT \		OUT (DIAGPORT),A
+  #DEFCONT \		CALL	FP_SETLEDS
+  #DEFCONT \		POP AF
 #ELSE
-#DEFINE	DIAG(N)	\;
+  #DEFINE		DIAG(N)	\;
 #ENDIF
 ;
 ; SCxxx: LED Port=0x0E, bit 2, inverted, dedicated port
 ; TinyZ80: LED Port=0x6E, bit 0, inverted, dedicated port
 ; Z80-512K: LED Port=0x6E, bit 0, inverted, dedicated port
 ; MBC: LED Port=0x70, bits 1-0, normal, shared w/ RTC port
+; DUO: LED Port=0x94, bits 1-0, normal, shared w/ RTC port
+; S100: LED Port = $0E, bit 2, inverted, dedicated port
 ; 
 #IF (LEDENABLE)
  #IF (LEDMODE == LEDMODE_STD)
-#DEFINE	LED(N)	PUSH	AF
-  #DEFCONT \	LD	A,~N
-  #DEFCONT \	OUT	(LEDPORT),A
-  #DEFCONT \	POP	AF
+    #DEFINE LED(N)	PUSH	AF
+    #DEFCONT \		LD	A,~N
+    #DEFCONT \		OUT	(LEDPORT),A
+    #DEFCONT \		POP	AF
  #ENDIF
  #IF (LEDMODE == LEDMODE_RTC)
-#DEFINE LED(N)	PUSH	AF
-  #DEFCONT \	LD	A,(HB_RTCVAL)
-  #DEFCONT \	AND	%11111100
-  #DEFCONT \	OR	(N & %00000011)
-  #DEFCONT \	LD	(HB_RTCVAL),A
-  #DEFCONT \	OUT	(LEDPORT),A
-  #DEFCONT \	POP	AF
+    #DEFINE LED(N)	PUSH	AF
+    #DEFCONT \		LD	A,(HB_RTCVAL)
+    #DEFCONT \		AND	%11111100
+    #DEFCONT \		OR	(N & %00000011)
+    #DEFCONT \		LD	(HB_RTCVAL),A
+    #DEFCONT \		OUT	(LEDPORT),A
+    #DEFCONT \		POP	AF
  #ENDIF
 #ELSE
-#DEFINE	LED(N)	\;
+  #DEFINE LED(N)	\;
 #ENDIF
 ;
 #DEFINE SYSCHKERR(HB_ERR) \
-  #DEFCONT \	CALL	SYSCHKA
-  #DEFCONT \	LD	A,HB_ERR
-  #DEFCONT \	OR	A
+#DEFCONT \	CALL	SYSCHKA
+#DEFCONT \	LD	A,HB_ERR
+#DEFCONT \	OR	A
 ;
 ;
 ;
@@ -194,7 +182,13 @@ MODCNT	.SET	MODCNT + 1
  #ENDIF
 #ENDIF
 ;
+; CONVERT ROMWBW LOGICAL BANK ID TO PHYSICAL 32K BANK OFFSET
 ;
+#DEFINE PBANK(X) (((X >> 7) * (RAMBIAS / 32)) + (X & $7F))
+;
+; CONVERT ROMWBW LOGICAL BANK ID TO Z280 PHYSICAL BANK (4K) OFFSET
+;
+#DEFINE Z2_BANK(X) (PBANK(X) << 3)
 ;
 ; THE RTCDEF EQUATE IS INITIALIZED HERE AND UPDATED BY DRIVER INCLUDES
 ; THAT SHARE THE RTC LATCH.  AS EACH DRIVER FILE IS INCLUDED, IT CAN
@@ -316,9 +310,9 @@ CB_BIDUSR	.DB	BID_USR
 CB_BIDBIOS	.DB	BID_BIOS
 CB_BIDAUX	.DB	BID_AUX
 CB_BIDRAMD0	.DB	BID_RAMD0
-CB_BIDRAMDN	.DB	BID_RAMDN
+CB_RAMD_BNKS	.DB	RAMD_BNKS
 CB_BIDROMD0	.DB	BID_ROMD0
-CB_BIDROMDN	.DB	BID_ROMDN
+CB_ROMD_BNKS	.DB	ROMD_BNKS
 ;
 	.FILL	(HCB + HCB_SIZ - $),0	; PAD REMAINDER OF HCB
 ;
@@ -465,7 +459,11 @@ HBX_ROM:
 	BIT	7,A			; BIT 7 SET REQUESTS RAM PAGE
 	JR	Z,HBX_ROM		; NOT SET, SELECT ROM PAGE
 	RES	7,A			; RAM PAGE REQUESTED: CLEAR ROM BIT
+  #IF (PLATFORM == PLT_DUO)
+	ADD	A,64			; ADD 64 x 32K - RAM STARTS FROM 2048K
+  #ELSE
 	ADD	A,16			; ADD 16 x 32K - RAM STARTS FROM 512K
+  #ENDIF
 ;
 HBX_ROM:
 	RLCA				; TIMES 2 - GET 16K PAGE INSTEAD OF 32K
@@ -1105,7 +1103,17 @@ Z280_BOOTERR	.TEXT	"\r\n\r\n*** Application mode boot not supported under Z280 n
 ;
 	DI				; NO INTERRUPTS
 	IM	1			; INTERRUPT MODE 1
-
+;
+#IF ((PLATFORM == PLT_DUO) & TRUE)
+	; WAIT A WHILE
+	LD	HL,0
+BOOTWAIT:
+	DEC	HL
+	LD	A,H
+	OR	L
+	JR	NZ,BOOTWAIT
+#ENDIF
+;
 ;#IF ((PLATFORM == PLT_MBC) | (PLATFORM == PLT_SBC))
 	; INITIALIZE RTC LATCH BYTE
 	; FOR SOME PLATFORMS THIS CONTROLS HI/LO SPEED CIRCUIT
@@ -1206,14 +1214,14 @@ Z280_BOOTPDRTBL:
 	.DW	($006 << 4) | $A
 	.DW	($007 << 4) | $A
 	; UPPER 32 K (COMMON)
-	.DW	(((((BID_COM & $7F) * 8) + 0) + (1 << (RAMLOC - 12))) << 4) | $A
-	.DW	(((((BID_COM & $7F) * 8) + 1) + (1 << (RAMLOC - 12))) << 4) | $A
-	.DW	(((((BID_COM & $7F) * 8) + 2) + (1 << (RAMLOC - 12))) << 4) | $A
-	.DW	(((((BID_COM & $7F) * 8) + 3) + (1 << (RAMLOC - 12))) << 4) | $A
-	.DW	(((((BID_COM & $7F) * 8) + 4) + (1 << (RAMLOC - 12))) << 4) | $A
-	.DW	(((((BID_COM & $7F) * 8) + 5) + (1 << (RAMLOC - 12))) << 4) | $A
-	.DW	(((((BID_COM & $7F) * 8) + 6) + (1 << (RAMLOC - 12))) << 4) | $A
-	.DW	(((((BID_COM & $7F) * 8) + 7) + (1 << (RAMLOC - 12))) << 4) | $A
+	.DW	((Z2_BANK(BID_COM) + 0) << 4) | $A
+	.DW	((Z2_BANK(BID_COM) + 1) << 4) | $A
+	.DW	((Z2_BANK(BID_COM) + 2) << 4) | $A
+	.DW	((Z2_BANK(BID_COM) + 3) << 4) | $A
+	.DW	((Z2_BANK(BID_COM) + 4) << 4) | $A
+	.DW	((Z2_BANK(BID_COM) + 5) << 4) | $A
+	.DW	((Z2_BANK(BID_COM) + 6) << 4) | $A
+	.DW	((Z2_BANK(BID_COM) + 7) << 4) | $A
 ;
 Z280_INITZ:
 ;
@@ -1310,7 +1318,13 @@ Z280_INITZ:
 	INC	A
 	OUT	(MPGSEL_1),A
  #ENDIF
-	LD	A,62
+;
+  #IF (PLATFORM == PLT_DUO)
+	LD	A,128 + (RAMSIZE / 16) - 2
+  #ELSE
+	LD	A,64 - 2
+  #ENDIF
+;
 	OUT	(MPGSEL_2),A
 	INC	A
 	OUT	(MPGSEL_3),A
@@ -1413,7 +1427,7 @@ S100MON_SKIP:
 ;
 ; THIS VALUE IS TEMPORARILY STORED AT HBX_LOC - 2
 ; BECAUSE WE ARE CURRENTLY RUNNING IN ROM.  AFTER WE TRANSITION HBIOS
-; TO RAM, THE VALUE IS MOVED TO IT'S REAL LCOATION AT HB_APPBNK.
+; TO RAM, THE VALUE IS MOVED TO IT'S REAL LOCATION AT HB_APPBNK.
 ;
 	LD	A,(HB_CURBNK)		; GET HB_CURBNK
 	LD	(HBX_LOC - 2),A		; ... AND SAVE TEMP FOR APPBNK
@@ -1585,67 +1599,18 @@ MBC_SINGLE:
 ;
 #ENDIF
 ;
-; IF THIS IS A ROM-LESS SYSTEM, THEN WE NEED TO COPY THE PAYLOAD
-; (LOADER, MONITOR, ZSDOS) THAT HAS BEEN LOADED TO PHYSICAL RAM
-; BANKS 0 AND 1 TO THE USER TPA BANK TO RUN AFTER BOOT.
-; IT IS DONE PRIOR TO COPYING HBIOS TO IT'S FINAL BANK BECAUSE
-; THE PAYLOAD MAY EXTEND INTO THE HBIOS OPERATING BANK.  THIS
-; HAPPENS PRIMARILY IN THE CASE WHERE THE
-; SYSTEM HAS THE MINIMUM 128KB OF RAM.
-;
-#IFDEF ROMBOOT
-  #IF (ROMSIZE == 0)
- ; 
-	; THE PAYLOAD IS LIKELY TO CROSS OVER THE RAM BANK 0/1
-	; BOUNDARY.  BNKCPY DOES NOT HANDLE THIS BECAUSE IT ASSUMES
-	; THE COMMON BANK IS USED AFTER PASSING OVER THE BANK
-	; BOUNDARY.  WE WORK AROUND THAT HERE BY DOING TWO COPIES.
-	; THE FIRST ONE HANDLES THE PORTION OF THE PAYLOAD FROM THE
-	; END OF HBIOS TO THE BANK BOUNDARY ($8000).  THE SECOND
-	; ONE HANDLES THE PORTION THAT EXTENDS INTO THE SECOND
-	; PHYSICAL RAM BANK.
-;
-	; COPY PORTION OF PAYLOAD FOLLOWING HBIOS TO THE BANK
-	; BOUNDARY AT $8000 INTO START OF TPA.
-	LD	A,BID_RAM0
-	LD	(HB_SRCBNK),A
-	LD	A,BID_USR
-	LD	(HB_DSTBNK),A
-	LD	HL,HB_END
-	LD	DE,0
-	LD	BC,$8000-HB_END
-;
-    #IF (MEMMGR == MM_Z280)
-	CALL	Z280_BNKCPY
-    #ELSE
-	CALL	HBX_BNKCPY
-    #ENDIF
-;
-	; COPY REMAINDER OF PAYLOAD EXTENDING INTO THE SECOND PHYSICAL
-	; RAM BANK.  NOTE THAT THE DESTINATION ADDRESS (DE) IS
-	; ALREADY CORRECT FROM THE PRIOR COPY.
-	LD	A,BID_RAM0+1
-	LD	(HB_SRCBNK),A
-	LD	HL,$0000
-	; DE IS ALREADY CORRECT
-	LD	BC,$8000-($8000-HB_END)
-;
-    #IF (MEMMGR == MM_Z280)
-	CALL	Z280_BNKCPY
-    #ELSE
-	CALL	HBX_BNKCPY
-    #ENDIF
-;
-  #ENDIF
-;
-#ENDIF
-;
 ; IF ALREADY EXECUTING IN RAM, BYPASS RAM BANK INSTALLATION
 ;
 	LD	A,(HB_RAMFLAG)
 	OR	A
 	JR	NZ,HB_START1
 ;
+; IF BID_BOOT AND BID_BIOS ARE THE SAME, THEN IT IS NEVER APPROPRIATE
+; TO COPY THE HBIOS IMAGE FROM BID_BOOT TO BID_BIOS.  THIS IS TYPICALLY
+; THE CASE FOR A ROMLESS SYSTEM.
+;
+#IF (BID_BOOT != BID_BIOS)
+;
 ; INSTALL HBIOS IN RAM BANK
 ;
 	LD	A,(HB_CURBNK)
@@ -1655,24 +1620,26 @@ MBC_SINGLE:
 	LD	HL,0
 	LD	DE,0
 	LD	BC,$8000
-#IF (MEMMGR == MM_Z280)
+  #IF (MEMMGR == MM_Z280)
 	CALL	Z280_BNKCPY
-#ELSE
+  #ELSE
 	CALL	HBX_BNKCPY
-#ENDIF
+  #ENDIF
 ;
 ; TRANSITION TO HBIOS IN RAM BANK
 ;
-#IF (MEMMGR == MM_Z280)
+  #IF (MEMMGR == MM_Z280)
 	LD	A,BID_BIOS
 	LD	B,$10			; FIRST SYSTEM PDR
 	CALL	Z280_BNKSEL
 	JR	HB_START1
-#ELSE
+  #ELSE
 	LD	A,BID_BIOS		; BIOS BANK ID
 	LD	IX,HB_START1		; EXECUTION RESUMES HERE
 	CALL	HBX_BNKCALL		; CONTINUE IN RAM BANK, DO NOT RETURN
 	HALT				; WE SHOULD NOT COME BACK HERE!
+  #ENDIF
+;
 #ENDIF
 ;
 HB_RAMFLAG	.DB	FALSE		; INITIALLY FALSE, SET TO TRUE BELOW AFTER RAM TRANSITION
@@ -1690,10 +1657,6 @@ HB_START1:				; BNKCALL ARRIVES HERE, BUT NOW RUNNING IN RAM BANK
 	; NOTIFY THAT WE MADE THE TRANSITION!
 	DIAG(DIAG_03)
 	LED(%00000010)
-;
-	; SET THE IN-RAM FLAG
-	LD	A,TRUE			; ACCUM := TRUE
-	LD	(HB_RAMFLAG),A		; SET RAMFLAG
 ;
 	; RECOVER DATA PASSED PRIOR TO RAM TRANSITION
 	; (HBX_LOC - 1) = BATCOND, (HBX_LOC - 2) = APPBNK
@@ -1711,7 +1674,7 @@ HB_START1:				; BNKCALL ARRIVES HERE, BUT NOW RUNNING IN RAM BANK
 	; HL IS TOP 16 BITS OF PHYSICAL ADDRESS OF IVT
 	; IVT *MUST* BE ON A 4K BOUNDARY
 	LD	C,Z280_VPR
-	LD	HL,0 + ((((BID_BIOS & $7F) * 8) + (1 << (RAMLOC - 12))) << 4) + (Z280_IVT >> 8)
+	LD	HL,0 + (((PBANK(BID_BIOS) << 15) + Z280_IVT) >> 8)
 	LDCTL	(C),HL
 #ENDIF
 ;
@@ -1892,6 +1855,14 @@ HB_CPU1:
 	LD	A,L
 	LD	(HB_CPUTYPE),A
 ;
+; CLEAR DISPATCH TABLE ENTRIES
+;
+	XOR	A		; ZERO
+	LD	(CIO_CNT),A	; CIO DEVICES
+	LD	(DIO_CNT),A	; DIO DEVICES
+	LD	(VDA_CNT),A	; VDA DEVICES
+	LD	(SND_CNT),A	; SND DEVICES
+;
 #IF (DSRTCENABLE)
 	CALL	DSRTC_PREINIT
 #ENDIF
@@ -1900,12 +1871,14 @@ HB_CPU1:
  #IF (ICMENABLE)
 	CALL	ICM_PREINIT
  #ENDIF
-#ENDIF
 ;
-#IF (DSKYENABLE)
  #IF (PKDENABLE)
 	CALL	PKD_PREINIT
  #ENDIF
+;
+  #IF (H8PENABLE)
+	CALL	H8P_PREINIT
+  #ENDIF
 #ENDIF
 ;
 #IF (DSKYENABLE)
@@ -2120,11 +2093,40 @@ HB_CPU3:
 	LD	HL,HB_TIMINT
 	CALL	HB_ADDIM1		; ADD TO IM1 CALL LIST
    #ENDIF
-
+;
  #ENDIF
 ;
 #ENDIF
 ;
+; TEMPLATE FOR SETTING UP INTERRUPTS USING THE MBC/DUODYNE IM2 INTERRUPT
+; PIN HEADERS. UPDATE HB_DUMMYx TO POINT TO THE INTERRUPT ROUTINE.
+; IN STD.ASM ALLOCATE THE EQUIVALENT INT_IM2PHx INTERRUPT TABLE ENTRY NUMBER. 
+;
+;
+;	LD	HL,HB_DUMMY0
+;	LD	(IVT(INT_IM2PH0)),HL
+;
+;	LD	HL,HB_DUMMY1
+;	LD	(IVT(INT_IM2PH1)),HL
+;
+;	LD	HL,HB_DUMMY2
+;	LD	(IVT(INT_IM2PH2)),HL
+;
+;	LD	HL,HB_DUMMY3
+;	LD	(IVT(INT_IM2PH3)),HL
+;
+;	LD	HL,HB_DUMMY4
+;	LD	(IVT(INT_IM2PH4)),HL
+;
+;	LD	HL,HB_DUMMY5
+;	LD	(IVT(INT_IM2PH5)),HL
+;
+;	LD	HL,HB_DUMMY6
+;	LD	(IVT(INT_IM2PH6)),HL
+;
+;	LD	HL,HB_DUMMY7
+;	LD	(IVT(INT_IM2PH7)),HL
+;
 #IF (KIOENABLE)
 	CALL	KIO_PREINIT
 #ENDIF
@@ -2668,13 +2670,13 @@ HB_CKBNK:
 	LD	BC,1			; DECREMENT VALUE
 	XOR	A			; ZERO ACCUM
 HB_CKBNK1:
-#IF (MEMMGR == MM_Z280)
+    #IF (MEMMGR == MM_Z280)
 	LD	D,A			; WORKING VALUE TO D
 	LDUD	A,(HL)			; GRAB NEXT BYTE FROM USER SPACE
 	ADD	A,D			; ADD NEXT BYTE
-#ELSE
+    #ELSE
 	ADD	A,(HL)			; ADD NEXT BYTE
-#ENDIF
+    #ENDIF
 	OR	A			; CLEAR CARRY
 	SBC	HL,BC			; DECREMENT
 	JR	NC,HB_CKBNK1		; LOOP TILL DONE
@@ -2772,6 +2774,7 @@ HB_WDZ:
 ;
 	LD	A,(CB_CONDEV)		; GET CURRENT CONSOLE
 	LD	(HB_NEWCON),A		; AND INIT NEW CONSOLE VAR
+;
 #IF CRTACT
 ;
 ; BIOS IS CONFIGURED TO AUTO ACTIVATE CRT DEVICE.  FIRST,
@@ -2789,17 +2792,18 @@ HB_WDZ:
 	BIT	6,A			; BIT 6 HAS CONFIG JUMPER STATE
 	JR	Z,INITSYS3		; Z=SHORTED, BYPASS CONSOLE SWITCH
  #ENDIF
+;
+  #IF (PLATFORM == PLT_S100)
+	IN	A,($75)			; GET IO BYTE
+	AND	%00000001		; ISOLATE CONSOLE BIT
+	JR	NZ,INITSYS3		; NOT SET, BYPASS CONSOLE SWITCH
+  #ENDIF
 ;
 	LD	A,(CB_CRTDEV)		; GET CRT DISPLAY DEVICE
 	LD	(HB_NEWCON),A		; AND QUEUE TO SWITCH
 ;
 #ENDIF
 ;
-; THIS IS A GOOD PLACE TO DETERMINE IF FRONT PANEL HARDWARE REALLY
-; EXISTS.
-;
-	CALL	FP_DETECT
-;
 #IF (FPSW_ENABLE)
 ;
 ; IF WE HAVE FRONT PANEL SWITCHES, THIS IS THE RIGHT PLACE TO HANDLE
@@ -2813,8 +2817,9 @@ HB_WDZ:
 	LD	A,FPSW_IO
 	CALL	PRTHEXBYTE
 ;
-	; THE EXISTENCE OF THE FP WAS TESTED EARLIER.  IF IT DOESN'T
-	; EXIST, BAIL OUT.
+	CALL	FP_DETECT
+;
+	; IF FP DOESN'T EXIST, BAIL OUT.
 	LD	A,(FPSW_ACTIVE)		; GET FP EXISTENCE FLAG
 	OR	A			; SET FLAGS
 	JR	NZ,HB_FP1		; IF WE HAVE ONE, CONTINUE
@@ -3048,11 +3053,7 @@ INITSYS4:
 ; CHAIN TO LOADER
 ;
 #IFDEF ROMBOOT
-  #IF (ROMSIZE > 0)
 	LD	A,BID_IMG0		; CHAIN TO OS IMAGES BANK
-  #ELSE
-	LD	A,BID_USR		; CHAIN TO USER BANK
-  #ENDIF
 #ELSE
 	LD	A,BID_USR		; CHAIN TO USER BANK
 #ENDIF
@@ -3142,6 +3143,9 @@ HB_PCINITTBL:
 #IF (TMSENABLE)
 	.DW	TMS_PREINIT
 #ENDIF
+#IF (SCONENABLE)
+	.DW	SCON_PREINIT
+#ENDIF
 HB_PCINITTBLLEN	.EQU	(($ - HB_PCINITTBL) / 2)

 ;==================================================================================================
@@ -3155,15 +3159,19 @@ HB_INITTBL:
 #IF (CTCENABLE)
 	.DW	CTC_INIT
 #ENDIF
+#IF (PCFENABLE)
+	.DW	PCF_INIT
+#ENDIF
 #IF (DSKYENABLE)
  #IF (ICMENABLE)
 	.DW	ICM_INIT
  #ENDIF
-#ENDIF
-#IF (DSKYENABLE)
  #IF (PKDENABLE)
 	.DW	PKD_INIT
  #ENDIF
+  #IF (H8PENABLE)
+	.DW	H8P_INIT
+  #ENDIF
 #ENDIF
 #IF (AY38910ENABLE)
 	.DW	AY38910_INIT		; AUDIBLE INDICATOR OF BOOT START
@@ -3223,7 +3231,6 @@ HB_INITTBL:
 	.DW	INTRTC_INIT
 #ENDIF
 #IF (DS7RTCENABLE)
-	.DW	PCF8584_INIT
 	.DW	DS7RTC_INIT
 #ENDIF
 #IF (RP5RTCENABLE)
@@ -3244,6 +3251,9 @@ HB_INITTBL:
 #IF (TMSENABLE)
 	.DW	TMS_INIT
 #ENDIF
+#IF (SCONENABLE)
+	.DW	SCON_INIT
+#ENDIF
 #IF (VRCENABLE)
 	.DW	VRC_INIT
 #ENDIF
@@ -3286,6 +3296,12 @@ HB_INITTBL:
 #IF (PPPENABLE)
 	.DW	PPP_INIT
 #ENDIF
+#IF (CHENABLE)
+	.DW	CH_INIT
+#ENDIF
+#IF (ESPENABLE)
+	.DW	ESP_INIT
+#ENDIF
 ;
 HB_INITTBLLEN	.EQU	(($ - HB_INITTBL) / 2)
 ;
@@ -4078,10 +4094,6 @@ SYS_RESINT:
 ; GO BACK TO ROM BOOT LOADER
 ;
 SYS_RESWARM:
-;
-#IF (ROMSIZE == 0)
-	JR	SYS_RESCOLD
-#ENDIF
 ;
 	CALL	SYS_RESINT
 ;
@@ -4100,13 +4112,6 @@ SYS_RESWARM:
 ;
 SYS_RESCOLD:
 ;
-#IF (ROMSIZE == 0)
-	LD	DE,STR_RESTART
-	CALL	Z,WRITESTR
-	DI
-	HALT
-#ENDIF
-;
 #IF (MEMMGR == MM_Z280)
 	JP	Z280_RESTART
 #ELSE
@@ -5111,6 +5116,99 @@ SYS_INTSET1:
 	RET				; DONE
 ;
 ;==================================================================================================
+;   Z280 INTERRUPT VECTOR TABLE
+;==================================================================================================
+;
+#IF (MEMMGR == MM_Z280)
+;
+	; THE Z280 IVT MUST BE ON A 4K BOUNDARY.  IT HAS BEEN LOCATED
+	; HERE IN AN EFFORT TO MINIMIZE WASTED SPACE.  THERE SHOULD BE
+	; A LITTLE LESS THAN 4K OF CODE ABOVE.
+;
+Z280_IVT_SLACK	.EQU	$1000 - ($ & $FFF)
+		.ECHO	"Z280 IVT SLACK occupies "
+		.ECHO	Z280_IVT_SLACK
+		.ECHO	" bytes.\n"
+		;.FILL	$1000 - ($ & $FFF)	; MUST BE 4K ALIGNED!
+		.FILL	Z280_IVT_SLACK		; MUST BE 4K ALIGNED!
+;
+Z280_IVT:
+	.DW	0, 0			; RESERVED
+	.DW	0			; NMI MSR
+	.DW	0			; NMI VECTOR
+	.DW	$0000			; INT A MSR
+	.DW	Z280_BADINT		; INT A VECTOR
+	.DW	$0000			; INT B MSR
+	.DW	Z280_BADINT		; INT B VECTOR
+	.DW	$0000			; INT C MSR
+	.DW	Z280_BADINT		; INT C VECTOR
+	.DW	$0000			; COUNTER/TIMER 0 MSR
+	.DW	Z280_BADINT		; COUNTER/TIMER 0 VECTOR
+	.DW	$0000			; COUNTER/TIMER 1 MSR
+	.DW	Z280_BADINT		; COUNTER/TIMER 1 VECTOR
+	.DW	0, 0			; RESERVED
+	.DW	$0000			; COUNTER/TIMER 2 MSR
+	.DW	Z280_BADINT		; COUNTER/TIMER 2 VECTOR
+	.DW	$0000			; DMA CHANNEL 0 MSR
+	.DW	Z280_BADINT		; DMA CHANNEL 0 VECTOR
+	.DW	$0000			; DMA CHANNEL 1 MSR
+	.DW	Z280_BADINT		; DMA CHANNEL 1 VECTOR
+	.DW	$0000			; DMA CHANNEL 2 MSR
+	.DW	Z280_BADINT		; DMA CHANNEL 2 VECTOR
+	.DW	$0000			; DMA CHANNEL 3 MSR
+	.DW	Z280_BADINT		; DMA CHANNEL 3 VECTOR
+	.DW	$0000			; UART RECEIVER MSR
+	.DW	Z280_BADINT		; UART RECEIVER VECTOR
+	.DW	$0000			; UART TRANSMITTER MSR
+	.DW	Z280_BADINT		; UART TRANSMITTER VECTOR
+	.DW	$0000			; SINGLE STEP TRAP MSR
+	.DW	Z280_SSTEP		; SINGLE STEP TRAP VECTOR
+	.DW	$0000			; BREAK ON HALT TRAP MSR
+	.DW	Z280_BRKHLT		; BREAK ON HALT TRAP VECTOR
+	.DW	$0000			; DIVISION EXCEPTION TRAP MSR
+	.DW	Z280_DIVEXC		; DIVISION EXCEPTION TRAP VECTOR
+	.DW	$0000			; STACK OVERFLOW WARNING TRAP MSR
+	.DW	Z280_STKOVR		; STACK OVERFLOW WARNING TRAP VECTOR
+	.DW	$0000			; ACCESS VIOLATION TRAP MSR
+	.DW	Z280_ACCVIO		; ACCESS VIOLATION TRAP VECTOR
+	.DW	$0000			; SYSTEM CALL TRAP MSR
+	.DW	Z280_SYSCALL		; SYSTEM CALL TRAP VECTOR
+	.DW	$0000			; PRIVILEGED INSTRUCTION TRAP MSR
+	.DW	Z280_PRIVINST		; PRIVILEGED INSTRUCTION TRAP VECTOR
+	.DW	$0000			; EPU <- MEMORY EXTENDED INSTRUCTION TRAP MSR
+	.DW	$0000			; EPU <- MEMORY EXTENDED INSTRUCTION TRAP VECTOR
+	.DW	$0000			; MEMORY <- EPU EXTENDED INSTRUCTION TRAP MSR
+	.DW	$0000			; MEMORY <- EPU EXTENDED INSTRUCTION TRAP VECTOR
+	.DW	$0000			; A <- EPU EXTENDED INSTRUCTION TRAP MSR
+	.DW	$0000			; A <- EPU EXTENDED INSTRUCTION TRAP VECTOR
+	.DW	$0000			; EPU INTERNAL OPERATION EXTENDED INSTRUCTION TRAP MSR
+	.DW	$0000			; EPU INTERNAL OPERATION EXTENDED INSTRUCTION TRAP VECTOR
+	.DW	0, 0			; RESERVED
+	.DW	0, 0			; RESERVED
+	; PROGRAM COUNTER VALUES FOR NMI/INTA (16)
+	.DW	HBX_IV00
+	.DW	HBX_IV01
+	.DW	HBX_IV02
+	.DW	HBX_IV03
+	.DW	HBX_IV04
+	.DW	HBX_IV05
+	.DW	HBX_IV06
+	.DW	HBX_IV07
+	.DW	HBX_IV08
+	.DW	HBX_IV09
+	.DW	HBX_IV0A
+	.DW	HBX_IV0B
+	.DW	HBX_IV0C
+	.DW	HBX_IV0D
+	.DW	HBX_IV0E
+	.DW	HBX_IV0F
+	; THE REMAINDER OF THE Z280 IVT IS TRUNCATED HERE BECAUSE IT
+	; TAKES A BUNCH OF SPACE AND IS NOT USED.  WE SUPPORT ONLY
+	; 16 VECTORED INTERRUPTS AND THEY MUST BE CONNECTED TO INTA.
+;
+#ENDIF
+;
+;==================================================================================================
 ;   GLOBAL HBIOS FUNCTIONS
 ;==================================================================================================
 ;
@@ -5670,94 +5768,6 @@ HB_ALLOC1:
 HB_TMPSZ	.DW	0
 HB_TMPREF	.DW	0
 ;
-;==================================================================================================
-;   Z280 INTERRUPT VECTOR TABLE
-;==================================================================================================
-;
-#IF (MEMMGR == MM_Z280)
-;
-	; THE Z280 IVT MUST BE ON A 4K BOUNDARY.  IT HAS BEEN LOCATED
-	; HERE IN AN EFFORT TO MINIMIZE WASTED SPACE.  THERE SHOULD BE
-	; A LITTLE LESS THAN 4K OF CODE ABOVE.
-;
-	.FILL	$1000 - ($ & $FFF)	; MUST BE 4K ALIGNED!
-;
-Z280_IVT:
-	.DW	0, 0			; RESERVED
-	.DW	0			; NMI MSR
-	.DW	0			; NMI VECTOR
-	.DW	$0000			; INT A MSR
-	.DW	Z280_BADINT		; INT A VECTOR
-	.DW	$0000			; INT B MSR
-	.DW	Z280_BADINT		; INT B VECTOR
-	.DW	$0000			; INT C MSR
-	.DW	Z280_BADINT		; INT C VECTOR
-	.DW	$0000			; COUNTER/TIMER 0 MSR
-	.DW	Z280_BADINT		; COUNTER/TIMER 0 VECTOR
-	.DW	$0000			; COUNTER/TIMER 1 MSR
-	.DW	Z280_BADINT		; COUNTER/TIMER 1 VECTOR
-	.DW	0, 0			; RESERVED
-	.DW	$0000			; COUNTER/TIMER 2 MSR
-	.DW	Z280_BADINT		; COUNTER/TIMER 2 VECTOR
-	.DW	$0000			; DMA CHANNEL 0 MSR
-	.DW	Z280_BADINT		; DMA CHANNEL 0 VECTOR
-	.DW	$0000			; DMA CHANNEL 1 MSR
-	.DW	Z280_BADINT		; DMA CHANNEL 1 VECTOR
-	.DW	$0000			; DMA CHANNEL 2 MSR
-	.DW	Z280_BADINT		; DMA CHANNEL 2 VECTOR
-	.DW	$0000			; DMA CHANNEL 3 MSR
-	.DW	Z280_BADINT		; DMA CHANNEL 3 VECTOR
-	.DW	$0000			; UART RECEIVER MSR
-	.DW	Z280_BADINT		; UART RECEIVER VECTOR
-	.DW	$0000			; UART TRANSMITTER MSR
-	.DW	Z280_BADINT		; UART TRANSMITTER VECTOR
-	.DW	$0000			; SINGLE STEP TRAP MSR
-	.DW	Z280_SSTEP		; SINGLE STEP TRAP VECTOR
-	.DW	$0000			; BREAK ON HALT TRAP MSR
-	.DW	Z280_BRKHLT		; BREAK ON HALT TRAP VECTOR
-	.DW	$0000			; DIVISION EXCEPTION TRAP MSR
-	.DW	Z280_DIVEXC		; DIVISION EXCEPTION TRAP VECTOR
-	.DW	$0000			; STACK OVERFLOW WARNING TRAP MSR
-	.DW	Z280_STKOVR		; STACK OVERFLOW WARNING TRAP VECTOR
-	.DW	$0000			; ACCESS VIOLATION TRAP MSR
-	.DW	Z280_ACCVIO		; ACCESS VIOLATION TRAP VECTOR
-	.DW	$0000			; SYSTEM CALL TRAP MSR
-	.DW	Z280_SYSCALL		; SYSTEM CALL TRAP VECTOR
-	.DW	$0000			; PRIVILEGED INSTRUCTION TRAP MSR
-	.DW	Z280_PRIVINST		; PRIVILEGED INSTRUCTION TRAP VECTOR
-	.DW	$0000			; EPU <- MEMORY EXTENDED INSTRUCTION TRAP MSR
-	.DW	$0000			; EPU <- MEMORY EXTENDED INSTRUCTION TRAP VECTOR
-	.DW	$0000			; MEMORY <- EPU EXTENDED INSTRUCTION TRAP MSR
-	.DW	$0000			; MEMORY <- EPU EXTENDED INSTRUCTION TRAP VECTOR
-	.DW	$0000			; A <- EPU EXTENDED INSTRUCTION TRAP MSR
-	.DW	$0000			; A <- EPU EXTENDED INSTRUCTION TRAP VECTOR
-	.DW	$0000			; EPU INTERNAL OPERATION EXTENDED INSTRUCTION TRAP MSR
-	.DW	$0000			; EPU INTERNAL OPERATION EXTENDED INSTRUCTION TRAP VECTOR
-	.DW	0, 0			; RESERVED
-	.DW	0, 0			; RESERVED
-	; PROGRAM COUNTER VALUES FOR NMI/INTA (16)
-	.DW	HBX_IV00
-	.DW	HBX_IV01
-	.DW	HBX_IV02
-	.DW	HBX_IV03
-	.DW	HBX_IV04
-	.DW	HBX_IV05
-	.DW	HBX_IV06
-	.DW	HBX_IV07
-	.DW	HBX_IV08
-	.DW	HBX_IV09
-	.DW	HBX_IV0A
-	.DW	HBX_IV0B
-	.DW	HBX_IV0C
-	.DW	HBX_IV0D
-	.DW	HBX_IV0E
-	.DW	HBX_IV0F
-	; THE REMAINDER OF THE Z280 IVT IS TRUNCATED HERE BECAUSE IT
-	; TAKES A BUNCH OF SPACE AND IS NOT USED.  WE SUPPORT ONLY
-	; 16 VECTORED INTERRUPTS AND THEY MUST BE CONNECTED TO INTA.
-;
-#ENDIF
-;
 ; Z280 BANK SELECTION (CALLED FROM PROXY)
 ;
 #IF (MEMMGR == MM_Z280)
@@ -5779,7 +5789,7 @@ Z280_BNKSEL:
 	LDCTL	HL,(C)			; GET CURRENT I/O PAGE
 	PUSH	HL			; SAVE IT
 	LD	L,$FF			; NEW I/O PAGE
-	LDCTL	(C),HL
+	LDCTL	(C),HL			; IMPLEMENT
 ;
 	; CONVERT BANK ID TO TOP 12 BITS OF PHYSICAL ADDRESS
 	; WITH $0A IN THE LOW ORDER NIBBLE:
@@ -5790,8 +5800,10 @@ Z280_BNKSEL:
 	MULTU	A,$80			; HL=0R00 0BBB B000 0000
 	BIT	6,H			; RAM BIT SET?
 	JR	Z,Z280_BNKSEL2		; IF NOT, ALL DONE
-	RES	6,H			; OTHERWISE, MOVE RAM BIT
-	SET	RAMLOC-16,H		; HL=0000 RBBB B000 0000
+	RES	6,H			; OTHERWISE, REMOVE RAM BIT
+	LD	A,RAMBIAS >> 6		; RAM OFFSET (TOP 8 BITS)
+	OR	H			; RECOMBINE
+	LD	H,A			; AND PUT BACK IN H
 ;
 Z280_BNKSEL2:
 ;
@@ -6039,10 +6051,12 @@ Z2DMAADR1:
 	; MOVE THE RAM/ROM BIT.
 	; RCBUS DMA HI=0000 RBBB BAAA 1111 LO=1111 AAAA AAAA AAAA
 	; ZZ80MB DMA HI=R000 0BBB BAAA 1111 LO=1111 AAAA AAAA AAAA
-	BIT	6,H
-	JR	Z,Z2DMAADR2
-	RES	6,H
-	SET	RAMLOC-16,H
+	BIT	6,H			; RAM BIT SET?
+	JR	Z,Z2DMAADR2		; IF NOT, ALL DONE
+	RES	6,H			; OTHERWISE, REMOVE RAM BIT
+	LD	A,RAMBIAS >> 6		; RAM OFFSET (TOP 8 BITS)
+	OR	H			; RECOMBINE
+	LD	H,A			; AND PUT BACK IN H
 ;
 Z2DMAADR2:
 	PUSH	HL			; SAVE IT FOR NOW
@@ -6093,9 +6107,7 @@ SIZ_ICM	.EQU	$ - ORG_ICM
 		.ECHO	SIZ_ICM
 		.ECHO	" bytes.\n"
  #ENDIF
-#ENDIF
 ;
-#IF (DSKYENABLE)
  #IF (PKDENABLE)
 ORG_PKD	.EQU	$
  #INCLUDE "pkd.asm"
@@ -6104,6 +6116,15 @@ SIZ_PKD	.EQU	$ - ORG_PKD
 		.ECHO	SIZ_PKD
 		.ECHO	" bytes.\n"
  #ENDIF
+;
+  #IF (H8PENABLE)
+ORG_H8P	.EQU	$
+  #INCLUDE "h8p.asm"
+SIZ_H8P	.EQU	$ - ORG_H8P
+		.ECHO	"H8P occupies "
+		.ECHO	SIZ_H8P
+		.ECHO	" bytes.\n"
+  #ENDIF
 #ENDIF
 ;
 #IF (DSRTCENABLE)
@@ -6132,6 +6153,7 @@ SIZ_BQRTC	.EQU	$ - ORG_BQRTC
 		.ECHO	SIZ_BQRTC
 		.ECHO	" bytes.\n"
 #ENDIF
+;
 #IF (SIMRTCENABLE)
 ORG_SIMRTC	.EQU	$
  #INCLUDE "simrtc.asm"
@@ -6140,15 +6162,16 @@ SIZ_SIMRTC	.EQU	$ - ORG_SIMRTC
 		.ECHO	SIZ_SIMRTC
 		.ECHO	" bytes.\n"
 #ENDIF
-#IF (DS7RTCENABLE & (DS7RTCMODE=DS7RTCMODE_PCF))
-ORG_PCF8584	.EQU	$
-  #INCLUDE "pcf8584.asm"
-SIZ_PCF8584	.EQU	$ - ORG_PCF8584
-		.ECHO	"PCF8584 occupies "
-		.ECHO	SIZ_PCF8584
+;
+#IF (PCFENABLE)
+ORG_PCF		.EQU	$
+  #INCLUDE "pcf.asm"
+SIZ_PCF		.EQU	$ - ORG_PCF
+		.ECHO	"PCF occupies "
+		.ECHO	SIZ_PCF
 		.ECHO	" bytes.\n"
 #ENDIF
-
+;
 #IF (DS7RTCENABLE)
 ORG_DS7RTC	.EQU	$
  #INCLUDE "ds7rtc.asm"
@@ -6295,12 +6318,21 @@ SIZ_VDU		.EQU	$ - ORG_VDU
 #IF (TMSENABLE)
 ORG_TMS		.EQU	$
  #INCLUDE "tms.asm"
-SIZ_TMS		.EQU	$ - ORG_TMS
+SIZ_TMS	.EQU	$ - ORG_TMS
 		.ECHO	"TMS occupies "
 		.ECHO	SIZ_TMS
 		.ECHO	" bytes.\n"
 #ENDIF
 ;
+#IF (SCONENABLE)
+ORG_SCON		.EQU	$
+  #INCLUDE "scon.asm"
+SIZ_SCON	.EQU	$ - ORG_SCON
+		.ECHO	"SCON occupies "
+		.ECHO	SIZ_SCON
+		.ECHO	" bytes.\n"
+#ENDIF
+;
 #IF (GDCENABLE)
 ORG_GDC	.EQU	$
  #INCLUDE "gdc.asm"
@@ -6434,6 +6466,24 @@ SIZ_PPP		.EQU	$ - ORG_PPP
 		.ECHO	" bytes.\n"
 #ENDIF
 ;
+#IF (CHENABLE)
+ORG_CH		.EQU	$
+  #INCLUDE "ch.asm"
+SIZ_CH		.EQU	$ - ORG_CH
+		.ECHO	"CH occupies "
+		.ECHO	SIZ_CH
+		.ECHO	" bytes.\n"
+#ENDIF
+;
+#IF (ESPENABLE)
+ORG_ESP		.EQU	$
+  #INCLUDE "esp.asm"
+SIZ_ESP		.EQU	$ - ORG_ESP
+		.ECHO	"ESP occupies "
+		.ECHO	SIZ_ESP
+		.ECHO	" bytes.\n"
+#ENDIF
+;
 #IF (MDENABLE)
 ORG_MD		.EQU	$
  #INCLUDE "md.asm"
@@ -6895,7 +6945,6 @@ PS_PRTDT:
 	BIT	7,A			; FLOPPY BIT SET?
 	LD	HL,PS_DTFLOP		; ASSUME FLOPPY
 	JP	NZ,PS_PRT18		; IF FLOPPY, JUMP AHEAD
-
 	LD	C,E
 	LD	DE,PS_DTHARD
 	LD	A,00001111B
@@ -7104,7 +7153,7 @@ PS_PRTSC1:
 	RET
 ;
 PS_PRTSC2:
-	PRTS("PropTerm$")		; ASSUME PROPELLER
+	PRTS("Term Module$")
 	CALL	PC_COMMA
 	PRTS("ANSI$")
 	RET
@@ -7192,10 +7241,9 @@ PS_SOUND:
 	LD	E,BF_SNDQ_DEV
 	RST	08
 	PUSH	BC
-	LD	C,B
-	LD	A,11110000B		; TYPE IS IN UPPER NIBBLE
+	LD	A,B
 	LD	DE,PS_SDSN76489
-	CALL	PRTIDXMSK
+	CALL	PRTIDXDEA
 	CALL	PS_PAD18
 	POP	BC
 ;
@@ -7220,9 +7268,8 @@ PS_SOUND:
 ;
 PS_PRTDEV:
 	EX	DE,HL
-	LD	C,H
-	LD	A,11110000B		; TYPE IS IN UPPER NIBBLE
-	CALL	PRTIDXMSK
+	LD	A,H			; TYPE ID
+	CALL	PRTIDXDEA		; PRINT TYPE LABEL
 	LD	A,L			; UNIT NUMBER
 	CALL	PRTDECB			; PRINT NUM, ASSUME 1 CHAR
 	CALL	PC_COLON		; PRINT COLON
@@ -7298,6 +7345,8 @@ PS_DDHDSK	.TEXT	"HDSK$"
 PS_DDPPA	.TEXT	"PPA$"
 PS_DDIMM	.TEXT	"IMM$"
 PS_DDSYQ	.TEXT	"SYQ$"
+PS_DDCHUSB	.TEXT	"CHUSB$"
+PS_DDCHSD	.TEXT	"CHSD$"
 ;
 ; DISK TYPE STRINGS
 ;
@@ -7343,6 +7392,9 @@ PS_SDUF		.TEXT	"UF$"
 PS_SDDUART	.TEXT	"DUART$"
 PS_SDZ2U	.TEXT	"Z2U$"
 PS_SDLPT	.TEXT	"LPT$"
+PS_SDESPCON	.TEXT	"ESPCON$"
+PS_SDESPSER	.TEXT	"ESPSER$"
+PS_SDSCON	.TEXT	"SCON$"
 ;
 ; CHARACTER SUB TYPE STRINGS
 ;
@@ -7687,7 +7739,6 @@ STR_LOWBAT	.DB	"\r\n\r\n+++ LOW BATTERY +++$"
 STR_PANIC	.TEXT	"\r\n>>> PANIC: $"
 STR_SYSCHK	.TEXT	"\r\n>>> SYSCHK: $"
 STR_CONTINUE	.TEXT	"\r\nContinue (Y/N)? $"
-STR_RESTART	.TEXT	"\r\n\r\n>>> Press hardware reset button to restart system\r\n\r\n$"
 ;
 #IF (DSKYENABLE)	;	'H','B','I','O',' ',' ',' ',' '
 MSG_HBVER		.DB	$76,$7F,$30,$3F,$00,$00,$00,$00	; "HBIO    "
--- a/Source/HBIOS/hbios.inc
+++ b/Source/HBIOS/hbios.inc
@@ -152,6 +152,7 @@ PLT_RPH		.EQU	14		; RHYOPHYRE GRAPHICS COMPUTER
 PLT_Z80RETRO	.EQU	15		; Z80 RETRO COMPUTER
 PLT_S100	.EQU	16		; S100 COMPUTERS Z180 SYSTEM
 PLT_DUO		.EQU	17		; DUODYNE Z80 SYSTEM
+PLT_HEATH	.EQU	18		; HEATHKIT H8 Z80 SYSTEM
 ;
 ; HBIOS GLOBAL ERROR RETURN VALUES
 ;
@@ -302,17 +303,20 @@ MID_HDNEW	.EQU	10
 ; CHAR DEVICE IDS
 ;
 CIODEV_UART	.EQU	$00
-CIODEV_ASCI	.EQU	$10
-CIODEV_TERM	.EQU	$20
-CIODEV_PRPCON	.EQU	$30
-CIODEV_PPPCON	.EQU	$40
-CIODEV_SIO	.EQU	$50
-CIODEV_ACIA	.EQU	$60
-CIODEV_PIO	.EQU	$70
-CIODEV_UF	.EQU	$80
-CIODEV_DUART	.EQU	$90
-CIODEV_Z2U	.EQU	$A0
-CIODEV_LPT	.EQU	$B0
+CIODEV_ASCI	.EQU	$01
+CIODEV_TERM	.EQU	$02
+CIODEV_PRPCON	.EQU	$03
+CIODEV_PPPCON	.EQU	$04
+CIODEV_SIO	.EQU	$05
+CIODEV_ACIA	.EQU	$06
+CIODEV_PIO	.EQU	$07
+CIODEV_UF	.EQU	$08
+CIODEV_DUART	.EQU	$09
+CIODEV_Z2U	.EQU	$0A
+CIODEV_LPT	.EQU	$0B
+CIODEV_ESPCON	.EQU	$0C
+CIODEV_ESPSER	.EQU	$0D
+CIODEV_SCON	.EQU	$0E
 ;
 ; SUB TYPES OF CHAR DEVICES
 ;
@@ -324,48 +328,51 @@ CIODEV_LPT	.EQU	$B0
 ; DISK DEVICE IDS
 ;
 DIODEV_MD	.EQU	$00
-DIODEV_FD	.EQU	$10
-DIODEV_RF	.EQU	$20
-DIODEV_IDE	.EQU	$30
-DIODEV_ATAPI	.EQU	$40
-DIODEV_PPIDE	.EQU	$50
-DIODEV_SD	.EQU	$60
-DIODEV_PRPSD	.EQU	$70
-DIODEV_PPPSD	.EQU	$80
-DIODEV_HDSK	.EQU	$90
-DIODEV_PPA	.EQU	$A0
-DIODEV_IMM	.EQU	$B0
-DIODEV_SYQ	.EQU	$C0
+DIODEV_FD	.EQU	$01
+DIODEV_RF	.EQU	$02
+DIODEV_IDE	.EQU	$03
+DIODEV_ATAPI	.EQU	$04
+DIODEV_PPIDE	.EQU	$05
+DIODEV_SD	.EQU	$06
+DIODEV_PRPSD	.EQU	$07
+DIODEV_PPPSD	.EQU	$08
+DIODEV_HDSK	.EQU	$09
+DIODEV_PPA	.EQU	$0A
+DIODEV_IMM	.EQU	$0B
+DIODEV_SYQ	.EQU	$0C
+DIODEV_CHUSB	.EQU	$0D
+DIODEV_CHSD	.EQU	$0E
 ;
 ; RTC DEVICE IDS
 ;
 RTCDEV_DS	.EQU	$00		; DS1302
-RTCDEV_BQ	.EQU	$10		; BQ4845P
-RTCDEV_SIMH	.EQU	$20		; SIMH
-RTCDEV_INT	.EQU	$30		; PERIODIC INT TIMER
-RTCDEV_DS7	.EQU	$40		; DS1307 (I2C)
-RTCDEV_RP5	.EQU	$50		; RP5C01
+RTCDEV_BQ	.EQU	$01		; BQ4845P
+RTCDEV_SIMH	.EQU	$02		; SIMH
+RTCDEV_INT	.EQU	$03		; PERIODIC INT TIMER
+RTCDEV_DS7	.EQU	$04		; DS1307 (I2C)
+RTCDEV_RP5	.EQU	$05		; RP5C01
 ;
 ; DSKY DEVICE IDS
 ;
 DSKYDEV_ICM	.EQU	$00		; Intersil ICM7218
-DSKYDEV_PKD	.EQU	$10		; Intel P8279
+DSKYDEV_PKD	.EQU	$01		; Intel P8279
+DSKYDEV_H8P	.EQU	$02		; Heath H8 Panel
 ;
 ; VIDEO DEVICE IDS
 ;
 VDADEV_VDU	.EQU	$00		; ECB VDU - MOTOROLA 6545
-VDADEV_CVDU	.EQU	$10		; ECB COLOR VDU - MOS 8563
-VDADEV_GDC	.EQU	$20		; GRAPHICS DISPLAY CTLR - UPD7220
-VDADEV_TMS	.EQU	$30		; N8 ONBOARD VDA SUBSYSTEM - TMS 9918
-VDADEV_VGA	.EQU	$40		; ECB VGA3 - HITACHI HD6445
-VDADEV_VRC	.EQU	$50		; VGARC
+VDADEV_CVDU	.EQU	$01		; ECB COLOR VDU - MOS 8563
+VDADEV_GDC	.EQU	$02		; GRAPHICS DISPLAY CTLR - UPD7220
+VDADEV_TMS	.EQU	$03		; N8 ONBOARD VDA SUBSYSTEM - TMS 9918
+VDADEV_VGA	.EQU	$04		; ECB VGA3 - HITACHI HD6445
+VDADEV_VRC	.EQU	$05		; VGARC
 ;
 ; SOUND DEVICE IDS
 ;
 SNDDEV_SN76489	.EQU	$00
-SNDDEV_AY38910	.EQU	$10
-SNDDEV_BITMODE	.EQU	$20
-SNDDEV_YM2612	.EQU	$30
+SNDDEV_AY38910	.EQU	$01
+SNDDEV_BITMODE	.EQU	$02
+SNDDEV_YM2612	.EQU	$03
 ;
 ; DSKY KEYS
 ;
@@ -428,9 +435,9 @@ HCB_BIDUSR	.EQU	$D9		; USER BANK (TPA)
 HCB_BIDBIOS	.EQU	$DA		; BIOS BANK (HBIOS, UBIOS)
 HCB_BIDAUX	.EQU	$DB		; AUX BANK (BPBIOS)
 HCB_BIDRAMD0	.EQU	$DC		; FIRST BANK OF RAM DRIVE
-HCB_BIDRAMDN	.EQU	$DD		; LAST BANK OF RAM DRIVE
+HCB_RAMD_BNKS	.EQU	$DD		; RAM DRIVE BANK COUNT
 HCB_BIDROMD0	.EQU	$DE		; FIRST BANK OF ROM DRIVE
-HCB_BIDROMDN	.EQU	$DF		; LAST BANK OF ROM DRIVE
+HCB_ROMD_BNKS	.EQU	$DF		; ROM DRIVE BANK COUNT
 ;
 ; HBIOS PROXY COMMON DATA BLOCK
 ; EXACTLY 32 BYTES AT $FFE0-$FFFF
--- a/Source/HBIOS/hbios_env.asm
+++ b/Source/HBIOS/hbios_env.asm
@@ -24,7 +24,11 @@
 ;
 ; Print all desired config values...
 ;
+#if (ROMSIZE > 0)
 	prtval("ROMSIZE$", ROMSIZE)
+#else
+	prtval("ROMSIZE$", RAMSIZE)
+#endif
 	prtval("CPUFAM$", CPUFAM)
 ;
 	ret
--- a/Source/HBIOS/md.asm
+++ b/Source/HBIOS/md.asm
@@ -72,32 +72,30 @@ MD_INIT:
 ;
 #IF (MDROM)
 	PRTS(" ROMDISK=$")
-;	LD	HL,ROMSIZE - 128
-	LD	A,(HCB + HCB_ROMBANKS)	; GET NUMBER OF BANKS
-	SUB	(TOT_ROM_RB)
-	LD	L,A
-	LD	H,0			; CALCULATE RAM SIZE
+	LD	A,(CB_ROMD_BNKS)	; ROM DISK SIZE IN BANKS
+	LD	L,A			; PUT IN L
+	LD	H,0			; CALCULATE ROM DISK SIZE
 	ADD	HL,HL			; X2
 	ADD	HL,HL			; X4
 	ADD	HL,HL			; X8
 	ADD	HL,HL			; X16
 	ADD	HL,HL			; X32
+	LD	(MD_ROMDSIZE),HL	; SAVE ROM DISK SIZE
 	CALL	PRTDEC
 	PRTS("KB$")
 #ENDIF
 ;
 #IF (MDRAM)
 	PRTS(" RAMDISK=$")
-;	LD	HL,RAMSIZE - 256
-	LD	A,(HCB + HCB_RAMBANKS)	; GET NUMBER OF BANKS
-	SUB	(TOT_RAM_RB)		; LESS RESERVED BANKS
-	LD	L,A
-	LD	H,0			; CALCULATE RAM SIZE
+	LD	A,(CB_RAMD_BNKS)	; RAM DISK SIZE IN BANKS
+	LD	L,A			; PUT IN L
+	LD	H,0			; CALCULATE RAM DISK SIZE
 	ADD	HL,HL			; X2
 	ADD	HL,HL			; X4
 	ADD	HL,HL			; X8
 	ADD	HL,HL			; X16
 	ADD	HL,HL			; X32
+	LD	(MD_RAMDSIZE),HL	; SAVE RAM DISK SIZE
 	CALL	PRTDEC
 	PRTS("KB$")
 #ENDIF
@@ -183,21 +181,18 @@ MD_CAP:					; ASSUMES THAT UNIT 0 IS RAM, UNIT 1 IS ROM
 	SYSCHKERR(ERR_NOUNIT)		; INVALID UNIT
 	RET
 MD_CAP0:
-	LD	A,(HCB + HCB_RAMBANKS)	; POINT TO RAM BANK COUNT
-	LD	B,TOT_RAM_RB		; SET # RESERVED RAM BANKS
-	JR	MD_CAP2
+	; RAM DISK SIZE
+	LD	HL,(MD_RAMDSIZE)	; SIZE IN KB
+	JR	MD_CAP2			; CONTINUE
 MD_CAP1:
-	LD	A,(HCB + HCB_ROMBANKS)	; POINT TO ROM BANK COUNT
-	LD	B,TOT_ROM_RB		; SET # RESERVED ROM BANKS
+	; ROM DISK SIZE
+	LD	HL,(MD_ROMDSIZE)	; SIZE IN KB
 MD_CAP2:
-	SUB	B			; SUBTRACT OUT RESERVED BANKS
-	LD	H,A			; H := # BANKS
-	LD	E,64			; # 512 BYTE BLOCKS / BANK
-	CALL	MULT8			; HL := TOTAL # 512 BYTE BLOCKS
-	LD	DE,0			; NEVER EXCEEDS 64K, ZERO HIGH WORD
+	ADD	HL,HL			; CONVERT TO BLOCK COUNT
+	LD	DE,0			; FILL IN HIGH WORD
 	LD	BC,512			; 512 BYTE SECTOR
-	XOR	A
-	RET
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
 ;
 ;
 ;
@@ -1032,6 +1027,8 @@ MD_FFSEN	.DB	00h		; FLASH FILES SYSTEM ENABLE
 ;
 #ENDIF
 ;
+MD_ROMDSIZE	.DW	0
+MD_RAMDSIZE	.DW	0
 MD_RWFNADR	.DW	0
 MD_DSKBUF	.DW	0
 MD_SRCBNK	.DB	0
--- a/Source/HBIOS/pcf8584.asm
+++ b/Source/HBIOS/pcf8584.asm
@@ -2,12 +2,11 @@
 ; PCF8584 I2C CLOCK DRIVER
 ;==================================================================================================
 ;
-PCF_BASE  	.EQU  0F0H
+PCF_BASE  	.EQU  PCFBASE
 PCF_ID   	.EQU  0AAH
-CPU_CLK	  	.EQU  12
-
+;
 PCF_RS0		.EQU  PCF_BASE
-PCF_RS1		.EQU  PCF_RS0+1
+PCF_RS1		.EQU  PCF_BASE+1
 PCF_OWN	 	.EQU  (PCF_ID >> 1)	 	; PCF'S ADDRESS IN SLAVE MODE
 ;
 ;T4LC512D	.EQU	10100000B		; DEVICE IDENTIFIER
@@ -37,10 +36,10 @@ PCF_STA  	.EQU  00000100B
 PCF_STO  	.EQU  00000010B
 PCF_ACK  	.EQU  00000001B
 ;
-PCF_START_		.EQU  (PCF_PIN | PCF_ES0 | PCF_STA | PCF_ACK)
-PCF_STOP_		.EQU  (PCF_PIN | PCF_ES0 | PCF_STO | PCF_ACK)
-PCF_REPSTART_ 	.EQU  (	   PCF_ES0 | PCF_STA | PCF_ACK)
-PCF_IDLE_		.EQU  (PCF_PIN | PCF_ES0		| PCF_ACK)
+PCF_START_	.EQU  (PCF_PIN | PCF_ES0 | PCF_STA | PCF_ACK)
+PCF_STOP_	.EQU  (PCF_PIN | PCF_ES0 | PCF_STO | PCF_ACK)
+PCF_REPSTART_ 	.EQU  (PCF_ES0 | PCF_STA | PCF_ACK)
+PCF_IDLE_	.EQU  (PCF_PIN | PCF_ES0 | PCF_ACK)
 ;
 ; STATUS REGISTER BITS
 ;
@@ -54,43 +53,6 @@ PCF_AAS   	.EQU  00000100B
 PCF_LAB   	.EQU  00000010B
 PCF_BB		.EQU  00000001B
 ;
-; CLOCK CHIP FREQUENCIES
-;
-PCF_CLK3   	.EQU	000H
-PCF_CLK443 	.EQU	010H
-PCF_CLK6   	.EQU	014H
-PCF_CLK8   	.EQU	018H
-PCF_CLK12  	.EQU	01cH
-;
-; TRANSMISSION FREQUENCIES
-;
-PCF_TRNS90 	.EQU	000H	;  90 kHz */
-PCF_TRNS45 	.EQU	001H	;  45 kHz */
-PCF_TRNS11 	.EQU	002H	;  11 kHz */
-PCF_TRNS15 	.EQU	003H	; 1.5 kHz */
-;
-; TIMEOUT AND DELAY VALUES (ARBITRARY)
-;
-PCF_PINTO	.EQU	65000
-PCF_ACKTO	.EQU	65000
-PCF_BBTO	.EQU	65000
-PCF_LABDLY	.EQU	65000
-;
-; DATA PORT REGISTERS
-;
-#IF (CPU_CLK = 443)
-PCF_CLK .EQU PCF_CLK4433
-#ELSE 
- #IF (CPU_CLK = 8)
-PCF_CLK .EQU PCF_CLK8
- #ELSE 
-  #IF (CPU_CLK = 12)
-PCF_CLK .EQU PCF_CLK12
-  #ELSE ***ERROR
-  #ENDIF
- #ENDIF	
-#ENDIF
-;
 ; THE PCF8584 TARGETS A TOP I2C CLOCK SPEED OF 90KHZ AND SUPPORTS DIVIDERS FOR 
 ; 3, 4.43, 6, 8 AND 12MHZ TO ACHEIVE THIS.
 ;
@@ -104,14 +66,44 @@ PCF_CLK .EQU PCF_CLK12
 ; |  12MHz  |       |        |       |         |        | 90Khz | 120Khz |   138Khz  |  150Khz |
 ; +----------------------------------------------------------------------------------+---------+
 ;
-PCF8584_INIT:
+; CLOCK CHIP FREQUENCIES
+;
+PCF_CLK3   	.EQU	000H
+PCF_CLK443 	.EQU	010H
+PCF_CLK6   	.EQU	014H
+PCF_CLK8   	.EQU	018H
+PCF_CLK12  	.EQU	01CH
+;
+; TRANSMISSION FREQUENCIES
+;
+PCF_TRNS90 	.EQU	000H	;  90 kHz */
+PCF_TRNS45 	.EQU	001H	;  45 kHz */
+PCF_TRNS11 	.EQU	002H	;  11 kHz */
+PCF_TRNS15 	.EQU	003H	; 1.5 kHz */
+;
+; BELOW VARIABLES CONTROL PCF CLOCK DIVISOR PROGRAMMING
+; HARD-CODED FOR NOW
+;
+PCF_CLK	  	.EQU	PCF_CLK12
+PCF_TRNS	.EQU	PCF_TRNS90
+;
+; TIMEOUT AND DELAY VALUES (ARBITRARY)
+;
+PCF_PINTO	.EQU	65000
+PCF_ACKTO	.EQU	65000
+PCF_BBTO	.EQU	65000
+PCF_LABDLY	.EQU	65000
+;
+; DATA PORT REGISTERS
+;
+PCF_INIT:
 	CALL	NEWLINE				; Formatting
-	PRTS("I2C: IO=0x$")
+	PRTS("PCF: IO=0x$")
 	LD	A, PCF_BASE
 	CALL	PRTHEXBYTE
 	CALL	PC_SPACE
-	CALL	PCF_INIT
-	CALL	NEWLINE
+	CALL	PCF_INITDEV
+	;CALL	NEWLINE
 	RET
 ;
 ; LINUX DRIVER BASED CODE
@@ -141,11 +133,13 @@ PCF_STOP:
 ;
 ;-----------------------------------------------------------------------------
 ;
-PCF_INIT:
+PCF_INITDEV:
 	LD	A,PCF_PIN   	; S1=80H: S0 SELECTED, SERIAL 
 	OUT	(PCF_RS1),A	; INTERFACE OFF
 	NOP
 	IN	A,(PCF_RS1)	; CHECK TO SEE S1 NOW USED AS R/W
+	;CALL	PC_SPACE
+	;CALL	PRTHEXBYTE
 	AND	07FH	  	; CTRL. PCF8584 DOES THAT WHEN ESO
 	JR	NZ,PCF_FAIL	; IS ZERO
 ;
@@ -153,6 +147,8 @@ PCF_INIT:
 	OUT	(PCF_RS0),A	; EFFECTIVE ADDRESS IS (OWN <<1)
 	NOP
 	IN	A,(PCF_RS0)	; CHECK IT IS REALLY WRITTEN
+	;CALL	PC_SPACE
+	;CALL	PRTHEXBYTE
 	CP	PCF_OWN
 	JP	NZ,PCF_SETERR
 ;
@@ -160,14 +156,18 @@ PCF_INIT:
 	OUT	(PCF_RS1),A		; NEXT BYTE IN S2
 	NOP
 	IN	A,(PCF_RS1)
+	;CALL	PC_SPACE
+	;CALL	PRTHEXBYTE
 	AND	07FH
 	CP	PCF_ES1
 	JP	NZ,PCF_REGERR
 ;
-	LD	A,PCF_CLK	; LOAD CLOCK REGISTER S2
+	LD	A,PCF_CLK | PCF_TRNS	; LOAD CLOCK REGISTER S2
 	OUT	(PCF_RS0),A
 	NOP
 	IN	A,(PCF_RS0)	; CHECK IT'S REALLY WRITTEN, ONLY
+	;CALL	PC_SPACE
+	;CALL	PRTHEXBYTE
 	AND	1FH	   	; THE LOWER 5 BITS MATTER
 	CP	PCF_CLK
 	JP	NZ,PCF_CLKERR
@@ -176,6 +176,8 @@ PCF_INIT:
 	OUT	(PCF_RS1),A  
 	NOP
 	IN	A,(PCF_RS1)  
+	;CALL	PC_SPACE
+	;CALL	PRTHEXBYTE
 	CP	+(PCF_PIN | PCF_BB)
 	JP	NZ,PCF_IDLERR
 ;
@@ -381,12 +383,12 @@ PCF_READI2C:
 ;
 ; POLL THE BUS BUSY BIT TO DETERMINE IF BUS IS FREE.
 ; RETURN WITH A=00H/Z STATUS IF BUS IS FREE
-; RETURN WITH A=FFH/NZ STATUS IF BUS
+; RETURN WITH A=FFH/NZ STATUS IF BUS IS BUSY
 ;
 ; AFTER RESET THE BUS BUSY BIT WILL BE SET TO 1 I.E. NOT BUSY
 ;
 PCF_WAIT_FOR_BB:
-	 LD	HL,PCF_BBTO
+	LD	HL,PCF_BBTO
 PCF_WFBB0:
 	IN	A,(PCF_RS1)
 	AND	PCF_BB
--- a/Source/HBIOS/pkd.asm
+++ b/Source/HBIOS/pkd.asm
@@ -371,7 +371,6 @@ PKD_KEYMAP:
 	; POS	$18  $19  $1A  $1B
 	; KEY   [F4] [F3] [F2] [F1]
 	.DB	$23, $22, $21, $20
-
 ;
 ;==================================================================================================
 ; PKD OUTPUT ROUTINES
--- a/Source/HBIOS/ppp.asm
+++ b/Source/HBIOS/ppp.asm
@@ -4,7 +4,6 @@
 ;==================================================================================================
 ;
 ; TODO:
-;   1) ADD SUPPORT FOR DSKY
 ;
 PPP_IO		.EQU	PPPBASE + 0	; PPP DATA I/O (PPI PORT A)
 PPP_CTL		.EQU	PPPBASE + 2	; PPP CTL LINES (PPI PORT C)
@@ -689,7 +688,7 @@ PPPSD_RESET:
 PPPSD_DEVICE:
 	LD	D,DIODEV_PPPSD		; D := DEVICE TYPE
 	LD	E,(IY+PPPSD_DEV)	; E := PHYSICAL DEVICE NUMBER
-	LD	C,%01110010		; C := ATTRIBUTES, REMOVABLE, SD CARD
+	LD	C,%00110010		; C := ATTRIBUTES, REMOVABLE, SD CARD
 	LD	H,0			; H := 0, DRIVER HAS NO MODES
 	LD	L,PPPBASE		; L := BASE I/O ADDRESS
 	XOR	A			; SIGNAL SUCCESS
--- a/Source/HBIOS/prp.asm
+++ b/Source/HBIOS/prp.asm
@@ -4,7 +4,6 @@
 ;==================================================================================================
 ;
 ; TODO:
-;   1) ADD SUPPORT FOR DSKY
 ;
 PRP_IOBASE	.EQU	$A8
 ;
@@ -546,7 +545,7 @@ PRPSD_RESET:
 PRPSD_DEVICE:
 	LD	D,DIODEV_PRPSD		; D := DEVICE TYPE
 	LD	E,(IY+PRPSD_DEV)	; E := PHYSICAL DEVICE NUMBER
-	LD	C,%01110010		; C := ATTRIBUTES, REMOVABLE, SD CARD
+	LD	C,%00110010		; C := ATTRIBUTES, REMOVABLE, SD CARD
 	LD	H,0			; H := 0, DRIVER HAS NO MODES
 	LD	L,PRP_IOBASE		; L := BASE I/O ADDRESS
 	XOR	A			; SIGNAL SUCCESS
--- a/Source/HBIOS/romldr.asm
+++ b/Source/HBIOS/romldr.asm
@@ -140,7 +140,8 @@ start:
 	rst	08			; do it
 	ld	a,c			; previous bank to A
 	ld	(bid_ldr),a		; save previous bank for later
-	bit	7,a			; starting from ROM?
+	;;;bit	7,a			; starting from ROM?
+	cp	BID_IMG0		; ROM startup?
 #endif
 ;
 #if (BIOS == BIOS_UNA)
@@ -1343,6 +1344,36 @@ diskread:
 ;
 #endif
 ;
+; Built-in mini-loader for S100 Monitor.  The S100 platform build
+; imbeds the S100 Monitor in the ROM at the start of bank 3 (BID_IMG2).
+; This bit of code just launches the monitor directly from that bank.
+;
+#if (BIOS == BIOS_WBW)
+  #if (PLATFORM == PLT_S100)
+;
+s100mon:
+	; Warn user that console is being directed to the S100 bus
+	; if the IOBYTE bit 0 is 0 (%xxxxxxx0).
+	in	a,($75)			; get IO byte
+	and	%00000001		; isolate console bit
+	jr	nz,s100mon1		; if 0, bypass msg
+	ld	hl,str_s100con		; console msg string
+	call	pstr			; display it
+;
+s100mon1:
+	; Launch S100 Monitor from ROM Bank 3
+	call	ldelay			; wait for UART buf to empty
+	di				; suspend interrupts
+	ld	a,BID_IMG2		; S100 monitor bank
+	ld	ix,0			; execution resumes here
+	jp	HB_BNKCALL		; do it
+;
+str_smon	.db	"S100 Z180 Monitor",0
+str_s100con	.db	"\r\n\r\nConsole on S100 Bus",0
+;
+  #endif
+#endif
+;
 ;=======================================================================
 ; Utility functions
 ;=======================================================================
@@ -2159,7 +2190,9 @@ err:
 	ld	hl,str_err_prefix
 	call	pstr
 	pop	hl
-	jp	pstr
+	call	pstr
+	or	$ff			; signal error
+	ret				; done
 ;
 str_err_prefix	.db	bel,"\r\n\r\n*** ",0
 str_err_invcmd	.db	"Invalid command",0
@@ -2311,6 +2344,11 @@ ra_tbl:
 ;      ---------  -------  -----  --------  -----        -------  -------  ----------
 ra_ent(str_mon,	  'M',	   KY_CL, BID_IMG0, MON_IMGLOC,  MON_LOC, MON_SIZ, MON_SERIAL)
 ra_entsiz	.equ	$ - ra_tbl
+#if (BIOS == BIOS_WBW)
+  #if (PLATFORM == PLT_S100)
+ra_ent(str_smon,  'S',	   $FF,	  bid_cur , $8000,       $8000,   $0001,   s100mon)
+  #endif
+#endif
 ra_ent(str_zsys,  'Z',	   KY_FW, BID_IMG0, ZSYS_IMGLOC, CPM_LOC, CPM_SIZ, CPM_ENT)
 ra_ent(str_cpm22, 'C',	   KY_BK, BID_IMG0, CPM_IMGLOC,  CPM_LOC, CPM_SIZ, CPM_ENT)
 #if (BIOS == BIOS_WBW)
@@ -2333,7 +2371,7 @@ ra_tbl_app:
 ;      Name	  Key	   Dsky	  Bank	    Src	         Dest	    Size     Entry
 ;      ---------  -------  -----  --------  -----       -------  -------  ----------
 ra_ent(str_mon,	  'M',	   KY_CL, bid_cur,  MON_IMGLOC,  MON_LOC, MON_SIZ, MON_SERIAL)
-ra_ent(str_zsys,  'Z',	   KY_FW, bid_cur,  ZSYS_IMGLOC,  CPM_LOC, CPM_SIZ, CPM_ENT)
+ra_ent(str_zsys,  'Z',	   KY_FW, bid_cur,  ZSYS_IMGLOC, CPM_LOC, CPM_SIZ, CPM_ENT)
 #if (DSKYENABLE)
 ra_ent(str_dsky,  'Y'+$80, KY_GO, bid_cur,  MON_IMGLOC,  MON_LOC, MON_SIZ, MON_DSKY)
 #endif
--- a/Source/HBIOS/s100mon.z80
+++ b/Source/HBIOS/s100mon.z80
--- a/Source/HBIOS/scon.asm
+++ b/Source/HBIOS/scon.asm
@@ -0,0 +1,126 @@
+;
+;==================================================================================================
+; S100 PROPELLER CONSOLE DRIVER
+;==================================================================================================
+;
+; TODO:
+;
+SCON_IOBASE	.EQU	$00
+;
+SCON_STATUS	.EQU	SCON_IOBASE
+SCON_DATA	.EQU	SCON_IOBASE + 1
+;
+SCON_KBDRDY	.EQU	%00000010
+SCON_DSPRDY	.EQU	%00000100
+;
+SCON_COLS	.EQU	80
+SCON_ROWS	.EQU	40
+;
+;
+;
+SCON_PREINIT:
+	XOR	A
+	RET
+;
+;
+;
+SCON_INIT:
+	CALL	NEWLINE
+	PRTS("SCON:$")
+;
+	; DISPLAY CONSOLE DIMENSIONS
+	CALL	PC_SPACE
+	LD	A,SCON_COLS
+	CALL	PRTDECB
+	LD	A,'X'
+	CALL	COUT
+	LD	A,SCON_ROWS
+	CALL	PRTDECB
+	CALL	PRTSTRD
+	.TEXT	" TEXT (ANSI)$"
+;
+; ADD OURSELVES TO CIO DISPATCH TABLE
+;
+	LD	D,0			; PHYSICAL UNIT IS ZERO
+	LD	E,CIODEV_SCON		; DEVICE TYPE
+	LD	BC,SCON_FNTBL		; BC := FUNCTION TABLE ADDRESS
+	CALL	CIO_ADDENT		; ADD ENTRY, A := UNIT ASSIGNED
+	LD	(HCB + HCB_CRTDEV),A	; SET OURSELVES AS THE CRT DEVICE
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; DRIVER FUNCTION TABLE
+;
+SCON_FNTBL:
+	.DW	SCON_IN
+	.DW	SCON_OUT
+	.DW	SCON_IST
+	.DW	SCON_OST
+	.DW	SCON_INITDEV
+	.DW	SCON_QUERY
+	.DW	SCON_DEVICE
+#IF (($ - SCON_FNTBL) != (CIO_FNCNT * 2))
+	.ECHO	"*** INVALID SCON FUNCTION TABLE ***\n"
+#ENDIF
+;
+;
+;
+SCON_IN:
+	CALL	SCON_IST		; CHECK FOR CHAR PENDING
+	JR	Z,SCON_IN		; WAIT FOR IT IF NECESSARY
+	IN0	A,(SCON_DATA)		; READ THE CHAR FROM PROPIO
+	LD	E,A
+	RET
+;
+;
+;
+SCON_IST:
+	IN0	A,(SCON_STATUS)		; READ LINE STATUS REGISTER
+	AND	SCON_KBDRDY		; ISOLATE KBDRDY
+	JP	Z,CIO_IDLE		; RETURN VIA IDLE PROCESSING
+	OR	$FF			; SET A=$FF TO SIGNAL READY
+	RET				; RETURN
+;
+;
+;
+SCON_OUT:
+	CALL	SCON_OST		; CHECK FOR OUTPUT READY
+	JR	Z,SCON_OUT		; WAIT IF NECESSARY
+	LD	A,E			; RECOVER THE CHAR TO WRITE
+	OUT0	(SCON_DATA),A		; WRITE THE CHAR TO PROPIO
+	RET
+;
+;
+;
+SCON_OST:
+	IN0	A,(SCON_STATUS)		; READ LINE STATUS REGISTER
+	AND	SCON_DSPRDY 		; ISOLATE DSPRDY
+	JP	Z,CIO_IDLE		; RETURN VIA IDLE PROCESSING
+	OR	$FF			; SET A=$FF TO SIGNAL READY
+	RET				; RETURN
+;
+;
+;
+SCON_INITDEV:
+	SYSCHKERR(ERR_NOTIMPL)
+	RET
+;
+;
+;
+SCON_QUERY:
+	LD	DE,0
+	LD	HL,0
+	XOR	A
+	RET
+;
+;
+;
+SCON_DEVICE:
+	LD	D,CIODEV_SCON		; D := DEVICE TYPE
+	LD	E,0			; E := DEVICE NUM, ALWAYS 0
+	LD	C,$BF			; C := DEVICE TYPE, 0xBF IS PROP TERM
+	LD	H,0			; H := 0, DRIVER HAS NO MODES
+	LD	L,SCON_IOBASE		; L := BASE I/O ADDRESS
+	XOR	A			; SIGNAL SUCCESS
+	RET
--- a/Source/HBIOS/sd.asm
+++ b/Source/HBIOS/sd.asm
@@ -9,14 +9,14 @@
 ;	- TEST XC CARD TYPE DETECTION
 ;	- TRY TO GET INIT TO FAIL, REMOVE DELAYS AT START OF GOIDLE?
 ;
-;----------------------------------------------------------------------------------------------
-; SD Signal	Active	JUHA	N8	CSIO	PPI	UART	DSD	MK4	SC	MT
-; ------------	------- ------- ------- ------- ------- ------- ------- -------	-------	-------
-; CS (DAT3)	LO ->	RTC:2	RTC:2	RTC:2	~PC:4	~MCR:3	OPR:2	SD:2	~RTC:2/3OPR:4/5
-; CLK		HI ->	RTC:1	RTC:1	CSIO	PC:1	~MCR:2	OPR:1	CSIO	CSIO	SPI
-; DI (CMD)	HI ->	RTC:0	RTC:0	CSIO	PC:0	~MCR:0	OPR:0	CSIO	CSIO	SPI
-; DO (DAT0)	HI ->	RTC:7	RTC:6	CSIO	PB:7	~MSR:5	OPR:0	CSIO	CSIO	SPI
-;----------------------------------------------------------------------------------------------
+;-----------------------------------------------------------------------------------------------------
+; SD Signal	Active	JUHA	N8	CSIO	PPI	UART	DSD	MK4	SC	MT     PIO
+; ------------	------- ------- ------- ------- ------- ------- ------- -------	-------	--------------
+; CS (DAT3)	LO ->	RTC:2	RTC:2	RTC:2	~PC:4	~MCR:3	OPR:2	SD:2	~RTC:2/3OPR:4/5~OPR:3
+; CLK		HI ->	RTC:1	RTC:1	CSIO	PC:1	~MCR:2	OPR:1	CSIO	CSIO	SPI    OPR:4
+; DI (CMD)	HI ->	RTC:0	RTC:0	CSIO	PC:0	~MCR:0	OPR:0	CSIO	CSIO	SPI    OPR:0
+; DO (DAT0)	HI ->	RTC:7	RTC:6	CSIO	PB:7	~MSR:5	OPR:0	CSIO	CSIO	SPI    OPR:7
+;-----------------------------------------------------------------------------------------------------
 ;
 ; CS = CHIP SELECT (AKA DAT3 FOR NON-SPI MODE)
 ; CLK = CLOCK
@@ -167,6 +167,7 @@ RTCDEF		.SET	RTCDEF | SD_OPRDEF	; SET DEFAULT IN HBIOS MAINLINE
 SD_DEVMAX	.EQU	1		; NUMBER OF PHYSICAL UNITS (SOCKETS)
 SD_PPIBASE	.EQU	SDPPIBASE	; BASE IO PORT FOR PPI
 SD_PPIB		.EQU	SDPPIBASE + 1	; PPI PORT B (INPUT: DOUT)
+SD_PPIB		.EQU	SDPPIBASE + 1	; PPI PORT B (INPUT: DOUT)
 SD_PPIC		.EQU	SDPPIBASE + 2	; PPI PORT C (OUTPUT: CS, CLK, DIN)
 SD_PPIX		.EQU	SDPPIBASE + 3	; PPI CONTROL PORT
 SD_OPRREG	.EQU	SD_PPIC		; PPI PORT C IS OPR REG
@@ -298,7 +299,10 @@ SD_INVCS	.EQU	FALSE		; INVERT CS
 SD_DEVMAX	.EQU	1		; NUMBER OF PHYSICAL UNITS (SOCKETS)
 SD_IOBASE	.EQU	$69		; IO BASE ADDRESS FOR SD INTERFACE
 SD_OPRREG	.EQU	SD_IOBASE	; OUTPUT PORT (OUTPUT: CS, CLK, DIN)
-SD_OPRDEF	.EQU	%11111111	; OUTPUT PORT DEFAULT STATE
+;--- WBW
+;SD_OPRDEF	.EQU	%11111111	; OUTPUT PORT DEFAULT STATE
+SD_OPRDEF	.EQU	%11101111	; OUTPUT PORT DEFAULT STATE
+;---
 SD_INPREG	.EQU	SD_IOBASE	; INPUT REGISTER
 SD_CS0		.EQU	%00001000	; SELECT
 SD_CLK		.EQU	%00010000	; CLOCK
@@ -928,7 +932,7 @@ SD_RESET:
 SD_DEVICE:
 	LD	D,DIODEV_SD		; D := DEVICE TYPE
 	LD	E,(IY+SD_DEV)		; E := PHYSICAL DEVICE NUMBER
-	LD	C,%01110010		; C := ATTRIBUTES, REMOVABLE, SD CARD
+	LD	C,%00110010		; C := ATTRIBUTES, REMOVABLE, SD CARD
 	LD	H,SDMODE		; H := MODE
 	LD	L,(SD_IOBASE)		; L := BASE I/O ADDRESS
 	XOR	A			; SIGNAL SUCCESS
@@ -1801,6 +1805,7 @@ SD_SETUP:
 ;
 #IF (SDMODE == SDMODE_PIO)
 	LD	A,SD_OPRDEF		; All output bits high
+	LD	(SD_OPRVAL),A		; WBW
 	OUT	(SD_OPRREG),A
 	LD	A,$CF			; Port B mode 3
 	OUT	(SD_DDR),A
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
Wayne Warthen	a157d9ba13	Device Type ID Reorganization Driver Device Type ID's have been stored in the upper nibble. However, running out of ID's, I have changed them to occupy the entire byte. This is a breaking change, so I have updated the minor version number to maintain integrity between components. So, v3.3 will never become a stable release and I am moving directly to v3.4.	2023-10-05 18:08:52 -07:00
Wayne Warthen	85783148be	Bump Version	2023-10-05 15:33:41 -07:00
Wayne Warthen	7bd930bc76	Issue #366 Further refinements to User Guide based on input from Dean Jenkins.	2023-10-05 15:04:26 -07:00
Wayne Warthen	c1fa7b420a	SD Media Automatic Drive Assignment - Issue #365 - Modified SD Media handling such that no OS drive letters will be assigned automatically at OS Startup if there is no media inserted.	2023-10-05 10:14:30 -07:00
Wayne Warthen	9072bc6d70	Issue #366 Based on input from Dean Jenkins: - Updated User Guide to clarify some nuances related to use of Combo Disk Images - Added "blank" slice images	2023-10-04 16:54:34 -07:00
Wayne Warthen	480dbe4f4c	Add Disk Images for ROMless Configurations	2023-10-03 19:44:49 -07:00
Wayne Warthen	26fad23c3a	Z280 ROMless Fixes - Corrected a couple deficiencies that caused Z280 CPUs to fail in the new ROMless configuration	2023-10-03 15:24:18 -07:00
Wayne Warthen	883dab7e97	ROMless Operation Overhaul - Implement new approach to ROMless boot and operation. Still missing the ability to seed the RAM disk. - Tweaks to CH driver	2023-10-01 17:22:19 -07:00
Wayne Warthen	d3f5643791	CH Driver Tweaks	2023-09-24 16:47:36 -07:00
Wayne Warthen	5299d24379	Merge pull request #363 from skullandbones/Issue-362_RPI4_no_bios.bin_v1 zxcc: Fix for load bios.bin failure on a RPi4	2023-09-24 16:25:50 -07:00
Dean Jenkins	a229db96a6	zxcc: Fix for load bios.bin failure on a RPi4 Fix load_bios() when used on a Raspberry Pi4. The defect was corrupting the path of the zxcc executable. The fix is to NUL terminate the path string from the readlink() call.	2023-09-24 17:04:35 +01:00
Wayne Warthen	092e44c62e	RPi Builds & CH375/6 Support - The build process was enhanced by Dean Jenkins to support the Raspberry Pi. Note that the Propeller firmware will not be generated by a RPi build. See Issue #358. - Initial support for USB storage via CH375/6.	2023-09-22 14:13:12 -07:00
Wayne Warthen	722bce819b	Bump Version	2023-09-16 13:41:32 -07:00
Wayne Warthen	2d470a2a90	Merge pull request #360 from danwerner21/dev ESP32 Driver updates	2023-09-16 13:24:08 -07:00
Dan Werner	b6700dfa4c	ESP32 Driver updates	2023-09-16 14:47:09 -05:00
Wayne Warthen	cfc76d0659	Add Heath H8 Framework	2023-09-14 19:38:17 -07:00
Wayne Warthen	7fce3277a0	Create SCZ180_sc700.asm - Missed this file on last commit	2023-09-13 14:56:24 -07:00
Wayne Warthen	2219e4c82d	Miscellaneous - Add SCZ180_sc700 standard build - Minor fix to DMAMON	2023-09-13 14:03:54 -07:00
Wayne Warthen	68e841e62c	Miscellaneous - Minor correction to DMAMON to restore proper operation of interrupt testing - Minor improvements to QPM documentation	2023-09-11 10:17:57 -07:00
Wayne Warthen	bb70c36b36	Improve QPM Build The QPM portion of the build has been updated to dynamically combine the current CBIOS with the static QPM CCP and BDOS binaries. This will keep the QPM system image up to date and avoid HBIOS version mismatch warnings.	2023-09-09 16:18:40 -07:00
Wayne Warthen	c391fd6d56	Support S100 Propeller Console	2023-09-07 18:16:25 -07:00
Wayne Warthen	e69caf5059	Add SROM (Serial ROM) Utility	2023-09-05 16:29:05 -07:00
Wayne Warthen	8b7e71049b	FDC Detection Update & Enable ESP Driver on Duodyne - Based on reports from Martin R, the FDC detection algorithm has been updated to try reading the FDC MSR register twice to try and get the desired value of 0x80. - Dan Werner's ESP board for Duodyne is working well, so the default Duodyne config has been changed to automatically detect this board.	2023-08-25 10:25:07 -07:00
Wayne Warthen	50e190c755	Merge pull request #357 from fernandocarolo/dev Fix references to the EPFDC driver in comments.	2023-08-23 14:44:47 -07:00
Wayne Warthen	d0eccf026b	Enable INTRTC for Easy Z80	2023-08-23 14:28:20 -07:00
Fernando Carolo	39f796ce22	Fix references to the EPFDC driver in comments. The EtchedPixels floppy disk controller is known by the identifier 'FDMODE_EPFDC', but the comments in the Config subdirectory have an incorrect reference to 'EPWDC'. This fix updates the comments to use the correct name.	2023-08-23 21:02:48 +01:00
Wayne Warthen	5610e79db4	Improve FD Driver Detection Credit to Martin R for reporting that his FDC was not being detected. The delay between FDC status register reads was increased in the detection routine to correct this.	2023-08-22 15:22:11 -07:00
Wayne Warthen	e782b78b16	Bump Version	2023-08-22 11:02:08 -07:00
Wayne Warthen	c0d3969244	Merge pull request #356 from b1ackmai1er/dev Duo/MBC IM2 Hardware Timer support	2023-08-22 10:54:30 -07:00
b1ackmai1er	c62af3df33	MBC / DUO IM2 template Template for setting up interrupts using the IM2 pin header on MBC and DUO platforms.	2023-08-22 13:16:42 +08:00
b1ackmai1er	6d736996fd	Merge pull request #60 from wwarthen/dev Support Serial Ports on ESP32 Board	2023-08-22 12:32:56 +08:00
Wayne Warthen	8bc801d0a4	Support Serial Ports on ESP32 Board	2023-08-21 17:40:34 -07:00
b1ackmai1er	2c6b7f7fb1	Update std.asm	2023-08-21 16:38:59 +08:00
b1ackmai1er	c3503f56d1	Update cfg_z80retro.asm	2023-08-21 16:29:27 +08:00
b1ackmai1er	d4c87996f0	Merge branch 'dev' of https://github.com/b1ackmai1er/RomWBW into dev	2023-08-21 16:25:29 +08:00
b1ackmai1er	9f5b3a8b1c	Duo/MBC IM2 Hardware Timer support	2023-08-21 16:00:47 +08:00
Wayne Warthen	d06e1e2a5c	Initial DUO Interrupt Handling	2023-08-20 15:03:34 -07:00
Wayne Warthen	22a0c52af3	Bump Version	2023-08-20 12:10:32 -07:00
Wayne Warthen	85aa7e89c2	Merge pull request #355 from b1ackmai1er/dev Update DMAMON	2023-08-20 11:56:16 -07:00
b1ackmai1er	59d04f2446	Update std.asm	2023-08-20 18:18:55 +08:00
b1ackmai1er	9cc52e30d6	Update dmamon.asm	2023-08-20 18:16:19 +08:00
Wayne Warthen	e1a4e815dc	Fix S100 Z180 Board LED Operation - Status LED for S100 Z180 board was not enabled. Credit to Jay Cotton for finding this.	2023-08-17 12:53:59 -07:00
Wayne Warthen	3c340d1ab9	Miscellaneous - Minor documentation updates - Improve ESP driver hardware detection	2023-08-17 11:26:19 -07:00
Wayne Warthen	138248fafc	Merge pull request #354 from oholiab/xm_send_on_port Add port option to XM's send mode	2023-08-16 19:40:40 -07:00
Matt Carroll	834eefb0bb	Add port option to XM's send mode	2023-08-16 15:03:12 +01:00
Wayne Warthen	7835eb5deb	Duodyne Work in Progress - Updated DMA Driver - Updated PCF I2C Driver	2023-08-02 13:21:52 -07:00
Wayne Warthen	d1a5c66147	Update DUO_std.asm	2023-07-28 15:43:31 -07:00
Wayne Warthen	b184ccfb78	Miscellaneous - Updated S100 Monitor launch code to warn user if console will be directed to S100 bus vs. active on-board UART. - Updated Duodyne early boot to add a delay to stabilize the boot process. This is temporary and needs to be further investigated.	2023-07-28 15:19:54 -07:00
Wayne Warthen	4776b32cd3	Revise S100 Monitor Boot Option	2023-07-26 13:52:50 -07:00
Wayne Warthen	2bc5333f2b	Add Boot Loader Menu Entry for S100 Z180 Monitor Invocation	2023-07-25 16:47:51 -07:00
Wayne Warthen	a5575456e2	Initial Support for Duodyne	2023-07-24 19:24:49 -07:00
Wayne Warthen	bdb8dc020b	Update S100 Monitor to v0.34	2023-07-22 18:56:37 -07:00
Wayne Warthen	faaba69554	Improve sd.asm SD Card Compatibility - PIO mode of sd.asm driver modified to setup shadow register (Issue #352). - Relocated Z280 IVT to improve space utilization in HBIOS bank.	2023-07-17 14:52:14 -07:00
Wayne Warthen	0395bba4f5	Preliminary Support for ESP32 Nhyodyne Module - Initial console support for Dan Werner's ESP32 Module	2023-07-10 13:16:24 -07:00
Wayne Warthen	14ac7a917b	Upgrade s100mon to Latest - Incorporated latest S100 Board Monitor code from John Monahan	2023-07-09 12:38:48 -07:00