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3 Commits

Author SHA1 Message Date
Wayne Warthen
9f71fe05aa Cleanup IDE and PPIDE drivers
- The use of hardware reset has been improved such that it is generally only used at initial boot up.
- Minor improvements to CF card detection and initialization.
- Implement a simple wait mechanism to accommodate the startup time of the RC2014 SD Pico module.
- Front panel I/O port for SC series of systems has been moved to 0x00 which is consistent with all other systems and avoids some I/O conflicts.
2023-04-30 12:03:16 -07:00
Wayne Warthen
ad3c533145 Fix IDE Detection on Spinning Disks
Prior improvement to IDE device detection broke detection of spinning hard disks.  IDE registers cannot be used prior to device init completion (spin up).  Not a problem for CF, but special steps required to ensure devices are fully initialized before register testing.
2023-04-23 18:47:43 -07:00
Wayne Warthen
e43a939f54 Improve IDE Device Detection
Per issue #343, some systems could initially detect a non-existent IDE device which would cause a long time-out.  This should resolve the issue.
2023-04-21 17:08:18 -07:00
8 changed files with 800 additions and 575 deletions

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@@ -35,8 +35,10 @@ Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
;
FPENABLE .SET TRUE ; ENABLES FRONT PANEL SWITCHES
DIAGENABLE .SET TRUE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
DIAGPORT .SET $00 ; DIAGNOSTIC PORT ADDRESS
LEDENABLE .SET TRUE ; ENABLE STATUS LED (SINGLE LED)
DIAGENABLE .SET FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
;
DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
INTRTCENABLE .SET TRUE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)

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@@ -35,10 +35,10 @@ Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
;
FPENABLE .SET TRUE ; ENABLES FRONT PANEL SWITCHES
FPBASE .SET $A0 ; FRONT PANEL I/O PORT BASE ADDRESS
FPBASE .SET $00 ; FRONT PANEL I/O PORT BASE ADDRESS
LEDENABLE .SET TRUE ; ENABLE STATUS LED (SINGLE LED)
DIAGENABLE .SET TRUE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
DIAGPORT .SET $A0 ; DIAGNOSTIC PORT ADDRESS
DIAGPORT .SET $00 ; DIAGNOSTIC PORT ADDRESS
;
DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
INTRTCENABLE .SET TRUE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)

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@@ -35,10 +35,10 @@ Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
;
FPENABLE .SET TRUE ; ENABLES FRONT PANEL SWITCHES
FPBASE .SET $A0 ; FRONT PANEL I/O PORT BASE ADDRESS
FPBASE .SET $00 ; FRONT PANEL I/O PORT BASE ADDRESS
LEDENABLE .SET TRUE ; ENABLE STATUS LED (SINGLE LED)
DIAGENABLE .SET TRUE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
DIAGPORT .SET $A0 ; DIAGNOSTIC PORT ADDRESS
DIAGPORT .SET $00 ; DIAGNOSTIC PORT ADDRESS
;
DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
INTRTCENABLE .SET TRUE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)

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@@ -67,7 +67,7 @@ SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
;
FPENABLE .EQU FALSE ; ENABLES FRONT PANEL SWITCHES
FPBASE .EQU $0D ; FRONT PANEL I/O PORT BASE ADDRESS
FPBASE .EQU $00 ; FRONT PANEL I/O PORT BASE ADDRESS
DIAGENABLE .EQU TRUE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
DIAGPORT .EQU $0D ; DIAGNOSTIC PORT ADDRESS
DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

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@@ -2,7 +2,7 @@
#DEFINE RMN 3
#DEFINE RUP 0
#DEFINE RTP 0
#DEFINE BIOSVER "3.3.0-dev.4"
#DEFINE BIOSVER "3.3.0-dev.7"
#define rmj RMJ
#define rmn RMN
#define rup RUP

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@@ -3,5 +3,5 @@ rmn equ 3
rup equ 0
rtp equ 0
biosver macro
db "3.3.0-dev.4"
db "3.3.0-dev.7"
endm