Cleanup IDE and PPIDE drivers

- The use of hardware reset has been improved such that it is generally only used at initial boot up.
- Minor improvements to CF card detection and initialization.
- Implement a simple wait mechanism to accommodate the startup time of the RC2014 SD Pico module.
- Front panel I/O port for SC series of systems has been moved to 0x00 which is consistent with all other systems and avoids some I/O conflicts.

Doc/ChangeLog.txt

@@ -1,3 +1,11 @@
+Version 3.3
+-----------
+- WBW: Support Front Panel switches
+- A?C: Preliminary support for Z80-Retro
+- A?C: Support for SD PIO
+- A?C: Support for Z80-Retro SD interface
+- WBW: Support per-drive floppy configuration
+
 Version 3.2.1
 -------------
 - M?P: Fixed Zeta 2 FDD and CPUSPD config settings

ReadMe.md

@@ -1,9 +1,9 @@
 
 
 **RomWBW ReadMe** \
-Version 3.2.1 \
+Version 3.3 \
 Wayne Warthen  ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \
-27 Mar 2023
+16 Apr 2023
 
 # Overview
 

ReadMe.txt

@@ -1,6 +1,6 @@
 RomWBW ReadMe
 Wayne Warthen (wwarthen@gmail.com)
-27 Mar 2023
+16 Apr 2023
 
 
 

Source/Doc/Basic.h

@@ -1,4 +1,4 @@
-$define{doc_ver}{Version 3.2.1}$
+$define{doc_ver}{Version 3.3}$
 $define{doc_product}{RomWBW}$
 $define{doc_root}{https://github.com/wwarthen/RomWBW/raw/dev/Doc}$
 $ifndef{doc_title}$ $define{doc_title}{Document Title}$ $endif$

Source/Doc/SystemGuide.md

@@ -2123,6 +2123,17 @@ Wait States (D) is the actual number of wait states, not the number
 of wait states added.  The returned Status (A) is a standard HBIOS 
 result code.
 
+#### SYSGET Subfunction 0xF4 -- Get Front Panel Swithes (PANEL)
+
+| **Entry Parameters**                   | **Returned Values**                    |
+|----------------------------------------|----------------------------------------|
+| B: 0xF8                                | A: Status                              |
+| C: 0xF4                                | L: Switches                            |
+
+This function will return the current value of the switches (L) from the
+front panel of the system.  If no front panel is available in the
+system, the returned Status (A) will indicate a No Hardware error.
+
 ### Function 0xF9 -- System Set (SYSSET)
 
 | **Entry Parameters**                   | **Returned Values**                    |
@@ -2206,6 +2217,18 @@ limited set of divisors.  If there is no satisfactory divisor to
 retain the existing baud rate under the new CPU speed, then the baud
 rate of the ASCI port(s) will be affected.
 
+#### SYSSET Subfunction 0xF4 -- Set Front Panel LEDs (PANEL)
+
+| **Entry Parameters**                   | **Returned Values**                    |
+|----------------------------------------|----------------------------------------|
+| B: 0xF8                                | A: Status                              |
+| C: 0xF4                                |                                        |
+| L: LEDs                                |                                        |
+
+This function will set the front panel LEDs based on the bits in L. If 
+no front panel is available in the system, the returned Status (A) will 
+indicate a No Hardware error.
+
 ### Function 0xFA -- System Peek (SYSPEEK)
 
 | **Entry Parameters**                   | **Returned Values**                    |

Source/Doc/UserGuide.md

@@ -201,6 +201,7 @@ below, **carefully** pick the appropriate ROM image for your hardware.
 | [Z80 ZRC CPU Module]^7^                                        | RCBus   | RCZ80_zrc.rom      | 115200        |
 | [Z280 ZZRCC CPU Module]^7^                                     | RCBus   | RCZ280_zzrc.rom    | 115200        |
 | [Z280 ZZ80MB SBC]^7^                                           | RCBus   | RCZ280_zz80mb.rom  | 115200        |
+| [Z80-Retro SBC]^8^                                             | -       | Z80RETRO_std.rom   | 38400         |
 
 | ^1^Designed by Andrew Lynch
 | ^2^Designed by Sergey Kiselev
@@ -209,6 +210,7 @@ below, **carefully** pick the appropriate ROM image for your hardware.
 | ^5^Designed by Stephen Cousins
 | ^6^Designed by Steve Garcia
 | ^7^Designed by Bill Shen
+| ^8^Designed by Peter Wilson
 
 RCBus refers to Spencer Owen's RC2014 bus specification and derivatives
 including RC26, RC40, RC80, and BP80.
@@ -782,6 +784,55 @@ The use of diagnostic levels above 4 are really intended only for
 software developers.  I do not recommend changing this under
 normal circumstances.
 
+## Front Panel
+
+RomWBW supports the concept of a simple front panel.  The following 
+image is a conceptual view of such a front panel.  If your system has a 
+front panel, it should look similar to the [RomWBW Front Panel](#panel).
+
+![RomWBW Front Panel](Graphics/Panel){#panel width=50% }
+
+The LEDs in the top row of the panel are used for multiple purposes.
+They are initially used to display the progress of the
+system boot.  This may help in diagnosing a hardware or configuration
+issue in a system that does not progress far enough to display text
+output on the console.  The meaning of the LEDs is:
+
+|            |                              |
+|------------|------------------------------|
+| `O-------` | System Boot has started      |
+| `OO------` | Common RAM bank activated    |
+| `OOO-----` | HBIOS transitioned to RAM    |
+| `OOOO----` | Basic initialization done    |
+| `OOOOO---` | CPU detection complete       |
+| `OOOOOO--` | System timer configured      |
+| `OOOOOOO-` | Pre-console device init done |
+| `OOOOOOOO` | Console activation           |
+
+Once the system has booted, the LEDs are used to indicate disk device
+activity.  Each LED numbered 7-0 represents disk units 7-0.  As each
+disk device performs I/O, the LED will light.
+
+The second row of the front panel is composed of switches that allow
+you to control a few aspects of the system startup.
+
+The first two switches affect the device used as the console initially.
+Setting the CRT/Serial switch will cause the system to boot directly 
+to an attached CRT device (if available).  Setting the Pri/Sec switch 
+will cause the system to boot to the secondary Serial or CRT device 
+(depending on the setting of the first switch).
+
+The final six switches allow you to cause the system to automatically
+boot into a desired function.  The Auto/Menu switch must be set to
+enable this, otherwise the normal ROM Loader prompt will be used.
+If the Disk/ROM switch is not set, then you can use the last 3
+switches to select a ROM app to auto-start.  If the Disk/ROM switch is
+set, then the system will attempt a disk boot based on the following
+switches.  The Floppy/Hard switch can be used to boot to a Floppy or
+Hard Disk.  In either case, the first Floppy or Hard Disk will be used
+for the boot.  If a Hard Disk boot is selected, then the last three
+switches can be used to select any of the first 8 slices.
+
 # Disk Management
 
 The systems supported by RomWBW all have the ability to use persistent
@@ -3808,6 +3859,21 @@ the RomWBW HBIOS configuration.
 
 `\clearpage`{=latex}
 
+### Z80-Retro SBC
+
+|                   |                  |
+|-------------------|------------------|
+| ROM Image File    | Z80RETRO_std.rom |
+| Console Baud Rate | 38400            |
+| Interrupts        | Mode 2           |
+
+ - CPU speed is assumed to be 14.7456 MHz
+ - Hardware auto-detected:
+   - SIO Serial Interface Module
+   - Onboard CTC
+
+`\clearpage`{=latex}
+
 ## Appendix B - Device Summary
 
 The table below briefly describes each of the possible devices that

Source/HBIOS/API.txt

@@ -117,7 +117,11 @@ GET ($F8):
 						L=Clock Mult (0:Half, 1:Full, 2: Double)
 						D=Memory Wait States
 						E=I/O Wait States
-						
+
+    PANEL ($F4):
+      BC=Function/Subfunction			A=Result
+						L=Switch Values
+
 
 SET ($F9):
   BC=Function/Subfunction                       A=Result
@@ -142,6 +146,11 @@ SET ($F9):
 						E=I/O Wait States
 						
 
+    PANEL ($F4):
+      BC=Function/Subfunction			A=Result
+						L=LED Values
+
+
 PEEK ($FA):
   B=Function                       		A=Result
   D=Bank					E=Byte Value

Source/HBIOS/Build.cmd

@@ -223,5 +223,6 @@ call Build SCZ180 sc503 || exit /b
 call Build DYNO std || exit /b
 call Build UNA std || exit /b
 call Build RPH std || exit /b
+call Build Z80RETRO std || exit /b
 
 goto :eof

Source/HBIOS/Build.ps1

@@ -27,7 +27,7 @@ $ErrorAction = 'Stop'
 # UNA BIOS is simply imbedded, it is not built here.
 #
 
-$PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "UNA"
+$PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "Z80RETRO", "UNA"
 $PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO", "RPH"
 $PlatformListZ280 = "RCZ280"
 

Source/HBIOS/Build.sh

@@ -38,6 +38,7 @@ if [ "${ROM_PLATFORM}" == "dist" ] ; then
 	ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc140"; bash Build.sh
 	ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc503"; bash Build.sh
 	ROM_PLATFORM="UNA"; ROM_CONFIG="std"; bash Build.sh
+	ROM_PLATFORM="Z80RETRO"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="ZETA"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="ZETA2"; ROM_CONFIG="std"; bash Build.sh
 	exit

Source/HBIOS/Config/RCZ180_ext.asm

@@ -29,6 +29,8 @@
 CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
+FPENABLE	.SET	TRUE		; ENABLES FRONT PANEL SWITCHES
+;
 MEMMGR		.SET	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
 ;
 Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2

Source/HBIOS/Config/RCZ180_nat.asm

@@ -29,6 +29,8 @@
 CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
+FPENABLE	.SET	TRUE		; ENABLES FRONT PANEL SWITCHES
+;
 MEMMGR		.SET	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
 ;
 Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2

Source/HBIOS/Config/RCZ280_ext.asm

@@ -30,6 +30,8 @@ CPUOSC		.SET	12000000	; CPU OSC FREQ IN MHZ
 INTMODE		.SET	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
+FPENABLE	.SET	TRUE		; ENABLES FRONT PANEL SWITCHES
+;
 MEMMGR		.SET	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
 ;
 Z280_MEMLOWAIT	.SET	0		; Z280: LOW 8MB MEMORY WAIT STATES (0-3)

Source/HBIOS/Config/RCZ280_nat.asm

@@ -30,6 +30,8 @@ CPUOSC		.SET	12000000	; CPU OSC FREQ IN MHZ
 INTMODE		.SET	3		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
+FPENABLE	.SET	TRUE		; ENABLES FRONT PANEL SWITCHES
+;
 MEMMGR		.SET	MM_Z280		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 ;
 Z280_MEMLOWAIT	.SET	0		; Z280: LOW 8MB MEMORY WAIT STATES (0-3)

Source/HBIOS/Config/RCZ280_zz80mb.asm

@@ -32,6 +32,8 @@ CPUOSC		.SET	12000000	; CPU OSC FREQ IN MHZ
 INTMODE		.SET	3		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
+FPENABLE	.SET	TRUE		; ENABLES FRONT PANEL SWITCHES
+;
 MEMMGR		.SET	MM_Z280		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 ;
 RAMLOC		.SET	23		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE

Source/HBIOS/Config/RCZ280_zzrc.asm

@@ -32,6 +32,8 @@ CPUOSC		.SET	14745600	; CPU OSC FREQ IN MHZ
 INTMODE		.SET	3		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
+FPENABLE	.SET	TRUE		; ENABLES FRONT PANEL SWITCHES
+;
 MEMMGR		.SET	MM_Z280		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 ;
 RAMSIZE		.SET	256		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)

Source/HBIOS/Config/RCZ80_easy.asm

@@ -33,6 +33,8 @@ CPUOSC		.SET	10000000	; CPU OSC FREQ IN MHZ
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 ;
+FPENABLE	.SET	TRUE		; ENABLES FRONT PANEL SWITCHES
+;
 WDOGMODE	.SET	WDOG_EZZ80	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 WDOGIO		.SET	$6F		; WATCHDOG REGISTER ADR
 ;

Source/HBIOS/Config/RCZ80_kio.asm

@@ -30,6 +30,8 @@ CPUOSC		.SET	7372800		; CPU OSC FREQ IN MHZ
 INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
+FPENABLE	.SET	TRUE		; ENABLES FRONT PANEL SWITCHES
+;
 DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
 KIOENABLE	.SET	TRUE		; ENABLE ZILOG KIO SUPPORT

Source/HBIOS/Config/RCZ80_skz.asm

@@ -29,6 +29,8 @@
 CPUOSC		.SET	7372800		; CPU OSC FREQ IN MHZ
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
+FPENABLE	.SET	TRUE		; ENABLES FRONT PANEL SWITCHES
+;
 SKZENABLE	.SET	TRUE		; ENABLE SERGEY'S Z80-512K FEATURES
 SKZDIV		.SET	DIV_12		; UART CLK (CLK2) DIVIDER FOR Z80-512K
 WDOGMODE	.SET	WDOG_SKZ	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]

Source/HBIOS/Config/RCZ80_std.asm

@@ -29,6 +29,8 @@
 CPUOSC		.SET	7372800		; CPU OSC FREQ IN MHZ
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
+FPENABLE	.SET	TRUE		; ENABLES FRONT PANEL SWITCHES
+;
 DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
 ;
@@ -53,6 +55,7 @@ FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
 SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.SET	SDMODE_PIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|USR]
 SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY
 ;
 PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)

Source/HBIOS/Config/RCZ80_tiny.asm

@@ -33,6 +33,8 @@ CPUOSC		.SET	16000000	; CPU OSC FREQ IN MHZ
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 ;
+FPENABLE	.SET	TRUE		; ENABLES FRONT PANEL SWITCHES
+;
 EIPCENABLE	.SET	TRUE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 WDOGMODE	.SET	WDOG_EZZ80	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 WDOGIO		.SET	$6F		; WATCHDOG REGISTER ADR

Source/HBIOS/Config/RCZ80_zrc.asm

@@ -30,6 +30,8 @@
 CPUOSC		.SET	14745600	; CPU OSC FREQ IN MHZ
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
+FPENABLE	.SET	TRUE		; ENABLES FRONT PANEL SWITCHES
+;
 RAMSIZE		.SET	1536		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 MEMMGR		.SET	MM_ZRC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
 ;

Source/HBIOS/Config/RCZ80_zrc_ram.asm

@@ -31,6 +31,8 @@
 CPUOSC		.SET	7372800		; CPU OSC FREQ IN MHZ
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
+FPENABLE	.SET	TRUE		; ENABLES FRONT PANEL SWITCHES
+;
 RAMSIZE		.SET	2048		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.SET	0		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
 MEMMGR		.SET	MM_ZRC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]

Source/HBIOS/Config/SBC_simh.asm

@@ -30,6 +30,9 @@ INTMODE		.SET	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 ;
 HTIMENABLE	.SET	TRUE		; ENABLE SIMH TIMER SUPPORT
 ;
+SIMRTCENABLE	.SET	TRUE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+DSRTCENABLE	.SET	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+;
 UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 UARTSBCFORCE	.SET	TRUE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 ;

Source/HBIOS/Config/SCZ180_sc126.asm

@@ -35,6 +35,7 @@ Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
 Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
 Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 ;
+FPENABLE	.SET	TRUE		; ENABLES FRONT PANEL SWITCHES
 DIAGENABLE	.SET	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.SET	$0D		; DIAGNOSTIC PORT ADDRESS
 ;

Source/HBIOS/Config/SCZ180_sc130.asm

@@ -35,8 +35,10 @@ Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
 Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
 Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 ;
+FPENABLE	.SET	TRUE		; ENABLES FRONT PANEL SWITCHES
+DIAGENABLE	.SET	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
+DIAGPORT	.SET	$00		; DIAGNOSTIC PORT ADDRESS
 LEDENABLE	.SET	TRUE		; ENABLE STATUS LED (SINGLE LED)
-DIAGENABLE	.SET	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 ;
 DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 INTRTCENABLE	.SET	TRUE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)

Source/HBIOS/Config/SCZ180_sc140.asm

@@ -34,9 +34,11 @@ Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
 Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
 Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 ;
+FPENABLE	.SET	TRUE		; ENABLES FRONT PANEL SWITCHES
+FPBASE		.SET	$00		; FRONT PANEL I/O PORT BASE ADDRESS
 LEDENABLE	.SET	TRUE		; ENABLE STATUS LED (SINGLE LED)
 DIAGENABLE	.SET	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
-DIAGPORT	.SET	$A0		; DIAGNOSTIC PORT ADDRESS
+DIAGPORT	.SET	$00		; DIAGNOSTIC PORT ADDRESS
 ;
 DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 INTRTCENABLE	.SET	TRUE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)

Source/HBIOS/Config/SCZ180_sc503.asm

@@ -34,9 +34,11 @@ Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
 Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
 Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 ;
+FPENABLE	.SET	TRUE		; ENABLES FRONT PANEL SWITCHES
+FPBASE		.SET	$00		; FRONT PANEL I/O PORT BASE ADDRESS
 LEDENABLE	.SET	TRUE		; ENABLE STATUS LED (SINGLE LED)
 DIAGENABLE	.SET	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
-DIAGPORT	.SET	$A0		; DIAGNOSTIC PORT ADDRESS
+DIAGPORT	.SET	$00		; DIAGNOSTIC PORT ADDRESS
 ;
 DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 INTRTCENABLE	.SET	TRUE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)

Source/HBIOS/Config/Z80RETRO_std.asm

@@ -0,0 +1,35 @@
+;
+;==================================================================================================
+;   ZETA2 STANDARD CONFIGURATION
+;==================================================================================================
+;
+; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
+; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
+; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
+; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
+; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
+; YOUR FILE IN THE BUILD PROCESS.
+;
+; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
+; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
+; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
+; SETTINGS.
+;
+; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
+; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
+; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
+; DIRECTORIES ABOVE THIS ONE).
+;
+#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
+;
+#include "cfg_z80retro.asm"
+;
+CPUOSC		.SET	14745600	; CPU OSC FREQ IN MHZ
+INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+;
+UARTENABLE	.SET	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+;
+SDENABLE	.SET	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)

Source/HBIOS/asci.asm

@@ -53,7 +53,7 @@
 ; ASEXT:
 ; 7 6 5 4 3 2 1 0
 ; R D C X B F D S
-; 0 1 1 0 0 1 1 0   DEFAULT VALUES
+; 0 1 1 0 0 0 0 0   DEFAULT VALUES
 ; | | | | | | | |
 ; | | | | | | | +-- SEND BREAK
 ; | | | | | | +---- BREAK DETECT (RO)
@@ -64,6 +64,10 @@
 ; | +-------------- DCD0 DISABLE
 ; +---------------- RDRF INT INHIBIT
 ;
+ASCI_DEF_CNTLA	.EQU	$64
+ASCI_DEF_CNTLB	.EQU	$20
+ASCI_DEF_ASEXT	.EQU	$60
+;
 ASCI_BUFSZ	.EQU	32		; RECEIVE RING BUFFER SIZE
 ;
 ASCI_NONE	.EQU	0		; NOT PRESENT
@@ -513,17 +517,29 @@ ASCI_INITDEV3:
 	SET	4,C			; SET CNTLB BIT 4 FOR ODD PARITY
 ;
 ASCI_INITDEV4:
+	; SETUP ASEXT
+	LD	A,D			; CONFIG HIGH BYTE
+	AND	%00100000		; BIT 5 IS RTS
+	CPL				; INVERT FOR ASEXT
+	LD	L,A			; MOVE TO L
+	LD	A,ASCI_DEF_ASEXT	; GET ASEXT DEFAULT
+	AND	L			; COMBINE
+	LD	L,A			; AND LEAVE IN L
+;
 	; SAVE CONFIG PERMANENTLY NOW
 	LD	(IY+4),E		; SAVE LOW WORD
 	LD	(IY+5),D		; SAVE HI WORD
 	JR	ASCI_INITGO
 ;
 ASCI_INITSAFE:
-	LD	B,$64			; CNTLA FAILSAFE VALUE
-	LD	C,$20			; CNTLB FAILSAFE VALUE
+	LD	B,ASCI_DEF_CNTLA	; CNTLA FAILSAFE VALUE
+	LD	C,ASCI_DEF_CNTLB	; CNTLB FAILSAFE VALUE
+	LD	L,ASCI_DEF_ASEXT	; ASEXT FAILSAFE VALUE
 ;
 ASCI_INITGO:
 	; IMPLEMENT CONFIGURATION
+	; B = CNTLA, C=CNTLB, L=ASEXT
+	PUSH	HL			; SAVE ASEXT
 	LD	H,B			; H := CNTLA VAL
 	LD	L,C			; L := CNTLB VAL
 	LD	B,0			; MSB OF PORT MUST BE ZERO!
@@ -532,6 +548,7 @@ ASCI_INITGO:
 	INC	C			; BUMP TO
 	INC	C			; ... CNTLB REG, B IS STILL 0
 	OUT	(C),L			; WRITE CNTLB VALUE
+	POP	HL			; RECOVER ASEXT
 	INC	C			; BUMP TO
 	INC	C			; ... STAT REG, B IS STILL 0
 #IF ((ASCIINTS) & (INTMODE > 0))
@@ -543,8 +560,11 @@ ASCI_INITGO:
 	LD	A,$0E			; BUMP TO
 	ADD	A,C			; ... ASEXT REG
 	LD	C,A			; PUT IN C FOR I/O, B IS STILL 0
-	LD	A,$66			; STATIC VALUE FOR ASEXT
-	OUT	(C),A			; WRITE ASEXT REG
+	BIT	0,C			; IS C ADDRESSING AN ODD NUMBERED PORT?
+	JR	NZ,ASCI_INITGOZ		; IF SO, THIS IS SEC SERIAL, NO CTS!
+	OUT	(C),L			; WRITE ASEXT REG
+;
+ASCI_INITGOZ:
 ;
 #IF ((ASCIINTS) & (INTMODE > 0))
 ;

Source/HBIOS/cfg_dyno.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_DYNO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_DYNO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -66,6 +66,8 @@ SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
+FPENABLE	.EQU	FALSE		; ENABLES FRONT PANEL SWITCHES
+FPBASE		.EQU	$00		; FRONT PANEL I/O PORT BASE ADDRESS
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
@@ -146,7 +148,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ACFG	.EQU	SER_115200_8N1	; SIO 0A: SERIAL LINE CONFIG
@@ -154,7 +156,7 @@ SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 SIO0BCLK	.EQU	7372800		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0BCFG	.EQU	SER_115200_8N1	; SIO 0B: SERIAL LINE CONFIG
 SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
 SIO1ACLK	.EQU	7372800		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO1ACFG	.EQU	SER_115200_8N1	; SIO 1A: SERIAL LINE CONFIG
@@ -183,9 +185,9 @@ FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_DYNO	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
@@ -225,7 +227,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_master.asm

@@ -12,7 +12,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -95,6 +95,8 @@ SKZDIV		.EQU	DIV_1		; UART CLK (CLK2) DIVIDER FOR Z80-512K
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 WDOGIO		.EQU	$6F		; WATCHDOG REGISTER ADR
 ;
+FPENABLE	.EQU	FALSE		; ENABLES FRONT PANEL SWITCHES
+FPBASE		.EQU	$00		; FRONT PANEL I/O PORT BASE ADDRESS
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
@@ -194,7 +196,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
@@ -202,7 +204,7 @@ SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 SIO0BCLK	.EQU	CPUOSC		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
 SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
 SIO1ACLK	.EQU	CPUOSC		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO1ACFG	.EQU	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
@@ -237,9 +239,9 @@ FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_NONE	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 RFCNT		.EQU	1		; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
@@ -280,7 +282,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_NONE	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDMODE		.EQU	SDMODE_NONE	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_mbc.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_MBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_MBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -60,6 +60,8 @@ SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
+FPENABLE	.EQU	FALSE		; ENABLES FRONT PANEL SWITCHES
+FPBASE		.EQU	$00		; FRONT PANEL I/O PORT BASE ADDRESS
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
@@ -132,7 +134,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$B0		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
@@ -166,9 +168,9 @@ FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_MBC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 RFCNT		.EQU	1		; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
@@ -209,7 +211,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_JUHA	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDMODE		.EQU	SDMODE_JUHA	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_mk4.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_MK4		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_MK4		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -66,6 +66,8 @@ SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
+FPENABLE	.EQU	FALSE		; ENABLES FRONT PANEL SWITCHES
+FPBASE		.EQU	$00		; FRONT PANEL I/O PORT BASE ADDRESS
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
@@ -143,7 +145,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$B0		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
@@ -176,9 +178,9 @@ FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_DIDE	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 RFCNT		.EQU	1		; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
@@ -219,7 +221,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MK4	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDMODE		.EQU	SDMODE_MK4	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_n8.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_N8		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_N8		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -68,6 +68,8 @@ SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
+FPENABLE	.EQU	FALSE		; ENABLES FRONT PANEL SWITCHES
+FPBASE		.EQU	$00		; FRONT PANEL I/O PORT BASE ADDRESS
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
@@ -145,7 +147,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$B0		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
@@ -178,9 +180,9 @@ FDENABLE	.EQU	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_N8	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 RFCNT		.EQU	1		; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
@@ -221,7 +223,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_CSIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT]
+SDMODE		.EQU	SDMODE_CSIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	N8_PPI0		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_rcz180.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_RCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -66,6 +66,8 @@ SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
+FPENABLE	.EQU	FALSE		; ENABLES FRONT PANEL SWITCHES
+FPBASE		.EQU	$00		; FRONT PANEL I/O PORT BASE ADDRESS
 DIAGENABLE	.EQU	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
@@ -146,7 +148,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ACFG	.EQU	SER_115200_8N1	; SIO 0A: SERIAL LINE CONFIG
@@ -154,7 +156,7 @@ SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 SIO0BCLK	.EQU	7372800		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0BCFG	.EQU	SER_115200_8N1	; SIO 0B: SERIAL LINE CONFIG
 SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
 SIO1ACLK	.EQU	7372800		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO1ACFG	.EQU	SER_115200_8N1	; SIO 1A: SERIAL LINE CONFIG
@@ -183,9 +185,9 @@ FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
@@ -225,7 +227,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_rcz280.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RCZ280	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_RCZ280	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z280	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -66,6 +66,8 @@ SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
+FPENABLE	.EQU	FALSE		; ENABLES FRONT PANEL SWITCHES
+FPBASE		.EQU	$00		; FRONT PANEL I/O PORT BASE ADDRESS
 DIAGENABLE	.EQU	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
@@ -156,7 +158,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
@@ -164,7 +166,7 @@ SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 SIO0BCLK	.EQU	7372800		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
 SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
 SIO1ACLK	.EQU	7372800		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO1ACFG	.EQU	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
@@ -193,9 +195,9 @@ FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
@@ -235,7 +237,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_rcz80.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RCZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_RCZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -65,6 +65,8 @@ SKZDIV		.EQU	DIV_1		; UART CLK (CLK2) DIVIDER FOR Z80-512K
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 WDOGIO		.EQU	$6E		; WATCHDOG REGISTER ADR
 ;
+FPENABLE	.EQU	FALSE		; ENABLES FRONT PANEL SWITCHES
+FPBASE		.EQU	$00		; FRONT PANEL I/O PORT BASE ADDRESS
 DIAGENABLE	.EQU	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
@@ -150,7 +152,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
@@ -158,7 +160,7 @@ SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 SIO0BCLK	.EQU	CPUOSC		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
 SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
 SIO1ACLK	.EQU	CPUOSC		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO1ACFG	.EQU	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
@@ -187,9 +189,9 @@ FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
@@ -229,7 +231,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_rph.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RPH		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_RPH		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	TRUE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -66,6 +66,8 @@ SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
+FPENABLE	.EQU	FALSE		; ENABLES FRONT PANEL SWITCHES
+FPBASE		.EQU	$00		; FRONT PANEL I/O PORT BASE ADDRESS
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
@@ -167,9 +169,9 @@ FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_N8	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 RFCNT		.EQU	1		; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
@@ -210,7 +212,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_CSIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDMODE		.EQU	SDMODE_CSIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	RPH_PPI0	; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_sbc.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -60,6 +60,8 @@ SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
+FPENABLE	.EQU	FALSE		; ENABLES FRONT PANEL SWITCHES
+FPBASE		.EQU	$00		; FRONT PANEL I/O PORT BASE ADDRESS
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
@@ -132,7 +134,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$B0		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
@@ -161,14 +163,13 @@ MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
 MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
-;
 FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_DIO3	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 RFCNT		.EQU	1		; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
@@ -209,7 +210,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_JUHA	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDMODE		.EQU	SDMODE_JUHA	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_scz180.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_SCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_SCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -66,6 +66,8 @@ SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
+FPENABLE	.EQU	FALSE		; ENABLES FRONT PANEL SWITCHES
+FPBASE		.EQU	$00		; FRONT PANEL I/O PORT BASE ADDRESS
 DIAGENABLE	.EQU	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$0D		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
@@ -146,7 +148,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ACFG	.EQU	SER_115200_8N1	; SIO 0A: SERIAL LINE CONFIG
@@ -154,7 +156,7 @@ SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 SIO0BCLK	.EQU	7372800		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0BCFG	.EQU	SER_115200_8N1	; SIO 0B: SERIAL LINE CONFIG
 SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
 SIO1ACLK	.EQU	7372800		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO1ACFG	.EQU	SER_115200_8N1	; SIO 1A: SERIAL LINE CONFIG
@@ -183,9 +185,9 @@ FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
@@ -225,7 +227,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_SC	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDMODE		.EQU	SDMODE_SC	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_una.asm

@@ -15,10 +15,12 @@
 ;
 #INCLUDE "../UBIOS/ubios.inc"
 ;
-;PLATFORM	.EQU	PLT_UNA		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+;PLATFORM	.EQU	PLT_UNA		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_UNA	; HARDWARE BIOS: BIOS_[WBW|UNA]
 ;
+FPENABLE	.EQU	FALSE		; ENABLES FRONT PANEL SWITCHES
+;
 BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
 ;
 CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO

Source/HBIOS/cfg_z80retro.asm

@@ -0,0 +1,223 @@
+;
+;==================================================================================================
+;   ROMWBW 2.X CONFIGURATION DEFAULTS FOR SIMPLE Z80 RETRO
+;==================================================================================================
+;
+; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
+; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
+; UNDER THIS DIRECTORY.
+;
+; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
+; FOR THE PLATFORM.
+;
+#DEFINE PLATFORM_NAME "Z80Retro", " [", CONFIG, "]"
+;
+#INCLUDE "hbios.inc"
+;
+PLATFORM	.EQU	PLT_Z80RETRO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
+CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+;
+BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+;
+CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.EQU	14745600	; CPU OSC FREQ IN MHZ
+INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;
+RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MPGSEL_0	.EQU	$60		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_1	.EQU	$61		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_2	.EQU	$62		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_3	.EQU	$63		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
+MPGENA		.EQU	$64		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
+;
+RTCIO		.EQU	$70		; RTC LATCH REGISTER ADR
+;
+KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+;
+CTCENABLE	.EQU	TRUE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.EQU	$40		; CTC BASE I/O ADDRESS
+CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER (too fast for RomWBW right now)
+CTCMODE		.EQU	CTCMODE_CTR	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
+CTCPRE		.EQU	256		; PRESCALE CONSTANT (1-256)
+CTCPRECH	.EQU	0		; PRESCALE CHANNEL (0-3)
+CTCTIMCH	.EQU	1		; TIMER CHANNEL (0-3)
+CTCOSC		.EQU	7372800		; CTC CLOCK FREQUENCY
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
+SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+;
+WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+;
+FPENABLE	.EQU	FALSE		; ENABLES FRONT PANEL SWITCHES
+FPBASE		.EQU	$00		; FRONT PANEL I/O PORT BASE ADDRESS
+DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
+DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
+DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
+DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+;
+LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED
+LEDMODE		.EQU	LEDMODE_RTC	; LEDMODE_[STD|RTC]
+LEDPORT		.EQU	$00		; STATUS LED PORT ADDRESS
+LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+;
+DSKYENABLE	.EQU	FALSE		; ENABLES DSKY
+DSKYMODE	.EQU	DSKYMODE_V1	; DSKY VERSION: DSKYMODE_[V1|NG]
+DSKYPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF DSKY PPI
+DSKYOSC		.EQU	3000000		; OSCILLATOR FREQ FOR DSKYNG (IN HZ)
+;
+BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MKYENABLE	.EQU	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+;
+DSRTCENABLE	.EQU	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
+DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+;
+DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+;
+BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+;
+INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+;
+RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
+HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+;
+DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+;
+DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+;
+UARTENABLE	.EQU	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
+UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
+UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
+UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
+UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
+UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
+UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+;
+ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+;
+Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+;
+ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+;
+SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIO0MODE	.EQU	SIOMODE_Z80R	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.EQU	CPUOSC/2	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.EQU	CPUOSC/2	; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1MODE	.EQU	SIOMODE_Z80R	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
+SIO1ACLK	.EQU	CPUOSC/2	; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1ACFG	.EQU	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
+SIO1ACTCC	.EQU	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1BCLK	.EQU	CPUOSC/2	; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1BCFG	.EQU	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
+SIO1BCTCC	.EQU	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+;
+XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+;
+VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
+TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+;
+MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+;
+FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.EQU	FDMODE_ZETA2	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.EQU	1		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+;
+RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+;
+IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+;
+PPIDEENABLE	.EQU	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.EQU	$60		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+;
+SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.EQU	SDMODE_Z80R	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+;
+PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+;
+PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+PPPBASE		.EQU	$60		; PPP: PPI REGISTERS BASE ADDRESS
+PPPSDENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
+PPPSDTRACE	.EQU	1		; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPPCONENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
+;
+HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+;
+LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+;
+PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+PIOSBASE	.EQU	$60		; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
+;
+UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+;
+SN76489ENABLE	.EQU	FALSE		; SN76489 SOUND DRIVER
+AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
+SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+;
+DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+;
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)

Source/HBIOS/cfg_zeta.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_ZETA	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_ZETA	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; BIOS_[WBW|UNA]: HARDWARE BIOS
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -52,6 +52,8 @@ SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
+FPENABLE	.EQU	FALSE		; ENABLES FRONT PANEL SWITCHES
+FPBASE		.EQU	$00		; FRONT PANEL I/O PORT BASE ADDRESS
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
@@ -137,9 +139,9 @@ FDENABLE	.EQU	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_ZETA	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	1		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
@@ -153,7 +155,7 @@ PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
 PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_zeta2.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_ZETA2	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_ZETA2	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -63,6 +63,8 @@ SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
+FPENABLE	.EQU	FALSE		; ENABLES FRONT PANEL SWITCHES
+FPBASE		.EQU	$00		; FRONT PANEL I/O PORT BASE ADDRESS
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
@@ -148,9 +150,9 @@ FDENABLE	.EQU	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_ZETA2	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	1		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
@@ -164,7 +166,7 @@ PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
 PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/fd.asm

@@ -109,7 +109,7 @@ FRC_TOSEEKWT	.EQU	-15H		; EB
 ; FD DEVICE CONFIGURATION
 ;
 FD_DEVCNT	.EQU	FDCNT		; 2 DEVICES SUPPORTED
-FD_CFGSIZ	.EQU	8		; SIZE OF CFG TBL ENTRIES
+FD_CFGSIZ	.EQU	9		; SIZE OF CFG TBL ENTRIES
 ;
 ; PER DEVICE DATA OFFSETS
 ;					; OFFSET OF...
@@ -121,25 +121,28 @@ FD_HST		.EQU	4		; HOSTS SEEK POSITION
 FD_HSTTRK	.EQU	FD_HST + 0	; HOST TRACK (WORD)
 FD_HSTSEC	.EQU	FD_HST + 2	; HOST SECTOR (BYTE)
 FD_HSTHD	.EQU	FD_HST + 3	; HOST HEAD (BYTE)
+FD_TYPE		.EQU	8		; FLOPPY DSIK TYPE (BYTE)
 ;
 FD_CFGTBL:
 	; DEVICE 0, PRIMARY MASTER
 	.DB	0			; DEVICE NUMBER
 	.DB	0			; DEVICE STATUS
-	.DB	FDMEDIA			; MEDIA TYPE
+	.DB	$FF			; CURRENT MEDIA TYPE (INIT TO NONE)
 	.DB	$FF			; CURRENT TRACK
 	.DW	0			; HOST TRACK
 	.DB	0			; HOST SECTOR
 	.DB	0			; HOST HEAD
+	.DB	FD0TYPE			; DRIVE TYPE
 #IF (FD_DEVCNT >= 2)
 	; DEVICE 1, PRIMARY SLAVE
 	.DB	1			; DRIVER DEVICE NUMBER
 	.DB	0			; DEVICE STATUS
-	.DB	FDMEDIA			; MEDIA TYPE
+	.DB	$FF			; CURRENT MEDIA TYPE (INIT TO NONE)
 	.DB	$FF			; CURRENT TRACK
 	.DW	0			; HOST TRACK
 	.DB	0			; HOST SECTOR
 	.DB	0			; HOST HEAD
+	.DB	FD1TYPE			; DRIVE TYPE
 #ENDIF
 ;
 #IF ($ - FD_CFGTBL) != (FD_DEVCNT * FD_CFGSIZ)
@@ -199,6 +202,42 @@ FSST_ENTSIZ	.EQU	$ - FSST
 FSST_COUNT	.EQU	(($ - FSST) / FSST_ENTSIZ)	; # ENTRIES IN TABLE
 #ENDIF
 ;
+; FDC DRIVE TYPE MEDIA OPTIONS
+;
+; THIS TABLE LISTS THE TYPES OF MEDIA THAT SHOULD BE ATTEMPTED
+; FOR EACH POSSIBLE DRIVE TYPE.  THE ENTRIES MATCH THE ORDER OF THE
+; FDT_ VALUES DEFINED IN STD.ASM
+;
+FD_MEDIAMAP:
+		.DW	FDMM_NONE	; NO DRIVE TYPE
+		.DW	FDMM_3DD
+		.DW	FDMM_3HD
+		.DW	FDMM_5DD
+		.DW	FDMM_5HD
+		.DW	FDMM_8
+;
+FDMM_NONE	.DB	$FF
+FDMM_3DD	.DB	FDM720, $FF
+FDMM_3HD	.DB	FDM144, FDM720, $FF
+FDMM_5DD	.DB	FDM360, $FF
+FDMM_5HD	.DB	FDM120, FDM360, $FF
+FDMM_8		.DB	FDM111, $FF
+;
+; FDC DRIVE TYPE ATTRIBUTES
+;
+; LOOKUP TABLE TO MAP THE DEVICE ATTRIBUTES BYTE RETURNED
+; BY THE FD_DEVICE FUNCTION BASED ON THE DRIVE TYPE.
+; THE ENTRIES MATCH THE ORDER OF THE
+; FDT_ VALUES DEFINED IN STD.ASM
+;
+FD_DEVATTR:
+		.DB	%11100000	; DRIVE TYPE NONE
+		.DB	%11010100	; DRIVE TYPE 3.5 DD
+		.DB	%11011000	; DRIVE TYPE 3.5 HD
+		.DB	%10110100	; DRIVE TYPE 5.25 DD
+		.DB	%10111000	; DRIVE TYPE 5.25 HD
+		.DB	%10010100	; DRIVE TYPE 8
+;
 ; FDC COMMANDS
 ;
 CFD_READ	.EQU	00000110B	; CMD,HDS/DS,C,H,R,N,EOT,GPL,DTL --> ST0,ST1,ST2,C,H,R,N
@@ -498,21 +537,11 @@ FD_DEFMED:
 FD_DEVICE:
 	LD	D,DIODEV_FD		; D := DEVICE TYPE
 	LD	E,(IY+FD_DEV)		; E := PHYSICAL DEVICE NUMBER
-#IF (FDMEDIA == FDM720)
-	LD	C,%11010100		; 3.5" DS/DD
-#ENDIF
-#IF (FDMEDIA == FDM144)
-	LD	C,%11011000		; 3.5" DS/HD
-#ENDIF
-#IF (FDMEDIA == FDM360)
-	LD	C,%10110100		; 5.25" DS/DD
-#ENDIF
-#IF (FDMEDIA == FDM120)
-	LD	C,%10111000		; 5.25" DS/HD
-#ENDIF
-#IF (FDMEDIA == FDM111)
-	LD	C,%10010100		; 8" DS/DD
-#ENDIF
+
+	LD	A,(IY+FD_TYPE)		; DRIVE TYPE
+	LD	HL,FD_DEVATTR		; DEVICE ATTR TABLE
+	CALL	ADDHLA			; POINT TO ENTRY
+	LD	C,(HL)			; GET IT
 	LD	H,FDMODE		; H := MODE
 	LD	L,FDC_MSR		; L := BASE I/O ADDRESS
 	XOR	A			; SIGNAL SUCCESS
@@ -527,9 +556,7 @@ FD_MEDIA:
 
 #IF (FDMAUTO)
 	; SETUP TO READ TRK 0, HD 0, SEC 0
-	;LD	A,C			; C STILL HAS REQUESTED DRIVE
 	LD	A,(IY+FD_DEV)		; GET DRIVE UNIT
-	;AND	0FH
 	LD	(FCD_DS),A
 	LD	A,0
 	LD	(FCD_C),A
@@ -538,53 +565,77 @@ FD_MEDIA:
 	LD	(FCD_R),A
 	LD	A,DOP_READID
 	LD	(FCD_DOP),A
+#ENDIF
 
-#IF (FDTRACE < 3)
+
+	LD	A,(IY+FD_TYPE)		; GET DRIVE TYPE VALUE
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	LD	HL,FD_MEDIAMAP		; POINT TO MEDIA MAP TABLE
+	ADD	A,A			; TABLE IS WORD SIZED
+	CALL	ADDHLA			; LOOKUP ENTRY
+	LD	A,(HL)			; DEREFERENCE
+	INC	HL
+	LD	H,(HL)
+	LD	L,A
+
+#IF (FDMAUTO)
+  #IF (FDTRACE < 3)
 	; SUPPRESS TRACING FOR MEDIA TESTS
 	LD	A,0
 	LD	(FCD_TRACE),A
-#ENDIF
-
-	LD	B,5
+  #ENDIF
 
+	LD	B,5			; 5 ATTEMPTS
 FD_MEDIARETRY:
-	; TRY PRIMARY MEDIA CHOICE FIRST
-	LD	A,FDMEDIA
-	CALL	FD_TESTMEDIA
-	JR	Z,FD_MEDIA3		; IF SUCCESS, WE ARE DONE
-
-	; TRY ALTERNATE MEDIA CHOICE
-	LD	A,FDMEDIAALT
-	CALL	FD_TESTMEDIA
-	JR	Z,FD_MEDIA3		; IF SUCCESS, WE ARE DONE
-
-	DJNZ	FD_MEDIARETRY
+	PUSH	HL			; SAVE MEDIA MAP PTR
+	CALL	FD_MEDIALOOP		; TRY IT
+	POP	HL			; RECOVER MEDIA MAP PTR
+	JR	Z,FD_MEDIA3		; CONTINUE ON SUCCESS
+	DJNZ	FD_MEDIARETRY		; LOOP TILL DONE
 
+FD_MEDIARETRY1:
 	; NO JOY, RETURN WITH E=0 (NO MEDIA)
-	;LD	HL,(FDDS_MEDIAADR)
-	;LD	(HL),0			; SET TO NO MEDIA
-	LD	(IY+FD_MEDTYP),0	; SET DRIVE = NO MEDIA
-	LD	E,0
+	LD	(IY+FD_MEDTYP),$FF	; SET MEDIA TYPE TO UNDEFINED
+	LD	E,0			; NO MEDIA FLAG
 	LD	A,ERR_NOMEDIA		; SIGNAL ERROR
 	OR	A			; SET FLAGS
 	RET
 
+FD_MEDIALOOP:
+	LD	A,(HL)			; LOAD NEXT MEDIA TYPE TO TRY
+	CP	$FF			; END OF MEDIA TYPES TO TRY?
+	JR	Z,FD_MEDIALOOP1		; NO MORE TO TRY, LOOP EXIT
+	CALL	FD_TESTMEDIA		; TRY IT
+	RET	Z			; RETURN ON SUCCESS
+	INC	HL			; NEXT MEDIA TYPE TO TRY
+	JR	FD_MEDIALOOP		; LOOP
+FD_MEDIALOOP1:
+	OR	$FF			; SIGNAL FAILURE
+	RET				; RETURN
+
 FD_TESTMEDIA:
-	;LD	HL,(FDDS_MEDIAADR)
-	;LD	(HL),A
+	;CALL	PRTHEXBYTE		; *DEBUG*
 	LD	(IY+FD_MEDTYP),A
+	PUSH	HL
 	PUSH	BC
 	CALL	FD_START
 	POP	BC
+	POP	HL
+	;CALL	PRTHEXBYTE		; *DEBUG*
 	RET
 
 FD_MEDIA3:
 
-#IF (FDTRACE < 3)
+  #IF (FDTRACE < 3)
 	; RESTORE TRACING FOR MEDIA TESTS
 	LD	A,FDTRACE
 	LD	(FCD_TRACE),A
-#ENDIF
+  #ENDIF
+#ELSE
+
+	LD	A,(HL)
+	LD	(IY+FD_MEDTYP),A
+
 #ENDIF
 
 FD_MEDIA4:
@@ -778,7 +829,7 @@ FD_DETECT1:
 ;
 FD_INITUNIT:
 	LD	(IY+FD_STAT),0		; CLEAR STATUS
-	LD	(IY+FD_MEDTYP),FDMEDIA	; SET DEFAULT MEDIA TYPE
+	LD	(IY+FD_MEDTYP),$FF	; SET UNKNOWN MEDIA TYPE
 	LD	(IY+FD_CURTRK),$FE	; SPECIAL VALUE FOR CURTRK
 	RET
 ;
@@ -1285,7 +1336,8 @@ FC_SETUPIO:
 	LD	(DE),A
 	INC	DE
 
-	LD	A,(FCD_EOT)
+	;LD	A,(FCD_EOT)
+	LD	A,(FCD_R)		; READ ONLY ONE SECTOR
 	LD	(DE),A
 	INC	DE
 
@@ -1397,15 +1449,17 @@ FC_RESETFDC:
 ; PULSE TERMCT TO TERMINATE ANY ACTIVE EXECUTION PHASE
 ;
 FC_PULSETC:
-#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC) | (FDMODE == FDMODE_DYNO) | (FDMODE == FDMODE_EPFDC) | (FDMODE == FDMODE_MBC))
-	IN	A,(FDC_TC)
-#ELSE
-	LD	A,(FST_DOR)
-	SET	0,A
-	OUT	(FDC_DOR),A
-	RES	0,A
-	OUT	(FDC_DOR),A
-#ENDIF
+; PULSING TC NO LONGER REQUIRED BECAUSE WE ONLY READ A SINGLE SECTOR
+;
+;#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC) | (FDMODE == FDMODE_DYNO) | (FDMODE == FDMODE_EPFDC) | (FDMODE == FDMODE_MBC))
+;	IN	A,(FDC_TC)
+;#ELSE
+;	LD	A,(FST_DOR)
+;	SET	0,A
+;	OUT	(FDC_DOR),A
+;	RES	0,A
+;	OUT	(FDC_DOR),A
+;#ENDIF
 	RET
 ;
 ; SET FST_DOR FOR MOTOR CONTROL ON
@@ -1694,7 +1748,7 @@ FXR_TO:		; TIMEOUT
 ;
 FXR_ABORT:	; EXECUTION ABORTED
 	HB_EI				; INTERRUPTS OK AGAIN
-	JR	FOP_RES			; GET RSEULTS, NO NEED TO PULSE TC
+	JR	FOP_RES			; GET RESULTS, NO NEED TO PULSE TC
 ;
 FXR_END:	; EXECUTION COMPLETED NORMALLY
 	CALL	FC_PULSETC		; PULSE TC TO END EXECUTION
@@ -1828,7 +1882,9 @@ FOP_EVALST1:
 
 	LD	C,FRC_ENDCYL
 	BIT	7,A
-	JR	NZ,FOP_SETFST
+	; THI IS NORMAL BECAUSE WE NOW READ ONLY A SINGLE SECTOR
+	;JR	NZ,FOP_SETFST
+	JR	NZ,FOP_EXIT
 
 	LD	C,FRC_DATAERR
 	BIT	5,A

Source/HBIOS/hbios.asm

@@ -22,7 +22,7 @@
 ;   SYSTEM INITIALIZATION, THE IMAGE OF THE RUNNING ROM BANK IS COPIED TO A RAM BANK
 ;   CREATING A SHADOW COPY IN RAM.  EXECUTION IS THAN TRANSFERRED TO THE RAM SHADOW COPY.
 ;   THIS IS ESSENTIAL BECAUSE THE HBIOS CODE DOES NOT SUPPORT RUNNING IN READ ONLY MEMORY
-;   (EXCEPT FOR THE INITIAL LAUNCHING CODE).  IN THIS MODE, THE HBIOS INITIALIZATION WILL
+;   (EXCEPT FOR THE INITIAL LAUNCHING CODE).  IN THIS MODE, THE HBI OS INITIALIZATION WILL
 ;   ALSO COPY THE OS IMAGES BANK IN ROM TO THE USER RAM BANK AND LAUNCH IT AFTER HBIOS
 ;   IS INSTALLED.
 ;
@@ -1908,7 +1908,7 @@ HB_CPU1:
 ; LATER.
 ;
 	CALL	HB_CPUSPD		; DYNAMIC CPU SPEED DETECTION
-	JR	NZ,HB_CPUSPD2		; SKIP AHEAD IF FAILED
+	JR	NZ,HB_CPU2		; SKIP AHEAD IF FAILED
 ;
 ; RECORD THE UPDATED CPU OSCILLATOR SPEED
 ;
@@ -1921,7 +1921,7 @@ HB_CPU1:
 ;
 	LD	(HB_CPUOSC),HL		; RECORD MEASURED SPEED
 ;
-HB_CPUSPD2:
+HB_CPU2:
 ;
 ; INIT CPUKHZ BASED ON OSCILLATOR SPEED
 ;
@@ -2232,6 +2232,29 @@ NOT_REC_M0:
 	CALL	DSKY_SHOW
 #ENDIF
 ;
+#IF FPENABLE
+;
+; IF FRONT PANEL IS ENABLED IN CONFIG, WE NEED TO CHECK TO SEE IF THE
+; HARDWARE REALLY EXISTS.  THE ONLY WAY TO DO THAT IS TO SEE IF THE
+; FRONT PANEL PORT SEEMS TO BE VALID (NOT FLOATING).  HERE WE JUST
+; DO THE CHECKING AND RECORD WHETHER THE FP SWITCHES ARE USEABLE.
+;
+	; THE SWITCH HARDWARE MAY OR MAY NOT BE INSTALLED.  SO, HERE WE
+	; ATTEMPT TO CONFIRM WE HAVE A VALID PORT.  CREDIT TO STEPHEN
+	; COUSINS FOR THIS APPROACH.
+	LD	C,FPBASE		; ADR OF SWITCH PORT
+	IN	C,(C)			; READ IT USING IN (C)
+	IN	A,(FPBASE)		; READ IT USING IN (PORT)
+	CP	C			; PORT FLOATING ON MISMATCH
+	JR	NZ,HB_SWZ		; ABORT IF FLOATING
+	CP	$FF			; $FF ALSO MEANS PORT INACTIVE
+	JR	Z,HB_SWZ		; ABORT IF SO
+	OR	$FF			; SIGNAL FP EXISTS
+	LD	(HB_HASFP),A		; AND SAVE IT
+HB_SWZ:
+;
+#ENDIF
+;
 #IF FALSE
 ;
 ; TEST DEBUG ***************************************************************************************
@@ -2248,7 +2271,6 @@ NOT_REC_M0:
 ;
 ;
 ;
-;
 #IF (BOOT_DELAY > 100)
 	.ECHO	"*** ERROR: INVALID BOOT_DELAY (BOOT_DELAY > 100)!!!\n"
 	!!!	; FORCE AN ASSEMBLY ERROR
@@ -2274,6 +2296,29 @@ HB_BOOTDLY:
 	LD	A,BOOTCON		; GET REQUESTED CONSOLE DEV
 	LD	(CB_CONDEV),A		; SAVE IT
 HB_CONRDY:
+;
+; MOST SERIAL PORTS ARE CONFIGURED WITH HARDWARE FLOW CONTROL ENABLED.
+; IF THERE IS A PROBLEM WITH THE RTS SIGNAL, THEN OUTPUT TO THE CONSOLE
+; WILL BE STALLED WHICH CAN LEAD A USER TO THINK THE SYSTEM IS TOTALLY
+; DEAD WHEN, IN FACT, IT IS JUST WAITING FOR RTS TO BE ASSERTED.  ALSO,
+; IF THE USER IS BOOTING TO A CRT DEVICE AND DISCONNECTS THE CONSOLE
+; SERIAL PORT, THE SYSTEM WILL WAIT FOR RTS AND NEVER BOOT.  SO, HERE
+; WE SAVE THE ACTIVE CONSOLE CONFIGURATION, THEN TURN OFF HARDWARE
+; FLOW CONTROL.  THE ORIGINAL CONFIGURATION WILL BE RESTORED BELOW
+; PRIOR TO LAUNCING THE ROM LOADER.
+;
+	; RETRIEVE THE CONFIG FROM THE CONSOLE PORT
+	LD	B,BF_CIOQUERY		; HBIOS QUERY CIO CONFIG
+	LD	A,(CB_CONDEV)		; GET CONSOLE DEVICE
+	LD	(HB_BOOTCON),A		; SAVE IT FOR LATER
+	LD	C,A			; BOOT CONSOLE TO C
+	CALL	HB_DISPATCH		; INTERNAL HBIOS CALL
+	LD	(HB_BOOTCFG),DE		; SAVE CONFIG
+	RES	5,D			; CLEAR RTS BIT
+	LD	B,BF_CIOINIT		; HBIOS CIO INIT
+	LD	A,(CB_CONDEV)		; GET CONSOLE DEVICE
+	LD	C,A			; BOOT CONSOLE TO C
+	CALL	HB_DISPATCH		; INTERNAL HBIOS CALL
 
 #IF (WBWDEBUG == USEMIO)		; OUTPUT ANY CACHED DEBUG TEXT
 	LD	HL,MIOOUTPTR
@@ -2720,8 +2765,10 @@ HB_WDZ:
 	LD	HL,(CB_HEAPTOP)
 	LD	(HEAPCURB),HL
 ;
-; NOW SWITCH TO CRT CONSOLE IF CONFIGURED
+; NOW SWITCH CONSOLES IF CONFIGURED
 ;
+	LD	A,(CB_CONDEV)		; GET CURRENT CONSOLE
+	LD	(HB_NEWCON),A		; AND INIT NEW CONSOLE VAR
 #IF CRTACT
 ;
 ; BIOS IS CONFIGURED TO AUTO ACTIVATE CRT DEVICE.  FIRST,
@@ -2740,20 +2787,107 @@ HB_WDZ:
 	JR	Z,INITSYS3		; Z=SHORTED, BYPASS CONSOLE SWITCH
   #ENDIF
 ;
-	; NOTIFY USER OF CONSOLE SWITCH ON BOOT CONSOLE
-	CALL	NEWLINE2
-	PRTX(STR_SWITCH)
-	CALL	NEWLINE
-;
-	; SWITCH TO CRT CONSOLE
 	LD	A,(CB_CRTDEV)		; GET CRT DISPLAY DEVICE
-	LD	(CB_CONDEV),A		; SAVE IT AS ACTIVE CONSOLE DEVICE
+	LD	(HB_NEWCON),A		; AND QUEUE TO SWITCH
+;
+#ENDIF
+;
+#IF FPENABLE
+;
+; IF WE HAVE FRONT PANEL SWITCHES, THIS IS THE RIGHT PLACE TO HANDLE
+; ANY CONSOLE CHANGE REQUESTS.  THE FRONT PANEL HAS TWO SWITCHES
+; RELATED TO THIS: 1) CRT/SER, AND 2) SEC/PRI.  IF CRT/SER IS SET,
+; THEN WE SWITCH TO THE CRT DEVICE (IF THERE IS ONE).  IF THE SEC/PRI
+; SWITCH IS SET, THEN WE ATTEMPT TO USE THE SECOND SERIAL OR CRT
+; DEVICE.
+;
+	PRTS("\r\nFP: IO=0x$")
+	LD	A,FPBASE
+	CALL	PRTHEXBYTE
+;
+	; THE EXISTENCE OF THE FP WAS TESTED EARLIER.  IF IT DOESN'T
+	; EXIST, BAIL OUT.
+	LD	A,(HB_HASFP)		; GET FP EXISTENCE FLAG
+	OR	A			; SET FLAGS
+	JR	NZ,HB_FP1		; IF WE HAVE ONE, CONTINUE
+;
+	; HANDLE NO FP
+	PRTS(" NOT PRESENT$")
+	JR	HB_FPZ
+;
+HB_FP1:
+	; WE NOW BELIEVE WE HAVE A VALID SWITCH SETTINGS VALUE.
+	; CHECK FOR CRT SWITCH VALUE AND SWITCH TO CRT IF SET.
+	; NOTE THAT CB_CRTDEV WILL BE ZERO IF THERE IS NO CRT DEVICE
+	; IN THE SYSTEM, SO WE DON'T NEED TO CHECK FOR THE EXISTENCE
+	; OF A CRT DEVICE -- IT WILL JUST FAILBACK TO FIRST SERIAL
+	; PORT.
+	PRTS(" SWITCHES=0x$")		; TAG
+	IN	A,(FPBASE)		; GET SWITCH SETTINGS
+	CALL	PRTHEXBYTE		; DISPLAY VALUE
+	LD	B,A			; SAVE IN REG B
+	AND	SW_CRT			; TEST CRT BIT
+	JR	Z,HB_FP2		; SKIP AHEAD IF NOT SET
+	LD	A,(CB_CRTDEV)		; GET CRT DISPLAY DEVICE
+	CP	$FF			; $FF MEANS NO CRT PRESENT
+	JR	Z,HB_FP2		; BYPASS IF SO
+	LD	(HB_NEWCON),A		; QUEUE NEW CONSOLE UNIT
+;
+HB_FP2:
+	; IF SEC SWITCH IS SET, WE WANT TO BUMP TO SECONDARY
+	; CRT OR SERIAL DEVICE.  FOR NOW, WE ARE GOING TO CHEAT AND
+	; JUST INCREMENT THE CONSOLE DEVICE UNIT.  THIS SHOULD WORK
+	; ASSUMING NORMAL ORDERING OF THE CHARACTER DEVICE UNITS.
+	LD	A,B			; RECOVER SWITCH SETTINGS
+	AND	SW_SEC			; TEST SEC BIT
+	JR	Z,HB_FPZ		; IF NOT SET, THEN ALL DONE
+;
+	; INCREMENT CONSOLE UNIT, BUT MAKE SURE IT DOES NOT EXCEED
+	; THE HIGHEST CHAR UNIT IN SYSTEM.
+	LD	A,(CIO_CNT)		; GET CHAR UNIT COUNT
+	LD	B,A			; MOVE TO B
+	LD	A,(HB_NEWCON)		; GET NEW CONSOLE UNIT
+	INC	A			; BUMP TO SECONDARY
+	CP	B			; A (UNIT) >= B (CNT)?
+	JR	NC,HB_FPZ		; ABORT IF UNIT TOO HIGH
+	LD	(HB_NEWCON),A		; UPDATE NEW CONSOLE UNIT
+;
+HB_FPZ:
 ;
-	; DISPLAY HBIOS BANNER ON NEW CONSOLE
-	PRTX(STR_BANNER)
 #ENDIF
 ;
 INITSYS3:
+;
+; IF WE ARE GOING TO SWITCH CONSOLES, IT IS IMPLEMENTED HERE.  A
+; MESSAGE IS PRINTED ON THE OLD CONSOLE INDICATING WHERE THE NEW
+; CONSOLE IS AND THE NEW CONSOLE RECEIVES AN HBIOS BANNER.
+;
+	LD	A,(HB_BOOTCON)		; GET ORIGINAL BOOT CONSOLE DEV
+	LD	C,A			; PUT IN C
+	LD	A,(HB_NEWCON)		; GET NEW CONSOLE DEVICE
+	CP	C			; COMPARE
+	JR	Z,INITSYS3A		; NO CHANGE, BYPASS
+;
+	LD	DE,STR_CONSOLE		; CONSOLE CHANGE NOTIFY
+	CALL	WRITESTR		; PRINT IT
+	LD	A,(HB_NEWCON)		; GET NEW CONSOLE UNIT NUM
+	CALL	PRTDECB			; PRINT UNIT NUM
+	LD	(CB_CONDEV),A		; IMPLEMENT NEW CONSOLE!
+	CALL	NEWLINE2		; FORMATTING
+	LD	DE,STR_BANNER		; POINT TO BANNER
+	CALL	NZ,WRITESTR		; OUTPUT IF CONSOLE MOVED
+;
+INITSYS3A:
+;
+; RESTORE BOOT CONSOLE CONFIGURATION
+;
+	CALL	LDELAY			; ALLOW SERIAL PORT TO FLUSH
+	LD	B,BF_CIOINIT		; HBIOS CIO INIT
+	LD	A,(HB_BOOTCON)		; ORIGINAL BOOT CONSOLE DEVICE
+	LD	C,A			; BOOT CONSOLE TO C
+	LD	DE,(HB_BOOTCFG)		; SAVED ORIGINAL CONSOLE CFG
+	CALL	HB_DISPATCH		; INTERNAL HBIOS CALL
+;
 	CALL	PRTSUM			; PRINT UNIT/DEVICE SUMMARY TABLE
 ;
 #IF 0
@@ -4115,9 +4249,130 @@ SYS_GET:
 	JP	Z,SYS_GETBNKINFO
 	CP	BF_SYSGET_CPUSPD
 	JP	Z,SYS_GETCPUSPD
+	CP	BF_SYSGET_PANEL
+	JP	Z,SYS_GETPANEL
 	SYSCHKERR(ERR_NOFUNC)		; SIGNAL ERROR
 	RET
 ;
+; GET SERIAL UNIT COUNT
+;
+SYS_GETCIOCNT:
+	LD	A,(CIO_CNT)		; GET DEVICE COUNT (FIRST BYTE OF LIST)
+	LD	E,A			; PUT IT IN E
+	XOR	A			; SIGNALS SUCCESS
+	RET
+;
+; GET SERIAL UNIT API FN ADR AND DATA ADR
+;   ENTRY:
+;     D: FUNCTION
+;     E: UNIT
+;   RETURNS:
+;     HL: FUNCTION ADDRESS
+;     DE: DATA BLOB ADDRESS
+;
+SYS_GETCIOFN:
+	BIT	7,E			; CHECK FOR SPECIAL UNIT CODE
+	CALL	NZ,SYS_GETCIOFN1	; IF SO, HANDLE IT
+	LD	IY,CIO_TBL		; POINT TO UNIT TABLE
+	JP	SYS_GETFN		; GO TO COMMON CODE
+;
+SYS_GETCIOFN1:
+	LD	A,(CB_CONDEV)		; UNIT $80 -> CONSOLE UNIT
+	LD	E,A			; REPLACE UNIT VALUE IN C
+	RET				; AND BACK TO REGULAR FLOW
+;
+;
+; GET DISK UNIT COUNT
+;
+SYS_GETDIOCNT:
+	LD	A,(DIO_CNT)		; GET DEVICE COUNT (FIRST BYTE OF LIST)
+	LD	E,A			; PUT IT IN E
+	XOR	A			; SIGNALS SUCCESS
+	RET
+;
+; GET DISK UNIT API FN ADR AND DATA ADR
+;   ENTRY:
+;     D: FUNCTION
+;     E: UNIT
+;   RETURNS:
+;     HL: FUNCTION ADDRESS
+;     DE: DATA BLOB ADDRESS
+;
+SYS_GETDIOFN:
+	LD	IY,DIO_TBL		; POINT TO UNIT TABLE
+	JP	SYS_GETFN		; GO TO COMMON CODE
+;
+; GET RTC UNIT COUNT
+;
+SYS_GETRTCCNT:
+	LD	E,0			; ASSUME 0 RTC DEVICES
+	LD	A,(RTC_DISPACT)		; IS RTC ACTIVE?
+	OR	A			; SET FLAGS
+	JR	Z,SYS_GETRTCCNT1	; IF NONE, DONE
+	INC	E			; SET ONE DEVICE
+SYS_GETRTCCNT1:
+	XOR	A			; SIGNALS SUCCESS
+	RET
+;
+; GET VIDEO UNIT COUNT
+;
+SYS_GETVDACNT:
+	LD	A,(VDA_CNT)		; GET DEVICE COUNT (FIRST BYTE OF LIST)
+	LD	E,A			; PUT IT IN E
+	XOR	A			; SIGNALS SUCCESS
+	RET
+;
+; GET VIDEO UNIT API FN ADR AND DATA ADR
+;   ENTRY:
+;     D: FUNCTION
+;     E: UNIT
+;   RETURNS:
+;     HL: FUNCTION ADDRESS
+;     DE: DATA BLOB ADDRESS
+;
+SYS_GETVDAFN:
+	LD	IY,VDA_TBL		; POINT TO UNIT TABLE
+	JP	SYS_GETFN		; GO TO COMMON CODE
+;
+; GET SOUND UNIT COUNT
+;
+SYS_GETSNDCNT:
+	LD	A,(SND_CNT)		; GET DEVICE COUNT (FIRST BYTE OF LIST)
+	LD	E,A			; PUT IT IN E
+	XOR	A			; SIGNALS SUCCESS
+	RET
+;
+; GET SOUND UNIT API FN ADR AND DATA ADR
+;   ENTRY:
+;     D: FUNCTION
+;     E: UNIT
+;   RETURNS:
+;     HL: FUNCTION ADDRESS
+;     DE: DATA BLOB ADDRESS
+;
+SYS_GETSNDFN:
+	LD	IY,SND_TBL		; POINT TO UNIT TABLE
+	JP	SYS_GETFN		; GO TO COMMON CODE
+;
+; SHARED CODE TO COMPLETE A FUNCTION LOOKUP
+; ENTRY:
+;   IY: DISPATCH FUNCTION TABLE
+;   D: FUNCTION ID
+;   E: UNIT NUMBER
+; EXIT:
+;   HL: DRIVER FUNCTION ADDRESS
+;   DE: DRIVER UNIT DATA ADDRESS
+;
+SYS_GETFN:
+	LD	A,D			; GET FUNC NUM FROM D
+	LD	B,A			; AND PUT IN B
+	LD	A,E			; GET UNIT NUM FROM E
+	LD	C,A			; AND PUT IN C
+	CALL	HB_DISPCALC		; CALC FN ADR & BLOB ADR
+	PUSH	IY			; MOVE DATA ADR
+	POP	DE			; ... TO DE
+	RET				; AF STILL HAS RESULT OF CALC
+;
 ; GET TIMER
 ;   RETURNS:
 ;     DE:HL: TIMER VALUE (32 BIT)
@@ -4275,124 +4530,27 @@ SYS_GETCPUSPD1:
 	OR	$FF
 	RET
 ;
-; GET SERIAL UNIT COUNT
-;
-SYS_GETCIOCNT:
-	LD	A,(CIO_CNT)		; GET DEVICE COUNT (FIRST BYTE OF LIST)
-	LD	E,A			; PUT IT IN E
-	XOR	A			; SIGNALS SUCCESS
-	RET
-;
-; GET SERIAL UNIT API FN ADR AND DATA ADR
-;   ENTRY:
-;     D: FUNCTION
-;     E: UNIT
+; GET FRONT PANEL SWITCH VALUES BYTE
 ;   RETURNS:
-;     HL: FUNCTION ADDRESS
-;     DE: DATA BLOB ADDRESS
+;     L: SWITCH VALUES BYTE
 ;
-SYS_GETCIOFN:
-	BIT	7,E			; CHECK FOR SPECIAL UNIT CODE
-	CALL	NZ,SYS_GETCIOFN1	; IF SO, HANDLE IT
-	LD	IY,CIO_TBL		; POINT TO UNIT TABLE
-	JP	SYS_GETFN		; GO TO COMMON CODE
+SYS_GETPANEL:
 ;
-SYS_GETCIOFN1:
-	LD	A,(CB_CONDEV)		; UNIT $80 -> CONSOLE UNIT
-	LD	E,A			; REPLACE UNIT VALUE IN C
-	RET				; AND BACK TO REGULAR FLOW
-;
-;
-; GET DISK UNIT COUNT
-;
-SYS_GETDIOCNT:
-	LD	A,(DIO_CNT)		; GET DEVICE COUNT (FIRST BYTE OF LIST)
-	LD	E,A			; PUT IT IN E
-	XOR	A			; SIGNALS SUCCESS
-	RET
-;
-; GET DISK UNIT API FN ADR AND DATA ADR
-;   ENTRY:
-;     D: FUNCTION
-;     E: UNIT
-;   RETURNS:
-;     HL: FUNCTION ADDRESS
-;     DE: DATA BLOB ADDRESS
-;
-SYS_GETDIOFN:
-	LD	IY,DIO_TBL		; POINT TO UNIT TABLE
-	JP	SYS_GETFN		; GO TO COMMON CODE
-;
-; GET RTC UNIT COUNT
-;
-SYS_GETRTCCNT:
-	LD	E,0			; ASSUME 0 RTC DEVICES
-	LD	A,(RTC_DISPACT)		; IS RTC ACTIVE?
+#IF FPENABLE
+	LD	A,(HB_HASFP)		; GET FP EXISTS FLAG
 	OR	A			; SET FLAGS
-	JR	Z,SYS_GETRTCCNT1	; IF NONE, DONE
-	INC	E			; SET ONE DEVICE
-SYS_GETRTCCNT1:
-	XOR	A			; SIGNALS SUCCESS
-	RET
-;
-; GET VIDEO UNIT COUNT
-;
-SYS_GETVDACNT:
-	LD	A,(VDA_CNT)		; GET DEVICE COUNT (FIRST BYTE OF LIST)
-	LD	E,A			; PUT IT IN E
-	XOR	A			; SIGNALS SUCCESS
-	RET
-;
-; GET VIDEO UNIT API FN ADR AND DATA ADR
-;   ENTRY:
-;     D: FUNCTION
-;     E: UNIT
-;   RETURNS:
-;     HL: FUNCTION ADDRESS
-;     DE: DATA BLOB ADDRESS
-;
-SYS_GETVDAFN:
-	LD	IY,VDA_TBL		; POINT TO UNIT TABLE
-	JP	SYS_GETFN		; GO TO COMMON CODE
-;
-; GET SOUND UNIT COUNT
-;
-SYS_GETSNDCNT:
-	LD	A,(SND_CNT)		; GET DEVICE COUNT (FIRST BYTE OF LIST)
-	LD	E,A			; PUT IT IN E
-	XOR	A			; SIGNALS SUCCESS
-	RET
-;
-; GET SOUND UNIT API FN ADR AND DATA ADR
-;   ENTRY:
-;     D: FUNCTION
-;     E: UNIT
-;   RETURNS:
-;     HL: FUNCTION ADDRESS
-;     DE: DATA BLOB ADDRESS
-;
-SYS_GETSNDFN:
-	LD	IY,SND_TBL		; POINT TO UNIT TABLE
-	JP	SYS_GETFN		; GO TO COMMON CODE
-;
-; SHARED CODE TO COMPLETE A FUNCTION LOOKUP
-; ENTRY:
-;   IY: DISPATCH FUNCTION TABLE
-;   D: FUNCTION ID
-;   E: UNIT NUMBER
-; EXIT:
-;   HL: DRIVER FUNCTION ADDRESS
-;   DE: DRIVER UNIT DATA ADDRESS
-;
-SYS_GETFN:
-	LD	A,D			; GET FUNC NUM FROM D
-	LD	B,A			; AND PUT IN B
-	LD	A,E			; GET UNIT NUM FROM E
-	LD	C,A			; AND PUT IN C
-	CALL	HB_DISPCALC		; CALC FN ADR & BLOB ADR
-	PUSH	IY			; MOVE DATA ADR
-	POP	DE			; ... TO DE
-	RET				; AF STILL HAS RESULT OF CALC
+	JR	Z,SYS_GETPANEL1		; HANDLE NOT EXISTS
+	IN	A,(FPBASE)		; READ SWITCHES
+	LD	H,0			; FOR FUTURE
+	LD	L,A			; PUT SWITCHES VALUE IN L
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
+#ENDIF
+SYS_GETPANEL1:	; HANDLE NON-EXISTENT FRONT PANEL
+	LD	HL,0			; ZERO RESULT VALUE
+	LD	A,ERR_NOHW		; NO HARDWARE ERR
+	OR	A			; SET FLAGS
+	RET				; DONE
 ;
 ; SET SYSTEM PARAMETERS
 ; PARAMETER(S) TO SET INDICATED IN C
@@ -4407,6 +4565,8 @@ SYS_SET:
 	JR	Z,SYS_SETBOOTINFO
 	CP	BF_SYSSET_CPUSPD
 	JR	Z,SYS_SETCPUSPD
+	CP	BF_SYSSET_PANEL
+	JP	Z,SYS_SETPANEL
 	SYSCHKERR(ERR_NOFUNC)		; SIGNAL ERROR
 	RET
 ;
@@ -4682,6 +4842,23 @@ SYS_SETCPUSPD_ERR:
 	OR	$FF			; NOT SUPPORTED
 	RET
 ;
+; SET FRONT PANEL LEDS
+;   ON ENTRY:
+;     L: LED VALUES BYTE
+;
+SYS_SETPANEL:
+;
+#IF DIAGENABLE
+	LD	A,L
+	OUT	(DIAGPORT),A
+	XOR	A
+	RET
+#ELSE
+	LD	A,ERR_NOHW		; NO HARDWARE ERR
+	OR	A			; SET FLAGS
+	RET
+#ENDIF
+;
 ; RETURN A BYTE OF MEMORY FROM SPECIFIED BANK
 ; ENTRY: D=BANK ID, HL=ADDRESS
 ; RETURN: E=BYTE VALUE
@@ -6286,27 +6463,33 @@ HB_CPUSPD1:
   #ENDIF
 
 	; WAIT FOR AN INITIAL TICK TO ALIGN, THEN WAIT
-	; FOR SECOND TICK AND TO GET A FULL ONE SECOND LOOP COUNT
+	; FOR A SECOND TICK TO GET A FULL ONE SECOND LOOP COUNT.
+	; WAITSEC WILL SET ZF IF AN OVERFLOW OCCURS (MEANING THAT THE
+	; CLOCK IS NOT TICKING).  THERE IS NO
+	; POINT IN CALLING HB_WAITSEC AGAIN IN THAT CASE, SO WE ONLY
+	; CALL HB_WAITSEC AGAIN IF ZF IS NOT SET.
 	CALL	DSRTC_START
 	CALL	HB_RDSEC		; GET SECONDS
 	LD	(HB_CURSEC),A		; AND INIT CURSEC
 	CALL	HB_WAITSEC		; WAIT FOR SECONDS TICK
 	LD	(HB_CURSEC),A		; SAVE NEW VALUE
-	CALL	HB_WAITSEC		; WAIT FOR SECONDS TICK
+	; CALL HB_WAITSEC AGAIN, BUT ONLY IF ZF IS NOT SET
+	CALL	NZ,HB_WAITSEC		; WAIT FOR SECONDS TICK
 ;
   #IF (CPUFAM == CPU_Z180)
 	; RESTORE W/S SETTINGS FROM BEFORE TEST
 	POP	AF
 	OUT0	(Z180_DCNTL),A
   #ENDIF
-;
-	LD	A,H
-	OR	L
-	RET	Z			; FAILURE, USE DEFAULT CPU SPEED
 ;
 	; MOVE LOOP COUNT TO HL
 	PUSH	DE
 	POP	HL
+;
+	; CHECK FOR OVERFLOW (NOT TICKING)
+	LD	A,H
+	OR	L
+	JR	Z,HB_CPUSPD2		; FAILURE, USE DEFAULT CPU SPEED
 ;
 	; TIMES 4 FOR CPU SPEED IN KHZ
 ;	RES	0,L			; GRANULARITY
@@ -6322,6 +6505,7 @@ HB_CPUSPD1:
 HB_WAITSEC:
 	; WAIT FOR SECONDS TICK
 	; RETURN SECS VALUE IN A, LOOP COUNT IN DE
+	; ZF IS SET ON OVERFLOW (CLOCK NOT TICKING)
 	LD	DE,0			; INIT LOOP COUNTER
 HB_WAITSEC1:
 ;
@@ -6366,14 +6550,14 @@ HB_RDSEC:
 	CALL	DSRTC_END		; FINISH IT
 	LD	A,E			; VALUE TO A
 	RET
-;
-  #ELSE
-;
-	OR	$FF			; SIGNAL ERROR
-	RET				; NO RTC, ABORT
 ;
 #ENDIF
 ;
+HB_CPUSPD2:
+	; HANDLE NO RTC OR NOT TICKING
+	OR	$FF			; SIGNAL ERROR
+	RET				; AND DONE
+;
 ; SYSTEM CHECK: DUMP MACHINE STATE AND CONTINUE?
 ;
 SYSCHKA:
@@ -7238,7 +7422,8 @@ HB_BOOT_REC	.DB	0		; BOOT MODE (0=NORMAL, 1=RECOVERY MODE)
 ;
 STR_BANNER	.DB	"RomWBW HBIOS v", BIOSVER, ", ", TIMESTAMP, "$"
 STR_PLATFORM	.DB	PLATFORM_NAME, "$"
-STR_SWITCH	.DB	"*** Activating CRT Console ***$"
+;STR_SWITCH	.DB	"*** Activating CRT Console ***$"
+STR_CONSOLE	.DB	"\r\n\r\n  Console on Unit #$"
 STR_BADINT	.DB	"\r\n*** BAD INT ***\r\n$"
 STR_LOWBAT	.DB	"\r\n\r\n+++ LOW BATTERY +++$"
 ;
@@ -7262,6 +7447,12 @@ HB_CURSEC	.DB	0		; CURRENT SECOND (TEMP)
 ;
 HB_BCDTMP	.FILL	5,0		; BCD NUMBER STORAGE (TEMP)
 ;
+HB_BOOTCON	.DB	0		; INITIAL BOOT CONSOLE SAVE AREA
+HB_BOOTCFG	.DW	0		; CONSOLE CONFIG SAVE AREA
+HB_NEWCON	.DB	0		; NEW CONSOLE TO SWITCH TO
+;
+HB_HASFP	.DB	0		; NON-ZERO MEANS FP EXISTS
+;
 HB_WRKBUF	.FILL	512,0		; INTERNAL DISK BUFFER
 ;
 HB_END		.EQU	$

Source/HBIOS/hbios.inc

@@ -109,11 +109,13 @@ BF_SYSGET_CPUINFO	.EQU	$F0	; GET CPU INFORMATION
 BF_SYSGET_MEMINFO	.EQU	$F1	; GET MEMORY CAPACTITY INFO
 BF_SYSGET_BNKINFO	.EQU	$F2	; GET BANK ASSIGNMENT INFO
 BF_SYSGET_CPUSPD	.EQU	$F3	; GET CLOCK SPEED & WAIT STATES
+BF_SYSGET_PANEL		.EQU	$F4	; GET FRONT PANEL SWITCHES VAL
 ;
 BF_SYSSET_TIMER		.EQU	$D0	; SET TIMER VALUE
 BF_SYSSET_SECS		.EQU	$D1	; SET SECONDS VALUE
 BF_SYSSET_BOOTINFO	.EQU	$E0	; SET BOOT INFORMATION
 BF_SYSSET_CPUSPD	.EQU	$F3	; SET CLOCK SPEED & WAIT STATES
+BF_SYSSET_PANEL		.EQU	$F4	; SET FRONT PANEL LEDS
 ;
 BF_SYSINT_INFO		.EQU	$00	; GET INTERRUPT SYSTEM INFO
 BF_SYSINT_GET		.EQU	$10	; GET INT VECTOR ADDRESS
@@ -137,6 +139,7 @@ PLT_DYNO	.EQU	11		; DYNO MICRO-ATX MOTHERBOARD
 PLT_RCZ280	.EQU	12		; RCBUS W/ Z280
 PLT_MBC		.EQU	13		; MULTI BOARD COMPUTER
 PLT_RPH		.EQU	14		; RHYOPHYRE GRAPHICS COMPUTER
+PLT_Z80RETRO	.EQU	15		; Z80 RETRO COMPUTER
 ;
 ; HBIOS GLOBAL ERROR RETURN VALUES
 ;
@@ -261,6 +264,15 @@ DIAG_08 .EQU 11111111B ; ON
 DIAG_09 .EQU 11111111B ; ON 
 #ENDIF
 ;
+; FRONT PANEL SWITCHES
+;
+SW_CRT		.EQU	%10000000	; CRT/SER CONSOLE
+SW_SEC		.EQU	%01000000	; SEC/PRI CONSOLE
+SW_AUTO		.EQU	%00100000	; AUTO/MENU BOOT
+SW_DISK		.EQU	%00010000	; DISK/ROM
+SW_FLOP		.EQU	%00001000	; FLOP/HD
+SW_OPT		.EQU	%00000111	; SLICE/ROM APP
+;
 ; MEDIA ID VALUES
 ;
 MID_NONE	.EQU	0

Source/HBIOS/romldr.asm

@@ -180,6 +180,30 @@ start1:
 	call	pstr			; do it
 	call	clrbuf			; zero fill the cmd buffer
 ;
+#if (BIOS == BIOS_WBW)
+;
+	ld	b,BF_SYSGET		; HBIOS SysGet
+	ld	c,BF_SYSGET_PANEL	; ... Panel swiches value
+	rst	08			; do it
+	jr	nz,nofp			; no switches, skip over
+	ld	a,l			; put value in A
+	ld	(switches),a		; save it
+;
+	call	nl			; formatting
+	ld	hl,str_switches		; tag
+	call	pstr			; display
+	ld	a,(switches)		; get switches value
+	call	prthexbyte		; display
+;
+	ld	a,(switches)		; get switches value
+	and	SW_AUTO			; auto boot?
+	call	nz,runfp		; process front panel
+;
+nofp:
+	; fall thru
+;
+#endif
+;
 #if (BOOT_TIMEOUT != -1)
 	; Initialize auto command timeout downcounter
 	or	$FF			; auto cmd active value
@@ -212,12 +236,12 @@ prompt:
 	ld	hl,msg_sel		; boot select msg
 	call	DSKY_SHOW		; show on DSKY
 
- #IF (DSKYMODE == DSKYMODE_NG)
+ #if (DSKYMODE == DSKYMODE_NG)
 	call 	DSKY_PUTLED
 	.db 	$3f,$3f,$3f,$3f,$00,$00,$00,$00
 	call 	DSKY_BEEP
 	call 	DSKY_L2ON
- #ENDIF
+ #endif
 
 #endif
 ;
@@ -366,6 +390,125 @@ runcmd2:
 	ld	(bootslice),a		; save boot slice
 	jp	diskboot		; boot the disk unit/slice
 ;
+#if (BIOS == BIOS_WBW)
+;
+;=======================================================================
+; Process Front Panel switches
+;=======================================================================
+;
+runfp:
+	ld	a,(switches)		; get switches value
+	and	SW_DISK			; disk boot?
+	jr	nz,fp_diskboot		; handle disk boot
+;
+fp_romboot:
+	; Handle FP ROM boot
+	ld	a,(switches)		; get switches value
+	and	SW_OPT			; isolate options bits
+	ld	hl,fpapps		; rom apps cmd char list
+	call	addhla			; point to the right one
+	ld	a,(hl)			; get it
+;
+	; Attempt ROM application launch
+	ld	ix,(ra_tbl_loc)		; point to start of ROM app tbl
+	ld	c,a			; save command in C
+fp_romboot1:
+	ld	a,(ix+ra_conkey)	; get match char
+	and	~$80			; clear "hidden entry" bit
+	cp	c			; compare
+	jp	z,romload		; if match, load it
+	ld	de,ra_entsiz		; table entry size
+	add	ix,de			; bump IX to next entry
+	ld	a,(ix)			; check for end
+	or	(ix+1)			; ... of table
+	jr	nz,fp_romboot1		; loop till done
+	ret				; no match, return
+;
+fpapps	.db	"MBFPCZNU"
+;
+fp_diskboot:
+	; get count of disk units
+	ld	b,BF_SYSGET		; HBIOS Get function
+	ld	c,BF_SYSGET_DIOCNT	; HBIOS DIO Count sub fn
+	rst	08			; call HBIOS
+	ld	a,e			; count to A
+	ld	(diskcnt),a		; save it
+	or	a			; set flags
+	ret	z			; bort if no disk units
+	ld	a,(switches)		; get switches value
+	and	SW_FLOP			; floppy switch bit
+	jr	nz,fp_flopboot		; handle auto flop boot
+	; fall thru for auto hd boot
+;
+fp_hdboot:
+	; Find the first hd with media and boot to that unit using
+	; the slice specified by the FP switches.
+	ld	a,(diskcnt)		; get disk count
+	ld	b,a			; init loop counter
+	ld	c,0			; init disk index
+fp_hdboot1:
+	push	bc			; save loop control
+	ld	b,BF_DIODEVICE		; HBIOS Disk Device func
+	rst	08			; unit in C, do it
+	pop	bc			; restore loop control
+	ld	a,d			; device type to A
+	cp	DIODEV_IDE		; type IDE or greater is HD
+	jr	c,fp_hdboot2		; if not, continue loop
+	push	bc			; save loop control
+	ld	b,BF_DIOMEDIA		; HBIOS Sense Media
+	ld	e,1			; perform media discovery
+	rst	08			; do it
+	pop	bc			; restore loop control
+	jr	z,fp_hdboot3		; if has media, go boot it
+fp_hdboot2:
+	inc	c			; else next disk
+	djnz	fp_hdboot1		; loop thru all disks
+	ret				; nothing works, abort
+;
+fp_hdboot3:
+	ld	a,c			; disk unit to A
+	ld	(bootunit),a		; save it
+	ld	a,(switches)		; get switches value
+	and	SW_OPT			; isolate slice value
+	ld	(bootslice),a		; save it
+	jp	diskboot		; do it
+;
+fp_flopboot:
+	; Find the nth floppy drive and boot to that unit.  The
+	; floppy number is based on the option switches.
+	ld	a,(diskcnt)		; get disk count
+	ld	b,a			; init loop counter
+	ld	c,0			; init disk index
+	ld	a,(switches)		; get switches value
+	and	SW_OPT			; isolate option bits
+	ld	e,a			; floppy unit down counter
+	inc	e			; pre-increment for ZF check
+fp_flopboot1:
+	push	bc			; save loop control
+	push	de			; save floppy down ctr
+	ld	b,BF_DIODEVICE		; HBIOS Disk Device func
+	rst	08			; unit in C, do it
+	ld	a,d			; device type to A
+	pop	de			; restore loop control
+	pop	bc			; restore floppy down ctr
+	cp	DIODEV_FD		; type FD?
+	jr	nz,fp_flopboot3		; if not floppy, skip
+	dec	e			; decrement down ctr
+	jr	z,fp_flopboot2		; if ctr expired, boot this unit
+fp_flopboot3:
+	inc	c			; else next disk
+	djnz	fp_flopboot1		; loop thru all disks
+	ret				; nothing works, abort
+;
+fp_flopboot2:
+	ld	a,c			; disk unit to A
+	ld	(bootunit),a		; save it
+	xor	a		;	; zero accum
+	ld	(bootslice),a		; floppy boot slice is always 0
+	jp	diskboot		; do it
+;
+#endif
+;
 ;=======================================================================
 ; Process a DSKY command from key in A
 ;=======================================================================
@@ -2168,6 +2311,7 @@ str_upd		.db	"XModem Flash Updater",0
 str_user	.db	"User App",0
 str_egg		.db	"",0
 str_net		.db	"Network Boot",0
+str_switches	.db	"FP Switches = 0x",0
 newcon		.db	0
 newspeed	.db	0
 ;
@@ -2194,6 +2338,8 @@ ra_tbl_loc	.dw	0		; points to active ra_tbl
 bootunit	.db	0		; boot disk unit
 bootslice	.db	0		; boot disk slice
 loadcnt		.db	0		; num disk sectors to load
+switches	.db	0		; front panel switches
+diskcnt		.db	0		; disk unit count value
 ;
 ;=======================================================================
 ; Pad remainder of ROM Loader

Source/HBIOS/sd.asm

@@ -282,6 +282,35 @@ SD_INVCS	.EQU	FALSE		; INVERT CS
 #ENDIF
 ;
 ;
+#IF (SDMODE == SDMODE_PIO)		; Z80 PIO
+;
+;	These mappings work for the RCbus Gluino card with an Arduino
+;	shield attached and are the ones also used in other bitbang setups
+;	directly attached to a PIO. It also works on a straight digital I/O
+;	port as the config writes will disappear into oblivion harmlessly
+;	
+;	The Gluino mapping (ie Arduino pin mapping equivalent) is thus
+;	D10 SS, D11 CIPO, D12 COPI, D13 SCL.
+;
+;	For speed reasons MISO/MOSI are mapped to the top and bottom bits.
+;	RomWBW doesn't yet use this fact but the optimized Fuzix routines do.
+;
+SD_DEVMAX	.EQU	1		; NUMBER OF PHYSICAL UNITS (SOCKETS)
+SD_IOBASE	.EQU	$69		; IO BASE ADDRESS FOR SD INTERFACE
+SD_OPRREG	.EQU	SD_IOBASE	; OUTPUT PORT (OUTPUT: CS, CLK, DIN)
+SD_OPRDEF	.EQU	%11111111	; OUTPUT PORT DEFAULT STATE
+SD_INPREG	.EQU	SD_IOBASE	; INPUT REGISTER
+SD_CS0		.EQU	%00001000	; SELECT
+SD_CLK		.EQU	%00010000	; CLOCK
+SD_DI		.EQU	%00000001	; DATA IN (CARD <- CPU) MOSI
+SD_DO		.EQU	%10000000	; DATA OUT (CARD -> CPU) MISO
+SD_CINIT	.EQU	TRUE		; INITIALIZE OUTPUT PORT
+SD_DDR		.EQU	$6B		; DATA DIRECTION REGISTER
+SD_DDRVAL	.EQU	%11100110	; DATA DIRECTION REGISTER VALUE
+SD_INVCS	.EQU	TRUE		; INVERT CS
+#ENDIF
+;
+;
 #IF (SDMODE == SDMODE_USR)		; USER DEFINED HARDWARE CONFIGURATION
 ;
 ; THIS MODE IS INTENDED TO ALLOW A USER TO EASILY CONFIGURE A CUSTOM
@@ -304,6 +333,27 @@ SD_DDRVAL	.EQU	%00001101	; DATA DIRECTION REGISTER VALUE
 SD_INVCS	.EQU	FALSE		; INVERT CS
 #ENDIF
 ;
+#IF (SDMODE == SDMODE_Z80R)		; Z80 Retro
+;
+;	SPLIT OVER TWO REGISTERS TO DRIVE CLK. THE CS LINE IS ON THE GPIO
+;	WHICH IS THE SAME LATCHES THAT CONTROL MMU ON/OFF, SO DON;T GLITCH
+;	THEM WHEN UPDATING!
+;
+SD_DEVMAX	.EQU	1		; NUMBER OF PHYSICAL UNITS (SOCKETS)
+SD_OPRDEF	.EQU	%00000001	; OUTPUT PORT DEFAULT STATE
+SD_OPRMSK	.EQU	%00000101	; OUTPUT PORT MASK
+SD_OPRREG	.EQU	$64		; CS VIA GPIO
+SD_IOBASE	.EQU	$68		; 68/69 FOR OUTPUT
+SD_IOREG	.EQU	SD_IOBASE	; INPUT REGISTER
+SD_IOCLK	.EQU	SD_IOBASE+1	; CLOCK IS OFF A0
+SD_GPIO		.EQU	$64		; MISO IS ON THE GPIO
+SD_CS0		.EQU	%00000100	; SELECT
+SD_DI		.EQU	%00000001	; DATA IN (CARD <- CPU) MOSI
+SD_DO		.EQU	%00000001	; DATA OUT (CARD -> CPU) MISO
+SD_CINIT	.EQU	FALSE		; INITIALIZE OUTPUT PORT
+SD_INVCS	.EQU	FALSE		; INVERT CS
+#ENDIF
+;
 #IF (SD_DEVCNT > SD_DEVMAX)
 	.ECHO	"*** ERROR: SDCNT EXCEEDS MAXIMUM SUPPORTED BY INTERFACE!!!\n"
 	!!!	; FORCE AN ASSEMBLY ERROR
@@ -510,6 +560,22 @@ SD_INIT:
 	CALL	PRTHEXBYTE
 #ENDIF
 ;
+#IF (SDMODE == SDMODE_PIO)
+	PRTS(" MODE=PIO$")
+	PRTS(" IO=0x$")
+	LD	A,SD_IOBASE
+	CALL	PRTHEXBYTE
+#ENDIF
+;
+#IF (SDMODE == SDMODE_Z80R)
+	PRTS(" MODE=Z80R$")
+	PRTS(" IO=0x$")
+	LD	A,SD_IOBASE
+	CALL	PRTHEXBYTE
+	LD	A,SD_OPRDEF
+	LD	(SD_OPRVAL),A
+#ENDIF
+;
 #IF (SDMODE == SDMODE_USR)
 	PRTS(" MODE=USER$")
 	PRTS(" IO=0x$")
@@ -1736,6 +1802,17 @@ SD_SETUP:
 	OUT	(SD_OPRREG),A		; OPRREG == SIO_MCR
 #ENDIF
 ;
+#IF (SDMODE == SDMODE_PIO)
+	LD	A,SD_OPRDEF		; All output bits high
+	OUT	(SD_OPRREG),A
+	LD	A,$CF			; Port B mode 3
+	OUT	(SD_DDR),A
+	LD	A,SD_DDRVAL		; Set the direction bits
+	OUT	(SD_DDR),A
+	LD	A,$07			; No interrupts
+	OUT	(SD_DDR),A
+#ENDIF
+;
 #IF (SDMODE == SDMODE_USR)
   #IF (SD_CINIT == TRUE)
 	LD	A,(SD_OPRMSK)		; GET OUTPUT PORT MASK
@@ -1863,7 +1940,7 @@ SD_DESELECT:
 	AND	~SD_CS0
 #ENDIF
 ; ADJUST BIT(S) FOR INTERFACES USING INVERTED CS BITS
-#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC))
+#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_PIO) | (SDMODE == SDMODE_Z80R))
   #IF ((SDMODE == SDMODE_SC) & (SD_DEVCNT > 1))
 	XOR	SD_CS0 | SD_CS1
   #ELSE
@@ -1910,9 +1987,48 @@ SD_PUT:
 	SET	4,A			; SET TRANSMIT ENABLE
 	OUT0	(SD_CNTR),A
   #ELSE
-    #IF (SDMODE == SDMODE_UART)
+
+    #IF (SDMODE == SDMODE_Z80R)
+	; USE C - THE CALLING CODE FOR COMMAND SEND FAILS TO SAVE HL/DE
+	; WHILST THE OTHER PATHS DO ?
+        LD	C,A
+	RL	C
+	RLA
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	RL	C
+	RLA
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	RL	C
+	RLA
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	RL	C
+	RLA
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	RL	C
+	RLA
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	RL	C
+	RLA
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	RL	C
+	RLA
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	RL	C
+	RLA
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+    #ELSE
+
+      #IF (SDMODE == SDMODE_UART)
 	XOR	$FF			; DI IS INVERTED ON UART
-    #ENDIF
+      #ENDIF
 	LD	C,A			; C=BYTE TO SEND
 	LD	B,8			; SEND 8 BITS (LOOP 8 TIMES)
 	LD	A,(SD_OPRVAL)		; LOAD CURRENT OPR VALUE
@@ -1928,6 +2044,7 @@ SD_PUT1:
 	DJNZ	SD_PUT1			; REPEAT FOR ALL 8 BITS
 	LD	A,(SD_OPRVAL)		; LOAD CURRENT OPR VALUE
 	OUT	(SD_OPRREG),A		; LEAVE WITH CLOCK LOW
+    #ENDIF
   #ENDIF
 #ENDIF
 	RET				; DONE
@@ -1950,34 +2067,83 @@ SD_GET:
 	CALL	MIRROR			; MSB<-->LSB MIRROR BITS
 	LD	A,C			; KEEP RESULT
   #ELSE
+    #IF (SDMODE == SDMODE_Z80R)
+	; MUST PRESERVE HL,DE
+	PUSH	DE
+	LD	A,1
+	LD	C,SD_GPIO
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	IN	B,(C)
+	RR	B
+	RL	E
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	IN	B,(C)
+	RR	B
+	RL	E
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	IN	B,(C)
+	RR	B
+	RL	E
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	IN	B,(C)
+	RR	B
+	RL	E
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	IN	B,(C)
+	RR	B
+	RL	E
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	IN	B,(C)
+	RR	B
+	RL	E
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	IN	B,(C)
+	RR	B
+	RL	E
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	IN	B,(C)
+	RR	B
+	RL	E
+	LD	A,E
+	POP	DE
+    #ELSE
 	LD	B,8			; RECEIVE 8 BITS (LOOP 8 TIMES)
 	LD	A,(SD_OPRVAL)		; LOAD CURRENT OPR VALUE
 SD_GET1:
 	XOR	SD_CLK			; TOGGLE CLOCK
 	OUT	(SD_OPRREG),A		; UPDATE CLOCK
 	IN	A,(SD_INPREG)		; READ THE DATA WHILE CLOCK IS ACTIVE
-    #IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_PPI))
+      #IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_PIO))
 	RLA				; ROTATE INP:7 INTO CF
-    #ENDIF
-    #IF (SDMODE == SDMODE_N8)
+      #ENDIF
+      #IF (SDMODE == SDMODE_N8)
 	RLA				; ROTATE INP:6 INTO CF
 	RLA				; "
-    #ENDIF
-    #IF (SDMODE == SDMODE_UART)
+      #ENDIF
+      #IF (SDMODE == SDMODE_UART)
 	RLA				; ROTATE INP:5 INTO CF
 	RLA				; "
 	RLA				; "
-    #ENDIF
-    #IF (SDMODE == SDMODE_DSD)
+      #ENDIF
+      #IF (SDMODE == SDMODE_DSD)
 	RRA				; ROTATE INP:0 INTO CF
-    #ENDIF
+      #ENDIF
 	RL	C			; ROTATE CF INTO C:0
 	LD	A,(SD_OPRVAL)		; BACK TO INITIAL VALUES (TOGGLE CLOCK)
 	OUT	(SD_OPRREG),A		; DO IT
 	DJNZ	SD_GET1			; REPEAT FOR ALL 8 BITS
 	LD	A,C			; GET BYTE RECEIVED INTO A
-    #IF (SDMODE == SDMODE_UART)
+      #IF (SDMODE == SDMODE_UART)
 	XOR	$FF			; DO IS INVERTED ON UART
+      #ENDIF
     #ENDIF
   #ENDIF
 #ENDIF

Source/HBIOS/sio.asm

@@ -60,13 +60,20 @@ SIO0B_CMD	.EQU	SIO0BASE + $03
 SIO0B_DAT	.EQU	SIO0BASE + $01
 #ENDIF
 ;
-#IF (SIO0MODE == SIOMODE_ZP)		
+#IF (SIO0MODE == SIOMODE_ZP)
 SIO0A_CMD	.EQU	SIO0BASE + $06
 SIO0A_DAT	.EQU	SIO0BASE + $04 
 SIO0B_CMD	.EQU	SIO0BASE + $07
 SIO0B_DAT	.EQU	SIO0BASE + $05
 #ENDIF
 ;
+#IF (SIO0MODE == SIOMODE_Z80R)
+SIO0A_CMD	.EQU	SIO0BASE + $03
+SIO0A_DAT	.EQU	SIO0BASE + $01
+SIO0B_CMD	.EQU	SIO0BASE + $02
+SIO0B_DAT	.EQU	SIO0BASE + $00
+#ENDIF
+;
 #IF (SIOCNT >= 2)
 ;
   #IF (SIO1MODE == SIOMODE_STD)
@@ -97,6 +104,13 @@ SIO1B_CMD	.EQU	SIO1BASE + $07
 SIO1B_DAT	.EQU	SIO1BASE + $05
   #ENDIF
 ;
+#IF (SIO1MODE == SIOMODE_Z80R)
+SIO1A_CMD	.EQU	SIO0BASE + $03
+SIO1A_DAT	.EQU	SIO0BASE + $01 
+SIO1B_CMD	.EQU	SIO0BASE + $02
+SIO1B_DAT	.EQU	SIO0BASE + $00
+#ENDIF
+;
 #ENDIF
 ;
 SIO_PREINIT:
@@ -785,10 +799,14 @@ SIO_INITBROK:
 ;
 ; SET RECEIVE DATA BITS WR3 
 ;	
+	LD	A,D			; HI WORD OF CONFIG
+	AND	%00100000		; BIT 5 IS AUTO-CTS
+	LD	H,A			; SAVE IN H
 	LD	A,L			; DATA BITS
 	AND	$C0			; CLEAR OTHER BITS
-	OR	$21			; CTS/DCD AUTO, RX ENABLE
-;	
+	OR	$01			; RX ENABLE
+	OR	H			; COMBINE WITH AUTO-CTS
+;
 	LD	(SIO_WR3),A
 ;
 ; SAVE CONFIG PERMANENTLY NOW

Source/HBIOS/std.asm

@@ -1,5 +1,5 @@
 ; The purpose of this file is to define generic symbols and to include
-; the requested build configuraton file to bring in platform specifics.
+; the requested build configuration file to bring in platform specifics.
 
 ; There are several hardware platforms supported by SBC.
 ; 1.  SBC	Z80 SBC (v1 or v2) w/ ECB interface
@@ -16,6 +16,7 @@
 ; 12. RCZ280	Z280 CPU on RCBUS or ZZ80MB
 ; 13. MBC	Andrew Lynch's Multi Board Computer
 ; 14. RPH	Andrew Lynch's RHYOPHYRE Graphics Computer
+; 15. Z80RETRO	Peter Wilson's Z80-Retro Computer
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;
@@ -91,6 +92,15 @@ FDM360		.EQU	2		; 5.25" FLOPPY, 360KB, 2 SIDES, 40 TRKS, 9 SECTORS
 FDM120		.EQU	3		; 5.25" FLOPPY, 1.2MB, 2 SIDES, 80 TRKS, 15 SECTORS
 FDM111		.EQU	4		; 8" FLOPPY, 1.11MB, 2 SIDES, 74 TRKS, 15 SECTORS
 ;
+; FLOPPY DISK TYPE
+;
+FDT_NONE	.EQU	0		; NONE
+FDT_3DD		.EQU	1		; 3.5" FLOPPY, DOUBLE DENSITY
+FDT_3HD		.EQU	2		; 3.5" FLOPPY, HIGH DENSITY
+FDT_5DD		.EQU	3		; 5.25" FLOPPY, DOUBLE DENSITY
+FDT_5HD		.EQU	4		; 5.25" FLOPPY, HIGH DNSITY
+FDT_8		.EQU	5		; 8" FLOPPY, DOUBLE DENSITY
+;
 ; ZILOG CTC MODE SELECTIONS
 ;
 CTCMODE_NONE	.EQU	0		; NO CTC
@@ -116,6 +126,7 @@ SIOMODE_STD	.EQU	1		; STD SIO REG CFG (EZZ80, KIO)
 SIOMODE_RC	.EQU	2		; RCBUS SIO MODULE (SPENCER OWEN)
 SIOMODE_SMB	.EQU	3		; RCBUS SIO MODULE (SCOTT BAKER)
 SIOMODE_ZP	.EQU	4		; ECB-ZILOG PERIPHERALS BOARD
+SIOMODE_Z80R	.EQU	5		; SIO A/B SWAPPED
 ;
 ; TYPE OF CONSOLE BELL TO USE
 ;
@@ -182,6 +193,8 @@ SDMODE_MK4	.EQU	7		; MARK IV
 SDMODE_SC	.EQU	8		; SC (Steve Cousins)
 SDMODE_MT	.EQU	9		; MT (Shift register SPI WIZNET for RCBUS)
 SDMODE_USR	.EQU	10		; USER DEFINED (in sd.asm) (NOT COMPLETE)
+SDMODE_PIO	.EQU	11		; Z80 PIO bitbang
+SDMODE_Z80R	.EQU	12		; Z80 Retro
 ;
 ; AY SOUND CHIP MODE SELECTIONS
 ;

Source/Images/d_zsdos/ReadMe.txt

@@ -45,7 +45,7 @@ an equate. Version 1.2 was never distributed and contains only a few
 minor fixes.  Unfortunately, the use of v1.2 would make it incompatible 
 with many support modules and overlays due to their reliance on 
 hard-coded address assumptions.  This is probably why it was never 
-distributed.  I encountered this myself with the date stamping code –- 
+distributed.  I encountered this myself with the date stamping code -- 
 it won't work with v1.2 because it does a version check. For now, I have 
 chosen to use v1.1 to maximize compatibility (seems to be what everyone 
 is doing). Ultimately, I may go back and try to rebuild everything in 

Source/ver.inc

@@ -1,8 +1,8 @@
 #DEFINE	RMJ	3
-#DEFINE	RMN	2
-#DEFINE	RUP	1
+#DEFINE	RMN	3
+#DEFINE	RUP	0
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.2.1-dev.4"
+#DEFINE BIOSVER	"3.3.0-dev.7"
 #define rmj	RMJ
 #define rmn	RMN
 #define rup	RUP

Source/ver.lib

@@ -1,7 +1,7 @@
 rmj	equ	3
-rmn	equ	2
-rup	equ	1
+rmn	equ	3
+rup	equ	0
 rtp	equ	0
 biosver	macro
-	db	"3.2.1-dev.4"
+	db	"3.3.0-dev.7"
 	endm

Tools/simh/Sim.cmd

@@ -2,8 +2,9 @@
 set ROM=..\..\Binary\SBC_simh.rom
 if not "%1"=="" set ROM=..\..\Binary\%1.rom
 if not exist %ROM% goto romerr
-rem start C:\Users\WWarthen\Bin\putty.exe -load "SIMH Telnet"
-start /w altairz80.exe sim.cfg %ROM%
+:: start C:\Users\WWarthen\Bin\putty.exe -load "SIMH Telnet"
+:: start /w altairz80.exe sim.cfg %ROM%
+altairz80.exe sim.cfg %ROM%
 goto :eof
 
 :romerr