ROMless Operation Overhaul

- Implement new approach to ROMless boot and operation. Still missing the ability to seed the RAM disk. - Tweaks to CH driver
CH Driver Tweaks
2026-02-07 15:03:13 -06:00 · 2023-10-01 17:22:19 -07:00 · 2023-09-24 16:47:36 -07:00 · 2023-09-24 16:25:50 -07:00 · 2023-09-24 17:04:35 +01:00 · 2023-09-22 14:13:12 -07:00
40 changed files with 1616 additions and 299 deletions
--- a/Doc/ChangeLog.txt
+++ b/Doc/ChangeLog.txt
@@ -21,6 +21,8 @@ Version 3.3
 - WBW: Fix S100 Z180 LED operation (credit to Jay Cotton for finding this issue)
 - WBW: QPM system image is now combined with current CBIOS during build
 - WBW: Added framework for Heath platform
+- WBW: Support for USB Disks via CH375/CH376
+- D?J: Support for Raspberry Pi build process

 Version 3.2.1
 -------------
--- a/Source/Apps/assign.asm
+++ b/Source/Apps/assign.asm
@@ -31,6 +31,7 @@
 ;   2022-02-28 [WBW] Use HBIOS to swap banks under CP/M 3
 ;                    Use CPM3 BDOS direct BIOS call to get DRVTBL adr
 ;   2023-06-19 [WBW] Update for revised DIODEVICE API
+;   2023-09-19 [WBW] Added CHUSB & CHSD device support
 ;_______________________________________________________________________________
 ;
 ; ToDo:
@@ -1920,8 +1921,8 @@ dev09	.db	"HDSK",0
 dev10	.db	"PPA",0
 dev11	.db	"IMM",0
 dev12	.db	"SYQ",0
-dev13	.equ	devunk
-dev14	.equ	devunk
+dev13	.db	"CHUSB",0
+dev14	.db	"CHSD",0
 dev15	.equ	devunk
 ;
 devcnt	.equ	10		; 10 devices defined
@@ -1942,10 +1943,10 @@ stack	.equ	$		; stack top
 ; Messages
 ;
 indent	.db	"   ",0
-msgban1	.db	"ASSIGN v1.6 for RomWBW CP/M ",0
+msgban1	.db	"ASSIGN v1.7 for RomWBW CP/M ",0
 msg22	.db	"2.2",0
 msg3	.db	"3",0
-msbban2	.db	", 16-Jun-2023",0
+msbban2	.db	", 19-Sep-2023",0
 msghb	.db	" (HBIOS Mode)",0
 msgub	.db	" (UBIOS Mode)",0
 msgban3	.db	"Copyright 2021, Wayne Warthen, GNU GPL v3",0
--- a/Source/CBIOS/cbios.asm
+++ b/Source/CBIOS/cbios.asm
@@ -2529,24 +2529,21 @@ MD_INIT:
 ; UDPATE THE RAM/ROM DPB STRUCTURES BASED ON HARDWARE
 ;
 #IFDEF PLTWBW
-	; TODO: HANDLE DISABLED RAM/ROM DISK BETTER.
-	; IF RAM OR ROM DISK ARE DISABLED, BELOW WILL STILL
-	; TRY TO ADJUST THE DPB BASED ON RAM BANK CALCULATIONS.
-	; IT SHOULD NOT MATTER BECAUSE THE DPB SHOULD NEVER BE
-	; USED.  IT WOULD BE BETTER TO GET RAMD0/ROMD0 AND
-	; RAMDN/ROMDN FROM THE HCB AND USE THOSE TO CALC THE
-	; DPB ADJUSTMENT.  IF DN-D0=0, BYPASS ADJUSTMENT.
-	LD	A,(HCB + HCB_ROMBANKS)	; ROM BANK COUNT
-	SUB	4		; REDUCE BANK COUNT BY RESERVED PAGES
-	LD	IX,DPB_ROM	; ADDRESS OF DPB
-	CALL	MD_INIT1	; FIX IT UP
+	; NOTE: ROM AND/OR RAM DISK MAY NOT BE ACTIVE, BUT WE GO
+	; AHEAD AND UPDATE BOTH DPBS ANYWAY.  IT CAUSES NO HARM SINCE
+	; INACTIVE RAM/ROM DISK WILL NEVER BE ACCESSED.
 ;
-	LD	A,(HCB + HCB_RAMBANKS)	; RAM BANK COUNT
-	SUB	8		; REDUCE BANK COUNT BY RESERVED PAGES
-	LD	IX,DPB_RAM	; ADDRESS OF DPB
-	CALL	MD_INIT1	; FIX IT UP
+	; ROM DISK
+	LD	A,(HCB + HCB_ROMD_BNKS)	; ROM DISK SIZE IN BANKS
+	LD	IX,DPB_ROM		; ADDRESS OF DPB
+	CALL	MD_INIT1		; FIX IT UP
 ;
-	JR	MD_INIT4	; DONE
+	; RAM DISK
+	LD	A,(HCB + HCB_RAMD_BNKS)	; RAM DISK SIZE IN BANKS
+	LD	IX,DPB_RAM		; ADDRESS OF DPB
+	CALL	MD_INIT1		; FIX IT UP
+;	
+	JR	MD_INIT4		; DONE
 ;
 MD_INIT1:
 ;
@@ -3394,8 +3391,8 @@ DEV09	.DB	"HDSK$"
 DEV10	.DB	"PPA$"
 DEV11	.DB	"IMM$"
 DEV12	.DB	"SYQ$"
-DEV13	.EQU	DEVUNK
-DEV14	.EQU	DEVUNK
+DEV13	.DB	"CHUSB$"
+DEV14	.DB	"CHSD$"
 DEV15	.EQU	DEVUNK
 ;
 #ENDIF
--- a/Source/CPM3/diskio.z80
+++ b/Source/CPM3/diskio.z80
@@ -355,38 +355,30 @@ dpb$hdnew:	; 8MB Hard Disk Drive (new format)
 ;		called for first time initialization.

 dsk$init:
-	; TODO: Handle disabled RAM/ROM disk better.
-	; If RAM or ROM disk are disabled, below will still
-	; try to adjust the DPB based on RAM bank calculations.
-	; It should not matter because the DPB should never be
-	; used.  It would be better to get RAMD0/ROMD0 and
-	; RAMDN/ROMDN from the HCB and use those to calc the
-	; DPB adjustment.  If DN-D0=0, bypass adjustment.
-	ld	b,0FAh			; HBIOS Peek Function
-	ld	a,(@hbbio)		; HBIOS bank id
-	ld	d,a			; ... goes in D
-	ld	hl,10Ch			; Offset 10Ch is ROM bank cnt
-	rst	08			; Call HBIOS, value in E
-	ld	a,e			; move count to accum
-	sub	4			; reduce by # reserved banks
-	ld	ix,dpb$rom		; address of DPB
-	call	dsk$init1		; fix it up
-	
-	ld	b,0FAh			; HBIOS Peek Function
-	ld	a,(@hbbio)		; HBIOS bank id
-	ld	d,a			; ... goes in D
-	ld	hl,10Bh			; Offset 10Bh is RAM bank cnt
-	rst	08			; Call HBIOS, value in E
-	ld	a,e			; move count to accum
-	sub	8			; reduce by # reserved banks
-	ld	ix,dpb$ram		; address of DPB
-	call	dsk$init1		; fix it up

+	; NOTE: ROM and/or RAM disk may not be active, but we go
+	; ahead and update both DPBs anyway.  It causes no harm since
+	; inactive RAM/ROM disk will never be accessed.
+
+	ld	hl,1DFh			; ROM disk bank cnt in HCB
+	ld	ix,dpb$rom		; address of ROM Disk DPB
+	call	dsk$init1		; fix it up
+	ld	hl,1DDh			; RAM dsik bank cnt in HCB
+	ld	ix,dpb$ram		; address of RAM Disk DPB
+	call	dsk$init1		; fix it up
 	ret				; done

 dsk$init1:
+	; Get bank count of RAM/ROM disk
+	ld	b,0FAh			; HBIOS Peek Function
+	ld	a,(@hbbio)		; HBIOS bank id
+	ld	d,a			; ... goes in D
+	rst	08			; Call HBIOS, value in E
+	;ld	a,e			; move count to accum
+
 	; Setup HL with bank count
-	ld	l,a			; lsb
+	;ld	l,a			; lsb
+	ld	l,e			; lsb
 	ld	h,0			; msb is always zero

 	; Update EXM field
--- a/Source/CPM3/genbnk.dat
+++ b/Source/CPM3/genbnk.dat
@@ -8,12 +8,12 @@ MEMTOP   = FD
 BNKSWT   = Y
 COMBAS   = 80
 LERROR   = Y
-NUMSEGS  = 04
+NUMSEGS  = 02
 MEMSEG00 = 01,17,00
 MEMSEG01 = 0E,72,02
 MEMSEG02 = 01,7F,03
-MEMSEG03 = 01,7F,04
-MEMSEG04 = 01,7F,05
+MEMSEG03 = 00,C0,04
+MEMSEG04 = 00,C0,05
 MEMSEG05 = 00,C0,06
 MEMSEG06 = 00,C0,07
 MEMSEG07 = 00,C0,08
@@ -25,38 +25,38 @@ MEMSEG0C = 00,C0,0D
 MEMSEG0D = 00,C0,0E
 MEMSEG0E = 00,C0,0F
 MEMSEG0F = 00,C0,10
-HASHDRVA = Y
-HASHDRVB = Y
-HASHDRVC = Y
-HASHDRVD = Y
-HASHDRVE = Y
-HASHDRVF = Y
-HASHDRVG = Y
-HASHDRVH = Y
-HASHDRVI = Y
-HASHDRVJ = Y
-HASHDRVK = Y
-HASHDRVL = Y
-HASHDRVM = Y
-HASHDRVN = Y
-HASHDRVO = Y
-HASHDRVP = Y
-ALTBNKSA = Y
-ALTBNKSB = Y
-ALTBNKSC = Y
-ALTBNKSD = Y
-ALTBNKSE = Y
-ALTBNKSF = Y
-ALTBNKSG = Y
-ALTBNKSH = Y
-ALTBNKSI = Y
-ALTBNKSJ = Y
-ALTBNKSK = Y
-ALTBNKSL = Y
-ALTBNKSM = Y
-ALTBNKSN = Y
-ALTBNKSO = Y
-ALTBNKSP = Y
+HASHDRVA = N
+HASHDRVB = N
+HASHDRVC = N
+HASHDRVD = N
+HASHDRVE = N
+HASHDRVF = N
+HASHDRVG = N
+HASHDRVH = N
+HASHDRVI = N
+HASHDRVJ = N
+HASHDRVK = N
+HASHDRVL = N
+HASHDRVM = N
+HASHDRVN = N
+HASHDRVO = N
+HASHDRVP = N
+ALTBNKSA = N
+ALTBNKSB = N
+ALTBNKSC = N
+ALTBNKSD = N
+ALTBNKSE = N
+ALTBNKSF = N
+ALTBNKSG = N
+ALTBNKSH = N
+ALTBNKSI = N
+ALTBNKSJ = N
+ALTBNKSK = N
+ALTBNKSL = N
+ALTBNKSM = N
+ALTBNKSN = N
+ALTBNKSO = N
+ALTBNKSP = N
 NDIRRECA = 08
 NDIRRECB = 00
 NDIRRECC = 00
--- a/Source/CPM3/genres.dat
+++ b/Source/CPM3/genres.dat
@@ -8,7 +8,7 @@ MEMTOP   = FD
 BNKSWT   = N
 COMBAS   = 00
 LERROR   = Y
-NUMSEGS  = 03
+NUMSEGS  = 01
 MEMSEG00 = 00,80,00
 MEMSEG01 = 00,C0,02
 MEMSEG02 = 00,C0,03
--- a/Source/CPM3/move.z80
+++ b/Source/CPM3/move.z80
@@ -65,12 +65,11 @@ xbnkmov:
 ; ------------	--------------	-------
 ; COMMON	BID_COM		8Fh
 ; 0: OS/BUFS	BID_USR         8Eh
-;		BID_BIOS	8Dh	
-; 1: TPA	BID_AUX		8Ch
-; 2: BUFS	BID_AUX-1	8Bh
-; 3: BUFS	BID_AUX-2	8Ah
-; 4: BUFS	BID_AUX-3	89h
-; 5: BUFS	BID_AUX-4	88h
+; 1: TPA	BID_AUX		8Dh
+; 2: BUFS	BID_AUX-1	8Ch
+; 3: BUFS	BID_AUX-2	8Bh
+; 4: BUFS	BID_AUX-3	8Ah
+; 5: BUFS	BID_AUX-4	89h
 ;
 ; N.B., Below BID_AUX is considered RAM disk bank.  Need to
 ; make sure RAM disk is kept small enough to stay below
@@ -80,17 +79,13 @@ xbnkmov:
 ; to adjust for real size of RAM in system
 ;
 ?bnkxlt:
-	or	a
-	jr	z,bank0
-	neg			; 2 -> -2
-	add	a,8Dh		; 8Dh - 2 = 8Bh
-@hbbio	equ	$ - 1		; BID_BIOS
-	ret
-bank0:
-	ld	a,8Eh		; 0 -> 8Eh
+	neg			; ex: 2 -> -2
+	add	a,8Eh		; ex: 8Eh - 2 = 8Ch
@hbusr	equ	$ - 1		; BID_USR
 	ret
-	
+
+@hbbio	db	0		; BID_BIOS
+
 movtyp	db	0		; non-zero for interbank move

 movbnks:
--- a/Source/HBIOS/Bank
+++ b/Source/HBIOS/Bank
@@ -0,0 +1,65 @@
+ROM Bank Layout
+
+Bank ID		Module		Start	Size
+------		------		------	------
+0x00		hbios		0x0000	0x8000
+		<end>		0x8000
+
+0x01		loader		0x0000	0x1000
+		dbgmon		0x1000	0x2000
+		cpm22		0x2000	0x3000
+		zsys		0x5000	0x3000
+		<end>		0x8000
+
+0x02		forth		0x0000	0x1700
+		basic		0x1700	0x2000
+		tbasic		0x3700	0x0900
+		game		0x4000	0x0900
+		egg		0x4900	0x0200
+		netboot         0x4B00	0x1000
+		updater         0x5B00	0x0D00
+		usrrom		0x6800	0x1800
+		<end>		0x8000
+
+0x03		imgpad2		0x0000	0x8000
+		<end>		0x8000
+
+0x04 - N	ROM Disk Data
+
+
+RAM Bank Layout
+
+Bank ID         Usage
+-------         ------
+0x80            RomWBW HBIOS
+0x81-0x8B       RAM Disk Data
+0x8C		CP/M 3 Buffers
+0x8D            CP/M 3 OS
+0x8E            User TPA
+0x8F            Common
+
+
+ROMless Bank Layout
+
+Bank ID         Usage
+-------         ------
+0x80            RomWBW HBIOS
+0x81		Loader, DbgMon, CP/M 2.2, ZSDOS
+0x82		ROM Apps
+0x83		More ROM Apps
+0x84-0x8B       RAM Disk Data
+0x8C		CP/M 3 Buffers
+0x8D            CP/M 3 OS
+0x8E            User TPA
+0x8F            Common
+
+
+ROMless Tiny Bank Layout (128K)
+NOTE: No ROM Apps, No CP/M 3 support
+
+Bank ID         Usage
+-------         ------
+0x80            RomWBW HBIOS
+0x81		Loader, DbgMon, CP/M 2.2, ZSDOS
+0x82            User TPA
+0x83            Common
--- a/Source/HBIOS/Build.cmd
+++ b/Source/HBIOS/Build.cmd
@@ -110,10 +110,8 @@ copy /b romldr.bin + dbgmon.bin + ..\zsdos\zsys_wbw.bin osimg_small.bin || exit
 :: should yield a result of zero.
 ::

-if %ROMSize% gtr 0 (
-    for %%f in (hbios_rom.bin osimg.bin osimg1.bin osimg2.bin) do (
-      "%TOOLS%\srecord\srec_cat.exe" %%f -Binary -Crop 0 0x7FFF -Checksum_Negative_Big_Endian 0x7FFF 1 1 -o %%f -Binary || exit /b
-    )
+for %%f in (hbios_rom.bin osimg.bin osimg1.bin osimg2.bin) do (
+  "%TOOLS%\srecord\srec_cat.exe" %%f -Binary -Crop 0 0x7FFF -Checksum_Negative_Big_Endian 0x7FFF 1 1 -o %%f -Binary || exit /b
 )

 ::
@@ -137,8 +135,8 @@ if %ROMSize% gtr 0 (
    copy /b hbios_rom.bin + osimg.bin + osimg1.bin + osimg2.bin %ROMName%.upd || exit /b
    copy /b hbios_app.bin + osimg_small.bin %ROMName%.com || exit /b
 ) else (
-    copy /b hbios_rom.bin + osimg_small.bin %ROMName%.rom || exit /b
-    copy /b hbios_rom.bin + osimg_small.bin %ROMName%.upd || exit /b
+    copy /b hbios_rom.bin + osimg.bin + osimg1.bin + osimg2.bin %ROMName%.rom || exit /b
+    copy /b hbios_rom.bin + osimg.bin + osimg1.bin + osimg2.bin %ROMName%.upd || exit /b
    copy /b hbios_app.bin + osimg_small.bin %ROMName%.com || exit /b
 )

--- a/Source/HBIOS/Makefile
+++ b/Source/HBIOS/Makefile
@@ -67,11 +67,9 @@ $(OBJECTS) : $(ROMDEPS)
 		else \
 			cat imgpad2.bin >osimg2.bin ; \
 		fi ; \
-		if [ $(ROMSIZE) -gt 0 ] ; then \
-			for f in hbios_rom.bin osimg.bin osimg1.bin osimg2.bin ; do \
-				srec_cat $$f -Binary -Crop 0 0x7FFF -Checksum_Negative_Big_Endian 0x7FFF 1 1 -o $$f -Binary ; \
-			done \
-		fi \
+		for f in hbios_rom.bin osimg.bin osimg1.bin osimg2.bin ; do \
+			srec_cat $$f -Binary -Crop 0 0x7FFF -Checksum_Negative_Big_Endian 0x7FFF 1 1 -o $$f -Binary ; \
+		done \
 	fi
 	if [ $(ROM_PLATFORM) = UNA ] ; then \
 		cp osimg.bin $(DEST)/UNA_WBW_SYS.bin ; \
@@ -83,8 +81,8 @@ $(OBJECTS) : $(ROMDEPS)
 			cat hbios_rom.bin osimg.bin osimg1.bin osimg2.bin >$(ROMNAME).upd ; \
 			cat hbios_app.bin osimg_small.bin > $(ROMNAME).com ; \
 		else \
-			cat hbios_rom.bin osimg_small.bin > $(ROMNAME).rom ; \
-			cat hbios_rom.bin osimg_small.bin > $(ROMNAME).upd ; \
+			cat hbios_rom.bin osimg.bin osimg1.bin osimg2.bin >$(ROMNAME).rom ; \
+			cat hbios_rom.bin osimg.bin osimg1.bin osimg2.bin >$(ROMNAME).upd ; \
 			cat hbios_app.bin osimg_small.bin > $(ROMNAME).com ; \
 		fi \
 	fi
--- a/Source/HBIOS/ROM
+++ b/Source/HBIOS/ROM
@@ -1,39 +0,0 @@
-RomWBW ROM Layout
-
-Bank		Module		Start	Size
------		------		------	------		
-0		hbios		0x0000	0x8000
-		<end>		0x8000
-
-1		loader		0x0000	0x1000
-		dbgmon		0x1000	0x2000
-		cpm22		0x2000	0x3000
-		zsys		0x5000	0x3000
-		<end>		0x8000        
-
-2		forth		0x0000	0x1700
-		basic		0x1700	0x2000
-		tbasic		0x3700	0x0900
-		game		0x4000	0x0900
-		egg		0x4900	0x0200
-		netboot         0x4B00	0x1000
-		updater         0x5B00	0x0D00
-		usrrom		0x6800	0x1800
-		<end>		0x8000
-
-3		imgpad2		0x0000	0x8000
-		<end>		0x8000
-
-4 - N		ROM Disk Data
-
-
-RomWBW RAM Layout
-
-Bank ID         Usage                   Physical Address
-------         ------                  ----------------
-0x80-0x87       RAM Disk Data           0x80000-0xBFFFF
-0x88-0x8B       CP/M 3 Buffers          0xC0000-0xDFFFF
-0x8C            CP/M 3 OS               0xE0000-0xE7FFF
-0x8D            RomWBW HBIOS            0xE8000-0xEFFFF
-0x8E            User TPA                0xF0000-0xF7FFF
-0x8F            Common                  0xF8000-0xFFFFF
--- a/Source/HBIOS/cfg_duo.asm
+++ b/Source/HBIOS/cfg_duo.asm
@@ -230,6 +230,18 @@ SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$BE		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.EQU	$FF		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
--- a/Source/HBIOS/cfg_dyno.asm
+++ b/Source/HBIOS/cfg_dyno.asm
@@ -247,6 +247,8 @@ SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
--- a/Source/HBIOS/cfg_heath.asm
+++ b/Source/HBIOS/cfg_heath.asm
@@ -251,6 +251,8 @@ SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
--- a/Source/HBIOS/cfg_master.asm
+++ b/Source/HBIOS/cfg_master.asm
@@ -299,6 +299,18 @@ SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$BE		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.EQU	$FF		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
--- a/Source/HBIOS/cfg_mbc.asm
+++ b/Source/HBIOS/cfg_mbc.asm
@@ -227,6 +227,8 @@ SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
--- a/Source/HBIOS/cfg_mk4.asm
+++ b/Source/HBIOS/cfg_mk4.asm
@@ -237,6 +237,8 @@ SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	TRUE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
--- a/Source/HBIOS/cfg_n8.asm
+++ b/Source/HBIOS/cfg_n8.asm
@@ -239,6 +239,8 @@ SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
--- a/Source/HBIOS/cfg_rcz180.asm
+++ b/Source/HBIOS/cfg_rcz180.asm
@@ -253,6 +253,18 @@ SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$BE		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.EQU	$FF		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
--- a/Source/HBIOS/cfg_rcz280.asm
+++ b/Source/HBIOS/cfg_rcz280.asm
@@ -257,6 +257,18 @@ SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$BE		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.EQU	$FF		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
--- a/Source/HBIOS/cfg_rcz80.asm
+++ b/Source/HBIOS/cfg_rcz80.asm
@@ -251,6 +251,18 @@ SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$BE		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.EQU	$FF		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
--- a/Source/HBIOS/cfg_rph.asm
+++ b/Source/HBIOS/cfg_rph.asm
@@ -228,6 +228,8 @@ SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	FALSE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
--- a/Source/HBIOS/cfg_s100.asm
+++ b/Source/HBIOS/cfg_s100.asm
@@ -247,6 +247,8 @@ SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
--- a/Source/HBIOS/cfg_sbc.asm
+++ b/Source/HBIOS/cfg_sbc.asm
@@ -226,6 +226,8 @@ SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
--- a/Source/HBIOS/cfg_scz180.asm
+++ b/Source/HBIOS/cfg_scz180.asm
@@ -247,6 +247,18 @@ SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$BE		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.EQU	$FF		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
--- a/Source/HBIOS/cfg_z80retro.asm
+++ b/Source/HBIOS/cfg_z80retro.asm
@@ -200,6 +200,8 @@ SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
--- a/Source/HBIOS/cfg_zeta.asm
+++ b/Source/HBIOS/cfg_zeta.asm
@@ -171,6 +171,8 @@ SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
--- a/Source/HBIOS/cfg_zeta2.asm
+++ b/Source/HBIOS/cfg_zeta2.asm
@@ -182,6 +182,8 @@ SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
--- a/Source/HBIOS/ch.asm
+++ b/Source/HBIOS/ch.asm
--- a/Source/HBIOS/dsrtc.asm
+++ b/Source/HBIOS/dsrtc.asm
@@ -145,6 +145,8 @@ DSRTC_PREINIT:
 	;OR	DSRTC_IDLE		; SET OUR IDLE BITS
 	;LD	(DSRTC_OPRVAL),A	; SAVE IT
 ;
+	XOR	A			; ZERO
+	LD	(DSRTC_STAT),A		; CLEAR STATUS
 	CALL	DSRTC_DETECT		; HARDWARE DETECTION
 	LD	(DSRTC_STAT),A		; SAVE RESULT
 	RET	NZ			; ABORT IF ERROR
--- a/Source/HBIOS/esp.asm
+++ b/Source/HBIOS/esp.asm
@@ -33,7 +33,8 @@ ESP_1_SPARE	.EQU	%00100000
 ;
 ; COMMAND OPCODES
 ;
-ESP_CMD_NOP	.EQU	0		; NO OP
+ESP_CMD_NOP	.EQU	0		; NO OP/SYNC
+ESP_CMD_SYNC	.EQU	0		; NO OP/SYNC
 ESP_0_CMD_COUT	.EQU	1		; CHAR OUT
 ESP_0_CMD_CSTR	.EQU	2		; STRING OUT
 ESP_0_CMD_KIN	.EQU	3		; KEY IN
@@ -76,11 +77,11 @@ ESP_INIT:
 ;
 ESP_INIT1:
 	CALL	ESP_PRTVER
-	
+
 	LD	A,(ESP_PRES)
 	SET	0,A
 	LD	(ESP_PRES),A
-	
+
 ;
 ESP_INIT2:
 	; DETECT SECOND ESP32 MODULE
@@ -151,6 +152,7 @@ ESP_DETECT1:
 	RET				; DONE
 ;
 ESP_DETECT2:
+	CALL 	ESP_SYNC
 	;LD	A,B			; *DEBUG*
 	;CALL	PC_SPACE		; *DEBUG*
 	;CALL	PRTHEXBYTE		; *DEBUG*
@@ -178,8 +180,8 @@ ESP_DETECT2:
 ; CLEAR ESP INPUT QUEUE
 ;
 ESP_CLR:
-	LD	B,0			; MAX CHARS TO READ
-ESP_CLR0:
+;	LD	B,0			; MAX CHARS TO READ   /Removed DDW
+;ESP_CLR0:   /Removed DDW
 	CALL	ESP_WTNBSY		; WAIT TILL NOT BUSY
 	RET	NZ			; BAIL OUT IF TIMEOUT
 	IN	A,(ESP_STAT)		; GET STATUS
@@ -187,13 +189,28 @@ ESP_CLR0:
 	RET	Z			; IF NOT, DONE
 	LD	C,(IY+ESP_CFG_IO)	; ESP I/O PORT
 	IN	A,(C)			; GET BYTE
-	DJNZ	ESP_CLR0		; LOOP TILL DONE
-	OR	$FF			; SIGNAL FAILURE
+	JP 	ESP_CLR
+;	DJNZ	ESP_CLR0		; LOOP TILL DONE /Removed DDW
+;	OR	$FF			; SIGNAL FAILURE /Removed DDW
+;	RET /Removed DDW
+
+;
+; RE-SYNC ESP  (added DDW)
+;
+ESP_SYNC:
+	LD	B,0				; sync count -- WORST CASE  PERFORMACE COULD BE IMPROVED BY REDUCING THIS VALUE
+ESP_SYNC0:
+	PUSH 	BC
+	LD	A,ESP_CMD_SYNC		; Sync ESP
+	CALL	ESP_OUT			; SEND CMD OPCODE
+	POP 	BC
+	DJNZ	ESP_SYNC0		; LOOP TILL DONE
 	RET
 ;
 ; PRINT ESP VERSION STRING TO CONSOLE
 ;
 ESP_PRTVER:
+	CALL 	ESP_SYNC
 	CALL	ESP_CLR			; CLEAR ANY PENDING DATA
 	;LD	DE,1000			; SMALL DELAY HERE
 	;CALL	VDELAY			; ... SEEMS TO HELP RELIABILITY
@@ -224,13 +241,13 @@ ESP_OUT:
 ESP_INWAIT:
 	CALL	ESP_WTNBSY		; WAIT TILL NOT BUSY
 	CALL	ESP_WTRDY		; WAIT FOR READY TO OUTPUT
-	; FALL THRU (GET CHAR VIA ESP_IN)
+	JP 		ESP_IN1			; Added DDW
 ;
 ; GET BYTE FROM ESP (NON BLOCKING)
 ;
 ESP_IN:
 	CALL	ESP_WTNBSY		; WAIT TILL NOT BUSY
-ESP_IN1:	
+ESP_IN1:
 	LD	C,(IY+ESP_CFG_IO)	; ESP I/O PORT
 	IN	A,(C)			; GET BYTE
 	PUSH	AF			; SAVE VALUE
@@ -244,7 +261,7 @@ ESP_WTNBSY:
 	LD	B,0			; MAX TRIES
 	;PUSH	HL			; SAVE HL
 	;LD	HL,0			; MAX TRIES
-ESP_WTNBSY1:	
+ESP_WTNBSY1:
 	LD	C,(IY+ESP_CFG_ST)	; ESP STATUS PORT
 	IN	A,(C)			; GET STATUS
 	AND	(IY+ESP_CFG_BSYMSK)	; IS ESP BUSY?
@@ -255,7 +272,7 @@ ESP_WTNBSY1:
 	;LD	A,H			; CHECK FOR
 	;OR	L			; ... TIMEOUT
 	;JR	NZ,ESP_WTNBSY1		; LOOP AS NEEDED
-	CALL	PC_ASTERISK		; *DEBUG*
+	;CALL	PC_ASTERISK		; *DEBUG*
 	OR	$FF			; SIGNAL TIMEOUT
 ;ESP_WTNBSY_Z:
 	;POP	HL			; RECOVER HL
@@ -265,7 +282,7 @@ ESP_WTNBSY1:
 ;
 ESP_WTBSY:
 	LD	B,3			; MAX TRIES
-ESP_WTBSY1:	
+ESP_WTBSY1:
 	LD	C,(IY+ESP_CFG_ST)	; ESP STATUS PORT
 	IN	A,(C)			; GET STATUS
 	XOR	$FF			; INVERT SO 0=BUSY
@@ -307,7 +324,8 @@ ESP_WTRDY1:
 	AND	(IY+ESP_CFG_RDYMSK)	; IS ESP READY TO OUTPUT
 	RET	Z			; RETURN IF READY
 	DJNZ	ESP_WTRDY1		; ELSE LOOP
-	CALL	PC_PERIOD		; *DEBUG*
+	;CALL	PC_PERIOD		; *DEBUG*
+	CALL 	ESP_SYNC 		; SOMETHING WENT WRONG, ENSURE SYNC (Added DDW)
 	OR	$FF			; SIGNAL TIMEOUT
 	RET				; AND RETURN
 ;
@@ -393,6 +411,7 @@ ESPCON_IN:
 ;
 ;
 ESPCON_IST:
+	CALL	ESP_CLR			; CLEAR ANY PENDING DATA (Added DDW)
 	LD	A,ESP_0_CMD_KST		; KBD BUF STATUS
 	CALL	ESP_OUT			; SEND CMD OPCODE
 	CALL	ESP_INWAIT		; GET BUF SIZE
@@ -423,7 +442,9 @@ ESPCON_OST:
 ;
 ;
 ESPCON_INITDEV:
-	SYSCHKERR(ERR_NOTIMPL)
+	CALL 	ESP_CLR
+	CALL 	ESP_SYNC
+;	SYSCHKERR(ERR_NOTIMPL)  Removed DDW
 	RET
 ;
 ;
@@ -529,6 +550,7 @@ ESPSER_IN:
 ;
 ;
 ESPSER_IST:
+	CALL	ESP_CLR			; CLEAR ANY PENDING DATA (Added DDW)
 	LD	A,ESP_CMD_SST		; SERIAL STATUS
 	CALL	ESP_OUT			; SEND CMD OPCODE
 	CALL	ESP_INWAIT		; GET BUF SIZE
@@ -559,6 +581,8 @@ ESPSER_OST:
 ;
 ;
 ESPSER_INITDEV:
+	CALL 	ESP_CLR
+	CALL 	ESP_SYNC
 	PUSH	DE			; SAVE INCOMING CONFIG WORD
 ;
 	; XLATE NEW LINE MODE INTO C
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -318,9 +318,9 @@ CB_BIDUSR	.DB	BID_USR
 CB_BIDBIOS	.DB	BID_BIOS
 CB_BIDAUX	.DB	BID_AUX
 CB_BIDRAMD0	.DB	BID_RAMD0
-CB_BIDRAMDN	.DB	BID_RAMDN
+CB_RAMD_BNKS	.DB	RAMD_BNKS
 CB_BIDROMD0	.DB	BID_ROMD0
-CB_BIDROMDN	.DB	BID_ROMDN
+CB_ROMD_BNKS	.DB	ROMD_BNKS
 ;
 	.FILL	(HCB + HCB_SIZ - $),0	; PAD REMAINDER OF HCB
 ;
@@ -1435,7 +1435,7 @@ S100MON_SKIP:
 ;
 ; THIS VALUE IS TEMPORARILY STORED AT HBX_LOC - 2
 ; BECAUSE WE ARE CURRENTLY RUNNING IN ROM.  AFTER WE TRANSITION HBIOS
-; TO RAM, THE VALUE IS MOVED TO IT'S REAL LCOATION AT HB_APPBNK.
+; TO RAM, THE VALUE IS MOVED TO IT'S REAL LOCATION AT HB_APPBNK.
 ;
 	LD	A,(HB_CURBNK)		; GET HB_CURBNK
 	LD	(HBX_LOC - 2),A		; ... AND SAVE TEMP FOR APPBNK
@@ -1607,63 +1607,10 @@ MBC_SINGLE:
 ;
 #ENDIF
 ;
-; IF THIS IS A ROM-LESS SYSTEM, THEN WE NEED TO COPY THE PAYLOAD
-; (LOADER, MONITOR, ZSDOS) THAT HAS BEEN LOADED TO PHYSICAL RAM
-; BANKS 0 AND 1 TO THE USER TPA BANK TO RUN AFTER BOOT.
-; IT IS DONE PRIOR TO COPYING HBIOS TO IT'S FINAL BANK BECAUSE
-; THE PAYLOAD MAY EXTEND INTO THE HBIOS OPERATING BANK.  THIS
-; HAPPENS PRIMARILY IN THE CASE WHERE THE
-; SYSTEM HAS THE MINIMUM 128KB OF RAM.
-;
-#IFDEF ROMBOOT
-  #IF (ROMSIZE == 0)
- ; 
-	; THE PAYLOAD IS LIKELY TO CROSS OVER THE RAM BANK 0/1
-	; BOUNDARY.  BNKCPY DOES NOT HANDLE THIS BECAUSE IT ASSUMES
-	; THE COMMON BANK IS USED AFTER PASSING OVER THE BANK
-	; BOUNDARY.  WE WORK AROUND THAT HERE BY DOING TWO COPIES.
-	; THE FIRST ONE HANDLES THE PORTION OF THE PAYLOAD FROM THE
-	; END OF HBIOS TO THE BANK BOUNDARY ($8000).  THE SECOND
-	; ONE HANDLES THE PORTION THAT EXTENDS INTO THE SECOND
-	; PHYSICAL RAM BANK.
-;
-	; COPY PORTION OF PAYLOAD FOLLOWING HBIOS TO THE BANK
-	; BOUNDARY AT $8000 INTO START OF TPA.
-	LD	A,BID_RAM0
-	LD	(HB_SRCBNK),A
-	LD	A,BID_USR
-	LD	(HB_DSTBNK),A
-	LD	HL,HB_END
-	LD	DE,0
-	LD	BC,$8000-HB_END
-;
-    #IF (MEMMGR == MM_Z280)
-	CALL	Z280_BNKCPY
-    #ELSE
-	CALL	HBX_BNKCPY
-    #ENDIF
-;
-	; COPY REMAINDER OF PAYLOAD EXTENDING INTO THE SECOND PHYSICAL
-	; RAM BANK.  NOTE THAT THE DESTINATION ADDRESS (DE) IS
-	; ALREADY CORRECT FROM THE PRIOR COPY.
-	LD	A,BID_RAM0+1
-	LD	(HB_SRCBNK),A
-	LD	HL,$0000
-	; DE IS ALREADY CORRECT
-	LD	BC,$8000-($8000-HB_END)
-;
-    #IF (MEMMGR == MM_Z280)
-	CALL	Z280_BNKCPY
-    #ELSE
-	CALL	HBX_BNKCPY
-    #ENDIF
-;
-  #ENDIF
-;
-#ENDIF
-;
 ; IF ALREADY EXECUTING IN RAM, BYPASS RAM BANK INSTALLATION
 ;
+	LD	A,TRUE
+	LD	(HB_RAMFLAG),A
 	LD	A,(HB_RAMFLAG)
 	OR	A
 	JR	NZ,HB_START1
@@ -1712,10 +1659,6 @@ HB_START1:				; BNKCALL ARRIVES HERE, BUT NOW RUNNING IN RAM BANK
 	; NOTIFY THAT WE MADE THE TRANSITION!
 	DIAG(DIAG_03)
 	LED(%00000010)
-;
-	; SET THE IN-RAM FLAG
-	LD	A,TRUE			; ACCUM := TRUE
-	LD	(HB_RAMFLAG),A		; SET RAMFLAG
 ;
 	; RECOVER DATA PASSED PRIOR TO RAM TRANSITION
 	; (HBX_LOC - 1) = BATCOND, (HBX_LOC - 2) = APPBNK
@@ -1914,6 +1857,14 @@ HB_CPU1:
 	LD	A,L
 	LD	(HB_CPUTYPE),A
 ;
+; CLEAR DISPATCH TABLE ENTRIES
+;
+	XOR	A		; ZERO
+	LD	(CIO_CNT),A	; CIO DEVICES
+	LD	(DIO_CNT),A	; DIO DEVICES
+	LD	(VDA_CNT),A	; VDA DEVICES
+	LD	(SND_CNT),A	; SND DEVICES
+;
 #IF (DSRTCENABLE)
 	CALL	DSRTC_PREINIT
 #ENDIF
@@ -3104,11 +3055,7 @@ INITSYS4:
 ; CHAIN TO LOADER
 ;
 #IFDEF ROMBOOT
-  #IF (ROMSIZE > 0)
 	LD	A,BID_IMG0		; CHAIN TO OS IMAGES BANK
-  #ELSE
-	LD	A,BID_USR		; CHAIN TO USER BANK
-  #ENDIF
 #ELSE
 	LD	A,BID_USR		; CHAIN TO USER BANK
 #ENDIF
@@ -3351,6 +3298,9 @@ HB_INITTBL:
 #IF (PPPENABLE)
 	.DW	PPP_INIT
 #ENDIF
+#IF (CHENABLE)
+	.DW	CH_INIT
+#ENDIF
 #IF (ESPENABLE)
 	.DW	ESP_INIT
 #ENDIF
@@ -4146,10 +4096,6 @@ SYS_RESINT:
 ; GO BACK TO ROM BOOT LOADER
 ;
 SYS_RESWARM:
-;
-#IF (ROMSIZE == 0)
-	JR	SYS_RESCOLD
-#ENDIF
 ;
 	CALL	SYS_RESINT
 ;
@@ -4168,13 +4114,6 @@ SYS_RESWARM:
 ;
 SYS_RESCOLD:
 ;
-#IF (ROMSIZE == 0)
-	LD	DE,STR_RESTART
-	CALL	Z,WRITESTR
-	DI
-	HALT
-#ENDIF
-;
 #IF (MEMMGR == MM_Z280)
 	JP	Z280_RESTART
 #ELSE
@@ -6525,6 +6464,15 @@ SIZ_PPP		.EQU	$ - ORG_PPP
 		.ECHO	" bytes.\n"
 #ENDIF
 ;
+#IF (CHENABLE)
+ORG_CH		.EQU	$
+  #INCLUDE "ch.asm"
+SIZ_CH		.EQU	$ - ORG_CH
+		.ECHO	"CH occupies "
+		.ECHO	SIZ_CH
+		.ECHO	" bytes.\n"
+#ENDIF
+;
 #IF (ESPENABLE)
 ORG_ESP		.EQU	$
  #INCLUDE "esp.asm"
@@ -7398,6 +7346,8 @@ PS_DDHDSK	.TEXT	"HDSK$"
 PS_DDPPA	.TEXT	"PPA$"
 PS_DDIMM	.TEXT	"IMM$"
 PS_DDSYQ	.TEXT	"SYQ$"
+PS_DDCHUSB	.TEXT	"CHUSB$"
+PS_DDCHSD	.TEXT	"CHSD$"
 ;
 ; DISK TYPE STRINGS
 ;
@@ -7790,7 +7740,6 @@ STR_LOWBAT	.DB	"\r\n\r\n+++ LOW BATTERY +++$"
 STR_PANIC	.TEXT	"\r\n>>> PANIC: $"
 STR_SYSCHK	.TEXT	"\r\n>>> SYSCHK: $"
 STR_CONTINUE	.TEXT	"\r\nContinue (Y/N)? $"
-STR_RESTART	.TEXT	"\r\n\r\n>>> Press hardware reset button to restart system\r\n\r\n$"
 ;
 #IF (DSKYENABLE)	;	'H','B','I','O',' ',' ',' ',' '
 MSG_HBVER		.DB	$76,$7F,$30,$3F,$00,$00,$00,$00	; "HBIO    "
--- a/Source/HBIOS/hbios.inc
+++ b/Source/HBIOS/hbios.inc
@@ -340,6 +340,8 @@ DIODEV_HDSK	.EQU	$90
 DIODEV_PPA	.EQU	$A0
 DIODEV_IMM	.EQU	$B0
 DIODEV_SYQ	.EQU	$C0
+DIODEV_CHUSB	.EQU	$D0
+DIODEV_CHSD	.EQU	$E0
 ;
 ; RTC DEVICE IDS
 ;
@@ -433,9 +435,9 @@ HCB_BIDUSR	.EQU	$D9		; USER BANK (TPA)
 HCB_BIDBIOS	.EQU	$DA		; BIOS BANK (HBIOS, UBIOS)
 HCB_BIDAUX	.EQU	$DB		; AUX BANK (BPBIOS)
 HCB_BIDRAMD0	.EQU	$DC		; FIRST BANK OF RAM DRIVE
-HCB_BIDRAMDN	.EQU	$DD		; LAST BANK OF RAM DRIVE
+HCB_RAMD_BNKS	.EQU	$DD		; RAM DRIVE BANK COUNT
 HCB_BIDROMD0	.EQU	$DE		; FIRST BANK OF ROM DRIVE
-HCB_BIDROMDN	.EQU	$DF		; LAST BANK OF ROM DRIVE
+HCB_ROMD_BNKS	.EQU	$DF		; ROM DRIVE BANK COUNT
 ;
 ; HBIOS PROXY COMMON DATA BLOCK
 ; EXACTLY 32 BYTES AT $FFE0-$FFFF
--- a/Source/HBIOS/md.asm
+++ b/Source/HBIOS/md.asm
@@ -72,32 +72,30 @@ MD_INIT:
 ;
 #IF (MDROM)
 	PRTS(" ROMDISK=$")
-;	LD	HL,ROMSIZE - 128
-	LD	A,(HCB + HCB_ROMBANKS)	; GET NUMBER OF BANKS
-	SUB	(TOT_ROM_RB)
-	LD	L,A
-	LD	H,0			; CALCULATE RAM SIZE
+	LD	A,(CB_ROMD_BNKS)	; ROM DISK SIZE IN BANKS
+	LD	L,A			; PUT IN L
+	LD	H,0			; CALCULATE ROM DISK SIZE
 	ADD	HL,HL			; X2
 	ADD	HL,HL			; X4
 	ADD	HL,HL			; X8
 	ADD	HL,HL			; X16
 	ADD	HL,HL			; X32
+	LD	(MD_ROMDSIZE),HL	; SAVE ROM DISK SIZE
 	CALL	PRTDEC
 	PRTS("KB$")
 #ENDIF
 ;
 #IF (MDRAM)
 	PRTS(" RAMDISK=$")
-;	LD	HL,RAMSIZE - 256
-	LD	A,(HCB + HCB_RAMBANKS)	; GET NUMBER OF BANKS
-	SUB	(TOT_RAM_RB)		; LESS RESERVED BANKS
-	LD	L,A
-	LD	H,0			; CALCULATE RAM SIZE
+	LD	A,(CB_RAMD_BNKS)	; RAM DISK SIZE IN BANKS
+	LD	L,A			; PUT IN L
+	LD	H,0			; CALCULATE RAM DISK SIZE
 	ADD	HL,HL			; X2
 	ADD	HL,HL			; X4
 	ADD	HL,HL			; X8
 	ADD	HL,HL			; X16
 	ADD	HL,HL			; X32
+	LD	(MD_RAMDSIZE),HL	; SAVE RAM DISK SIZE
 	CALL	PRTDEC
 	PRTS("KB$")
 #ENDIF
@@ -183,21 +181,18 @@ MD_CAP:					; ASSUMES THAT UNIT 0 IS RAM, UNIT 1 IS ROM
 	SYSCHKERR(ERR_NOUNIT)		; INVALID UNIT
 	RET
 MD_CAP0:
-	LD	A,(HCB + HCB_RAMBANKS)	; POINT TO RAM BANK COUNT
-	LD	B,TOT_RAM_RB		; SET # RESERVED RAM BANKS
-	JR	MD_CAP2
+	; RAM DISK SIZE
+	LD	HL,(MD_RAMDSIZE)	; SIZE IN KB
+	JR	MD_CAP2			; CONTINUE
 MD_CAP1:
-	LD	A,(HCB + HCB_ROMBANKS)	; POINT TO ROM BANK COUNT
-	LD	B,TOT_ROM_RB		; SET # RESERVED ROM BANKS
+	; ROM DISK SIZE
+	LD	HL,(MD_ROMDSIZE)	; SIZE IN KB
 MD_CAP2:
-	SUB	B			; SUBTRACT OUT RESERVED BANKS
-	LD	H,A			; H := # BANKS
-	LD	E,64			; # 512 BYTE BLOCKS / BANK
-	CALL	MULT8			; HL := TOTAL # 512 BYTE BLOCKS
-	LD	DE,0			; NEVER EXCEEDS 64K, ZERO HIGH WORD
+	ADD	HL,HL			; CONVERT TO BLOCK COUNT
+	LD	DE,0			; FILL IN HIGH WORD
 	LD	BC,512			; 512 BYTE SECTOR
-	XOR	A
-	RET
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
 ;
 ;
 ;
@@ -1032,6 +1027,8 @@ MD_FFSEN	.DB	00h		; FLASH FILES SYSTEM ENABLE
 ;
 #ENDIF
 ;
+MD_ROMDSIZE	.DW	0
+MD_RAMDSIZE	.DW	0
 MD_RWFNADR	.DW	0
 MD_DSKBUF	.DW	0
 MD_SRCBNK	.DB	0
--- a/Source/HBIOS/romldr.asm
+++ b/Source/HBIOS/romldr.asm
@@ -140,7 +140,8 @@ start:
 	rst	08			; do it
 	ld	a,c			; previous bank to A
 	ld	(bid_ldr),a		; save previous bank for later
-	bit	7,a			; starting from ROM?
+	;;;bit	7,a			; starting from ROM?
+	cp	BID_IMG0		; ROM startup?
 #endif
 ;
 #if (BIOS == BIOS_UNA)
@@ -2189,7 +2190,9 @@ err:
 	ld	hl,str_err_prefix
 	call	pstr
 	pop	hl
-	jp	pstr
+	call	pstr
+	or	$ff			; signal error
+	ret				; done
 ;
 str_err_prefix	.db	bel,"\r\n\r\n*** ",0
 str_err_invcmd	.db	"Invalid command",0
--- a/Source/HBIOS/std.asm
+++ b/Source/HBIOS/std.asm
@@ -566,10 +566,8 @@ SYSTIM	.SET	TM_Z280
 ;
 ; MEMORY BANK CONFIGURATION
 ;
-WBW_ROM_R	.EQU	128	; 128K			; RESERVED ROM REQUIRED FOR ROMWBW
-WBW_RAM_R	.EQU	256	; 256K			; RESERVED RAM REQUIRED FOR ROMWBW
-TOT_ROM_RB	.EQU	(WBW_ROM_R / 32)		; TOTAL ROM BANKS RESERVED
-TOT_RAM_RB	.EQU	(WBW_RAM_R / 32)		; TOTAL RAM BANKS RESERVED
+ROMBANKS	.EQU	(ROMSIZE / 32)			; TOTAL ROM BANKS
+RAMBANKS	.EQU	(RAMSIZE / 32)			; TOTAL RAM BANKS
 ;
 #IF (BIOS == BIOS_UNA)
 BID_ROM0	.EQU	$0000
@@ -580,26 +578,45 @@ BID_RAM0	.EQU	$8000
 BID_ROM0	.EQU	$00
 BID_RAM0	.EQU	$80
 #ENDIF
-
-BID_ROMN	.EQU	(BID_ROM0 + ((ROMSIZE / 32) - 1))
-BID_RAMN	.EQU	(BID_RAM0 + ((RAMSIZE / 32) - 1))
 ;
-BID_RAMD0	.EQU	BID_RAM0	; FIRST RAM DRIVE BANK			 ^  RAM
-BID_RAMDN	.EQU	BID_RAMN - TOT_RAM_RB	; LAST RAM DRIVE BANK		 |  DRIVE
-;					; OS BUFFERS CP/M3?			-+ THESE	CPM3 BNK 5 (BUF)
-;					; OS BUFFERS CP/M3?			 | MAKE		CPM3 BNK 4 (BUF)
-;					; OS BUFFERS CP/M3?			 | UP		CPM3 BNK 3 (BUF)
-;					; OS BUFFERS CP/M3?			 | THE		CPM3 BNK 2 (BUF)
-BID_AUX		.EQU	BID_RAMN - 3	; AUX BANK (BPBIOS, ETC.)		 | 256KB	CPM3 BNK 1 (TPA)
-BID_BIOS	.EQU	BID_RAMN - 2	; BIOS BANK				 | RESERVED
-BID_USR		.EQU	BID_RAMN - 1	; USER BANK (CP/M TPA, ETC.)		 | RAM		CPM3 BNK 0 (OS)
-BID_COM		.EQU	BID_RAMN - 0	; COMMON BANK, UPPER 32K		-+ BANKS
-BID_BOOT	.EQU	BID_ROM0 + 0	; BOOT BANK				-+ THESE MAKE
-BID_IMG0	.EQU	BID_ROM0 + 1	; ROM LOADER AND FIRST IMAGES BANK	 | UP THE 128KB
-BID_IMG1	.EQU	BID_ROM0 + 2	; SECOND IMAGES BANK		 	 | RESERVED
-BID_IMG2	.EQU	BID_ROM0 + 3	; NETWORK BOOT				-+ ROM BANKS
-BID_ROMD0	.EQU	BID_ROM0 + 4	; FIRST ROM DRIVE BANK			 |  ROM
-BID_ROMDN	.EQU	BID_ROMN	; LAST ROM DRIVE BANK			 V  DRIVE
+BID_ROMN	.EQU	(BID_ROM0 + ROMBANKS - 1)
+BID_RAMN	.EQU	(BID_RAM0 + RAMBANKS - 1)
+;
+#IF (ROMSIZE > 0)
+;										-- TYPICAL --
+BID_BOOT	.EQU	BID_ROM0 + 0	; BOOT BANK				0x00
+BID_IMG0	.EQU	BID_ROM0 + 1	; ROM LOADER AND FIRST IMAGES BANK	0x01
+BID_IMG1	.EQU	BID_ROM0 + 2	; SECOND IMAGES BANK		 	0x02
+BID_IMG2	.EQU	BID_ROM0 + 3	; RESERVED				0x03
+BID_ROMD0	.EQU	BID_ROM0 + 4	; FIRST ROM DRIVE BANK			0x04
+BID_ROMDN	.EQU	BID_ROMN	; LAST ROM DRIVE BANK			0x0F
+;
+BID_BIOS	.EQU	BID_RAM0	; HBIOS BANK				0x80
+BID_RAMD0	.EQU	BID_RAM0 + 1	; FIRST RAM DRIVE BANK			0x81
+BID_RAMDN	.EQU	BID_RAMN - 4	; LAST RAM DRIVE BANK			0x8B
+BID_BUF		.EQU	BID_RAMN - 3	; OS BUFFERS (CP/M3)			0x8C
+BID_AUX		.EQU	BID_RAMN - 2	; AUX BANK (CP/M 3, BPBIOS, ETC.)	0x8D
+BID_USR		.EQU	BID_RAMN - 1	; USER BANK (CP/M TPA, ETC.)		0x8E
+BID_COM		.EQU	BID_RAMN - 0	; COMMON BANK, UPPER 32K		0x8F
+;
+#ELSE
+;										-- TYPICAL --
+BID_BOOT	.EQU	BID_RAM0 + 0	; BOOT BANK				0x80
+BID_IMG0	.EQU	BID_RAM0 + 1	; ROM LOADER AND FIRST IMAGES BANK	0x81
+BID_IMG1	.EQU	BID_RAM0 + 2	; SECOND IMAGES BANK		 	0x82
+BID_IMG2	.EQU	BID_RAM0 + 3	; RESERVED				0x83
+BID_RAMD0	.EQU	BID_RAM0 + 4	; FIRST RAM DRIVE BANK			0x84
+BID_RAMDN	.EQU	BID_RAMN - 4	; LAST RAM DRIVE BANK			0x8B
+BID_BUF		.EQU	BID_RAMN - 3	; OS BUFFERS (CP/M3)			0x8C
+BID_AUX		.EQU	BID_RAMN - 2	; AUX BANK (CP/M 3, BPBIOS, ETC.)	0x8D
+BID_USR		.EQU	BID_RAMN - 1	; USER BANK (CP/M TPA, ETC.)		0x8E
+BID_COM		.EQU	BID_RAMN - 0	; COMMON BANK, UPPER 32K		0x8F
+;
+BID_BIOS	.EQU	BID_BOOT	; HBIOS BANK				0x80
+BID_ROMD0	.EQU	0		; NO ROM DRIVE
+BID_ROMDN	.EQU	$FF		; NO ROM DRIVE
+;
+#ENDIF
 ;
 #IF (ROMSIZE == 0)
 BID_BOOT	.SET	BID_RAM0	; SPECIAL CASE ROM-LESS SYSTEM
@@ -609,17 +626,21 @@ BID_BOOT	.SET	BID_RAM0	; SPECIAL CASE ROM-LESS SYSTEM
 ;
  #IF (!MDRAM)
 BID_RAMD0	.SET	$FF		; RAM DRIVE DISABLED
-BID_RAMDN	.SET	$FF		; RAM DRIVE DISABLED
+BID_RAMDN	.SET	0		; RAM DRIVE DISABLED
  #ENDIF
 ;
  #IF (!MDROM)
 BID_ROMD0	.SET	$FF		; ROM DRIVE DISABLED
-BID_ROMDN	.SET	$FF		; ROM DRIVE DISABLED
+BID_ROMDN	.SET	0		; ROM DRIVE DISABLED
  #ENDIF
 ;
+ROMD_BNKS	.EQU	(BID_ROMDN - BID_ROMD0 + 1)
+RAMD_BNKS	.EQU	(BID_RAMDN - BID_RAMD0 + 1)
+;
 #ENDIF
 ;
-#IF FALSE
+#IF TRUE
+	.ECHO "BID_BUF: " \ .ECHO BID_BUF \ .ECHO "\n"
 	.ECHO "BID_AUX: " \ .ECHO BID_AUX \ .ECHO "\n"
 	.ECHO "BID_BIOS: " \ .ECHO BID_BIOS \ .ECHO "\n"
 	.ECHO "BID_USR: " \ .ECHO BID_USR \ .ECHO "\n"
--- a/Source/Makefile
+++ b/Source/Makefile
@@ -1,8 +1,37 @@
 #
 # order is actually important, because of build dependencies
 #
+BUILDPROP := 1
+UNAME := $(shell uname)
+ifeq ($(UNAME), Linux)
+# Inhibit building Propeller on unsupported
+# Linux host architectures such as ARM eg. Raspberry Pi
+	BUILDPROP := 0
+	ARCH := $(shell uname -m)
+	ifeq ($(ARCH), x86_64)
+		BUILDPROP := 1
+	endif
+	ifeq ($(ARCH), i686)
+		BUILDPROP := 1
+	endif
+	ifeq ($(ARCH), i386)
+		BUILDPROP := 1
+	endif
+	ifeq ($(ARCH), x86)
+		BUILDPROP := 1
+	endif
+# Add here any more supported x86 based
+# uname machine strings for building Propeller
+endif
+
 SUBDIRS = HDIAG
+
+ifeq ($(BUILDPROP), 1)
 SUBDIRS += Prop
+else
+$(info "Builing Propeller is not supported on this $(ARCH) host Linux OS")
+endif
+
 SUBDIRS += Apps
 SUBDIRS += CBIOS
 SUBDIRS += Forth
--- a/Source/ver.inc
+++ b/Source/ver.inc
@@ -2,7 +2,7 @@
 #DEFINE	RMN	3
 #DEFINE	RUP	0
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.3.0-dev.54"
+#DEFINE BIOSVER	"3.3.0-dev.58"
 #define rmj	RMJ
 #define rmn	RMN
 #define rup	RUP
--- a/Source/ver.lib
+++ b/Source/ver.lib
@@ -3,5 +3,5 @@ rmn	equ	3
 rup	equ	0
 rtp	equ	0
 biosver	macro
-	db	"3.3.0-dev.54"
+	db	"3.3.0-dev.58"
 	endm
--- a/Tools/unix/zxcc/zxcc.c
+++ b/Tools/unix/zxcc/zxcc.c
@@ -127,7 +127,15 @@ void load_bios(void)
 		uint32_t size = CPM_MAXPATH - 8;
 		_NSGetExecutablePath(dir, &size);
 #else
-		readlink("/proc/self/exe", dir, CPM_MAXPATH - 8);   /* allow room for bios.bin */
+		ssize_t len;
+		len = readlink("/proc/self/exe", dir, CPM_MAXPATH - 8);   /* allow room for bios.bin */
+		if (len < 0)
+		{
+			/* len of -1 indicates an error occurred */
+			len = 0;
+		}
+		/* Terminate the dir string with a NUL character */
+		dir[len] = 0;
 #endif
 		q = strrchr(dir, DIRSEPCH);
 		*++q = 0;
Author	SHA1	Message	Date
Wayne Warthen	883dab7e97	ROMless Operation Overhaul - Implement new approach to ROMless boot and operation. Still missing the ability to seed the RAM disk. - Tweaks to CH driver	2023-10-01 17:22:19 -07:00
Wayne Warthen	d3f5643791	CH Driver Tweaks	2023-09-24 16:47:36 -07:00
Wayne Warthen	5299d24379	Merge pull request #363 from skullandbones/Issue-362_RPI4_no_bios.bin_v1 zxcc: Fix for load bios.bin failure on a RPi4	2023-09-24 16:25:50 -07:00
Dean Jenkins	a229db96a6	zxcc: Fix for load bios.bin failure on a RPi4 Fix load_bios() when used on a Raspberry Pi4. The defect was corrupting the path of the zxcc executable. The fix is to NUL terminate the path string from the readlink() call.	2023-09-24 17:04:35 +01:00
Wayne Warthen	092e44c62e	RPi Builds & CH375/6 Support - The build process was enhanced by Dean Jenkins to support the Raspberry Pi. Note that the Propeller firmware will not be generated by a RPi build. See Issue #358. - Initial support for USB storage via CH375/6.	2023-09-22 14:13:12 -07:00
Wayne Warthen	722bce819b	Bump Version	2023-09-16 13:41:32 -07:00
Wayne Warthen	2d470a2a90	Merge pull request #360 from danwerner21/dev ESP32 Driver updates	2023-09-16 13:24:08 -07:00
Dan Werner	b6700dfa4c	ESP32 Driver updates	2023-09-16 14:47:09 -05:00