Update FAT.COM on ROM disks

The original release of v3.4 contained an out-of-date copy of FAT.COM on the ROM disks.  This **only** updates FAT.COM on the ROM disks.  Do **not** use FAT.COM from the original ROM disks.
- The copy of FAT.COM on the hard/floppy disk images was fine in the original release.  Only the ROM disks contained the out-of-date version.
- It is not necessary to update your hard/floppy disks when upgrading your ROM to this patch version.

.github/pull_request_template.md

@@ -1,7 +1,7 @@
 <!--
 BEFORE YOU CREATE A PULL REQUEST:
 
-- Please base all pull requests against the dev branch
+- Please base all pull requests against the master branch
 - Include a clear description of your change
 - Reference related Issue(s) (e.g., "Resolves Issue #123")
 

.gitignore

@@ -95,6 +95,7 @@ Tools/unix/zx/zx
 !Source/ZPM3/*.[Cc][Oo][Mm]
 !Source/ZSDOS/*.[Cc][Oo][Mm]
 !Source/ZRC/*.bin
+!Source/ZRC512/*.bin
 !Source/Z1RCC/*.bin
 !Source/ZZRCC/*.bin
 !Tools/cpm/**

Doc/ChangeLog.txt

@@ -4,10 +4,40 @@ NOTE: Changes require HBIOS/CBIOS/Apps sync, version bump to 3.4 to ensure integ
 - WBW: Device type number moved from upper nibble to full byte
 - A?C: Support for EP ITX-Mini Z180 Platform
 - M?R: Significant improvement in User Guide document
-
+- J?P: Preliminary support for Monsputer (MON)
+- JLC: Standardize TMS driver memory map for compatibility
+- WBW: Improved IDE device detection
+- WBW: Fixed decompression when run on Z280
+- K?B: WDATE generic HBIOS date/time utility
+- WBW: Create new DSKY framework with simple driver style interface
+- JBL: Added ColecoVision config in TMS driver
+- WBW: Added support for interrupt mode 1 on Z180
+- WBW: Added S100 platform
+- WBW: Added Duodyne platform
+- WBW: Incorporated John Monahan's S100 Monitor in S100 platform build
+- WBW: Support ESP32 on Duodyne
+- M?C: Fixed port specification when using XM.COM send transfers
+- PMS: Support for Duodyne DMA
+- WBW: Added Serial ROM (SROM.COM) utility
+- WBW: Support S100 Propeller Console
+- SCC: Added support for SC700
+- WBW: Added Heath H8 platform
+- D?J: Enhanced build to run on Raspberry Pi 4
+- WBW: Complete overhaul of ROMless boot operation
+- WBW: Prevent access to slices outside of partition
+- T?P: Contributed the HTALK utility
+- WBW: CTS stall detection
+- W?S: Updated FLASH utility to v1.3.7
+- L?N: Updated UNARC to new OS universal version
+- B?C: Added support for Z1RCC
+- M?R: User Guide enhancements and corrections
+- D?H: Added support for specification of secondary console
+- WBW: Added platform for Monsputer
+- WBW: Added FAT.COM to standard ROM Disk (removed RMAC.COM & LINK.COM)
 
 Version 3.3
 -----------
+NOTE: v3.3 was never released
 - WBW: Support Front Panel switches
 - A?C: Preliminary support for Z80-Retro
 - A?C: Support for SD PIO
@@ -15,7 +45,7 @@ Version 3.3
 - WBW: Support per-drive floppy configuration
 - WBW: Support for Bill Shen's VGARC
 - WBW: Support for MG014 Parallel Port module + printer
-- WBW: Support for EMM Zip Drive on PPI interface (much inspiration from Alan Cox)
+- WBW: Support for IMM Zip Drive on PPI interface (much inspiration from Alan Cox)
 - WBW: Support for PPA Zip Drive on PPI interface (much inspiration from Alan Cox)
 - WBW: Support for SyQuest SparQ Drive on PPI interface (much inspiration from Alan Cox)
 - WBW: Support for ATAPI Disk Drives (not CD-ROMs) on IDE and PPIDE interfaces

ReadMe.md

@@ -3,7 +3,7 @@
 **RomWBW ReadMe** \
 Version 3.4 \
 Wayne Warthen  ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \
-29 Nov 2023
+30 Dec 2023
 
 # Overview
 
@@ -14,15 +14,24 @@ platforms are supported including those produced by these developer
 communities:
 
 - [RetroBrew Computers](https://www.retrobrewcomputers.org)
-- [RC2014](https://rc2014.co.uk),
+  (<https://www.retrobrewcomputers.org>)
+- [RC2014](https://rc2014.co.uk) (<https://rc2014.co.uk>),  
   [RC2014-Z80](https://groups.google.com/g/rc2014-z80)
-- [retro-comp](https://groups.google.com/forum/#!forum/retro-comp)
+  (<https://groups.google.com/g/rc2014-z80>)
+- [Retro Computing](https://groups.google.com/g/retro-comp)
+  (<https://groups.google.com/g/retro-comp>)
 - [Small Computer Central](https://smallcomputercentral.com/)
+  (<https://smallcomputercentral.com/>)
+
+A complete list of the currently supported platforms is found in the
+\[Installation\] section.
 
 General features include:
 
+- Z80 Family CPUs including Z80, Z180, and Z280
 - Banked memory services for several banking designs
-- Disk drivers for RAM, ROM, Floppy, IDE, CF, and SD
+- Disk drivers for RAM, ROM, Floppy, IDE ATA/ATAPI, CF, SD, USB, Zip,
+  Iomega
 - Serial drivers including UART (16550-like), ASCI, ACIA, SIO
 - Video drivers including TMS9918, SY6545, MOS8563, HD6445
 - Keyboard (PS/2) drivers via VT8242 or PPI interfaces
@@ -42,11 +51,11 @@ ROM firmware itself:
 
 A dynamic disk drive letter assignment mechanism allows mapping
 operating system drive letters to any available disk media.
-Additionally, mass storage devices (IDE Disk, CF Card, SD Card) support
-the use of multiple slices (up to 256 per device). Each slice contains a
-complete CP/M filesystem and can be mapped independently to any drive
-letter. This overcomes the inherent size limitations in legacy OSes and
-allows up to 2GB of accessible storage on a single device.
+Additionally, mass storage devices (IDE Disk, CF Card, SD Card, etc.)
+support the use of multiple slices (up to 256 per device). Each slice
+contains a complete CP/M filesystem and can be mapped independently to
+any drive letter. This overcomes the inherent size limitations in legacy
+OSes and allows up to 2GB of accessible storage on a single device.
 
 The pre-built ROM firmware images are generally suitable for most users.
 However, it is also very easy to modify and build custom ROM images that
@@ -66,7 +75,7 @@ changing media.
 By design, RomWBW isolates all of the hardware specific functions in the
 ROM chip itself. The ROM provides a hardware abstraction layer such that
 all of the operating systems and applications on a disk will run on any
-RomWBW-based system. To put it simply, you can take a disk (or CF/SD
+RomWBW-based system. To put it simply, you can take a disk (or CF/SD/USB
 Card) and move it between systems transparently.
 
 A tool is provided that allows you to access a FAT-12/16/32 filesystem.
@@ -76,18 +85,19 @@ OSes such as Windows, MacOS, and Linux very easy.
 
 # Acquiring RomWBW
 
-The [RomWBW Repository](https://github.com/wwarthen/RomWBW) on GitHub is
-the official distribution location for all project source and
-documentation. The fully-built distribution releases are available on
-the [RomWBW Releases Page](https://github.com/wwarthen/RomWBW/releases)
-of the repository. On this page, you will normally see a Development
-Snapshot as well as recent stable releases. Unless you have a specific
-reason, I suggest you stick to the most recent stable release. Expand
-the “Assets” drop-down for the release you want to download, then select
-the asset named RomWBW-vX.X.X-Package.zip. The Package asset includes
-all pre-built ROM and Disk images as well as full source code. The other
-assets contain only source code and do not have the pre-built ROM or
-disk images.
+The [RomWBW Repository](https://github.com/wwarthen/RomWBW)
+(<https://github.com/wwarthen/RomWBW>) on GitHub is the official
+distribution location for all project source and documentation. The
+fully-built distribution releases are available on the [RomWBW Releases
+Page](https://github.com/wwarthen/RomWBW/releases)
+(<https://github.com/wwarthen/RomWBW/releases>) of the repository. On
+this page, you will normally see a Development Snapshot as well as
+recent stable releases. Unless you have a specific reason, I suggest you
+stick to the most recent stable release. Expand the “Assets” drop-down
+for the release you want to download, then select the asset named
+RomWBW-vX.X.X-Package.zip. The Package asset includes all pre-built ROM
+and Disk images as well as full source code. The other assets contain
+only source code and do not have the pre-built ROM or disk images.
 
 All source code and distributions are maintained on GitHub. Code
 contributions are very welcome.
@@ -187,6 +197,32 @@ let me know if I missed you!
   Aztec C, HiTech C, SLR Z80ASM, Turbo Pascal, Microsoft BASIC Compiler,
   Microsoft Fortran Compiler, and a Games compendium.
 
+- Martin R has provided substantial help reviewing and improving the
+  User Guide.
+
+- Jacques Pelletier has contributed the DS1501 RTC driver code.
+
+- Jose Collado has contributed enhancements to the TMS driver including
+  compatibility with standard TMS register configuration.
+
+- Kevin Boone has contributed a generic HBIOS date/time utility (WDATE).
+
+- Matt Carroll has contributed a fix to XM.COM that corrects the port
+  specification when doing a send.
+
+- Dean Jenkins enhanced the build process to accommodate the Raspberry
+  Pi 4.
+
+- Tom Plano has contributed a new utility (HTALK) to allow talking
+  directly to HBIOS COM ports.
+
+- Lars Nelson has contributed several generic utilities such as a
+  universal (OS agnostic) UNARC application.
+
+- Dylan Hall added support for specifying a secondary console.
+
+- Bill Shen has contributed boot loaders for several of his systems.
+
 Contributions of all kinds to RomWBW are very welcome.
 
 # Licensing

ReadMe.txt

@@ -1,6 +1,6 @@
 RomWBW ReadMe
 Wayne Warthen (wwarthen@gmail.com)
-29 Nov 2023
+30 Dec 2023
 
 
 
@@ -13,15 +13,21 @@ Z80/180/280 retro-computing hardware systems. A wide variety of
 platforms are supported including those produced by these developer
 communities:
 
--   RetroBrew Computers
--   RC2014, RC2014-Z80
--   retro-comp
--   Small Computer Central
+-   RetroBrew Computers (https://www.retrobrewcomputers.org)
+-   RC2014 (https://rc2014.co.uk),
+    RC2014-Z80 (https://groups.google.com/g/rc2014-z80)
+-   Retro Computing (https://groups.google.com/g/retro-comp)
+-   Small Computer Central (https://smallcomputercentral.com/)
+
+A complete list of the currently supported platforms is found in the
+[Installation] section.
 
 General features include:
 
+-   Z80 Family CPUs including Z80, Z180, and Z280
 -   Banked memory services for several banking designs
--   Disk drivers for RAM, ROM, Floppy, IDE, CF, and SD
+-   Disk drivers for RAM, ROM, Floppy, IDE ATA/ATAPI, CF, SD, USB, Zip,
+    Iomega
 -   Serial drivers including UART (16550-like), ASCI, ACIA, SIO
 -   Video drivers including TMS9918, SY6545, MOS8563, HD6445
 -   Keyboard (PS/2) drivers via VT8242 or PPI interfaces
@@ -41,11 +47,11 @@ ROM firmware itself:
 
 A dynamic disk drive letter assignment mechanism allows mapping
 operating system drive letters to any available disk media.
-Additionally, mass storage devices (IDE Disk, CF Card, SD Card) support
-the use of multiple slices (up to 256 per device). Each slice contains a
-complete CP/M filesystem and can be mapped independently to any drive
-letter. This overcomes the inherent size limitations in legacy OSes and
-allows up to 2GB of accessible storage on a single device.
+Additionally, mass storage devices (IDE Disk, CF Card, SD Card, etc.)
+support the use of multiple slices (up to 256 per device). Each slice
+contains a complete CP/M filesystem and can be mapped independently to
+any drive letter. This overcomes the inherent size limitations in legacy
+OSes and allows up to 2GB of accessible storage on a single device.
 
 The pre-built ROM firmware images are generally suitable for most users.
 However, it is also very easy to modify and build custom ROM images that
@@ -65,7 +71,7 @@ changing media.
 By design, RomWBW isolates all of the hardware specific functions in the
 ROM chip itself. The ROM provides a hardware abstraction layer such that
 all of the operating systems and applications on a disk will run on any
-RomWBW-based system. To put it simply, you can take a disk (or CF/SD
+RomWBW-based system. To put it simply, you can take a disk (or CF/SD/USB
 Card) and move it between systems transparently.
 
 A tool is provided that allows you to access a FAT-12/16/32 filesystem.
@@ -78,16 +84,18 @@ OSes such as Windows, MacOS, and Linux very easy.
 ACQUIRING ROMWBW
 
 
-The RomWBW Repository on GitHub is the official distribution location
-for all project source and documentation. The fully-built distribution
-releases are available on the RomWBW Releases Page of the repository. On
-this page, you will normally see a Development Snapshot as well as
-recent stable releases. Unless you have a specific reason, I suggest you
-stick to the most recent stable release. Expand the “Assets” drop-down
-for the release you want to download, then select the asset named
-RomWBW-vX.X.X-Package.zip. The Package asset includes all pre-built ROM
-and Disk images as well as full source code. The other assets contain
-only source code and do not have the pre-built ROM or disk images.
+The RomWBW Repository (https://github.com/wwarthen/RomWBW) on GitHub is
+the official distribution location for all project source and
+documentation. The fully-built distribution releases are available on
+the RomWBW Releases Page (https://github.com/wwarthen/RomWBW/releases)
+of the repository. On this page, you will normally see a Development
+Snapshot as well as recent stable releases. Unless you have a specific
+reason, I suggest you stick to the most recent stable release. Expand
+the “Assets” drop-down for the release you want to download, then select
+the asset named RomWBW-vX.X.X-Package.zip. The Package asset includes
+all pre-built ROM and Disk images as well as full source code. The other
+assets contain only source code and do not have the pre-built ROM or
+disk images.
 
 All source code and distributions are maintained on GitHub. Code
 contributions are very welcome.
@@ -189,6 +197,33 @@ let me know if I missed you!
     including Aztec C, HiTech C, SLR Z80ASM, Turbo Pascal, Microsoft
     BASIC Compiler, Microsoft Fortran Compiler, and a Games compendium.
 
+-   Martin R has provided substantial help reviewing and improving the
+    User Guide.
+
+-   Jacques Pelletier has contributed the DS1501 RTC driver code.
+
+-   Jose Collado has contributed enhancements to the TMS driver
+    including compatibility with standard TMS register configuration.
+
+-   Kevin Boone has contributed a generic HBIOS date/time utility
+    (WDATE).
+
+-   Matt Carroll has contributed a fix to XM.COM that corrects the port
+    specification when doing a send.
+
+-   Dean Jenkins enhanced the build process to accommodate the Raspberry
+    Pi 4.
+
+-   Tom Plano has contributed a new utility (HTALK) to allow talking
+    directly to HBIOS COM ports.
+
+-   Lars Nelson has contributed several generic utilities such as a
+    universal (OS agnostic) UNARC application.
+
+-   Dylan Hall added support for specifying a secondary console.
+
+-   Bill Shen has contributed boot loaders for several of his systems.
+
 Contributions of all kinds to RomWBW are very welcome.
 
 

Source/Apps/Build.cmd

@@ -1,13 +1,10 @@
 @echo off
 setlocal
 
-set TOOLS=../../Tools
+set TOOLS=..\..\Tools
 set APPBIN=..\..\Binary\Apps
-
 set PATH=%TOOLS%\tasm32;%TOOLS%\zxcc;%PATH%
-
 set TASMTABS=%TOOLS%\tasm32
-
 set CPMDIR80=%TOOLS%/cpm/
 
 call :asm syscopy || exit /b

Source/Apps/FDU/fdu.asm

@@ -48,7 +48,8 @@
 ;   2020-04-29: v5.5	ADDED SUPPORT FOR ETCHED PIXELS FDC
 ;   2020-12-12: v5.6	UPDATED SMALLZ80 TO NEW I/O ADDRESSES
 ;   2021-03-24: v5.7    ADDED SOME SINGLE-SIDED FORMATS
-;   2021-07-26: v5.8	ADDED SUPPORT MBC FDC
+;   2021-07-26: v5.8	ADDED SUPPORT FOR NHYODYNE (MBC) FDC
+;   2023-12-10: v5.9	ADDED SUPPORT FOR DUODYNE (DUO) FDC
 ;			
 ;_______________________________________________________________________________
 ;
@@ -85,6 +86,7 @@ FDC_SMZ80	.EQU		8
 FDC_DYNO	.EQU		9
 FDC_EPFDC	.EQU		10
 FDC_MBC		.EQU		11
+FDC_DUO		.EQU		12
 ;
 ; FDC MODE
 ;
@@ -219,8 +221,8 @@ INIT5:
 	XOR	A
 	RET
 		
-STR_BANNER	.DB	"Floppy Disk Utility (FDU) v5.8, 26-Jul-2021$"
-STR_BANNER2	.DB	"Copyright (C) 2021, Wayne Warthen, GNU GPL v3","$"
+STR_BANNER	.DB	"Floppy Disk Utility (FDU) v5.9, 10-Dec-2023$"
+STR_BANNER2	.DB	"Copyright (C) 2023, Wayne Warthen, GNU GPL v3","$"
 STR_HBIOS	.DB	" [HBIOS]$"
 STR_UBIOS	.DB	" [UBIOS]$"
 ;
@@ -292,6 +294,7 @@ FDCTBL:	;	LABEL		CONFIG DATA
 	.DW	STR_DYNO,	CFG_DYNO
 	.DW	STR_EPFDC,	CFG_EPFDC
 	.DW	STR_MBC,	CFG_MBC
+	.DW	STR_DUO,	CFG_DUO
 FDCCNT	.EQU	($-FDCTBL)/4	; FD CONTROLLER COUNT
 ;
 ; FDC LABEL STRINGS
@@ -307,7 +310,8 @@ STR_RCWDC	.TEXT	"RC-WDC$"
 STR_SMZ80	.TEXT	"SMZ80$"
 STR_DYNO	.TEXT	"DYNO$"
 STR_EPFDC	.TEXT	"EPFDC$"
-STR_MBC		.TEXT	"MBC$"
+STR_MBC		.TEXT	"NHYODYNE$"
+STR_DUO		.TEXT	"DUODYNE$"
 ;
 ; FDC CONFIGURATION BLOCKS
 ;
@@ -448,7 +452,18 @@ CFG_MBC:
 	.DB	035H	; CONFIGURATION CONTROL REGISTER
 	.DB	036H	; DACK (WHEN READ)
 	.DB	037H	; TERMINAL COUNT (W/ DACK)
-	.DB	0FFH	; NOT USED BY ZETA SBC V2
+	.DB	0FFH	; NOT USED
+	.DB	_PCAT	; MODE=
+;
+CFG_DUO:
+	.DB	080H	; FDC MAIN STATUS REGISTER
+	.DB	081H	; FDC DATA PORT
+	.DB	0FFH	; DATA INPUT REGISTER
+	.DB	086H	; DIGITAL OUTPUT REGISTER (WHEN WRITTEN)
+	.DB	085H	; CONFIGURATION CONTROL REGISTER
+	.DB	086H	; DACK (WHEN READ)
+	.DB	087H	; TERMINAL COUNT (W/ DACK)
+	.DB	0FFH	; NOT USED
 	.DB	_PCAT	; MODE=
 ;
 FDCID	.DB	0			; FDC IDENTIFIER (0 INDEXED)
@@ -470,7 +485,8 @@ FSS_MENU:
 	.TEXT	"  (I) SmallZ80 Expansion\r\n"
 	.TEXT	"  (J) Dyno-Card FDC, D1030\r\n"
 	.TEXT	"  (K) RCBus EPFDC\r\n"
-	.TEXT	"  (L) Multi-Board Computer FDC\r\n"
+	.TEXT	"  (L) Nhyodyne FDC\r\n"
+	.TEXT	"  (M) Duodyne FDC\r\n"
 	.TEXT	"  (X) Exit\r\n"
 	.TEXT	"=== OPTION ===> $\r\n"
 ;	
@@ -1561,6 +1577,7 @@ MD_MAP:
 		.DB	%00000001	; DYNO	POLL
 		.DB	%00000001	; EPFDC	POLL
 		.DB	%00000001	; MBC	POLL
+		.DB	%00000001	; DUO	POLL
 ;
 ; MEDIA DESCRIPTION BLOCK
 ;
@@ -2021,7 +2038,7 @@ FM_DRAW0B:	; ZETA, DIO3
 	LD	A,(FST_DOR)
 	AND	00000010B
 	JR	FM_DRAW1
-FM_DRAW0C:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC, MBC
+FM_DRAW0C:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC, MBC, DUO
 	LD	A,(FST_DOR)
 	AND	11110000B
 	JR	FM_DRAW1
@@ -2174,7 +2191,7 @@ FM_MOTOR0B:	; ZETA, DIO3
 	LD	A,(FST_DOR)
 	AND	00000010B
 	JR	FM_MOTOR1
-FM_MOTOR0C:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC, MBC
+FM_MOTOR0C:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC, MBC, DUO
 	LD	A,(FST_DOR)
 	AND	11110000B
 	JR	FM_MOTOR1
@@ -2913,7 +2930,7 @@ FC_INIT1:	; DIO
 FC_INIT2:	; ZETA, DIO3
 	LD	A,(FCD_DORB)
 	JR	FC_INIT5
-FC_INIT3:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC, MBC
+FC_INIT3:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC, MBC, DUO
 	LD	A,(FCD_DORC)
 	JR	FC_INIT5
 FC_INIT4:	; WDSMC
@@ -2957,7 +2974,7 @@ FC_RESETFDC1:	; ZETA, DIO3, RCSMC
 	POP	AF
 	OUT	(C),A
 	JR	FC_RESETFDC3
-FC_RESETFDC2:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC, MBC
+FC_RESETFDC2:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC, MBC, DUO
 	LD	A,0
 	OUT	(C),A
 	LD	A,(FST_DOR)
@@ -2984,7 +3001,7 @@ FC_PULSETC:
 	;RES	0,A
 	;OUT	(C),A
 	;JR	FC_PULSETC2
-;FC_PULSETC1:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC, MBC
+;FC_PULSETC1:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC, MBC, DUO
 	;LD	C,(IY+CFG_TC)
 	;IN	A,(C)
 	;JR	FC_PULSETC2
@@ -3016,7 +3033,7 @@ FC_MOTORON2:	; ZETA, DIO3
 	LD	HL,FST_DOR		; POINT TO FDC_DOR
 	SET	1,(HL)
 	JR	FC_MOTORON5
-FC_MOTORON3:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC, MBC
+FC_MOTORON3:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC, MBC, DUO
 	LD	HL,FST_DOR		; POINT TO FDC_DOR
 	LD	A,(HL)			; START WITH CURRENT DOR
 	AND	11111100B		; GET RID OF ANY ACTIVE DS BITS
@@ -3080,7 +3097,7 @@ FC_MOTOROFF2:	; ZETA, DIO3
 	LD	HL,FST_DOR		; POINT TO FDC_DOR
 	RES	1,(HL)
 	JR	FC_MOTOROFF5
-FC_MOTOROFF3:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC, MBC
+FC_MOTOROFF3:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC, MBC, DUO
 	LD	HL,FST_DOR		; POINT TO FDC_DOR
 	LD	A,DORC_INIT
 	LD	(HL),A
@@ -3950,7 +3967,7 @@ DORB_BR500	.EQU	10100000B	; 500KBPS
 ;
 DORB_INIT	.EQU	DORB_BR250
 ;
-; *** DIDE/N8/ZETA2/RCWDC/SMZ80/DYNO/EPFDC/MBC ***
+; *** DIDE/N8/ZETA2/RCWDC/SMZ80/DYNO/EPFDC/MBC/DUO ***
 ;
 DORC_INIT	.EQU	00001100B	; SOFT RESET INACTIVE, DMA ENABLED
 ;

Source/Apps/FDU/fdu.doc

@@ -1,14 +1,15 @@
 ================================================================
-Floppy Disk Utility (FDU) v5.3 for RetroBrew Computers 
-Disk IO / Zeta / Dual-IDE / N8 / RCBus / SmallZ80 / Dyno
+Floppy Disk Utility (FDU) v5.9 for RetroBrew Computers 
+Disk IO / Zeta / Dual-IDE / N8 / RCBus / SmallZ80 / Dyno / Nhyodyne / Duodyne
 ================================================================
 
-Updated January 5, 2020
+Updated December 12, 2023
 by Wayne Warthen (wwarthen@gmail.com)
 
 Application to test the hardware functionality of the Floppy 
 Disk Controller (FDC) on the ECB DISK I/O, DISK I/O V3, ZETA 
-SBC, Dual IDE w/ Floppy, or N8 board.
+SBC, Dual IDE w/ Floppy, N8, RCBus, SmallZ80, Dyno, Nhyodyne,
+Duodyne systems.
  
 The intent is to provide a testbed that allows direct testing 
 of all possible media types and modes of access.  The 
@@ -77,9 +78,10 @@ supported:
  - RCBus
  - SmallZ80
  - Dyno
- - MBC
+ - Nhyodyne (MBC)
+ - Duodyne (DUO)
 
-You must be using either a RomWBW or UBA based OS version.
+You must be using either a RomWBW or UNA based OS version.
 
 You must have one of the following floppy disk controllers:
 
@@ -93,7 +95,8 @@ You must have one of the following floppy disk controllers:
  - RCBus Scott Baker WDC-based Floppy Module
  - SmallZ80 FDC
  - Dyno FDC
- - MBC FDC
+ - Nhyodyne (MBC) FDC
+ - Duodyne (DUO) FDC
  
 Finally, you will need a floppy drive connected via an 
 appropriate cable:
@@ -165,8 +168,11 @@ hardwired I/O ranges are assumed in the code.
 Dyno does not have any relevant jumper settings.  The 
 hardwired I/O ranges are assumed in the code.
 
-The MBC FDC is expected to be strapped to use neither INT nor NMI.  It
-is also not expected to use DMA.
+The Nhyodyne (MBC) FDC is expected to be strapped to use neither INT
+nor NMI.  It is also not expected to use DMA.
+
+The Duodyne (DUO) FDC is expected to be strapped to use neither INT
+nor NMI.  It is also not expected to use DMA.
 
 Modes of Operation
 ------------------
@@ -533,4 +539,7 @@ WW 3/24/2021: v5.7
   - Added support for a few single-sided formats
 
 WW 7/26/2021: v5.8
-  - Added support for MBC FDC
+  - Added support for Nhyodyne (MBC) FDC
+
+WW 12/10/2023: v5.9
+  - Added support for Duodyne (DUO) FDC

Source/Apps/cpuspd/cpuspd.asm

@@ -189,9 +189,9 @@ show_spd:
 	ld	b,BF_SYSGET
 	ld	c,BF_SYSGET_CPUINFO
 	rst	08
-	jp	nz,err_not_sup
+	jp	nz,err_api
 	call	crlf2
-	ld	(cpu_spd),de		; save CPU speed for now
+	push	de			; save CPU speed for now
 	push	bc			; Oscillator speed to HL
 	pop	hl
 	ld	de,str_spacer
@@ -199,10 +199,18 @@ show_spd:
 	call	prtd3m			; print it
 	ld	de,str_oscspd
 	call	prtstr
+	call	crlf
+	ld	de,str_cpuspd
+	call	prtstr
+	pop	hl			; recover CPU speed
+	call	prtd3m			; print it
+	ld	de,str_mhz
+	call	prtstr
+;
 	ld	b,BF_SYSGET
 	ld	c,BF_SYSGET_CPUSPD
 	rst	08
-	jp	nz,err_not_sup
+	ret	nz			; no CPU speed info, done
 	push	de			; save wait states for now
 	ld	a,l
 	ld	de,str_slow
@@ -216,11 +224,6 @@ show_spd:
 	jr	z,show_spd1
 	jp	err_invalid
 show_spd1:
-	call	crlf
-	call	prtstr
-	ld	hl,(cpu_spd)		; recover CPU speed
-	call	prtd3m
-	ld	de,str_cpuspd
 	call	prtstr
 	pop	hl
 	ld	a,h			; memory wait states
@@ -284,6 +287,9 @@ err_not_sup:
 err_invalid:
 	ld	de,str_err_invalid
 	jr	err_ret
+err_api:
+	ld	de,str_err_api
+	jr	err_ret
 ;
 err_ret:
 	call	crlf2
@@ -659,21 +665,24 @@ delay1:
 ; Constants
 ;=======================================================================
 ;
-str_banner		.db	"RomWBW CPU Speed Selector v0.5, 2-Feb-2022",0
+str_banner		.db	"RomWBW CPU Speed Selector v0.6, 29-Dec-2023",0
 str_spacer		.db	"  ",0
 str_oscspd		.db	" MHz Oscillator",0
-str_slow		.db	"  CPU speed is HALF (",0
-str_full		.db	"  CPU speed is FULL (",0
-str_dbl			.db	"  CPU speed is DOUBLE (",0
-str_cpuspd		.db	" MHz)",0
+str_cpuspd		.db	"  CPU speed is ",0
+str_mhz			.db	" MHz",0
+
+str_slow		.db	" (Half)",0
+str_full		.db	" (Full)",0
+str_dbl			.db	" (Double)",0
 str_memws		.db	" Memory Wait State(s)",0
 str_iows		.db	" I/O Wait State(s)",0
 str_err_una		.db	"  ERROR: UNA not supported by application",0
 str_err_inv		.db	"  ERROR: Invalid BIOS (signature missing)",0
 str_err_ver		.db	"  ERROR: Unexpected HBIOS version",0
 str_err_parm		.db	"  ERROR: Parameter error (CPUSPD /? for usage)",0
-str_err_not_sup		.db	"  ERROR: Platform or configuration not supported!",0
+str_err_not_sup		.db	"  ERROR: Platform or configuration does not support CPU speed configuration!",0
 str_err_invalid		.db	"  ERROR: Invalid configuration!",0
+str_err_api		.db	"  ERROR: HBIOS API error!",0
 str_usage		.db	"  Usage: CPUSPD <cpuspd>,<memws>,<iows>\r\n"
 			.db	"\r\n"
 			.db	"         <cpuspd>: \"Half\", \"Full\", or \"Double\"\r\n"
@@ -693,7 +702,6 @@ stack		.equ	$		; stack top
 ;
 ;
 tmpstr		.fill	9,0		; temp string (8 chars, 0 term)
-cpu_spd		.dw	0		; current cpu speed
 new_cpu_spd	.db	$FF		; new CPU speed
 new_ws_mem	.db	$FF		; new memory wait states
 new_ws_io	.db	$FF		; new I/O wait states

Source/BPBIOS/Build.cmd

@@ -3,8 +3,8 @@ setlocal
 
 pushd ZCPR33 && call Build || exit /b & popd
 
-set PATH=%PATH%;..\..\Tools\zxcc;..\..\Tools\cpmtools;
-
+set TOOLS=..\..\Tools
+set PATH=%PATH%;%TOOLS%\zxcc;%TOOLS%\cpmtools;
 set CPMDIR80=%TOOLS%/cpm/
 
 call :makebp 33
@@ -48,7 +48,8 @@ if exist bp%VER%.prn del bp%VER%.prn || exit /b
 ren bpbio-ww.prn bp%VER%.prn || exit /b
 if exist bp%VER%.err del bp%VER%.err || exit /b
 ren bpbio-ww.err bp%VER%.err || exit /b
-copy bpbio-ww.rel bp%VER%.rel || exit /b
+if exist bp%VER%.rel del bp%VER%.rel || exit /b
+ren bpbio-ww.rel bp%VER%.rel || exit /b
 
 rem pause
 

Source/BPBIOS/Makefile

@@ -1,44 +1,37 @@
 VERSIONS = \
-	33t 33tbnk \
-	33n 33nbnk \
-	34t 34tbnk \
-	34n 34nbnk \
-	41tbnk 41nbnk
+	33 33bnk \
+	33 33bnk \
+	34 34bnk \
+	34 34bnk \
+	41bnk
 
-HD0IMG = ../../Binary/hd_bp.img
 IMGFILES = $(foreach ver,$(VERSIONS),bp$(ver).img)
 DISTFILES = *.zex *.rel myterm.z3t
 
-OTHERS = zcpr33n.rel zcpr33t.rel \
-	bpbio-ww.rel bpsys.dat bpsys.bak bpbio-ww.err def-ww.lib *.img
+OTHERS = zcpr33.rel bp*.prn bp*.rel \
+	bpbio-ww.rel bpsys.dat bpsys.bak bpbio-ww.err def-ww.lib bp*.img
 
 TOOLS = ../../Tools
 
 SUBDIRS = ZCPR33
 include $(TOOLS)/Makefile.inc
 
-$(HD0IMG): $(IMGFILES)
-	if [ -f $(HD0IMG) ] ; then \
-		for f in $(IMGFILES) $(DISTFILES) ; do \
-			$(BINDIR)/cpmrm -f wbw_hd0 $(HD0IMG) 0:$$f ; \
-		done ; \
-		$(CPMCP) -f wbw_hd0 $(HD0IMG) $(IMGFILES) $(DISTFILES) 0: ; \
-	fi
-
-zcpr33n.rel zcpr33t.rel:
+zcpr33.rel:
 	(cd ZCPR33 ; make)
 
-all:: $(HD0IMG)
+all:: $(IMGFILES)
 
-clean::
-	@rm -f $(HD0IMG)
+# clean::
+# 	$(MAKE) --directory ZCPR3 clean
 
-%.img: zcpr33n.rel zcpr33t.rel
+%.img: zcpr33.rel
 	$(eval VER := $(subst .img,,$(subst bp,,$@)))
 	cp def-ww-z$(VER).lib def-ww.lib
 	rm -f bpbio-ww.rel
 	$(ZXCC) ZMAC -BPBIO-WW -/P
 	mv bpbio-ww.prn bp$(VER).prn
+	if [ -f bpbio-ww.err ] ; then mv bpbio-ww.err bp$(VER).err; fi
+	mv bpbio-ww.rel bp$(VER).rel
 	cp bp$(VER).dat bpsys.dat
 	$(ZXCC) ./bpbuild.com -bpsys.dat 0 < bpbld1.rsp
 	cp bpsys.img bpsys.dat

Source/BPBIOS/ZCPR33/Build.cmd

@@ -1,8 +1,8 @@
 @echo off
 setlocal
 
-set PATH=%PATH%;..\..\..\Tools\zxcc;..\..\..\Tools\cpmtools;
-
+set TOOLS=..\..\..\Tools
+set PATH=%PATH%;%TOOLS%\zxcc;%TOOLS%\cpmtools;
 set CPMDIR80=%TOOLS%/cpm/
 
 copy ..\z3base.lib . || exit /b

Source/BPBIOS/ZCPR33/Makefile

@@ -1,5 +1,5 @@
-OBJECTS = zcpr33n.rel zcpr33t.rel
-OTHERS = z3basen.lib z3baset.lib
+OBJECTS = zcpr33.rel
+OTHERS = z3base.lib *.prn *.rel
 TOOLS = ../../../Tools
 DEST = ..
 
@@ -7,12 +7,7 @@ include $(TOOLS)/Makefile.inc
 
 DIFFPATH = $(DIFFTO)/Source/BPBIOS
 
-zcpr33t.rel: ../z3baset.lib
-	cp ../z3baset.lib z3baset.lib
-	$(ZXCC) ZMAC -zcpr33t.z80 -/P
-	rm z3baset.lib
-
-zcpr33n.rel: ../z3basen.lib
-	cp ../z3basen.lib z3basen.lib
-	$(ZXCC) ZMAC -zcpr33n.z80 -/P
-	rm z3basen.lib
+zcpr33.rel: ../z3base.lib
+	cp ../z3base.lib z3base.lib
+	$(ZXCC) ZMAC -zcpr33.z80 -/P
+	rm z3base.lib

Source/BPBIOS/cboot-ww.z80

@@ -102,6 +102,9 @@ CBOOT:
 ; BPCNFG to configure a generic IMG file for specific Hard Drive Partitions.
 
 CBOOT0:
+	LD	BC,HBF_SYSRES_INT	; HB Func: Internal Reset
+	CALL	HBX_INVOKE		; Do it
+
 	LD	HL,BRAME	; Get end of banked RAM
 	LD	(HISAV),HL	;   and save for later use
 	  IF  HARDDSK

Source/BPBIOS/deblock.z80

@@ -268,16 +268,15 @@ MATCH:	LD	A,(SECMSK)	; Get the sector mask
 ;
 ; Modified to use HBIOS host buffer
 ;
-	; HSTBUF is always in HBIOS bank where I/O is done
-	LD	A,(TPABNK)	; TPA BANK
-	DEC	A		; HBIOS bank is one below
-	LD	C,A
+	; HSTBUF is always in HBIOS bank where I/O is actually done
+	LD	A,(HB_BNKBIOS)	; HBIOS bank id
+	LD	C,A		; Set Read Source Bank
 	  IF  BANKED
-	LD	A,(DMABNK)	; Set Read Destination Bank
+	LD	A,(DMABNK)	; Read Destination Bank
 	  ELSE
-	LD	A,(TPABNK)	; Set Read Destination Bank
+	LD	A,(TPABNK)	; Read Destination Bank
 	  ENDIF
-	LD	B,A
+	LD	B,A		; Set Read Destination Bank
 	LD	A,(READOP)	; Direction?
 	OR	A
 	JR	NZ,OKBNKS	; ..jump if read

Source/BPBIOS/def-ww-z33.lib

@@ -133,8 +133,8 @@ BNK1	EQU	BID_COM		;   Second TPA Bank (Common Bank)	48000H
 BNK2	EQU	BID_SYS		; System Bank (BIOS, DOS, CPR)		50000H
 BNKU	EQU	00H		; User Area Bank			58000H
 				; (set to 0 to disable)
-BNK3	EQU	BID_RAMD	; First Bank for RAM disk		60000H
-BNKM	EQU	BID_RAMM	; Maximum Bank #			F8000H
+BNK3	EQU	BID_BUF		; First Bank for RAM disk		60000H
+BNKM	EQU	BID_BUF		; Maximum Bank #			F8000H
 
 	  IF  NO	; REMOVE CODE - NOT NEEDED WITH HBIOS makes a
        			; nice resource for Z180 programing in general

Source/BPBIOS/def-ww-z33bnk.lib

@@ -133,8 +133,8 @@ BNK1	EQU	BID_COM		;   Second TPA Bank (Common Bank)	48000H
 BNK2	EQU	BID_SYS		; System Bank (BIOS, DOS, CPR)		50000H
 BNKU	EQU	00H		; User Area Bank			58000H
 				; (set to 0 to disable)
-BNK3	EQU	BID_RAMD	; First Bank for RAM disk		60000H
-BNKM	EQU	BID_RAMM	; Maximum Bank #			F8000H
+BNK3	EQU	BID_BUF		; First Bank for RAM disk		60000H
+BNKM	EQU	BID_BUF		; Maximum Bank #			F8000H
 
 	  IF  NO	; REMOVE CODE - NOT NEEDED WITH HBIOS makes a
        			; nice resource for Z180 programing in general

Source/BPBIOS/def-ww-z34.lib

@@ -133,8 +133,8 @@ BNK1	EQU	BID_COM		;   Second TPA Bank (Common Bank)	48000H
 BNK2	EQU	BID_SYS		; System Bank (BIOS, DOS, CPR)		50000H
 BNKU	EQU	00H		; User Area Bank			58000H
 				; (set to 0 to disable)
-BNK3	EQU	BID_RAMD	; First Bank for RAM disk		60000H
-BNKM	EQU	BID_RAMM	; Maximum Bank #			F8000H
+BNK3	EQU	BID_BUF		; First Bank for RAM disk		60000H
+BNKM	EQU	BID_BUF		; Maximum Bank #			F8000H
 
 	  IF  NO	; REMOVE CODE - NOT NEEDED WITH HBIOS makes a
        			; nice resource for Z180 programing in general

Source/BPBIOS/def-ww-z34bnk.lib

@@ -133,8 +133,8 @@ BNK1	EQU	BID_COM		;   Second TPA Bank (Common Bank)	48000H
 BNK2	EQU	BID_SYS		; System Bank (BIOS, DOS, CPR)		50000H
 BNKU	EQU	00H		; User Area Bank			58000H
 				; (set to 0 to disable)
-BNK3	EQU	BID_RAMD	; First Bank for RAM disk		60000H
-BNKM	EQU	BID_RAMM	; Maximum Bank #			F8000H
+BNK3	EQU	BID_BUF		; First Bank for RAM disk		60000H
+BNKM	EQU	BID_BUF		; Maximum Bank #			F8000H
 
 	  IF  NO	; REMOVE CODE - NOT NEEDED WITH HBIOS makes a
        			; nice resource for Z180 programing in general

Source/BPBIOS/def-ww-z41bnk.lib

@@ -133,8 +133,8 @@ BNK1	EQU	BID_COM		;   Second TPA Bank (Common Bank)	48000H
 BNK2	EQU	BID_SYS		; System Bank (BIOS, DOS, CPR)		50000H
 BNKU	EQU	00H		; User Area Bank			58000H
 				; (set to 0 to disable)
-BNK3	EQU	BID_RAMD	; First Bank for RAM disk		60000H
-BNKM	EQU	BID_RAMM	; Maximum Bank #			F8000H
+BNK3	EQU	BID_BUF		; First Bank for RAM disk		60000H
+BNKM	EQU	BID_BUF		; Maximum Bank #			F8000H
 
 	  IF  NO	; REMOVE CODE - NOT NEEDED WITH HBIOS makes a
        			; nice resource for Z180 programing in general

Source/BPBIOS/dpbhd-ww.lib

@@ -46,7 +46,7 @@
 ; NOTE: No Skew Table needed since Hard Disk Format is locked w/No Skew 
 
 ;.....
-; Currently, BPBIOS supports 2 memory drive devices and 3 phyical hard 
+; Currently, BPBIOS supports 2 memory drive devices and 3 physical hard 
 ;	drive like devices.  BPBIOS can support seven but unfortunately
 ;	BPCNFG only supports 3 hard drive like devices and the source 
 ;	code is not available, so menu 4 is meaningless.  Devices 
@@ -64,26 +64,22 @@
 ;
 ;	Starting with ver 2.8 of HBIOS, devices are discovered at boot
 ;	time and assigned device numbers.  Since devices are tested in
-;	a certain order, the device numbers are somewhat predicably 
+;	a certain order, the device numbers are somewhat predictably 
 ;	assigned.  Memory drives are discovered first.  IDE drives are 
 ;	discovered next so that IDE Hard drives including CF cards are 
 ;	assigned device 2 and device 3 if a slave drive is supported by
 ;	the interface.  Next comes the SD drive and is assigned device 3
 ;	or 4 depending on the whether there is an ide slave drive.
-;	USB drive is assigned device 4 or 5 .  For SIMH HDSK0 is device 0
+;	USB drive is assigned device 4 or 5.  For SIMH HDSK0 is device 0
 ;	and HDSK1 is device 1.  Memory drives are now handled as LBA
 ;	devices, ie like hard drives.
 ;
 ; The following non-memory drive capacities and configurations used for 
-; the SIMH, SD and IDE drives: Slice geometry is 256, 512 byte sectors, 
-; 1 head per track and 1 with one reserved track, a block size of 4096 
-; bytes with 512 directory entries.  An equivalent geometry is 16 
-; sectors and 16 heads per track.  Internally BPBIOS uses a uniform 
-; logical organization with 64 logical records per logical track.  
-; Thus there are 16 logical tracks per physical track with 1040 
-; logical (65 physical) tracks per slice.  If all partitions are not 
-; physically present, the missing partitions can be disabled in the 
-; BPBCNFG configuration file or by hand.  Note that HBIOS uses LBA, 
+; the SIMH, SD and IDE drives: Track geometry is 16 512 byte sectors.
+; A slice is exactly 64 tracks, with 1 of the 64 tracks as a system
+; track.  There are 1024 directory entries per slice. If all partitions
+; are not physically present, the missing partitions can be disabled in
+; the BPBCNFG configuration file or by hand.  Note that HBIOS uses LBA, 
 ; Logical Block Addressing, for non-floppy drives.
 ;
 ; For SBC V1,2, ZETA, MARK IV and N8, the following non-memory partitions 
@@ -94,26 +90,26 @@
 ;	partition	Size	Blocks	Block 	Offset in
 ;			MByte		Size	logical tracks
 ;====================================================================
-;	   C		 8	 2048	4096	1*16          = 16
-;	   D		 8	 2048	4096	(1+65)*16     = 1056
-;	   E		 8	 2048	4096	(1+2*65)*16   = 2096
-;	   F		 8	 2048	4096	(1+3*65)*16   = 3136
-;	   G		 8	 2048	4096	(1+4*65)*16   = 4176
-;	   H		 8	 2048	4096	(1+5*65)*16   = 5216
-;	   I		 8	 2048	4096	(1+6*65)*16   = 6256
-;	   J		 8	 2048	4096	(1+7*65)*16   = 7296
+;	   C		 8	 2044	4096	128+(1024*0)+2 = 130
+;	   D		 8	 2044	4096	128+(1024*1)+2 = 1154
+;	   E		 8	 2044	4096	128+(1024*2)+2 = 2178
+;	   F		 8	 2044	4096	128+(1024*3)+2 = 3202
+;	   G		 8	 2044	4096	128+(1024*4)+2 = 4226
+;	   H		 8	 2044	4096	128+(1024*5)+2 = 5250
+;	   I		 8	 2044	4096	128+(1024*6)+2 = 6274
+;	   J		 8	 2044	4096	128+(1024*7)+2 = 7298
 ;
 ; These are capacities and configurations used for SD card:
 ;
 ;	partition	Size	Blocks	Block 	Offset
 ;			MByte		Size	logical tracks
 ;====================================================================
-;	   K		 8	 2048	4096	1*16          = 16
-;	   L		 8	 2048	4096	(1+65)*16     = 1056
-;	   M		 8	 2048	4096	(1+2*65)*16   = 2096
-;	   N		 8	 2048	4096	(1+3*65)*16   = 3136
+;	   K		 8	 2044	4096	128+(1024*0)+2 = 130
+;	   L		 8	 2044	4096	128+(1024*1)+2 = 1154
+;	   M		 8	 2044	4096	128+(1024*2)+2 = 2178
+;	   N		 8	 2044	4096	128+(1024*3)+2 = 3202
 ;
-; RAM drive is paritition A while ROM drive is partition B. 
+; RAM drive is partition A while ROM drive is partition B. 
 ;
 ; For example, a typical Memory drive configuration is: 
 ;
@@ -199,17 +195,17 @@ DPBROM:	DEFW	64		; Sectors/Track
 				;  even though real layout is 256 physical
 				;  sectors per track
 	DEFB	0		; Physical tracks/side (No Meaning in HD)
-HSIZ0	EQU	2048		; # of blocks in first Partition  (1024 trks)
+HSIZ0	EQU	2048 - 4	; # of blocks in first Partition  (1022 trks)
 				;	
 DPB50:	DEFW	64		; Sctrs/Trk	
 	DEFB	5		; Blk Shf Fctr	
 	DEFB	31		; Block Mask	
 	DEFB	1		; Extent Mask	
-	DEFW	HSIZ0-1		; Disk Size-1	
-	DEFW	511		; Dir Max-1 - 4 blocks	
-	DEFB	0F0H,0		; Alloc 0,1 - 4 blocks	
+	DEFW	HSIZ0-1		; Disk Size-1
+	DEFW	1024-1		; Dir Max-1
+	DEFB	0FFH,0		; Alloc 0,1
 	DEFW	0		; Check Size	
-	DEFW	16		; Trk Offset	
+	DEFW	128+(1024*0)+2	; Trk Offset
 	  ENDIF
 ;
 ;.....
@@ -226,17 +222,17 @@ DPB50:	DEFW	64		; Sctrs/Trk
 				; sectors per track
 	DEFB	0		; Physical tracks/side (No Meaning in HD)
 
-HSIZ1	EQU	2048		; # of blocks in Second Partition  (1024 trks)
+HSIZ1	EQU	2048 - 4	; # of blocks in Second Partition  (1022 trks)
 				;		
 DPB51:	DEFW	64		; Scts/Trk	
 	DEFB	5		; Blk Shf Fctr
 	DEFB	31		; Block Mask	
 	DEFB	1		; Extent Mask	
 	DEFW	HSIZ1-1		; Disk Size-1	
-	DEFW	511		; Dir Max-1	4 blocks
-	DEFB	0F0H,0		; Alloc 0,1	
+	DEFW	1024-1		; Dir Max-1
+	DEFB	0FFH,0		; Alloc 0,1
 	DEFW	0		; Check size	
-	DEFW	(1+65)*16	; Track offset	1056
+	DEFW	128+(1024*1)+2	; Trk Offset
 	  ENDIF
 ;
 ;.....
@@ -253,21 +249,21 @@ DPB51:	DEFW	64		; Scts/Trk
 				; sectors per track
 	DEFB	0		; Physical tracks/side (No Meaning in HD)
 
-HSIZ2	EQU	2048		; # of blocks in third Partition (1024 tracks)
+HSIZ2	EQU	2048 - 4	; # of blocks in Second Partition  (1022 trks)
 				;	
 DPB52:	DEFW	64		; Scts/Trk	
 	DEFB	5		; Blk Shf Fctr	
 	DEFB	31		; Block Mask	
 	DEFB	1		; Extent Mask	
 	DEFW	HSIZ2-1		; Disk Size-1	
-	DEFW	511		; Dir Max-1	4 blocks
-	DEFB	0F0H,0		; Alloc 0,1	
+	DEFW	1024-1		; Dir Max-1
+	DEFB	0FFH,0		; Alloc 0,1
 	DEFW	0		; Check size	
-	DEFW	(1+2*65)*16	; Track offset = 2096
+	DEFW	128+(1024*2)+2	; Trk Offset
 	  ENDIF
 ;
 ;.....
-; Partition F.  HBIOS Disk 0, Slice 4
+; Partition F.  HBIOS Disk 0, Slice 3
 
 	  IF  DRV_F
 	DEFB	'HBDSK0:3 ','F'+80H ; Id - 10 bytes
@@ -280,17 +276,17 @@ DPB52:	DEFW	64		; Scts/Trk
 				; sectors per track
 	DEFB	0		; Physical tracks/side (No Meaning in HD)
 
-HSIZ3	EQU	2048		; # of blocks in Fourth Partition (1024 tracks)
+HSIZ3	EQU	2048 - 4	; # of blocks in Second Partition  (1022 trks)
 				;	
 DPB53:	DEFW	64		; Scts/Trk	
 	DEFB	5		; Blk Shf Fctr	
 	DEFB	31		; Block Mask	
 	DEFB	1		; Extent Mask	
 	DEFW	HSIZ3-1		; Disk Size-1	
-	DEFW	511		; Dir Max-1	4 blocks
-	DEFB	0F0H,0		; Alloc 0,1	
+	DEFW	1024-1		; Dir Max-1
+	DEFB	0FFH,0		; Alloc 0,1
 	DEFW	0		; Check size	
-	DEFW	(1+3*65)*16	; Track offset = 3136
+	DEFW	128+(1024*3)+2	; Trk Offset
 	  ENDIF
 ;	
 ;.....
@@ -307,17 +303,17 @@ DPB53:	DEFW	64		; Scts/Trk
 				; sectors per track
 	DEFB	0		; Physical tracks/side (No Meaning in HD)
 
-HSIZ4	EQU	2048		; # of blocks in first Partition  (1024 trks)
+HSIZ4	EQU	2048 - 4	; # of blocks in Second Partition  (1022 trks)
 				;	
 DPB54:	DEFW	64		; Sctrs/Trk	
 	DEFB	5		; Blk Shf Fctr
 	DEFB	31		; Block Mask
 	DEFB	1		; Extent Mask
 	DEFW	HSIZ4-1		; Disk Size - 1
-	DEFW	511		; Dir Max-1	4 blocks
-	DEFB	0F0H,0		; Alloc 0,1	
+	DEFW	1024-1		; Dir Max-1
+	DEFB	0FFH,0		; Alloc 0,1
 	DEFW	0		; Check size	
-	DEFW	(1+4*65)*16	; Track offset = 16
+	DEFW	128+(1024*4)+2	; Trk Offset
 	  ENDIF
 ;
 ;.....
@@ -334,17 +330,17 @@ DPB54:	DEFW	64		; Sctrs/Trk
 				;   sectors per track
 	DEFB	0		; Physical tracks/side (No Meaning in HD)
 
-HSIZ5	EQU	2048		; # of blocks in Second Partition  (1024 trks)
+HSIZ5	EQU	2048 - 4	; # of blocks in Second Partition  (1022 trks)
 				;		
 DPB55:	DEFW	64		; Sctrs/Trk - actually 256	
 	DEFB	5		; Blk Shf Fctr	
 	DEFB	31		; Block Mask	
 	DEFB	1		; Extent Mask	
 	DEFW	HSIZ5-1		; Disk Size-1	
-	DEFW	511		; Dir Max-1	
-	DEFB	0F0H,0		; Alloc 0,1 - 4 blocks	
+	DEFW	1024-1		; Dir Max-1
+	DEFB	0FFH,0		; Alloc 0,1
 	DEFW	0		; Check Size	
-	DEFW	(1+5*65)*16	; Trk Offset = 1056
+	DEFW	128+(1024*5)+2	; Trk Offset
 	  ENDIF
 ;
 ;.....
@@ -361,17 +357,17 @@ DPB55:	DEFW	64		; Sctrs/Trk - actually 256
 				; sectors per track
 	DEFB	0		; Physical tracks/side (No Meaning in HD)
 
-HSIZ6	EQU	2048		; # of blocks in third Partition (1024 tracks)
+HSIZ6	EQU	2048 - 4	; # of blocks in Second Partition  (1022 trks)
 				;	
 DPB56:	DEFW	64		; Scts/Trk	
 	DEFB	5		; Blk Shf Fctr	
 	DEFB	31		; Block Mask	
 	DEFB	1		; Extent Mask	
 	DEFW	HSIZ6-1		; Disk Size-1	
-	DEFW	511		; Dir Max-1	4 blocks
-	DEFB	0F0H,0		; Alloc 0,1	
+	DEFW	1024-1		; Dir Max-1
+	DEFB	0FFH,0		; Alloc 0,1
 	DEFW	0		; Check size	
-	DEFW	(1+6*65)*16	; Track offset	= 2096
+	DEFW	128+(1024*6)+2	; Trk Offset
 	  ENDIF
 
 ;.....
@@ -388,17 +384,17 @@ DPB56:	DEFW	64		; Scts/Trk
 				; sectors per track
 	DEFB	0		; Physical tracks/side (No Meaning in HD)
 
-HSIZ7	EQU	2048		; # of blocks in Fourth Partition (1024 tracks)
+HSIZ7	EQU	2048 - 4	; # of blocks in Second Partition  (1022 trks)
 				;
 DPB57:	DEFW	64		; Scts/Trk	
 	DEFB	5		; Blk Shf Fctr	
 	DEFB	31		; Block Mask	
 	DEFB	1		; Extent Mask	
 	DEFW	HSIZ7-1		; Disk Size-1	
-	DEFW	511		; Dir Max-1	4 blocks
-	DEFB	0F0H,0		; Alloc 0,1	
+	DEFW	1024-1		; Dir Max-1
+	DEFB	0FFH,0		; Alloc 0,1
 	DEFW	0		; Check size	
-	DEFW	(1+7*65)*16	; Track offset = 3136
+	DEFW	128+(1024*7)+2	; Trk Offset
 	  ENDIF
 ;
 ;.....
@@ -414,17 +410,18 @@ DPB57:	DEFW	64		; Scts/Trk
 				;  even though real layout is 256 physical
 				;  sectors per track
 	DEFB	0		; Physical tracks/side (No Meaning in HD)
-HSIZ8	EQU	2048		; # of blocks in first Partition  (1024 trks)
+
+HSIZ8	EQU	2048 - 4	; # of blocks in Second Partition  (1022 trks)
 				;	
 DPB58:	DEFW	64		; Sctrs/Trk	
 	DEFB	5		; Blk Shf Fctr	
 	DEFB	31		; Block Mask	
 	DEFB	1		; Extent Mask	
 	DEFW	HSIZ8-1		; Disk Size-1	
-	DEFW	511		; Dir Max-1 - 4 blocks	
-	DEFB	0F0H,0		; Alloc 0,1 - 4 blocks	
+	DEFW	1024-1		; Dir Max-1
+	DEFB	0FFH,0		; Alloc 0,1
 	DEFW	0		; Check Size	
-	DEFW	16		; Trk Offset	
+	DEFW	128+(1024*0)+2	; Trk Offset
 	  ENDIF
 ;
 ;.....
@@ -441,17 +438,17 @@ DPB58:	DEFW	64		; Sctrs/Trk
 				; sectors per track
 	DEFB	0		; Physical tracks/side (No Meaning in HD)
 
-HSIZ9	EQU	2048		; # of blocks in Second Partition  (1024 trks)
+HSIZ9	EQU	2048 - 4	; # of blocks in Second Partition  (1022 trks)
 				;		
 DPB59:	DEFW	64		; Scts/Trk	
 	DEFB	5		; Blk Shf Fctr
 	DEFB	31		; Block Mask	
 	DEFB	1		; Extent Mask	
 	DEFW	HSIZ9-1		; Disk Size-1	
-	DEFW	511		; Dir Max-1	4 blocks
-	DEFB	0F0H,0		; Alloc 0,1	
+	DEFW	1024-1		; Dir Max-1
+	DEFB	0FFH,0		; Alloc 0,1
 	DEFW	0		; Check size	
-	DEFW	(1+65)*16	; Track offset	1056
+	DEFW	128+(1024*1)+2	; Trk Offset
 	  ENDIF
 ;
 ;.....
@@ -468,17 +465,17 @@ DPB59:	DEFW	64		; Scts/Trk
 				; sectors per track
 	DEFB	0		; Physical tracks/side (No Meaning in HD)
 
-HSIZ10	EQU	2048		; # of blocks in Second Partition  (1024 trks)
+HSIZ10	EQU	2048 - 4	; # of blocks in Second Partition  (1022 trks)
 				;		
 DPB60:	DEFW	64		; Scts/Trk
 	DEFB	5		; Blk Shf Fctr
 	DEFB	31		; Block Mask	
 	DEFB	1		; Extent Mask	
-	DEFW	HSIZ10		; Disk Size-1	
-	DEFW	511		; Dir Max-1	4 blocks
-	DEFB	0F0H,0		; Alloc 0,1	
+	DEFW	HSIZ10-1		; Disk Size-1	
+	DEFW	1024-1		; Dir Max-1
+	DEFB	0FFH,0		; Alloc 0,1
 	DEFW	0		; Check size	
-	DEFW	(1+2*65)*16	; Track offset	2096
+	DEFW	128+(1024*2)+2	; Trk Offset
 	  ENDIF
 ;
 ;.....
@@ -492,18 +489,17 @@ DPB60:	DEFW	64		; Scts/Trk
 	DEFB	16		; Logical Sectors per track
 	DEFB	0		; Physical tracks/side (No Meaning in HD)
 
-HSIZ11	EQU	2048		; # of blocks in Forth Logical Drive 
-				;   (1024 tracks)
+HSIZ11	EQU	2048 - 4	; # of blocks in Second Partition  (1022 trks)
 
 DPB61:	DEFW	64		; Scts/Trk
 	DEFB	5		; Blk Shf Fctr
 	DEFB	31		; Block Mask
 	DEFB	1		; Extent Mask
 	DEFW	HSIZ11-1 	; Disk Size-1
-	DEFW	511		; Dir Max-1
-	DEFB	0F0H,0		; Alloc 0,1
+	DEFW	1024-1		; Dir Max-1
+	DEFB	0FFH,0		; Alloc 0,1
 	DEFW	0		; Check size
-	DEFW	(1+3*65)*16	; Track offset	3136
+	DEFW	128+(1024*3)+2	; Trk Offset
 	  ENDIF
 		
 ;=========== End of Hard Disk DPBs ===========

Source/BPBIOS/hard-ww.z80

@@ -183,7 +183,6 @@ HDSK_RW1:
 	POP	BC              ; RESTORE INCOMING FUNCTION, DEVICE/UNIT
 	RET	NZ              ; ABORT IF SEEK RETURNED AN ERROR W/ ERROR IN A
 	LD	HL,(HB_DSKBUF)  ; GET BUFFER ADDRESS
-	;LD	D,BID_HB	; BUFFER IN HBIOS BANK
 	LD	A,(HB_BNKBIOS)	; BUFFER IN HBIOS BANK
 	LD	D,A		; PUT IN D
 	LD	E,1		; ONE SECTOR

Source/BPBIOS/hbios.z80

@@ -9,6 +9,7 @@
 HBF_ALLOC	EQU	0F6H		; HBIOS Func: ALLOCATE Heap Memory
 HBF_PEEK	EQU	0FAH		; HBIOS Func: Peek Byte
 HBF_POKE	EQU	0FBH		; HBIOS Func: Poke Byte
+HBF_SYSRES_INT	EQU	0F000H		; HBIOS Func: Internal Reset
 HBF_MEMINFO	EQU	0F8F1H		; HBIOS Func: Get Memory Info
 HBF_BNKINFO	EQU	0F8F2H		; HBIOS Func: Get Bank Info
 ;
@@ -43,22 +44,23 @@ HBX_CPYLEN	EQU	0FFE8H
 ; call here, make required changes, then update the
 ; BIOSJT to point directly to the normal SELMEM routine for
 ; all subsequent calls.
+;
+; When called, the incoming bank id will be the original hard-coded
+; bank id prior to any adjustments.  These original bank id's are
+; coded to be an offset from the ending HBIOS RAM bank id which
+; is (80h + RAM banks).  See romwbw.lib.  We update the requested
+; bank id for this initial call to make it the proper absolute
+; HBIOS bank id.
+;
+; See romwbw.lib for additional RAM bank layout information.
 
-	; BPBIOS	HBIOS		Typical
-	; ------------	--------------	--------------
-	;  -1: <COMMON>	BID_COM		90h - 1 = 8Fh
-	;  -2: TPABNK	BID_USR         90h - 2 = 8Eh
-	;  -3: <HBIOS>	BID_BIOS	90h - 3 = 8Dh	
-	;  -4: SYSBNK	BID_AUX		90h - 4 = 8Ch
-	;  -9: BNKM	BID_AUX-5	90h - 9 = 87h
-	; -16: RAMBNK	RAMD0		90h - 16 = 80h
-	
 HB_SELMEM:
-	PUSH	AF
 	PUSH	BC
 	PUSH	DE
 	PUSH	HL
 	
+	PUSH	AF		; Save incoming bank request
+	
 	  IF HB_DEBUG AND FALSE
 	CALL	PRTSTRD
 	DEFB	'[HB_SELMEM: $'
@@ -68,23 +70,30 @@ HB_SELMEM:
 	  ENDIF
 	
 	LD	BC,HBF_BNKINFO	; HBIOS BNKINFO function
-	CALL	HBX_INVOKE	; DO IT, D=BID_BIOS, E=BID_USER
-	LD	A,D		; BID_BIOS
-	LD	(HB_BNKBIOS),A	; SET HB_BNKBIOS
-	ADD	A,3		; HBIOS + 3
-	LD	(HB_BNKEND),A	; ... is the ending RAM bank
-	  IF BANKED
-	LD	(BNKADJ+1),A	; Dynamically update SELBNK
-	  ENDIF
-	  
+	CALL	HBX_INVOKE	; Do it, D=BIOS bank, E=USER (TPA) bank
+	LD	A,D		; BIOS bank
+	LD	(HB_BNKBIOS),A	; Save it for later (deblock & hard-ww)
+	LD	A,E		; USER (TPA) bank
+	LD	(TPABNK),A	; Update BP register
+	DEC	A		; SYS bank is one below USER
+	LD	(SYSBNK),A	; Update BP register
+	DEC	A		; HBIOS BUF bank is one more below
+	;LD	(UABNK),A	; Set BPBIOS USER bank
+	LD	(RAMBNK),A	; Update BP RAM disk bank register
+	LD	(MAXBNK),A	; Update ending bank register
+	
 	LD	HL,SELMEM	; Future SELMEM calls will
 	LD	(BIOSJT+(27*3)+1),HL	; ... go to real SELMEM
 	
+	POP	BC		; Recover requested bank to B
+	LD	A,(TPABNK)	; Get TPA bank
+	ADD	2		; Offset to ending RAM bank id
+	ADD	B		; Adjust for incoming request
+	
 	POP	HL
 	POP	DE
 	POP	BC
-	POP	AF
-	JP	SELMEM
+	JP	SELMEM		; Continue to normal SELMEM
 	
 ;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
 ; Move Data - Possibly between banks.  This resembles CP/M 3, but
@@ -97,15 +106,10 @@ HB_SELMEM:
 ;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
 
 HB_MOVE:
-	PUSH	HL
-	LD	HL,HB_BNKEND
 	LD	A,(HB_SRCBNK)
-	ADD	A,(HL)		; Adjust for HBIOS bank ids
 	LD	(HBX_SRCBNK),A
 	LD	A,(HB_DSTBNK)
-	ADD	A,(HL)		; Adjust for HBIOS bank ids
 	LD	(HBX_DSTBNK),A
-	POP	HL
 	CALL	HBX_BNKCPY
 	PUSH	HL
 	LD	HL,(TPABNK)	; Get TPA Bank #
@@ -141,6 +145,5 @@ HB_XMOVE:
 HB_SRCBNK:	DEFS	1	; Move Source Bank #
 HB_DSTBNK:	DEFS	1	; Move Destination Bank #
 HB_BNKBIOS:	DEFS	1	; Bank id of HBIOS bank
-HB_BNKEND:	DEFS	1	; End of available RAM banks (last bank + 1)
 HB_DSKBUF:	DEFS	2	; Address of physical disk buffer in HBIOS bank
 

Source/BPBIOS/ibmv-ww.z80

@@ -115,10 +115,22 @@ SELMEM:	LD	(USRBNK),A	; Update user bank
 ;  Must preserve all Registers including Flags.
 ;  All Bank Switching MUST be done by this routine
 ;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
+;
+; Parameter to BNKADJ (ADD) is set dynamically at initialization.
 
 SELBNK:	PUSH	AF		; Save regs
 SELBN0:	LD	(CURBNK),A	; Save as current bank #
-BNKADJ:	ADD	A,90H		; Adjust for HBIOS bank ids
+
+	  IF HB_DEBUG AND FALSE
+
+	CALL	PRTSTRD
+	DEFB	'[SELBNK: $'
+	CALL	PRTHEXBYTE
+	CALL	PRTSTRD
+	DEFB	']$'
+
+	  ENDIF
+
 	CALL	HBX_BNKSEL
 	POP	AF		; restore regs
 	RET
@@ -172,7 +184,7 @@ FRGETB:
 	PUSH	BC		; Save BC
 	PUSH	DE		; Save DE
 	LD	B,0FAH		; HBIOS Peek function
-	LD	D,C		; Bank in D
+	LD	D,C
 	CALL	HBX_INVOKE	; Do it
 	LD	A,E		; Value to A
 	POP	DE		; Restore DE
@@ -203,8 +215,8 @@ FRPUTB:
 	PUSH	BC		; Save BC
 	PUSH	DE		; Save DE
 	LD	B,0FBH		; HBIOS Poke function
-	LD	D,C		; Bank in D
 	LD	E,A		; Value in E
+	LD	D,C
 	CALL	HBX_INVOKE	; Do it
 	POP	DE		; Restore DE
 	POP	BC		; Restore BC

Source/BPBIOS/romwbw.lib

@@ -48,20 +48,33 @@ DRV_P		SET	NO		; YES if system has flopy drives
 ;
 ; RAM/ROM Bank Reserve
 ;
-HB_RAMRESV	EQU	8		; RAM reserve is 8 banks
+HB_RAMRESV	EQU	5		; RAM reserve is 5 banks
 HB_ROMRESV	EQU	4		; ROM reserve is 4 banks
 ;
 ; Layout of RAM banks
 ;
-; TODO: Query system via HBIOS API to determine the actual bank
-; assignments, then adjust BPBIOS operation accordingly.
+; The BID_xxx values below are used to set the initial values of
+; the BPBIOS bank registers (see def-ww-xxx.lib and HB_SELMEM in
+; hbios.z80).  The running values of the BPBIOS bank registers (TPABNK,
+; SYSBNK, etc.) are set to absolute HBIOS bank ids in hbios.z80 during
+; startup.
 ;
-BID_RAMD	EQU	-16	; 90h - 16 = 80h
-BID_RAMM	EQU	-9	; 90h - 9 = 87h
-BID_SYS		EQU	-4	; 90h - 4 = 8Ch
-BID_HB		EQU	-3	; 90h - 3 = 8Dh
-BID_USR		EQU	-2	; 90h - 2 = 8Eh
-BID_COM		EQU	-1	; 90h - 1 = 8Fh
+; The values below are expressed as an offset from the ending HBIOS
+; RAM bank id.  They map to HBIOS bank ids
+; by subtracting from the ending HBIOS bank id (N).  HBIOS RAM bank ids
+; start at 80h.  The ending HBIOS bank id is (80h + RAM banks).  The
+; typical layout assumes 16 banks of RAM starting at HBIOS bank id 80h
+; and ending at bank id 90h (N = 90h).
+;
+; BPBIOS					HBIOS (TYPICAL)
+; --------------------------------------	---------------
+; <HBIOS>					80h   (80h)
+; <RAMD>					81h   (81h)
+; <RAMM>					N - 5 (8Bh)
+BID_BUF	EQU	-4	; BNK3 -> RAMBNK	N - 4 (8Ch)
+BID_SYS	EQU	-3	; BNK2 -> SYSBNK	N - 3 (8Dh)		
+BID_USR	EQU	-2	; BNK0 -> TPABNK	N - 2 (8Eh)		
+BID_COM	EQU	-1	; BNK1 ->		N - 1 (8Fh)		
 ;
 HB_EI	MACRO
 	EI

Source/Build.cmd

@@ -4,12 +4,13 @@ setlocal
 :: call BuildDoc || exit /b
 call BuildProp || exit /b
 call BuildShared || exit /b
-:: call BuildBP || exit /b
+call BuildBP || exit /b
 call BuildImages || exit /b
 call BuildROM %* || exit /b
 call BuildZRC || exit /b
 call BuildZ1RCC || exit /b
 call BuildZZRCC || exit /b
+call BuildZRC512 || exit /b
 
 if "%1" == "dist" (
   call Clean || exit /b

Source/BuildZRC512.cmd

@@ -0,0 +1,4 @@
+@echo off
+setlocal
+
+pushd ZRC512 && call Build || exit /b & popd

Source/Doc/Book.h

@@ -30,7 +30,9 @@ header-includes:
       {\scshape \bfseries \fontsize{48pt}{56pt} \selectfont $doc_product$ \par}
       {\bfseries \fontsize{32pt}{36pt} \selectfont $doc_title$ \par}
       \vspace{24pt}
-      {\huge $doc_ver$ \\ $doc_date$ \par}
+      {\huge $doc_ver$ \par}
+      \vspace{12pt}
+      {\large Updated $doc_date$ \par}
       \vspace{24pt}
       {\large \itshape $doc_orgname$ \\ \href{http://$doc_orgurl$}{$doc_orgurl$} \par}
       \vspace{12pt}

Source/Doc/ReadMe.md

@@ -10,14 +10,23 @@ A wide variety of platforms are supported including those
 produced by these developer communities:
 
 * [RetroBrew Computers](https://www.retrobrewcomputers.org)
-* [RC2014](https://rc2014.co.uk), [RC2014-Z80](https://groups.google.com/g/rc2014-z80)
-* [retro-comp](https://groups.google.com/forum/#!forum/retro-comp)
+  (<https://www.retrobrewcomputers.org>)
+* [RC2014](https://rc2014.co.uk) (<https://rc2014.co.uk>), \
+  [RC2014-Z80](https://groups.google.com/g/rc2014-z80)
+  (<https://groups.google.com/g/rc2014-z80>)
+* [Retro Computing](https://groups.google.com/g/retro-comp)
+  (<https://groups.google.com/g/retro-comp>)
 * [Small Computer Central](https://smallcomputercentral.com/)
+  (<https://smallcomputercentral.com/>)
+
+A complete list of the currently supported platforms is found in the
+[Installation] section.
 
 General features include:
 
+* Z80 Family CPUs including Z80, Z180, and Z280
 * Banked memory services for several banking designs
-* Disk drivers for RAM, ROM, Floppy, IDE, CF, and SD
+* Disk drivers for RAM, ROM, Floppy, IDE ATA/ATAPI, CF, SD, USB, Zip, Iomega
 * Serial drivers including UART (16550-like), ASCI, ACIA, SIO
 * Video drivers including TMS9918, SY6545, MOS8563, HD6445
 * Keyboard (PS/2) drivers via VT8242 or PPI interfaces
@@ -34,12 +43,12 @@ ROM firmware itself:
 * ROM BASIC (Nascom BASIC and Tasty BASIC)
 * ROM Forth
 
-A dynamic disk drive letter assignment mechanism allows mapping
-operating system drive letters to any available disk media.
-Additionally, mass storage devices (IDE Disk, CF Card, SD Card) support
-the use of multiple slices (up to 256 per device). Each slice contains
-a complete CP/M filesystem and can be mapped independently to any
-drive letter. This overcomes the inherent size limitations in legacy
+A dynamic disk drive letter assignment mechanism allows mapping 
+operating system drive letters to any available disk media. 
+Additionally, mass storage devices (IDE Disk, CF Card, SD Card, etc.) 
+support the use of multiple slices (up to 256 per device). Each slice 
+contains a complete CP/M filesystem and can be mapped independently to 
+any drive letter. This overcomes the inherent size limitations in legacy
 OSes and allows up to 2GB of accessible storage on a single device.
 
 The pre-built ROM firmware images are generally suitable for most
@@ -61,7 +70,7 @@ By design, RomWBW isolates all of the hardware specific functions in
 the ROM chip itself.  The ROM provides a hardware abstraction layer
 such that all of the operating systems and applications on a disk
 will run on any RomWBW-based system.  To put it simply, you can take
-a disk (or CF/SD Card) and move it between systems transparently.
+a disk (or CF/SD/USB Card) and move it between systems transparently.
 
 A tool is provided that allows you to access a FAT-12/16/32 filesystem. 
 The FAT filesystem may be coresident on the same disk media as RomWBW 
@@ -70,18 +79,19 @@ OSes such as Windows, MacOS, and Linux very easy.
 
 # Acquiring RomWBW
 
-The [RomWBW Repository](https://github.com/wwarthen/RomWBW) on GitHub is
-the official distribution location for all project source and
-documentation.  The fully-built distribution releases are available on
-the [RomWBW Releases Page](https://github.com/wwarthen/RomWBW/releases)
-of the repository.  On this page, you will normally see a Development
-Snapshot as well as recent stable releases. Unless you have a specific
-reason, I suggest you stick to the most recent stable release. Expand
-the "Assets" drop-down for the release you want to download, then select
-the asset named RomWBW-vX.X.X-Package.zip. The Package asset includes
-all pre-built ROM and Disk images as well as full source code. The other
-assets contain only source code and do not have the pre-built ROM or
-disk images.
+The [RomWBW Repository](https://github.com/wwarthen/RomWBW)
+(<https://github.com/wwarthen/RomWBW>) on GitHub is the official 
+distribution location for all project source and documentation.  The 
+fully-built distribution releases are available on the
+[RomWBW Releases Page](https://github.com/wwarthen/RomWBW/releases)
+(<https://github.com/wwarthen/RomWBW/releases>) of the repository.  On 
+this page, you will normally see a Development Snapshot as well as 
+recent stable releases. Unless you have a specific reason, I suggest you
+ stick to the most recent stable release. Expand the "Assets" drop-down 
+for the release you want to download, then select the asset named 
+RomWBW-vX.X.X-Package.zip. The Package asset includes all pre-built ROM 
+and Disk images as well as full source code. The other assets contain 
+only source code and do not have the pre-built ROM or disk images.
 
 All source code and distributions are maintained on GitHub. Code
 contributions are very welcome.
@@ -177,6 +187,33 @@ please let me know if I missed you!
   BASIC Compiler, Microsoft Fortran Compiler, and a Games
   compendium.
 
+* Martin R has provided substantial help reviewing and improving the
+  User Guide.
+
+* Jacques Pelletier has contributed the DS1501 RTC driver code.
+
+* Jose Collado has contributed enhancements to the TMS driver
+  including compatibility with standard TMS register configuration.
+
+* Kevin Boone has contributed a generic HBIOS date/time utility (WDATE).
+
+* Matt Carroll has contributed a fix to XM.COM that corrects the
+  port specification when doing a send.
+
+* Dean Jenkins enhanced the build process to accommodate the
+  Raspberry Pi 4.
+
+* Tom Plano has contributed a new utility (HTALK) to allow talking
+  directly to HBIOS COM ports.
+
+* Lars Nelson has contributed several generic utilities such as
+  a universal (OS agnostic) UNARC application.
+
+* Dylan Hall added support for specifying a secondary console.
+
+* Bill Shen has contributed boot loaders for several of his
+  systems.
+
 Contributions of all kinds to RomWBW are very welcome.
 
 # Licensing

Source/Doc/SystemGuide.md

@@ -1460,14 +1460,17 @@ standard HBIOS result code.
 |----------------------------------------|----------------------------------------|
 | B: 0x47                                | A: Status                              |
 | C: Video Unit                          |                                        |
+| D: Scope                               |                                        |
 | E: Color                               |                                        |
 
-Assign the specified Color (E) code to be used for all subsequent 
-character writes/fills. This color is also used to fill new lines 
-generated by scroll operations. Refer to the color code table above for 
-a list of the available color codes. Note that a given video display may
-or may not support any/all colors.  The Status (A) is a standard HBIOS 
-result code.
+Assign the specified Color (E) code for character foreground/background.
+If Scope (D) is 0, the specified color will  be used for all 
+subsequent character writes/fills. This color is also used to fill new 
+lines generated by scroll operations.  If Scope (D) is 1, then the 
+specified foreground/background color will be applied immediately to the
+ entire screen.  Refer to the color code table above for a list of the 
+available color codes. Note that a given video display may or may not 
+support any/all colors.  The Status (A) is a standard HBIOS result code.
 
 ### Function 0x48 -- Video Write Character (VDAWRC)
 

Source/Doc/UserGuide.md

@@ -43,6 +43,33 @@ find this document far too basic.  Others will find it lacking in many
 areas.  I am doing my best and encourage you to provide constructive
 feedback.
 
+`\clearpage`{=latex}
+
+#### Conventions
+
+##### Size Suffixes
+
+Within this document and in RomWBW in general, the use of size
+suffixes KB, MB, GB, and TB refer to the binary variant as shown
+below.  The modern suffixes (KiB, MiB, etc.) are not used here because
+they were not prevalent during the time that the RomWBW OSes were
+used.  This keeps all of RomWBW and associated applications consistent.
+
+| Suffix     | Value     | Meaning                                |
+|------------|-----------|----------------------------------------|
+| KB         | 1024      | 1,024 bytes                            |
+| MB         | 1024^2^   | 1,048,576 bytes                        |
+| GB         | 1024^3^   | 1,073,741,824 bytes                    |
+| TB         | 1024^4^   | 1,099,511,627,776 bytes                |
+
+##### Links and URLs
+
+Many of the references in this document to Internet addresses (URLs)
+do not provide the address in the text.  However, these links are
+embedded and "clickable" within the documents.  Your PDF viewer should
+highlight these links in some manner (typically an alternate color
+or an underline).
+
 # Overview
 
 RomWBW software provides a complete, commercial quality 
@@ -52,9 +79,14 @@ A wide variety of platforms are supported including those
 produced by these developer communities:
 
 * [RetroBrew Computers](https://www.retrobrewcomputers.org)
-* [RC2014](https://rc2014.co.uk), [RC2014-Z80](https://groups.google.com/g/rc2014-z80)
-* [retro-comp](https://groups.google.com/forum/#!forum/retro-comp)
+  (<https://www.retrobrewcomputers.org>)
+* [RC2014](https://rc2014.co.uk) (<https://rc2014.co.uk>), \
+  [RC2014-Z80](https://groups.google.com/g/rc2014-z80)
+  (<https://groups.google.com/g/rc2014-z80>)
+* [Retro Computing](https://groups.google.com/g/retro-comp)
+  (<https://groups.google.com/g/retro-comp>)
 * [Small Computer Central](https://smallcomputercentral.com/)
+  (<https://smallcomputercentral.com/>)
 
 A complete list of the currently supported platforms is found in the
 [Installation] section.
@@ -118,18 +150,19 @@ OSes such as Windows, MacOS, and Linux very easy.
 
 ## Acquiring RomWBW
 
-The [RomWBW Repository](https://github.com/wwarthen/RomWBW) on GitHub is
-the official distribution location for all project source and
-documentation.  The fully-built distribution releases are available on
-the [RomWBW Releases Page](https://github.com/wwarthen/RomWBW/releases)
-of the repository.  On this page, you will normally see a Development
-Snapshot as well as recent stable releases. Unless you have a specific
-reason, I suggest you stick to the most recent stable release. Expand
-the "Assets" drop-down for the release you want to download, then select
-the asset named RomWBW-vX.X.X-Package.zip. The Package asset includes
-all pre-built ROM and Disk images as well as full source code. The other
-assets contain only source code and do not have the pre-built ROM or
-disk images.
+The [RomWBW Repository](https://github.com/wwarthen/RomWBW)
+(<https://github.com/wwarthen/RomWBW>) on GitHub is the official 
+distribution location for all project source and documentation.  The 
+fully-built distribution releases are available on the
+[RomWBW Releases Page](https://github.com/wwarthen/RomWBW/releases)
+(<https://github.com/wwarthen/RomWBW/releases>) of the repository.  On 
+this page, you will normally see a Development Snapshot as well as 
+recent stable releases. Unless you have a specific reason, I suggest you
+ stick to the most recent stable release. Expand the "Assets" drop-down 
+for the release you want to download, then select the asset named 
+RomWBW-vX.X.X-Package.zip. The Package asset includes all pre-built ROM 
+and Disk images as well as full source code. The other assets contain 
+only source code and do not have the pre-built ROM or disk images.
 
 All source code and distributions are maintained on GitHub. Code
 contributions are very welcome.
@@ -220,6 +253,7 @@ is discussed in [Customizing RomWBW].
 | [Rhyophyre Z180 SBC]^1^                                        | -       | RPH_std.rom           | 38400         |
 | [Z80 ZRC CPU Module]^7^                                        | RCBus   | RCZ80_zrc.rom         | 115200        |
 | [Z80 ZRC CPU Module]^7^ ROMless                                | RCBus   | RCZ80_zrc_ram.rom     | 115200        |
+| [Z80 ZRC512 CPU Module]^7^                                     | RCBus   | RCZ80_zrc512.rom      | 115200        |
 | [Z180 Z1RCC CPU Module]^7^                                     | RCBus   | RCZ180_z1rcc.rom      | 115200        |
 | [Z280 ZZRCC CPU Module]^7^                                     | RCBus   | RCZ280_zzrcc.rom      | 115200        |
 | [Z280 ZZRCC CPU Module]^7^ ROMless                             | RCBus   | RCZ280_zzrcc_ram.rom  | 115200        |
@@ -277,7 +311,8 @@ your hardware provider's documentation for details. A null-modem
 connection may be required. Set the baud rate as indicated in the table 
 above. Set the line characteristics to 8 data bits, 1 stop bit, no 
 parity, and no flow control. If possible, select ANSI or VT-100 terminal
-emulation.
+emulation.  Hardware flow control is not required for terminal
+operation, but may be necessary for [Serial Port Transfers].
 
 RomWBW will automatically attempt to detect and support typical add-on
 components for each of the systems supported. More information on the
@@ -798,7 +833,8 @@ Sound 0     SND0:       AY-3-8910         3+1 CHANNELS
 
 The 'R' command within the Boot Loader performs a software reset of
 the system.  The system will perform a startup just like powering
-up or pressing the hardware reset button.
+up or pressing the hardware reset button (although the hardware is
+not physically reset).
 
 There is generally no need to do this, but it can be convenient when
 you want to see the boot messages again or ensure your system is in
@@ -2604,6 +2640,7 @@ therefore, globally available.
 | XM              | XModem file transfer program adapted to hardware. Automatically uses primary serial port on system.  |
 | FLASH           | Will Sowerbutts' in-situ ROM programming utility.                                                    |
 | FDISK80         | John Coffman's Z80 hard disk partitioning tool.  See documentation in Doc directory.                 |
+| FAT             | Access MS-DOS FAT filesystems from RomWBW (based on FatFs).        |
 | TALK            | Direct console I/O to a specified character device.                                                  |
 | RTC             | Manage and test the Real Time Clock hardware.                                                        |
 | TIMER           | Display value of running periodic system timer.                                                      |
@@ -2611,12 +2648,12 @@ therefore, globally available.
 
 Some custom applications do not fit on the ROM disk. They are found on the
 disk image files or the individual files can be found in the Binary/Apps
-directory of the distribution.
+directory of the distribution.  They are also included on the
+floppy disk and hard disk images.
 
 | **Application** | **Description**                                                    |
 |-----------------|--------------------------------------------------------------------|
 | TUNE            | Play .PT2, .PT3, .MYM audio files.                                 |
-| FAT             | Access MS-DOS FAT filesystems from RomWBW (based on FatFs).        |
 | INTTEST         | Test interrupt vector hooking.                                     |
 
 # FAT Filesystem
@@ -3434,11 +3471,11 @@ users. All required build tools (compilers, assemblers, etc.) are
 included in the distribution, so it is not necessary to setup a build
 environment on your computer.
 
-RomWBW can be built on modern Windows, Linux, or MacOS computers.  The
-process for building a custom ROM is documented in the ReadMe.txt file
-in the Source directory of the distribution.  Any modern version of
-Windows, MacOS, or Linux released in the last 10 years should be able
-to run the build process.
+RomWBW can be built on modern Windows, Linux, or MacOS computers.  The 
+process for building a custom ROM is documented in the ReadMe.txt file 
+in the Source directory of the distribution.  Any modern version of 
+Windows (32-bit or 64-bit), MacOS, or Linux released in the last 10 
+years should be able to run the build process.
 
 For those who are interested in more than basic system customization,
 note that all source code is provided (including the operating
@@ -3677,6 +3714,7 @@ them over any older versions of the app on your disk:
 * TALK.COM
 * RTC.COM
 * TIMER.COM
+* FAT.COM
 
 For example: `B>COPY ASSIGN.COM C:`
 
@@ -3686,9 +3724,13 @@ system and then update all copies. These applications are found in
 the Binary/Apps directory of the distribution and in all of the disk
 images.
 
-* FAT.COM
 * TUNE.COM
 
+The files normally contained on the standard ROM Disk is based on a 512K
+ROM.  If your system has a smaller size ROM, then not all of these 
+files will be included on your ROM Disk.  You will need to copy them to
+your system from the /Binary/Apps folder of the RomWBW distribution.
+
 **WARNING**: If you run a RomWBW-specific application that is not
 the appropriate for the version of RomWBW you are running, the
 application will generate an error message and abort.
@@ -3848,6 +3890,33 @@ please let me know if I missed you!
   BASIC Compiler, Microsoft Fortran Compiler, and a Games
   compendium.
 
+* Martin R has provided substantial help reviewing and improving the
+  User Guide.
+
+* Jacques Pelletier has contributed the DS1501 RTC driver code.
+
+* Jose Collado has contributed enhancements to the TMS driver
+  including compatibility with standard TMS register configuration.
+
+* Kevin Boone has contributed a generic HBIOS date/time utility (WDATE).
+
+* Matt Carroll has contributed a fix to XM.COM that corrects the
+  port specification when doing a send.
+
+* Dean Jenkins enhanced the build process to accommodate the
+  Raspberry Pi 4.
+
+* Tom Plano has contributed a new utility (HTALK) to allow talking
+  directly to HBIOS COM ports.
+
+* Lars Nelson has contributed several generic utilities such as
+  a universal (OS agnostic) UNARC application.
+
+* Dylan Hall added support for specifying a secondary console.
+
+* Bill Shen has contributed boot loaders for several of his
+  systems.
+
 Contributions of all kinds to RomWBW are very welcome.
 
 # Licensing
@@ -4215,6 +4284,10 @@ the RomWBW HBIOS configuration.
 - SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED
 - SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED
 - ACIA: IO=128, INTERRUPTS ENABLED
+- CH: IO=62
+- CH: IO=60
+- CHUSB: IO=62
+- CHUSB: IO=60
 - MD: TYPE=RAM
 - MD: TYPE=ROM
 - FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD
@@ -4251,6 +4324,10 @@ the RomWBW HBIOS configuration.
 - UART: MODE=RC, IO=168
 - SIO MODE=STD, IO=136, CHANNEL A, INTERRUPTS ENABLED
 - SIO MODE=STD, IO=136, CHANNEL B, INTERRUPTS ENABLED
+- CH: IO=62
+- CH: IO=60
+- CHUSB: IO=62
+- CHUSB: IO=60
 - MD: TYPE=RAM
 - MD: TYPE=ROM
 - FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD
@@ -4295,6 +4372,10 @@ the RomWBW HBIOS configuration.
 - SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED
 - SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED
 - SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED
+- CH: IO=62
+- CH: IO=60
+- CHUSB: IO=62
+- CHUSB: IO=60
 - MD: TYPE=RAM
 - MD: TYPE=ROM
 - FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD
@@ -4336,6 +4417,10 @@ the RomWBW HBIOS configuration.
 - SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED
 - SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED
 - SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED
+- CH: IO=62
+- CH: IO=60
+- CHUSB: IO=62
+- CHUSB: IO=60
 - MD: TYPE=RAM
 - MD: TYPE=ROM
 - FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD
@@ -4377,6 +4462,10 @@ the RomWBW HBIOS configuration.
 - SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED
 - SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED
 - SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED
+- CH: IO=62
+- CH: IO=60
+- CHUSB: IO=62
+- CHUSB: IO=60
 - ACIA: IO=128, INTERRUPTS ENABLED
 - MD: TYPE=RAM
 - MD: TYPE=ROM
@@ -4416,6 +4505,10 @@ the RomWBW HBIOS configuration.
 - SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED
 - SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED
 - SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED
+- CH: IO=62
+- CH: IO=60
+- CHUSB: IO=62
+- CHUSB: IO=60
 - MD: TYPE=RAM
 - MD: TYPE=ROM
 - FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD
@@ -4456,6 +4549,10 @@ the RomWBW HBIOS configuration.
 - SIO MODE=STD, IO=128, CHANNEL B, INTERRUPTS ENABLED
 - SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED
 - SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED
+- CH: IO=62
+- CH: IO=60
+- CHUSB: IO=62
+- CHUSB: IO=60
 - MD: TYPE=RAM
 - MD: TYPE=ROM
 - FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD
@@ -4496,6 +4593,10 @@ the RomWBW HBIOS configuration.
 - SIO MODE=STD, IO=24, CHANNEL B, INTERRUPTS ENABLED
 - SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED
 - SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED
+- CH: IO=62
+- CH: IO=60
+- CHUSB: IO=62
+- CHUSB: IO=60
 - MD: TYPE=RAM
 - MD: TYPE=ROM
 - FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD
@@ -4537,6 +4638,10 @@ the RomWBW HBIOS configuration.
 - SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED
 - SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED
 - ACIA: IO=128, INTERRUPTS ENABLED
+- CH: IO=62
+- CH: IO=60
+- CHUSB: IO=62
+- CHUSB: IO=60
 - MD: TYPE=RAM
 - MD: TYPE=ROM
 - FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD
@@ -4580,6 +4685,10 @@ the RomWBW HBIOS configuration.
 - SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED
 - SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED
 - SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED
+- CH: IO=62
+- CH: IO=60
+- CHUSB: IO=62
+- CHUSB: IO=60
 - MD: TYPE=RAM
 - MD: TYPE=ROM
 - FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD
@@ -4624,6 +4733,10 @@ the RomWBW HBIOS configuration.
 - SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED
 - SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED
 - SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED
+- CH: IO=62
+- CH: IO=60
+- CHUSB: IO=62
+- CHUSB: IO=60
 - MD: TYPE=RAM
 - MD: TYPE=ROM
 - FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD
@@ -4695,6 +4808,10 @@ the RomWBW HBIOS configuration.
 - SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED
 - SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED
 - SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED
+- CH: IO=62
+- CH: IO=60
+- CHUSB: IO=62
+- CHUSB: IO=60
 - MD: TYPE=RAM
 - MD: TYPE=ROM
 - FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD
@@ -4738,6 +4855,10 @@ the RomWBW HBIOS configuration.
 - SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED
 - SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED
 - SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED
+- CH: IO=62
+- CH: IO=60
+- CHUSB: IO=62
+- CHUSB: IO=60
 - MD: TYPE=RAM
 - MD: TYPE=ROM
 - FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD
@@ -4781,7 +4902,11 @@ the RomWBW HBIOS configuration.
 - SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED
 - SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED
 - SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED
-- MD: TYPE=RAM
+- CH: IO=62
+- CH: IO=60
+- CHUSB: IO=62
+- CHUSB: IO=60
+S- MD: TYPE=RAM
 - MD: TYPE=ROM
 - FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD
 - FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD
@@ -4937,6 +5062,10 @@ the RomWBW HBIOS configuration.
 - ACIA: IO=128, INTERRUPTS ENABLED
 - VRC: IO=0, KBD MODE=VRC, KBD IO=244
 - KBD: ENABLED
+- CH: IO=62
+- CH: IO=60
+- CHUSB: IO=62
+- CHUSB: IO=60
 - MD: TYPE=RAM
 - MD: TYPE=ROM
 - FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD
@@ -4980,6 +5109,57 @@ the RomWBW HBIOS configuration.
 - ACIA: IO=128, INTERRUPTS ENABLED
 - VRC: IO=0, KBD MODE=VRC, KBD IO=244
 - KBD: ENABLED
+- CH: IO=62
+- CH: IO=60
+- CHUSB: IO=62
+- CHUSB: IO=60
+- MD: TYPE=RAM
+- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD
+- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD
+- IDE: MODE=RC, IO=16, MASTER
+- IDE: MODE=RC, IO=16, SLAVE
+- PPIDE: IO=32, MASTER
+- PPIDE: IO=32, SLAVE
+- CTC: IO=136
+
+##### Notes:
+
+- ROMless boot -- HBIOS is loaded from disk at boot
+- CPU speed will be dynamically measured at startup if DSRTC is present
+
+`\clearpage`{=latex}
+
+### Z80 ZRC512 CPU Module
+
+#### ROM Image File:  RCZ80_zrc512.rom
+
+|                   |               |
+|-------------------|---------------|
+| Default CPU Speed | 22.000 MHz    |
+| Interrupts        | Mode 1        |
+| System Timer      | None          |
+| Serial Default    | 115200 Baud   |
+| Memory Manager    | ZRC           |
+| ROM Size          | 0 KB          |
+| RAM Size          | 512 KB        |
+
+##### Supported Hardware (see [Appendix B - Device Summary]):
+
+- FP: LEDIO=0, SWIO=0
+- DSRTC: MODE=STD, IO=192
+- UART: MODE=RC, IO=160
+- UART: MODE=RC, IO=168
+- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED
+- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED
+- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED
+- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED
+- ACIA: IO=128, INTERRUPTS ENABLED
+- VRC: IO=0, KBD MODE=VRC, KBD IO=244
+- KBD: ENABLED
+- CH: IO=62
+- CH: IO=60
+- CHUSB: IO=62
+- CHUSB: IO=60
 - MD: TYPE=RAM
 - FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD
 - FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD
@@ -5023,6 +5203,10 @@ the RomWBW HBIOS configuration.
 - SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED
 - SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED
 - SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED
+- CH: IO=62
+- CH: IO=60
+- CHUSB: IO=62
+- CHUSB: IO=60
 - MD: TYPE=RAM
 - FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD
 - FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD
@@ -5063,6 +5247,10 @@ the RomWBW HBIOS configuration.
 - SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED
 - SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED
 - SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED
+- CH: IO=62
+- CH: IO=60
+- CHUSB: IO=62
+- CHUSB: IO=60
 - VRC: IO=0, KBD MODE=VRC, KBD IO=244
 - KBD: ENABLED
 - MD: TYPE=RAM
@@ -5107,6 +5295,10 @@ the RomWBW HBIOS configuration.
 - SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED
 - VRC: IO=0, KBD MODE=VRC, KBD IO=244
 - KBD: ENABLED
+- CH: IO=62
+- CH: IO=60
+- CHUSB: IO=62
+- CHUSB: IO=60
 - MD: TYPE=RAM
 - FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD
 - FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD
@@ -5149,6 +5341,10 @@ the RomWBW HBIOS configuration.
 - SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED
 - VRC: IO=0, KBD MODE=VRC, KBD IO=244
 - KBD: ENABLED
+- CH: IO=62
+- CH: IO=60
+- CHUSB: IO=62
+- CHUSB: IO=60
 - MD: TYPE=RAM
 - MD: TYPE=ROM
 - FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD
@@ -5216,7 +5412,6 @@ the RomWBW HBIOS configuration.
 - MD: TYPE=ROM
 - SD: MODE=SC, IO=12, UNITS=1
 
-
 ##### Notes:
 
 `\clearpage`{=latex}

Source/HBIOS/Build.cmd

@@ -139,7 +139,7 @@ if %ROMSize% gtr 0 (
     copy /b hbios_rom.bin + osimg.bin + osimg1.bin + osimg2.bin %ROMName%.upd || exit /b
     copy /b hbios_app.bin + osimg_small.bin %ROMName%.com || exit /b
 ) else (
-    copy /b hbios_rom.bin + osimg.bin + osimg1.bin + osimg2.bin  + ..\RomDsk\ram%ROMSize%_wbw.dat %ROMName%.rom || exit /b
+    copy /b hbios_rom.bin + osimg.bin + osimg1.bin + osimg2.bin  + ..\RomDsk\ram%RAMSize%_wbw.dat %ROMName%.rom || exit /b
     copy /b hbios_rom.bin + osimg.bin + osimg1.bin + osimg2.bin %ROMName%.upd || exit /b
     copy /b hbios_app.bin + osimg_small.bin %ROMName%.com || exit /b
 )
@@ -218,6 +218,7 @@ call Build RCZ80 skz || exit /b
 :: call Build RCZ80 duart || exit /b
 call Build RCZ80 zrc || exit /b
 call Build RCZ80 zrc_ram || exit /b
+call Build RCZ80 zrc512 || exit /b
 call Build RCZ180 ext || exit /b
 call Build RCZ180 nat || exit /b
 call Build RCZ180 z1rcc || exit /b
@@ -240,5 +241,6 @@ call Build S100 std || exit /b
 call Build DUO std || exit /b
 call Build HEATH std || exit /b
 call Build EPITX std || exit /b
+:: call Build MON std || exit /b
 
 goto :eof

Source/HBIOS/Build.ps1

@@ -27,7 +27,7 @@ $ErrorAction = 'Stop'
 # UNA BIOS is simply imbedded, it is not built here.
 #
 
-$PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "Z80RETRO", "DUO", "UNA", "HEATH"
+$PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "Z80RETRO", "DUO", "UNA", "HEATH", "MON"
 $PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO", "RPH", "S100", "EPITX"
 $PlatformListZ280 = "RCZ280"
 

Source/HBIOS/Build.sh

@@ -6,6 +6,7 @@ set -e
 export ROM_PLATFORM
 export ROM_CONFIG
 export ROMSIZE
+export RAMSIZE
 export CPUFAM
 
 if [ "${ROM_PLATFORM}" == "dist" ] ; then
@@ -30,6 +31,7 @@ if [ "${ROM_PLATFORM}" == "dist" ] ; then
 	ROM_PLATFORM="RCZ80"; ROM_CONFIG="skz"; bash Build.sh
 	ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc"; bash Build.sh
 	ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc_ram"; bash Build.sh
+	ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc512"; bash Build.sh
 	ROM_PLATFORM="RPH"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="SBC"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="SBC"; ROM_CONFIG="simh"; bash Build.sh
@@ -48,6 +50,7 @@ if [ "${ROM_PLATFORM}" == "dist" ] ; then
 	ROM_PLATFORM="ZETA2"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="HEATH"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="EPITX"; ROM_CONFIG="std"; bash Build.sh
+#	ROM_PLATFORM="MON"; ROM_CONFIG="std"; bash Build.sh
 	exit
 fi
 
@@ -112,4 +115,4 @@ fi
 
 #echo OBJECTS=${OBJECTS}
 
-make ROM_PLATFORM=${ROM_PLATFORM} ROM_CONFIG=${ROM_CONFIG} ROMSIZE=${ROMSIZE}
+make ROM_PLATFORM=${ROM_PLATFORM} ROM_CONFIG=${ROM_CONFIG} ROMSIZE=${ROMSIZE} RAMSIZE=${RAMSIZE}

Source/HBIOS/Config/MON_std.asm

@@ -0,0 +1,30 @@
+;
+;==================================================================================================
+;   MONSPUTER Z80 STANDARD CONFIGURATION
+;==================================================================================================
+;
+; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
+; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
+; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
+; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
+; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
+; YOUR FILE IN THE BUILD PROCESS.
+;
+; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
+; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
+; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
+; SETTINGS.
+;
+; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
+; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
+; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
+; DIRECTORIES ABOVE THIS ONE).
+;
+#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
+;
+#include "cfg_mon.asm"
+;
+CPUOSC		.SET	4000000		; CPU OSC FREQ IN MHZ
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP

Source/HBIOS/Config/RCZ280_ext.asm

@@ -26,7 +26,7 @@
 ;
 #include "cfg_rcz280.asm"
 ;
-CPUOSC		.SET	12000000	; CPU OSC FREQ IN MHZ
+CPUOSC		.SET	24000000	; CPU OSC FREQ IN MHZ
 INTMODE		.SET	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;

Source/HBIOS/Config/RCZ280_nat.asm

@@ -26,7 +26,7 @@
 ;
 #include "cfg_rcz280.asm"
 ;
-CPUOSC		.SET	12000000	; CPU OSC FREQ IN MHZ
+CPUOSC		.SET	24000000	; CPU OSC FREQ IN MHZ
 INTMODE		.SET	3		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;

Source/HBIOS/Config/RCZ280_zzrcc.asm

@@ -50,7 +50,7 @@ MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
 MDRAM		.SET	TRUE		; MD: ENABLE RAM DISK
 ;
 Z2UENABLE	.SET	TRUE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
-Z2UOSC		.SET	(CPUOSC / 8)	; Z2U: OSC FREQUENCY IN MHZ
+Z2UOSC		.SET	(CPUOSC / 16)	; Z2U: OSC FREQUENCY IN MHZ
 Z2U0HFC		.SET	TRUE		; Z2U0: ENABLE HARDWARE FLOW CONTROL
 UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)

Source/HBIOS/Config/RCZ280_zzrcc_ram.asm

@@ -50,7 +50,7 @@ MDROM		.SET	FALSE		; MD: ENABLE ROM DISK
 MDRAM		.SET	TRUE		; MD: ENABLE RAM DISK
 ;
 Z2UENABLE	.SET	TRUE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
-Z2UOSC		.SET	(CPUOSC / 8)	; Z2U: OSC FREQUENCY IN MHZ
+Z2UOSC		.SET	(CPUOSC / 16)	; Z2U: OSC FREQUENCY IN MHZ
 Z2U0HFC		.SET	TRUE		; Z2U0: ENABLE HARDWARE FLOW CONTROL
 UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)

Source/HBIOS/Config/RCZ80_zrc.asm

@@ -34,8 +34,8 @@ CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
 FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
 ;
-RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE		.SET	256		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+RAMSIZE		.SET	1536		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
 MEMMGR		.SET	MM_ZRC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
 ;
 UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)

Source/HBIOS/Config/RCZ80_zrc512.asm

@@ -0,0 +1,68 @@
+;
+;==================================================================================================
+;   RCBUS Z80 ZRC512 CONFIGURATION
+;==================================================================================================
+;
+; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
+; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
+; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
+; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
+; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
+; YOUR FILE IN THE BUILD PROCESS.
+;
+; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
+; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
+; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
+; SETTINGS.
+;
+; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
+; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
+; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
+; DIRECTORIES ABOVE THIS ONE).
+;
+#DEFINE PLATFORM_NAME "ZRC512", " [", CONFIG, "]"
+;
+#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
+;
+#include "cfg_rcz80.asm"
+;
+CPUOSC		.SET	22000000	; CPU OSC FREQ IN MHZ
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+;
+FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+;
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.SET	0		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+MEMMGR		.SET	MM_ZRC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
+;
+MDROM		.SET	FALSE		; MD: ENABLE ROM DISK
+;
+UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+ACIAENABLE	.SET	TRUE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+;
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
+MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+VRCENABLE	.SET	TRUE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+;
+AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
+AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+;
+FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
+;
+IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY
+IMMENABLE	.SET	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+;
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)

Source/HBIOS/Config/SCZ180_sc131.asm

@@ -52,3 +52,4 @@ PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM
 SDENABLE	.SET	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
 SDMODE		.SET	SDMODE_SC	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
 SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
+CHENABLE	.SET	FALSE		; CH: ENABLE CH375/376 USB SUPPORT

Source/HBIOS/Makefile

@@ -53,6 +53,7 @@ ROMNAME=${ROM_PLATFORM}_${ROM_CONFIG}
 # $(info ROM_PLATFORM=$(ROM_PLATFORM))
 # $(info ROM_CONFIG=$(ROM_CONFIG))
 # $(info ROMSIZE=$(ROMSIZE))
+# $(info RAMSIZE=$(RAMSIZE))
 # $(info ROMNAME=$(ROMNAME))
 # $(info CPUFAM=$(CPUFAM))
 # $(info TASM=$(TASM))
@@ -81,7 +82,7 @@ $(OBJECTS) : $(ROMDEPS)
 			cat hbios_rom.bin osimg.bin osimg1.bin osimg2.bin >$(ROMNAME).upd ; \
 			cat hbios_app.bin osimg_small.bin > $(ROMNAME).com ; \
 		else \
-			cat hbios_rom.bin osimg.bin osimg1.bin osimg2.bin >$(ROMNAME).rom ; \
+			cat hbios_rom.bin osimg.bin osimg1.bin osimg2.bin ../RomDsk/ram$(RAMSIZE)_wbw.dat >$(ROMNAME).rom ; \
 			cat hbios_rom.bin osimg.bin osimg1.bin osimg2.bin >$(ROMNAME).upd ; \
 			cat hbios_app.bin osimg_small.bin > $(ROMNAME).com ; \
 		fi \

Source/HBIOS/Makefile.new

@@ -0,0 +1,132 @@
+DIST_OBJECTS := \
+	DYNO_std MK4_std N8_std RCZ180_ext RCZ180_nat RCZ180_z1rcc \
+	RCZ280_ext RCZ280_nat RCZ280_zz80mb RCZ280_zzrcc RCZ280_zzrcc_ram \
+	RCZ80_std RCZ80_kio RCZ80_easy RCZ80_tiny RCZ80_skz RCZ80_zrc \
+	RCZ80_zrc_ram RCZ80_zrc512 RPH_std SBC_std SBC_simh MBC_std \
+	DUO_std SCZ180_sc126 SCZ180_sc130 SCZ180_sc131 SCZ180_sc140 \
+	SCZ180_sc503 SCZ180_sc700 S100_std UNA_std Z80RETRO_std \
+	ZETA_std ZETA2_std HEATH_std EPITX_std
+#	RCZ80_mt RCZ80_duart MON_std 
+
+OBJECTS := $(DIST_OBJECTS)
+OBJECTS := SBC_std MK4_std UNA_std S100_std
+OBJECTS := $(OBJECTS:=.rom) $(OBJECTS:=.com) $(OBJECTS:=.upd)
+OBJECTS := $(filter-out UNA_%.com UNA_%.upd,$(OBJECTS))
+
+DEST = ../../Binary
+TOOLS = ../../Tools
+OTHERS := *.img *.rom *.com *.upd *.bin *.hex cpm.sys zsys.sys build.inc
+OTHERS +=  *.build.inc font*.asm *.dat hbios_env.sh
+
+FONTS := font8x11c.asm font8x11u.asm font8x16c.asm font8x16u.asm
+FONTS += font8x8c.asm font8x8u.asm fontcgac.asm fontcgau.asm
+FONTS += fontvgarcc.asm fontvgarcu.asm
+
+BUILD_COMPONENT = \
+	cp $(*F).build.inc build.inc ; \
+	$(TASM) $(TASMFLAGS) $< $@ $(@:.bin=.lst) ; \
+	rm build.inc
+
+SHELL=/bin/bash
+
+include $(TOOLS)/Makefile.inc
+
+font%.asm:
+	cp ../Fonts/$@ .
+
+camel80.bin:
+	cp ../Forth/$@ .
+
+tastybasic.bin:
+	cp ../TastyBasic/src/$@ .
+
+s100mon.bin:
+	$(ZXCC) $(CPM)/SLR180 -s100mon/FH
+	$(ZXCC) $(CPM)/MLOAD25 -s100mon.bin=s100mon
+
+%.build.inc:
+	echo $@
+	echo "; RomWBW Configured for $(*F) at $$(date +%Y-%m-%d)" >>$@
+	echo ";" >>$@
+	echo "#DEFINE TIMESTAMP \"$$(date +%Y-%m-%d)\"" >>$@
+	echo "#DEFINE CONFIG \"$(*F)\"" >>$@
+	echo ";" >>$@
+	echo "#INCLUDE \"Config/$(*F).asm\"" >>$@
+	echo ";" >>$@
+	cat $@
+
+%.usrrom.bin: usrrom.asm %.build.inc ; $(BUILD_COMPONENT)
+%.updater.bin: updater.asm %.build.inc ; $(BUILD_COMPONENT)
+%.eastaegg.bin: eastaegg.asm %.build.inc ; $(BUILD_COMPONENT)
+%.game.bin: game.asm %.build.inc ; $(BUILD_COMPONENT)
+%.nascom.bin: nascom.asm %.build.inc ; $(BUILD_COMPONENT)
+%.romldr.bin: romldr.asm %.build.inc ; $(BUILD_COMPONENT)
+%.dbgmon.bin: dbgmon.asm %.build.inc ; $(BUILD_COMPONENT)
+
+%.hbios_env.com: hbios_env.asm %.build.inc
+	cp $(*F).build.inc build.inc
+	$(TASM) $(TASMFLAGS) -dBASH $< $@ $(@:.com=.lst)
+	rm build.inc
+
+%.hbios_env.sh: %.hbios_env.com
+	$(ZXCC) $< >$@
+
+%.hbios_rom.bin: hbios.asm %.build.inc %.hbios_env.sh $(FONTS)
+	. ./$(*F).hbios_env.sh ; \
+	TARGETS=("" "z80" "hd64180" "z280") ; \
+	CPU=$${TARGETS[$$CPUFAM]} ; \
+	cp $(*F).build.inc build.inc ; \
+	$(BINDIR)/uz80as -t $$CPU -dROMBOOT $< $@ $(@:.bin=.lst) ; \
+	srec_cat $@ -Binary -Crop 0 0x7FFF -Checksum_Negative_Big_Endian 0x7FFF 1 1 -o $@ -Binary ; \
+	rm build.inc
+
+%.hbios_app.bin: hbios.asm %.build.inc %.hbios_env.sh $(FONTS)
+	. ./$(*F).hbios_env.sh ; \
+	TARGETS=("" "z80" "hd64180" "z280") ; \
+	CPU=$${TARGETS[$$CPUFAM]} ; \
+	cp $(*F).build.inc build.inc ; \
+	$(BINDIR)/uz80as -t $$CPU -dAPPBOOT $< $@ $(@:.bin=.lst) ; \
+	rm build.inc
+
+UNA_%.osimg.bin: UNA_%.romldr.bin UNA_%.dbgmon.bin
+	cat UNA_$(*F).romldr.bin UNA_$(*F).dbgmon.bin ../ZSDOS/zsys_una.bin ../CPM22/cpm_una.bin >$@
+	srec_cat $@ -Binary -Crop 0 0x7FFF -Checksum_Negative_Big_Endian 0x7FFF 1 1 -o $@ -Binary
+
+%.osimg.bin: %.romldr.bin %.dbgmon.bin
+	cat $(*F).romldr.bin $(*F).dbgmon.bin ../ZSDOS/zsys_wbw.bin ../CPM22/cpm_wbw.bin >$@
+	srec_cat $@ -Binary -Crop 0 0x7FFF -Checksum_Negative_Big_Endian 0x7FFF 1 1 -o $@ -Binary
+
+%.osimg_small.bin: %.romldr.bin %.dbgmon.bin
+	cat $(*F).romldr.bin $(*F).dbgmon.bin ../ZSDOS/zsys_wbw.bin >$@
+
+%.osimg1.bin: camel80.bin %.nascom.bin tastybasic.bin %.game.bin %.eastaegg.bin netboot.mod %.updater.bin %.usrrom.bin
+	cat camel80.bin $(*F).nascom.bin tastybasic.bin $(*F).game.bin $(*F).eastaegg.bin netboot.mod $(*F).updater.bin $(*F).usrrom.bin >$@
+	srec_cat $@ -Binary -Crop 0 0x7FFF -Checksum_Negative_Big_Endian 0x7FFF 1 1 -o $@ -Binary
+
+%.imgpad2.bin: imgpad2.asm %.build.inc
+	cp $(*F).build.inc build.inc
+	$(TASM) $(TASMFLAGS) $< $@ $(@:.bin=.lst)
+	srec_cat $@ -Binary -Crop 0 0x7FFF -Checksum_Negative_Big_Endian 0x7FFF 1 1 -o $@ -Binary
+	rm build.inc
+
+S100_%.imgpad2.bin: s100mon.bin
+	cp $< $@
+	srec_cat $@ -Binary -Crop 0 0x7FFF -Checksum_Negative_Big_Endian 0x7FFF 1 1 -o $@ -Binary
+
+UNA_%.rom: UNA_%.osimg.bin UNA_%.hbios_env.sh
+	. ./UNA_$(*F).hbios_env.sh ; \
+	cat ../UBIOS/UNA-BIOS.BIN UNA_$(*F).osimg.bin ../UBIOS/FSFAT.BIN ../RomDsk/rom$${ROMSIZE}_una.dat >$@ ; \
+	cp UNA_$(*F).osimg.bin $(DEST)/UNA_WBW_SYS.bin ; \
+	cp ../RomDsk/rom$${ROMSIZE}_una.dat $(DEST)/UNA_WBW_ROM$${ROMSIZE}.bin
+
+%.rom: %.hbios_rom.bin %.osimg.bin %.osimg1.bin %.imgpad2.bin %.hbios_env.sh
+	. ./$(*F).hbios_env.sh ; \
+	if [ $$ROMSIZE -gt 0 ] ; then RD="rom$$ROMSIZE" ; else RD="ram$$RAMSIZE" ; fi ; \
+	cat $(*F).hbios_rom.bin $(*F).osimg.bin $(*F).osimg1.bin $(*F).imgpad2.bin ../RomDsk/$${RD}_wbw.dat >$@
+
+%.com: %.hbios_app.bin %.osimg_small.bin
+	cat $(*F).hbios_app.bin $(*F).osimg_small.bin >$@
+
+%.upd: %.hbios_rom.bin %.osimg.bin %.osimg1.bin %.imgpad2.bin
+	cat $(*F).hbios_rom.bin $(*F).osimg.bin $(*F).osimg1.bin $(*F).imgpad2.bin >$@
+

Source/HBIOS/ansi.asm

@@ -3,6 +3,10 @@
 ;   ANSI EMULATION MODULE
 ;==================================================================================================
 ;
+; ENHANCED BY: JOSE L. COLLADO -- 12/21/2023 - 
+;  NEW ANSI PRIVATE SEQUENCE TO INIT VDU AND CHANGE DEFAULT COLORS
+;  (SEE ANSI CONTROL SEQUENCE DISPATCHING SECTION BELOW FOR DETAILS)
+;
 ; TODO:
 ;   1) INSERT/DELETE CHARACTERS CTL SEQUENCES
 ;   2) OTHER CTL SEQUENCES?
@@ -61,6 +65,7 @@ ANSI_RESET:
 	LD	(ANSI_ATTR),A	; CLEAR ATTRIBUTES
 	LD	A,ANSI_DEFCOLOR	; DEFAULT COLOR
 	LD	(ANSI_COLOR),A	; RESET COLOR
+	LD	(ANSI_SCOLOR),A	; RESET SCREEN COLOR
 	XOR	A		; ZERO ACCUM
 	LD	(ANSI_WRAP),A	; CLEAR WRAP FLAG
 	LD	(ANSI_LNM),A	; SET LINE FEED NEW LINE MODE
@@ -385,6 +390,17 @@ ANSI_ESCDISP2:	; ESC DISPATCHING FOR '#' INT CHAR
 ;   ANSI CONTROL SEQUENCE DISPATCHING
 ;==================================================================================================
 ;
+;--------------------------------------------------------------------------------------------------
+; ### JLC Mod - NEW ANSI PRIVATE SEQUENCE TO INIT VDU AND CHANGE DEFAULT COLORS ###
+;--------------------------------------------------------------------------------------------------
+; Follows ANSI Standards described in VT100.net for Private Sequences.
+; Implements the ESC Seq.: \ESC[{Num1};{Num2}'{' where '{' is the final char of new Private Sequence.
+;  Initializes the VDU and Changes Default Colors according to the following table:
+;  	{Num1}: 30..37 - Foreground color (black, red, green, yellow, blue, magenta, cyan, white)
+;  	{Num2}: 40..47 - Background color (black, red, green, yellow, blue, magenta, cyan, white)
+;
+; Example: \ESC[37;44{ sets text to white on blue background, \ESC[0{ returns to default colors.
+;
 ANSI_CTLDISP:
 	LD	(ANSI_FINAL),A		; RECORD THE FINAL CHARACTER
 #IF (ANSITRACE >= 2)
@@ -453,6 +469,11 @@ ANSI_STD1:	; DISPATCH FOR FINAL CHAR W/ NO INTERMEDIATE CHAR AND NO PRIVATE CHAR
 	CP	'm'			; SGR: SELECT GRAPHIC RENDITION
 	JP	Z,ANSI_SGR
 	; CHECK FOR ANY OTHERS HERE
+	; ### JLC Mod - New Private Sequence with Parameters checked here...
+	CP	'{'					; SSC: SET SCREEN COLORS
+	JP	Z,ANSI_SSC
+	;
+	; ANY OTHERS ARE IGNORED
 	JR	ANSI_UNK		; UNKNOWN, ABORT
 ;
 ANSI_DEC:	; DISPATCH ON INTERMEDIATE CHAR W/ PRIVATE CHAR = '?' (DEC)
@@ -1147,14 +1168,15 @@ ANSI_SGR1:	; PROCESSING LOOP
 	INC	HL			; POINT TO NEXT PARM
 	DJNZ	ANSI_SGR1		; LOOP TILL DONE
 ;
-	; NOW IMPLEMENT ALL CHANGES
+	; NOW IMPLEMENT ALL CHANGES FOR SGR
 	LD	A,(ANSI_ATTR)		; GET THE ATTRIBUTE VALUE
 	LD	E,A			; MOVE TO E
 	LD	B,BF_VDASAT		; SET ATTRIBUTE FUNCTION
 	CALL	ANSI_VDADISP		; CALL THE FUNCTION
 	LD	A,(ANSI_COLOR)		; GET THE COLOR VALUE
 	LD	E,A			; MOVE TO E
-	LD	B,BF_VDASCO		; SET ATTRIBUTE FUNCTION
+	LD	D,0			; SET INDIVIDUAL CHAR COLORS
+	LD	B,BF_VDASCO		; SET COLOR FUNCTION
 	CALL	ANSI_VDADISP		; CALL THE FUNCTION
 	RET				; RETURN
 ;
@@ -1234,6 +1256,81 @@ ANSI_SGR_BG:
 ;
 ;
 ;
+;......................................................................................
+; ### JLC Mod - Implement new Private Sequence to call VDASCO and Change Default Colors
+;
+ANSI_SSC:	; SET SCREEN COLOR (CUSTOM EXTENSION)
+	LD	A,(ANSI_PARIDX)		; GET CURRENT PARM INDEX
+	INC	A			; INC TO MAKE IT THE COUNT
+	LD	B,A			; B IS NOW LOOP COUNTER
+	LD	HL,ANSI_PARLST		; HL POINTS TO START OF PARM LIST
+;
+ANSI_SSC1:	; PROCESSING LOOP
+	PUSH	BC			; PRESERVE BC
+	PUSH	HL			; PRESERVE HL
+	LD	A,(HL)
+	CALL	ANSI_SSC2		; HANDLE PARM
+	POP	HL			; RESTORE HL
+	POP	BC			; RESTORE BC
+	INC	HL			; POINT TO NEXT PARM
+	DJNZ	ANSI_SSC1		; LOOP TILL DONE
+;
+	; NOW IMPLEMENT ALL CHANGES FOR SSC
+	LD	A,(ANSI_SCOLOR)		; GET THE COLOR VALUE
+	LD	E,A			; MOVE TO E
+	LD	D,1			; SET SCREEN COLORS
+	LD	B,BF_VDASCO		; SET COLOR FUNCTION
+	CALL	ANSI_VDADISP		; CALL THE FUNCTION
+	RET				; RETURN
+;
+ANSI_SSC2:	; HANDLE THE REQUEST CODE
+	CP	0			; ALL OFF
+	JR	Z,ANSI_SSC_OFF		; DO IT
+	CP	30			; START OF FOREGROUND
+	RET	C			; OUT OF RANGE
+	CP	38			; END OF RANGE
+	JR	C,ANSI_SSC_FG		; SET FOREGROUND
+	CP	40			; START OF BACKGROUND
+	RET	C			; OUT OF RANGE
+	CP	48			; END OF RANGE
+	JR	C,ANSI_SSC_BG		; SET BACKGROUND
+	RET				; OTHERWISE OUT OF RANGE
+;
+ANSI_SSC_OFF:
+	LD	A,ANSI_DEFCOLOR		; DEFAULT COLOR
+	LD	(ANSI_SCOLOR),A		; RESET COLOR
+	RET
+;
+ANSI_SSC_BOLD:
+	LD	A,(ANSI_SCOLOR)		; LOAD CURRENT COLOR
+	OR	%00001000		; SET BOLD BIT
+	LD	(ANSI_SCOLOR),A		; SAVE IT
+	RET
+;
+ANSI_SSC_FG:
+	SUB	30
+	LD	E,A
+	LD	A,(ANSI_SCOLOR)
+	AND	%11111000
+	OR	E
+	LD	(ANSI_SCOLOR),A
+	RET
+;
+ANSI_SSC_BG:
+	SUB	40
+	RLCA
+	RLCA
+	RLCA
+	RLCA
+	LD	E,A
+	LD	A,(ANSI_SCOLOR)
+	AND	%10001111
+	OR	E
+	LD	(ANSI_SCOLOR),A
+	RET
+;
+;
+;
 ANSI_DECALN:	; DEC SCREEN ALIGNMENT TEST
 	LD	DE,0		; PREPARE TO HOME CURSOR
 	LD	(ANSI_POS),DE	; SAVE NEW CURSOR POSITION
@@ -1394,7 +1491,8 @@ ANSI_ROWS	.DB	24	; NUMBER OF ROWS ON SCREEN
 ;
 ANSI_STATE	.DW	PANIC		; CURRENT FUNCTION FOR STATE MACHINE
 ANSI_ATTR	.DB	ANSI_DEFATTR	; CURRENT CHARACTER ATTRIBUTE
-ANSI_COLOR	.DB	ANSI_DEFCOLOR	; CURRENT CHARACTER COLOR;
+ANSI_COLOR	.DB	ANSI_DEFCOLOR	; CURRENT CHARACTER FG/BG COLOR
+ANSI_SCOLOR	.DB	ANSI_DEFCOLOR	; CURRENT SCREEN FG/BG COLOR
 ANSI_WRAP	.DB	0		; WRAP PENDING FLAG
 ANSI_TABS	.FILL	32,0		; TAB STOP BIT MAP (256 BITS)
 ANSI_LNM	.DB	0		; LINE FEED NEW LINE MODE FLAG
@@ -1415,3 +1513,25 @@ ANSI_VARLEN	.EQU	$ - ANSI_VARS
 ;
 ANSI_VDAUNIT	.DB	$FF	; VIDEO UNIT NUM OF ATTACHED VDA DEVICE
 ANSI_DEVNUM	.DB	$FF	; TERMINAL DEVICE NUMBER
+;
+;=============================================================
+; BASIC ANSI COLOR TABLE (NIBBLES FOR FOREGROUND & BACKGROUND)
+; ------------------------------------------------------------
+;	 0 Black
+;	 1 Red
+;	 2 Green
+;	 3 Brown
+;	 4 Blue
+;	 5 Magenta
+;	 6 Cyan
+;	 7 White
+;	 8 Gray
+;	 9 Light Red
+;	 A Light Green
+;	 B Yellow
+;	 C Light Blue
+;	 D Light Magenta
+;	 E Light Cyan
+;	 F Bright White
+;=============================================================
+;

Source/HBIOS/cfg_duo.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_DUO		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+PLATFORM	.EQU	PLT_DUO		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,7 @@ DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
 MPGSEL_0	.EQU	$50		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$51		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$52		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
@@ -65,11 +65,11 @@ SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
-FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
-FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
-FPLED_DSKACT	.EQU	FALSE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
-FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
-FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+FPLED_ENABLE	.EQU	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.EQU	$42		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.EQU	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.EQU	$42		; FP: PORT ADDRESS FOR FP SWITCHES
 ;
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
@@ -78,12 +78,12 @@ LEDMODE		.EQU	LEDMODE_RTC	; LEDMODE_[STD|RTC]
 LEDPORT		.EQU	RTCIO		; STATUS LED PORT ADDRESS
 LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
-DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYENABLE	.EQU	TRUE		; ENABLES DSKY FUNCTIONALITY
 DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
 ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
-ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
-PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
-PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
+ICMPPIBASE	.EQU	$88		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.EQU	TRUE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.EQU	$88		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
@@ -178,8 +178,8 @@ MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
 ;
-FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.EQU	FDMODE_MBC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDENABLE	.EQU	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.EQU	FDMODE_DUO	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
@@ -211,10 +211,10 @@ IDE2DATHI	.EQU	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
 IDE2A8BIT	.EQU	TRUE		; IDE 2A (MASTER): 8 BIT XFER
 IDE2B8BIT	.EQU	TRUE		; IDE 2B (MASTER): 8 BIT XFER
 ;
-PPIDEENABLE	.EQU	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDEENABLE	.EQU	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
 PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
-PPIDE0BASE	.EQU	$60		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0BASE	.EQU	$88		; PPIDE 0: PPI REGISTERS BASE ADR
 PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
 PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 PPIDE1BASE	.EQU	$20		; PPIDE 1: PPI REGISTERS BASE ADR
@@ -224,12 +224,13 @@ PPIDE2BASE	.EQU	$14		; PPIDE 2: PPI REGISTERS BASE ADR
 PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
-SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_JUHA	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.EQU	TRUE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
 CHENABLE	.EQU	TRUE		; CH: ENABLE CH375/376 USB SUPPORT
 CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_dyno.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_DYNO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+PLATFORM	.EQU	PLT_DYNO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,7 @@ DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
 RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)

Source/HBIOS/cfg_epitx.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_EPITX	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|EPITX]
+PLATFORM	.EQU	PLT_EPITX	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,7 @@ DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.AS
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
 RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 ;
 Z180_BASE	.EQU	$C0		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
@@ -253,12 +253,12 @@ CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
 CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
-CH0BASE		.EQU	$BE		; CH 0: BASE I/O ADDRESS
+CHCNT		.EQU	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$3E		; CH 0: BASE I/O ADDRESS
 CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
 CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
-CH1BASE		.EQU	$FF		; CH 1: BASE I/O ADDRESS
-CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
+CH1BASE		.EQU	$3C		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	TRUE		; CH 1: ENABLE USB DISK
 CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
 ;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)

Source/HBIOS/cfg_heath.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_HEATH	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+PLATFORM	.EQU	PLT_HEATH	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,7 @@ DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.AS
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)

Source/HBIOS/cfg_master.asm

@@ -12,7 +12,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -31,7 +31,7 @@ DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_NONE		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MEMMGR		.EQU	MM_NONE		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
 RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
@@ -303,12 +303,12 @@ CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
 CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
-CH0BASE		.EQU	$BE		; CH 0: BASE I/O ADDRESS
+CHCNT		.EQU	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$3E		; CH 0: BASE I/O ADDRESS
 CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
 CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
-CH1BASE		.EQU	$FF		; CH 1: BASE I/O ADDRESS
-CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
+CH1BASE		.EQU	$3C		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	TRUE		; CH 1: ENABLE USB DISK
 CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
 ;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)

Source/HBIOS/cfg_mbc.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_MBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+PLATFORM	.EQU	PLT_MBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,7 @@ DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_MBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MEMMGR		.EQU	MM_MBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
 ;
@@ -227,6 +227,7 @@ SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
 CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
 ;

Source/HBIOS/cfg_mk4.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_MK4		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+PLATFORM	.EQU	PLT_MK4		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,7 @@ DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
 RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 ;
 Z180_BASE	.EQU	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
@@ -236,6 +236,7 @@ SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	TRUE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
 CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
 ;

Source/HBIOS/cfg_mon.asm

@@ -0,0 +1,328 @@
+;
+;==================================================================================================
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR MONSPUTER Z80
+;==================================================================================================
+;
+; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
+; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
+; UNDER THIS DIRECTORY.
+;
+; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
+; FOR THE PLATFORM.
+;
+#DEFINE PLATFORM_NAME "Monsputer", " [", CONFIG, "]"
+;
+#INCLUDE "hbios.inc"
+;
+PLATFORM	.EQU	PLT_MON		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+;
+BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+;
+CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.EQU	4000000		; CPU OSC FREQ IN MHZ
+INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;
+RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+MEMMGR		.EQU	MM_MON		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
+;
+RTCIO		.EQU	$C0		; RTC LATCH REGISTER ADR
+;
+KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+;
+CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
+CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
+CTCMODE		.EQU	CTCMODE_TIM16	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
+CTCPRE		.EQU	256		; PRESCALE CONSTANT (1-256)
+CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
+CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
+CTCOSC		.EQU	CPUOSC		; CTC CLOCK FREQUENCY
+;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
+SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+SKZDIV		.EQU	DIV_1		; UART CLK (CLK2) DIVIDER FOR Z80-512K
+;
+WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+WDOGIO		.EQU	$6E		; WATCHDOG REGISTER ADR
+;
+FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+;
+DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+;
+LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
+LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|RTC]
+LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
+LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+;
+DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+;
+BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
+CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYENABLE	.EQU	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+;
+DSRTCENABLE	.EQU	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
+DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+;
+DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+;
+BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+;
+INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+;
+RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
+HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+;
+DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+;
+DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+DUARTCNT	.EQU	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
+DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
+DUART0ACFG	.EQU	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
+DUART0BCFG	.EQU	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
+DUART1BASE	.EQU	$40		; DUART 1: BASE ADDRESS OF CHIP
+DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
+DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
+;
+UARTENABLE	.EQU	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
+UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
+UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
+UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
+UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
+UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
+UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+;
+ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+;
+Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+;
+ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+ACIADEBUG	.EQU	FALSE		; ACIA: ENABLE DEBUG OUTPUT
+ACIACNT		.EQU	1		; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
+ACIA0BASE	.EQU	$80		; ACIA 0: REGISTERS BASE ADR
+ACIA0CLK	.EQU	CPUOSC		; ACIA 0: OSC FREQ IN HZ
+ACIA0DIV	.EQU	1		; ACIA 0: SERIAL CLOCK DIVIDER
+ACIA0CFG	.EQU	DEFSERCFG	; ACIA 0: SERIAL LINE CONFIG  (SEE STD.ASM)
+ACIA1BASE	.EQU	$40		; ACIA 1: REGISTERS BASE ADR
+ACIA1CLK	.EQU	CPUOSC		; ACIA 1: OSC FREQ IN HZ
+ACIA1DIV	.EQU	1		; ACIA 1: SERIAL CLOCK DIVIDER
+ACIA1CFG	.EQU	DEFSERCFG	; ACIA 1: SERIAL LINE CONFIG  (SEE STD.ASM)
+;
+SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.EQU	CPUOSC		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
+SIO1ACLK	.EQU	CPUOSC		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1ACFG	.EQU	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
+SIO1ACTCC	.EQU	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1BCLK	.EQU	CPUOSC		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1BCFG	.EQU	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
+SIO1BCTCC	.EQU	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+;
+XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+;
+VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
+TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+;
+MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+;
+FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+;
+RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+;
+IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.EQU	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT		.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.EQU	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE0BASE	.EQU	$10		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.EQU	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.EQU	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.EQU	TRUE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.EQU	TRUE		; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.EQU	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE1BASE	.EQU	$00		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.EQU	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.EQU	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.EQU	TRUE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.EQU	TRUE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.EQU	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE2BASE	.EQU	$00		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.EQU	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.EQU	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.EQU	TRUE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.EQU	TRUE		; IDE 2B (MASTER): 8 BIT XFER
+;
+PPIDEENABLE	.EQU	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.EQU	$20		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1BASE	.EQU	$00		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE2BASE	.EQU	$00		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+;
+SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.EQU	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$3E		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.EQU	$3C		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	TRUE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+;
+PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+;
+PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
+HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+;
+LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTMODE		.EQU	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTCNT		.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
+LPTTRACE	.EQU	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+LPT0BASE	.EQU	$0C		; LPT 0: REGISTERS BASE ADR
+LPT1BASE	.EQU	$00		; LPT 1: REGISTERS BASE ADR
+;
+PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
+PPACNT		.EQU	1		; PPA: NUMBER OF PPA DEVICES (1-2)
+PPATRACE	.EQU	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPAMODE		.EQU	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
+PPA0BASE	.EQU	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
+PPA1BASE	.EQU	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
+;
+IMMENABLE	.EQU	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+IMMCNT		.EQU	1		; IMM: NUMBER OF IMM DEVICES (1-2)
+IMMTRACE	.EQU	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IMMMODE		.EQU	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
+IMM0BASE	.EQU	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
+IMM1BASE	.EQU	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
+;
+SYQENABLE	.EQU	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
+SYQCNT		.EQU	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
+SYQTRACE	.EQU	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SYQMODE		.EQU	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
+SYQ0BASE	.EQU	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQ1BASE	.EQU	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
+;
+PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+;
+UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+;
+SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
+SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
+;
+AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
+AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
+;
+SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+;
+DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.EQU	DMAMODE_RC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
+;
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_n8.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_N8		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+PLATFORM	.EQU	PLT_N8		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,7 @@ DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_N8		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MEMMGR		.EQU	MM_N8		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
 RAMBIAS		.EQU	0		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 ;
 Z180_BASE	.EQU	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
@@ -238,6 +238,7 @@ SDPPIBASE	.EQU	N8_PPI0		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
 CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
 ;

Source/HBIOS/cfg_rcz180.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+PLATFORM	.EQU	PLT_RCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,7 @@ DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.AS
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
 RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
@@ -253,16 +253,16 @@ SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
-CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHENABLE	.EQU	TRUE		; CH: ENABLE CH375/376 USB SUPPORT
 CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
-CH0BASE		.EQU	$BE		; CH 0: BASE I/O ADDRESS
+CHCNT		.EQU	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$3E		; CH 0: BASE I/O ADDRESS
 CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
 CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
-CH1BASE		.EQU	$FF		; CH 1: BASE I/O ADDRESS
-CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
+CH1BASE		.EQU	$3C		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	TRUE		; CH 1: ENABLE USB DISK
 CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
 ;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)

Source/HBIOS/cfg_rcz280.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RCZ280	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+PLATFORM	.EQU	PLT_RCZ280	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z280	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -28,13 +28,13 @@ BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
 ;
 CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
-CPUOSC		.EQU	12000000	; CPU OSC FREQ IN MHZ
+CPUOSC		.EQU	24000000	; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
 RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
@@ -257,16 +257,16 @@ SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
-CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHENABLE	.EQU	TRUE		; CH: ENABLE CH375/376 USB SUPPORT
 CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
-CH0BASE		.EQU	$BE		; CH 0: BASE I/O ADDRESS
+CHCNT		.EQU	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$3E		; CH 0: BASE I/O ADDRESS
 CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
 CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
-CH1BASE		.EQU	$FF		; CH 1: BASE I/O ADDRESS
-CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
+CH1BASE		.EQU	$3C		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	TRUE		; CH 1: ENABLE USB DISK
 CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
 ;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)

Source/HBIOS/cfg_rcz80.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RCZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+PLATFORM	.EQU	PLT_RCZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,7 @@ DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.AS
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
@@ -252,16 +252,16 @@ SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
-CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHENABLE	.EQU	TRUE		; CH: ENABLE CH375/376 USB SUPPORT
 CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
-CH0BASE		.EQU	$BE		; CH 0: BASE I/O ADDRESS
+CHCNT		.EQU	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$3E		; CH 0: BASE I/O ADDRESS
 CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
 CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
-CH1BASE		.EQU	$FF		; CH 1: BASE I/O ADDRESS
-CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
+CH1BASE		.EQU	$3C		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	TRUE		; CH 1: ENABLE USB DISK
 CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
 ;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)

Source/HBIOS/cfg_rph.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RPH		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+PLATFORM	.EQU	PLT_RPH		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	TRUE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,7 @@ DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_RPH		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MEMMGR		.EQU	MM_RPH		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
 RAMBIAS		.EQU	0		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 ;
 Z180_BASE	.EQU	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
@@ -227,6 +227,7 @@ SDPPIBASE	.EQU	RPH_PPI0	; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
 CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
 ;

Source/HBIOS/cfg_s100.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_S100	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+PLATFORM	.EQU	PLT_S100	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,7 @@ DEFSERCFG	.EQU	SER_57600_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
 RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)

Source/HBIOS/cfg_sbc.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,7 @@ DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MEMMGR		.EQU	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
 ;
@@ -226,6 +226,7 @@ SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
 CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
 ;

Source/HBIOS/cfg_scz180.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_SCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+PLATFORM	.EQU	PLT_SCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,7 @@ DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.AS
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
 RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
@@ -247,16 +247,16 @@ SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
-CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHENABLE	.EQU	TRUE		; CH: ENABLE CH375/376 USB SUPPORT
 CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
-CH0BASE		.EQU	$BE		; CH 0: BASE I/O ADDRESS
+CHCNT		.EQU	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$3E		; CH 0: BASE I/O ADDRESS
 CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
 CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
-CH1BASE		.EQU	$FF		; CH 1: BASE I/O ADDRESS
-CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
+CH1BASE		.EQU	$3C		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	TRUE		; CH 1: ENABLE USB DISK
 CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
 ;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)

Source/HBIOS/cfg_una.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "../UBIOS/ubios.inc"
 ;
-;PLATFORM	.EQU	PLT_UNA		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+;PLATFORM	.EQU	PLT_UNA		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_UNA	; HARDWARE BIOS: BIOS_[WBW|UNA]
 ;

Source/HBIOS/cfg_z80retro.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_Z80RETRO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+PLATFORM	.EQU	PLT_Z80RETRO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,7 @@ DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
 MPGSEL_0	.EQU	$60		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$61		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$62		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
@@ -200,6 +200,7 @@ SDMODE		.EQU	SDMODE_Z80R	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
 CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
 ;

Source/HBIOS/cfg_zeta.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_ZETA	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+PLATFORM	.EQU	PLT_ZETA	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; BIOS_[WBW|UNA]: HARDWARE BIOS
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,7 @@ DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MEMMGR		.EQU	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
 ;
@@ -171,6 +171,7 @@ SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
 CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
 ;

Source/HBIOS/cfg_zeta2.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_ZETA2	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+PLATFORM	.EQU	PLT_ZETA2	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,7 @@ DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
@@ -182,6 +182,7 @@ SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
 CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
 ;

Source/HBIOS/chsd.asm

@@ -0,0 +1,685 @@
+;
+;==================================================================================================
+; CH376 SD CARD SUB-DRIVER
+;==================================================================================================
+;
+; Thanks and credit to Alan Cox.  Much of this driver is based on
+; his code in FUZIX (https://github.com/EtchedPixels/FUZIX).
+;
+; This file contains the SD Card specific support for the CH37x
+; driver.  This file is included by the core driver file (ch.asm) as
+; needed.  Note that only the CH376 actually supports SD Card access.
+;
+; The SD Card support is implemented using the CH376 file-level
+; support.  It is *not* possible to access SD Cards using raw
+; sector I/O.
+;
+; TODO:
+;  - Implement auto-recovery on error status?
+;
+#DEFINE	CHSD_IMGFILE "DISK.IMG"
+;
+CHSD_FASTIO	.EQU	TRUE		; USE INIR/OTIR?
+;
+; CHUSB DEVICE STATUS
+;
+CHSD_STOK	.EQU	0
+CHSD_STNOMEDIA	.EQU	-1
+CHSD_STCMDERR	.EQU	-2
+CHSD_STIOERR	.EQU	-3
+CHSD_STTO	.EQU	-4
+CHSD_STNOTSUP	.EQU	-5
+CHSD_STNOFILE	.EQU	-6
+;
+; CHSD DEVICE CONFIGURATION
+;
+CHSD_CFGSIZ	.EQU	14		; SIZE OF USB CFG TBL ENTRIES
+;
+; CONFIG ENTRY DATA OFFSETS
+;
+; THE LOCATION OF CHSD_MODE IS SHARED BY ALL SUB-DRIVERS AND THE
+; CH_SETMODE FUNCTION IN THE MAIN DRIVER (CH.ASM).  IF YOU CHANGE
+; IT, YOU MUST SYNC UP THE MAIN DRIVER AND ALL SUB-DRIVERS!
+;
+; FIRST 3 BYTES SAME AS CH CONFIG
+CHSD_STAT	.EQU	3		; LAST STATUS (BYTE)
+CHSD_MEDCAP	.EQU	4		; MEDIA CAPACITY (DWORD)
+CHSD_LBA	.EQU	8		; CURRENT LBA (DWORD)
+CHSD_MODE	.EQU	12		; PTR TO MODE BYTE (WORD)
+;
+CHSD_CFGTBL:
+;
+#IF (CHCNT >= 1)
+CHSD_CFG0:
+	.DB	0			; DEV NUM, FILLED DYNAMICALLY
+	.DB	CHTYP_NONE		; DEV TYPE, FILLED DYNCAMICALLY
+	.DB	CH0BASE			; IO BASE ADDRESS
+	.DB	0			; DEVICE STATUS
+	.DW	0,0			; DEVICE CAPACITY
+	.DW	0,0			; CURRENT LBA
+	.DW	CH0_MODE		; POINTER TO MODE BYTE
+;
+  #IF (CH0SDENABLE)
+	.ECHO	"CHSD: IO="
+	.ECHO	CH0BASE
+	.ECHO	"\n"
+  #ENDIF
+#ENDIF
+;
+#IF (CHCNT >= 2)
+CHSD_CFG1:
+	.DB	0			; DEV NUM
+	.DB	CHTYP_NONE		; DEV TYPE, FILLED DYNCAMICALLY
+	.DB	CH1BASE			; IO BASE ADDRESS
+	.DB	0			; DEVICE STATUS
+	.DW	0,0			; DEVICE CAPACITY
+	.DW	0,0			; CURRENT LBA
+	.DW	CH1_MODE		; POINTER TO MODE BYTE
+;
+  #IF (CH1SDENABLE)
+	.ECHO	"CHSD: IO="
+	.ECHO	CH1BASE
+	.ECHO	"\n"
+  #ENDIF
+#ENDIF
+;
+#IF ($ - CHSD_CFGTBL) != (CHCNT * CHSD_CFGSIZ)
+	.ECHO	"*** INVALID CHSD CONFIG TABLE ***\n"
+#ENDIF
+;
+	.DB	$FF			; END OF TABLE MARKER
+;
+;
+;
+CHSD_INIT:
+	LD	A,(IY+CH_TYPE)		; GET DEVICE TYPE
+	PUSH	HL			; COPY INCOMING HL
+	POP	IY			; ... TO IY
+	LD	(IY+CH_TYPE),A		; SAVE DEVICE TYPE
+;
+	; UPDATE DRIVER RELATIVE UNIT NUMBER IN CONFIG TABLE
+	LD	A,(CHSD_DEVNUM)		; GET NEXT UNIT NUM TO ASSIGN
+	LD	(IY+CH_DEV),A		; UPDATE IT
+	INC	A			; BUMP TO NEXT UNIT NUM TO ASSIGN
+	LD	(CHSD_DEVNUM),A		; SAVE IT
+;
+	; ADD UNIT TO GLOBAL DISK UNIT TABLE
+	LD	BC,CHSD_FNTBL		; BC := FUNC TABLE ADR
+	PUSH	IY			; CFG ENTRY POINTER
+	POP	DE			; COPY TO DE
+	CALL	DIO_ADDENT		; ADD ENTRY TO GLOBAL DISK DEV TABLE
+;
+	CALL	CHSD_RESET		; RESET & DISCOVER MEDIA
+#IF (CHSDTRACE <= 1)
+	CALL	NZ,CHSD_PRTSTAT
+#ENDIF
+	RET	NZ			; ABORT ON FAILURE
+;
+	; START PRINTING DEVICE INFO
+	CALL	CHSD_PRTPREFIX		; PRINT DEVICE PREFIX
+;
+	; PRINT STORAGE CAPACITY (BLOCK COUNT)
+	PRTS(" BLOCKS=0x$")		; PRINT FIELD LABEL
+	LD	A,CHSD_MEDCAP		; OFFSET TO CAPACITY FIELD
+	CALL	LDHLIYA			; HL := IY + A, REG A TRASHED
+	CALL	LD32			; GET THE CAPACITY VALUE
+	CALL	PRTHEX32		; PRINT HEX VALUE
+;
+	; PRINT STORAGE SIZE IN MB
+	PRTS(" SIZE=$")			; PRINT FIELD LABEL
+	LD	B,11			; 11 BIT SHIFT TO CONVERT BLOCKS --> MB
+	CALL	SRL32			; RIGHT SHIFT
+	CALL	PRTDEC32		; PRINT DWORD IN DECIMAL
+	PRTS("MB$")			; PRINT SUFFIX
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; DRIVER FUNCTION TABLE
+;
+CHSD_FNTBL:
+	.DW	CHSD_STATUS
+	.DW	CHSD_RESET
+	.DW	CHSD_SEEK
+	.DW	CHSD_READ
+	.DW	CHSD_WRITE
+	.DW	CHSD_VERIFY
+	.DW	CHSD_FORMAT
+	.DW	CHSD_DEVICE
+	.DW	CHSD_MEDIA
+	.DW	CHSD_DEFMED
+	.DW	CHSD_CAP
+	.DW	CHSD_GEOM
+#IF (($ - CHSD_FNTBL) != (DIO_FNCNT * 2))
+	.ECHO	"*** INVALID CHSD FUNCTION TABLE ***\n"
+#ENDIF
+;
+CHSD_VERIFY:
+CHSD_FORMAT:
+CHSD_DEFMED:
+	SYSCHKERR(ERR_NOTIMPL)		; NOT IMPLEMENTED
+	RET
+;
+;
+;
+CHSD_READ:
+	LD	A,CH_MODE_SD		; REQUEST SD MODE
+	CALL	CH_SETMODE		; DO IT
+	JP	NZ,CHSD_CMDERR		; HANDLE ERROR
+;
+	CALL	HB_DSKREAD		; HOOK HBIOS DISK READ SUPERVISOR
+	LD	(CHSD_DSKBUF),HL	; SAVE DISK BUFFER ADDRESS
+	CALL	CHSD_RWSTART		; SET LBA OFFSET
+	RET	NZ
+;
+	;PRTS("\n\rREAD:$")		; *DEBUG*
+	LD	A,CH_CMD_BYTERD		; BYTE READ
+	CALL	CH_CMD			; SEND COMMAND
+	CALL	CH_NAP
+	LD	A,0			; LSB
+	CALL	CH_WR			; SEND IT
+	LD	A,2			; MSB
+	CALL	CH_WR			; SEND IT
+	CALL	CH_POLL			; GET RESULT
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CP	$1D			; DATA READY TO READ?
+	JP	NZ,CHSD_IOERR		; HANDLE I/O ERROR
+;
+	LD	HL,(CHSD_DSKBUF)
+CHSD_READ1:
+	CALL	CH_CMD_RD		; SEND READ USB DATA CMD
+	CALL	CH_RD			; GET DATA LENGTH
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+;
+#IF (CHSD_FASTIO)
+	LD	B,A			; BYTE COUNT TO READ
+	LD	C,(IY+CH_IOBASE)	; BASE PORT
+	INIR				; DO IT FAST
+#ELSE
+	LD	B,A			; SAVE IT
+CHSD_READ2:
+	CALL	CH_RD			; GET DATA BYTE
+	LD	(HL),A			; SAVE IN BUFFER
+	INC	HL			; INC BUF PTR
+	DJNZ	CHSD_READ2		; LOOP TILL DONE W/ ALL BYTES
+#ENDIF
+;
+	LD	A,CH_CMD_BYTERDGO	; BYTE READ GO COMMAND
+	CALL	CH_CMD			; SEND IT
+	CALL	CH_NAP
+	CALL	CH_POLL			; GET RESULT
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CP	$1D			; MORE?
+	JR	Z,CHSD_READ1		; IF SO, GET MORE
+	CP	$14			; GOOD FINISH?
+	JP	NZ,CHSD_IOERR		; HANDLE ERROR
+;
+	; INCREMENT LBA
+	PUSH	HL			; SAVE HL
+	LD	A,CHSD_LBA		; LBA OFFSET
+	CALL	LDHLIYA			; HL := IY + A, REG A TRASHED
+	CALL	INC32HL			; INCREMENT THE VALUE
+	POP	HL			; RESTORE HL
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+;
+;
+CHSD_WRITE:
+	LD	A,CH_MODE_SD		; REQUEST SD MODE
+	CALL	CH_SETMODE		; DO IT
+	JP	NZ,CHSD_CMDERR		; HANDLE ERROR
+;
+	CALL	HB_DSKWRITE		; HOOK HBIOS DISK WRITE SUPERVISOR
+	LD	(CHSD_DSKBUF),HL	; SAVE DISK BUFFER ADDRESS
+	CALL	CHSD_RWSTART		; SET LBA OFFSET'
+	RET	NZ
+;
+	;PRTS("\n\rWRITE:$")		; *DEBUG*
+	LD	A,CH_CMD_BYTEWR		; BYTE WRITE
+	CALL	CH_CMD			; SEND COMMAND
+	LD	A,0			; LSB
+	CALL	CH_WR			; SEND IT
+	LD	A,2			; MSB
+	CALL	CH_WR			; SEND IT
+	CALL	CH_POLL			; GET RESULT
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CP	$1E			; DATA READY TO GO?
+	JP	NZ,CHSD_IOERR		; HANDLE I/O ERROR
+;
+	LD	HL,(CHSD_DSKBUF)
+CHSD_WRITE1:
+	LD	A,CH_CMD_WRREQDAT	; WRITE REQUESTED DATA CMD
+	CALL	CH_CMD			; SEND IT
+	CALL	CH_RD			; GET DATA LENGTH
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+;
+#IF (CHSD_FASTIO)
+	LD	B,A			; BYTE COUNT TO WRITE
+	LD	C,(IY+CH_IOBASE)	; BASE PORT
+	OTIR				; DO IT FAST
+#ELSE
+	LD	B,A			; SAVE IT
+CHSD_WRITE2:
+	CALL	CH_WR			; WRITE DATA BYTE
+	LD	(HL),A			; SAVE IN BUFFER
+	INC	HL			; INC BUF PTR
+	DJNZ	CHSD_WRITE2		; LOOP TILL DONE W/ ALL BYTES
+#ENDIF
+;
+	LD	A,CH_CMD_BYTEWRGO	; BYTE WRITE GO COMMAND
+	CALL	CH_CMD			; SEND IT
+	CALL	CH_NAP
+	CALL	CH_POLL			; GET RESULT
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CP	$1E			; MORE?
+	JR	Z,CHSD_WRITE1		; IF SO, SEND MORE
+	CP	$14			; GOOD FINISH?
+	JP	NZ,CHSD_IOERR		; HANDLE ERROR
+;
+	; INCREMENT LBA
+	PUSH	HL			; SAVE HL
+	LD	A,CHSD_LBA		; LBA OFFSET
+	CALL	LDHLIYA			; HL := IY + A, REG A TRASHED
+	CALL	INC32HL			; INCREMENT THE VALUE
+	POP	HL			; RESTORE HL
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; SEEK TO CURRENT LBA
+;
+CHSD_RWSTART:
+	;PRTS("\n\rRWST:$")		; *DEBUG*
+	LD	A,CH_CMD_BYTE_LOC	; BYTE LOCATE COMMAND (SEEK)
+	CALL	CH_CMD			; SEND IT
+;
+	; GET CURRENT LBA OFFSET
+	LD	A,CHSD_LBA		; OFFSET TO CAPACITY FIELD
+	CALL	LDHLIYA			; HL := IY + A, REG A TRASHED
+	CALL	LD32			; OFFSET = DE:HL
+;
+	; CONVERT OFFSET FROM LBA TO BYTE
+	LD	B,9
+CHSD_RWSTART1:
+	SLA	L
+	RL	H
+	RL	E
+	RL	D
+	DJNZ	CHSD_RWSTART1
+	;CALL	PRTHEX32		; *DEBUG*
+;
+	; SEND THE BYTE OFFSET (LSB FIRST)
+	LD	A,L
+	CALL	CH_WR
+	LD	A,H
+	CALL	CH_WR
+	LD	A,E
+	CALL	CH_WR
+	LD	A,D
+	CALL	CH_WR
+;
+	CALL	CH_POLL			; WAIT FOR RESPONSE
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CP	$14			; CHECK RESULT
+	JP	NZ,CHSD_CMDERR		; HANDLE CMD ERROR
+;
+	XOR	A
+	RET
+;
+;
+;
+CHSD_STATUS:
+	; RETURN UNIT STATUS
+	LD	A,(IY+CHSD_STAT)	; GET STATUS OF SELECTED DEVICE
+	OR	A			; SET FLAGS
+	RET				; AND RETURN
+;
+; RESET THE INTERFACE AND REDISCOVER MEDIA
+;
+CHSD_RESET:
+	;PRTS("\n\rRES SD:$")		; *DEBUG*
+;
+	; ACTIVATE SD MODE
+	LD	A,CH_CMD_MODE		; SET MODE COMMAND
+	CALL	CH_CMD			; SEND IT
+	LD	A,3			; SD MODE
+	CALL	CH_WR			; SEND IT
+	CALL	CH_NAP			; SMALL WAIT
+	CALL	CH_RD			; GET RESULT
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CALL	CH_NAP			; SMALL WAIT
+;
+	LD	A,CH_MODE_SD		; WE ARE NOW IN SD MODE
+	LD	L,(IY+CHSD_MODE+0)	; GET MODE PTR (LSB)
+	LD	H,(IY+CHSD_MODE+1)	; GET MODE PTR (MSB)
+	LD	(HL),A			; SAVE IT
+;
+	CALL	CHSD_DSKMNT		; MOUNT DISK
+	RET	NZ
+;
+	; OPEN DISK IMAGE FILE
+	LD	DE,CHSD_FNAME
+	CALL	CHSD_FOPEN
+	RET	NZ
+;
+	; GET FILESIZE
+	CALL	CHSD_FILESIZE
+	RET	NZ
+;
+	; SET STATUS AND RETURN
+	XOR	A			; CLEAR STATUS
+	LD	(IY+CHSD_STAT),A	; RECORD STATUS
+	OR	A			; SET FLAGS
+	RET				; AND RETURN
+;
+;
+;
+CHSD_DEVICE:
+	LD	D,DIODEV_CHSD		; D := DEVICE TYPE
+	LD	E,(IY+CH_DEV)		; E := PHYSICAL DEVICE NUMBER
+	LD	C,%00110010		; SD HARD DISK ATTRIBUTES
+	LD	H,(IY+CH_TYPE)		; H := MODE
+	LD	L,(IY+CH_IOBASE)	; L := BASE I/O ADDRESS
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; CHSD_GETMED
+;
+CHSD_MEDIA:
+	LD	A,E			; GET FLAGS
+	OR	A			; SET FLAGS
+	JR	Z,CHSD_MEDIA1		; JUST REPORT CURRENT STATUS AND MEDIA
+	CALL	CHSD_RESET		; RESET CHSD INTERFACE
+;
+CHSD_MEDIA1:
+	LD	A,(IY+CHSD_STAT)	; GET STATUS
+	OR	A			; SET FLAGS
+	LD	D,0			; NO MEDIA CHANGE DETECTED
+	LD	E,MID_HD		; ASSUME WE ARE OK
+	RET	Z			; RETURN IF GOOD INIT
+	LD	E,MID_NONE		; SIGNAL NO MEDIA
+	LD	A,ERR_NOMEDIA		; NO MEDIA ERROR
+	OR	A			; SET FLAGS
+	RET				; AND RETURN
+;
+;
+;
+CHSD_SEEK:
+	BIT	7,D			; CHECK FOR LBA FLAG
+	CALL	Z,HB_CHS2LBA		; CLEAR MEANS CHS, CONVERT TO LBA
+	RES	7,D			; CLEAR FLAG REGARDLESS (DOES NO HARM IF ALREADY LBA)
+	LD	(IY+CHSD_LBA+0),L	; SAVE NEW LBA
+	LD	(IY+CHSD_LBA+1),H	; ...
+	LD	(IY+CHSD_LBA+2),E	; ...
+	LD	(IY+CHSD_LBA+3),D	; ...
+	XOR	A			; SIGNAL SUCCESS
+	RET				; AND RETURN
+;
+;
+;
+CHSD_CAP:
+	LD	A,(IY+CHSD_STAT)	; GET STATUS
+	PUSH	AF			; SAVE IT
+	LD	A,CHSD_MEDCAP		; OFFSET TO CAPACITY FIELD
+	CALL	LDHLIYA			; HL := IY + A, REG A TRASHED
+	CALL	LD32			; GET THE CURRENT CAPACITY INTO DE:HL
+	LD	BC,512			; 512 BYTES PER BLOCK
+	POP	AF			; RECOVER STATUS
+	OR	A			; SET FLAGS
+	RET
+;
+;
+;
+CHSD_GEOM:
+	; FOR LBA, WE SIMULATE CHS ACCESS USING 16 HEADS AND 16 SECTORS
+	; RETURN HS:CC -> DE:HL, SET HIGH BIT OF D TO INDICATE LBA CAPABLE
+	CALL	CHSD_CAP		; GET TOTAL BLOCKS IN DE:HL, BLOCK SIZE TO BC
+	LD	L,H			; DIVIDE BY 256 FOR # TRACKS
+	LD	H,E			; ... HIGH BYTE DISCARDED, RESULT IN HL
+	LD	D,16 | $80		; HEADS / CYL = 16, SET LBA CAPABILITY BIT
+	LD	E,16			; SECTORS / TRACK = 16
+	RET				; DONE, A STILL HAS CHSD_CAP STATUS
+;
+; CH37X HELPER ROUTINES
+;
+;
+; PERFORM DISK MOUNT
+;
+CHSD_DSKMNT:
+	;PRTS("\n\rMOUNT:$")		; *DEBUG*
+	LD	A,CH_CMD_DSKMNT		; DISK QUERY
+	CALL	CH_CMD			; DO IT
+	CALL	CH_POLL			; WAIT FOR RESPONSE
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CP	$82			; NO DISK?
+	JP	Z,CHSD_NOMEDIA		; HANDLE NO MEDIA ERROR
+	CP	$14			; SUCCESS?
+	JP	NZ,CHSD_CMDERR		; HANDLE ERROR
+;
+#IF FALSE
+	CALL	CH_CMD_RD		; SEND READ COMMAND
+	CALL	CH_RD			; GET LENGTH
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	LD	B,A			; LOOP COUNTER
+	LD	HL,HB_WRKBUF		; USE WORK BUFFER FOR DATA
+CHSD_DSKMNT1:
+	CALL	CH_RD			; GET A BYTE
+	LD	(HL),A			; SAVE IT
+	INC	HL			; BUMP BUF PTR
+	DJNZ	CHSD_DSKMNT1		; LOOP FOR ALL DATA
+;
+	;LD	DE,HB_WRKBUF		; *DEBUG*
+	;CALL	DUMP_BUFFER		; *DEBUG*
+;
+	CALL	CHSD_PRTPREFIX		; PRINT DEVICE PREFIX
+	LD	HL,HB_WRKBUF + 8
+	LD	B,28
+CHSD_DSKMNT2:
+	LD	A,(HL)
+	INC	HL
+	CALL	COUT
+	DJNZ	CHSD_DSKMNT2
+#ENDIF
+;
+	XOR	A
+	RET
+;
+; SET FILE NAME
+;
+CHSD_SETFNAME:
+	;PRTS("\n\rSETFNAME:$")		; *DEBUG*
+	LD	A,CH_CMD_SET_FN		; SET FILE NAME COMMAND
+	CALL	CH_CMD			; SEND IT
+	CALL	CH_NAP
+	;CALL	DELAY			; MAY NOT BE NEEDED
+	;CALL	PC_SPACE		; *DEBUG*
+CHSD_SETFNAME1:
+	;CALL	DELAY
+	LD	A,(DE)			; GET NEXT BYTE
+	INC	DE			; BUMP POINTER
+	CALL	CH_WR			; SEND IT
+	;CALL	COUT			; *DEBUG*
+	OR	A			; CHECK FOR NUL (EOS)
+	RET	Z			; IF NUL, DONE
+	JR	CHSD_SETFNAME1		; SEND MORE CHARACTERS
+;
+; OPEN FILE
+;
+CHSD_FOPEN:
+	CALL	CHSD_SETFNAME
+	;PRTS("\n\rFOPEN:$")		; *DEBUG*
+	LD	A,CH_CMD_FOPEN		; FILE OPEN  COMMAND
+	CALL	CH_CMD			; SEND IT
+	CALL	CH_POLL			; WAIT FOR RESULT
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CP	$42			; MISSING FILE?
+	JP	Z,CHSD_NOFILE		; HANDLE ERROR
+	CP	$14			; SUCCESS?
+	JP	NZ,CHSD_IOERR		; HANDLE ERROR
+	RET				; RETURN WITH ZF SET APPROPRIATELY
+;
+; GET FILE SIZE
+;
+CHSD_FILESIZE:
+	;PRTS("\n\rFSIZE:$")
+	LD	A,CH_CMD_FILESIZE	; FILE SIZE COMMAND
+	CALL	CH_CMD			; SEND IT
+	LD	A,$68			; REQUIRED CMD PARAMETER
+	CALL	CH_WR			; SEND IT
+	CALL	CH_NAP
+	LD	A,CHSD_MEDCAP		; MEDIA CAPACITY OFFSET
+	CALL	LDHLIYA			; HL := IY + A, REG A TRASHED
+	PUSH	HL			; SAVE ADDRESS
+	CALL	CH_RD
+	LD	L,A
+	CALL	CH_RD
+	LD	H,A
+	CALL	CH_RD
+	LD	E,A
+	CALL	CH_RD
+	LD	D,A
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEX32		; *DEBUG*
+	LD	B,9			; ROTATE 9 BITS FOR DIV 512
+CHSD_FILESIZE1:
+	SRL	D
+	RR	E
+	RR	H
+	RR	L
+	DJNZ	CHSD_FILESIZE1		; LOOP TILL DONE
+	POP	BC			; RECOVER ADDRESS TO BC
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEX32		; *DEBUG*
+	CALL	ST32			; STORE IT
+	XOR	A			; SIGNAL SUCCESS
+	RET				; AND DONE
+;
+; ERROR HANDLERS
+;
+;
+CHSD_NOFILE:
+	LD	A,CHSD_STNOFILE
+	JR	CHSD_ERR
+;
+CHSD_NOMEDIA:
+	LD	A,CHSD_STNOMEDIA
+	JR	CHSD_ERR
+;
+CHSD_CMDERR:
+	LD	A,CHSD_STCMDERR
+	JR	CHSD_ERR
+;
+CHSD_IOERR:
+	LD	A,CHSD_STIOERR
+	JR	CHSD_ERR
+;
+CHSD_TO:
+	LD	A,CHSD_STTO
+	JR	CHSD_ERR
+;
+CHSD_NOTSUP:
+	LD	A,CHSD_STNOTSUP
+	JR	CHSD_ERR
+;
+CHSD_ERR:
+	LD	(IY+CHSD_STAT),A	; SAVE NEW STATUS
+;
+CHSD_ERR2:
+#IF (CHSDTRACE >= 2)
+	CALL	CHSD_PRTSTAT
+#ENDIF
+	OR	A			; SET FLAGS
+	RET
+;
+;
+;
+CHSD_PRTERR:
+	RET	Z			; DONE IF NO ERRORS
+	; FALL THRU TO CHSD_PRTSTAT
+;
+; PRINT FULL DEVICE STATUS LINE
+;
+CHSD_PRTSTAT:
+	PUSH	AF
+	PUSH	DE
+	PUSH	HL
+	LD	A,(IY+CHSD_STAT)
+	CALL	CHSD_PRTPREFIX		; PRINT UNIT PREFIX
+	CALL	PC_SPACE		; FORMATTING
+	CALL	CHSD_PRTSTATSTR
+	POP	HL
+	POP	DE
+	POP	AF
+	RET
+;
+; PRINT STATUS STRING
+;
+CHSD_PRTSTATSTR:
+	PUSH	AF
+	PUSH	DE
+	PUSH	HL
+	LD	A,(IY+CHSD_STAT)
+	NEG
+	LD	HL,CHSD_STR_ST_MAP
+	ADD	A,A
+	CALL	ADDHLA
+	LD	E,(HL)
+	INC	HL
+	LD	D,(HL)
+	CALL	WRITESTR
+	POP	HL
+	POP	DE
+	POP	AF
+	RET
+;
+; PRINT DIAGNONSTIC PREFIX
+;
+CHSD_PRTPREFIX:
+	PUSH	AF
+	CALL	NEWLINE
+	PRTS("CHSD$")
+	LD	A,(IY+CH_DEV)		; GET CURRENT DEVICE NUM
+	CALL	PRTDECB
+	CALL	PC_COLON
+	POP	AF
+	RET
+;
+; DATA STORAGE
+;
+CHSD_DEVNUM	.DB	0		; TEMP DEVICE NUM USED DURING INIT
+CHSD_DSKBUF	.DW	0
+;
+CHSD_FNAME	.DB	"/", CHSD_IMGFILE, 0
+;
+CHSD_STR_ST_MAP:
+	.DW		CHSD_STR_STOK
+	.DW		CHSD_STR_STNOMEDIA
+	.DW		CHSD_STR_STCMDERR
+	.DW		CHSD_STR_STIOERR
+	.DW		CHSD_STR_STTO
+	.DW		CHSD_STR_STNOTSUP
+	.DW		CHSD_STR_STNOFILE
+;
+CHSD_STR_STOK		.TEXT	"OK$"
+CHSD_STR_STNOMEDIA	.TEXT	"NO MEDIA$"
+CHSD_STR_STCMDERR	.TEXT	"COMMAND ERROR$"
+CHSD_STR_STIOERR	.TEXT	"IO ERROR$"
+CHSD_STR_STTO		.TEXT	"TIMEOUT$"
+CHSD_STR_STNOTSUP	.TEXT	"NOT SUPPORTED$"
+CHSD_STR_STNOFILE	.TEXT	"MISSING "
+			.TEXT	CHSD_IMGFILE
+			.TEXT	" FILE$"
+CHSD_STR_STUNK		.TEXT	"UNKNOWN ERROR$"

Source/HBIOS/chusb.asm

@@ -0,0 +1,792 @@
+;
+;==================================================================================================
+; CH375/376 USB SUB-DRIVER
+;==================================================================================================
+;
+; Thanks and credit to Alan Cox.  Much of this driver is based on
+; his code in FUZIX (https://github.com/EtchedPixels/FUZIX).
+;
+; This file contains the USB Drive specific support for the CH37x
+; driver.  This file is included by the core driver file (ch.asm) as
+; needed.
+;
+; The USB support is implemented as pure raw sector I/O.  The CH376
+; file-level support is not utilized.
+;
+; NOTES:
+;  - There seem to be compatibility issues with older USB thumb drives.
+;    Such drives will complete DISK_INIT successfully, but then return
+;    an error attempting to do any I/O.  The error is $17 indicating
+;    the CH37x encountered an overflow during communication with the
+;    device.   I found that adding a DISK_MOUNT command (only possible
+;    on CH376) resolved the issue for some devices, so that has been
+;    added to the RESET routine when using CH376.
+;
+; TODO:
+;  - Implement auto-recovery on error status?
+;
+CHUSB_FASTIO	.EQU	TRUE		; USE INIR/OTIR?
+;
+; CHUSB DEVICE STATUS
+;
+CHUSB_STOK	.EQU	0
+CHUSB_STNOMEDIA	.EQU	-1
+CHUSB_STCMDERR	.EQU	-2
+CHUSB_STIOERR	.EQU	-3
+CHUSB_STTO	.EQU	-4
+CHUSB_STNOTSUP	.EQU	-5
+;
+; CHUSB DEVICE CONFIGURATION
+;
+CHUSB_CFGSIZ	.EQU	14		; SIZE OF USB CFG TBL ENTRIES
+;
+; CONFIG ENTRY DATA OFFSETS
+;
+; THE LOCATION OF CHSD_MODE IS SHARED BY ALL SUB-DRIVERS AND THE
+; CH_SETMODE FUNCTION IN THE MAIN DRIVER (CH.ASM).  IF YOU CHANGE
+; IT, YOU MUST SYNC UP THE MAIN DRIVER AND ALL SUB-DRIVERS!
+;
+; FIRST 3 BYTES SAME AS CH CONFIG
+CHUSB_STAT	.EQU	3		; LAST STATUS (BYTE)
+CHUSB_MEDCAP	.EQU	4		; MEDIA CAPACITY (DWORD)
+CHUSB_LBA	.EQU	8		; CURRENT LBA (DWORD)
+CHUSB_MODE	.EQU	12		; PTR TO MODE BYTE (WORD)
+;
+CHUSB_CFGTBL:
+;
+#IF (CHCNT >= 1)
+CHUSB_CFG0:
+	.DB	0			; DEV NUM, FILLED DYNAMICALLY
+	.DB	CHTYP_NONE		; DEV TYPE, FILLED DYNCAMICALLY
+	.DB	CH0BASE			; IO BASE ADDRESS
+	.DB	0			; DEVICE STATUS
+	.DW	0,0			; DEVICE CAPACITY
+	.DW	0,0			; CURRENT LBA
+	.DW	CH0_MODE		; POINTER TO MODE BYTE
+;
+  #IF (CH0USBENABLE)
+	.ECHO	"CHUSB: IO="
+	.ECHO	CH0BASE
+	.ECHO	"\n"
+  #ENDIF
+#ENDIF
+;
+#IF (CHCNT >= 2)
+CHUSB_CFG1:
+	.DB	0			; DEV NUM
+	.DB	CHTYP_NONE		; DEV TYPE, FILLED DYNCAMICALLY
+	.DB	CH1BASE			; IO BASE ADDRESS
+	.DB	0			; DEVICE STATUS
+	.DW	0,0			; DEVICE CAPACITY
+	.DW	0,0			; CURRENT LBA
+	.DW	CH1_MODE		; POINTER TO MODE BYTE
+;
+  #IF (CH1USBENABLE)
+	.ECHO	"CHUSB: IO="
+	.ECHO	CH1BASE
+	.ECHO	"\n"
+  #ENDIF
+#ENDIF
+;
+#IF ($ - CHUSB_CFGTBL) != (CHCNT * CHUSB_CFGSIZ)
+	.ECHO	"*** INVALID CHUSB CONFIG TABLE ***\n"
+#ENDIF
+;
+	.DB	$FF			; END OF TABLE MARKER
+;
+;
+;
+CHUSB_INIT:
+	LD	A,(IY+CH_TYPE)		; GET DEVICE TYPE
+	PUSH	HL			; COPY INCOMING HL
+	POP	IY			; ... TO IY
+	LD	(IY+CH_TYPE),A		; SAVE DEVICE TYPE
+;
+	; UPDATE DRIVER RELATIVE UNIT NUMBER IN CONFIG TABLE
+	LD	A,(CHUSB_DEVNUM)	; GET NEXT UNIT NUM TO ASSIGN
+	LD	(IY+CH_DEV),A		; UPDATE IT
+	INC	A			; BUMP TO NEXT UNIT NUM TO ASSIGN
+	LD	(CHUSB_DEVNUM),A	; SAVE IT
+;
+	; ADD UNIT TO GLOBAL DISK UNIT TABLE
+	LD	BC,CHUSB_FNTBL		; BC := FUNC TABLE ADR
+	PUSH	IY			; CFG ENTRY POINTER
+	POP	DE			; COPY TO DE
+	CALL	DIO_ADDENT		; ADD ENTRY TO GLOBAL DISK DEV TABLE
+;
+	CALL	CHUSB_RESET		; RESET & DISCOVER MEDIA
+#IF (CHUSBTRACE <= 1)
+	CALL	NZ,CHUSB_PRTSTAT
+#ENDIF
+	RET	NZ			; ABORT ON FAILURE
+;
+	; START PRINTING DEVICE INFO
+	CALL	CHUSB_PRTPREFIX		; PRINT DEVICE PREFIX
+;
+	; PRINT STORAGE CAPACITY (BLOCK COUNT)
+	PRTS(" BLOCKS=0x$")		; PRINT FIELD LABEL
+	LD	A,CHUSB_MEDCAP		; OFFSET TO CAPACITY FIELD
+	CALL	LDHLIYA			; HL := IY + A, REG A TRASHED
+	CALL	LD32			; GET THE CAPACITY VALUE
+	CALL	PRTHEX32		; PRINT HEX VALUE
+;
+	; PRINT STORAGE SIZE IN MB
+	PRTS(" SIZE=$")			; PRINT FIELD LABEL
+	LD	B,11			; 11 BIT SHIFT TO CONVERT BLOCKS --> MB
+	CALL	SRL32			; RIGHT SHIFT
+	CALL	PRTDEC32		; PRINT DWORD IN DECIMAL
+	PRTS("MB$")			; PRINT SUFFIX
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; DRIVER FUNCTION TABLE
+;
+CHUSB_FNTBL:
+	.DW	CHUSB_STATUS
+	.DW	CHUSB_RESET
+	.DW	CHUSB_SEEK
+	.DW	CHUSB_READ
+	.DW	CHUSB_WRITE
+	.DW	CHUSB_VERIFY
+	.DW	CHUSB_FORMAT
+	.DW	CHUSB_DEVICE
+	.DW	CHUSB_MEDIA
+	.DW	CHUSB_DEFMED
+	.DW	CHUSB_CAP
+	.DW	CHUSB_GEOM
+#IF (($ - CHUSB_FNTBL) != (DIO_FNCNT * 2))
+	.ECHO	"*** INVALID CHUSB FUNCTION TABLE ***\n"
+#ENDIF
+;
+CHUSB_VERIFY:
+CHUSB_FORMAT:
+CHUSB_DEFMED:
+	SYSCHKERR(ERR_NOTIMPL)		; NOT IMPLEMENTED
+	RET
+;
+;
+;
+CHUSB_READ:
+	LD	A,CH_MODE_USB		; REQUEST USB MODE
+	CALL	CH_SETMODE		; DO IT
+	JP	NZ,CHUSB_CMDERR		; HANDLE ERROR
+;
+	CALL	HB_DSKREAD		; HOOK HBIOS DISK READ SUPERVISOR
+	LD	(CHUSB_DSKBUF),HL	; SAVE DISK BUFFER ADDRESS
+	LD	A,CH_CMD_DSKRD		; DISK READ COMMAND
+	CALL	CHUSB_RWSTART		; SEND CMD AND LBA
+;
+	; READ THE SECTOR IN 64 BYTE CHUNKS
+	LD	B,8			; 8 CHUNKS OF 64 FOR 512 BYTE SECTOR
+	LD	HL,(CHUSB_DSKBUF)	; GET DISK BUF ADR
+CHUSB_READ1:
+	CALL	CH_POLL			; WAIT FOR DATA READY
+	CP	$1D			; DATA READY TO READ?
+	;CALL	PC_LT			; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	JP	NZ,CHUSB_IOERR		; HANDLE IO ERROR
+	CALL	CH_CMD_RD		; SEND READ USB DATA CMD
+	CALL	CH_RD			; READ DATA BLOCK LENGTH
+	CP	64			; AS EXPECTED?
+	JP	NZ,CHUSB_IOERR		; IF NOT, HANDLE ERROR
+;
+#IF (CHUSB_FASTIO)
+	; READ 64 BYTE CHUNK
+	PUSH	BC			; SAVE LOOP CONTROL
+	LD	B,64			; READ 64 BYTES
+	LD	C,(IY+CH_IOBASE)	; BASE PORT
+	INIR				; DO IT FAST
+	POP	BC			; RESTORE LOOP CONTROL
+#ELSE
+	; BYTE READ LOOP
+	PUSH	BC			; SAVE LOOP CONTROL
+	LD	B,64			; READ 64 BYTES
+CHUSB_READ2:
+	CALL	CH_RD			; GET NEXT BYTE
+	LD	(HL),A			; SAVE IT
+	INC	HL			; INC BUF PTR
+	DJNZ	CHUSB_READ2		; LOOP AS NEEDED
+	POP	BC			; RESTORE LOOP CONTROL
+#ENDIF
+;
+	; PREPARE FOR NEXT CHUNK
+	LD	A,CH_CMD_DSKRDGO	; CONTINUE DISK READ
+	CALL	CH_CMD			; SEND IT
+	DJNZ	CHUSB_READ1		; LOOP TILL DONE
+;
+	; FINAL CHECK FOR COMPLETION & SUCCESS
+	CALL	CH_POLL			; WAIT FOR COMPLETION
+	CP	$14			; SUCCESS?
+	JP	NZ,CHUSB_IOERR		; IF NOT, HANDLE ERROR
+;
+	; INCREMENT LBA
+	PUSH	HL			; SAVE HL
+	LD	A,CHUSB_LBA		; LBA OFFSET
+	CALL	LDHLIYA			; HL := IY + A, REG A TRASHED
+	CALL	INC32HL			; INCREMENT THE VALUE
+	POP	HL			; RESTORE HL
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+;
+;
+CHUSB_WRITE:
+	LD	A,CH_MODE_USB		; REQUEST USB MODE
+	CALL	CH_SETMODE		; DO IT
+	JP	NZ,CHUSB_CMDERR		; HANDLE ERROR
+;
+	CALL	HB_DSKWRITE		; HOOK HBIOS DISK WRITE SUPERVISOR
+	LD	(CHUSB_DSKBUF),HL	; SAVE DISK BUFFER ADDRESS
+	LD	A,CH_CMD_DSKWR		; DISK READ COMMAND
+	CALL	CHUSB_RWSTART		; SEND CMD AND LBA
+;
+	; WRITE THE SECTOR IN 64 BYTE CHUNKS
+	LD	B,8			; 8 CHUNKS OF 64 FOR 512 BYTE SECTOR
+	LD	HL,(CHUSB_DSKBUF)	; GET DISK BUF ADR
+CHUSB_WRITE1:
+	CALL	CH_POLL			; WAIT FOR DATA READY
+	CP	$1E			; DATA READY TO WRITE
+	;CALL	PC_GT			; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	JP	NZ,CHUSB_IOERR		; HANDLE IO ERROR
+	CALL	CH_CMD_WR		; SEND WRITE USB DATA CMD
+	LD	A,64			; 64 BYTE CHUNK
+	CALL	CH_WR			; SEND DATA BLOCK LENGTH
+;
+#IF (CHUSB_FASTIO)
+	; WRITE 64 BYTE CHUNK
+	PUSH	BC			; SAVE LOOP CONTROL
+	LD	B,64			; WRITE 64 BYTES
+	LD	C,(IY+CH_IOBASE)	; BASE PORT
+	OTIR				; DO IT FAST
+	POP	BC			; RESTORE LOOP CONTROL
+#ELSE
+	; BYTE WRITE LOOP
+	PUSH	BC			; SAVE LOOP CONTROL
+	LD	B,64			; WRITE 64 BYTES
+CHUSB_WRITE2:
+	LD	A,(HL)			; GET NEXT BYTE
+	INC	HL			; INC BUF PTR
+	CALL	CH_WR			; WRITE NEXT BYTE
+	DJNZ	CHUSB_WRITE2		; LOOP AS NEEDED
+	POP	BC			; RESTORE LOOP CONTROL
+#ENDIF
+;
+	; PREPARE FOR NEXT CHUNK
+	LD	A,CH_CMD_DSKWRGO	; CONTINUE DISK READ
+	CALL	CH_CMD			; SEND IT
+	DJNZ	CHUSB_WRITE1		; LOOP TILL DONE
+;
+	; FINAL CHECK FOR COMPLETION & SUCCESS
+	CALL	CH_POLL			; WAIT FOR COMPLETION
+	CP	$14			; SUCCESS?
+	JP	NZ,CHUSB_IOERR		; IF NOT, HANDLE ERROR
+;
+	; INCREMENT LBA
+	PUSH	HL			; SAVE HL
+	LD	A,CHUSB_LBA		; LBA OFFSET
+	CALL	LDHLIYA			; HL := IY + A, REG A TRASHED
+	CALL	INC32HL			; INCREMENT THE VALUE
+	POP	HL			; RESTORE HL
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; INITIATE A DISK SECTOR READ/WRITE OPERATION
+; A: READ OR WRITE OPCODE
+;
+CHUSB_RWSTART:
+	CALL	CH_CMD			; SEND R/W COMMAND
+;
+	; SEND LBA, 4 BYTES, LITTLE ENDIAN
+	LD	A,CHUSB_LBA		; OFFSET TO CAPACITY FIELD
+	CALL	LDHLIYA			; HL := IY + A, REG A TRASHED
+	LD	B,4			; SEND 4 BYTES
+CHUSB_RWSTART1:
+	LD	A,(HL)			; GET BYTE
+	INC	HL			; BUMP PTR
+	CALL	CH_WR			; SEND BYTE
+	DJNZ	CHUSB_RWSTART1		; LOOP AS NEEDED
+;
+	; REQUEST 1 SECTOR
+	LD	A,1			; 1 SECTOR
+	CALL	CH_WR			; SEND IT
+	RET
+;
+;
+;
+CHUSB_STATUS:
+	; RETURN UNIT STATUS
+	LD	A,(IY+CHUSB_STAT)	; GET STATUS OF SELECTED DEVICE
+	OR	A			; SET FLAGS
+	RET				; AND RETURN
+;
+; RESET THE INTERFACE AND REDISCOVER MEDIA
+;
+CHUSB_RESET:
+	;PRTS("\n\rRES USB:$")		; *DEBUG*
+	;CALL	CH_FLUSH		; DISCARD ANY GARBAGE
+	;CALL	CH_RESET		; FULL CH37X RESET
+;
+	; RESET THE BUS
+	LD	A,CH_CMD_MODE		; SET MODE COMMAND
+	CALL	CH_CMD			; SEND IT
+	LD	A,7			; RESET BUS
+	CALL	CH_WR			; SEND IT
+	CALL	CH_NAP			; SMALL WAIT
+	CALL	CH_RD			; GET RESULT
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CALL	CH_NAP			; SMALL WAIT
+;
+	; ACTIVATE USB MODE
+	LD	A,CH_CMD_MODE		; SET MODE COMMAND
+	CALL	CH_CMD			; SEND IT
+	LD	A,6			; USB ENABLED, SEND SOF
+	CALL	CH_WR			; SEND IT
+	CALL	CH_NAP			; SMALL WAIT
+	CALL	CH_RD			; GET RESULT
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CALL	CH_NAP			; SMALL WAIT
+;
+	LD	A,CH_MODE_USB		; WE ARE NOW IN USB MODE
+	LD	L,(IY+CHUSB_MODE+0)	; GET MODE PTR (LSB)
+	LD	H,(IY+CHUSB_MODE+1)	; GET MODE PTR (MSB)
+	LD	(HL),A			; SAVE IT
+;
+	; INITIALIZE DISK
+	LD	B,24			; TRY A FEW TIMES
+CHUSB_RESET1:
+	;PRTS("\n\rDSKINIT:$")		; *DEBUG*
+	LD	A,CH_CMD_DSKINIT	; DISK INIT COMMAND
+	CALL	CH_CMD			; SEND IT
+	LD	DE,10000		; 10000 * 16 = 160US ???
+	LD	DE,20000		; 10000 * 16 = 160US ???
+	LD	DE,12500		; 1250 * 16 = 200US ???
+	CALL	VDELAY			; DELAY
+	CALL	CH_POLL			; WAIT FOR RESULT
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CP	$14			; SUCCESS?
+	JR	Z,CHUSB_RESET1A		; IF SO, CHECK READY
+	CP	$16			; NO MEDIA
+	JP	Z,CHUSB_NOMEDIA		; HANDLE IT
+	CALL	CH_NAP			; SMALL DELAY
+	DJNZ	CHUSB_RESET1		; LOOP AS NEEDED
+	JP	CHUSB_TO		; HANDLE TIMEOUT
+;
+CHUSB_RESET1A:
+	;CALL	CHUSB_DSKRES		; DISK RESET
+	;CP	$14			; GOOD?
+	;JR	Z,CHUSB_RESET2
+	;CALL	CHUSB_DSKRDY		; CHECK IF DISK READY
+	;CP	$14			; GOOD?
+	;JR	Z,CHUSB_RESET2		; IF SO, MOVE ON
+	;DJNZ	CHUSB_RESET1		; KEEP TRYING
+;
+CHUSB_RESET2:
+	; USE OF CH376 DISK_MOUNT COMMAND SEEMS TO IMPROVE
+	; COMPATIBILITY WITH SOME OLDER USB THUMBDRIVES.
+	LD	A,(IY+CH_TYPE)		; CH37X TYPE?
+	CP	CHTYP_376		; IS CH376?
+	CALL	Z,CHUSB_DSKMNT		; IF SO, TRY MOUNT, IGNORE ERRS
+	;CALL	CHUSB_AUTOSET		; *DEBUG*
+	;CALL	CHUSB_TSTCON		; *DEBUG*
+	;CALL	CHUSB_MAXLUN		; *DEBUG*
+	;CALL	CHUSB_DSKRDY		; *DEBUG*
+	;CALL	CHUSB_DSKINQ		; *DEBUG*
+;;
+	CALL	CHUSB_DSKSIZ		; GET AND RECORD DISK SIZE
+	RET	NZ			; ABORT ON ERROR
+;
+	; SET STATUS AND RETURN
+	XOR	A			; CLEAR STATUS
+	LD	(IY+CHUSB_STAT),A	; RECORD STATUS
+	OR	A			; SET FLAGS
+	RET				; AND RETURN
+;
+;
+;
+CHUSB_DEVICE:
+	LD	D,DIODEV_CHUSB		; D := DEVICE TYPE
+	LD	E,(IY+CH_DEV)		; E := PHYSICAL DEVICE NUMBER
+	LD	C,%00110011		; USB HARD DISK ATTRIBUTES
+	LD	H,(IY+CH_TYPE)		; H := MODE
+	LD	L,(IY+CH_IOBASE)	; L := BASE I/O ADDRESS
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; CHUSB_GETMED
+;
+CHUSB_MEDIA:
+	LD	A,E			; GET FLAGS
+	OR	A			; SET FLAGS
+	JR	Z,CHUSB_MEDIA1		; JUST REPORT CURRENT STATUS AND MEDIA
+	CALL	CHUSB_RESET		; RESET CHUSB INTERFACE
+;
+CHUSB_MEDIA1:
+	LD	A,(IY+CHUSB_STAT)	; GET STATUS
+	OR	A			; SET FLAGS
+	LD	D,0			; NO MEDIA CHANGE DETECTED
+	LD	E,MID_HD		; ASSUME WE ARE OK
+	RET	Z			; RETURN IF GOOD INIT
+	LD	E,MID_NONE		; SIGNAL NO MEDIA
+	LD	A,ERR_NOMEDIA		; NO MEDIA ERROR
+	OR	A			; SET FLAGS
+	RET				; AND RETURN
+;
+;
+;
+CHUSB_SEEK:
+	BIT	7,D			; CHECK FOR LBA FLAG
+	CALL	Z,HB_CHS2LBA		; CLEAR MEANS CHS, CONVERT TO LBA
+	RES	7,D			; CLEAR FLAG REGARDLESS (DOES NO HARM IF ALREADY LBA)
+	LD	(IY+CHUSB_LBA+0),L	; SAVE NEW LBA
+	LD	(IY+CHUSB_LBA+1),H	; ...
+	LD	(IY+CHUSB_LBA+2),E	; ...
+	LD	(IY+CHUSB_LBA+3),D	; ...
+	XOR	A			; SIGNAL SUCCESS
+	RET				; AND RETURN
+;
+;
+;
+CHUSB_CAP:
+	LD	A,(IY+CHUSB_STAT)	; GET STATUS
+	PUSH	AF			; SAVE IT
+	LD	A,CHUSB_MEDCAP		; OFFSET TO CAPACITY FIELD
+	CALL	LDHLIYA			; HL := IY + A, REG A TRASHED
+	CALL	LD32			; GET THE CURRENT CAPACITY INTO DE:HL
+	LD	BC,512			; 512 BYTES PER BLOCK
+	POP	AF			; RECOVER STATUS
+	OR	A			; SET FLAGS
+	RET
+;
+;
+;
+CHUSB_GEOM:
+	; FOR LBA, WE SIMULATE CHS ACCESS USING 16 HEADS AND 16 SECTORS
+	; RETURN HS:CC -> DE:HL, SET HIGH BIT OF D TO INDICATE LBA CAPABLE
+	CALL	CHUSB_CAP		; GET TOTAL BLOCKS IN DE:HL, BLOCK SIZE TO BC
+	LD	L,H			; DIVIDE BY 256 FOR # TRACKS
+	LD	H,E			; ... HIGH BYTE DISCARDED, RESULT IN HL
+	LD	D,16 | $80		; HEADS / CYL = 16, SET LBA CAPABILITY BIT
+	LD	E,16			; SECTORS / TRACK = 16
+	RET				; DONE, A STILL HAS CHUSB_CAP STATUS
+;
+; CH37X HELPER ROUTINES
+;
+;
+; PERFORM DISK MOUNT
+;
+CHUSB_DSKMNT:
+	;PRTS("\n\rMOUNT:$")		; *DEBUG*
+	LD	A,CH_CMD_DSKMNT		; DISK QUERY
+	CALL	CH_CMD			; DO IT
+	CALL	CH_POLL			; WAIT FOR RESPONSE
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CP	$14			; SUCCESS?
+	RET	NZ			; ABORT IF NOT
+;
+#IF FALSE
+	CALL	CH_CMD_RD		; SEND READ COMMAND
+	CALL	CH_RD			; GET LENGTH
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	LD	B,A			; LOOP COUNTER
+	LD	HL,HB_WRKBUF		; USE WORK BUFFER FOR DATA
+CHUSB_DSKMNT1:
+	CALL	CH_RD			; GET A BYTE
+	LD	(HL),A			; SAVE IT
+	INC	HL			; BUMP BUF PTR
+	DJNZ	CHUSB_DSKMNT1		; LOOP FOR ALL DATA
+;
+	;LD	DE,HB_WRKBUF		; *DEBUG*
+	;CALL	DUMP_BUFFER		; *DEBUG*
+;
+	CALL	CHUSB_PRTPREFIX		; PRINT DEVICE PREFIX
+	LD	HL,HB_WRKBUF + 8
+	LD	B,28
+CHUSB_DSKMNT2:
+	LD	A,(HL)
+	INC	HL
+	CALL	COUT
+	DJNZ	CHUSB_DSKMNT2
+#ENDIF
+;
+	XOR	A
+	RET
+;
+; PERFORM DISK SIZE
+;
+CHUSB_DSKSIZ:
+	;PRTS("\n\rDSKSIZ:$")		; *DEBUG*
+	LD	A,CH_CMD_DSKSIZ		; DISK SIZE COMMAND
+	CALL	CH_CMD			; SEND IT
+	CALL	CH_POLL			; WAIT FOR RESULT
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CP	$14			; SUCCESS?
+	JP	NZ,CHUSB_CMDERR		; HANDLE CMD ERROR
+	CALL	CH_CMD_RD		; SEND READ USB DATA CMD
+	CALL	CH_RD			; GET RD DATA LEN
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CP	$08			; MAKE SURE IT IS 8
+	JP	NZ,CHUSB_CMDERR		; HANDLE CMD ERROR
+	LD	A,CHUSB_MEDCAP		; MEDIA CAPACITY OFFSET
+	CALL	LDHLIYA			; HL := IY + A, REG A TRASHED
+	PUSH	HL			; SAVE ADDRESS
+	CALL	CH_RD
+	LD	D,A
+	CALL	CH_RD
+	LD	E,A
+	CALL	CH_RD
+	LD	H,A
+	CALL	CH_RD
+	LD	L,A
+	CALL	CH_RD
+	CALL	CH_RD
+	CALL	CH_RD
+	CALL	CH_RD
+	POP	BC			; RECOVER ADDRESS TO BC
+	CALL	ST32			; STORE IT
+	XOR	A			; SIGNAL SUCCESS
+	RET				; AND DONE
+;
+#IF FALSE
+;
+; PERFORM DISK INQUIRY
+; BASICALLY THE SCSI INQUIRY COMMAND
+;
+CHUSB_DSKINQ:
+	;PRTS("\n\rINQUIRY:$")		; *DEBUG*
+	LD	A,CH_CMD_DSKINQ		; DISK QUERY
+	CALL	CH_CMD			; DO IT
+	CALL	CH_POLL			; WAIT FOR RESPONSE
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CP	$14			; SUCCESS?
+	RET	NZ			; ABORT IF NOT
+	CALL	CH_CMD_RD		; SEND READ COMMAND
+	CALL	CH_RD			; GET LENGTH
+	LD	B,A			; LOOP COUNTER
+	LD	HL,HB_WRKBUF		; USE WORK BUFFER FOR DATA
+DSKINQ1:
+	CALL	CH_RD			; GET A BYTE
+	LD	(HL),A			; SAVE IT
+	INC	HL			; BUMP BUF PTR
+	DJNZ	DSKINQ1			; LOOP FOR ALL DATA
+;
+	;LD	DE,HB_WRKBUF		; *DEBUG*
+	;CALL	DUMP_BUFFER		; *DEBUG*
+;
+	;CALL	CHUSB_PRTPREFIX		; PRINT DEVICE PREFIX
+	;LD	HL,HB_WRKBUF + 8
+	;LD	B,28
+DSKINQ2:
+	;LD	A,(HL)
+	;INC	HL
+	;CALL	COUT
+	;DJNZ	DSKINQ2
+;
+	RET
+;
+; PERFORM SET RETRIES
+;
+CHUSB_SETRETRY:
+	;PRTS("\n\rSETRETRY:$")		; *DEBUG*
+	LD	A,CH_CMD_SETRETRY	; DISK READY
+	CALL	CH_CMD			; DO IT
+	CALL	CH_NAP
+	LD	A,$25			; CONSTANT
+	CALL	CH_WR			; SEND IT
+	CALL	CH_NAP
+	LD	A,$BF			; MAX
+	CALL	CH_WR
+	CALL	CH_NAP
+	CALL	CH_RD			; GET RESULT
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+;
+	RET
+;
+; PERFORM DISK RESET
+;
+CHUSB_DSKRES:
+	;PRTS("\n\rDSKRES:$")		; *DEBUG*
+	LD	A,CH_CMD_DSKRES		; DISK READY
+	CALL	CH_CMD			; DO IT
+	CALL	CH_POLL			; WAIT FOR RESPONSE
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+;
+	RET
+;
+; PERFORM DISK READY
+;
+CHUSB_DSKRDY:
+	;PRTS("\n\rDSKRDY:$")		; *DEBUG*
+	LD	A,CH_CMD_DSKRDY		; DISK READY
+	CALL	CH_CMD			; DO IT
+	CALL	CH_POLL			; WAIT FOR RESPONSE
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CP	$14			; *DEBUG*
+	JR	NZ,CHUSB_DSKRDY		; *DEBUG*
+;
+	RET
+;
+; PERFORM AUTO SETUP
+;
+CHUSB_AUTOSET:
+	;PRTS("\n\rAUTOSET:$")		; *DEBUG*
+	LD	A,CH_CMD_AUTOSET	; AUTOMATIC SETUP FOR USB
+	CALL	CH_CMD			; DO IT
+	CALL	LDELAY			; *DEBUG*
+	CALL	CH_POLL			; WAIT FOR RESPONSE
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+;
+	RET
+;
+; PERFORM TEST CONNECT
+;
+CHUSB_TSTCON:
+	;PRTS("\n\rTSTCON:$")		; *DEBUG*
+	LD	A,CH_CMD_TSTCON		; TEST USB DEVICE CONNECT
+	CALL	CH_CMD			; DO IT
+	CALL	CH_NAP			; WAIT A BIT
+	CALL	CH_RD			; GET RESPONSE
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+;
+	RET
+;
+; PERFORM GET MAX LUN
+;
+CHUSB_MAXLUN:
+	;PRTS("\n\rMAXLUN:$")		; *DEBUG*
+	LD	A,CH_CMD_MAXLUN		; TEST USB DEVICE CONNECT
+	CALL	CH_CMD			; DO IT
+	CALL	CH_NAP			; WAIT A BIT
+	LD	A,$38			; CONSTANT
+	CALL	CH_WR			; SEND IT
+	CALL	CH_NAP
+	CALL	CH_RD			; GET RESPONSE
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+;
+	RET
+;
+#ENDIF
+;
+; ERROR HANDLERS
+;
+;
+CHUSB_NOMEDIA:
+	LD	A,CHUSB_STNOMEDIA
+	JR	CHUSB_ERR
+;
+CHUSB_CMDERR:
+	LD	A,CHUSB_STCMDERR
+	JR	CHUSB_ERR
+;
+CHUSB_IOERR:
+	LD	A,CHUSB_STIOERR
+	JR	CHUSB_ERR
+;
+CHUSB_TO:
+	LD	A,CHUSB_STTO
+	JR	CHUSB_ERR
+;
+CHUSB_NOTSUP:
+	LD	A,CHUSB_STNOTSUP
+	JR	CHUSB_ERR
+;
+CHUSB_ERR:
+	LD	(IY+CHUSB_STAT),A	; SAVE NEW STATUS
+;
+CHUSB_ERR2:
+#IF (CHUSBTRACE >= 2)
+	CALL	CHUSB_PRTSTAT
+#ENDIF
+	OR	A			; SET FLAGS
+	RET
+;
+;
+;
+CHUSB_PRTERR:
+	RET	Z			; DONE IF NO ERRORS
+	; FALL THRU TO CHUSB_PRTSTAT
+;
+; PRINT FULL DEVICE STATUS LINE
+;
+CHUSB_PRTSTAT:
+	PUSH	AF
+	PUSH	DE
+	PUSH	HL
+	LD	A,(IY+CHUSB_STAT)
+	CALL	CHUSB_PRTPREFIX		; PRINT UNIT PREFIX
+	CALL	PC_SPACE		; FORMATTING
+	CALL	CHUSB_PRTSTATSTR
+	POP	HL
+	POP	DE
+	POP	AF
+	RET
+;
+; PRINT STATUS STRING
+;
+CHUSB_PRTSTATSTR:
+	PUSH	AF
+	PUSH	DE
+	PUSH	HL
+	LD	A,(IY+CHUSB_STAT)
+	NEG
+	LD	HL,CHUSB_STR_ST_MAP
+	ADD	A,A
+	CALL	ADDHLA
+	LD	E,(HL)
+	INC	HL
+	LD	D,(HL)
+	CALL	WRITESTR
+	POP	HL
+	POP	DE
+	POP	AF
+	RET
+;
+; PRINT DIAGNONSTIC PREFIX
+;
+CHUSB_PRTPREFIX:
+	PUSH	AF
+	CALL	NEWLINE
+	PRTS("CHUSB$")
+	LD	A,(IY+CH_DEV)		; GET CURRENT DEVICE NUM
+	CALL	PRTDECB
+	CALL	PC_COLON
+	POP	AF
+	RET
+;
+; DATA STORAGE
+;
+CHUSB_DEVNUM	.DB	0		; TEMP DEVICE NUM USED DURING INIT
+CHUSB_DSKBUF	.DW	0
+;
+CHUSB_STR_ST_MAP:
+	.DW		CHUSB_STR_STOK
+	.DW		CHUSB_STR_STNOMEDIA
+	.DW		CHUSB_STR_STCMDERR
+	.DW		CHUSB_STR_STIOERR
+	.DW		CHUSB_STR_STTO
+	.DW		CHUSB_STR_STNOTSUP
+;
+CHUSB_STR_STOK		.TEXT	"OK$"
+CHUSB_STR_STNOMEDIA	.TEXT	"NO MEDIA$"
+CHUSB_STR_STCMDERR	.TEXT	"COMMAND ERROR$"
+CHUSB_STR_STIOERR	.TEXT	"IO ERROR$"
+CHUSB_STR_STTO		.TEXT	"TIMEOUT$"
+CHUSB_STR_STNOTSUP	.TEXT	"NOT SUPPORTED$"
+CHUSB_STR_STUNK		.TEXT	"UNKNOWN ERROR$"

Source/HBIOS/ctc.asm

@@ -162,7 +162,9 @@ CTCTIVT		.EQU	INT_CTC0A + CTCTIMCH
 ;==================================================================================================
 ;
 CTC_PREINIT:
-	; BLINDLY RESET THE CTC ASSUMING IT IS THERE
+	; BLINDLY RESET THE CTC ASSUMING IT IS THERE.  PER ALAN COX
+	; THE CTC CONFIGURATION IS UNDEFINED AT STARTUP.  THIS SHOULD
+	; PRECLUDE POSSIBLE EXTRANEOUS INTERRUPTS.
 	LD	A,CTC_DEFCFG
 	OUT	(CTCBASE),A
 	OUT	(CTCBASE+1),A

Source/HBIOS/cvdu.asm

@@ -208,6 +208,11 @@ CVDU_VDASAT:
 	RET
 
 CVDU_VDASCO:
+	; WE HANDLE ONLY PER-CHARACTER COLORS (D=0)
+	LD	A,D			; GET CHAR/SCREEN SCOPE
+	OR	A			; CHARACTER?
+	JR	NZ,CVDU_VDASCO_Z	; IF NOT, JUST RETURN
+
 	; INCOMING IS:  IBGRIBGR (I=INTENSITY, B=BLUE, G=GREEN, R=RED)
 	; TRANSFORM TO: ----RGBI (DISCARD BACKGROUND COLOR IN HIGH NIBBLE)
 	XOR	A		; CLEAR A
@@ -221,6 +226,7 @@ CVDU_VDASCO1:
 	AND	%11110000	; CLEAR OUT OLD COLOR BITS
 	OR	E		; STUFF IN THE NEW ONES
 	LD	(CVDU_ATTR),A	; AND SAVE THE RESULT
+CVDU_VDASCO_Z:
 	XOR	A		; SIGNAL SUCCESS
 	RET
 

Source/HBIOS/dbgmon.asm

@@ -1729,20 +1729,27 @@ DSKY_PUTLED:
 	RET
 ;
 DSKY_HIGHLIGHTFWDKEYS:
-	LD	HL,DSKY_HIGHLIGHTFWDKEYLEDS
-	JR 	DSKY_PUTLED
+	LD	DE,DSKY_HIGHLIGHTFWDKEYLEDS
+	JR 	DSKY_HIGHLIGHT
 ;
 DSKY_HIGHLIGHTCMDKEYS:
-	LD	HL,DSKY_HIGHLIGHTCMDKEYLEDS
-	JR 	DSKY_PUTLED
+	LD	DE,DSKY_HIGHLIGHTCMDKEYLEDS
+	JR 	DSKY_HIGHLIGHT
 ;
 DSKY_HIGHLIGHTNUMKEYS:
-	LD	HL,DSKY_HIGHLIGHTNUMKEYLEDS
-	JR 	DSKY_PUTLED
+	LD	DE,DSKY_HIGHLIGHTNUMKEYLEDS
+	JR 	DSKY_HIGHLIGHT
 ;
 DSKY_HIGHLIGHTKEYSOFF:
-	LD	HL,DSKY_HIGHLIGHTKEYLEDSOFF
-	JR 	DSKY_PUTLED
+	LD	DE,DSKY_HIGHLIGHTKEYLEDSOFF
+	JR 	DSKY_HIGHLIGHT
+;
+DSKY_HIGHLIGHT:
+	PUSH	HL
+	EX	DE,HL
+	CALL	DSKY_PUTLED
+	POP	HL
+	RET
 ;
 DSKY_HIGHLIGHTFWDKEYLEDS	.DB 	$00,$00,$00,$30,$00,$00,$00,$00
 DSKY_HIGHLIGHTCMDKEYLEDS	.DB 	$20,$00,$20,$3F,$00,$00,$00,$00

Source/HBIOS/ds1501rtc.asm

@@ -53,42 +53,42 @@
 ;  +---+--+--+-----+----+----+----+----+----+----+------------------+----------------+
 ;  |14-1F |              Reserved                |                  |                |
 ;  +------+--+-----+----+----+----+----+----+----+------------------+----------------+
-
+;
 ;  * = Unused bits; unwritable and read as 0.
 ;  0 = should be set to 0 for valid time/calendar range.
 ;  Clock calendar data is BCD. Automatic leap year adjustment.
 ;  Day-Of-Week coded as Sunday = 1 through Saturday = 7.
-
+;
 ; Constants
-
-;By defining 2 bases, this allows some flexibility for address decoding
-DS1501NVM_BASE      .EQU    DS1501RTC_BASE + $10
+;
+; By defining 2 bases, this allows some flexibility for address decoding
+DS1501NVM_BASE		.EQU	DS1501RTC_BASE + $10
 
-DS1501RTC_SEC	    .EQU	DS1501RTC_BASE + $00
-DS1501RTC_MIN	    .EQU	DS1501RTC_BASE + $01
-DS1501RTC_HOUR	    .EQU	DS1501RTC_BASE + $02
+DS1501RTC_SEC		.EQU	DS1501RTC_BASE + $00
+DS1501RTC_MIN		.EQU	DS1501RTC_BASE + $01
+DS1501RTC_HOUR		.EQU	DS1501RTC_BASE + $02
 DS1501RTC_WEEK_DAY	.EQU	DS1501RTC_BASE + $03
-DS1501RTC_DAY	    .EQU	DS1501RTC_BASE + $04
-DS1501RTC_MONTH	    .EQU	DS1501RTC_BASE + $05
-DS1501RTC_YEAR	    .EQU	DS1501RTC_BASE + $06
-DS1501RTC_CENT      .EQU	DS1501RTC_BASE + $07
+DS1501RTC_DAY		.EQU	DS1501RTC_BASE + $04
+DS1501RTC_MONTH		.EQU	DS1501RTC_BASE + $05
+DS1501RTC_YEAR		.EQU	DS1501RTC_BASE + $06
+DS1501RTC_CENT		.EQU	DS1501RTC_BASE + $07
 DS1501RTC_SEC_ALM	.EQU	DS1501RTC_BASE + $08
 DS1501RTC_MIN_ALM	.EQU	DS1501RTC_BASE + $09
 DS1501RTC_HOUR_ALM	.EQU	DS1501RTC_BASE + $0A
 DS1501RTC_DAY_ALM	.EQU	DS1501RTC_BASE + $0B
-DS1501RTC_WDOG1     .EQU	DS1501RTC_BASE + $0C
-DS1501RTC_WDOG2 	.EQU	DS1501RTC_BASE + $0D
+DS1501RTC_WDOG1		.EQU	DS1501RTC_BASE + $0C
+DS1501RTC_WDOG2		.EQU	DS1501RTC_BASE + $0D
 DS1501RTC_CONTROLA	.EQU	DS1501RTC_BASE + $0E
 DS1501RTC_CONTROLB	.EQU	DS1501RTC_BASE + $0F
-
+;
 DS1501RTC_RAMADDR	.EQU	DS1501NVM_BASE + $00
 DS1501RTC_RAMDATA	.EQU	DS1501NVM_BASE + $03
-
-DS1501RTC_HIGH	.EQU	%11110000
-DS1501RTC_LOW	.EQU	%00001111
-
-;ControlA bit masks
-;BLF1| BLF2| PRS| PAB| TDF| KSF| WDF|IRQF
+;
+DS1501RTC_HIGH		.EQU	%11110000
+DS1501RTC_LOW		.EQU	%00001111
+;
+; ControlA bit masks
+; BLF1| BLF2| PRS| PAB| TDF| KSF| WDF|IRQF
 DS1501RTC_IRQF	.EQU	%00000001
 DS1501RTC_WDF	.EQU	%00000010
 DS1501RTC_KSF	.EQU	%00000100
@@ -97,9 +97,9 @@ DS1501RTC_PAB	.EQU	%00010000
 DS1501RTC_PRS 	.EQU	%00100000
 DS1501RTC_BLF2  .EQU	%01000000
 DS1501RTC_BLF1	.EQU	%10000000
-
-;ControlB bit masks
-;TE| CS| BME| TPE| TIE| KIE| WDE| WDS|
+;
+; ControlB bit masks
+; TE| CS| BME| TPE| TIE| KIE| WDE| WDS|
 DS1501RTC_WDS 	.EQU	%00000001
 DS1501RTC_WDE	.EQU	%00000010
 DS1501RTC_KIE	.EQU	%00000100
@@ -108,7 +108,7 @@ DS1501RTC_TPE	.EQU	%00010000
 DS1501RTC_BME 	.EQU	%00100000
 DS1501RTC_CS    .EQU	%01000000
 DS1501RTC_TE	.EQU	%10000000
-
+;
 DS1501RTC_BUFSIZE	.EQU	6		; 6 BYTE BUFFER (YYMMDDHHMMSS)
 
 	.ECHO	"DS1501RTC: RTCIO="
@@ -116,27 +116,28 @@ DS1501RTC_BUFSIZE	.EQU	6		; 6 BYTE BUFFER (YYMMDDHHMMSS)
 	.ECHO	", NVMIO="
 	.ECHO	DS1501NVM_BASE
 	.ECHO	"\n"
-
+;
 ; RTC Device Initialization Entry
-
+;
 DS1501RTC_INIT:
 	CALL	NEWLINE				; Formatting
 	PRTS("DS1501RTC: IO=0x$")
 	LD	A, DS1501RTC_BASE
 	CALL	PRTHEXBYTE
-
+;
 	CALL	NEWLINE				; Formatting
 	PRTS("DS1501NVM: IO=0x$")
 	LD	A, DS1501NVM_BASE
 	CALL	PRTHEXBYTE
-
-    IN	A,(DS1501RTC_CONTROLB)      ;clear any pending interrupt flags
-
+;
+	IN	A,(DS1501RTC_CONTROLB)		; Clear any pending interrupt flags
+;
 	XOR	A				; Zero A
-    OR      DS1501RTC_TE            ;enable time updates
-    OUT	(DS1501RTC_CONTROLB), A
-
+	OR	DS1501RTC_TE			; Enable time updates
+	OUT	(DS1501RTC_CONTROLB), A
+;
 	CALL	DS1501RTC_LOAD
+;
 	; DISPLAY CURRENT TIME
 	PRTS("  $")
 	LD	A, (DS1501RTC_BUF_MON)
@@ -156,44 +157,36 @@ DS1501RTC_INIT:
 	PRTS(":$")
 	LD	A, (DS1501RTC_BUF_SEC)
 	CALL	PRTHEXBYTE
-
+;
 	LD	BC,DS1501RTC_DISPATCH
 	CALL	RTC_SETDISP
-
+;
 	XOR	A				; Signal success
 	RET
-
+;
 ; RTC Device Function Dispatch Entry
 ;   A: Result (OUT), 0=OK, Z=OK, NZ=Error
 ;   B: Function (IN)
-
+;
 DS1501RTC_DISPATCH:
 	LD	A, B				; Get requested function
 	AND	$0F				; Isolate Sub-Function
-	JP	Z, DS1501RTC_GETTIM			; Get Time
+	JP	Z, DS1501RTC_GETTIM		; Get Time
 	DEC	A
-	JP	Z, DS1501RTC_SETTIM			; Set Time
+	JP	Z, DS1501RTC_SETTIM		; Set Time
 	DEC	A
-	JP	Z, DS1501RTC_GETBYT			; Get NVRAM Byte Value
+	JP	Z, DS1501RTC_GETBYT		; Get NVRAM Byte Value
 	DEC	A
-	JP	Z, DS1501RTC_SETBYT			; Set NVRAM Byte Value
+	JP	Z, DS1501RTC_SETBYT		; Set NVRAM Byte Value
 	DEC	A
-	JP	Z, DS1501RTC_GETBLK			; Get NVRAM Data Block Value
+	JP	Z, DS1501RTC_GETBLK		; Get NVRAM Data Block Value
 	DEC	A
-	JP	Z, DS1501RTC_SETBLK			; Set NVRAM Data Block Value
+	JP	Z, DS1501RTC_SETBLK		; Set NVRAM Data Block Value
 	DEC	A
-	JP	Z, DS1501RTC_GETALM			; Get Alarm
+	JP	Z, DS1501RTC_GETALM		; Get Alarm
 	DEC	A
-	JP	Z, DS1501RTC_SETALM			; Set Alarm
+	JP	Z, DS1501RTC_SETALM		; Set Alarm
 ;
-; NVRAM FUNCTIONS ARE NOT IMPLEMENTED YET
-;
-DS1501RTC_GETBYT:
-DS1501RTC_SETBYT:
-DS1501RTC_GETBLK:
-DS1501RTC_SETBLK:
-	CALL	PANIC
-
 ; RTC Get Time
 ;   A: Result (OUT), 0=OK, Z=OK, NZ=Error
 ;   HL: Date/Time Buffer (OUT)
@@ -234,7 +227,7 @@ DS1501RTC_SETTIM:
 	LD	(HB_SRCBNK), A			; Set it
 	LD	A, BID_BIOS			; Copy to BIOS bank
 	LD	(HB_DSTBNK), A			; Set it
-	LD	DE, DS1501RTC_BUF			; Destination Address
+	LD	DE, DS1501RTC_BUF		; Destination Address
 	LD	BC, DS1501RTC_BUFSIZE		; Length is 6 bytes
 #IF (INTMODE == 1)
 	DI
@@ -247,27 +240,123 @@ DS1501RTC_SETTIM:
 	LD	HL, DS1501RTC_BUF
 	CALL	DS1501RTC_SUSPEND
 	LD	A, (HL)
-	OUT	(DS1501RTC_YEAR), A			; Write Year
+	OUT	(DS1501RTC_YEAR), A		; Write Year
 	INC	HL
 	LD	A, (HL)
 	OUT	(DS1501RTC_MONTH), A		; Write Month
 	INC	HL
 	LD	A, (HL)
-	OUT	(DS1501RTC_DAY), A			; Write Day
+	OUT	(DS1501RTC_DAY), A		; Write Day
 	INC	HL
 	LD	A, (HL)
-	OUT	(DS1501RTC_HOUR), A			; Write Hour
+	OUT	(DS1501RTC_HOUR), A		; Write Hour
 	INC	HL
 	LD	A, (HL)
-	OUT	(DS1501RTC_MIN), A			; Write Minute
+	OUT	(DS1501RTC_MIN), A		; Write Minute
 	INC	HL
 	LD	A, (HL)
-	OUT	(DS1501RTC_SEC), A			; Write Second
+	OUT	(DS1501RTC_SEC), A		; Write Second
 	CALL	DS1501RTC_RESUME
-	; clean up and return
+;
+	; Clean up and return
 	XOR	A				; Signal success
 	RET					; And return
-
+;
+; RTC Get Byte
+;
+DS1501RTC_GETBYT:
+;
+; C Index
+; E Value
+; Set address
+;
+	LD	B, C
+	LD	C, DS1501RTC_RAMADDR
+	OUT	(C), B
+;
+	; Get data
+	IN	A, (DS1501RTC_RAMDATA)
+	LD	E,A
+;
+	; Return success
+	XOR	
+;
+	RET
+;
+; RTC Set Byte
+;
+DS1501RTC_SETBYT:
+;
+; C Index
+; E Value
+; Set address
+;
+	LD	B, C
+	LD	C, DS1501RTC_RAMADDR
+	OUT	(C), B
+;	
+	; Set data
+	LD	A,E
+	OUT	(DS1501RTC_RAMDATA), A
+;	
+	; Return success
+	XOR	A
+	RET
+;
+; RTC Get Block
+;
+DS1501RTC_GETBLK:
+;
+; HL Buffer Address
+;
+	LD	B, 0				; 256 Bytes
+;	
+	; Set BME
+	IN	A, (DS1501RTC_CONTROLB)
+	OR	DS1501RTC_BME
+	OUT	(DS1501RTC_CONTROLB), A
+;	
+	XOR	A
+	OUT	(DS1501RTC_RAMADDR), A
+	LD	C, DS1501RTC_RAMDATA
+	INIR
+;	
+	; Clear BME
+	IN	A, (DS1501RTC_CONTROLB)
+	AND	~DS1501RTC_BME
+	OUT	(DS1501RTC_CONTROLB), A
+;	
+	; Return success
+	XOR	A
+	RET
+;
+; RTC Set Block
+;
+DS1501RTC_SETBLK:
+;
+; HL Buffer Address
+;
+	LD B, 0					; 256 Bytes
+;
+	; Set BME
+	IN	A, (DS1501RTC_CONTROLB)
+	OR	DS1501RTC_BME
+	OUT	(DS1501RTC_CONTROLB), A
+;
+	XOR	A
+	OUT	(DS1501RTC_RAMADDR), A
+	LD	C, DS1501RTC_RAMDATA
+	OTIR
+;
+	; Clear BME
+	IN	A, (DS1501RTC_CONTROLB)
+	AND	~DS1501RTC_BME
+	OUT	(DS1501RTC_CONTROLB), A
+;
+	; Return success
+	XOR	A
+	RET
+;
 ; RTC Get Alarm
 ;   A: Result (OUT), 0=OK, Z=OK, NZ=Error
 ;   HL: Date/Time Buffer (OUT)
@@ -297,6 +386,7 @@ DS1501RTC_GETALM:
 	LD	(HL), A
 	CALL	DS1501RTC_RESUME
 	POP	HL				; Restore address of source buffer
+;
 	; Now copy to read destination (Interbank Save)
 	LD	A, BID_BIOS			; Copy from BIOS bank
 	LD	(HB_SRCBNK), A			; Set it
@@ -327,7 +417,7 @@ DS1501RTC_SETALM:
 	LD	(HB_SRCBNK), A			; Set it
 	LD	A, BID_BIOS			; Copy to BIOS bank
 	LD	(HB_DSTBNK), A			; Set it
-	LD	DE, DS1501RTC_BUF			; Destination Address
+	LD	DE, DS1501RTC_BUF		; Destination Address
 	LD	BC, DS1501RTC_BUFSIZE		; Length is 6 bytes
 #IF (INTMODE == 1)
 	DI
@@ -351,49 +441,50 @@ DS1501RTC_SETALM:
 	LD	A, (HL)
 	OUT	(DS1501RTC_SEC_ALM), A		; Write Second
 	CALL	DS1501RTC_RESUME
-	; clean up and return
+;
+	; Clean up and return
 	XOR	A				; Signal success
 	RET					; And return
-
+;
 DS1501RTC_SUSPEND:
 	IN	A, (DS1501RTC_CONTROLB)		; Suspend Clock
 	AND	~DS1501RTC_TE
 	OUT	(DS1501RTC_CONTROLB), A
 	RET
-
+;
 DS1501RTC_RESUME:
 	IN	A, (DS1501RTC_CONTROLB)		; Resume Clock
 	OR	DS1501RTC_TE
 	OUT	(DS1501RTC_CONTROLB), A
 	RET
-
+;
 DS1501RTC_LOAD:
 	LD	HL, DS1501RTC_BUF
 	PUSH	HL				; Save address of source buffer
 	CALL	DS1501RTC_SUSPEND
-	IN	A, (DS1501RTC_YEAR)			; Read Year
+	IN	A, (DS1501RTC_YEAR)		; Read Year
 	LD	(HL), A
 	INC	HL
 	IN	A, (DS1501RTC_MONTH)		; Read Month
 	LD	(HL), A
 	INC	HL
-	IN	A, (DS1501RTC_DAY)			; Read Day
+	IN	A, (DS1501RTC_DAY)		; Read Day
 	LD	(HL), A
 	INC	HL
-	IN	A, (DS1501RTC_HOUR)			; Read Hour
+	IN	A, (DS1501RTC_HOUR)		; Read Hour
 	LD	(HL), A
 	INC	HL
-	IN	A, (DS1501RTC_MIN)			; Read Minute
+	IN	A, (DS1501RTC_MIN)		; Read Minute
 	LD	(HL), A
 	INC	HL
-	IN	A, (DS1501RTC_SEC)			; Read Second
+	IN	A, (DS1501RTC_SEC)		; Read Second
 	LD	(HL), A
 	CALL	DS1501RTC_RESUME
 	POP	HL				; Restore address of source buffer
 	RET
-
+;
 ; Working Variables
-
+;
 DS1501RTC_BUF:
 DS1501RTC_BUF_YEAR:	.DB	0		; Year
 DS1501RTC_BUF_MON:	.DB	0		; Month

Source/HBIOS/fd.asm

@@ -84,6 +84,14 @@ FDC_DCR		.EQU	$35		; CONFIGURATION CONTROL REGISTER
 FDC_TC		.EQU	$37		; TERMINAL COUNT (W/ DACK)
   #DEFINE FDMODE_STR "MBC"
 #ENDIF
+#IF (FDMODE == FDMODE_DUO)
+FDC_MSR		.EQU	$80		; 8272 MAIN STATUS REGISTER
+FDC_DATA	.EQU	$81		; 8272 DATA PORT
+FDC_DOR		.EQU	$86		; DIGITAL OUTPUT REGISTER
+FDC_DCR		.EQU	$85		; CONFIGURATION CONTROL REGISTER
+FDC_TC		.EQU	$87		; TERMINAL COUNT (W/ DACK)
+  #DEFINE FDMODE_STR "DUO"
+#ENDIF
 ;
 ;
 ; DISK OPERATIONS
@@ -515,7 +523,7 @@ DOR_INIT	.EQU	11100000B	; INITIAL DEFAULT LATCH VALUE
 ;
 ; *** DIDE/N8/ZETA V2 ***
 ;
-#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC) | (FDMODE == FDMODE_DYNO) | (FDMODE == FDMODE_EPFDC) | (FDMODE == FDMODE_MBC))
+#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC) | (FDMODE == FDMODE_DYNO) | (FDMODE == FDMODE_EPFDC) | (FDMODE == FDMODE_MBC) | (FDMODE == FDMODE_DUO))
 DOR_INIT	.EQU	00001100B	; SOFT RESET INACTIVE, DMA ENABLED
 DOR_BR250	.EQU	DOR_INIT
 DOR_BR500	.EQU	DOR_INIT
@@ -812,6 +820,10 @@ FD_INIT:
 #IF (FDMODE == FDMODE_MBC)
 	PRTS("MBC$")
 #ENDIF
+;
+#IF (FDMODE == FDMODE_DUO)
+	PRTS("DUO$")
+#ENDIF
 ;	
 	PRTS(" IO=0x$")
 	LD	A,FDC_MSR
@@ -1455,7 +1467,7 @@ FC_SETDOR:
 ;
 ; SET FST_DCR
 ;
-#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC) | (FDMODE == FDMODE_DYNO) | (FDMODE == FDMODE_EPFDC) | (FDMODE == FDMODE_MBC))
+#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC) | (FDMODE == FDMODE_DYNO) | (FDMODE == FDMODE_EPFDC) | (FDMODE == FDMODE_MBC) | (FDMODE == FDMODE_DUO))
 ;
 FC_SETDCR
 	LD	(FST_DCR),A
@@ -1487,7 +1499,7 @@ FC_RESETFDC:
 #IF ((FDMODE == FDMODE_ZETA) | (FDMODE == FDMODE_DIO3) | (FDMODE == FDMODE_RCSMC))
 	RES	7,A
 #ENDIF
-#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC) | (FDMODE == FDMODE_DYNO) | (FDMODE == FDMODE_EPFDC) | (FDMODE == FDMODE_MBC))
+#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC) | (FDMODE == FDMODE_DYNO) | (FDMODE == FDMODE_EPFDC) | (FDMODE == FDMODE_MBC) | (FDMODE == FDMODE_DUO))
 	LD	A,0
 #ENDIF
 	CALL	FC_SETDOR
@@ -1504,7 +1516,7 @@ FC_RESETFDC:
 FC_PULSETC:
 ; PULSING TC NO LONGER REQUIRED BECAUSE WE ONLY READ A SINGLE SECTOR
 ;
-;#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC) | (FDMODE == FDMODE_DYNO) | (FDMODE == FDMODE_EPFDC) | (FDMODE == FDMODE_MBC))
+;#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC) | (FDMODE == FDMODE_DYNO) | (FDMODE == FDMODE_EPFDC) | (FDMODE == FDMODE_MBC) | (FDMODE == FDMODE_DUO))
 ;	IN	A,(FDC_TC)
 ;#ELSE
 ;	LD	A,(FST_DOR)
@@ -1561,7 +1573,7 @@ FC_MOTORON1:
 	CP	C			; COMPARE TO NEW MOTOR BITS
 	RET	Z			; SKIP DELAY, MOTOR WAS ALREADY ON
 #ENDIF
-#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC) | (FDMODE == FDMODE_DYNO) | (FDMODE == FDMODE_EPFDC) | (FDMODE == FDMODE_MBC))
+#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC) | (FDMODE == FDMODE_DYNO) | (FDMODE == FDMODE_EPFDC) | (FDMODE == FDMODE_MBC) | (FDMODE == FDMODE_DUO))
 	; SETUP DCR FOR DIDE HARDWARE
 	LD	A,(FCD_DCR)		; GET NEW DCR VALUE
 	CALL	FC_SETDCR		; AND IMPLEMENT IT

Source/HBIOS/gdc.asm

@@ -189,8 +189,13 @@ GDC_VDASAT:	; SET ATTRIBUTES
 	RET
 
 GDC_VDASCO:	; SET COLOR
+	; WE HANDLE ONLY PER-CHARACTER COLORS (D=0)
+	LD	A,D		; GET CHAR/SCREEN SCOPE
+	OR	A		; CHARACTER?
+	JR	NZ,GDC_VDASCO_Z	; IF NOT, JUST RETURN
 	LD	A,E		; GET THE INCOMING COLOR
 	LD	(GDC_COLOR),A	; AND SAVE FOR LATER
+GDC_VDASCO_Z:
 	XOR	A		; SIGNAL SUCCESS
 	RET
 

Source/HBIOS/hbios.asm

@@ -92,6 +92,8 @@ MODCNT	.SET	MODCNT + 1
 ;
 ;
 ;
+#DEFINE ALIGN(N) .FILL	((($+(N-1)) & ~(N-1)) - $)
+;
 #IF (FPLED_ENABLE)
   #DEFINE DIAG(N)	PUSH AF
   #DEFCONT \		LD A,N
@@ -610,6 +612,25 @@ HBX_ROM:
 	RET				; DONE
 #ENDIF
 ;
+#IF (MEMMGR == MM_MON)
+;
+; CURRENTLY ASSUMES FIRST 16 PAGES ARE RAM FOLLOWED BY 16 PAGES OF ROM.
+; SO, WE MAP HBIOS BANKS $00-$0F (ROM SELECT) TO $10-$%1F AND HBIOS
+; BANKS $80-$8F (RAM SELECT) TO $00-$0F.
+;
+	BIT	7,A			; BIT 7 SET REQUESTS RAM PAGE
+	JR	Z,HBX_ROM		; NOT SET, SELECT ROM PAGE
+	RES	7,A			; RAM PAGE REQUESTED: CLEAR ROM BIT
+	OUT	($FF),A			; DO IT
+	RET				; AND DONE
+;
+HBX_ROM:
+	ADD	A,$10			; OFFSET INTO ROM BANKS
+	OUT	($FF),A			; DO IT
+	RET				; DONE
+#ENDIF
+;
+;
 ;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
 ; Copy Data - Possibly between banks.  This resembles CP/M 3, but
 ;  usage of the HL and DE registers is reversed.
@@ -1226,10 +1247,8 @@ BOOTWAIT:
 ;
 	JR	Z280_INITZ		; JUMP TO CODE CONTINUATION
 ;
-    #IF (($ % 2) == 1)
-	; WORD ALIGN THE TABLE
-	.DB	0
-    #ENDIF
+	; WORD ALIGN THE PDR TABLE
+	ALIGN(2)
 ;
 Z280_BOOTPDRTBL:
 	; LOWER 32 K (BANKED)
@@ -2075,6 +2094,15 @@ HB_CPU2:
 HB_CPU3:
 #ENDIF
 ;
+#IF (CPUFAM == CPU_Z280)
+;
+	; Z280 ALWAYS HALVES THE INPUT OSCILLATOR TO DERIVE
+	; ACTUAL CPU SPEED.
+	; ADJUST HL TO REFLECT HALF SPEED OPERATION
+	SRL	H		; ADJUST HL ASSUMING
+	RR	L		; HALF SPEED OPERATION
+#ENDIF
+;
 ; HL SHOULD NOW HAVE FINAL CPU RUNNING SPEED IN KHZ.
 ; UPDATE CB_CPUMHZ/CB_CPUKHZ WITH THIS VALUE.
 ;
@@ -5204,12 +5232,12 @@ SYS_INTSET1:
 	; HERE IN AN EFFORT TO MINIMIZE WASTED SPACE.  THERE SHOULD BE
 	; A LITTLE LESS THAN 4K OF CODE ABOVE.
 ;
-Z280_IVT_SLACK	.EQU	$1000 - ($ & $FFF)
-		.ECHO	"Z280 IVT SLACK occupies "
-		.ECHO	Z280_IVT_SLACK
-		.ECHO	" bytes.\n"
-		;.FILL	$1000 - ($ & $FFF)	; MUST BE 4K ALIGNED!
-		.FILL	Z280_IVT_SLACK		; MUST BE 4K ALIGNED!
+Z280_IVT_SLACK_ORG	.EQU	$
+	ALIGN($1000)
+Z280_IVT_SLACK		.EQU	$ - Z280_IVT_SLACK_ORG
+	.ECHO	"Z280 IVT SLACK occupies "
+	.ECHO	Z280_IVT_SLACK
+	.ECHO	" bytes.\n"
 ;
 Z280_IVT:
 	.DW	0, 0			; RESERVED
@@ -7846,8 +7874,9 @@ HB_WRKBUF	.FILL	512,0		; INTERNAL DISK BUFFER
 ;
 #IFDEF MG014_MAP
 ;
-	.FILL	32 - ($ & (32 - 1))	; ALIGN TO 32 BYTE BOUNDARY
-
+	; ALIGN TO 32 BYTE BOUNDARY
+	ALIGN($20)
+;
 MG014_STATMAPLO:
 	; LOWER NIBBLE
 	.DB	$08	; 00

Source/HBIOS/hbios.inc

@@ -154,6 +154,7 @@ PLT_S100	.EQU	16		; S100 COMPUTERS Z180 SYSTEM
 PLT_DUO		.EQU	17		; DUODYNE Z80 SYSTEM
 PLT_HEATH	.EQU	18		; HEATHKIT H8 Z80 SYSTEM
 PLT_EPITX	.EQU	19		; Z180 MINI-ITX
+PLT_MON		.EQU	20		; MONSPUTER
 ;
 ; HBIOS GLOBAL ERROR RETURN VALUES
 ;

Source/HBIOS/hbios_env.asm

@@ -24,12 +24,9 @@
 ;
 ; Print all desired config values...
 ;
-#if (ROMSIZE > 0)
-	prtval("ROMSIZE$", ROMSIZE)
-#else
-	prtval("ROMSIZE$", RAMSIZE)
-#endif
 	prtval("CPUFAM$", CPUFAM)
+	prtval("ROMSIZE$", ROMSIZE)
+	prtval("RAMSIZE$", RAMSIZE)
 ;
 	ret
 ;

Source/HBIOS/ide.asm

@@ -1391,8 +1391,8 @@ IDE_RESET:
 ; IMMEDIATELY.  A SMALL WAIT IS PERFORMED HERE TO GIVE SUCH DEVICES
 ; A BETTER CHANCE TO SUCCEED LATER.
 ;
-;;;	CALL	LDELAY			; DELAY FOR SLAVE INIT
-	LD	DE,150000 / 16		; 
+;	LD	DE,150000 / 16		; 
+	LD	DE,300000 / 16		; 
 	CALL	VDELAY			; SMALL DELAY
 ;
 	JR	IDE_RESET3		; SKIP SOFT RESET

Source/HBIOS/pkd.asm

@@ -140,7 +140,7 @@ PKD_INIT:
 	LD	A,PKDPPIBASE		; GET BASE PORT
 	CALL	PRTHEXBYTE		; PRINT BASE PORT
 ;
-	LD	A,(PKD_PRESENT)	; PRESENT?
+	LD	A,(PKD_PRESENT)		; PRESENT?
 	OR	A			; SET FLAGS
 	RET	NZ			; YES, ALL DONE
 	PRTS(" NOT PRESENT$")		; NOT PRESENT

Source/HBIOS/ppide.asm

@@ -1373,8 +1373,8 @@ PPIDE_RESET:
 ; IMMEDIATELY.  A SMALL WAIT IS PERFORMED HERE TO GIVE SUCH DEVICES
 ; A BETTER CHANCE TO SUCCEED LATER.
 ;
-;;;	CALL	LDELAY			; DELAY FOR SLAVE INIT
-	LD	DE,150000 / 16		; 
+;	LD	DE,150000 / 16		; 
+	LD	DE,300000 / 16		; 
 	CALL	VDELAY			; SMALL DELAY
 ;
 	JR	PPIDE_RESET3		; SKIP SOFT RESET

Source/HBIOS/sd.asm

@@ -267,7 +267,11 @@ RTCDEF		.SET	RTCDEF | SD_OPRDEF	; SET DEFAULT IN HBIOS MAINLINE
 ; THANKS TO DOUGLAS MILLER FOR BRINGING THIS BEHAVIOR TO MY ATTENTION
 ; AND SUPPLYING ASSOCIATED FIXES.
 ;
+  #IF (PLATFORM == PLT_DUO)
+SD_BASE		.EQU	$8C		; Module base address
+  #ELSE
 SD_BASE		.EQU	$5C		; Module base address
+  #ENDIF
 SD_DEVMAX	.EQU	2		; NUMBER OF PHYSICAL UNITS (SOCKETS)
 SD_WRTR		.EQU	SD_BASE + 0	; Write data and transfer
 SD_RDTR		.EQU	SD_BASE + 1	; Read data and transfer

Source/HBIOS/std.asm

@@ -19,6 +19,9 @@
 ; 15. Z80RETRO	Peter Wilson's Z80-Retro Computer
 ; 16. S100	S100 Computers Z180-based System
 ; 17. DUO	Andrew Lynch's Duodyne Computer
+; 18. HEATH	Les Bird's Heath Z80 Board
+; 19. EPITX	Alan Cox' Mini-ITX System
+; 20. MON	Jacques Pelletier's Monsputer
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;
@@ -70,6 +73,7 @@ MM_Z280		.EQU	5		; Z280 NATIVE MEMORY MANAGER
 MM_ZRC		.EQU	6		; ZRC BANK SWITCHING
 MM_MBC		.EQU	7		; MBC MEMORY MANAGER
 MM_RPH		.EQU	8		; Z180 WITH RPH EXTENSIONS
+MM_MON		.EQU	9		; MONSPUTER MMU
 ;
 ; BOOT STYLE
 ;
@@ -161,7 +165,8 @@ FDMODE_RCSMC	.EQU	7		; RCBUS SMC 9266 @ $40 (SCOTT BAKER)
 FDMODE_RCWDC	.EQU	8		; RCBUS WDC 37C65 @ $40 (SCOTT BAKER)
 FDMODE_DYNO	.EQU	9		; DYNO WDC 37C65 @ $84
 FDMODE_EPFDC	.EQU	10		; RCBUS ETCHED PIXELS FDC
-FDMODE_MBC	.EQU	11		; MULTI-BOARD COMPUTER FDC
+FDMODE_MBC	.EQU	11		; NHYODYNE (MBC) FDC
+FDMODE_DUO	.EQU	12		; DUODUYNE (DUO) FDC
 ;
 ; IDE MODE SELECTIONS
 ;
@@ -628,6 +633,9 @@ SYSTIM	.SET	TM_Z280
   #ENDIF
   #IF (MEMMGR == MM_RPH)
 	.ECHO	"RHYOPHYRE ONBOARD (RPH)"
+  #ENDIF
+  #IF (MEMMGR == MM_MON)
+	.ECHO	"MONSPUTER ONBOARD (MON)"
   #ENDIF
 	.ECHO   "\n"
 #ENDIF

Source/HBIOS/tms.asm

@@ -201,7 +201,7 @@ TMS_INIT:
 #IF (TMSMODE == TMSMODE_MSX)
 	PRTS("MSX$")
 #ENDIF
-#IF (TMSMODE == TMSMODE_COLECO)		; ### JLC Mod for completeness ###
+#IF (TMSMODE == TMSMODE_COLECO)
 	PRTS("COLECO$")
 #ENDIF
 #IF (TMSMODE == TMSMODE_MSXKBD)
@@ -215,7 +215,6 @@ TMS_INIT:
 	LD	A,TMS_DATREG
 	CALL	PRTHEXBYTE
 	CALL	TMS_PROBE		; CHECK FOR HW EXISTENCE
-	;JP	TMS_INIT1		; ### JLC DEBUG: ALLWAYS CONTINUE ###
 	JR	Z,TMS_INIT1		; CONTINUE IF PRESENT
 ;
 	; *** HARDWARE NOT PRESENT ***
@@ -370,7 +369,40 @@ TMS_VDASAT:
 	RET
 
 TMS_VDASCO:
-	XOR	A			; NOT POSSIBLE, JUST SIGNAL SUCCESS
+	; ### JLC Mod - Implement Default Text Mode Colors via ANSI_VDASCO or direct HBIOS Call
+	;
+	; Color setting is in reg D in ANSI Format as described in RomWBW System Guide
+	; Convert Color Format from ANSI to TMS shuffling bits arround and using
+	; Color Conversion Table at TMS_COLOR_TBL (approximated equivalences)
+	; Save converted value to (TMS_TMSCOLOR)
+	;
+	; TMS hardware only allows setting a global (screen) foreground/background color.  So, we
+	; only process this command if E is 1.
+	;
+	LD	A,D			; GET CHAR/SCREEN SCOPE
+	CP	1			; SCREEN?
+	JR	NZ,TMS_VDASCO_Z		; IF NOT, JUST RETURN
+;
+	LD	A,E			; GET COLOR BYTE
+	AND	$F0			; ISOLATE BACKGROUND
+	RRCA \ RRCA \ RRCA \ RRCA	; MOVE TO LOWER NIBBLE
+	LD	HL,TMS_COLOR_TBL	; POINT TO COLOR CONVERSION TABLE
+	CALL	ADDHLA			; OFFSET TO DESIRED COLOR
+	LD	B,(HL)			; PUT NEW BG IN B
+;
+	LD	A,E			; GET COLOR BYTE
+	AND	$0F			; ISOLATE FOREGROUND
+	LD	HL,TMS_COLOR_TBL	; POINT TO COLOR CONVERSION TABLE
+	CALL	ADDHLA			; OFFSET TO DESIRED COLOR
+	LD	A,(HL)			; PUT NEW FG IN A
+	RLCA \ RLCA \ RLCA \ RLCA	; MOVE TO UPPER NIBBLE
+;
+	OR	B			; COMBINE WITH FG
+	LD	C, 7			; C = Color Register, A = Desired new Color in TMS Format
+	CALL	TMS_SET			; Write to specific TMS Register, Change Default Text Color
+;
+TMS_VDASCO_Z:
+	XOR	A			; SIGNAL SUCCESS
 	RET
 
 TMS_VDAWRC:
@@ -558,7 +590,7 @@ TMS_CRTINIT:
 	LD	HL,0
 	CALL	TMS_WR
 ;
-	; FILL ENTIRE 16KB VRAM CONTENTS with $00 ### JLC Comment fix ###
+	; FILL ENTIRE 16KB VRAM CONTENTS with $00
 	LD	DE,$4000		; 16KB
 TMS_CRTINIT1:
 	XOR	A
@@ -614,7 +646,7 @@ TMS_LOADFONT:
 #ENDIF
 ;
 	; FILL TMS_FNTVADDR BYTES FROM FONTDATA
-	LD	DE,TMS_FNTSIZE		; ### JLC Mod for JBL compatibility ###
+	LD	DE,TMS_FNTSIZE
 TMS_LOADFONT1:
 	LD	A,(HL)
 	OUT	(TMS_DATREG),A
@@ -738,7 +770,6 @@ TMS_XY2IDX:
 	CALL	MULT8			; MULTIPLY TO GET ROW OFFSET
 	LD	E,A			; GET COLUMN BACK
 	ADD	HL,DE			; ADD IT IN
-	; ### JLC Fix to allow Name Table Addresses other than $0000 and JBL Compatibility ###
 	LD	DE,TMS_CHRVADDR		; Add offset Address to start of Name Table (Char)
 	ADD	HL,DE
 	RET				; RETURN
@@ -787,7 +818,6 @@ TMS_FILL1:
 ;----------------------------------------------------------------------
 ;
 TMS_SCROLL:
-	; ### JLC Fix to allow Name Table Addresses other than $0000 and JBL Compatibility ###
 	LD	HL,TMS_CHRVADDR		; SOURCE ADDRESS OF CHARACTER BUFFER
 	LD	C,TMS_ROWS - 1		; SET UP LOOP COUNTER FOR ROWS - 1
 ;
@@ -839,7 +869,6 @@ TMS_SCROLL3:
 ;----------------------------------------------------------------------
 ;
 TMS_RSCROLL:
-	; ### JLC Fix to allow Name Table Addresses other than $0000 and JBL Compatibility ###
 	LD	HL,TMS_COLS * (TMS_ROWS - 1)
 	LD	DE,TMS_CHRVADDR		; Add offset Address to start of Name Table (Char)
 	ADD	HL,DE
@@ -980,10 +1009,13 @@ TMS_INTHNDL:
 ;   TMS DRIVER - DATA
 ;==================================================================================================
 ;
-TMS_POS		.DW 	0		; CURRENT DISPLAY POSITION
+TMS_POS		.DW	0		; CURRENT DISPLAY POSITION
 TMS_CURSAV	.DB	0		; SAVES ORIGINAL CHARACTER UNDER CURSOR
 TMS_BUF		.FILL	256,0		; COPY BUFFER
-
+;
+; ### JLC Mod
+; ANSI-->TMS Color Conversion Table
+TMS_COLOR_TBL	.DB	$01,$08,$02,$0A,$04,$06,$0C,$0F,$0E,$09,$03,$0B,$05,$0D,$07,$0F
 ;
 ;==================================================================================================
 ;   TMS DRIVER - INSTANCE DATA
@@ -1055,6 +1087,10 @@ TMS_IDAT:
 ; https://www.msx.org/wiki/Screen_Modes_Description#SCREEN_0_in_80-column_.28Text_mode_2.29
 ; BITS 1-0 SHOULD BE 1.  BITS 8-2 SHOULD BE (ADR >> 8).
 ;
+; ### JLC Mod
+; TEXT MODE DEFAULT COLOR (REG 7) CAN BE CHANGED INVOKING VDASCO
+; OR VIA ANSI PRIVATE ESC SEQ. (SEE ANSI.ASM FOR DETAILS)
+;
 TMS_INITVDU:	; V9958 REGISTER SET
 	.DB	$04		; REG 0 - NO EXTERNAL VID, SET M4 = 1 FOR 80 COLS
 TMS_INITVDU_REG_1:
@@ -1069,7 +1105,7 @@ TMS_INITVDU_REG_1:
 	.DB	$00		; REG 9
 	.DB	$00		; REG 10 - COLOUR TABLE A14-A16 (TMS_FNTVADDR - $1000)
 ;
-#ELSE 		; _______TMS9918 REGISTER SET ### JLC Mod for JBL compatibility & MODE II Readiness ###_______
+#ELSE 		; _______TMS9918 REGISTER SET_______
 ;
 TMS_INITVDU:	; V9918 REGISTER SET
 	.DB	$00		; REG 0 - SET TEXT MODE, NO EXTERNAL VID
@@ -1080,18 +1116,7 @@ TMS_INITVDU_REG_1:
 	.DB	$00		; REG 4 - SET PATTERN GENERATOR TABLE TO (TMS_FNTVADDR -> $0000)
 	.DB	$76		; REG 5 - SPRITE ATTRIBUTE IRRELEVANT, SET TO MODE II DEFAULT VALUE
 	.DB	$03		; REG 6 - NO SPRITE GENERATOR TABLE, SET TO MODE II DEFAULT VALUE
-	.DB	$E1		; REG 7 - GREY ON BLACK ### JLC Mod Change default text color for better readability YMMV ###
-;
-;TMS_INITVDU:
-;	.DB	$00		; REG 0 - NO EXTERNAL VID
-;TMS_INITVDU_REG_1:
-;	.DB	$50		; REG 1 - ENABLE SCREEN, SET TEXT MODE & BLANK SCREEN ### JLC comment fix (NOT MODE 1) ###
-;	.DB	$00		; REG 2 - PATTERN NAME TABLE := 0
-;	.DB	$00		; REG 3 - NO COLOR TABLE
-;	.DB	$01		; REG 4 - SET PATTERN GENERATOR TABLE TO (TMS_FNTVADDR -> $0800)
-;	.DB	$00		; REG 5 - SPRITE ATTRIBUTE IRRELEVANT
-;	.DB	$00		; REG 6 - NO SPRITE GENERATOR TABLE
-;	.DB	$F0		; REG 7 - WHITE ON TRANSPARENT
+	.DB	$E1		; REG 7 - TEXT COLOR
 ;
 #ENDIF
 ;
@@ -1101,3 +1126,29 @@ TMS_INITVDULEN	.EQU	$ - TMS_INITVDU
 #IF (CPUFAM == CPU_Z180)
 TMS_DCNTL	.DB	$00	; SAVE Z180 DCNTL AS NEEDED
 #ENDIF
+;
+; ### JLC Mod
+;===============================================================================
+; BASIC ANSI to TMS COLOR CONVERSION TABLE (NIBBLES FOR FOREGROUND & BACKGROUND)
+;          Follows RomWBW System Guide Chapter 8, HBIOS Reference
+;-------------------------------------------------------------------------------
+;					 ANSI Color 		TMS Equivalent
+;-------------------------------------------------------------------------------
+;					 0 Black		1
+;					 1 Red			8
+;					 2 Green		2
+;					 3 Brown		A
+;					 4 Blue			4
+;					 5 Magenta		6
+;					 6 Cyan			C
+;					 7 White		F
+;					 8 Gray			E
+;					 9 Light Red		9
+;					 A Light Green		3
+;					 B Yellow		B
+;	 				 C Light Blue		5
+;	 				 D Light Magenta	D
+;	 				 E Light Cyan		7
+;	 				 F Bright White		F
+;===============================================================================
+;

Source/HBIOS/uart.asm

@@ -216,19 +216,8 @@ UART_INIT1:
 	LD	A,(IY+1)		; GET UART TYPE
 	OR	A			; SET FLAGS
 	JR	Z,UART_INIT2		; SKIP IF ZERO (NOT DETECTED)
-	PUSH	AF			; SAVE TYPE VALUE
 	CALL	UART_PRTCFG		; PRINT IF NOT ZERO
-	POP	AF			; RESTORE TYPE VALUE
-	BIT	UART_CTSBAD,A		; CTS STALL?
-	JR	Z,UART_INIT2		; IF NOT, SKIP AHEAD
-	CALL	NEWLINE			; FORMATTING
-	PRTS("UART$")			; FORMATTING
-	LD	A,(IY)			; DEVICE NUM
-	CALL	PRTDECB			; PRINT DEVICE NUM
-	PRTS(": $")			; FORMATTING
-	LD	DE,UART_STR_BADCTS	; LOAD WARNING MESSAGE
-	CALL	WRITESTR		; ... AND PRINT IT
-;	
+;
 UART_INIT2:
 	POP	BC			; RESTORE LOOP CONTROL
 	INC	C			; NEXT UNIT
@@ -963,6 +952,11 @@ UART_PRTCFG2:
 	PRTS(" AFC$")
 ;
 UART_PRTCFG3:
+	BIT	UART_CTSBAD,(IY+1)	; GET BADCTS BIT
+	JR	Z,UART_PRTCFG4
+	PRTS(" NO_CTS!$")
+;
+UART_PRTCFG4:
 ;
 	XOR	A
 	RET
@@ -1023,8 +1017,6 @@ UART_STR_16850		.DB	"16850$"
 ;
 UART_PAR_MAP		.DB	"NONENMNS"
 ;
-UART_STR_BADCTS		.DB	"CTS STALL, HARDWARE FLOW CONTROL SUSPENDED$"
-;
 ; WORKING VARIABLES
 ;
 UART_DEV		.DB	0		; DEVICE NUM USED DURING INIT

Source/HBIOS/vga.asm

@@ -237,6 +237,10 @@ VGA_VDASAT:
 	JR	VGA_VDASCO2	; IMPLEMENT SETTING
 
 VGA_VDASCO:
+	; WE HANDLE ONLY PER-CHARACTER COLORS (D=0)
+	LD	A,D		; GET CHAR/SCREEN SCOPE
+	OR	A		; CHARACTER?
+	JR	NZ,VGA_VDASCO3	; IF NOT, JUST RETURN
 	; INCOMING IS:  IBGRIBGR (I=INTENSITY, B=BLUE, G=GREEN, R=RED)
 	; TRANSFORM TO: -RGBIRGB (DISCARD INTENSITY BIT IN HIGH NIBBLE)
 	;

Source/Images/Build.cmd

@@ -1,8 +1,9 @@
 @echo off
 setlocal
 
-::call BuildDisk.cmd bp hd wbw_hd512 || exit /b
-::goto :eof
+:: call BuildDisk.cmd bp hd wbw_hd1k
+:: copy /b hd1k_prefix.dat + ..\..\Binary\hd1k_bp.img + ..\..\Binary\hd1k_cpm22.img + ..\..\Binary\hd1k_zsdos.img + ..\..\Binary\hd1k_nzcom.img + ..\..\Binary\hd1k_cpm3.img + ..\..\Binary\hd1k_zpm3.img + ..\..\Binary\hd1k_ws4.img ..\..\Binary\hd1k_combo_bp.img || exit /b
+:: goto :eof
 
 echo.
 echo Building Floppy Disk Images...
@@ -42,8 +43,6 @@ call BuildDisk.cmd bascomp hd wbw_hd512 || exit /b
 call BuildDisk.cmd fortran hd wbw_hd512 || exit /b
 call BuildDisk.cmd games hd wbw_hd512 || exit /b
 
-if exist ..\BPBIOS\bpbio-ww.rel call BuildDisk.cmd bp hd wbw_hd512 || exit /b
-
 echo.
 echo Building Combo Disk (512 directory entry format) Image...
 copy /b ..\..\Binary\hd512_cpm22.img + ..\..\Binary\hd512_zsdos.img + ..\..\Binary\hd512_nzcom.img + ..\..\Binary\hd512_cpm3.img + ..\..\Binary\hd512_zpm3.img + ..\..\Binary\hd512_ws4.img ..\..\Binary\hd512_combo.img || exit /b
@@ -67,7 +66,7 @@ call BuildDisk.cmd bascomp hd wbw_hd1k || exit /b
 call BuildDisk.cmd fortran hd wbw_hd1k || exit /b
 call BuildDisk.cmd games hd wbw_hd1k || exit /b
 
-if exist ..\BPBIOS\bpbio-ww.rel call BuildDisk.cmd bp hd wbw_hd1k || exit /b
+if exist ..\BPBIOS\bp*.rel call BuildDisk.cmd bp hd wbw_hd1k || exit /b
 
 copy hd1k_prefix.dat ..\..\Binary\ || exit /b
 

Source/Images/Makefile

@@ -19,7 +19,7 @@ HD1KIMGS = hd1k_cpm22.img hd1k_zsdos.img hd1k_nzcom.img \
 HD1KXIMGS = hd1k_z80asm.img hd1k_aztecc.img hd1k_hitechc.img \
 	hd1k_bascomp.img hd1k_fortran.img hd1k_games.img \
 	hd1k_tpascal.img hd1k_qpm.img hd1k_blank.img
-# HD1KIMGS += hd1k_bp.img
+HD1KXIMGS += hd1k_bp.img
 
 HD512PREFIX =
 HD1KPREFIX = hd1k_prefix.dat

Source/Makefile

@@ -2,12 +2,12 @@
 # order is actually important, because of build dependencies
 #
 
-.PHONY: doc prop shared bp images rom zrc z1rcc zzrcc
+.PHONY: doc prop shared bp images rom zrc z1rcc zzrcc zrc512
 
 .ONESHELL:
 .SHELLFLAGS = -cex
 
-all: prop shared images rom zrc z1rcc zzrcc
+all: prop shared bp images rom zrc z1rcc zzrcc zrc512
 
 doc:
 	$(MAKE) --directory Doc $(ACTION)
@@ -50,6 +50,9 @@ z1rcc:
 zzrcc:
 	$(MAKE) --directory ZZRCC $(ACTION)
 
+zrc512:
+	$(MAKE) --directory ZRC512 $(ACTION)
+
 clean: ACTION=clean
 clean: all
 

Source/RomDsk/Build.cmd

@@ -24,27 +24,27 @@ set RomApps2=fdu format survey sysgen talk timer cpuspd
 
 set RomApps=
 
-copy NUL rom128_wbw.dat
-copy NUL rom128_una.dat
+copy NUL rom128_wbw.dat  || exit /b
+copy NUL rom128_una.dat || exit /b
 
 :: MakeDisk <OutputFile> <ImageSize> <Format> <Directory> <Bios>
 
 set RomApps=%RomApps1%
 
-call :MakeDisk rom256_wbw wbw_rom256 ROM_256KB 0x20000 wbw
-call :MakeDisk rom256_una wbw_rom256 ROM_256KB 0x20000 una
+call :MakeDisk rom256_wbw wbw_rom256 ROM_256KB 0x20000 wbw || exit /b
+call :MakeDisk rom256_una wbw_rom256 ROM_256KB 0x20000 una || exit /b
 
 set RomApps=%RomApps1% %RomApps2%
 
-call :MakeDisk rom512_wbw wbw_rom512 ROM_512KB 0x60000 wbw
-call :MakeDisk rom512_una wbw_rom512 ROM_512KB 0x60000 una
+call :MakeDisk rom512_wbw wbw_rom512 ROM_512KB 0x60000 wbw || exit /b
+call :MakeDisk rom512_una wbw_rom512 ROM_512KB 0x60000 una || exit /b
 
-call :MakeDisk rom1024_wbw wbw_rom1024 ROM_1024KB 0xE0000 wbw
-call :MakeDisk rom1024_una wbw_rom1024 ROM_1024KB 0xE0000 una
+call :MakeDisk rom1024_wbw wbw_rom1024 ROM_1024KB 0xE0000 wbw || exit /b
+call :MakeDisk rom1024_una wbw_rom1024 ROM_1024KB 0xE0000 una || exit /b
 
-call :MakeDisk ram512_wbw wbw_ram512 RAM_512KB 0x40000 wbw
+call :MakeDisk ram512_wbw wbw_ram512 RAM_512KB 0x40000 wbw || exit /b
 
-call :MakeDisk ram1024_wbw wbw_ram1024 RAM_1024KB 0xC0000 wbw
+call :MakeDisk ram1024_wbw wbw_ram1024 RAM_1024KB 0xC0000 wbw || exit /b
 
 goto :eof