Fix for CP/M 3 Floppy Boot

- CP/M 3 ldrbios had not been properly updated for device type id change. - ASSIGN command was not handling DPB's correctly due to device type id change.
Fix Makefiles
2026-02-07 06:53:13 -06:00 · 2023-10-13 10:29:43 -07:00 · 2023-10-12 17:45:00 -07:00 · 2023-10-12 17:25:40 -07:00 · 2023-10-12 12:49:05 -07:00 · 2023-10-10 14:09:21 -07:00
58 changed files with 175 additions and 117 deletions
--- a/Applications.pdf
+++ b/Applications.pdf
--- a/Catalog.pdf
+++ b/Catalog.pdf
--- a/Errata.pdf
+++ b/Errata.pdf
--- a/Applications.pdf
+++ b/Applications.pdf
--- a/Doc/RomWBW
+++ b/Doc/RomWBW
--- a/Doc/RomWBW
+++ b/Doc/RomWBW
--- a/ReadMe.md
+++ b/ReadMe.md
@@ -3,7 +3,7 @@
 **RomWBW ReadMe** \
 Version 3.4 \
 Wayne Warthen  ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \
-08 Oct 2023
+09 Oct 2023

 # Overview

--- a/ReadMe.txt
+++ b/ReadMe.txt
@@ -1,6 +1,6 @@
 RomWBW ReadMe
 Wayne Warthen (wwarthen@gmail.com)
-08 Oct 2023
+09 Oct 2023



--- a/Source/Apps/FAT/ReadMe.txt
+++ b/Source/Apps/FAT/ReadMe.txt
@@ -1,7 +1,7 @@
 RomWBW HBIOS CP/M FAT Utility ("FAT.COM")

 Author: Wayne Warthen
-Updated: 12-Apr-2021
+Updated: 12-Oct-2023

 Application to manipulate and exchange files with a FAT (DOS)
 filesystem.  Runs on any HBIOS hosted CP/M implementation.
@@ -101,4 +101,5 @@ HISTORY:
  11-Oct-2019: v0.9.7 (beta) fix FORMAT to use existing partition table entries
                             add attributes to directory listing
  12-Apr-2021: v0.9.8 (beta) support CP/NET drives
+  12-Oct-2023: v0.9.9 (beta) handle updated HBIOS Disk Device call
 		      
--- a/Source/Apps/FAT/fat.com
+++ b/Source/Apps/FAT/fat.com
--- a/Source/Apps/assign.asm
+++ b/Source/Apps/assign.asm
@@ -32,6 +32,7 @@
 ;                    Use CPM3 BDOS direct BIOS call to get DRVTBL adr
 ;   2023-06-19 [WBW] Update for revised DIODEVICE API
 ;   2023-09-19 [WBW] Added CHUSB & CHSD device support
+;   2023-10-13 [WBW] Fixed DPH creation to select correct DPB
 ;_______________________________________________________________________________
 ;
 ; ToDo:
@@ -665,10 +666,10 @@ makdphwbw:	; determine appropriate dpb (WBW mode, unit number in A)
 	jr	makdph0		; jump ahead
 makdph00:	
 	ld	e,6		; assume floppy
-	cp	$10		; floppy?
+	cp	$01		; floppy?
 	jr	z,makdph0	; yes, jump ahead
 	ld	e,3		; assume ram floppy
-	cp	$20		; ram floppy?
+	cp	$02		; ram floppy?
 	jr	z,makdph0	; yes, jump ahead
 	ld	e,4		; everything else is assumed to be hard disk
 	jr	makdph0		; yes, jump ahead
@@ -1935,13 +1936,13 @@ stack	.equ	$		; stack top
 ; Messages
 ;
 indent	.db	"   ",0
-msgban1	.db	"ASSIGN v1.7 for RomWBW CP/M ",0
+msgban1	.db	"ASSIGN v1.8 for RomWBW CP/M ",0
 msg22	.db	"2.2",0
 msg3	.db	"3",0
-msbban2	.db	", 19-Sep-2023",0
+msbban2	.db	", 13-Oct-2023",0
 msghb	.db	" (HBIOS Mode)",0
 msgub	.db	" (UBIOS Mode)",0
-msgban3	.db	"Copyright 2021, Wayne Warthen, GNU GPL v3",0
+msgban3	.db	"Copyright 2023, Wayne Warthen, GNU GPL v3",0
 msguse	.db	"Usage: ASSIGN D:[=[{D:|<device>[<unitnum>]:[<slicenum>]}]][,...]",13,10
 	.db	"  ex. ASSIGN           (display all active assignments)",13,10
 	.db	"      ASSIGN /?        (display version and usage)",13,10
--- a/Source/CPM3/biosldr.z80
+++ b/Source/CPM3/biosldr.z80
@@ -346,8 +346,7 @@ read:
 	ld	b,17h			; HBIOS DEVICE function
 	rst	08			; Do it, D=device type
 	ld	a,d			; put in accum
-	and	0F0h			; isolate high bits
-	cp	10h			; floppy?
+	cp	01h			; floppy?
 	jr	nz,read2		; if not, do LBA i/o
 	
 	; Floppy I/O
--- a/Source/Doc/UserGuide.md
+++ b/Source/Doc/UserGuide.md
@@ -2363,6 +2363,53 @@ You can also contact Phillip for detailed information on the Z180
 implementation of FreeRTOS for RomWBW.
 [feilipu](https://github.com/feilipu)

+## Fuzix
+
+Fuzix is a Unix-ish operating system for small systems.  It is the work 
+of Alan Cox and is hosted on GitHub at
+<https://github.com/EtchedPixels/FUZIX>. Fuzix itself is a stand-alone 
+operating system, but it frequently utilizes RomWBW to boot and launch 
+on RomWBW-supported platforms.
+
+For those Fuzix platforms that leverage RomWBW for startup, you will
+program your ROM with the normal RomWBW ROM -- there
+is no Fuzix-specific ROM.  A Fuzix disk image for your system is then
+written to your disk media.  After booting your system via the normal
+RomWBW ROM, you start Fuzix simply by choosing the disk device
+containing the Fuzix image at the RomWBW Loader prompt.
+
+To create a Fuzix disk image:
+
+* Locate and download the Fuzix disk image for your system from
+  <https://www.fuzix.org/>.
+
+* Remove the 1KB header from the image file.  The Fuzix disk images
+  are built to run under an emulator that requires a 1KB prefix.  You
+  must remove this prefix before writing the image to your physical
+  disk media.  Unix dd is the easiest way to do this:
+  
+  `dd bs=1024 skip=1 if=sc126-0.3.ide of=sc126-0.3.trimmed`
+
+* Write the trimmed image to your disk media.  This can also be
+  done with dd or with Win32DiskImager under Windows.
+
+To boot into Fuzix:
+
+* Power-up or reset your system.  RomWBW should load normally
+  and bring you to the RomWBW Boot Loader prompt.
+
+* Change your baud rate to 38,400.  This can be done from the
+  RomWBW Boot Loader prompt with the following command:
+
+  `I 0 38400`
+
+  You will also need to change your terminal baud rate at this time.
+
+* At the `bootdev:` prompt, enter `hda1`.  Fuzix should load and
+  you will be prompted for a date/time.
+
+* At the `login:` prompt, enter `root`.  No password is required.
+
 # Custom Applications

 The operation of the RomWBW hosted operating systems is enhanced through
--- a/Source/HBIOS/Bank
+++ b/Source/HBIOS/Bank
@@ -27,7 +27,18 @@ Bank ID		Module		Start	Size
 0x04 - N	ROM Disk Data


-RAM Bank Layout
+Typical ROM Bank Layout
+
+Bank ID         Usage
+-------         ------
+0x00            Boot Bank (HBIOS image)
+0x01		ROM Loader, Monitor, ROM OSes
+0x02		ROM Applications
+0x03		Reserved
+0x04-0x0F	ROM Disk Banks
+
+
+Typical RAM Bank Layout

 Bank ID         Usage
 -------         ------
@@ -39,7 +50,7 @@ Bank ID         Usage
 0x8F            Common


-ROMless Bank Layout
+Typical ROMless Bank Layout

 Bank ID         Usage
 -------         ------
--- a/Source/HBIOS/Config/DUO_std.asm
+++ b/Source/HBIOS/Config/DUO_std.asm
@@ -43,6 +43,5 @@ PCFENABLE	.SET	TRUE		; ENABLE PCF8584 I2C CONTROLLER
 MDFFENABLE	.SET	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
 UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-;UARTCFG	.SET	UARTCFG | SER_RTS
 ;
 ESPENABLE	.SET	TRUE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
--- a/Source/HBIOS/Config/DYNO_std.asm
+++ b/Source/HBIOS/Config/DYNO_std.asm
@@ -34,8 +34,6 @@ Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
 Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 ;
 ASCIENABLE	.SET	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
-;ASCI0CFG	.SET	SER_115200_8N1	; ASCI 0: SERIAL LINE CONFIG
-;ASCI1CFG	.SET	SER_115200_8N1	; ASCI 1: SERIAL LINE CONFIG
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 ;
--- a/Source/HBIOS/Config/MBC_std.asm
+++ b/Source/HBIOS/Config/MBC_std.asm
@@ -47,7 +47,6 @@ ICMENABLE	.SET	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
 PKDENABLE	.SET	TRUE		; ENABLES DSKY NG PKD DRIVER (8259)
 ;
 UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-;UARTCFG	.SET	UARTCFG | SER_RTS
 ;
 ESPENABLE	.SET	TRUE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
 ;
--- a/Source/HBIOS/Config/ZETA2_std.asm
+++ b/Source/HBIOS/Config/ZETA2_std.asm
@@ -31,7 +31,6 @@ INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 CRTACT		.SET	TRUE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
 UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-;UARTCFG	.SET	UARTCFG | SER_RTS
 UARTSBC		.SET	TRUE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
--- a/Source/HBIOS/Config/ZETA_std.asm
+++ b/Source/HBIOS/Config/ZETA_std.asm
@@ -31,7 +31,6 @@ INTMODE		.SET	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 CRTACT		.SET	TRUE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
 UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-;UARTCFG	.SET	UARTCFG | SER_RTS
 UARTSBC		.SET	TRUE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
--- a/Source/HBIOS/cfg_duo.asm
+++ b/Source/HBIOS/cfg_duo.asm
@@ -30,7 +30,7 @@ CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_UNSUP	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	8000000		; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
--- a/Source/HBIOS/cfg_dyno.asm
+++ b/Source/HBIOS/cfg_dyno.asm
@@ -30,7 +30,7 @@ CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
--- a/Source/HBIOS/cfg_heath.asm
+++ b/Source/HBIOS/cfg_heath.asm
@@ -30,7 +30,7 @@ CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	7372800		; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
--- a/Source/HBIOS/cfg_master.asm
+++ b/Source/HBIOS/cfg_master.asm
@@ -27,7 +27,7 @@ CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	8000000		; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
--- a/Source/HBIOS/cfg_mbc.asm
+++ b/Source/HBIOS/cfg_mbc.asm
@@ -30,7 +30,7 @@ CPUSPDCAP	.EQU	SPD_HILO	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_LOW		; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	8000000		; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
--- a/Source/HBIOS/cfg_mk4.asm
+++ b/Source/HBIOS/cfg_mk4.asm
@@ -30,7 +30,7 @@ CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
--- a/Source/HBIOS/cfg_n8.asm
+++ b/Source/HBIOS/cfg_n8.asm
@@ -30,7 +30,7 @@ CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
--- a/Source/HBIOS/cfg_rcz180.asm
+++ b/Source/HBIOS/cfg_rcz180.asm
@@ -30,7 +30,7 @@ CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
--- a/Source/HBIOS/cfg_rcz280.asm
+++ b/Source/HBIOS/cfg_rcz280.asm
@@ -30,7 +30,7 @@ CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	12000000	; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
--- a/Source/HBIOS/cfg_rcz80.asm
+++ b/Source/HBIOS/cfg_rcz80.asm
@@ -30,7 +30,7 @@ CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	7372800		; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
@@ -46,7 +46,7 @@ RTCIO		.EQU	$C0		; RTC LATCH REGISTER ADR
 KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
 KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
 ;
-CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCENABLE	.EQU	TRUE		; ENABLE ZILOG CTC SUPPORT
 CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
--- a/Source/HBIOS/cfg_rph.asm
+++ b/Source/HBIOS/cfg_rph.asm
@@ -30,7 +30,7 @@ CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
--- a/Source/HBIOS/cfg_s100.asm
+++ b/Source/HBIOS/cfg_s100.asm
@@ -30,7 +30,7 @@ CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_57600_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_57600_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
--- a/Source/HBIOS/cfg_sbc.asm
+++ b/Source/HBIOS/cfg_sbc.asm
@@ -30,7 +30,7 @@ CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	8000000		; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
--- a/Source/HBIOS/cfg_scz180.asm
+++ b/Source/HBIOS/cfg_scz180.asm
@@ -30,7 +30,7 @@ CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
--- a/Source/HBIOS/cfg_z80retro.asm
+++ b/Source/HBIOS/cfg_z80retro.asm
@@ -30,7 +30,7 @@ CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	14745600	; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
--- a/Source/HBIOS/cfg_zeta.asm
+++ b/Source/HBIOS/cfg_zeta.asm
@@ -30,7 +30,7 @@ CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	20000000	; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
--- a/Source/HBIOS/cfg_zeta2.asm
+++ b/Source/HBIOS/cfg_zeta2.asm
@@ -30,7 +30,7 @@ CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	8000000		; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
--- a/Source/HBIOS/ctc.asm
+++ b/Source/HBIOS/ctc.asm
@@ -25,7 +25,7 @@ CTC_TIM256CFG	.EQU	%00110111	; CTC TIMER/256 MODE CONFIG
 ; DETERMINE WHICH CHANNEL CAUSED AN INTERRUPT.
 ;==================================================================================================
 ;
-#IF (INTMODE != 2)
+#IF (CTCTIMER & (INTMODE != 2))
 	.ECHO	"*** WARNING: CTC TIMER DISABLED -- INTMODE 2 REQUIRED!!!\n"
 #ENDIF
 ;
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -2302,29 +2302,6 @@ HB_BOOTDLY:
 	LD	(CB_CONDEV),A		; SAVE IT
 HB_CONRDY:
 ;
-; MOST SERIAL PORTS ARE CONFIGURED WITH HARDWARE FLOW CONTROL ENABLED.
-; IF THERE IS A PROBLEM WITH THE RTS SIGNAL, THEN OUTPUT TO THE CONSOLE
-; WILL BE STALLED WHICH CAN LEAD A USER TO THINK THE SYSTEM IS TOTALLY
-; DEAD WHEN, IN FACT, IT IS JUST WAITING FOR RTS TO BE ASSERTED.  ALSO,
-; IF THE USER IS BOOTING TO A CRT DEVICE AND DISCONNECTS THE CONSOLE
-; SERIAL PORT, THE SYSTEM WILL WAIT FOR RTS AND NEVER BOOT.  SO, HERE
-; WE SAVE THE ACTIVE CONSOLE CONFIGURATION, THEN TURN OFF HARDWARE
-; FLOW CONTROL.  THE ORIGINAL CONFIGURATION WILL BE RESTORED BELOW
-; PRIOR TO LAUNCING THE ROM LOADER.
-;
-	; RETRIEVE THE CONFIG FROM THE CONSOLE PORT
-	LD	B,BF_CIOQUERY		; HBIOS QUERY CIO CONFIG
-	LD	A,(CB_CONDEV)		; GET CONSOLE DEVICE
-	LD	(HB_BOOTCON),A		; SAVE IT FOR LATER
-	LD	C,A			; BOOT CONSOLE TO C
-	CALL	HB_DISPATCH		; INTERNAL HBIOS CALL
-	LD	(HB_BOOTCFG),DE		; SAVE CONFIG
-	RES	5,D			; CLEAR RTS BIT
-	LD	B,BF_CIOINIT		; HBIOS CIO INIT
-	LD	A,(CB_CONDEV)		; GET CONSOLE DEVICE
-	LD	C,A			; BOOT CONSOLE TO C
-	CALL	HB_DISPATCH		; INTERNAL HBIOS CALL
-
 #IF (WBWDEBUG == USEMIO)		; OUTPUT ANY CACHED DEBUG TEXT
 	LD	HL,MIOOUTPTR
 	LD	E,(HL)
@@ -2891,16 +2868,6 @@ INITSYS3:
 	CALL	NZ,WRITESTR		; OUTPUT IF CONSOLE MOVED
 ;
 INITSYS3A:
-;
-; RESTORE BOOT CONSOLE CONFIGURATION
-;
-	CALL	LDELAY			; ALLOW SERIAL PORT TO FLUSH
-	LD	B,BF_CIOINIT		; HBIOS CIO INIT
-	LD	A,(HB_BOOTCON)		; ORIGINAL BOOT CONSOLE DEVICE
-	LD	C,A			; BOOT CONSOLE TO C
-	LD	DE,(HB_BOOTCFG)		; SAVED ORIGINAL CONSOLE CFG
-	CALL	HB_DISPATCH		; INTERNAL HBIOS CALL
-;
 	CALL	PRTSUM			; PRINT UNIT/DEVICE SUMMARY TABLE
 ;
 #IF 0
--- a/Source/HBIOS/std.asm
+++ b/Source/HBIOS/std.asm
@@ -640,27 +640,26 @@ RAMD_BNKS	.EQU	(BID_RAMDN - BID_RAMD0 + 1)
 ;
 #ENDIF
 ;
-#IF TRUE
-	.ECHO "BID_BUF: " \ .ECHO BID_BUF \ .ECHO "\n"
-	.ECHO "BID_AUX: " \ .ECHO BID_AUX \ .ECHO "\n"
-	.ECHO "BID_BIOS: " \ .ECHO BID_BIOS \ .ECHO "\n"
-	.ECHO "BID_USR: " \ .ECHO BID_USR \ .ECHO "\n"
-	.ECHO "BID_COM: " \ .ECHO BID_COM \ .ECHO "\n"
-
-	.ECHO "BID_BOOT: " \ .ECHO BID_BOOT \ .ECHO "\n"
-	.ECHO "BID_IMG0: " \ .ECHO BID_IMG0 \ .ECHO "\n"
-	.ECHO "BID_IMG1: " \ .ECHO BID_IMG1 \ .ECHO "\n"
-	.ECHO "BID_IMG2: " \ .ECHO BID_IMG2 \ .ECHO "\n"
-
-	.ECHO "BID_ROMD0: " \ .ECHO BID_ROMD0 \ .ECHO "\n"
-	.ECHO "BID_ROMDN: " \ .ECHO BID_ROMDN \ .ECHO "\n"
-	.ECHO "BID_RAMD0: " \ .ECHO BID_RAMD0 \ .ECHO "\n"
-	.ECHO "BID_RAMDN: " \ .ECHO BID_RAMDN \ .ECHO "\n"
-
+#IF FALSE
+	.ECHO "--- RAM/ROM CAPACITY ---\n"
 	.ECHO "BID_ROM0: " \ .ECHO BID_ROM0 \ .ECHO "\n"
 	.ECHO "BID_ROMN: " \ .ECHO BID_ROMN \ .ECHO "\n"
 	.ECHO "BID_RAM0: " \ .ECHO BID_RAM0 \ .ECHO "\n"
 	.ECHO "BID_RAMN: " \ .ECHO BID_RAMN \ .ECHO "\n"
+	.ECHO "--- BANK LAYOUT ---\n"
+	.ECHO "BID_BOOT: " \ .ECHO BID_BOOT \ .ECHO "\n"
+	.ECHO "BID_IMG0: " \ .ECHO BID_IMG0 \ .ECHO "\n"
+	.ECHO "BID_IMG1: " \ .ECHO BID_IMG1 \ .ECHO "\n"
+	.ECHO "BID_IMG2: " \ .ECHO BID_IMG2 \ .ECHO "\n"
+	.ECHO "BID_ROMD0: " \ .ECHO BID_ROMD0 \ .ECHO "\n"
+	.ECHO "BID_ROMDN: " \ .ECHO BID_ROMDN \ .ECHO "\n"
+	.ECHO "BID_BIOS: " \ .ECHO BID_BIOS \ .ECHO "\n"
+	.ECHO "BID_RAMD0: " \ .ECHO BID_RAMD0 \ .ECHO "\n"
+	.ECHO "BID_RAMDN: " \ .ECHO BID_RAMDN \ .ECHO "\n"
+	.ECHO "BID_BUF: " \ .ECHO BID_BUF \ .ECHO "\n"
+	.ECHO "BID_AUX: " \ .ECHO BID_AUX \ .ECHO "\n"
+	.ECHO "BID_USR: " \ .ECHO BID_USR \ .ECHO "\n"
+	.ECHO "BID_COM: " \ .ECHO BID_COM \ .ECHO "\n"
 #ENDIF
 ;
 ; MEMORY LAYOUT
--- a/Source/HBIOS/uart.asm
+++ b/Source/HBIOS/uart.asm
@@ -52,6 +52,7 @@ UART_EFR		.EQU	2	; LCR=$BF: ENHANCED FEATURE REG (READ/WRITE)
 UART_INTACT		.EQU	7	; INT RCV ACTIVE BIT
 UART_FIFOACT		.EQU	6	; FIFO ACTIVE BIT
 UART_AFCACT		.EQU	5	; AUTO FLOW CONTROL ACTIVE BIT
+UART_CTSBAD		.EQU	4	; CTS STALL DETECTED
 ;
 #IF (PLATFORM == PLT_DUO)
 UARTSBASE		.EQU	$58
@@ -173,7 +174,19 @@ UART_INITUNIT:
 	LD	A,(HL)			; PUT IN ACCUM
 	INC	(HL)			; INCREMENT IT (FOR NEXT LOOP)
 	LD	(IY),A			; UDPATE UNIT NUM
+;
+	; CHECK FOR CTS STALL (CTS SHOULD BE ASSERTED HERE)
+	BIT	5,(IY+5)		; IS RTS REQUESTED?
+	JR	Z,UART_INITUNIT1	; IF NOT, SKIP CTS CHECK
+	UART_INP(UART_MSR)		; LOAD MODEM STATUS REG
+	BIT	4,A			; CTS
+	JR	NZ,UART_INITUNIT1	; IF CTS HIGH (GOOD), SKIP AHEAD
+;
+	; CTS LOOKS BORKED, SHUT OFF RTS/CTS FLOW CONTROL
+	RES	5,(IY+5)		; CLEAR RTS BIT OF CONFIG MSB
+	SET	UART_CTSBAD,(IY+1)	; RECORD BAD CTS
 ;	
+UART_INITUNIT1:
 	; SET DEFAULT CONFIG
 	LD	DE,-1			; LEAVE CONFIG ALONE
 	JP	UART_INITDEVX		; IMPLEMENT IT AND RETURN
@@ -197,8 +210,21 @@ UART_INIT1:
 	
 	LD	A,(IY+1)		; GET UART TYPE
 	OR	A			; SET FLAGS
-	CALL	NZ,UART_PRTCFG		; PRINT IF NOT ZERO
-
+	JR	Z,UART_INIT2		; SKIP IF ZERO (NOT DETECTED)
+	PUSH	AF			; SAVE TYPE VALUE
+	CALL	UART_PRTCFG		; PRINT IF NOT ZERO
+	POP	AF			; RESTORE TYPE VALUE
+	BIT	UART_CTSBAD,A		; CTS STALL?
+	JR	Z,UART_INIT2		; IF NOT, SKIP AHEAD
+	CALL	NEWLINE			; FORMATTING
+	PRTS("UART$")			; FORMATTING
+	LD	A,(IY)			; DEVICE NUM
+	CALL	PRTDECB			; PRINT DEVICE NUM
+	PRTS(": $")			; FORMATTING
+	LD	DE,UART_STR_BADCTS	; LOAD WARNING MESSAGE
+	CALL	WRITESTR		; ... AND PRINT IT
+;	
+UART_INIT2:
 	POP	BC			; RESTORE LOOP CONTROL
 	INC	C			; NEXT UNIT
 	DJNZ	UART_INIT1		; LOOP TILL DONE
@@ -992,6 +1018,8 @@ UART_STR_16850		.DB	"16850$"
 ;
 UART_PAR_MAP		.DB	"NONENMNS"
 ;
+UART_STR_BADCTS		.DB	"CTS STALL, HARDWARE FLOW CONTROL SUSPENDED$"
+;
 ; WORKING VARIABLES
 ;
 UART_DEV		.DB	0		; DEVICE NUM USED DURING INIT
--- a/Source/Images/Common/All/SUPERSUB.COM
+++ b/Source/Images/Common/All/SUPERSUB.COM
--- a/Source/Images/Common/All/SUPERSUB.DOC
+++ b/Source/Images/Common/All/SUPERSUB.DOC
@@ -1,4 +1,4 @@
-			SUPERSUB DOCUMENTATION	(revised 09/13/81)
+			SUPERSUB DOCUMENTATION	(revised 09/25/84)
 			----------------------

 						09/05/81
@@ -11,6 +11,17 @@ are familiar with that utility and its use.

 			------------------

+Version 1.3 update:
+
+George Cary has added MP/M capability to version 1.2 of SuperSUB. In
+version 1.3 I fixed a problem that caused SuperSUB to bomb when the
+.SUB file did not end in a 1AH (which is an ascii end-of-file
+character). It was depending on the 1AH to end the file, and ignoring
+the physical end-of-file. Physical end-of-file will now terminate
+properly.			- Jeffrey J. Nonken
+
+			------------------
+
 Version 1.1 update:

 Control-character translation has been added.  This facility works
@@ -138,4 +149,4 @@ NOTES
 5) Interactive mode may be aborted by typing control-C as the first
   character of a line.  Also, all normal CP/M editing characters are
   available.
-
+
--- a/Source/RomDsk/RAM_1024KB/SUPERSUB.COM
+++ b/Source/RomDsk/RAM_1024KB/SUPERSUB.COM
--- a/Source/RomDsk/RAM_512KB/SUPERSUB.COM
+++ b/Source/RomDsk/RAM_512KB/SUPERSUB.COM
--- a/Source/RomDsk/ROM_1024KB/SUPERSUB.COM
+++ b/Source/RomDsk/ROM_1024KB/SUPERSUB.COM
--- a/Source/RomDsk/ROM_512KB/SUPERSUB.COM
+++ b/Source/RomDsk/ROM_512KB/SUPERSUB.COM
--- a/Source/ZRC/Build.cmd
+++ b/Source/ZRC/Build.cmd
@@ -14,8 +14,8 @@ goto :eof
 :build_zrc

 srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x0 0x100 zrc_cfldr.bin -binary -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x100 0x200 zrc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x0 0x200 zrc_cfldr.bin -binary -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x1B8 0x200 zrc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
 srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
 srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ80_zrc.rom -binary -offset 0x24000 -o temp.dat -binary
 move temp.dat ..\..\Binary\hd1k_zrc_prefix.dat
@@ -27,8 +27,8 @@ goto :eof
 :build_zrc_ram

 srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x0 0x100 zrc_cfldr.bin -binary -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x100 0x200 zrc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x0 0x200 zrc_cfldr.bin -binary -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x1B8 0x200 zrc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
 srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
 srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ80_zrc_ram.rom -binary -offset 0x24000 -o temp.dat -binary
 move temp.dat ..\..\Binary\hd1k_zrc_ram_prefix.dat
--- a/Source/ZRC/Makefile
+++ b/Source/ZRC/Makefile
@@ -27,16 +27,16 @@ DIFFPATH = $(DIFFTO)/Binary

 $(HD1KZRCPREFIX):
 	srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
-	srec_cat temp.dat -binary -exclude 0x0 0x100 zrc_cfldr.bin -binary -o temp.dat -binary
-	srec_cat temp.dat -binary -exclude 0x100 0x200 zrc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x0 0x200 zrc_cfldr.bin -binary -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x1B8 0x200 zrc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
 	srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
 	srec_cat temp.dat -binary -exclude 0x24000 0xA4000 $(ZRCROM) -binary -offset 0x24000 -o temp.dat -binary
 	mv temp.dat $@

 $(HD1KZRCRAMPREFIX):
 	srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
-	srec_cat temp.dat -binary -exclude 0x0 0x100 zrc_cfldr.bin -binary -o temp.dat -binary
-	srec_cat temp.dat -binary -exclude 0x100 0x200 zrc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x0 0x200 zrc_cfldr.bin -binary -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x1B8 0x200 zrc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
 	srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
 	srec_cat temp.dat -binary -exclude 0x24000 0xA4000 $(ZRCRAMROM) -binary -offset 0x24000 -o temp.dat -binary
 	mv temp.dat $@
--- a/Source/ZRC/ZRC
+++ b/Source/ZRC/ZRC
@@ -4,8 +4,8 @@ ZRC Disk Prefix Layout
 ---- Bytes ----   --- Sectors ---
 Start   Length    Start   Length    Description
 ------- -------   ------- -------   ---------------------------
-0x00000 0x00100   0       0.5       CF Boot Loader
-0x00100 0x00100   0.5     0.5       RomWBW Partition Table
+0x00000 0x001BE   0       1         CF Boot Loader
+0x001B8 0x00048                     RomWBW Partition Table
 0x00200 0x1EE00   1       247       Unused
 0x1F000 0x01000   248     8         ZRC Monitor v0.7
 0x20000 0x04000   256     32        Unused
@@ -17,9 +17,9 @@ Notes
 -----

 - At startup CPLD ROM is mapped to Z80 CPU address space 0x0000-0x003F, CPU begins execution at 0x0000
- CPLD ROM (CF bootstrap mode) reads CF Boot Loader (256B) from start of CF (MBR) to 0xB000 and runs it
+- CPLD ROM (CF bootstrap mode) reads CF Boot Loader (512B) from start of CF (MBR) to 0xB000 and runs it
 - CF Boot Loader reads ZRC Monitor (4KB) from sectors 0xF8-0xFF of CF to 0xB400 and runs it
 - ZRC Monitor reads 512KB (RomWBW) from sectors 0x120-0x51F of CF into first 512KB of physical RAM
 - ZRC Monitor maps first 32KB of physical RAM to first 32KB of CPU RAM and starts execution at 0x0000

-- WBW 2:30 PM 10/8/2023
+-- WBW 3:30 PM 10/12/2023
--- a/Source/ZRC/zrc_cfldr.bin
+++ b/Source/ZRC/zrc_cfldr.bin
--- a/Source/ZRC/zrc_ptbl.bin
+++ b/Source/ZRC/zrc_ptbl.bin
--- a/Source/ZZRCC/Build.cmd
+++ b/Source/ZZRCC/Build.cmd
@@ -17,8 +17,8 @@ goto :eof
 :build_zzrcc

 srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x0 0x100 zzrcc_cfldr.bin -binary -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x100 0x200 zzrcc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x0 0x200 zzrcc_cfldr.bin -binary -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x1B8 0x200 zzrcc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
 srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrcc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
 srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ280_zzrcc.rom -binary -offset 0x24000 -o temp.dat -binary
 move temp.dat ..\..\Binary\hd1k_zzrcc_prefix.dat
@@ -30,8 +30,8 @@ goto :eof
 :build_zzrcc_ram

 srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x0 0x100 zzrcc_cfldr.bin -binary -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x100 0x200 zzrcc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x0 0x200 zzrcc_cfldr.bin -binary -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x1B8 0x200 zzrcc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
 srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrcc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
 srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ280_zzrcc_ram.rom -binary -offset 0x24000 -o temp.dat -binary
 move temp.dat ..\..\Binary\hd1k_zzrcc_ram_prefix.dat
--- a/Source/ZZRCC/Makefile
+++ b/Source/ZZRCC/Makefile
@@ -27,16 +27,16 @@ DIFFPATH = $(DIFFTO)/Binary

 $(HD1KZZRCCPREFIX):
 	srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
-	srec_cat temp.dat -binary -exclude 0x0 0x100 zzrcc_cfldr.bin -binary -o temp.dat -binary
-	srec_cat temp.dat -binary -exclude 0x100 0x200 zzrcc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x0 0x200 zzrcc_cfldr.bin -binary -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x1B8 0x200 zzrcc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
 	srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrcc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
 	srec_cat temp.dat -binary -exclude 0x24000 0xA4000 $(ZZRCCROM) -binary -offset 0x24000 -o temp.dat -binary
 	mv temp.dat $@

 $(HD1KZZRCCRAMPREFIX):
 	srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
-	srec_cat temp.dat -binary -exclude 0x0 0x100 zzrcc_cfldr.bin -binary -o temp.dat -binary
-	srec_cat temp.dat -binary -exclude 0x100 0x200 zzrcc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x0 0x200 zzrcc_cfldr.bin -binary -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x1B8 0x200 zzrcc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
 	srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrcc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
 	srec_cat temp.dat -binary -exclude 0x24000 0xA4000 $(ZZRCCRAMROM) -binary -offset 0x24000 -o temp.dat -binary
 	mv temp.dat $@
--- a/Source/ZZRCC/ZZRCC
+++ b/Source/ZZRCC/ZZRCC
@@ -4,8 +4,8 @@ ZZRCC Disk Prefix Layout
 ---- Bytes ----   --- Sectors ---
 Start   Length    Start   Length    Description
 ------- -------   ------- -------   ---------------------------
-0x00000 0x00100   0       0.5       CF Boot Loader
-0x00100 0x00100   0.5     0.5       RomWBW Partition Table
+0x00000 0x001BE   0       1         CF Boot Loader
+0x001B8 0x00048                     RomWBW Partition Table
 0x00200 0x1EE00   1       247       Unused
 0x1F000 0x01000   248     8         ZZRCC Monitor v0.5
 0x20000 0x04000   256     32        Unused
@@ -17,9 +17,9 @@ Notes
 -----

 - At startup CPLD ROM is mapped to Z280 CPU address space 0x0000-0x003F, CPU begins execution at 0x0000
- CPLD ROM (CF bootstrap mode) reads CF Boot Loader (256B) from start of CF (MBR) to 0xB000 and runs it
+- CPLD ROM (CF bootstrap mode) reads CF Boot Loader (512B) from start of CF (MBR) to 0xB000 and runs it
 - CF Boot Loader reads ZZRCC Monitor (4KB) from sectors 0xF8-0xFF of CF to 0xB400 and runs it
 - ZZRCC Monitor reads 512KB (RomWBW) from sectors 0x120-0x51F of CF into first 512KB of physical RAM
 - ZZRCC Monitor maps first 32KB of physical RAM to first 32KB of CPU RAM and starts execution at 0x0000

-WBW 2:36 PM 10/8/2023
+-WBW 3:30 PM 10/12/2023
--- a/Source/ZZRCC/zzrcc_cfldr.bin
+++ b/Source/ZZRCC/zzrcc_cfldr.bin
--- a/Source/ZZRCC/zzrcc_ptbl.bin
+++ b/Source/ZZRCC/zzrcc_ptbl.bin
--- a/Source/ver.inc
+++ b/Source/ver.inc
@@ -2,7 +2,7 @@
 #DEFINE	RMN	4
 #DEFINE	RUP	0
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.4.0-dev.5"
+#DEFINE BIOSVER	"3.4.0-dev.9"
 #define rmj	RMJ
 #define rmn	RMN
 #define rup	RUP
--- a/Source/ver.lib
+++ b/Source/ver.lib
@@ -3,5 +3,5 @@ rmn	equ	4
 rup	equ	0
 rtp	equ	0
 biosver	macro
-	db	"3.4.0-dev.5"
+	db	"3.4.0-dev.9"
 	endm
Author	SHA1	Message	Date
Wayne Warthen	b175808a92	Fix for CP/M 3 Floppy Boot - CP/M 3 ldrbios had not been properly updated for device type id change. - ASSIGN command was not handling DPB's correctly due to device type id change.	2023-10-13 10:29:43 -07:00
Wayne Warthen	3e86e79133	Fix Makefiles	2023-10-12 17:45:00 -07:00
Wayne Warthen	3247e67ed4	ZRC and ZZRCC Image Creation Updates - Modified ZRC and ZZRCC image creation scripts to allow up to 0x1B8 of boot code.	2023-10-12 17:25:40 -07:00
Wayne Warthen	bbc84f0c2d	Fix FAT Application API Call FAT application had not been updated to reflect a change in the HBIOS Disk Device API call return data. This is corrected in this check-in. Related discussion in #368.	2023-10-12 12:49:05 -07:00
Wayne Warthen	872d51e9b6	Detect CTS Stall - Detect CTS at startup to ensure it is asserted. If not, disable hardware flow control to avoid stalling the console at boot. Only for UART driver because this is the only place it is currently relevant.	2023-10-10 14:09:21 -07:00
Wayne Warthen	b41f189a4c	Miscellaneous - Add minimal Fuzix instructions to User Guide - Enable CTC auto-detect by default for RCBus. It causes no problems to auto-detect it and it will stop a CTC from generating unexpected interrupts after a soft restart. - Upgrade `SUPERSUB` to v1.3 (previously v1.1)	2023-10-09 16:50:18 -07:00