Fix for CP/M 3 Floppy Boot

- CP/M 3 ldrbios had not been properly updated for device type id change.
- ASSIGN command was not handling DPB's correctly due to device type id change.

Source/Apps/assign.asm

@@ -32,6 +32,7 @@
 ;                    Use CPM3 BDOS direct BIOS call to get DRVTBL adr
 ;   2023-06-19 [WBW] Update for revised DIODEVICE API
 ;   2023-09-19 [WBW] Added CHUSB & CHSD device support
+;   2023-10-13 [WBW] Fixed DPH creation to select correct DPB
 ;_______________________________________________________________________________
 ;
 ; ToDo:
@@ -665,10 +666,10 @@ makdphwbw:	; determine appropriate dpb (WBW mode, unit number in A)
 	jr	makdph0		; jump ahead
 makdph00:	
 	ld	e,6		; assume floppy
-	cp	$10		; floppy?
+	cp	$01		; floppy?
 	jr	z,makdph0	; yes, jump ahead
 	ld	e,3		; assume ram floppy
-	cp	$20		; ram floppy?
+	cp	$02		; ram floppy?
 	jr	z,makdph0	; yes, jump ahead
 	ld	e,4		; everything else is assumed to be hard disk
 	jr	makdph0		; yes, jump ahead
@@ -1935,13 +1936,13 @@ stack	.equ	$		; stack top
 ; Messages
 ;
 indent	.db	"   ",0
-msgban1	.db	"ASSIGN v1.7 for RomWBW CP/M ",0
+msgban1	.db	"ASSIGN v1.8 for RomWBW CP/M ",0
 msg22	.db	"2.2",0
 msg3	.db	"3",0
-msbban2	.db	", 19-Sep-2023",0
+msbban2	.db	", 13-Oct-2023",0
 msghb	.db	" (HBIOS Mode)",0
 msgub	.db	" (UBIOS Mode)",0
-msgban3	.db	"Copyright 2021, Wayne Warthen, GNU GPL v3",0
+msgban3	.db	"Copyright 2023, Wayne Warthen, GNU GPL v3",0
 msguse	.db	"Usage: ASSIGN D:[=[{D:|<device>[<unitnum>]:[<slicenum>]}]][,...]",13,10
 	.db	"  ex. ASSIGN           (display all active assignments)",13,10
 	.db	"      ASSIGN /?        (display version and usage)",13,10

Source/CPM3/biosldr.z80

@@ -346,8 +346,7 @@ read:
 	ld	b,17h			; HBIOS DEVICE function
 	rst	08			; Do it, D=device type
 	ld	a,d			; put in accum
-	and	0F0h			; isolate high bits
-	cp	10h			; floppy?
+	cp	01h			; floppy?
 	jr	nz,read2		; if not, do LBA i/o
 	
 	; Floppy I/O

Source/ZRC/Build.cmd

@@ -14,8 +14,8 @@ goto :eof
 :build_zrc
 
 srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x0 0x100 zrc_cfldr.bin -binary -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x100 0x200 zrc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x0 0x200 zrc_cfldr.bin -binary -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x1B8 0x200 zrc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
 srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
 srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ80_zrc.rom -binary -offset 0x24000 -o temp.dat -binary
 move temp.dat ..\..\Binary\hd1k_zrc_prefix.dat
@@ -27,8 +27,8 @@ goto :eof
 :build_zrc_ram
 
 srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x0 0x100 zrc_cfldr.bin -binary -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x100 0x200 zrc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x0 0x200 zrc_cfldr.bin -binary -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x1B8 0x200 zrc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
 srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
 srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ80_zrc_ram.rom -binary -offset 0x24000 -o temp.dat -binary
 move temp.dat ..\..\Binary\hd1k_zrc_ram_prefix.dat

Source/ZRC/Makefile

@@ -27,16 +27,16 @@ DIFFPATH = $(DIFFTO)/Binary
 
 $(HD1KZRCPREFIX):
 	srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
-	srec_cat temp.dat -binary -exclude 0x0 0x100 zrc_cfldr.bin -binary -o temp.dat -binary
-	srec_cat temp.dat -binary -exclude 0x100 0x200 zrc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x0 0x200 zrc_cfldr.bin -binary -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x1B8 0x200 zrc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
 	srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
 	srec_cat temp.dat -binary -exclude 0x24000 0xA4000 $(ZRCROM) -binary -offset 0x24000 -o temp.dat -binary
 	mv temp.dat $@
 
 $(HD1KZRCRAMPREFIX):
 	srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
-	srec_cat temp.dat -binary -exclude 0x0 0x100 zrc_cfldr.bin -binary -o temp.dat -binary
-	srec_cat temp.dat -binary -exclude 0x100 0x200 zrc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x0 0x200 zrc_cfldr.bin -binary -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x1B8 0x200 zrc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
 	srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
 	srec_cat temp.dat -binary -exclude 0x24000 0xA4000 $(ZRCRAMROM) -binary -offset 0x24000 -o temp.dat -binary
 	mv temp.dat $@

Source/ZRC/ZRC Disk Layout.txt

@@ -4,8 +4,8 @@ ZRC Disk Prefix Layout
 ---- Bytes ----   --- Sectors ---
 Start   Length    Start   Length    Description
 ------- -------   ------- -------   ---------------------------
-0x00000 0x00100   0       0.5       CF Boot Loader
-0x00100 0x00100   0.5     0.5       RomWBW Partition Table
+0x00000 0x001BE   0       1         CF Boot Loader
+0x001B8 0x00048                     RomWBW Partition Table
 0x00200 0x1EE00   1       247       Unused
 0x1F000 0x01000   248     8         ZRC Monitor v0.7
 0x20000 0x04000   256     32        Unused
@@ -17,9 +17,9 @@ Notes
 -----
 
 - At startup CPLD ROM is mapped to Z80 CPU address space 0x0000-0x003F, CPU begins execution at 0x0000
-- CPLD ROM (CF bootstrap mode) reads CF Boot Loader (256B) from start of CF (MBR) to 0xB000 and runs it
+- CPLD ROM (CF bootstrap mode) reads CF Boot Loader (512B) from start of CF (MBR) to 0xB000 and runs it
 - CF Boot Loader reads ZRC Monitor (4KB) from sectors 0xF8-0xFF of CF to 0xB400 and runs it
 - ZRC Monitor reads 512KB (RomWBW) from sectors 0x120-0x51F of CF into first 512KB of physical RAM
 - ZRC Monitor maps first 32KB of physical RAM to first 32KB of CPU RAM and starts execution at 0x0000
 
--- WBW 2:30 PM 10/8/2023
+-- WBW 3:30 PM 10/12/2023

Source/ZZRCC/Build.cmd

@@ -17,8 +17,8 @@ goto :eof
 :build_zzrcc
 
 srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x0 0x100 zzrcc_cfldr.bin -binary -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x100 0x200 zzrcc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x0 0x200 zzrcc_cfldr.bin -binary -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x1B8 0x200 zzrcc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
 srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrcc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
 srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ280_zzrcc.rom -binary -offset 0x24000 -o temp.dat -binary
 move temp.dat ..\..\Binary\hd1k_zzrcc_prefix.dat
@@ -30,8 +30,8 @@ goto :eof
 :build_zzrcc_ram
 
 srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x0 0x100 zzrcc_cfldr.bin -binary -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x100 0x200 zzrcc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x0 0x200 zzrcc_cfldr.bin -binary -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x1B8 0x200 zzrcc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
 srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrcc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
 srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ280_zzrcc_ram.rom -binary -offset 0x24000 -o temp.dat -binary
 move temp.dat ..\..\Binary\hd1k_zzrcc_ram_prefix.dat

Source/ZZRCC/Makefile

@@ -27,16 +27,16 @@ DIFFPATH = $(DIFFTO)/Binary
 
 $(HD1KZZRCCPREFIX):
 	srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
-	srec_cat temp.dat -binary -exclude 0x0 0x100 zzrcc_cfldr.bin -binary -o temp.dat -binary
-	srec_cat temp.dat -binary -exclude 0x100 0x200 zzrcc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x0 0x200 zzrcc_cfldr.bin -binary -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x1B8 0x200 zzrcc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
 	srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrcc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
 	srec_cat temp.dat -binary -exclude 0x24000 0xA4000 $(ZZRCCROM) -binary -offset 0x24000 -o temp.dat -binary
 	mv temp.dat $@
 
 $(HD1KZZRCCRAMPREFIX):
 	srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
-	srec_cat temp.dat -binary -exclude 0x0 0x100 zzrcc_cfldr.bin -binary -o temp.dat -binary
-	srec_cat temp.dat -binary -exclude 0x100 0x200 zzrcc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x0 0x200 zzrcc_cfldr.bin -binary -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x1B8 0x200 zzrcc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
 	srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrcc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
 	srec_cat temp.dat -binary -exclude 0x24000 0xA4000 $(ZZRCCRAMROM) -binary -offset 0x24000 -o temp.dat -binary
 	mv temp.dat $@

Source/ZZRCC/ZZRCC Disk Layout.txt

@@ -4,8 +4,8 @@ ZZRCC Disk Prefix Layout
 ---- Bytes ----   --- Sectors ---
 Start   Length    Start   Length    Description
 ------- -------   ------- -------   ---------------------------
-0x00000 0x00100   0       0.5       CF Boot Loader
-0x00100 0x00100   0.5     0.5       RomWBW Partition Table
+0x00000 0x001BE   0       1         CF Boot Loader
+0x001B8 0x00048                     RomWBW Partition Table
 0x00200 0x1EE00   1       247       Unused
 0x1F000 0x01000   248     8         ZZRCC Monitor v0.5
 0x20000 0x04000   256     32        Unused
@@ -17,9 +17,9 @@ Notes
 -----
 
 - At startup CPLD ROM is mapped to Z280 CPU address space 0x0000-0x003F, CPU begins execution at 0x0000
-- CPLD ROM (CF bootstrap mode) reads CF Boot Loader (256B) from start of CF (MBR) to 0xB000 and runs it
+- CPLD ROM (CF bootstrap mode) reads CF Boot Loader (512B) from start of CF (MBR) to 0xB000 and runs it
 - CF Boot Loader reads ZZRCC Monitor (4KB) from sectors 0xF8-0xFF of CF to 0xB400 and runs it
 - ZZRCC Monitor reads 512KB (RomWBW) from sectors 0x120-0x51F of CF into first 512KB of physical RAM
 - ZZRCC Monitor maps first 32KB of physical RAM to first 32KB of CPU RAM and starts execution at 0x0000
 
--WBW 2:36 PM 10/8/2023
+-WBW 3:30 PM 10/12/2023

Source/ver.inc

@@ -2,7 +2,7 @@
 #DEFINE	RMN	4
 #DEFINE	RUP	0
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.4.0-dev.7"
+#DEFINE BIOSVER	"3.4.0-dev.9"
 #define rmj	RMJ
 #define rmn	RMN
 #define rup	RUP

Source/ver.lib

@@ -3,5 +3,5 @@ rmn	equ	4
 rup	equ	0
 rtp	equ	0
 biosver	macro
-	db	"3.4.0-dev.7"
+	db	"3.4.0-dev.9"
 	endm