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v3.5.0-dev
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v3.5.0-dev
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@@ -6,37 +6,37 @@
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||||
*** ***
|
||||
***********************************************************************
|
||||
|
||||
This directory ("Binary") is part of the RomWBW System Software
|
||||
distribution archive. It contains the completed binary outputs of
|
||||
the build process. As described below, these files are used to
|
||||
This directory ("Binary") is part of the RomWBW System Software
|
||||
distribution archive. It contains the completed binary outputs of
|
||||
the build process. As described below, these files are used to
|
||||
assemble a working RetroBrew Computers system.
|
||||
|
||||
The files in this directory are created by the build process that is
|
||||
documented in the ReadMe.txt file in the Source directory. When
|
||||
released the directory is populated with the default output files.
|
||||
However, the output of custom builds will be placed in this directory
|
||||
The files in this directory are created by the build process that is
|
||||
documented in the ReadMe.txt file in the Source directory. When
|
||||
released the directory is populated with the default output files.
|
||||
However, the output of custom builds will be placed in this directory
|
||||
as well.
|
||||
|
||||
If you only see a few files in this directory, then you downloaded
|
||||
just the source from GitHub. To retrieve the full release download
|
||||
package, go to https://github.com/wwarthen/RomWBW. On this page,
|
||||
look for the text "XX releases" where XX is a number. Click on this
|
||||
text to go to the releases page. On this page, you will see the
|
||||
latest releases listed. For each release, you will see a package
|
||||
file called something like "RomWBW-2.9.0-Package.zip". Click on the
|
||||
If you only see a few files in this directory, then you downloaded
|
||||
just the source from GitHub. To retrieve the full release download
|
||||
package, go to https://github.com/wwarthen/RomWBW. On this page,
|
||||
look for the text "XX releases" where XX is a number. Click on this
|
||||
text to go to the releases page. On this page, you will see the
|
||||
latest releases listed. For each release, you will see a package
|
||||
file called something like "RomWBW-2.9.0-Package.zip". Click on the
|
||||
package file for the release you want to download.
|
||||
|
||||
ROM Firmware Images (<plt>_<cfg>.rom)
|
||||
-------------------------------------
|
||||
|
||||
The files with a ".rom" extension are binary images ready to program
|
||||
into an appropriate PROM. These files are named with the format
|
||||
<plt>_<cfg>.rom. <plt> refers to the primary platform such as Zeta,
|
||||
N8, Mark IV, etc. <cfg> refers to the specific configuration. In
|
||||
general, there will be a standard configuration ("std") for each
|
||||
platform. So, for example, the file called MK4_std.rom is a ROM
|
||||
image for the Mark IV with the standard configuration. If a custom
|
||||
configuration called "custom" is created and built, a new file called
|
||||
The files with a ".rom" extension are binary images ready to program
|
||||
into an appropriate PROM. These files are named with the format
|
||||
<plt>_<cfg>.rom. <plt> refers to the primary platform such as Zeta,
|
||||
N8, Mark IV, etc. <cfg> refers to the specific configuration. In
|
||||
general, there will be a standard configuration ("std") for each
|
||||
platform. So, for example, the file called MK4_std.rom is a ROM
|
||||
image for the Mark IV with the standard configuration. If a custom
|
||||
configuration called "custom" is created and built, a new file called
|
||||
MK4_custom.rom will be added to this directory.
|
||||
|
||||
Documentation of the pre-built ROM Images is contained in
|
||||
@@ -54,52 +54,52 @@ contents. Refer to the RomWBW User Guide for more information.
|
||||
ROM Executable Images (<plt>_<cfg>.com)
|
||||
---------------------------------------
|
||||
|
||||
When a ROM image (".rom") is created, an executable version of the
|
||||
ROM is also created. These files have the same naming convention as
|
||||
the ROM Image files, but have the extension ".com". These files can
|
||||
When a ROM image (".rom") is created, an executable version of the
|
||||
ROM is also created. These files have the same naming convention as
|
||||
the ROM Image files, but have the extension ".com". These files can
|
||||
be copied to a working system and run like a normal CP/M application.
|
||||
|
||||
When run on the target system, they install in RAM just like they had
|
||||
When run on the target system, they install in RAM just like they had
|
||||
been loaded from ROM. This allows a new ROM build to be tested
|
||||
without reprogramming the actual ROM.
|
||||
|
||||
WARNING: In a few cases the .com file is too big to load. If you get
|
||||
a message like "Full" or "BAD LOAD" when trying to load one of the
|
||||
.com files, it is too big. In these cases, you will not be able to
|
||||
WARNING: In a few cases the .com file is too big to load. If you get
|
||||
a message like "Full" or "BAD LOAD" when trying to load one of the
|
||||
.com files, it is too big. In these cases, you will not be able to
|
||||
test the ROM prior to programming it.
|
||||
|
||||
VDU ROM Image (vdu.rom)
|
||||
-----------------------
|
||||
|
||||
The VDU video board requires a dedicated onboard ROM containing the
|
||||
font data. The "vdu.rom" file contains the binary data to program
|
||||
The VDU video board requires a dedicated onboard ROM containing the
|
||||
font data. The "vdu.rom" file contains the binary data to program
|
||||
onto that chip.
|
||||
|
||||
Disk Images (fd_*.img, hd_*.img, psys.img)
|
||||
------------------------------------------
|
||||
Disk Images (fd_*.img, hd_*.img)
|
||||
--------------------------------
|
||||
|
||||
RomWBW includes a mechanism for generating floppy disk and hard disk
|
||||
binary images that are ready to copy directly to a floppy, hard disk,
|
||||
CF Card, or SD Card which will then be ready for use in any
|
||||
RomWBW includes a mechanism for generating floppy disk and hard disk
|
||||
binary images that are ready to copy directly to a floppy, hard disk,
|
||||
CF Card, or SD Card which will then be ready for use in any
|
||||
RomWBW-based system.
|
||||
|
||||
Essentially, these files contain prepared floppy and hard disk images
|
||||
with a large set of programs and related files. By copying the
|
||||
contents of these files to appropriate media as described below, you
|
||||
Essentially, these files contain prepared floppy and hard disk images
|
||||
with a large set of programs and related files. By copying the
|
||||
contents of these files to appropriate media as described below, you
|
||||
can quickly create ready-to-use media. Win32DiskImager or
|
||||
RawWriteWin can be used to copy images directly to media. These
|
||||
programs are included in the RomWBW Tools directory.
|
||||
|
||||
The fd_*.img files are floppy disk images. They are sized for 1.44MB
|
||||
floppy media and can be copied to actual floppy disks using
|
||||
RawWriteWin (as long as you have access to a floppy drive on your
|
||||
Windows computer). The resulting floppy disks will be usable on any
|
||||
The fd_*.img files are floppy disk images. They are sized for 1.44MB
|
||||
floppy media and can be copied to actual floppy disks using
|
||||
RawWriteWin (as long as you have access to a floppy drive on your
|
||||
Windows computer). The resulting floppy disks will be usable on any
|
||||
RomWBW-based system with floppy drive(s).
|
||||
|
||||
Likewise, the hd512_*.img and hd1k_*.img files are hard disk images.
|
||||
Each file is intended to be copied to the start of any type of hard
|
||||
disk media (typically a CF Card or SD Card). The resulting media will
|
||||
be usable on any RomWBW-based system that accepts the corresponding
|
||||
Likewise, the hd512_*.img and hd1k_*.img files are hard disk images.
|
||||
Each file is intended to be copied to the start of any type of hard
|
||||
disk media (typically a CF Card or SD Card). The resulting media will
|
||||
be usable on any RomWBW-based system that accepts the corresponding
|
||||
media type.
|
||||
|
||||
NOTE: The hd512_*.img files are equivalent to the hd_*.img
|
||||
@@ -109,34 +109,58 @@ maximum number of CP/M directory entries from 512 to 1024.
|
||||
Refer to the ReadMe.txt in the Source/Images directory
|
||||
for details.
|
||||
|
||||
Documentation of the pre-built disk images is contained in the
|
||||
Documentation of the pre-built disk images is contained in the
|
||||
"RomWBW User Guide" found in the Doc directory. The contents of
|
||||
the disk images is contained in the "RomWBW Disk Catalog", but it
|
||||
is significantly out-of-date.
|
||||
|
||||
The contents of the floppy/hard disk images are created by
|
||||
the BuildImages.cmd script in the Source directory. Additional
|
||||
information on how to generate custom disk images is found in the
|
||||
The contents of the floppy/hard disk images are created by
|
||||
the BuildImages.cmd script in the Source directory. Additional
|
||||
information on how to generate custom disk images is found in the
|
||||
Source\Images ReadMe.txt file.
|
||||
|
||||
The psys.img file contains a full implementation of the UCSD p-System
|
||||
for the Z80 running under RomWBW. This image file must be placed on
|
||||
disk media by itself (not appended or concatenated with hd*.img files.
|
||||
Refer to the Source/pSys/ReadMe.txt file for more information on the
|
||||
Disk Images (hd512_combo.img, hd1k_combo.img, *_std_hd1k_combo.img)
|
||||
-------------------------------------------------------------------
|
||||
|
||||
The hd512_combo.img and hd1k_combo.img file are the primary combo
|
||||
disk image files suitable for most platforms.
|
||||
|
||||
The *_std_hd1k_combo.img files are platform specific combo files
|
||||
typically used in romless platforms, they also contain RomWBW binary code
|
||||
that is loaded at boot time into RAM
|
||||
|
||||
Disk Images (hd1k_prefix.dat, *_std_hd1k_prefix.dat)
|
||||
----------------------------------------------------
|
||||
|
||||
The hd1k_prefix.dat file is part of the combo disk images and is
|
||||
applied to hd1k image files as a prefix, it contains the standard
|
||||
partion table.
|
||||
|
||||
The *_std_hd1k_prefix.dat files are platform specific prefixes
|
||||
typically used in romless platforms, they also contain RomWBW binary code
|
||||
that is loaded at boot time into RAM
|
||||
|
||||
Disk Images (psys.img)
|
||||
----------------------
|
||||
|
||||
The psys.img file contains a full implementation of the UCSD p-System
|
||||
for the Z80 running under RomWBW. This image file must be placed on
|
||||
disk media by itself (not appended or concatenated with hd*.img files.
|
||||
Refer to the Source/pSys/ReadMe.txt file for more information on the
|
||||
p-System implementation.
|
||||
|
||||
Propeller ROM Images (*.eeprom)
|
||||
-------------------------------
|
||||
|
||||
The files with and extension of ".eeprom" contain the binary images
|
||||
to be programmed into the Propeller-based boards. The list below
|
||||
The files with and extension of ".eeprom" contain the binary images
|
||||
to be programmed into the Propeller-based boards. The list below
|
||||
indicates which file targets each of the Propeller board variants:
|
||||
|
||||
ParPortProp ParPortProp.eeprom
|
||||
PropIO V1 PropIO.eeprom
|
||||
PropIO V2 PropIO2.eeprom
|
||||
|
||||
Refer to the board documentation of the boards for more information
|
||||
Refer to the board documentation of the boards for more information
|
||||
on how to program the EEPROMs on these boards.
|
||||
|
||||
Apps Directory
|
||||
@@ -144,4 +168,4 @@ Apps Directory
|
||||
|
||||
The Apps subdirectory contains the executable application files that
|
||||
are specific to RomWBW. The source for these applications is found
|
||||
in the Source\Apps directory of the distribution.
|
||||
in the Source\Apps directory of the distribution.
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
586
ReadMe.md
586
ReadMe.md
@@ -1,293 +1,293 @@
|
||||
|
||||
|
||||
**RomWBW ReadMe** \
|
||||
Version 3.5 \
|
||||
Wayne Warthen ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \
|
||||
05 Sep 2024
|
||||
|
||||
# Overview
|
||||
|
||||
RomWBW software provides a complete, commercial quality implementation
|
||||
of CP/M (and workalike) operating systems and applications for modern
|
||||
Z80/180/280 retro-computing hardware systems. A wide variety of
|
||||
platforms are supported including those produced by these developer
|
||||
communities:
|
||||
|
||||
- [RetroBrew Computers](https://www.retrobrewcomputers.org)
|
||||
(<https://www.retrobrewcomputers.org>)
|
||||
- [RC2014](https://rc2014.co.uk) (<https://rc2014.co.uk>),
|
||||
[RC2014-Z80](https://groups.google.com/g/rc2014-z80)
|
||||
(<https://groups.google.com/g/rc2014-z80>)
|
||||
- [Retro Computing](https://groups.google.com/g/retro-comp)
|
||||
(<https://groups.google.com/g/retro-comp>)
|
||||
- [Small Computer Central](https://smallcomputercentral.com/)
|
||||
(<https://smallcomputercentral.com/>)
|
||||
|
||||
A complete list of the currently supported platforms is found in the
|
||||
\[Installation\] section.
|
||||
|
||||
General features include:
|
||||
|
||||
- Z80 Family CPUs including Z80, Z180, and Z280
|
||||
- Banked memory services for several banking designs
|
||||
- Disk drivers for RAM, ROM, Floppy, IDE ATA/ATAPI, CF, SD, USB, Zip,
|
||||
Iomega
|
||||
- Serial drivers including UART (16550-like), ASCI, ACIA, SIO
|
||||
- Video drivers including TMS9918, SY6545, MOS8563, HD6445
|
||||
- Keyboard (PS/2) drivers via VT8242 or PPI interfaces
|
||||
- Real time clock drivers including DS1302, BQ4845
|
||||
- OSes: CP/M 2.2, ZSDOS, CP/M 3, NZ-COM, ZPM3, QPM, p-System, and
|
||||
FreeRTOS
|
||||
- Built-in VT-100 terminal emulation support
|
||||
|
||||
RomWBW is distributed as both source code and pre-built ROM and disk
|
||||
images. Some of the provided software can be launched directly from the
|
||||
ROM firmware itself:
|
||||
|
||||
- System Monitor
|
||||
- Operating Systems (CP/M 2.2, ZSDOS)
|
||||
- ROM BASIC (Nascom BASIC and Tasty BASIC)
|
||||
- ROM Forth
|
||||
|
||||
A dynamic disk drive letter assignment mechanism allows mapping
|
||||
operating system drive letters to any available disk media.
|
||||
Additionally, mass storage devices (IDE Disk, CF Card, SD Card, etc.)
|
||||
support the use of multiple slices (up to 256 per device). Each slice
|
||||
contains a complete CP/M filesystem and can be mapped independently to
|
||||
any drive letter. This overcomes the inherent size limitations in legacy
|
||||
OSes and allows up to 2GB of accessible storage on a single device.
|
||||
|
||||
The pre-built ROM firmware images are generally suitable for most users.
|
||||
However, it is also very easy to modify and build custom ROM images that
|
||||
fully tailor the firmware to your specific preferences. All tools
|
||||
required to build custom ROM firmware under Windows are included – no
|
||||
need to install assemblers, etc. The firmware can also be built using
|
||||
Linux or MacOS after confirming a few standard tools have been
|
||||
installed.
|
||||
|
||||
Multiple disk images are provided in the distribution. Most disk images
|
||||
contain a complete, bootable, ready-to-run implementation of a specific
|
||||
operating system. A “combo” disk image contains multiple slices, each
|
||||
with a full operating system implementation. If you use this disk image,
|
||||
you can easily pick whichever operating system you want to boot without
|
||||
changing media.
|
||||
|
||||
By design, RomWBW isolates all of the hardware specific functions in the
|
||||
ROM chip itself. The ROM provides a hardware abstraction layer such that
|
||||
all of the operating systems and applications on a disk will run on any
|
||||
RomWBW-based system. To put it simply, you can take a disk (or CF/SD/USB
|
||||
Card) and move it between systems transparently.
|
||||
|
||||
A tool is provided that allows you to access a FAT-12/16/32 filesystem.
|
||||
The FAT filesystem may be coresident on the same disk media as RomWBW
|
||||
slices or on stand-alone media. This makes exchanging files with modern
|
||||
OSes such as Windows, MacOS, and Linux very easy.
|
||||
|
||||
# Acquiring RomWBW
|
||||
|
||||
The [RomWBW Repository](https://github.com/wwarthen/RomWBW)
|
||||
(<https://github.com/wwarthen/RomWBW>) on GitHub is the official
|
||||
distribution location for all project source and documentation. The
|
||||
fully-built distribution releases are available on the [RomWBW Releases
|
||||
Page](https://github.com/wwarthen/RomWBW/releases)
|
||||
(<https://github.com/wwarthen/RomWBW/releases>) of the repository. On
|
||||
this page, you will normally see a Development Snapshot as well as
|
||||
recent stable releases. Unless you have a specific reason, I suggest you
|
||||
stick to the most recent stable release. Expand the “Assets” drop-down
|
||||
for the release you want to download, then select the asset named
|
||||
RomWBW-vX.X.X-Package.zip. The Package asset includes all pre-built ROM
|
||||
and Disk images as well as full source code. The other assets contain
|
||||
only source code and do not have the pre-built ROM or disk images.
|
||||
|
||||
All source code and distributions are maintained on GitHub. Code
|
||||
contributions are very welcome.
|
||||
|
||||
# Installation & Operation
|
||||
|
||||
In general, installation of RomWBW on your platform is very simple. You
|
||||
just need to program your ROM with the correct ROM image from the RomWBW
|
||||
distribution. Subsequently, you can write disk images on your disk
|
||||
drives (IDE disk, CF Card, SD Card, etc.) which then provides even more
|
||||
functionality.
|
||||
|
||||
Complete instructions for installation and operation of RomWBW are found
|
||||
in the [RomWBW User
|
||||
Guide](https://github.com/wwarthen/RomWBW/raw/master/Doc/RomWBW%20User%20Guide.pdf).
|
||||
|
||||
## Documentation
|
||||
|
||||
Documentation for RomWBW includes:
|
||||
|
||||
- [RomWBW User
|
||||
Guide](https://github.com/wwarthen/RomWBW/raw/master/Doc/RomWBW%20User%20Guide.pdf)
|
||||
- [RomWBW System
|
||||
Guide](https://github.com/wwarthen/RomWBW/raw/master/Doc/RomWBW%20System%20Guide.pdf)
|
||||
- [RomWBW
|
||||
Applications](https://github.com/wwarthen/RomWBW/raw/master/Doc/RomWBW%20Applications.pdf)
|
||||
- [RomWBW
|
||||
Errata](https://github.com/wwarthen/RomWBW/raw/master/Doc/RomWBW%20Errata.pdf)
|
||||
|
||||
# Acknowledgments
|
||||
|
||||
I want to acknowledge that a great deal of the code and inspiration for
|
||||
RomWBW has been provided by or derived from the work of others in the
|
||||
RetroBrew Computers Community. I sincerely appreciate all of their
|
||||
contributions. The list below is probably missing many names – please
|
||||
let me know if I missed you!
|
||||
|
||||
- Andrew Lynch started it all when he created the N8VEM Z80 SBC which
|
||||
became the first platform RomWBW supported. Some of his original code
|
||||
can still be found in RomWBW.
|
||||
|
||||
- Dan Werner wrote much of the code from which RomWBW was originally
|
||||
derived and he has always been a great source of knowledge and advice.
|
||||
|
||||
- Douglas Goodall contributed code, time, testing, and advice in “the
|
||||
early days”. He created an entire suite of application programs to
|
||||
enhance the use of RomWBW. Unfortunately, they have become unusable
|
||||
due to internal changes within RomWBW. As of RomWBW 2.6, these
|
||||
applications are no longer provided.
|
||||
|
||||
- Sergey Kiselev created several hardware platforms for RomWBW including
|
||||
the very popular Zeta.
|
||||
|
||||
- David Giles created support for the Z180 CSIO which is now included SD
|
||||
Card driver.
|
||||
|
||||
- Phil Summers contributed the Forth and BASIC adaptations in ROM, the
|
||||
AY-3-8910 sound driver, DMA support, and a long list of general code
|
||||
and documentation enhancements.
|
||||
|
||||
- Ed Brindley contributed some of the code that supports the RCBus
|
||||
platform.
|
||||
|
||||
- Spencer Owen created the RC2014 series of hobbyist kit computers which
|
||||
has exponentially increased RomWBW usage. Some of his kits include
|
||||
RomWBW.
|
||||
|
||||
- Stephen Cousins has likewise created a series of hobbyist kit
|
||||
computers at Small Computer Central and is distributing RomWBW with
|
||||
many of them.
|
||||
|
||||
- Alan Cox has contributed some driver code and has provided a great
|
||||
deal of advice.
|
||||
|
||||
- The CP/NET client files were developed by Douglas Miller.
|
||||
|
||||
- Phillip Stevens contributed support for FreeRTOS.
|
||||
|
||||
- Curt Mayer contributed the original Linux / MacOS build process.
|
||||
|
||||
- UNA BIOS and FDISK80 are the products of John Coffman.
|
||||
|
||||
- FLASH4 is a product of Will Sowerbutts.
|
||||
|
||||
- CLRDIR is a product of Max Scane.
|
||||
|
||||
- Tasty Basic is a product of Dimitri Theulings.
|
||||
|
||||
- Dean Netherton contributed the sound driver interface and the SN76489
|
||||
sound driver.
|
||||
|
||||
- The RomWBW Disk Catalog document was produced by Mykl Orders.
|
||||
|
||||
- Rob Prouse has created many of the supplemental disk images including
|
||||
Aztec C, HiTech C, SLR Z80ASM, Turbo Pascal, Microsoft BASIC Compiler,
|
||||
Microsoft Fortran Compiler, and a Games compendium.
|
||||
|
||||
- Martin R has provided substantial help reviewing and improving the
|
||||
User Guide and Applications documents.
|
||||
|
||||
- Mark Pruden has also contributed a great deal of content to the User
|
||||
Guide.
|
||||
|
||||
- Jacques Pelletier has contributed the DS1501 RTC driver code.
|
||||
|
||||
- Jose Collado has contributed enhancements to the TMS driver including
|
||||
compatibility with standard TMS register configuration.
|
||||
|
||||
- Kevin Boone has contributed a generic HBIOS date/time utility (WDATE).
|
||||
|
||||
- Matt Carroll has contributed a fix to XM.COM that corrects the port
|
||||
specification when doing a send.
|
||||
|
||||
- Dean Jenkins enhanced the build process to accommodate the Raspberry
|
||||
Pi 4.
|
||||
|
||||
- Tom Plano has contributed a new utility (HTALK) to allow talking
|
||||
directly to HBIOS COM ports.
|
||||
|
||||
- Lars Nelson has contributed several generic utilities such as a
|
||||
universal (OS agnostic) UNARC application.
|
||||
|
||||
- Dylan Hall added support for specifying a secondary console.
|
||||
|
||||
- Bill Shen has contributed boot loaders for several of his systems.
|
||||
|
||||
- Laszlo Szolnoki has contributed an EF9345 video display controller
|
||||
driver.
|
||||
|
||||
- Ladislau Szilagyi has contributed an enhanced version of CP/M Cowgol
|
||||
that leverages RomWBW memory banking.
|
||||
|
||||
- Les Bird has contributed support for the NABU w/ Option Board
|
||||
|
||||
Contributions of all kinds to RomWBW are very welcome.
|
||||
|
||||
# Licensing
|
||||
|
||||
RomWBW is free software: you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License as published by the Free
|
||||
Software Foundation, either version 3 of the License, or (at your
|
||||
option) any later version.
|
||||
|
||||
RomWBW is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with RomWBW. If not, see <https://www.gnu.org/licenses/>.
|
||||
|
||||
Portions of RomWBW were created by, contributed by, or derived from the
|
||||
work of others. It is believed that these works are being used in
|
||||
accordance with the intentions and/or licensing of their creators.
|
||||
|
||||
If anyone feels their work is being used outside of its intended
|
||||
licensing, please notify:
|
||||
|
||||
> Wayne Warthen
|
||||
> <wwarthen@gmail.com>
|
||||
|
||||
RomWBW is an aggregate work. It is composed of many individual,
|
||||
standalone programs that are distributed as a whole to function as a
|
||||
cohesive system. Each program may have its own licensing which may be
|
||||
different from other programs within the aggregate.
|
||||
|
||||
In some cases, a single program (e.g., CP/M Operating System) is
|
||||
composed of multiple components with different licenses. It is believed
|
||||
that in all such cases the licenses are compatible with GPL version 3.
|
||||
|
||||
RomWBW encourages code contributions from others. Contributors may
|
||||
assert their own copyright in their contributions by annotating the
|
||||
contributed source code appropriately. Contributors are further
|
||||
encouraged to submit their contributions via the RomWBW source code
|
||||
control system to ensure their contributions are clearly documented.
|
||||
|
||||
All contributions to RomWBW are subject to this license.
|
||||
|
||||
# Getting Assistance
|
||||
|
||||
The best way to get assistance with RomWBW or any aspect of the
|
||||
RetroBrew Computers projects is via one of the community forums:
|
||||
|
||||
- [RetroBrew Computers Forum](https://www.retrobrewcomputers.org/forum/)
|
||||
- [RC2014 Google
|
||||
Group](https://groups.google.com/forum/#!forum/rc2014-z80)
|
||||
- [retro-comp Google
|
||||
Group](https://groups.google.com/forum/#!forum/retro-comp)
|
||||
|
||||
Submission of issues and bugs are welcome at the [RomWBW GitHub
|
||||
Repository](https://github.com/wwarthen/RomWBW).
|
||||
|
||||
Also feel free to email Wayne Warthen at <wwarthen@gmail.com>.
|
||||
|
||||
|
||||
**RomWBW ReadMe** \
|
||||
Version 3.5 \
|
||||
Wayne Warthen ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \
|
||||
06 Sep 2024
|
||||
|
||||
# Overview
|
||||
|
||||
RomWBW software provides a complete, commercial quality implementation
|
||||
of CP/M (and workalike) operating systems and applications for modern
|
||||
Z80/180/280 retro-computing hardware systems. A wide variety of
|
||||
platforms are supported including those produced by these developer
|
||||
communities:
|
||||
|
||||
- [RetroBrew Computers](https://www.retrobrewcomputers.org)
|
||||
(<https://www.retrobrewcomputers.org>)
|
||||
- [RC2014](https://rc2014.co.uk) (<https://rc2014.co.uk>),
|
||||
[RC2014-Z80](https://groups.google.com/g/rc2014-z80)
|
||||
(<https://groups.google.com/g/rc2014-z80>)
|
||||
- [Retro Computing](https://groups.google.com/g/retro-comp)
|
||||
(<https://groups.google.com/g/retro-comp>)
|
||||
- [Small Computer Central](https://smallcomputercentral.com/)
|
||||
(<https://smallcomputercentral.com/>)
|
||||
|
||||
A complete list of the currently supported platforms is found in the
|
||||
\[Installation\] section.
|
||||
|
||||
General features include:
|
||||
|
||||
- Z80 Family CPUs including Z80, Z180, and Z280
|
||||
- Banked memory services for several banking designs
|
||||
- Disk drivers for RAM, ROM, Floppy, IDE ATA/ATAPI, CF, SD, USB, Zip,
|
||||
Iomega
|
||||
- Serial drivers including UART (16550-like), ASCI, ACIA, SIO
|
||||
- Video drivers including TMS9918, SY6545, MOS8563, HD6445
|
||||
- Keyboard (PS/2) drivers via VT8242 or PPI interfaces
|
||||
- Real time clock drivers including DS1302, BQ4845
|
||||
- OSes: CP/M 2.2, ZSDOS, CP/M 3, NZ-COM, ZPM3, QPM, p-System, and
|
||||
FreeRTOS
|
||||
- Built-in VT-100 terminal emulation support
|
||||
|
||||
RomWBW is distributed as both source code and pre-built ROM and disk
|
||||
images. Some of the provided software can be launched directly from the
|
||||
ROM firmware itself:
|
||||
|
||||
- System Monitor
|
||||
- Operating Systems (CP/M 2.2, ZSDOS)
|
||||
- ROM BASIC (Nascom BASIC and Tasty BASIC)
|
||||
- ROM Forth
|
||||
|
||||
A dynamic disk drive letter assignment mechanism allows mapping
|
||||
operating system drive letters to any available disk media.
|
||||
Additionally, mass storage devices (IDE Disk, CF Card, SD Card, etc.)
|
||||
support the use of multiple slices (up to 256 per device). Each slice
|
||||
contains a complete CP/M filesystem and can be mapped independently to
|
||||
any drive letter. This overcomes the inherent size limitations in legacy
|
||||
OSes and allows up to 2GB of accessible storage on a single device.
|
||||
|
||||
The pre-built ROM firmware images are generally suitable for most users.
|
||||
However, it is also very easy to modify and build custom ROM images that
|
||||
fully tailor the firmware to your specific preferences. All tools
|
||||
required to build custom ROM firmware under Windows are included – no
|
||||
need to install assemblers, etc. The firmware can also be built using
|
||||
Linux or MacOS after confirming a few standard tools have been
|
||||
installed.
|
||||
|
||||
Multiple disk images are provided in the distribution. Most disk images
|
||||
contain a complete, bootable, ready-to-run implementation of a specific
|
||||
operating system. A “combo” disk image contains multiple slices, each
|
||||
with a full operating system implementation. If you use this disk image,
|
||||
you can easily pick whichever operating system you want to boot without
|
||||
changing media.
|
||||
|
||||
By design, RomWBW isolates all of the hardware specific functions in the
|
||||
ROM chip itself. The ROM provides a hardware abstraction layer such that
|
||||
all of the operating systems and applications on a disk will run on any
|
||||
RomWBW-based system. To put it simply, you can take a disk (or CF/SD/USB
|
||||
Card) and move it between systems transparently.
|
||||
|
||||
A tool is provided that allows you to access a FAT-12/16/32 filesystem.
|
||||
The FAT filesystem may be coresident on the same disk media as RomWBW
|
||||
slices or on stand-alone media. This makes exchanging files with modern
|
||||
OSes such as Windows, MacOS, and Linux very easy.
|
||||
|
||||
# Acquiring RomWBW
|
||||
|
||||
The [RomWBW Repository](https://github.com/wwarthen/RomWBW)
|
||||
(<https://github.com/wwarthen/RomWBW>) on GitHub is the official
|
||||
distribution location for all project source and documentation. The
|
||||
fully-built distribution releases are available on the [RomWBW Releases
|
||||
Page](https://github.com/wwarthen/RomWBW/releases)
|
||||
(<https://github.com/wwarthen/RomWBW/releases>) of the repository. On
|
||||
this page, you will normally see a Development Snapshot as well as
|
||||
recent stable releases. Unless you have a specific reason, I suggest you
|
||||
stick to the most recent stable release. Expand the “Assets” drop-down
|
||||
for the release you want to download, then select the asset named
|
||||
RomWBW-vX.X.X-Package.zip. The Package asset includes all pre-built ROM
|
||||
and Disk images as well as full source code. The other assets contain
|
||||
only source code and do not have the pre-built ROM or disk images.
|
||||
|
||||
All source code and distributions are maintained on GitHub. Code
|
||||
contributions are very welcome.
|
||||
|
||||
# Installation & Operation
|
||||
|
||||
In general, installation of RomWBW on your platform is very simple. You
|
||||
just need to program your ROM with the correct ROM image from the RomWBW
|
||||
distribution. Subsequently, you can write disk images on your disk
|
||||
drives (IDE disk, CF Card, SD Card, etc.) which then provides even more
|
||||
functionality.
|
||||
|
||||
Complete instructions for installation and operation of RomWBW are found
|
||||
in the [RomWBW User
|
||||
Guide](https://github.com/wwarthen/RomWBW/raw/master/Doc/RomWBW%20User%20Guide.pdf).
|
||||
|
||||
## Documentation
|
||||
|
||||
Documentation for RomWBW includes:
|
||||
|
||||
- [RomWBW User
|
||||
Guide](https://github.com/wwarthen/RomWBW/raw/master/Doc/RomWBW%20User%20Guide.pdf)
|
||||
- [RomWBW System
|
||||
Guide](https://github.com/wwarthen/RomWBW/raw/master/Doc/RomWBW%20System%20Guide.pdf)
|
||||
- [RomWBW
|
||||
Applications](https://github.com/wwarthen/RomWBW/raw/master/Doc/RomWBW%20Applications.pdf)
|
||||
- [RomWBW
|
||||
Errata](https://github.com/wwarthen/RomWBW/raw/master/Doc/RomWBW%20Errata.pdf)
|
||||
|
||||
# Acknowledgments
|
||||
|
||||
I want to acknowledge that a great deal of the code and inspiration for
|
||||
RomWBW has been provided by or derived from the work of others in the
|
||||
RetroBrew Computers Community. I sincerely appreciate all of their
|
||||
contributions. The list below is probably missing many names – please
|
||||
let me know if I missed you!
|
||||
|
||||
- Andrew Lynch started it all when he created the N8VEM Z80 SBC which
|
||||
became the first platform RomWBW supported. Some of his original code
|
||||
can still be found in RomWBW.
|
||||
|
||||
- Dan Werner wrote much of the code from which RomWBW was originally
|
||||
derived and he has always been a great source of knowledge and advice.
|
||||
|
||||
- Douglas Goodall contributed code, time, testing, and advice in “the
|
||||
early days”. He created an entire suite of application programs to
|
||||
enhance the use of RomWBW. Unfortunately, they have become unusable
|
||||
due to internal changes within RomWBW. As of RomWBW 2.6, these
|
||||
applications are no longer provided.
|
||||
|
||||
- Sergey Kiselev created several hardware platforms for RomWBW including
|
||||
the very popular Zeta.
|
||||
|
||||
- David Giles created support for the Z180 CSIO which is now included SD
|
||||
Card driver.
|
||||
|
||||
- Phil Summers contributed the Forth and BASIC adaptations in ROM, the
|
||||
AY-3-8910 sound driver, DMA support, and a long list of general code
|
||||
and documentation enhancements.
|
||||
|
||||
- Ed Brindley contributed some of the code that supports the RCBus
|
||||
platform.
|
||||
|
||||
- Spencer Owen created the RC2014 series of hobbyist kit computers which
|
||||
has exponentially increased RomWBW usage. Some of his kits include
|
||||
RomWBW.
|
||||
|
||||
- Stephen Cousins has likewise created a series of hobbyist kit
|
||||
computers at Small Computer Central and is distributing RomWBW with
|
||||
many of them.
|
||||
|
||||
- Alan Cox has contributed some driver code and has provided a great
|
||||
deal of advice.
|
||||
|
||||
- The CP/NET client files were developed by Douglas Miller.
|
||||
|
||||
- Phillip Stevens contributed support for FreeRTOS.
|
||||
|
||||
- Curt Mayer contributed the original Linux / MacOS build process.
|
||||
|
||||
- UNA BIOS and FDISK80 are the products of John Coffman.
|
||||
|
||||
- FLASH4 is a product of Will Sowerbutts.
|
||||
|
||||
- CLRDIR is a product of Max Scane.
|
||||
|
||||
- Tasty Basic is a product of Dimitri Theulings.
|
||||
|
||||
- Dean Netherton contributed the sound driver interface and the SN76489
|
||||
sound driver.
|
||||
|
||||
- The RomWBW Disk Catalog document was produced by Mykl Orders.
|
||||
|
||||
- Rob Prouse has created many of the supplemental disk images including
|
||||
Aztec C, HiTech C, SLR Z80ASM, Turbo Pascal, Microsoft BASIC Compiler,
|
||||
Microsoft Fortran Compiler, and a Games compendium.
|
||||
|
||||
- Martin R has provided substantial help reviewing and improving the
|
||||
User Guide and Applications documents.
|
||||
|
||||
- Mark Pruden has also contributed a great deal of content to the User
|
||||
Guide.
|
||||
|
||||
- Jacques Pelletier has contributed the DS1501 RTC driver code.
|
||||
|
||||
- Jose Collado has contributed enhancements to the TMS driver including
|
||||
compatibility with standard TMS register configuration.
|
||||
|
||||
- Kevin Boone has contributed a generic HBIOS date/time utility (WDATE).
|
||||
|
||||
- Matt Carroll has contributed a fix to XM.COM that corrects the port
|
||||
specification when doing a send.
|
||||
|
||||
- Dean Jenkins enhanced the build process to accommodate the Raspberry
|
||||
Pi 4.
|
||||
|
||||
- Tom Plano has contributed a new utility (HTALK) to allow talking
|
||||
directly to HBIOS COM ports.
|
||||
|
||||
- Lars Nelson has contributed several generic utilities such as a
|
||||
universal (OS agnostic) UNARC application.
|
||||
|
||||
- Dylan Hall added support for specifying a secondary console.
|
||||
|
||||
- Bill Shen has contributed boot loaders for several of his systems.
|
||||
|
||||
- Laszlo Szolnoki has contributed an EF9345 video display controller
|
||||
driver.
|
||||
|
||||
- Ladislau Szilagyi has contributed an enhanced version of CP/M Cowgol
|
||||
that leverages RomWBW memory banking.
|
||||
|
||||
- Les Bird has contributed support for the NABU w/ Option Board
|
||||
|
||||
Contributions of all kinds to RomWBW are very welcome.
|
||||
|
||||
# Licensing
|
||||
|
||||
RomWBW is free software: you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License as published by the Free
|
||||
Software Foundation, either version 3 of the License, or (at your
|
||||
option) any later version.
|
||||
|
||||
RomWBW is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with RomWBW. If not, see <https://www.gnu.org/licenses/>.
|
||||
|
||||
Portions of RomWBW were created by, contributed by, or derived from the
|
||||
work of others. It is believed that these works are being used in
|
||||
accordance with the intentions and/or licensing of their creators.
|
||||
|
||||
If anyone feels their work is being used outside of its intended
|
||||
licensing, please notify:
|
||||
|
||||
> Wayne Warthen
|
||||
> <wwarthen@gmail.com>
|
||||
|
||||
RomWBW is an aggregate work. It is composed of many individual,
|
||||
standalone programs that are distributed as a whole to function as a
|
||||
cohesive system. Each program may have its own licensing which may be
|
||||
different from other programs within the aggregate.
|
||||
|
||||
In some cases, a single program (e.g., CP/M Operating System) is
|
||||
composed of multiple components with different licenses. It is believed
|
||||
that in all such cases the licenses are compatible with GPL version 3.
|
||||
|
||||
RomWBW encourages code contributions from others. Contributors may
|
||||
assert their own copyright in their contributions by annotating the
|
||||
contributed source code appropriately. Contributors are further
|
||||
encouraged to submit their contributions via the RomWBW source code
|
||||
control system to ensure their contributions are clearly documented.
|
||||
|
||||
All contributions to RomWBW are subject to this license.
|
||||
|
||||
# Getting Assistance
|
||||
|
||||
The best way to get assistance with RomWBW or any aspect of the
|
||||
RetroBrew Computers projects is via one of the community forums:
|
||||
|
||||
- [RetroBrew Computers Forum](https://www.retrobrewcomputers.org/forum/)
|
||||
- [RC2014 Google
|
||||
Group](https://groups.google.com/forum/#!forum/rc2014-z80)
|
||||
- [retro-comp Google
|
||||
Group](https://groups.google.com/forum/#!forum/retro-comp)
|
||||
|
||||
Submission of issues and bugs are welcome at the [RomWBW GitHub
|
||||
Repository](https://github.com/wwarthen/RomWBW).
|
||||
|
||||
Also feel free to email Wayne Warthen at <wwarthen@gmail.com>.
|
||||
|
||||
598
ReadMe.txt
598
ReadMe.txt
@@ -1,299 +1,299 @@
|
||||
RomWBW ReadMe
|
||||
Wayne Warthen (wwarthen@gmail.com)
|
||||
05 Sep 2024
|
||||
|
||||
|
||||
|
||||
OVERVIEW
|
||||
|
||||
|
||||
RomWBW software provides a complete, commercial quality implementation
|
||||
of CP/M (and workalike) operating systems and applications for modern
|
||||
Z80/180/280 retro-computing hardware systems. A wide variety of
|
||||
platforms are supported including those produced by these developer
|
||||
communities:
|
||||
|
||||
- RetroBrew Computers (https://www.retrobrewcomputers.org)
|
||||
- RC2014 (https://rc2014.co.uk),
|
||||
RC2014-Z80 (https://groups.google.com/g/rc2014-z80)
|
||||
- Retro Computing (https://groups.google.com/g/retro-comp)
|
||||
- Small Computer Central (https://smallcomputercentral.com/)
|
||||
|
||||
A complete list of the currently supported platforms is found in the
|
||||
[Installation] section.
|
||||
|
||||
General features include:
|
||||
|
||||
- Z80 Family CPUs including Z80, Z180, and Z280
|
||||
- Banked memory services for several banking designs
|
||||
- Disk drivers for RAM, ROM, Floppy, IDE ATA/ATAPI, CF, SD, USB, Zip,
|
||||
Iomega
|
||||
- Serial drivers including UART (16550-like), ASCI, ACIA, SIO
|
||||
- Video drivers including TMS9918, SY6545, MOS8563, HD6445
|
||||
- Keyboard (PS/2) drivers via VT8242 or PPI interfaces
|
||||
- Real time clock drivers including DS1302, BQ4845
|
||||
- OSes: CP/M 2.2, ZSDOS, CP/M 3, NZ-COM, ZPM3, QPM, p-System, and
|
||||
FreeRTOS
|
||||
- Built-in VT-100 terminal emulation support
|
||||
|
||||
RomWBW is distributed as both source code and pre-built ROM and disk
|
||||
images. Some of the provided software can be launched directly from the
|
||||
ROM firmware itself:
|
||||
|
||||
- System Monitor
|
||||
- Operating Systems (CP/M 2.2, ZSDOS)
|
||||
- ROM BASIC (Nascom BASIC and Tasty BASIC)
|
||||
- ROM Forth
|
||||
|
||||
A dynamic disk drive letter assignment mechanism allows mapping
|
||||
operating system drive letters to any available disk media.
|
||||
Additionally, mass storage devices (IDE Disk, CF Card, SD Card, etc.)
|
||||
support the use of multiple slices (up to 256 per device). Each slice
|
||||
contains a complete CP/M filesystem and can be mapped independently to
|
||||
any drive letter. This overcomes the inherent size limitations in legacy
|
||||
OSes and allows up to 2GB of accessible storage on a single device.
|
||||
|
||||
The pre-built ROM firmware images are generally suitable for most users.
|
||||
However, it is also very easy to modify and build custom ROM images that
|
||||
fully tailor the firmware to your specific preferences. All tools
|
||||
required to build custom ROM firmware under Windows are included – no
|
||||
need to install assemblers, etc. The firmware can also be built using
|
||||
Linux or MacOS after confirming a few standard tools have been
|
||||
installed.
|
||||
|
||||
Multiple disk images are provided in the distribution. Most disk images
|
||||
contain a complete, bootable, ready-to-run implementation of a specific
|
||||
operating system. A “combo” disk image contains multiple slices, each
|
||||
with a full operating system implementation. If you use this disk image,
|
||||
you can easily pick whichever operating system you want to boot without
|
||||
changing media.
|
||||
|
||||
By design, RomWBW isolates all of the hardware specific functions in the
|
||||
ROM chip itself. The ROM provides a hardware abstraction layer such that
|
||||
all of the operating systems and applications on a disk will run on any
|
||||
RomWBW-based system. To put it simply, you can take a disk (or CF/SD/USB
|
||||
Card) and move it between systems transparently.
|
||||
|
||||
A tool is provided that allows you to access a FAT-12/16/32 filesystem.
|
||||
The FAT filesystem may be coresident on the same disk media as RomWBW
|
||||
slices or on stand-alone media. This makes exchanging files with modern
|
||||
OSes such as Windows, MacOS, and Linux very easy.
|
||||
|
||||
|
||||
|
||||
ACQUIRING ROMWBW
|
||||
|
||||
|
||||
The RomWBW Repository (https://github.com/wwarthen/RomWBW) on GitHub is
|
||||
the official distribution location for all project source and
|
||||
documentation. The fully-built distribution releases are available on
|
||||
the RomWBW Releases Page (https://github.com/wwarthen/RomWBW/releases)
|
||||
of the repository. On this page, you will normally see a Development
|
||||
Snapshot as well as recent stable releases. Unless you have a specific
|
||||
reason, I suggest you stick to the most recent stable release. Expand
|
||||
the “Assets” drop-down for the release you want to download, then select
|
||||
the asset named RomWBW-vX.X.X-Package.zip. The Package asset includes
|
||||
all pre-built ROM and Disk images as well as full source code. The other
|
||||
assets contain only source code and do not have the pre-built ROM or
|
||||
disk images.
|
||||
|
||||
All source code and distributions are maintained on GitHub. Code
|
||||
contributions are very welcome.
|
||||
|
||||
|
||||
|
||||
INSTALLATION & OPERATION
|
||||
|
||||
|
||||
In general, installation of RomWBW on your platform is very simple. You
|
||||
just need to program your ROM with the correct ROM image from the RomWBW
|
||||
distribution. Subsequently, you can write disk images on your disk
|
||||
drives (IDE disk, CF Card, SD Card, etc.) which then provides even more
|
||||
functionality.
|
||||
|
||||
Complete instructions for installation and operation of RomWBW are found
|
||||
in the RomWBW User Guide.
|
||||
|
||||
|
||||
Documentation
|
||||
|
||||
Documentation for RomWBW includes:
|
||||
|
||||
- RomWBW User Guide
|
||||
- RomWBW System Guide
|
||||
- RomWBW Applications
|
||||
- RomWBW Errata
|
||||
|
||||
|
||||
|
||||
ACKNOWLEDGMENTS
|
||||
|
||||
|
||||
I want to acknowledge that a great deal of the code and inspiration for
|
||||
RomWBW has been provided by or derived from the work of others in the
|
||||
RetroBrew Computers Community. I sincerely appreciate all of their
|
||||
contributions. The list below is probably missing many names – please
|
||||
let me know if I missed you!
|
||||
|
||||
- Andrew Lynch started it all when he created the N8VEM Z80 SBC which
|
||||
became the first platform RomWBW supported. Some of his original
|
||||
code can still be found in RomWBW.
|
||||
|
||||
- Dan Werner wrote much of the code from which RomWBW was originally
|
||||
derived and he has always been a great source of knowledge and
|
||||
advice.
|
||||
|
||||
- Douglas Goodall contributed code, time, testing, and advice in “the
|
||||
early days”. He created an entire suite of application programs to
|
||||
enhance the use of RomWBW. Unfortunately, they have become unusable
|
||||
due to internal changes within RomWBW. As of RomWBW 2.6, these
|
||||
applications are no longer provided.
|
||||
|
||||
- Sergey Kiselev created several hardware platforms for RomWBW
|
||||
including the very popular Zeta.
|
||||
|
||||
- David Giles created support for the Z180 CSIO which is now included
|
||||
SD Card driver.
|
||||
|
||||
- Phil Summers contributed the Forth and BASIC adaptations in ROM, the
|
||||
AY-3-8910 sound driver, DMA support, and a long list of general code
|
||||
and documentation enhancements.
|
||||
|
||||
- Ed Brindley contributed some of the code that supports the RCBus
|
||||
platform.
|
||||
|
||||
- Spencer Owen created the RC2014 series of hobbyist kit computers
|
||||
which has exponentially increased RomWBW usage. Some of his kits
|
||||
include RomWBW.
|
||||
|
||||
- Stephen Cousins has likewise created a series of hobbyist kit
|
||||
computers at Small Computer Central and is distributing RomWBW with
|
||||
many of them.
|
||||
|
||||
- Alan Cox has contributed some driver code and has provided a great
|
||||
deal of advice.
|
||||
|
||||
- The CP/NET client files were developed by Douglas Miller.
|
||||
|
||||
- Phillip Stevens contributed support for FreeRTOS.
|
||||
|
||||
- Curt Mayer contributed the original Linux / MacOS build process.
|
||||
|
||||
- UNA BIOS and FDISK80 are the products of John Coffman.
|
||||
|
||||
- FLASH4 is a product of Will Sowerbutts.
|
||||
|
||||
- CLRDIR is a product of Max Scane.
|
||||
|
||||
- Tasty Basic is a product of Dimitri Theulings.
|
||||
|
||||
- Dean Netherton contributed the sound driver interface and the
|
||||
SN76489 sound driver.
|
||||
|
||||
- The RomWBW Disk Catalog document was produced by Mykl Orders.
|
||||
|
||||
- Rob Prouse has created many of the supplemental disk images
|
||||
including Aztec C, HiTech C, SLR Z80ASM, Turbo Pascal, Microsoft
|
||||
BASIC Compiler, Microsoft Fortran Compiler, and a Games compendium.
|
||||
|
||||
- Martin R has provided substantial help reviewing and improving the
|
||||
User Guide and Applications documents.
|
||||
|
||||
- Mark Pruden has also contributed a great deal of content to the User
|
||||
Guide.
|
||||
|
||||
- Jacques Pelletier has contributed the DS1501 RTC driver code.
|
||||
|
||||
- Jose Collado has contributed enhancements to the TMS driver
|
||||
including compatibility with standard TMS register configuration.
|
||||
|
||||
- Kevin Boone has contributed a generic HBIOS date/time utility
|
||||
(WDATE).
|
||||
|
||||
- Matt Carroll has contributed a fix to XM.COM that corrects the port
|
||||
specification when doing a send.
|
||||
|
||||
- Dean Jenkins enhanced the build process to accommodate the Raspberry
|
||||
Pi 4.
|
||||
|
||||
- Tom Plano has contributed a new utility (HTALK) to allow talking
|
||||
directly to HBIOS COM ports.
|
||||
|
||||
- Lars Nelson has contributed several generic utilities such as a
|
||||
universal (OS agnostic) UNARC application.
|
||||
|
||||
- Dylan Hall added support for specifying a secondary console.
|
||||
|
||||
- Bill Shen has contributed boot loaders for several of his systems.
|
||||
|
||||
- Laszlo Szolnoki has contributed an EF9345 video display controller
|
||||
driver.
|
||||
|
||||
- Ladislau Szilagyi has contributed an enhanced version of CP/M Cowgol
|
||||
that leverages RomWBW memory banking.
|
||||
|
||||
- Les Bird has contributed support for the NABU w/ Option Board
|
||||
|
||||
Contributions of all kinds to RomWBW are very welcome.
|
||||
|
||||
|
||||
|
||||
LICENSING
|
||||
|
||||
|
||||
RomWBW is free software: you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License as published by the Free
|
||||
Software Foundation, either version 3 of the License, or (at your
|
||||
option) any later version.
|
||||
|
||||
RomWBW is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with RomWBW. If not, see https://www.gnu.org/licenses/.
|
||||
|
||||
Portions of RomWBW were created by, contributed by, or derived from the
|
||||
work of others. It is believed that these works are being used in
|
||||
accordance with the intentions and/or licensing of their creators.
|
||||
|
||||
If anyone feels their work is being used outside of its intended
|
||||
licensing, please notify:
|
||||
|
||||
Wayne Warthen
|
||||
wwarthen@gmail.com
|
||||
|
||||
RomWBW is an aggregate work. It is composed of many individual,
|
||||
standalone programs that are distributed as a whole to function as a
|
||||
cohesive system. Each program may have its own licensing which may be
|
||||
different from other programs within the aggregate.
|
||||
|
||||
In some cases, a single program (e.g., CP/M Operating System) is
|
||||
composed of multiple components with different licenses. It is believed
|
||||
that in all such cases the licenses are compatible with GPL version 3.
|
||||
|
||||
RomWBW encourages code contributions from others. Contributors may
|
||||
assert their own copyright in their contributions by annotating the
|
||||
contributed source code appropriately. Contributors are further
|
||||
encouraged to submit their contributions via the RomWBW source code
|
||||
control system to ensure their contributions are clearly documented.
|
||||
|
||||
All contributions to RomWBW are subject to this license.
|
||||
|
||||
|
||||
|
||||
GETTING ASSISTANCE
|
||||
|
||||
|
||||
The best way to get assistance with RomWBW or any aspect of the
|
||||
RetroBrew Computers projects is via one of the community forums:
|
||||
|
||||
- RetroBrew Computers Forum
|
||||
- RC2014 Google Group
|
||||
- retro-comp Google Group
|
||||
|
||||
Submission of issues and bugs are welcome at the RomWBW GitHub
|
||||
Repository.
|
||||
|
||||
Also feel free to email Wayne Warthen at wwarthen@gmail.com.
|
||||
RomWBW ReadMe
|
||||
Wayne Warthen (wwarthen@gmail.com)
|
||||
06 Sep 2024
|
||||
|
||||
|
||||
|
||||
OVERVIEW
|
||||
|
||||
|
||||
RomWBW software provides a complete, commercial quality implementation
|
||||
of CP/M (and workalike) operating systems and applications for modern
|
||||
Z80/180/280 retro-computing hardware systems. A wide variety of
|
||||
platforms are supported including those produced by these developer
|
||||
communities:
|
||||
|
||||
- RetroBrew Computers (https://www.retrobrewcomputers.org)
|
||||
- RC2014 (https://rc2014.co.uk),
|
||||
RC2014-Z80 (https://groups.google.com/g/rc2014-z80)
|
||||
- Retro Computing (https://groups.google.com/g/retro-comp)
|
||||
- Small Computer Central (https://smallcomputercentral.com/)
|
||||
|
||||
A complete list of the currently supported platforms is found in the
|
||||
[Installation] section.
|
||||
|
||||
General features include:
|
||||
|
||||
- Z80 Family CPUs including Z80, Z180, and Z280
|
||||
- Banked memory services for several banking designs
|
||||
- Disk drivers for RAM, ROM, Floppy, IDE ATA/ATAPI, CF, SD, USB, Zip,
|
||||
Iomega
|
||||
- Serial drivers including UART (16550-like), ASCI, ACIA, SIO
|
||||
- Video drivers including TMS9918, SY6545, MOS8563, HD6445
|
||||
- Keyboard (PS/2) drivers via VT8242 or PPI interfaces
|
||||
- Real time clock drivers including DS1302, BQ4845
|
||||
- OSes: CP/M 2.2, ZSDOS, CP/M 3, NZ-COM, ZPM3, QPM, p-System, and
|
||||
FreeRTOS
|
||||
- Built-in VT-100 terminal emulation support
|
||||
|
||||
RomWBW is distributed as both source code and pre-built ROM and disk
|
||||
images. Some of the provided software can be launched directly from the
|
||||
ROM firmware itself:
|
||||
|
||||
- System Monitor
|
||||
- Operating Systems (CP/M 2.2, ZSDOS)
|
||||
- ROM BASIC (Nascom BASIC and Tasty BASIC)
|
||||
- ROM Forth
|
||||
|
||||
A dynamic disk drive letter assignment mechanism allows mapping
|
||||
operating system drive letters to any available disk media.
|
||||
Additionally, mass storage devices (IDE Disk, CF Card, SD Card, etc.)
|
||||
support the use of multiple slices (up to 256 per device). Each slice
|
||||
contains a complete CP/M filesystem and can be mapped independently to
|
||||
any drive letter. This overcomes the inherent size limitations in legacy
|
||||
OSes and allows up to 2GB of accessible storage on a single device.
|
||||
|
||||
The pre-built ROM firmware images are generally suitable for most users.
|
||||
However, it is also very easy to modify and build custom ROM images that
|
||||
fully tailor the firmware to your specific preferences. All tools
|
||||
required to build custom ROM firmware under Windows are included – no
|
||||
need to install assemblers, etc. The firmware can also be built using
|
||||
Linux or MacOS after confirming a few standard tools have been
|
||||
installed.
|
||||
|
||||
Multiple disk images are provided in the distribution. Most disk images
|
||||
contain a complete, bootable, ready-to-run implementation of a specific
|
||||
operating system. A “combo” disk image contains multiple slices, each
|
||||
with a full operating system implementation. If you use this disk image,
|
||||
you can easily pick whichever operating system you want to boot without
|
||||
changing media.
|
||||
|
||||
By design, RomWBW isolates all of the hardware specific functions in the
|
||||
ROM chip itself. The ROM provides a hardware abstraction layer such that
|
||||
all of the operating systems and applications on a disk will run on any
|
||||
RomWBW-based system. To put it simply, you can take a disk (or CF/SD/USB
|
||||
Card) and move it between systems transparently.
|
||||
|
||||
A tool is provided that allows you to access a FAT-12/16/32 filesystem.
|
||||
The FAT filesystem may be coresident on the same disk media as RomWBW
|
||||
slices or on stand-alone media. This makes exchanging files with modern
|
||||
OSes such as Windows, MacOS, and Linux very easy.
|
||||
|
||||
|
||||
|
||||
ACQUIRING ROMWBW
|
||||
|
||||
|
||||
The RomWBW Repository (https://github.com/wwarthen/RomWBW) on GitHub is
|
||||
the official distribution location for all project source and
|
||||
documentation. The fully-built distribution releases are available on
|
||||
the RomWBW Releases Page (https://github.com/wwarthen/RomWBW/releases)
|
||||
of the repository. On this page, you will normally see a Development
|
||||
Snapshot as well as recent stable releases. Unless you have a specific
|
||||
reason, I suggest you stick to the most recent stable release. Expand
|
||||
the “Assets” drop-down for the release you want to download, then select
|
||||
the asset named RomWBW-vX.X.X-Package.zip. The Package asset includes
|
||||
all pre-built ROM and Disk images as well as full source code. The other
|
||||
assets contain only source code and do not have the pre-built ROM or
|
||||
disk images.
|
||||
|
||||
All source code and distributions are maintained on GitHub. Code
|
||||
contributions are very welcome.
|
||||
|
||||
|
||||
|
||||
INSTALLATION & OPERATION
|
||||
|
||||
|
||||
In general, installation of RomWBW on your platform is very simple. You
|
||||
just need to program your ROM with the correct ROM image from the RomWBW
|
||||
distribution. Subsequently, you can write disk images on your disk
|
||||
drives (IDE disk, CF Card, SD Card, etc.) which then provides even more
|
||||
functionality.
|
||||
|
||||
Complete instructions for installation and operation of RomWBW are found
|
||||
in the RomWBW User Guide.
|
||||
|
||||
|
||||
Documentation
|
||||
|
||||
Documentation for RomWBW includes:
|
||||
|
||||
- RomWBW User Guide
|
||||
- RomWBW System Guide
|
||||
- RomWBW Applications
|
||||
- RomWBW Errata
|
||||
|
||||
|
||||
|
||||
ACKNOWLEDGMENTS
|
||||
|
||||
|
||||
I want to acknowledge that a great deal of the code and inspiration for
|
||||
RomWBW has been provided by or derived from the work of others in the
|
||||
RetroBrew Computers Community. I sincerely appreciate all of their
|
||||
contributions. The list below is probably missing many names – please
|
||||
let me know if I missed you!
|
||||
|
||||
- Andrew Lynch started it all when he created the N8VEM Z80 SBC which
|
||||
became the first platform RomWBW supported. Some of his original
|
||||
code can still be found in RomWBW.
|
||||
|
||||
- Dan Werner wrote much of the code from which RomWBW was originally
|
||||
derived and he has always been a great source of knowledge and
|
||||
advice.
|
||||
|
||||
- Douglas Goodall contributed code, time, testing, and advice in “the
|
||||
early days”. He created an entire suite of application programs to
|
||||
enhance the use of RomWBW. Unfortunately, they have become unusable
|
||||
due to internal changes within RomWBW. As of RomWBW 2.6, these
|
||||
applications are no longer provided.
|
||||
|
||||
- Sergey Kiselev created several hardware platforms for RomWBW
|
||||
including the very popular Zeta.
|
||||
|
||||
- David Giles created support for the Z180 CSIO which is now included
|
||||
SD Card driver.
|
||||
|
||||
- Phil Summers contributed the Forth and BASIC adaptations in ROM, the
|
||||
AY-3-8910 sound driver, DMA support, and a long list of general code
|
||||
and documentation enhancements.
|
||||
|
||||
- Ed Brindley contributed some of the code that supports the RCBus
|
||||
platform.
|
||||
|
||||
- Spencer Owen created the RC2014 series of hobbyist kit computers
|
||||
which has exponentially increased RomWBW usage. Some of his kits
|
||||
include RomWBW.
|
||||
|
||||
- Stephen Cousins has likewise created a series of hobbyist kit
|
||||
computers at Small Computer Central and is distributing RomWBW with
|
||||
many of them.
|
||||
|
||||
- Alan Cox has contributed some driver code and has provided a great
|
||||
deal of advice.
|
||||
|
||||
- The CP/NET client files were developed by Douglas Miller.
|
||||
|
||||
- Phillip Stevens contributed support for FreeRTOS.
|
||||
|
||||
- Curt Mayer contributed the original Linux / MacOS build process.
|
||||
|
||||
- UNA BIOS and FDISK80 are the products of John Coffman.
|
||||
|
||||
- FLASH4 is a product of Will Sowerbutts.
|
||||
|
||||
- CLRDIR is a product of Max Scane.
|
||||
|
||||
- Tasty Basic is a product of Dimitri Theulings.
|
||||
|
||||
- Dean Netherton contributed the sound driver interface and the
|
||||
SN76489 sound driver.
|
||||
|
||||
- The RomWBW Disk Catalog document was produced by Mykl Orders.
|
||||
|
||||
- Rob Prouse has created many of the supplemental disk images
|
||||
including Aztec C, HiTech C, SLR Z80ASM, Turbo Pascal, Microsoft
|
||||
BASIC Compiler, Microsoft Fortran Compiler, and a Games compendium.
|
||||
|
||||
- Martin R has provided substantial help reviewing and improving the
|
||||
User Guide and Applications documents.
|
||||
|
||||
- Mark Pruden has also contributed a great deal of content to the User
|
||||
Guide.
|
||||
|
||||
- Jacques Pelletier has contributed the DS1501 RTC driver code.
|
||||
|
||||
- Jose Collado has contributed enhancements to the TMS driver
|
||||
including compatibility with standard TMS register configuration.
|
||||
|
||||
- Kevin Boone has contributed a generic HBIOS date/time utility
|
||||
(WDATE).
|
||||
|
||||
- Matt Carroll has contributed a fix to XM.COM that corrects the port
|
||||
specification when doing a send.
|
||||
|
||||
- Dean Jenkins enhanced the build process to accommodate the Raspberry
|
||||
Pi 4.
|
||||
|
||||
- Tom Plano has contributed a new utility (HTALK) to allow talking
|
||||
directly to HBIOS COM ports.
|
||||
|
||||
- Lars Nelson has contributed several generic utilities such as a
|
||||
universal (OS agnostic) UNARC application.
|
||||
|
||||
- Dylan Hall added support for specifying a secondary console.
|
||||
|
||||
- Bill Shen has contributed boot loaders for several of his systems.
|
||||
|
||||
- Laszlo Szolnoki has contributed an EF9345 video display controller
|
||||
driver.
|
||||
|
||||
- Ladislau Szilagyi has contributed an enhanced version of CP/M Cowgol
|
||||
that leverages RomWBW memory banking.
|
||||
|
||||
- Les Bird has contributed support for the NABU w/ Option Board
|
||||
|
||||
Contributions of all kinds to RomWBW are very welcome.
|
||||
|
||||
|
||||
|
||||
LICENSING
|
||||
|
||||
|
||||
RomWBW is free software: you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License as published by the Free
|
||||
Software Foundation, either version 3 of the License, or (at your
|
||||
option) any later version.
|
||||
|
||||
RomWBW is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with RomWBW. If not, see https://www.gnu.org/licenses/.
|
||||
|
||||
Portions of RomWBW were created by, contributed by, or derived from the
|
||||
work of others. It is believed that these works are being used in
|
||||
accordance with the intentions and/or licensing of their creators.
|
||||
|
||||
If anyone feels their work is being used outside of its intended
|
||||
licensing, please notify:
|
||||
|
||||
Wayne Warthen
|
||||
wwarthen@gmail.com
|
||||
|
||||
RomWBW is an aggregate work. It is composed of many individual,
|
||||
standalone programs that are distributed as a whole to function as a
|
||||
cohesive system. Each program may have its own licensing which may be
|
||||
different from other programs within the aggregate.
|
||||
|
||||
In some cases, a single program (e.g., CP/M Operating System) is
|
||||
composed of multiple components with different licenses. It is believed
|
||||
that in all such cases the licenses are compatible with GPL version 3.
|
||||
|
||||
RomWBW encourages code contributions from others. Contributors may
|
||||
assert their own copyright in their contributions by annotating the
|
||||
contributed source code appropriately. Contributors are further
|
||||
encouraged to submit their contributions via the RomWBW source code
|
||||
control system to ensure their contributions are clearly documented.
|
||||
|
||||
All contributions to RomWBW are subject to this license.
|
||||
|
||||
|
||||
|
||||
GETTING ASSISTANCE
|
||||
|
||||
|
||||
The best way to get assistance with RomWBW or any aspect of the
|
||||
RetroBrew Computers projects is via one of the community forums:
|
||||
|
||||
- RetroBrew Computers Forum
|
||||
- RC2014 Google Group
|
||||
- retro-comp Google Group
|
||||
|
||||
Submission of issues and bugs are welcome at the RomWBW GitHub
|
||||
Repository.
|
||||
|
||||
Also feel free to email Wayne Warthen at wwarthen@gmail.com.
|
||||
|
||||
@@ -2,8 +2,12 @@
|
||||
setlocal
|
||||
|
||||
::
|
||||
:: NOTE: Pandoc and Latex (MiKTeX or TexLive) must be installed
|
||||
:: and available on commandline for this build to work!!!
|
||||
:: NOTE: Pandoc, LuaLatex (MiKTeX or TexLive), and Roboto Font
|
||||
:: must be installed and available on commandline for this build to work!!!
|
||||
::
|
||||
:: - Pandoc (https://pandoc.org/)
|
||||
:: - MiKTeX (https://miktex.org/)
|
||||
:: - Install Roboto font from MiKTeX Console
|
||||
::
|
||||
|
||||
set TOOLS=..\..\Tools
|
||||
@@ -35,9 +39,6 @@ echo.
|
||||
|
||||
echo Processing document %1...
|
||||
|
||||
::gpp -o %1.tmp %1.md
|
||||
::gpp -o %1.tmp -U "\\" "" "{" "}{" "}" "{" "}" "#" "" %1.md
|
||||
::gpp -o %1.tmp -U "" "" "(" "," ")" "(" ")" "#" "" -M "#" "\n" " " " " "\n" "(" ")" %1.md
|
||||
gpp -o %1.tmp -U "$" "$" "{" "}{" "}$" "{" "}" "@@@" "" -M "$" "$" "{" "}{" "}$" "{" "}" %1.md || exit /b
|
||||
|
||||
::pandoc %1.tmp -f markdown -t latex -s -o %1.tex --default-image-extension=pdf || exit /b
|
||||
|
||||
@@ -1,11 +1,14 @@
|
||||
#
|
||||
# NOTE: gpp, Pandoc, and Latex (MiKTeX or TexLive) must be installed
|
||||
# NOTE: gpp, Pandoc, LuaLatex (MiKTeX or TexLive), and Roboto Font must be installed
|
||||
# and available on commandline for this build to work!!!
|
||||
# Typically "sudo apt install gpp pandoc texlive-latex-extra texlive-luatex texlive-fonts-extra fonts-roboto"
|
||||
# On Macintosh
|
||||
#
|
||||
# On MacOS:
|
||||
# brew install gpp pandoc texlive
|
||||
# brew install --cask font-roboto
|
||||
#
|
||||
# On Ubuntu Linux:
|
||||
# apt install gpp pandoc texlive texlive-luatex texlive-fonts-extra
|
||||
#
|
||||
OBJECTS = ReadMe.gfm ReadMe.txt UserGuide.pdf SystemGuide.pdf Applications.pdf Catalog.pdf Errata.pdf
|
||||
# DEST = ../../Doc
|
||||
TOOLS = ../../Tools
|
||||
@@ -40,4 +43,4 @@ deploy :
|
||||
cp SystemGuide.pdf "../../Doc/RomWBW System Guide.pdf"
|
||||
cp Applications.pdf "../../Doc/RomWBW Applications.pdf"
|
||||
cp Catalog.pdf "../../Doc/RomWBW Disk Catalog.pdf"
|
||||
cp Errata.pdf "../../Doc/RomWBW Errata.pdf"
|
||||
cp Errata.pdf "../../Doc/RomWBW Errata.pdf"
|
||||
|
||||
@@ -1072,6 +1072,18 @@ The concept of slices is described in detail in the section
|
||||
The mapping of a hardware disk (and slice) to a Drive letter
|
||||
in an operating system. A Drive has a file system installed on it
|
||||
|
||||
#### Disk Image
|
||||
|
||||
A disk image is a predefined image of a complete CP/M filesystem,
|
||||
or filesystem(s), including any partition tables (for hard disk images).
|
||||
Each disk image has the complete set of normal applications and tools
|
||||
distributed with the associated operating system or application suite.
|
||||
|
||||
This comes in for form of a file which is suitable for copying directly
|
||||
onto target media, using a modern computer. It is generally easier to
|
||||
use these disk images than transferring files over individually.
|
||||
See the section [Disk Images] for further details.
|
||||
|
||||
## Startup Hardware Discovery
|
||||
|
||||
During startup RomWBW performs detection for hardware supported by your
|
||||
@@ -1241,16 +1253,17 @@ With some understanding of how RomWBW presents disk space to the
|
||||
operating systems, we need to go over the options for actually setting
|
||||
up your disk(s) with content.
|
||||
|
||||
### Preparing Media for first use
|
||||
### Preparing Media for First Use
|
||||
|
||||
You can initialize the media in-place using your RomWBW system.
|
||||
Essentially, this means you are creating a set of blank directories on
|
||||
your disk so that files can be saved there.
|
||||
This is somewhat analogous to partitioning partitioning of a hard disk
|
||||
This is somewhat analogous to partitioning of a hard disk
|
||||
or doing a low level format of a floppy disk.
|
||||
|
||||
Initilizing a Floppy disk is covered in the section [Floppy Disk Formatting],
|
||||
or for a Hard disk the section [Hard Disk Preparation]
|
||||
or for a Hard disk the section [Hard Disk Preparation] covers the steps to
|
||||
manually setup a hard disk for first use.
|
||||
|
||||
### Clearing (Formatting) Drives
|
||||
|
||||
@@ -1298,30 +1311,6 @@ Directory cleared.
|
||||
B>
|
||||
```
|
||||
|
||||
### Making Bootable Media
|
||||
|
||||
If you want to make a disk bootable, you will need to use `SYSCOPY` to
|
||||
setup the system track(s) of the slice.
|
||||
The use of `SYSCOPY` depends on the operating system and is
|
||||
described in the [Operating Systems] chapter of this document.
|
||||
|
||||
As an example, let's assume you want to setup C: as a bootable Z-System disk.
|
||||
To setup the system track you would use:
|
||||
|
||||
```
|
||||
B>SYSCOPY C:=B:ZSYS.SYS
|
||||
|
||||
SYSCOPY v2.0 for RomWBW CP/M, 17-Feb-2020 (CP/M 2 Mode)
|
||||
Copyright 2020, Wayne Warthen, GNU GPL v3
|
||||
|
||||
Transfer system image from B:ZSYS.SYS to C: (Y/N)? Y
|
||||
Reading image... Writing image... Done
|
||||
```
|
||||
|
||||
Once this process succeeds, you will be able to boot directly to the
|
||||
disk slice from the boot loader prompt. See the instructions in
|
||||
[Starting Operating Systems from Disk] for details on this.
|
||||
|
||||
### Checking Disk Layout
|
||||
|
||||
If you are not sure which disk layout is used for your existing
|
||||
@@ -1643,10 +1632,7 @@ There are two approaches to preparing disks for use by RomWBW.
|
||||
including files to a disk.
|
||||
|
||||
This section of the document describes the manual process of preparing
|
||||
empty disks that are ready for use by an operating system. You will
|
||||
need to refer to [Transferring Files] for more information on getting
|
||||
files onto the disks. You will also need to follow the instructions
|
||||
in [Operating Systems] to make disks bootable.
|
||||
empty disks that are ready for use by an operating system.
|
||||
|
||||
Alternatively, you can use the pre-built RomWBW disk images to quickly
|
||||
create disk media that already has a large selection of files and
|
||||
@@ -1760,7 +1746,7 @@ First you need to understand
|
||||
|
||||
* The disk layout approach (either hd1k or the legacy hd512).
|
||||
See [Hard Disk Layouts] section if you are not sure.
|
||||
HD1K should be the preferred layout.
|
||||
hd1k should be the preferred layout.
|
||||
* The number of 8MB slices that you want to allocate, preferred is 64 slices.
|
||||
At least 1 slice of 8MB is required
|
||||
* If you want to leave space for a FAT partition. See [FAT Filesystem Preparation]
|
||||
@@ -1787,9 +1773,9 @@ The disk unit number was assigned at boot See [Device Unit Assignments]
|
||||
|
||||
Refer to $doc_apps$ for more information on use of the `FDISK80` utility.
|
||||
|
||||
If you want to use the legacy hd512 layout skip down to the [Legacy (HD512)] section
|
||||
If you want to use the legacy hd512 layout skip down to the [Legacy (hd512)] section
|
||||
|
||||
#### Modern (HD1K)
|
||||
#### Modern (hd1k)
|
||||
|
||||
At this point, use the `I` command to initialize (reset)
|
||||
the partition table to an empty state.
|
||||
@@ -1849,7 +1835,7 @@ At this point, it is best to restart your system to make sure that
|
||||
the operating system is aware of the partition table updates. Start
|
||||
CP/M 2.2 or Z-System from ROM again.
|
||||
|
||||
#### Legacy (HD512)
|
||||
#### Legacy (hd512)
|
||||
|
||||
At this point, use the `I` command to initialize (reset)
|
||||
the partition table to an empty state.
|
||||
@@ -1862,6 +1848,12 @@ At this point, it is best to restart your system to make sure that
|
||||
the operating system is aware of the partition table updates. Start
|
||||
CP/M 2.2 or Z-System from ROM again.
|
||||
|
||||
#### FAT Partition
|
||||
|
||||
At this point you may want to consider creating a FAT partition
|
||||
Please see the section [FAT Filesystem Preparation] for detils on how
|
||||
to setup the FAT partition.
|
||||
|
||||
### Slice Initialization
|
||||
|
||||
You need to initialize each slice for CP/M to use it.
|
||||
@@ -1880,6 +1872,43 @@ using the same process. You may need to reassign drive letters to
|
||||
access some slices that are beyond the ones automatically assigned.
|
||||
You can use the `ASSIGN` command to handle this.
|
||||
|
||||
## Post Disk Preparation
|
||||
|
||||
Once a disk (either floppy or hard disk) has been initialised and
|
||||
formattted you may optionally;
|
||||
* Make the disk bootable
|
||||
* Copy system (or other) files to the disk
|
||||
|
||||
### Making a Disk Bootable
|
||||
|
||||
To make a disk bootable you will need to follow the specific instructions
|
||||
in [Operating Systems], as each operating system will be different.
|
||||
|
||||
Generally you will need to use `SYSCOPY` to setup the system track(s)
|
||||
of the disk.As an example, If you wanted to setup C: as a bootable
|
||||
Z-System disk you would use:
|
||||
|
||||
```
|
||||
B>SYSCOPY C:=B:ZSYS.SYS
|
||||
|
||||
SYSCOPY v2.0 for RomWBW CP/M, 17-Feb-2020 (CP/M 2 Mode)
|
||||
Copyright 2020, Wayne Warthen, GNU GPL v3
|
||||
|
||||
Transfer system image from B:ZSYS.SYS to C: (Y/N)? Y
|
||||
Reading image... Writing image... Done
|
||||
```
|
||||
|
||||
Once this process succeeds, you will be able to boot directly to the
|
||||
disk slice from the boot loader prompt. See the instructions in
|
||||
[Starting Operating Systems from Disk] for details on this.
|
||||
|
||||
### Copying System Files
|
||||
|
||||
As well as making the disk bootable, you may need to transfer other
|
||||
system and application files to your disks.
|
||||
Refer to [Transferring Files] for more information on getting
|
||||
files onto your disks.
|
||||
|
||||
# Disk Images
|
||||
|
||||
Since it would be quite a bit of work to transfer over all the files you
|
||||
@@ -2072,13 +2101,19 @@ positions indicated:
|
||||
| Slice 5 | WordStar v4 & ZDE Applications |
|
||||
| Slice 6-63 | _blank unformatted_ |
|
||||
|
||||
There are actually 2 combo disk images in the
|
||||
There are actually 2 primary combo disk images in the
|
||||
distribution. One for an hd512 disk layout (hd512_combo.img) and one
|
||||
for an hd1k disk layout (hd1k_combo.img). Simply use the image file that
|
||||
corresponds to your desired hard disk layout. Review the information
|
||||
in [Hard Disk Layouts] if you need more information of the disk layout
|
||||
options.
|
||||
|
||||
> **Note**: Apart from the hd512 and hd1k combo disk images (mentioned above)
|
||||
> there are actaully a number of other `hd1k_*_combo.img` files. These
|
||||
> additional combo files are platform (generally romless) specific,
|
||||
> and should be ignored unless you are on one of these platforms.
|
||||
> If you are on one of these platforms you must use the correct combo file
|
||||
|
||||
The combo disk image actaully only contains the initial partition table,
|
||||
and the first 6 slices (Slice 0 to 5), this is approximately 49MB in size.
|
||||
While the partition table reserves space to store 64 CP/M filesystem
|
||||
@@ -2175,6 +2210,12 @@ Linux/MacOS:
|
||||
|
||||
`cat hd1k_prefix.dat hd1k_cpm22.img hd1k_cpm3.img hd1k_ws >hd.img`
|
||||
|
||||
> **Note**: Apart from the hd1k_prefix.dat file (mentioned above)
|
||||
> there are actaully a number of other `hd1k_*_prefix.dat` files. These
|
||||
> additional prefix files are platform (generally romless) specific,
|
||||
> and should be ignored unless you are on one of these platforms.
|
||||
> If you are on one of these platforms you must use the correct prefix file
|
||||
|
||||
In all of the examples above, the resulting file (hd.img) would now be
|
||||
written to your hard disk media and would be ready to use in a RomWBW
|
||||
system.
|
||||
@@ -2963,195 +3004,6 @@ floppy disk and hard disk images.
|
||||
| TUNE | Play .PT2, .PT3, .MYM audio files. |
|
||||
| INTTEST | Test interrupt vector hooking. |
|
||||
|
||||
# FAT Filesystem
|
||||
|
||||
The FAT filesystem format that originated with MS-DOS is almost
|
||||
ubiquitous across modern computers. Virtually all operating systems
|
||||
now support reading and writing files to a FAT filesystem. For this
|
||||
reason, RomWBW now has the ability to read and write files on FAT
|
||||
filesystems.
|
||||
|
||||
This is accomplished by running a RomWBW custom application called `FAT`.
|
||||
This application understands both FAT filesystems as well as CP/M filesystems.
|
||||
|
||||
* Files can be copied between a FAT filesystem and a CP/M filesystem,
|
||||
but you cannot execute files directly from a FAT filesystem.
|
||||
* FAT12, FAT16, and FAT32 formats are supported.
|
||||
* Long filenames are not supported. Files with long filenames will
|
||||
show up with their names truncated into the older 8.3 convention.
|
||||
* A FAT filesystem can be located on floppy or hard disk media. For
|
||||
hard disk media, a valid FAT Filesystem partition must exist.
|
||||
* Note that CP/M (and compatible) OSes do not support all of the
|
||||
filename characters that a modern computer does. The following
|
||||
characters are **not permitted** in a CP/M filename:
|
||||
|
||||
`< > . , ; : = ? * [ ] _ % | ( ) / \`
|
||||
|
||||
The FAT application does not auto-rename files when it encounters
|
||||
invalid filenames. It will just issue an error and quit.
|
||||
Additionally, the error message is not very clear about the problem.
|
||||
|
||||
## FAT Filesystem Preparation
|
||||
|
||||
In general, you can create media formatted with a FAT filesystem on
|
||||
your RomWBW computer or on your modern computer. We will only be
|
||||
discussing the RomWBW-based approach here.
|
||||
|
||||
In the case of a floppy disk, you can use the `FAT` application to
|
||||
format the floppy disk. The floppy disk must already be physically
|
||||
formatted using RomWBW FDU or equivalent. If your floppy disk is on
|
||||
RomWBW disk unit 2, you could use `FAT FORMAT 2:`. This will overwrite
|
||||
the floppy with a FAT filesystem and all previous contents will be lost.
|
||||
Once formatted this way, the floppy disk can be used in a floppy drive
|
||||
attached to a modern computer or it can be used on RomWBW using the
|
||||
other `FAT` tool commands.
|
||||
|
||||
In the case of hard disk media, it is necessary to have a FAT
|
||||
partition. If you prepared your RomWBW hard disk media using the
|
||||
disk image process, then this partition will already be defined and
|
||||
you do not need to recreate it. This default FAT partition is located
|
||||
at approximately 512MB from the start of your disk and it is 384MB in
|
||||
size. So, your hard disk media must be 1GB or greater to use this
|
||||
default FAT partition.
|
||||
|
||||
You can confirm the existence of the FAT partition with `FDISK80` by
|
||||
using the 'P' command to show the current partition table. Here is an
|
||||
example of a partition table listing from `FDISK80` that includes the
|
||||
FAT partition (labelled "FAT16"):
|
||||
|
||||
```
|
||||
Capacity of disk 4: ( 4G) 7813120 Geom 77381010
|
||||
Nr ---Type- A -- Start End LBA start LBA count Size
|
||||
1 RomWBW 2e 8:0:1 1023:15:16 2048 1048576 512M
|
||||
2 FAT16 06 1023:0:1 1023:15:16 1050624 786432 384M
|
||||
3 00 *** empty ***
|
||||
4 00 *** empty ***
|
||||
```
|
||||
|
||||
If your hard disk media does not have a FAT partition already defined,
|
||||
you will need to define one using FDISK80 by using the 'N' command.
|
||||
Ensure that the location and size of the FAT partition does not
|
||||
overlap any of the CP/M slice area and that it fits within the size
|
||||
of your media.
|
||||
|
||||
Once the partition is defined, you will still need to format it. Just
|
||||
as with a floppy disk, you use the `FAT` tool to do this. If your
|
||||
hard disk media is on RomWBW disk unit 4, you would use `FAT FORMAT 4:`.
|
||||
This will look something like this:
|
||||
|
||||
```
|
||||
E>fat format 4:
|
||||
|
||||
About to format FAT Filesystem on Disk Unit #4.
|
||||
All existing FAT partition data will be destroyed!!!
|
||||
|
||||
Continue (y/n)?
|
||||
|
||||
Formatting... Done
|
||||
```
|
||||
|
||||
Your FAT filesystem is now ready to use.
|
||||
|
||||
If your RomWBW system has multiple disk drives/slots, you can also just
|
||||
create a disk with your modern computer that is a dedicated FAT
|
||||
filesystem disk. You can use your modern computer to format the disk
|
||||
(floppy, CF Card, SD Card, etc.), then insert the disk in your RomWBW
|
||||
computer and access it using `FAT` based on its RomWBW unit number.
|
||||
|
||||
**WARNING**: Microsoft Windows will sometimes suggest reformatting
|
||||
partitions that it does not recognize. If you are prompted to format a
|
||||
partition of your SD/CF/USB Media when inserting the card into a Windows
|
||||
computer, you probably want to select Cancel.
|
||||
|
||||
## FAT Application Usage
|
||||
|
||||
Complete instructions for the `FAT` application are found in $doc_apps$.
|
||||
Here, we will just provide a couple of simple examples. Note that the
|
||||
FAT application is not on the ROM disk because it is too large to
|
||||
include there.
|
||||
|
||||
The most important thing to understand about the `FAT` application is
|
||||
how it refers to FAT filesystems vs. CP/M filesystems. It infers this
|
||||
based on the file specification provided. If you use a specification
|
||||
like `C:SAMPLE.TXT`, it will use the C: drive of your CP/M operating
|
||||
system. If you use a specification like `4:SAMPLE.TXT`, it will use
|
||||
the FAT filesystem on the disk in RomWBW disk unit 4. Basically, if
|
||||
you start your file or directory specification with a number followed
|
||||
by a colon, it means FAT filesystem. Anything else will mean CP/M
|
||||
filesystem.
|
||||
|
||||
Here are a few examples. This first example shows how to get a FAT
|
||||
directory listing from RomWBW disk unit 4:
|
||||
|
||||
```
|
||||
E>fat dir 4:
|
||||
|
||||
Directory of 4:
|
||||
|
||||
|
||||
E>
|
||||
```
|
||||
|
||||
As you can see, there are currently no files there. Now let's copy
|
||||
a file from CP/M to the FAT directory:
|
||||
|
||||
```
|
||||
E>fat copy sample.txt 4:
|
||||
|
||||
Copying...
|
||||
|
||||
SAMPLE.TXT ==> 4:/SAMPLE.TXT ... [OK]
|
||||
|
||||
1 File(s) Copied
|
||||
```
|
||||
|
||||
If we list the FAT directory again, you will see the file:
|
||||
|
||||
```
|
||||
E>fat dir 4:
|
||||
|
||||
Directory of 4:
|
||||
|
||||
01/30/2023 17:50:14 29952 ---A SAMPLE.TXT
|
||||
|
||||
```
|
||||
|
||||
Now let's copy the file from the FAT filesystem back to CP/M. This
|
||||
time we will get a warning about overwriting the file. For this
|
||||
example, we don't want to do that, so we abort and reissue the
|
||||
command specifying a new filename to use:
|
||||
|
||||
```
|
||||
E>fat copy 4:sample.txt e:
|
||||
|
||||
Copying...
|
||||
|
||||
4:/SAMPLE.TXT ==> E:SAMPLE.TXT Overwrite? (Y/N) [Skipped]
|
||||
|
||||
0 File(s) Copied
|
||||
|
||||
E>fat copy 4:sample.txt e:sample2.txt
|
||||
|
||||
Copying...
|
||||
|
||||
4:/SAMPLE.TXT ==> E:SAMPLE2.TXT ... [OK]
|
||||
|
||||
1 File(s) Copied
|
||||
```
|
||||
|
||||
Finally, let's try using wildcards:
|
||||
|
||||
```
|
||||
E>fat copy sample*.* 4:
|
||||
|
||||
Copying...
|
||||
|
||||
SAMPLE.TXT ==> 4:/SAMPLE.TXT Overwrite? (Y/N) ... [OK]
|
||||
SAMPLE2.TXT ==> 4:/SAMPLE2.TXT ... [OK]
|
||||
|
||||
2 File(s) Copied
|
||||
```
|
||||
|
||||
# Real Time Clock
|
||||
|
||||
RomWBW supports a variety of real time clock hardware. If your
|
||||
@@ -3928,35 +3780,222 @@ detail in the Source/Images directory of the distribution.
|
||||
|
||||
## FAT Filesystem Transfers
|
||||
|
||||
The ability to interact with FAT filesystems was covered in
|
||||
[FAT Filesystem]. This capability means that you can generally use your
|
||||
modern computer to make an SD Card, CF Card, or USB Drive with a
|
||||
standard FAT32 filesystem on it, then place that media in your RomWBW
|
||||
computer and access the files.
|
||||
The FAT filesystem format that originated with MS-DOS is almost
|
||||
ubiquitous across modern computers. Virtually all operating systems
|
||||
now support reading and writing files to a FAT filesystem. For this
|
||||
reason, RomWBW now has the ability to read and write files on FAT
|
||||
filesystems.
|
||||
|
||||
When formatting the media on your modern computer, be sure to pick the
|
||||
FAT filesystem. NTFS and other filesystems will not work. As previously
|
||||
mentioned, the `FAT` application does not understand long filenames,
|
||||
only the traditional 8.3 filenames. If you have files on your modern
|
||||
computer with long filenames, it is usually easiest to rename them on
|
||||
the modern computer.
|
||||
This capability means that you can generally use your modern computer
|
||||
to make an SD Card, CF Card, or USB Drive with a standard FAT filesystem
|
||||
on it, then place that media in your RomWBW computer and access the files.
|
||||
|
||||
* Files can be copied between a FAT filesystem and a CP/M filesystem,
|
||||
but you cannot execute files directly from a FAT filesystem.
|
||||
|
||||
* FAT12, FAT16, and FAT32 formats are supported.
|
||||
|
||||
* Long filenames are not supported. Files with long filenames will
|
||||
show up with their names truncated into the older 8.3 convention.
|
||||
If you have files on your modern computer with long filenames,
|
||||
it is usually easiest to rename them on the modern computer.
|
||||
|
||||
* A FAT filesystem can be located on floppy or hard disk media. For
|
||||
hard disk media, a valid FAT Filesystem partition must exist.
|
||||
|
||||
Some additional **Notes** and **WARNINGS** Things to be careful about
|
||||
|
||||
* CP/M (and compatible) OSes do not support all of the
|
||||
filename characters that a modern computer does. The following
|
||||
characters are **not permitted** in a CP/M filename:
|
||||
|
||||
`< > . , ; : = ? * [ ] _ % | ( ) / \`
|
||||
|
||||
The FAT application does not auto-rename files when it encounters
|
||||
invalid filenames. It will just issue an error and quit.
|
||||
Additionally, the error message is not very clear about the problem.
|
||||
|
||||
* Microsoft Windows will sometimes suggest **reformatting**
|
||||
partitions that it does not recognize (e.g. RomWBW).
|
||||
If you are using media that contains both a FAT partition
|
||||
and a RomWBW partition you may prompted to format a partition of your
|
||||
SD/CF/USB Media when inserting the card into a Windows computer,
|
||||
you probably want to select Cancel.
|
||||
|
||||
### FAT Filesystem Preparation
|
||||
|
||||
In general, you can create media formatted with a FAT filesystem on
|
||||
your RomWBW computer or on your modern computer. We will only be
|
||||
discussing the RomWBW-based approach here.
|
||||
|
||||
#### Floppy Disk
|
||||
|
||||
In the case of a floppy disk, you can use the `FAT` application to
|
||||
format the floppy disk. The floppy disk must already be physically
|
||||
formatted using RomWBW FDU or equivalent. If your floppy disk is on
|
||||
RomWBW disk unit 2, you could use `FAT FORMAT 2:`. This will overwrite
|
||||
the floppy with a FAT filesystem and all previous contents will be lost.
|
||||
Once formatted this way, the floppy disk can be used in a floppy drive
|
||||
attached to a modern computer or it can be used on RomWBW using the
|
||||
other `FAT` tool commands.
|
||||
|
||||
#### Hard Disk
|
||||
|
||||
In the case of hard disk media, it is necessary to have a FAT
|
||||
partition. If you prepared your RomWBW hard disk media using the
|
||||
disk image process, then this partition will already be defined and
|
||||
you do not need to recreate it. This default FAT partition is located
|
||||
at approximately 512MB from the start of your disk and it is 384MB in
|
||||
size. So, your hard disk media must be 1GB or greater to use this
|
||||
default FAT partition.
|
||||
|
||||
You can confirm the existence of the FAT partition with `FDISK80` by
|
||||
using the 'P' command to show the current partition table. Here is an
|
||||
example of a partition table listing from `FDISK80` that includes the
|
||||
FAT partition (labelled "FAT16"):
|
||||
|
||||
```
|
||||
Capacity of disk 4: ( 4G) 7813120 Geom 77381010
|
||||
Nr ---Type- A -- Start End LBA start LBA count Size
|
||||
1 RomWBW 2e 8:0:1 1023:15:16 2048 1048576 512M
|
||||
2 FAT16 06 1023:0:1 1023:15:16 1050624 786432 384M
|
||||
3 00 *** empty ***
|
||||
4 00 *** empty ***
|
||||
```
|
||||
|
||||
If your hard disk media does not have a FAT partition already defined,
|
||||
you will need to define one using FDISK80 by using the 'N' command.
|
||||
Ensure that the location and size of the FAT partition does not
|
||||
overlap any of the CP/M slice area and that it fits within the size
|
||||
of your media.
|
||||
|
||||
Once the partition is defined, you will still need to format it. Just
|
||||
as with a floppy disk, you use the `FAT` tool to do this. If your
|
||||
hard disk media is on RomWBW disk unit 4, you would use `FAT FORMAT 4:`.
|
||||
This will look something like this:
|
||||
|
||||
```
|
||||
E>fat format 4:
|
||||
|
||||
About to format FAT Filesystem on Disk Unit #4.
|
||||
All existing FAT partition data will be destroyed!!!
|
||||
|
||||
Continue (y/n)?
|
||||
|
||||
Formatting... Done
|
||||
```
|
||||
|
||||
Your FAT filesystem is now ready to use.
|
||||
|
||||
If your RomWBW system has multiple disk drives/slots, you can also just
|
||||
create a disk with your modern computer that is a dedicated FAT
|
||||
filesystem disk. You can use your modern computer to format the disk
|
||||
(floppy, CF Card, SD Card, etc.), then insert the disk in your RomWBW
|
||||
computer and access it using `FAT` based on its RomWBW unit number.
|
||||
|
||||
### FAT Application Usage
|
||||
|
||||
Transferring files is accomplished by running a RomWBW custom application
|
||||
called `FAT`. This application understands both FAT filesystems as well
|
||||
as CP/M filesystems.
|
||||
|
||||
To copy files from your modern computer to your RomWBW computer, start
|
||||
by putting the disk media with the FAT filesystem in your modern
|
||||
computer. The modern computer should recognize it. Then copy the files
|
||||
you want to get to your RomWBW computer onto this media. Once done,
|
||||
remove the media from your modern computer and insert it in the RomWBW
|
||||
computer. Finally, use the `FAT` tool to copy the files onto a CP/M
|
||||
drive.
|
||||
computer.
|
||||
|
||||
This process works just fine in reverse if you want to copy files from a
|
||||
Finally, use the `FAT` tool to copy the files onto a CP/M
|
||||
drive. This process works just fine in reverse if you want to copy files from a
|
||||
CP/M filesystem to your modern computer.
|
||||
|
||||
**WARNING**: If you are using media that contains both a FAT partition
|
||||
and a RomWBW partition, your modern computer may be confused by the
|
||||
RomWBW partition. In some cases, it will prompt you to format the
|
||||
RomWBW partition because it doesn't know what it is. You will be
|
||||
prompted before it does this -- just be careful not to allow it.
|
||||
Complete instructions for the `FAT` application are found in $doc_apps$.
|
||||
Here, we will just provide a couple of simple examples. Note that the
|
||||
FAT application is not on the ROM disk because it is too large to
|
||||
include there.
|
||||
|
||||
The most important thing to understand about the `FAT` application is
|
||||
how it refers to FAT filesystems vs. CP/M filesystems. It infers this
|
||||
based on the file specification provided. If you use a specification
|
||||
like `C:SAMPLE.TXT`, it will use the C: drive of your CP/M operating
|
||||
system. If you use a specification like `4:SAMPLE.TXT`, it will use
|
||||
the FAT filesystem on the disk in RomWBW disk unit 4. Basically, if
|
||||
you start your file or directory specification with a number followed
|
||||
by a colon, it means FAT filesystem. Anything else will mean CP/M
|
||||
filesystem.
|
||||
|
||||
Here are a few examples. This first example shows how to get a FAT
|
||||
directory listing from RomWBW disk unit 4:
|
||||
|
||||
```
|
||||
E>fat dir 4:
|
||||
|
||||
Directory of 4:
|
||||
|
||||
|
||||
E>
|
||||
```
|
||||
|
||||
As you can see, there are currently no files there. Now let's copy
|
||||
a file from CP/M to the FAT directory:
|
||||
|
||||
```
|
||||
E>fat copy sample.txt 4:
|
||||
|
||||
Copying...
|
||||
|
||||
SAMPLE.TXT ==> 4:/SAMPLE.TXT ... [OK]
|
||||
|
||||
1 File(s) Copied
|
||||
```
|
||||
|
||||
If we list the FAT directory again, you will see the file:
|
||||
|
||||
```
|
||||
E>fat dir 4:
|
||||
|
||||
Directory of 4:
|
||||
|
||||
01/30/2023 17:50:14 29952 ---A SAMPLE.TXT
|
||||
|
||||
```
|
||||
|
||||
Now let's copy the file from the FAT filesystem back to CP/M. This
|
||||
time we will get a warning about overwriting the file. For this
|
||||
example, we don't want to do that, so we abort and reissue the
|
||||
command specifying a new filename to use:
|
||||
|
||||
```
|
||||
E>fat copy 4:sample.txt e:
|
||||
|
||||
Copying...
|
||||
|
||||
4:/SAMPLE.TXT ==> E:SAMPLE.TXT Overwrite? (Y/N) [Skipped]
|
||||
|
||||
0 File(s) Copied
|
||||
|
||||
E>fat copy 4:sample.txt e:sample2.txt
|
||||
|
||||
Copying...
|
||||
|
||||
4:/SAMPLE.TXT ==> E:SAMPLE2.TXT ... [OK]
|
||||
|
||||
1 File(s) Copied
|
||||
```
|
||||
|
||||
Finally, let's try using wildcards:
|
||||
|
||||
```
|
||||
E>fat copy sample*.* 4:
|
||||
|
||||
Copying...
|
||||
|
||||
SAMPLE.TXT ==> 4:/SAMPLE.TXT Overwrite? (Y/N) ... [OK]
|
||||
SAMPLE2.TXT ==> 4:/SAMPLE2.TXT ... [OK]
|
||||
|
||||
2 File(s) Copied
|
||||
```
|
||||
|
||||
# Customizing RomWBW
|
||||
|
||||
|
||||
@@ -1,30 +1,50 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; DUODYNE STANDARD CONFIGURATION
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR DUODYNE
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_duo.asm"
|
||||
#include "cfg_DUO.asm"
|
||||
;
|
||||
CPUOSC .SET 8000000 ; CPU OSC FREQ IN MHZ
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
|
||||
@@ -1,30 +1,50 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; DYNO STANDARD CONFIGURATION
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR DYNO
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_dyno.asm"
|
||||
#include "cfg_DYNO.asm"
|
||||
;
|
||||
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
|
||||
@@ -1,32 +1,52 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; Z180 Mini ITX STANDARD CONFIGURATION
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR Z180 MINI ITX
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "Z180 MiniITX"
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_epitx.asm"
|
||||
#include "cfg_EPITX.asm"
|
||||
;
|
||||
CRTACT .SET TRUE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
;
|
||||
|
||||
@@ -1,30 +1,50 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; S100 FPGZ Z80 STANDARD CONFIGURATION
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR S100 FPGA Z80
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_fz80.asm"
|
||||
#include "cfg_FZ80.asm"
|
||||
;
|
||||
CPUOSC .SET 8000000 ; CPU OSC FREQ IN MHZ
|
||||
CRTACT .SET TRUE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
|
||||
@@ -1,32 +1,52 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; STD Z180 STANDARD CONFIGURATION
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR GENESIS STD Z180
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "GM STD BUS Z180", " [", CONFIG, "]"
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_gmz180.asm"
|
||||
#include "cfg_GMZ180.asm"
|
||||
;
|
||||
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
|
||||
@@ -1,28 +1,48 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; HEATH H8 Z80 STANDARD CONFIGURATION
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR HEATH H8 Z80
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_heath.asm"
|
||||
#include "cfg_HEATH.asm"
|
||||
;
|
||||
|
||||
@@ -1,30 +1,50 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; MBC CONFIGURATION
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR NHYODYNE
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_mbc.asm"
|
||||
#include "cfg_MBC.asm"
|
||||
;
|
||||
CPUOSC .SET 8000000 ; CPU OSC FREQ IN MHZ
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
|
||||
@@ -1,30 +1,50 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; MARK IV STANDARD CONFIGURATION
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR MARK IV
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_mk4.asm"
|
||||
#include "cfg_MK4.asm"
|
||||
;
|
||||
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
|
||||
|
||||
@@ -1,30 +1,50 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; MONSPUTER Z80 STANDARD CONFIGURATION
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR MONSPUTER Z80
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_mon.asm"
|
||||
#include "cfg_MON.asm"
|
||||
;
|
||||
CPUOSC .SET 4000000 ; CPU OSC FREQ IN MHZ
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
|
||||
@@ -1,30 +1,50 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; N8 STANDARD CONFIGURATION
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR N8
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_n8.asm"
|
||||
#include "cfg_N8.asm"
|
||||
;
|
||||
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
|
||||
|
||||
@@ -1,30 +1,50 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; NABU Z80 STANDARD CONFIGURATION
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR NABU Z80
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_nabu.asm"
|
||||
#include "cfg_NABU.asm"
|
||||
;
|
||||
CRTACT .SET TRUE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
;
|
||||
|
||||
@@ -1,30 +1,50 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; RCBUS Z180 STANDARD CONFIGURATION (EXTERNAL MMU ON 512K RAM/ROM BANKED MEMORY MODULE)
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z180 W/ EXTERNAL Z2 MMU
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_rcz180.asm"
|
||||
#include "cfg_RCZ180.asm"
|
||||
;
|
||||
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
|
||||
@@ -1,30 +1,50 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; RCBUS Z180 STANDARD CONFIGURATION (NATIVE Z180 MMU W/ LINEAR MEMORY MODULE)
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z180 W/ NATIVE Z180 MMU
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_rcz180.asm"
|
||||
#include "cfg_RCZ180.asm"
|
||||
;
|
||||
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
|
||||
@@ -1,32 +1,52 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; RCBUS Z180 Z1RCC CONFIGURATION (ROMLESS)
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z180 ROMLESS Z1RCC
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "Z1RCC", " [", CONFIG, "]"
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_rcz180.asm"
|
||||
#include "cfg_RCZ180.asm"
|
||||
;
|
||||
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
|
||||
@@ -1,30 +1,50 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; RCBUS Z280 STANDARD CONFIGURATION (EXTERNAL MMU ON 512K RAM/ROM BANKED MEMORY MODULE)
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z280 W/ EXTERNAL Z2 MMU
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_rcz280.asm"
|
||||
#include "cfg_RCZ280.asm"
|
||||
;
|
||||
CPUOSC .SET 24000000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .SET 1 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
|
||||
|
||||
@@ -1,30 +1,50 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; RCBUS Z280 STANDARD CONFIGURATION (NATIVE Z280 MMU W/ LINEAR MEMORY)
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z280 W/ NATIVE Z280 MMU
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_rcz280.asm"
|
||||
#include "cfg_RCZ280.asm"
|
||||
;
|
||||
CPUOSC .SET 24000000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .SET 3 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
|
||||
|
||||
@@ -1,32 +1,52 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; RCBUS Z280 STANDARD CONFIGURATION (NATIVE Z280 MMU W/ LINEAR MEMORY ON ZZ80MB)
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS ZZ80MB Z280 W/ NATIVE Z280 MMU
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "ZZ80MB", " [", CONFIG, "]"
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_rcz280.asm"
|
||||
#include "cfg_RCZ280.asm"
|
||||
;
|
||||
CPUOSC .SET 24000000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .SET 3 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
|
||||
|
||||
@@ -1,32 +1,52 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; RCBUS Z280 ZZRCC CONFIGURATION (ROMLESS)
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z280 ROMLESS ZZRCC W/ NATIVE Z280 MMU
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "ZZRCC", " [", CONFIG, "]"
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_rcz280.asm"
|
||||
#include "cfg_RCZ280.asm"
|
||||
;
|
||||
CPUOSC .SET 29491200 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .SET 3 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
|
||||
|
||||
@@ -1,32 +1,52 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; RCBUS Z280 ZZRCC CONFIGURATION
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z280 ZZRCC W/ NATIVE Z280 MMU
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "ZZRCC", " [", CONFIG, "]"
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_rcz280.asm"
|
||||
#include "cfg_RCZ280.asm"
|
||||
;
|
||||
CPUOSC .SET 29491200 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .SET 3 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
|
||||
|
||||
@@ -1,32 +1,52 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; EASY Z80 STANDARD CONFIGURATION
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR EASY Z80
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "Easy-Z80", " [", CONFIG, "]"
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_rcz80.asm"
|
||||
#include "cfg_RCZ80.asm"
|
||||
;
|
||||
PLATFORM .SET PLT_EZZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
|
||||
CPUOSC .SET 10000000 ; CPU OSC FREQ IN MHZ
|
||||
|
||||
@@ -1,8 +1,49 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; RCBUS Z80 COLECOVISION-COMPATIBLE CONFIGURATION FOR J.B. LANGSTON'S GAME BOARDS
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z80 W/ JBL GAME BOARDS
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
; NOTES:
|
||||
;
|
||||
; THIS CONFIGURATION ENABLES DRIVERS FOR THE TMS9918 AND SN76489 BOARDS BY J.B. LANGSTON
|
||||
; AND THE YM2149 BOARD BY ED BRINDLEY. THE TMS9918 IS CONFIGURED TO USE THE COLECOVISION
|
||||
; PORTS AND HAS INTERRUPTS DISABLED BECAUSE COLECOVISION USES NMI, WHICH WOULD BREAK CP/M
|
||||
@@ -22,16 +63,9 @@
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "Z" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_rcz80.asm"
|
||||
#include "cfg_RCZ80.asm"
|
||||
;
|
||||
CPUOSC .SET 3686400 ; CPU OSC FREQ IN MHZ
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
|
||||
@@ -1,30 +1,50 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; RCBUS Z80 STANDARD CONFIGURATION W/ KIO
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z80 W/ KIO
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_rcz80.asm"
|
||||
#include "cfg_RCZ80.asm"
|
||||
;
|
||||
CPUOSC .SET 7372800 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
|
||||
|
||||
@@ -1,30 +1,50 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; RCBUS Z80 STANDARD CONFIGURATION W/ SERGEY KISELEV Z80 + 512K CPU
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z80 W/ SERGEY KISELEL Z80+512K CPU
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_rcz80.asm"
|
||||
#include "cfg_RCZ80.asm"
|
||||
;
|
||||
CPUOSC .SET 7372800 ; CPU OSC FREQ IN MHZ
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
|
||||
@@ -1,30 +1,50 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; RCBUS Z80 STANDARD CONFIGURATION
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z80
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_rcz80.asm"
|
||||
#include "cfg_RCZ80.asm"
|
||||
;
|
||||
CPUOSC .SET 7372800 ; CPU OSC FREQ IN MHZ
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
|
||||
@@ -1,32 +1,52 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; TINY Z80 STANDARD CONFIGURATION
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR TINY Z80
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "Tiny-Z80", " [", CONFIG, "]"
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_rcz80.asm"
|
||||
#include "cfg_RCZ80.asm"
|
||||
;
|
||||
PLATFORM .SET PLT_EZZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
|
||||
CPUOSC .SET 16000000 ; CPU OSC FREQ IN MHZ
|
||||
|
||||
57
Source/HBIOS/Config/RCZ80_user.asm
Normal file
57
Source/HBIOS/Config/RCZ80_user.asm
Normal file
@@ -0,0 +1,57 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW CUSTOM USER BUILD SETTINGS EXAMPLE FOR RCBUS Z80
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE IS AN EXAMPLE OF A CUSTOM USER SETTINGS FILE. THESE
|
||||
; SETTINGS OVERRIDE THE DEFAULT SETTINGS OF THE INHERITED FILES AS
|
||||
; DESIRED BY A USER.
|
||||
;
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; THIS FILE EXEMPLIFIES THE IDEAL WAY TO CREATE A USER SPECIFIC BUILD
|
||||
; CONFIGURATION. NOTICE THAT IT INCLUDES THE DEFAULT BUILD SETTINGS
|
||||
; FILE AND OVERRIDES SOME DESIRED SETTINGS.
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
; THIS EXAMPLE CUSTOM USER SETTINGS FILE DOES THE FOLLOWING:
|
||||
;
|
||||
; 1. SETS A CUSTOM NAME USED IN THE BOOT LOADER BANNER
|
||||
; 2. BOOTS ZSDOS BY DEFAULT AFTER 10 SECOND DELAY
|
||||
; 3. ENABLES LPT PRINTER SUPPORT
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "My Custom RCBus Computer", " [", CONFIG, "]"
|
||||
#DEFINE BOOT_DEFAULT "Z" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "Config/RCZ80_std.asm" ; INHERIT FROM OFFICIAL BUILD SETTINGS
|
||||
;
|
||||
BOOT_TIMEOUT .SET 10 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
;
|
||||
LPTENABLE .SET TRUE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
@@ -1,32 +1,52 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; RCBUS Z80 ZRC512 CONFIGURATION
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z80 ZRC512
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "ZRC512", " [", CONFIG, "]"
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_rcz80.asm"
|
||||
#include "cfg_RCZ80.asm"
|
||||
;
|
||||
CPUOSC .SET 22000000 ; CPU OSC FREQ IN MHZ
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
|
||||
@@ -1,32 +1,52 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; RCBUS Z80 ZRC CONFIGURATION
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z80 ROMLESS ZRC
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "ZRC", " [", CONFIG, "]"
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_rcz80.asm"
|
||||
#include "cfg_RCZ80.asm"
|
||||
;
|
||||
CPUOSC .SET 14745600 ; CPU OSC FREQ IN MHZ
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
|
||||
@@ -1,32 +1,52 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; RCBUS Z80 ZRC CONFIGURATION
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z80 ZRC
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "ZRC", " [", CONFIG, "]"
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_rcz80.asm"
|
||||
#include "cfg_RCZ80.asm"
|
||||
;
|
||||
CPUOSC .SET 14745600 ; CPU OSC FREQ IN MHZ
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
|
||||
@@ -1,30 +1,50 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; RHYOPHYRE STANDARD CONFIGURATION
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR RHYOPHYRE
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_rph.asm"
|
||||
#include "cfg_RPH.asm"
|
||||
;
|
||||
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
|
||||
@@ -1,30 +1,50 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; S100 STANDARD CONFIGURATION
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR S100
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_s100.asm"
|
||||
#include "cfg_S100.asm"
|
||||
;
|
||||
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ
|
||||
CRTACT .SET TRUE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
|
||||
@@ -27,7 +27,7 @@
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_sbc.asm"
|
||||
#include "cfg_SBC.asm"
|
||||
;
|
||||
BATCOND .SET TRUE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .SET TRUE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
|
||||
@@ -24,7 +24,7 @@
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_sbc.asm"
|
||||
#include "cfg_SBC.asm"
|
||||
;
|
||||
INTMODE .SET 1 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
|
||||
;
|
||||
|
||||
@@ -1,30 +1,50 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; SBC STANDARD CONFIGURATION
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR N8VEM SBC
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_sbc.asm"
|
||||
#include "cfg_SBC.asm"
|
||||
;
|
||||
CPUOSC .SET 8000000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .SET 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
|
||||
|
||||
@@ -1,32 +1,52 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; SC126 STANDARD CONFIGURATION
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR SC126
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "Small Computer SC126", " [", CONFIG, "]"
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_scz180.asm"
|
||||
#include "cfg_SCZ180.asm"
|
||||
;
|
||||
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
|
||||
@@ -1,32 +1,52 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; SC130 STANDARD CONFIGURATION
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR SC130
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "Small Computer SC130", " [", CONFIG, "]"
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_scz180.asm"
|
||||
#include "cfg_SCZ180.asm"
|
||||
;
|
||||
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
|
||||
@@ -1,32 +1,52 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; SC131 STANDARD CONFIGURATION
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR SC131
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "Small Computer SC131", " [", CONFIG, "]"
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_scz180.asm"
|
||||
#include "cfg_SCZ180.asm"
|
||||
;
|
||||
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ
|
||||
;
|
||||
|
||||
@@ -1,32 +1,52 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; SC140 STANDARD CONFIGURATION
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR PLATFORM: SBC
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "Small Computer SC140", " [", CONFIG, "]"
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_scz180.asm"
|
||||
#include "cfg_SCZ180.asm"
|
||||
;
|
||||
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ
|
||||
;
|
||||
|
||||
@@ -1,32 +1,52 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; SC503 STANDARD CONFIGURATION
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR SC503
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "Small Computer SC503", " [", CONFIG, "]"
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_scz180.asm"
|
||||
#include "cfg_SCZ180.asm"
|
||||
;
|
||||
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ
|
||||
;
|
||||
|
||||
@@ -1,32 +1,52 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; SC700 STANDARD CONFIGURATION
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR SC700
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "Small Computer SC700", " [", CONFIG, "]"
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_scz180.asm"
|
||||
#include "cfg_SCZ180.asm"
|
||||
;
|
||||
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
|
||||
@@ -1,27 +1,47 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; UNA STANDARD CONFIGURATION
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR UNA
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_una.asm"
|
||||
#include "cfg_UNA.asm"
|
||||
|
||||
@@ -1,30 +1,50 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ZETA2 STANDARD CONFIGURATION
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR Z80 RETRO
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_z80retro.asm"
|
||||
#include "cfg_Z80RETRO.asm"
|
||||
;
|
||||
CPUOSC .SET 14745600 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
|
||||
|
||||
@@ -1,30 +1,50 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ZETA2 STANDARD CONFIGURATION
|
||||
; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: ZETA 2
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_zeta2.asm"
|
||||
#include "cfg_ZETA2.asm"
|
||||
;
|
||||
CPUOSC .SET 8000000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
|
||||
|
||||
@@ -1,30 +1,50 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ZETA STANDARD CONFIGURATION
|
||||
; ROMWBW DEFAULT BUILD SETTINGS FOR ZETA
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
|
||||
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED.
|
||||
;
|
||||
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
|
||||
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_zeta.asm"
|
||||
#include "cfg_ZETA.asm"
|
||||
;
|
||||
CPUOSC .SET 8000000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .SET 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
|
||||
|
||||
381
Source/HBIOS/cfg_DUO.asm
Normal file
381
Source/HBIOS/cfg_DUO.asm
Normal file
@@ -0,0 +1,381 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: DUO
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD,
|
||||
; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
|
||||
; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE
|
||||
; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A
|
||||
; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "Duodyne", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "cfg_MASTER.asm"
|
||||
;
|
||||
PLATFORM .SET PLT_DUO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .SET FALSE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .SET SPD_UNSUP ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .SET 8000000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .SET SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .SET MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
MPGSEL_0 .SET $50 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_1 .SET $51 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_2 .SET $52 ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_3 .SET $53 ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGENA .SET $54 ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
|
||||
;
|
||||
RTCIO .SET $94 ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .SET $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .SET TRUE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .SET $60 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .SET TRUE ; ENABLE CTC PERIODIC TIMER
|
||||
CTCMODE .SET CTCMODE_CTR ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
|
||||
CTCPRE .SET 256 ; PRESCALE CONSTANT (1-256)
|
||||
CTCPRECH .SET 2 ; PRESCALE CHANNEL (0-3)
|
||||
CTCTIMCH .SET 3 ; TIMER CHANNEL (0-3)
|
||||
CTCOSC .SET (7372800/8) ; CTC CLOCK FREQUENCY
|
||||
;
|
||||
PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .SET $56 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
;
|
||||
WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
;
|
||||
FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .SET $42 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .SET $42 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .SET TRUE ; ENABLES STATUS LED
|
||||
LEDMODE .SET LEDMODE_RTC ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .SET RTCIO ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .SET $88 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .SET TRUE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .SET $88 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .SET 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .SET $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .SET $FF ; SSER: STATUS PORT
|
||||
SSERDATA .SET $FF ; SSER: DATA PORT
|
||||
SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
;
|
||||
UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .SET 4 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .SET 7372800 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .SET $58 ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .SET $A8 ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .SET SER_300_8N1 ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .SET $70 ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .SET $78 ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .SET FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
;
|
||||
Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
;
|
||||
SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .SET 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
SIO0MODE .SET SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .SET $60 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .SET (7372800/4) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .SET DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .SET 0 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .SET (7372800/4) ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .SET 1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
VDUSIZ .SET V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
|
||||
CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
CVDUMODE .SET CVDUMODE_MBC ; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
|
||||
CVDUMON .SET CVDUMON_CGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
|
||||
GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .SET TRUE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .SET TMSMODE_DUO ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .SET TRUE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VGASIZ .SET V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
|
||||
VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .SET TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .SET TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
;
|
||||
FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .SET FDMODE_DUO ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
RFCNT .SET 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
|
||||
;
|
||||
IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .SET IDEMODE_DIO ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .SET $20 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .SET $20 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .SET $28 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .SET FALSE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .SET FALSE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .SET $88 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .SET $20 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .SET $14 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .SET SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .SET TRUE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
CHTRACE .SET 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHUSBTRACE .SET 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHSDTRACE .SET 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHCNT .SET 1 ; CH: NUMBER OF BOARDS TO DETECT (1-2)
|
||||
CH0BASE .SET $4E ; CH 0: BASE I/O ADDRESS
|
||||
CH0USBENABLE .SET TRUE ; CH 0: ENABLE USB DISK
|
||||
CH0SDENABLE .SET TRUE ; CH 0: ENABLE SD DISK
|
||||
CH1BASE .SET $FF ; CH 1: BASE I/O ADDRESS
|
||||
CH1USBENABLE .SET FALSE ; CH 1: ENABLE USB DISK
|
||||
CH1SDENABLE .SET FALSE ; CH 1: ENABLE SD DISK
|
||||
;
|
||||
PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
ESPCONENABLE .SET TRUE ; ESP: ENABLE ESP32 CONSOLE IO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
HDSKTRACE .SET 1 ; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
;
|
||||
PIOENABLE .SET TRUE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .SET $68 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .SET $6C ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .SET TRUE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
LPTMODE .SET LPTMODE_SPP ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
|
||||
LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
LPT0BASE .SET $48 ; LPT 0: REGISTERS BASE ADR
|
||||
LPT1BASE .SET $EC ; LPT 1: REGISTERS BASE ADR
|
||||
;
|
||||
PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
PPACNT .SET 1 ; PPA: NUMBER OF PPA DEVICES (1-2)
|
||||
PPATRACE .SET 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPAMODE .SET PPAMODE_SPP ; PPA: DRIVER MODE: PPAMODE_[NONE|MG014]
|
||||
PPA0BASE .SET LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
PPA1BASE .SET LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
;
|
||||
IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
IMMCNT .SET 1 ; IMM: NUMBER OF IMM DEVICES (1-2)
|
||||
IMMTRACE .SET 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IMMMODE .SET IMMMODE_SPP ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
|
||||
IMM0BASE .SET LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
IMM1BASE .SET LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
;
|
||||
SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
SYQCNT .SET 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2)
|
||||
SYQTRACE .SET 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SYQMODE .SET IMMMODE_SPP ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
|
||||
SYQ0BASE .SET LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
SYQ1BASE .SET LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
;
|
||||
PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO4BASE .SET $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
|
||||
PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIOZBASE .SET $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
|
||||
PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
PIOSBASE .SET $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
|
||||
;
|
||||
UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
UFBASE .SET $0C ; UF: REGISTERS BASE ADR
|
||||
;
|
||||
SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .SET SNMODE_DUO ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
|
||||
;
|
||||
AY38910ENABLE .SET TRUE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .SET AYMODE_DUO ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
||||
;
|
||||
SPKENABLE .SET TRUE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .SET TRUE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .SET $40 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .SET DMAMODE_DUO ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
361
Source/HBIOS/cfg_DYNO.asm
Normal file
361
Source/HBIOS/cfg_DYNO.asm
Normal file
@@ -0,0 +1,361 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: DYNO
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD,
|
||||
; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
|
||||
; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE
|
||||
; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A
|
||||
; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "Dyno", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "cfg_MASTER.asm"
|
||||
;
|
||||
PLATFORM .SET PLT_DYNO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .SET SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .SET MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
RAMBIAS .SET ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
|
||||
MPGSEL_0 .SET $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_1 .SET $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_2 .SET $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_3 .SET $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGENA .SET $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
|
||||
;
|
||||
Z180_BASE .SET $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
|
||||
Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
|
||||
Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3)
|
||||
Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
|
||||
Z180_TIMER .SET TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
|
||||
;
|
||||
RTCIO .SET $0C ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .SET $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .SET $88 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER
|
||||
;
|
||||
PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
;
|
||||
WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
;
|
||||
FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED)
|
||||
LEDMODE .SET LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .SET $0E ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .SET 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .SET $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .SET TRUE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .SET $FF ; SSER: STATUS PORT
|
||||
SSERDATA .SET $FF ; SSER: DATA PORT
|
||||
SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
DUARTCNT .SET 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
DUART0BASE .SET $A0 ; DUART 0: BASE ADDRESS OF CHIP
|
||||
DUART0ACFG .SET DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG
|
||||
DUART0BCFG .SET DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG
|
||||
DUART1BASE .SET $40 ; DUART 1: BASE ADDRESS OF CHIP
|
||||
DUART1ACFG .SET DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
|
||||
DUART1BCFG .SET DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
|
||||
;
|
||||
UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .SET 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .SET $FF ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .SET $FF ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .SET $FF ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .SET $FF ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
ASCIINTS .SET TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
ASCISWAP .SET FALSE ; ASCI: SWAP CHANNELS
|
||||
ASCIBOOT .SET 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
ASCI0CFG .SET DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG
|
||||
ASCI1CFG .SET DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG
|
||||
;
|
||||
Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
;
|
||||
SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .SET 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
SIO0MODE .SET SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .SET 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .SET SER_115200_8N1 ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .SET 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .SET SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1MODE .SET SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO1BASE .SET $84 ; SIO 1: REGISTERS BASE ADR
|
||||
SIO1ACLK .SET 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1ACFG .SET SER_115200_8N1 ; SIO 1A: SERIAL LINE CONFIG
|
||||
SIO1ACTCC .SET -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1BCLK .SET 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1BCFG .SET SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG
|
||||
SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .SET TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .SET TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .SET FDMODE_DYNO ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
;
|
||||
IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .SET IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .SET $10 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .SET $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .SET $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .SET TRUE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .SET TRUE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .SET $4C ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .SET SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
;
|
||||
PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
;
|
||||
PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
;
|
||||
IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
;
|
||||
SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
;
|
||||
PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
;
|
||||
UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
;
|
||||
SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .SET SNMODE_NONE ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
||||
;
|
||||
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .SET AYMODE_NONE ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
||||
;
|
||||
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .SET DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
387
Source/HBIOS/cfg_EPITX.asm
Normal file
387
Source/HBIOS/cfg_EPITX.asm
Normal file
@@ -0,0 +1,387 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: EPITX
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD,
|
||||
; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
|
||||
; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE
|
||||
; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A
|
||||
; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "MiniITX"
|
||||
;
|
||||
#INCLUDE "cfg_MASTER.asm"
|
||||
;
|
||||
PLATFORM .SET PLT_EPITX ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .SET SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .SET MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
RAMBIAS .SET ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
|
||||
;
|
||||
Z180_BASE .SET $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
|
||||
Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
|
||||
Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3)
|
||||
Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
|
||||
Z180_TIMER .SET TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
|
||||
;
|
||||
RTCIO .SET $0C ; RTC LATCH REGISTER ADR - TODO
|
||||
;
|
||||
KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .SET $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .SET $88 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER
|
||||
;
|
||||
PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
;
|
||||
WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
;
|
||||
FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .SET FALSE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED)
|
||||
LEDMODE .SET LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .SET $0E ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .SET 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .SET $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
; TODO - ADD PS/2 BITBANGER
|
||||
VDAEMU_SERKBD .SET $00 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .SET $FF ; SSER: STATUS PORT
|
||||
SSERDATA .SET $FF ; SSER: DATA PORT
|
||||
SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
DUARTCNT .SET 2 ; DUART: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
DUART0BASE .SET $A0 ; DUART 0: BASE ADDRESS OF CHIP
|
||||
DUART0ACFG .SET DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG
|
||||
DUART0BCFG .SET DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG
|
||||
DUART1BASE .SET $40 ; DUART 1: BASE ADDRESS OF CHIP
|
||||
DUART1ACFG .SET DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
|
||||
DUART1BCFG .SET DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
|
||||
;
|
||||
UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .SET 2 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .SET $A0 ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .SET $A8 ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .SET $FF ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .SET $FF ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
ASCIINTS .SET TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
ASCISWAP .SET FALSE ; ASCI: SWAP CHANNELS
|
||||
ASCIBOOT .SET 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
ASCI0CFG .SET DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG
|
||||
ASCI1CFG .SET DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG
|
||||
;
|
||||
Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
;
|
||||
SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .SET 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
SIO0MODE .SET SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .SET 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .SET SER_115200_8N1 ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .SET 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .SET SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1MODE .SET SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO1BASE .SET $84 ; SIO 1: REGISTERS BASE ADR
|
||||
SIO1ACLK .SET 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1ACFG .SET SER_115200_8N1 ; SIO 1A: SERIAL LINE CONFIG
|
||||
SIO1ACTCC .SET -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1BCLK .SET 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1BCFG .SET SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG
|
||||
SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .SET TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .SET TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .SET FDMODE_EPFDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
;
|
||||
IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .SET IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .SET $10 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .SET $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .SET $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .SET TRUE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .SET TRUE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .SET $20 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .SET SDMODE_EPITX ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .SET $40 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
|
||||
SDTRACE .SET 2 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
CHTRACE .SET 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHUSBTRACE .SET 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHSDTRACE .SET 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHCNT .SET 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2)
|
||||
CH0BASE .SET $3E ; CH 0: BASE I/O ADDRESS
|
||||
CH0USBENABLE .SET TRUE ; CH 0: ENABLE USB DISK
|
||||
CH0SDENABLE .SET FALSE ; CH 0: ENABLE SD DISK
|
||||
CH1BASE .SET $3C ; CH 1: BASE I/O ADDRESS
|
||||
CH1USBENABLE .SET TRUE ; CH 1: ENABLE USB DISK
|
||||
CH1SDENABLE .SET FALSE ; CH 1: ENABLE SD DISK
|
||||
;
|
||||
PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
|
||||
LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
LPT0BASE .SET $0C ; LPT 0: REGISTERS BASE ADR
|
||||
LPT1BASE .SET $00 ; LPT 1: REGISTERS BASE ADR
|
||||
;
|
||||
PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
PPACNT .SET 1 ; PPA: NUMBER OF PPA DEVICES (1-2)
|
||||
PPATRACE .SET 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPAMODE .SET PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
|
||||
PPA0BASE .SET LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
PPA1BASE .SET LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
;
|
||||
IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
IMMCNT .SET 1 ; IMM: NUMBER OF IMM DEVICES (1-2)
|
||||
IMMTRACE .SET 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IMMMODE .SET IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
|
||||
IMM0BASE .SET LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
IMM1BASE .SET LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
;
|
||||
SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
SYQCNT .SET 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2)
|
||||
SYQTRACE .SET 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SYQMODE .SET IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
|
||||
SYQ0BASE .SET LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
SYQ1BASE .SET LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
;
|
||||
PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
;
|
||||
UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
;
|
||||
SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
||||
;
|
||||
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .SET AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
||||
;
|
||||
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .SET DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
396
Source/HBIOS/cfg_FZ80.asm
Normal file
396
Source/HBIOS/cfg_FZ80.asm
Normal file
@@ -0,0 +1,396 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: FZ80
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD,
|
||||
; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
|
||||
; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE
|
||||
; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A
|
||||
; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "S100 FPGA Z80", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "cfg_MASTER.asm"
|
||||
;
|
||||
PLATFORM .SET PLT_FZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .SET 8000000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .SET 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .SET SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .SET 0 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .SET MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
MPGSEL_0 .SET $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_1 .SET $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_2 .SET $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_3 .SET $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGENA .SET $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
|
||||
;
|
||||
RTCIO .SET $C0 ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .SET $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .SET $88 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER
|
||||
CTCMODE .SET CTCMODE_TIM16 ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
|
||||
CTCPRE .SET 256 ; PRESCALE CONSTANT (1-256)
|
||||
CTCPRECH .SET 2 ; PRESCALE CHANNEL (0-3)
|
||||
CTCTIMCH .SET 3 ; TIMER CHANNEL (0-3)
|
||||
CTCOSC .SET CPUOSC ; CTC CLOCK FREQUENCY
|
||||
;
|
||||
PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
SKZDIV .SET DIV_1 ; UART CLK (CLK2) DIVIDER FOR Z80-512K
|
||||
;
|
||||
WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
WDOGIO .SET $6E ; WATCHDOG REGISTER ADR
|
||||
;
|
||||
FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .SET $FF ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED)
|
||||
LEDMODE .SET LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .SET $0E ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .SET 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .SET $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .SET TRUE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .SET TRUE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .SET $34 ; SSER: STATUS PORT
|
||||
SSERDATA .SET $35 ; SSER: DATA PORT
|
||||
SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .SET TRUE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
DUARTCNT .SET 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
DUART0BASE .SET $A0 ; DUART 0: BASE ADDRESS OF CHIP
|
||||
DUART0ACFG .SET DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG
|
||||
DUART0BCFG .SET DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG
|
||||
DUART1BASE .SET $40 ; DUART 1: BASE ADDRESS OF CHIP
|
||||
DUART1ACFG .SET DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
|
||||
DUART1BCFG .SET DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
|
||||
;
|
||||
UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .SET 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .SET $FF ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .SET $FF ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .SET $FF ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .SET $FF ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .SET FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
;
|
||||
Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
ACIADEBUG .SET FALSE ; ACIA: ENABLE DEBUG OUTPUT
|
||||
ACIACNT .SET 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
ACIA0BASE .SET $80 ; ACIA 0: REGISTERS BASE ADR
|
||||
ACIA0CLK .SET CPUOSC ; ACIA 0: OSC FREQ IN HZ
|
||||
ACIA0DIV .SET 1 ; ACIA 0: SERIAL CLOCK DIVIDER
|
||||
ACIA0CFG .SET DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
ACIA1BASE .SET $40 ; ACIA 1: REGISTERS BASE ADR
|
||||
ACIA1CLK .SET CPUOSC ; ACIA 1: OSC FREQ IN HZ
|
||||
ACIA1DIV .SET 1 ; ACIA 1: SERIAL CLOCK DIVIDER
|
||||
ACIA1CFG .SET DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .SET 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
SIO0MODE .SET SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .SET CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .SET DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .SET CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1MODE .SET SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO1BASE .SET $84 ; SIO 1: REGISTERS BASE ADR
|
||||
SIO1ACLK .SET CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1ACFG .SET DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG
|
||||
SIO1ACTCC .SET -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1BCLK .SET CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1BCFG .SET DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG
|
||||
SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .SET TRUE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .SET TRUE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .SET FALSE ; MD: ENABLE ROM DISK
|
||||
MDRAM .SET TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
;
|
||||
IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .SET IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .SET $10 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .SET $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .SET $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .SET TRUE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .SET TRUE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .SET $30 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .SET SDMODE_FZ80 ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .SET 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
CHTRACE .SET 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHUSBTRACE .SET 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHSDTRACE .SET 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHCNT .SET 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2)
|
||||
CH0BASE .SET $3E ; CH 0: BASE I/O ADDRESS
|
||||
CH0USBENABLE .SET TRUE ; CH 0: ENABLE USB DISK
|
||||
CH0SDENABLE .SET FALSE ; CH 0: ENABLE SD DISK
|
||||
CH1BASE .SET $3C ; CH 1: BASE I/O ADDRESS
|
||||
CH1USBENABLE .SET TRUE ; CH 1: ENABLE USB DISK
|
||||
CH1SDENABLE .SET FALSE ; CH 1: ENABLE SD DISK
|
||||
;
|
||||
PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
|
||||
LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
LPT0BASE .SET $0C ; LPT 0: REGISTERS BASE ADR
|
||||
LPT1BASE .SET $00 ; LPT 1: REGISTERS BASE ADR
|
||||
;
|
||||
PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
PPACNT .SET 1 ; PPA: NUMBER OF PPA DEVICES (1-2)
|
||||
PPATRACE .SET 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPAMODE .SET PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
|
||||
PPA0BASE .SET LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
PPA1BASE .SET LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
;
|
||||
IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
IMMCNT .SET 1 ; IMM: NUMBER OF IMM DEVICES (1-2)
|
||||
IMMTRACE .SET 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IMMMODE .SET IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
|
||||
IMM0BASE .SET LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
IMM1BASE .SET LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
;
|
||||
SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
SYQCNT .SET 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2)
|
||||
SYQTRACE .SET 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SYQMODE .SET IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
|
||||
SYQ0BASE .SET LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
SYQ1BASE .SET LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
;
|
||||
PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
;
|
||||
UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
;
|
||||
SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
||||
;
|
||||
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
||||
;
|
||||
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .SET DMAMODE_RC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
393
Source/HBIOS/cfg_GMZ180.asm
Normal file
393
Source/HBIOS/cfg_GMZ180.asm
Normal file
@@ -0,0 +1,393 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: GMZ180
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD,
|
||||
; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
|
||||
; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE
|
||||
; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A
|
||||
; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "GM STD BUS Z180", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "cfg_MASTER.asm"
|
||||
;
|
||||
PLATFORM .SET PLT_GMZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
|
||||
CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .SET SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .SET MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
RAMBIAS .SET ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
|
||||
MPGSEL_0 .SET $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_1 .SET $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_2 .SET $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_3 .SET $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGENA .SET $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
|
||||
;
|
||||
Z180_BASE .SET $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
|
||||
Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
|
||||
Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3)
|
||||
Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
|
||||
Z180_TIMER .SET TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
|
||||
;
|
||||
RTCIO .SET $84 ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .SET $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .SET $88 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER
|
||||
;
|
||||
PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
;
|
||||
WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
;
|
||||
FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .SET FALSE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED)
|
||||
LEDMODE .SET LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .SET $0E ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .SET FALSE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .SET TRUE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
GM7303BASE .SET $30 ; BASE ADDRESS FOR GM3703 BOARD
|
||||
GM7303DSKACT .SET TRUE ; ENABLE DISK ACTIVITY OF GM7303 LCD DISPLAY
|
||||
;
|
||||
BOOTCON .SET 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .SET $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .SET TRUE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .SET $FF ; SSER: STATUS PORT
|
||||
SSERDATA .SET $FF ; SSER: DATA PORT
|
||||
SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
DUARTCNT .SET 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
DUART0BASE .SET $A0 ; DUART 0: BASE ADDRESS OF CHIP
|
||||
DUART0ACFG .SET DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG
|
||||
DUART0BCFG .SET DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG
|
||||
DUART1BASE .SET $40 ; DUART 1: BASE ADDRESS OF CHIP
|
||||
DUART1ACFG .SET DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
|
||||
DUART1BCFG .SET DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
|
||||
;
|
||||
UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .SET 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .SET $80 ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .SET $88 ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .SET $A0 ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .SET $A8 ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
ASCIINTS .SET TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
ASCISWAP .SET FALSE ; ASCI: SWAP CHANNELS
|
||||
ASCIBOOT .SET 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
ASCI0CFG .SET DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG
|
||||
ASCI1CFG .SET DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG
|
||||
;
|
||||
Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
;
|
||||
SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .SET 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
SIO0MODE .SET SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .SET 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .SET SER_115200_8N1 ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .SET 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .SET SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1MODE .SET SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO1BASE .SET $84 ; SIO 1: REGISTERS BASE ADR
|
||||
SIO1ACLK .SET 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1ACFG .SET SER_115200_8N1 ; SIO 1A: SERIAL LINE CONFIG
|
||||
SIO1ACTCC .SET -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1BCLK .SET 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1BCFG .SET SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG
|
||||
SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .SET TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .SET TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
;
|
||||
IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .SET IDEMODE_GIDE ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
|
||||
IDE0BASE .SET $20 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .SET $20 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .SET $28 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .SET TRUE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .SET TRUE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
|
||||
IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
|
||||
IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .SET $20 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .SET SDMODE_GM ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM]
|
||||
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
CHTRACE .SET 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHUSBTRACE .SET 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHSDTRACE .SET 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHCNT .SET 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2)
|
||||
CH0BASE .SET $3E ; CH 0: BASE I/O ADDRESS
|
||||
CH0USBENABLE .SET TRUE ; CH 0: ENABLE USB DISK
|
||||
CH0SDENABLE .SET FALSE ; CH 0: ENABLE SD DISK
|
||||
CH1BASE .SET $3C ; CH 1: BASE I/O ADDRESS
|
||||
CH1USBENABLE .SET TRUE ; CH 1: ENABLE USB DISK
|
||||
CH1SDENABLE .SET FALSE ; CH 1: ENABLE SD DISK
|
||||
;
|
||||
PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
|
||||
LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
LPT0BASE .SET $18 ; LPT 0: REGISTERS BASE ADR
|
||||
LPT1BASE .SET $00 ; LPT 1: REGISTERS BASE ADR
|
||||
;
|
||||
PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
PPACNT .SET 1 ; PPA: NUMBER OF PPA DEVICES (1-2)
|
||||
PPATRACE .SET 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPAMODE .SET PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
|
||||
PPA0BASE .SET LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
PPA1BASE .SET LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
;
|
||||
IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
IMMCNT .SET 1 ; IMM: NUMBER OF IMM DEVICES (1-2)
|
||||
IMMTRACE .SET 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IMMMODE .SET IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
|
||||
IMM0BASE .SET LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
IMM1BASE .SET LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
;
|
||||
SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
SYQCNT .SET 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2)
|
||||
SYQTRACE .SET 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SYQMODE .SET IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
|
||||
SYQ0BASE .SET LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
SYQ1BASE .SET LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
;
|
||||
PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
;
|
||||
UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
;
|
||||
SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
||||
;
|
||||
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .SET AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
||||
;
|
||||
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .SET DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
386
Source/HBIOS/cfg_HEATH.asm
Normal file
386
Source/HBIOS/cfg_HEATH.asm
Normal file
@@ -0,0 +1,386 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: HEATH
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD,
|
||||
; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
|
||||
; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE
|
||||
; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A
|
||||
; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "HEATHKIT", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "cfg_MASTER.asm"
|
||||
;
|
||||
PLATFORM .SET PLT_HEATH ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .SET 16384000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .SET 1 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .SET SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .SET MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
MPGSEL_0 .SET $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_1 .SET $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_2 .SET $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_3 .SET $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGENA .SET $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
|
||||
;
|
||||
RTCIO .SET $C0 ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .SET $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .SET $88 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER
|
||||
CTCMODE .SET CTCMODE_TIM16 ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
|
||||
CTCPRE .SET 256 ; PRESCALE CONSTANT (1-256)
|
||||
CTCPRECH .SET 2 ; PRESCALE CHANNEL (0-3)
|
||||
CTCTIMCH .SET 3 ; TIMER CHANNEL (0-3)
|
||||
CTCOSC .SET CPUOSC ; CTC CLOCK FREQUENCY
|
||||
;
|
||||
PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
SKZDIV .SET DIV_1 ; UART CLK (CLK2) DIVIDER FOR Z80-512K
|
||||
;
|
||||
WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
WDOGIO .SET $6E ; WATCHDOG REGISTER ADR
|
||||
;
|
||||
FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .SET FALSE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED)
|
||||
LEDMODE .SET LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .SET $0E ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .SET FALSE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .SET TRUE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .SET 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .SET $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .SET $FF ; SSER: STATUS PORT
|
||||
SSERDATA .SET $FF ; SSER: DATA PORT
|
||||
SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
DUARTCNT .SET 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
DUART0BASE .SET $A0 ; DUART 0: BASE ADDRESS OF CHIP
|
||||
DUART0ACFG .SET DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG
|
||||
DUART0BCFG .SET DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG
|
||||
DUART1BASE .SET $40 ; DUART 1: BASE ADDRESS OF CHIP
|
||||
DUART1ACFG .SET DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
|
||||
DUART1BCFG .SET DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
|
||||
;
|
||||
UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .SET 4 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .SET $E8 ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .SET $E0 ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .SET $D8 ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .SET $D0 ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .SET FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
;
|
||||
Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
ACIADEBUG .SET FALSE ; ACIA: ENABLE DEBUG OUTPUT
|
||||
ACIACNT .SET 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
ACIA0BASE .SET $80 ; ACIA 0: REGISTERS BASE ADR
|
||||
ACIA0CLK .SET CPUOSC ; ACIA 0: OSC FREQ IN HZ
|
||||
ACIA0DIV .SET 1 ; ACIA 0: SERIAL CLOCK DIVIDER
|
||||
ACIA0CFG .SET DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
ACIA1BASE .SET $40 ; ACIA 1: REGISTERS BASE ADR
|
||||
ACIA1CLK .SET CPUOSC ; ACIA 1: OSC FREQ IN HZ
|
||||
ACIA1DIV .SET 1 ; ACIA 1: SERIAL CLOCK DIVIDER
|
||||
ACIA1CFG .SET DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .SET 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
SIO0MODE .SET SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .SET CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .SET DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .SET CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1MODE .SET SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO1BASE .SET $84 ; SIO 1: REGISTERS BASE ADR
|
||||
SIO1ACLK .SET CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1ACFG .SET DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG
|
||||
SIO1ACTCC .SET -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1BCLK .SET CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1BCFG .SET DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG
|
||||
SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .SET TRUE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .SET TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .SET TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
;
|
||||
IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .SET IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .SET $10 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .SET $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .SET $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .SET TRUE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .SET TRUE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .SET $20 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .SET SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .SET 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
;
|
||||
PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
|
||||
LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
LPT0BASE .SET $0C ; LPT 0: REGISTERS BASE ADR
|
||||
LPT1BASE .SET $00 ; LPT 1: REGISTERS BASE ADR
|
||||
;
|
||||
PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
PPACNT .SET 1 ; PPA: NUMBER OF PPA DEVICES (1-2)
|
||||
PPATRACE .SET 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPAMODE .SET PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
|
||||
PPA0BASE .SET LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
PPA1BASE .SET LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
;
|
||||
IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
IMMCNT .SET 1 ; IMM: NUMBER OF IMM DEVICES (1-2)
|
||||
IMMTRACE .SET 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IMMMODE .SET IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
|
||||
IMM0BASE .SET LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
IMM1BASE .SET LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
;
|
||||
SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
SYQCNT .SET 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2)
|
||||
SYQTRACE .SET 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SYQMODE .SET IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
|
||||
SYQ0BASE .SET LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
SYQ1BASE .SET LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
;
|
||||
PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
;
|
||||
UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
;
|
||||
SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
||||
;
|
||||
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .SET AYMODE_MSX ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
||||
;
|
||||
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .SET DMAMODE_RC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
@@ -1,12 +1,46 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW 3.X CONFIGURATION MASTER
|
||||
; ROMWBW GLOBAL MASTER CONFIGURATION FILE
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE IS *NOT* A REAL CONFIGURATION FILE. IT IS A MASTER TEMPLATE FILE
|
||||
; CONTAINING ALL POSSIBLE CONFIGURATION SETTINGS ACROSS ALL PLATFORMS. IT IS
|
||||
; USED ONLY AS A REFERENCE TO HELP MANAGE THE FULL SET OF POSSIBLE SETTINGS AND
|
||||
; KEEP THINGS CONSISTENT.
|
||||
; THIS FILE IS THE GLOBAL MASTER CONFIGURATION FILE FOR THE ROMWBW
|
||||
; BUILD PROCESS. IT DEFINES ALL POSSIBLE CONFIGURATION SETTINGS
|
||||
; AVAILABLE WITHIN ROMWBW. MANY SETTINGS WILL NOT BE APPLICABLE TO
|
||||
; ALL OF THE DIFFERENT ROMWBW PLATFORMS.
|
||||
;
|
||||
; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE
|
||||
; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A
|
||||
; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; EACH FILE BELOW THIS TOP MASTER CONFIGURATION FILE INHERITS THE
|
||||
; CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY OVERRIDE THESE
|
||||
; SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THIS TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE. THE TOP TWO FILES SHOULD NOT BE MODIFIED. TO CUSTOMIZE YOUR
|
||||
; BUILD SETTINGS, YOU SHOULD MODIFY THE DEFAULT BUILD SETTINGS
|
||||
; (Config/<platform>_std.asm) OR PREFERABLY CREATE AN OPTIONAL CUSTOM
|
||||
; USER SETTINGS FILE THAT INCLUDES THE DEFAULT BUILD SETTINGS FILE (SEE
|
||||
; EXAMPLE Config/SBC_custom.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; *** NOTE: THIS FILE USES ".EQU" TO DEFINE ALL SETTINGS. ALL OTHER
|
||||
; CONFIGURATION FILES BELOW THIS FILE MUST USE ".SET" TO OVERRIDE
|
||||
; SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT TO USE ".EQU"
|
||||
; TO REDEFINE A PREVIOUS DEFINITION.
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "RomWBW", " [", CONFIG, "]"
|
||||
;
|
||||
368
Source/HBIOS/cfg_MBC.asm
Normal file
368
Source/HBIOS/cfg_MBC.asm
Normal file
@@ -0,0 +1,368 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: MBC
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD,
|
||||
; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
|
||||
; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE
|
||||
; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A
|
||||
; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "Nhyodyne", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "cfg_MASTER.asm"
|
||||
;
|
||||
PLATFORM .SET PLT_MBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .SET SPD_HILO ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .SET SPD_LOW ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .SET 8000000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .SET 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .SET SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .SET MM_MBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
MPCL_RAM .SET $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
|
||||
MPCL_ROM .SET $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
|
||||
;
|
||||
RTCIO .SET $70 ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .SET $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .SET TRUE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .SET $B0 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .SET TRUE ; ENABLE CTC PERIODIC TIMER
|
||||
CTCMODE .SET CTCMODE_CTR ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
|
||||
CTCPRE .SET 256 ; PRESCALE CONSTANT (1-256)
|
||||
CTCPRECH .SET 2 ; PRESCALE CHANNEL (0-3)
|
||||
CTCTIMCH .SET 3 ; TIMER CHANNEL (0-3)
|
||||
CTCOSC .SET (4915200/8) ; CTC CLOCK FREQUENCY
|
||||
;
|
||||
PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
;
|
||||
WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
;
|
||||
FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .SET TRUE ; ENABLES STATUS LED
|
||||
LEDMODE .SET LEDMODE_RTC ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .SET RTCIO ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .SET 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .SET $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .SET $FF ; SSER: STATUS PORT
|
||||
SSERDATA .SET $FF ; SSER: DATA PORT
|
||||
SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
;
|
||||
UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .SET 3 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .SET $68 ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .SET $80 ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .SET SER_300_8N1 ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .SET $88 ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .SET $FF ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .SET FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
;
|
||||
Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
;
|
||||
SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .SET 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
SIO0MODE .SET SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .SET $B0 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .SET (4915200/8) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .SET DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .SET (4915200/8) ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
VDUSIZ .SET V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
|
||||
CVDUENABLE .SET TRUE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
CVDUMODE .SET CVDUMODE_MBC ; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
|
||||
CVDUMON .SET CVDUMON_CGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
|
||||
GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .SET TRUE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .SET TMSMODE_MBC ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .SET TRUE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VGASIZ .SET V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
|
||||
VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .SET TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .SET TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
;
|
||||
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .SET FDMODE_MBC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
RFCNT .SET 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
|
||||
;
|
||||
IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .SET IDEMODE_DIO ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .SET $20 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .SET $20 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .SET $28 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .SET FALSE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .SET FALSE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .SET $60 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .SET $20 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .SET $14 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .SET SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
;
|
||||
PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
ESPCONENABLE .SET TRUE ; ESP: ENABLE ESP32 CONSOLE IO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
HDSKTRACE .SET 1 ; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
;
|
||||
PIOENABLE .SET TRUE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
LPTMODE .SET LPTMODE_SPP ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
|
||||
LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
LPT0BASE .SET $E8 ; LPT 0: REGISTERS BASE ADR
|
||||
LPT1BASE .SET $EC ; LPT 1: REGISTERS BASE ADR
|
||||
;
|
||||
PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
PPACNT .SET 1 ; PPA: NUMBER OF PPA DEVICES (1-2)
|
||||
PPATRACE .SET 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPAMODE .SET PPAMODE_SPP ; PPA: DRIVER MODE: PPAMODE_[NONE|MG014]
|
||||
PPA0BASE .SET LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
PPA1BASE .SET LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
;
|
||||
IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
IMMCNT .SET 1 ; IMM: NUMBER OF IMM DEVICES (1-2)
|
||||
IMMTRACE .SET 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IMMMODE .SET IMMMODE_SPP ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
|
||||
IMM0BASE .SET LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
IMM1BASE .SET LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
;
|
||||
SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
SYQCNT .SET 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2)
|
||||
SYQTRACE .SET 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SYQMODE .SET IMMMODE_SPP ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
|
||||
SYQ0BASE .SET LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
SYQ1BASE .SET LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
;
|
||||
PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO4BASE .SET $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
|
||||
PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIOZBASE .SET $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
|
||||
PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
PIOSBASE .SET $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
|
||||
;
|
||||
UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
UFBASE .SET $0C ; UF: REGISTERS BASE ADR
|
||||
;
|
||||
SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .SET SNMODE_NONE ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
||||
;
|
||||
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .SET AYMODE_MBC ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
||||
;
|
||||
SPKENABLE .SET TRUE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .SET DMAMODE_MBC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
364
Source/HBIOS/cfg_MK4.asm
Normal file
364
Source/HBIOS/cfg_MK4.asm
Normal file
@@ -0,0 +1,364 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: MK4
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD,
|
||||
; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
|
||||
; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE
|
||||
; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A
|
||||
; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "Mark IV", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "cfg_MASTER.asm"
|
||||
;
|
||||
PLATFORM .SET PLT_MK4 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .SET SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .SET MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
RAMBIAS .SET ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
|
||||
;
|
||||
Z180_BASE .SET $40 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
|
||||
Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
|
||||
Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3)
|
||||
Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
|
||||
Z180_TIMER .SET TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
|
||||
;
|
||||
MK4_IDE .SET $80 ; MK4: IDE REGISTERS BASE ADR
|
||||
MK4_XAR .SET $88 ; MK4: EXTERNAL ADDRESS REGISTER (XAR) ADR
|
||||
MK4_SD .SET $89 ; MK4: SD CARD CONTROL REGISTER ADR
|
||||
MK4_RTC .SET $8A ; MK4: RTC LATCH REGISTER ADR
|
||||
;
|
||||
RTCIO .SET MK4_RTC ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .SET $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .SET $B0 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER
|
||||
;
|
||||
PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
;
|
||||
WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
;
|
||||
FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED)
|
||||
LEDMODE .SET LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .SET $0E ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .SET 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .SET $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .SET $FF ; SSER: STATUS PORT
|
||||
SSERDATA .SET $FF ; SSER: DATA PORT
|
||||
SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
;
|
||||
UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .SET 6 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .SET TRUE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .SET $18 ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .SET $80 ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .SET SER_300_8N1 ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .SET $C0 ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .SET $C8 ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .SET $D0 ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .SET $D8 ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
ASCIINTS .SET TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
ASCISWAP .SET FALSE ; ASCI: SWAP CHANNELS
|
||||
ASCIBOOT .SET 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
ASCI0CFG .SET DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG
|
||||
ASCI1CFG .SET DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG
|
||||
;
|
||||
Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
;
|
||||
SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .SET 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
SIO0MODE .SET SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .SET $B0 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .SET (4915200/8) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .SET DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .SET (4915200/8) ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
VDUSIZ .SET V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
|
||||
CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
CVDUMODE .SET CVDUMODE_ECB ; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
|
||||
CVDUMON .SET CVDUMON_EGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
|
||||
GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .SET TMSMODE_SCG ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VGASIZ .SET V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
|
||||
VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .SET TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .SET TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .SET FDMODE_DIDE ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
RFCNT .SET 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
|
||||
;
|
||||
IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .SET IDEMODE_MK4 ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .SET $80 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .SET $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .SET $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .SET TRUE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .SET TRUE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .SET IDEMODE_DIDE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .SET $20 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .SET $28 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .SET $28 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .SET FALSE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .SET FALSE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .SET IDEMODE_DIDE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .SET $30 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .SET $38 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .SET $38 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .SET FALSE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .SET FALSE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .SET 2 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .SET $14 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .SET $20 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .SET SDMODE_MK4 ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .SET TRUE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
;
|
||||
PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
PPPBASE .SET $60 ; PPP: PPI REGISTERS BASE ADDRESS
|
||||
PPPSDENABLE .SET TRUE ; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
|
||||
PPPSDTRACE .SET 1 ; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPPCONENABLE .SET TRUE ; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
LPTMODE .SET LPTMODE_NONE ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
|
||||
LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
LPT0BASE .SET $E8 ; LPT 0: REGISTERS BASE ADR
|
||||
LPT1BASE .SET $EC ; LPT 1: REGISTERS BASE ADR
|
||||
;
|
||||
PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
;
|
||||
IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
;
|
||||
SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
;
|
||||
PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO4BASE .SET $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
|
||||
PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIOZBASE .SET $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
|
||||
PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
PIOSBASE .SET $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
|
||||
;
|
||||
UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
UFBASE .SET $0C ; UF: REGISTERS BASE ADR
|
||||
;
|
||||
SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .SET SNMODE_VGM ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
||||
;
|
||||
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .SET AYMODE_SCG ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
||||
;
|
||||
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .SET DMAMODE_ECB ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
391
Source/HBIOS/cfg_MON.asm
Normal file
391
Source/HBIOS/cfg_MON.asm
Normal file
@@ -0,0 +1,391 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: MON
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD,
|
||||
; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
|
||||
; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE
|
||||
; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A
|
||||
; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "Monsputer", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "cfg_MASTER.asm"
|
||||
;
|
||||
PLATFORM .SET PLT_MON ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .SET 4000000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .SET SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .SET MM_MON ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
;
|
||||
RTCIO .SET $C0 ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .SET $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .SET $88 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER
|
||||
CTCMODE .SET CTCMODE_TIM16 ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
|
||||
CTCPRE .SET 256 ; PRESCALE CONSTANT (1-256)
|
||||
CTCPRECH .SET 2 ; PRESCALE CHANNEL (0-3)
|
||||
CTCTIMCH .SET 3 ; TIMER CHANNEL (0-3)
|
||||
CTCOSC .SET CPUOSC ; CTC CLOCK FREQUENCY
|
||||
;
|
||||
PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
SKZDIV .SET DIV_1 ; UART CLK (CLK2) DIVIDER FOR Z80-512K
|
||||
;
|
||||
WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
WDOGIO .SET $6E ; WATCHDOG REGISTER ADR
|
||||
;
|
||||
FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED)
|
||||
LEDMODE .SET LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .SET $0E ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .SET 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .SET $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .SET $FF ; SSER: STATUS PORT
|
||||
SSERDATA .SET $FF ; SSER: DATA PORT
|
||||
SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
DUARTCNT .SET 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
DUART0BASE .SET $A0 ; DUART 0: BASE ADDRESS OF CHIP
|
||||
DUART0ACFG .SET DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG
|
||||
DUART0BCFG .SET DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG
|
||||
DUART1BASE .SET $40 ; DUART 1: BASE ADDRESS OF CHIP
|
||||
DUART1ACFG .SET DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
|
||||
DUART1BCFG .SET DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
|
||||
;
|
||||
UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .SET 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .SET $FF ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .SET $FF ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .SET $FF ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .SET $FF ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .SET FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
;
|
||||
Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
ACIADEBUG .SET FALSE ; ACIA: ENABLE DEBUG OUTPUT
|
||||
ACIACNT .SET 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
ACIA0BASE .SET $80 ; ACIA 0: REGISTERS BASE ADR
|
||||
ACIA0CLK .SET CPUOSC ; ACIA 0: OSC FREQ IN HZ
|
||||
ACIA0DIV .SET 1 ; ACIA 0: SERIAL CLOCK DIVIDER
|
||||
ACIA0CFG .SET DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
ACIA1BASE .SET $40 ; ACIA 1: REGISTERS BASE ADR
|
||||
ACIA1CLK .SET CPUOSC ; ACIA 1: OSC FREQ IN HZ
|
||||
ACIA1DIV .SET 1 ; ACIA 1: SERIAL CLOCK DIVIDER
|
||||
ACIA1CFG .SET DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .SET 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
SIO0MODE .SET SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .SET CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .SET DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .SET CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1MODE .SET SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO1BASE .SET $84 ; SIO 1: REGISTERS BASE ADR
|
||||
SIO1ACLK .SET CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1ACFG .SET DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG
|
||||
SIO1ACTCC .SET -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1BCLK .SET CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1BCFG .SET DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG
|
||||
SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .SET TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .SET TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
;
|
||||
IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .SET IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .SET $10 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .SET $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .SET $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .SET TRUE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .SET TRUE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .SET $20 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .SET SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .SET 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
CHTRACE .SET 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHUSBTRACE .SET 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHSDTRACE .SET 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHCNT .SET 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2)
|
||||
CH0BASE .SET $3E ; CH 0: BASE I/O ADDRESS
|
||||
CH0USBENABLE .SET TRUE ; CH 0: ENABLE USB DISK
|
||||
CH0SDENABLE .SET FALSE ; CH 0: ENABLE SD DISK
|
||||
CH1BASE .SET $3C ; CH 1: BASE I/O ADDRESS
|
||||
CH1USBENABLE .SET TRUE ; CH 1: ENABLE USB DISK
|
||||
CH1SDENABLE .SET FALSE ; CH 1: ENABLE SD DISK
|
||||
;
|
||||
PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
|
||||
LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
LPT0BASE .SET $0C ; LPT 0: REGISTERS BASE ADR
|
||||
LPT1BASE .SET $00 ; LPT 1: REGISTERS BASE ADR
|
||||
;
|
||||
PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
PPACNT .SET 1 ; PPA: NUMBER OF PPA DEVICES (1-2)
|
||||
PPATRACE .SET 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPAMODE .SET PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
|
||||
PPA0BASE .SET LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
PPA1BASE .SET LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
;
|
||||
IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
IMMCNT .SET 1 ; IMM: NUMBER OF IMM DEVICES (1-2)
|
||||
IMMTRACE .SET 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IMMMODE .SET IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
|
||||
IMM0BASE .SET LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
IMM1BASE .SET LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
;
|
||||
SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
SYQCNT .SET 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2)
|
||||
SYQTRACE .SET 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SYQMODE .SET IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
|
||||
SYQ0BASE .SET LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
SYQ1BASE .SET LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
;
|
||||
PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
;
|
||||
UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
;
|
||||
SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
||||
;
|
||||
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
||||
;
|
||||
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .SET DMAMODE_RC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
357
Source/HBIOS/cfg_N8.asm
Normal file
357
Source/HBIOS/cfg_N8.asm
Normal file
@@ -0,0 +1,357 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: N8
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD,
|
||||
; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
|
||||
; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE
|
||||
; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A
|
||||
; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "RetroBrew N8", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "cfg_MASTER.asm"
|
||||
;
|
||||
PLATFORM .SET PLT_N8 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .SET SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .SET MM_N8 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
RAMBIAS .SET 0 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
|
||||
;
|
||||
Z180_BASE .SET $40 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
|
||||
Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
|
||||
Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3)
|
||||
Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
|
||||
Z180_TIMER .SET TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
|
||||
;
|
||||
N8_PPI0 .SET $80 ; N8: FIRST PARALLEL PORT REGISTERS BASE ADR
|
||||
N8_PPI1 .SET $84 ; N8: SECOND PARALLEL PORT REGISTERS BASE ADR
|
||||
N8_RTC .SET $88 ; N8: RTC LATCH REGISTER ADR
|
||||
N8_ACR .SET $94 ; N8: AUXILLARY CONTROL REGISTER (ACR) ADR
|
||||
N8_RMAP .SET $96 ; N8: ROM PAGE REGISTER ADR
|
||||
N8_DEFACR .SET $1B ; N8: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE)
|
||||
;
|
||||
RTCIO .SET N8_RTC ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .SET $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .SET $B0 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER
|
||||
;
|
||||
PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
;
|
||||
WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
;
|
||||
FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .SET FALSE ; ENABLES STATUS LED
|
||||
LEDMODE .SET LEDMODE_RTC ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .SET RTCIO ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .SET N8_PPI0 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .SET N8_PPI0 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .SET 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .SET $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .SET $FF ; SSER: STATUS PORT
|
||||
SSERDATA .SET $FF ; SSER: DATA PORT
|
||||
SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
;
|
||||
UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .SET 5 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .SET TRUE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .SET $80 ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .SET $C0 ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .SET $C8 ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .SET $D0 ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .SET $D8 ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
ASCIINTS .SET TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
ASCISWAP .SET FALSE ; ASCI: SWAP CHANNELS
|
||||
ASCIBOOT .SET 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
ASCI0CFG .SET DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG
|
||||
ASCI1CFG .SET DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG
|
||||
;
|
||||
Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
;
|
||||
SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .SET 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
SIO0MODE .SET SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .SET $B0 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .SET (4915200/8) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .SET DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .SET (4915200/8) ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
VDUSIZ .SET V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
|
||||
CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
CVDUMODE .SET CVDUMODE_ECB ; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
|
||||
CVDUMON .SET CVDUMON_EGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
|
||||
GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .SET TRUE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .SET TMSMODE_N8 ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VGASIZ .SET V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
|
||||
VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .SET TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .SET TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .SET FDMODE_N8 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
RFCNT .SET 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
|
||||
;
|
||||
IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .SET IDEMODE_DIO ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .SET $20 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .SET $20 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .SET $28 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .SET FALSE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .SET FALSE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .SET N8_PPI0 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .SET SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .SET N8_PPI0 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
;
|
||||
PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
;
|
||||
PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
;
|
||||
IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
;
|
||||
SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
;
|
||||
PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO4BASE .SET $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
|
||||
PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIOZBASE .SET $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
|
||||
PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
PIOSBASE .SET N8_PPI0 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
|
||||
;
|
||||
UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
UFBASE .SET $0C ; UF: REGISTERS BASE ADR
|
||||
;
|
||||
SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .SET SNMODE_VGM ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
||||
;
|
||||
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .SET AYMODE_N8 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
||||
;
|
||||
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .SET DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
396
Source/HBIOS/cfg_NABU.asm
Normal file
396
Source/HBIOS/cfg_NABU.asm
Normal file
@@ -0,0 +1,396 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: NABU
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD,
|
||||
; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
|
||||
; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE
|
||||
; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A
|
||||
; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "NABU Personal Computer", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "cfg_MASTER.asm"
|
||||
;
|
||||
PLATFORM .SET PLT_NABU ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .SET 3580000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .SET SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .SET MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
MPGSEL_0 .SET $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_1 .SET $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_2 .SET $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_3 .SET $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGENA .SET $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
|
||||
;
|
||||
RTCIO .SET $C0 ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .SET $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .SET $88 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER
|
||||
CTCMODE .SET CTCMODE_TIM16 ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
|
||||
CTCPRE .SET 256 ; PRESCALE CONSTANT (1-256)
|
||||
CTCPRECH .SET 2 ; PRESCALE CHANNEL (0-3)
|
||||
CTCTIMCH .SET 3 ; TIMER CHANNEL (0-3)
|
||||
CTCOSC .SET CPUOSC ; CTC CLOCK FREQUENCY
|
||||
;
|
||||
PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
SKZDIV .SET DIV_1 ; UART CLK (CLK2) DIVIDER FOR Z80-512K
|
||||
;
|
||||
WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
WDOGIO .SET $6E ; WATCHDOG REGISTER ADR
|
||||
;
|
||||
FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .SET FALSE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .SET TRUE ; ENABLES STATUS LED (SINGLE LED)
|
||||
LEDMODE .SET LEDMODE_NABU ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .SET $00 ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .SET 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .SET $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
|
||||
DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .SET TRUE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .SET $FF ; SSER: STATUS PORT
|
||||
SSERDATA .SET $FF ; SSER: DATA PORT
|
||||
SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
DUARTCNT .SET 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
DUART0BASE .SET $A0 ; DUART 0: BASE ADDRESS OF CHIP
|
||||
DUART0ACFG .SET DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG
|
||||
DUART0BCFG .SET DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG
|
||||
DUART1BASE .SET $40 ; DUART 1: BASE ADDRESS OF CHIP
|
||||
DUART1ACFG .SET DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
|
||||
DUART1BCFG .SET DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
|
||||
;
|
||||
UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .SET 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .SET $48 ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .SET $FF ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .SET $FF ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .SET $FF ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .SET FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
;
|
||||
Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
ACIADEBUG .SET FALSE ; ACIA: ENABLE DEBUG OUTPUT
|
||||
ACIACNT .SET 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
ACIA0BASE .SET $80 ; ACIA 0: REGISTERS BASE ADR
|
||||
ACIA0CLK .SET CPUOSC ; ACIA 0: OSC FREQ IN HZ
|
||||
ACIA0DIV .SET 1 ; ACIA 0: SERIAL CLOCK DIVIDER
|
||||
ACIA0CFG .SET DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
ACIA1BASE .SET $40 ; ACIA 1: REGISTERS BASE ADR
|
||||
ACIA1CLK .SET CPUOSC ; ACIA 1: OSC FREQ IN HZ
|
||||
ACIA1DIV .SET 1 ; ACIA 1: SERIAL CLOCK DIVIDER
|
||||
ACIA1CFG .SET DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .SET 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
SIO0MODE .SET SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .SET CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .SET DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .SET CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1MODE .SET SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO1BASE .SET $84 ; SIO 1: REGISTERS BASE ADR
|
||||
SIO1ACLK .SET CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1ACFG .SET DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG
|
||||
SIO1ACTCC .SET -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1BCLK .SET CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1BCFG .SET DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG
|
||||
SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .SET TRUE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .SET TMSMODE_NABU ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .SET TRUE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .SET TRUE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .SET TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .SET TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
;
|
||||
IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .SET IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .SET $10 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .SET $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .SET $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .SET TRUE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .SET TRUE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .SET $60 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .SET SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .SET 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
CHTRACE .SET 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHUSBTRACE .SET 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHSDTRACE .SET 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHCNT .SET 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2)
|
||||
CH0BASE .SET $3E ; CH 0: BASE I/O ADDRESS
|
||||
CH0USBENABLE .SET TRUE ; CH 0: ENABLE USB DISK
|
||||
CH0SDENABLE .SET FALSE ; CH 0: ENABLE SD DISK
|
||||
CH1BASE .SET $3C ; CH 1: BASE I/O ADDRESS
|
||||
CH1USBENABLE .SET TRUE ; CH 1: ENABLE USB DISK
|
||||
CH1SDENABLE .SET FALSE ; CH 1: ENABLE SD DISK
|
||||
;
|
||||
PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
|
||||
LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
LPT0BASE .SET $0C ; LPT 0: REGISTERS BASE ADR
|
||||
LPT1BASE .SET $00 ; LPT 1: REGISTERS BASE ADR
|
||||
;
|
||||
PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
PPACNT .SET 1 ; PPA: NUMBER OF PPA DEVICES (1-2)
|
||||
PPATRACE .SET 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPAMODE .SET PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
|
||||
PPA0BASE .SET LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
PPA1BASE .SET LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
;
|
||||
IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
IMMCNT .SET 1 ; IMM: NUMBER OF IMM DEVICES (1-2)
|
||||
IMMTRACE .SET 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IMMMODE .SET IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
|
||||
IMM0BASE .SET LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
IMM1BASE .SET LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
;
|
||||
SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
SYQCNT .SET 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2)
|
||||
SYQTRACE .SET 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SYQMODE .SET IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
|
||||
SYQ0BASE .SET LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
SYQ1BASE .SET LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
;
|
||||
PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
;
|
||||
UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
;
|
||||
SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
||||
;
|
||||
AY38910ENABLE .SET TRUE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .SET AYMODE_NABU ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
||||
;
|
||||
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .SET DMAMODE_RC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
391
Source/HBIOS/cfg_RCZ180.asm
Normal file
391
Source/HBIOS/cfg_RCZ180.asm
Normal file
@@ -0,0 +1,391 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: RCZ180
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD,
|
||||
; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
|
||||
; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE
|
||||
; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A
|
||||
; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "RCBus", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "cfg_MASTER.asm"
|
||||
;
|
||||
PLATFORM .SET PLT_RCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .SET SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .SET MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
RAMBIAS .SET ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
|
||||
MPGSEL_0 .SET $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_1 .SET $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_2 .SET $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_3 .SET $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGENA .SET $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
|
||||
;
|
||||
Z180_BASE .SET $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
|
||||
Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
|
||||
Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3)
|
||||
Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
|
||||
Z180_TIMER .SET TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
|
||||
;
|
||||
RTCIO .SET $0C ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .SET $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .SET $88 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER
|
||||
;
|
||||
PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
;
|
||||
WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
;
|
||||
FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED)
|
||||
LEDMODE .SET LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .SET $0E ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .SET TRUE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .SET $AA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .SET 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .SET $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .SET $FF ; SSER: STATUS PORT
|
||||
SSERDATA .SET $FF ; SSER: DATA PORT
|
||||
SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
DUARTCNT .SET 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
DUART0BASE .SET $A0 ; DUART 0: BASE ADDRESS OF CHIP
|
||||
DUART0ACFG .SET DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG
|
||||
DUART0BCFG .SET DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG
|
||||
DUART1BASE .SET $40 ; DUART 1: BASE ADDRESS OF CHIP
|
||||
DUART1ACFG .SET DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
|
||||
DUART1BCFG .SET DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
|
||||
;
|
||||
UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .SET 4 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .SET $80 ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .SET $88 ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .SET $A0 ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .SET $A8 ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
ASCIINTS .SET TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
ASCISWAP .SET FALSE ; ASCI: SWAP CHANNELS
|
||||
ASCIBOOT .SET 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
ASCI0CFG .SET DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG
|
||||
ASCI1CFG .SET DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG
|
||||
;
|
||||
Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
;
|
||||
SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .SET 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
SIO0MODE .SET SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .SET 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .SET SER_115200_8N1 ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .SET 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .SET SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1MODE .SET SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO1BASE .SET $84 ; SIO 1: REGISTERS BASE ADR
|
||||
SIO1ACLK .SET 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1ACFG .SET SER_115200_8N1 ; SIO 1A: SERIAL LINE CONFIG
|
||||
SIO1ACTCC .SET -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1BCLK .SET 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1BCFG .SET SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG
|
||||
SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .SET TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .SET TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
;
|
||||
IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .SET IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .SET $10 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .SET $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .SET $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .SET TRUE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .SET TRUE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .SET $20 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .SET SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .SET 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .SET TRUE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
CHTRACE .SET 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHUSBTRACE .SET 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHSDTRACE .SET 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHCNT .SET 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2)
|
||||
CH0BASE .SET $3E ; CH 0: BASE I/O ADDRESS
|
||||
CH0USBENABLE .SET TRUE ; CH 0: ENABLE USB DISK
|
||||
CH0SDENABLE .SET FALSE ; CH 0: ENABLE SD DISK
|
||||
CH1BASE .SET $3C ; CH 1: BASE I/O ADDRESS
|
||||
CH1USBENABLE .SET TRUE ; CH 1: ENABLE USB DISK
|
||||
CH1SDENABLE .SET FALSE ; CH 1: ENABLE SD DISK
|
||||
;
|
||||
PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
|
||||
LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
LPT0BASE .SET $0C ; LPT 0: REGISTERS BASE ADR
|
||||
LPT1BASE .SET $00 ; LPT 1: REGISTERS BASE ADR
|
||||
;
|
||||
PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
PPACNT .SET 1 ; PPA: NUMBER OF PPA DEVICES (1-2)
|
||||
PPATRACE .SET 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPAMODE .SET PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
|
||||
PPA0BASE .SET LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
PPA1BASE .SET LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
;
|
||||
IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
IMMCNT .SET 1 ; IMM: NUMBER OF IMM DEVICES (1-2)
|
||||
IMMTRACE .SET 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IMMMODE .SET IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
|
||||
IMM0BASE .SET LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
IMM1BASE .SET LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
;
|
||||
SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
SYQCNT .SET 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2)
|
||||
SYQTRACE .SET 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SYQMODE .SET IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
|
||||
SYQ0BASE .SET LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
SYQ1BASE .SET LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
;
|
||||
PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
;
|
||||
UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
;
|
||||
SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
||||
;
|
||||
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .SET AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
||||
;
|
||||
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .SET DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
401
Source/HBIOS/cfg_RCZ280.asm
Normal file
401
Source/HBIOS/cfg_RCZ280.asm
Normal file
@@ -0,0 +1,401 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: RCZ280
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD,
|
||||
; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
|
||||
; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE
|
||||
; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A
|
||||
; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "RCBus", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "cfg_MASTER.asm"
|
||||
;
|
||||
PLATFORM .SET PLT_RCZ280 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .SET CPU_Z280 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .SET 24000000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .SET 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .SET SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .SET MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
RAMBIAS .SET ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
|
||||
MPGSEL_0 .SET $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_1 .SET $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_2 .SET $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_3 .SET $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGENA .SET $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
|
||||
;
|
||||
Z280_MEMLOWAIT .SET 0 ; Z280: LOW 8MB MEMORY WAIT STATES (0-3)
|
||||
Z280_MEMHIWAIT .SET 0 ; Z280: HIGH 8MB MEMORY WAIT STATES (0-3)
|
||||
Z280_IOWAIT .SET 1 ; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
|
||||
Z280_INTWAIT .SET 0 ; Z280: INT ACK WAIT STATUS (0-3)
|
||||
Z280_TIMER .SET TRUE ; Z280: ENABLE INTERNAL Z280 SYSTEM PERIODIC TIMER
|
||||
;
|
||||
RTCIO .SET $C0 ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .SET $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .SET $88 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER
|
||||
;
|
||||
PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
;
|
||||
WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
;
|
||||
FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED)
|
||||
LEDMODE .SET LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .SET $0E ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .SET TRUE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .SET 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .SET $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .SET $FF ; SSER: STATUS PORT
|
||||
SSERDATA .SET $FF ; SSER: DATA PORT
|
||||
SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
DUARTCNT .SET 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
DUART0BASE .SET $A0 ; DUART 0: BASE ADDRESS OF CHIP
|
||||
DUART0ACFG .SET DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG
|
||||
DUART0BCFG .SET DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG
|
||||
DUART1BASE .SET $40 ; DUART 1: BASE ADDRESS OF CHIP
|
||||
DUART1ACFG .SET DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
|
||||
DUART1BCFG .SET DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
|
||||
;
|
||||
UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .SET 4 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .SET $80 ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .SET $88 ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .SET $A0 ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .SET $A8 ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .SET FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
;
|
||||
Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
Z2UOSC .SET 1843200 ; Z2U: OSC FREQUENCY IN MHZ
|
||||
Z2UOSCEXT .SET TRUE ; Z2U: USE EXTERNAL OSCILLATOR
|
||||
Z2U0BASE .SET $10 ; Z2U 0: BASE I/O ADDRESS
|
||||
Z2U0CFG .SET DEFSERCFG ; Z2U 0: SERIAL LINE CONFIG
|
||||
Z2U0HFC .SET FALSE ; Z2U 0: ENABLE HARDWARE FLOW CONTROL
|
||||
;
|
||||
ACIAENABLE .SET TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
ACIADEBUG .SET FALSE ; ACIA: ENABLE DEBUG OUTPUT
|
||||
ACIACNT .SET 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
ACIA0BASE .SET $80 ; ACIA 0: REGISTERS BASE ADR
|
||||
ACIA0CLK .SET 7372800 ; ACIA 0: OSC FREQ IN HZ
|
||||
ACIA0DIV .SET 1 ; ACIA 0: SERIAL CLOCK DIVIDER
|
||||
ACIA0CFG .SET DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
ACIA1BASE .SET $40 ; ACIA 1: REGISTERS BASE ADR
|
||||
ACIA1CLK .SET 7372800 ; ACIA 1: OSC FREQ IN HZ
|
||||
ACIA1DIV .SET 1 ; ACIA 1: SERIAL CLOCK DIVIDER
|
||||
ACIA1CFG .SET DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .SET 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
SIO0MODE .SET SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .SET 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .SET DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .SET 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1MODE .SET SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO1BASE .SET $84 ; SIO 1: REGISTERS BASE ADR
|
||||
SIO1ACLK .SET 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1ACFG .SET DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG
|
||||
SIO1ACTCC .SET -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1BCLK .SET 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1BCFG .SET DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG
|
||||
SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .SET TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .SET TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
;
|
||||
IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .SET IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .SET $10 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .SET $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .SET $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .SET TRUE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .SET TRUE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .SET $20 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .SET SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .SET 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .SET TRUE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
CHTRACE .SET 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHUSBTRACE .SET 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHSDTRACE .SET 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHCNT .SET 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2)
|
||||
CH0BASE .SET $3E ; CH 0: BASE I/O ADDRESS
|
||||
CH0USBENABLE .SET TRUE ; CH 0: ENABLE USB DISK
|
||||
CH0SDENABLE .SET FALSE ; CH 0: ENABLE SD DISK
|
||||
CH1BASE .SET $3C ; CH 1: BASE I/O ADDRESS
|
||||
CH1USBENABLE .SET TRUE ; CH 1: ENABLE USB DISK
|
||||
CH1SDENABLE .SET FALSE ; CH 1: ENABLE SD DISK
|
||||
;
|
||||
PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
|
||||
LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
LPT0BASE .SET $0C ; LPT 0: REGISTERS BASE ADR
|
||||
LPT1BASE .SET $00 ; LPT 1: REGISTERS BASE ADR
|
||||
;
|
||||
PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
PPACNT .SET 1 ; PPA: NUMBER OF PPA DEVICES (1-2)
|
||||
PPATRACE .SET 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPAMODE .SET PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
|
||||
PPA0BASE .SET LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
PPA1BASE .SET LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
;
|
||||
IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
IMMCNT .SET 1 ; IMM: NUMBER OF IMM DEVICES (1-2)
|
||||
IMMTRACE .SET 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IMMMODE .SET IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
|
||||
IMM0BASE .SET LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
IMM1BASE .SET LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
;
|
||||
SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
SYQCNT .SET 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2)
|
||||
SYQTRACE .SET 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SYQMODE .SET IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
|
||||
SYQ0BASE .SET LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
SYQ1BASE .SET LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
;
|
||||
PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
;
|
||||
UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
;
|
||||
SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
||||
;
|
||||
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
||||
;
|
||||
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .SET DMAMODE_Z280 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
396
Source/HBIOS/cfg_RCZ80.asm
Normal file
396
Source/HBIOS/cfg_RCZ80.asm
Normal file
@@ -0,0 +1,396 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: RCZ80
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD,
|
||||
; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
|
||||
; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE
|
||||
; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A
|
||||
; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "RCBus", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "cfg_MASTER.asm"
|
||||
;
|
||||
PLATFORM .SET PLT_RCZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .SET 7372800 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .SET 1 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .SET SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .SET MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
MPGSEL_0 .SET $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_1 .SET $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_2 .SET $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_3 .SET $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGENA .SET $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
|
||||
;
|
||||
RTCIO .SET $C0 ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .SET $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .SET TRUE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .SET $88 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER
|
||||
CTCMODE .SET CTCMODE_TIM16 ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
|
||||
CTCPRE .SET 256 ; PRESCALE CONSTANT (1-256)
|
||||
CTCPRECH .SET 2 ; PRESCALE CHANNEL (0-3)
|
||||
CTCTIMCH .SET 3 ; TIMER CHANNEL (0-3)
|
||||
CTCOSC .SET CPUOSC ; CTC CLOCK FREQUENCY
|
||||
;
|
||||
PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
SKZDIV .SET DIV_1 ; UART CLK (CLK2) DIVIDER FOR Z80-512K
|
||||
;
|
||||
WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
WDOGIO .SET $6E ; WATCHDOG REGISTER ADR
|
||||
;
|
||||
FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED)
|
||||
LEDMODE .SET LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .SET $0E ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .SET TRUE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .SET 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .SET $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .SET $FF ; SSER: STATUS PORT
|
||||
SSERDATA .SET $FF ; SSER: DATA PORT
|
||||
SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
DUARTCNT .SET 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
DUART0BASE .SET $A0 ; DUART 0: BASE ADDRESS OF CHIP
|
||||
DUART0ACFG .SET DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG
|
||||
DUART0BCFG .SET DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG
|
||||
DUART1BASE .SET $40 ; DUART 1: BASE ADDRESS OF CHIP
|
||||
DUART1ACFG .SET DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
|
||||
DUART1BCFG .SET DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
|
||||
;
|
||||
UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .SET 4 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .SET $80 ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .SET $88 ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .SET $A0 ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .SET $A8 ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .SET FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
;
|
||||
Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .SET TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
ACIADEBUG .SET FALSE ; ACIA: ENABLE DEBUG OUTPUT
|
||||
ACIACNT .SET 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
ACIA0BASE .SET $80 ; ACIA 0: REGISTERS BASE ADR
|
||||
ACIA0CLK .SET CPUOSC ; ACIA 0: OSC FREQ IN HZ
|
||||
ACIA0DIV .SET 1 ; ACIA 0: SERIAL CLOCK DIVIDER
|
||||
ACIA0CFG .SET DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
ACIA1BASE .SET $40 ; ACIA 1: REGISTERS BASE ADR
|
||||
ACIA1CLK .SET CPUOSC ; ACIA 1: OSC FREQ IN HZ
|
||||
ACIA1DIV .SET 1 ; ACIA 1: SERIAL CLOCK DIVIDER
|
||||
ACIA1CFG .SET DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .SET 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
SIO0MODE .SET SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .SET CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .SET DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .SET CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1MODE .SET SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO1BASE .SET $84 ; SIO 1: REGISTERS BASE ADR
|
||||
SIO1ACLK .SET CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1ACFG .SET DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG
|
||||
SIO1ACTCC .SET -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1BCLK .SET CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1BCFG .SET DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG
|
||||
SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .SET TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .SET TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
;
|
||||
IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .SET IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .SET $10 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .SET $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .SET $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .SET TRUE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .SET TRUE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .SET $20 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .SET SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .SET 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .SET TRUE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
CHTRACE .SET 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHUSBTRACE .SET 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHSDTRACE .SET 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHCNT .SET 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2)
|
||||
CH0BASE .SET $3E ; CH 0: BASE I/O ADDRESS
|
||||
CH0USBENABLE .SET TRUE ; CH 0: ENABLE USB DISK
|
||||
CH0SDENABLE .SET FALSE ; CH 0: ENABLE SD DISK
|
||||
CH1BASE .SET $3C ; CH 1: BASE I/O ADDRESS
|
||||
CH1USBENABLE .SET TRUE ; CH 1: ENABLE USB DISK
|
||||
CH1SDENABLE .SET FALSE ; CH 1: ENABLE SD DISK
|
||||
;
|
||||
PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
|
||||
LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
LPT0BASE .SET $0C ; LPT 0: REGISTERS BASE ADR
|
||||
LPT1BASE .SET $00 ; LPT 1: REGISTERS BASE ADR
|
||||
;
|
||||
PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
PPACNT .SET 1 ; PPA: NUMBER OF PPA DEVICES (1-2)
|
||||
PPATRACE .SET 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPAMODE .SET PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
|
||||
PPA0BASE .SET LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
PPA1BASE .SET LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
;
|
||||
IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
IMMCNT .SET 1 ; IMM: NUMBER OF IMM DEVICES (1-2)
|
||||
IMMTRACE .SET 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IMMMODE .SET IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
|
||||
IMM0BASE .SET LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
IMM1BASE .SET LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
;
|
||||
SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
SYQCNT .SET 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2)
|
||||
SYQTRACE .SET 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SYQMODE .SET IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
|
||||
SYQ0BASE .SET LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
SYQ1BASE .SET LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
;
|
||||
PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
;
|
||||
UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
;
|
||||
SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
||||
;
|
||||
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
||||
;
|
||||
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .SET DMAMODE_RC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
345
Source/HBIOS/cfg_RPH.asm
Normal file
345
Source/HBIOS/cfg_RPH.asm
Normal file
@@ -0,0 +1,345 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: RPH
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD,
|
||||
; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
|
||||
; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE
|
||||
; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A
|
||||
; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "Rhyophyre", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "cfg_MASTER.asm"
|
||||
;
|
||||
PLATFORM .SET PLT_RPH ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .SET TRUE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .SET SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .SET MM_RPH ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
RAMBIAS .SET 0 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
|
||||
;
|
||||
Z180_BASE .SET $40 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
|
||||
Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
|
||||
Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3)
|
||||
Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
|
||||
Z180_TIMER .SET TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
|
||||
;
|
||||
RPH_PPI0 .SET $88 ; RPH: FIRST PARALLEL PORT REGISTERS BASE ADR
|
||||
RPH_RTC .SET $84 ; RPH: RTC LATCH REGISTER ADR
|
||||
RPH_ACR .SET $80 ; RPH: AUXILLARY CONTROL REGISTER (ACR) ADR
|
||||
RPH_DEFACR .SET $20 ; RPH: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE)
|
||||
;
|
||||
RTCIO .SET RPH_RTC ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .SET $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .SET $B0 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER
|
||||
;
|
||||
PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
;
|
||||
WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
;
|
||||
FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .SET FALSE ; ENABLES STATUS LED
|
||||
LEDMODE .SET LEDMODE_RTC ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .SET RTCIO ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .SET RPH_PPI0 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .SET RPH_PPI0 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .SET 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .SET $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .SET $FF ; SSER: STATUS PORT
|
||||
SSERDATA .SET $FF ; SSER: DATA PORT
|
||||
SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
;
|
||||
UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .SET 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .SET $FF ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .SET $FF ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .SET $FF ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .SET $FF ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
ASCIINTS .SET TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
ASCISWAP .SET FALSE ; ASCI: SWAP CHANNELS
|
||||
ASCIBOOT .SET 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
ASCI0CFG .SET DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG
|
||||
ASCI1CFG .SET DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG
|
||||
;
|
||||
Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
;
|
||||
SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
;
|
||||
XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
VDUSIZ .SET V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
|
||||
CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
CVDUMODE .SET CVDUMODE_ECB ; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
|
||||
CVDUMON .SET CVDUMON_EGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
|
||||
GDCENABLE .SET TRUE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
GDCMODE .SET GDCMODE_RPH ; GDC: GDC MODE: GDCMODE_[NONE|ECB|RPH]
|
||||
GDCMON .SET GDCMON_EGA ; GDC: GDC MONITOR SETUP: GDCMON_[NONE|CGA|EGA]
|
||||
TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .SET TMSMODE_N8 ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VGASIZ .SET V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
|
||||
VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .SET TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .SET TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .SET FDMODE_N8 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
RFCNT .SET 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
|
||||
;
|
||||
IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .SET IDEMODE_DIO ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .SET $20 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .SET $20 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .SET $28 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .SET FALSE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .SET FALSE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .SET RPH_PPI0 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .SET SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .SET RPH_PPI0 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
;
|
||||
PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .SET FALSE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .SET FALSE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
;
|
||||
PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
;
|
||||
IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
;
|
||||
SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
;
|
||||
PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO4BASE .SET $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
|
||||
PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIOZBASE .SET $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
|
||||
PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
PIOSBASE .SET RPH_PPI0 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
|
||||
;
|
||||
UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
UFBASE .SET $0C ; UF: REGISTERS BASE ADR
|
||||
;
|
||||
SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .SET SNMODE_NONE ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
||||
;
|
||||
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .SET AYMODE_N8 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
||||
;
|
||||
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .SET DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
381
Source/HBIOS/cfg_S100.asm
Normal file
381
Source/HBIOS/cfg_S100.asm
Normal file
@@ -0,0 +1,381 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: S100
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD,
|
||||
; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
|
||||
; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE
|
||||
; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A
|
||||
; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "S100", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "cfg_MASTER.asm"
|
||||
;
|
||||
PLATFORM .SET PLT_S100 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .SET SER_57600_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .SET MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
RAMBIAS .SET ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
|
||||
MPGSEL_0 .SET $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_1 .SET $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_2 .SET $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_3 .SET $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGENA .SET $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
|
||||
;
|
||||
Z180_BASE .SET $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
|
||||
Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
|
||||
Z180_MEMWAIT .SET 1 ; Z180: MEMORY WAIT STATES (0-3)
|
||||
Z180_IOWAIT .SET 2 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
|
||||
Z180_TIMER .SET TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
|
||||
;
|
||||
RTCIO .SET $0C ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .SET $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .SET $88 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER
|
||||
;
|
||||
PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
;
|
||||
WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
;
|
||||
FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .SET TRUE ; ENABLES STATUS LED (SINGLE LED)
|
||||
LEDMODE .SET LEDMODE_SC ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .SET $0E ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .SET 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .SET $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .SET $FF ; SSER: STATUS PORT
|
||||
SSERDATA .SET $FF ; SSER: DATA PORT
|
||||
SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
DUARTCNT .SET 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
DUART0BASE .SET $A0 ; DUART 0: BASE ADDRESS OF CHIP
|
||||
DUART0ACFG .SET DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG
|
||||
DUART0BCFG .SET DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG
|
||||
DUART1BASE .SET $40 ; DUART 1: BASE ADDRESS OF CHIP
|
||||
DUART1ACFG .SET DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
|
||||
DUART1BCFG .SET DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
|
||||
;
|
||||
UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .SET 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .SET $FF ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .SET $FF ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .SET $FF ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .SET $FF ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
ASCIINTS .SET TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
ASCISWAP .SET FALSE ; ASCI: SWAP CHANNELS
|
||||
ASCIBOOT .SET 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
ASCI0CFG .SET DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG
|
||||
ASCI1CFG .SET DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG
|
||||
;
|
||||
Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
;
|
||||
SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .SET 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
SIO0MODE .SET SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .SET 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .SET SER_115200_8N1 ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .SET 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .SET SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1MODE .SET SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO1BASE .SET $84 ; SIO 1: REGISTERS BASE ADR
|
||||
SIO1ACLK .SET 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1ACFG .SET SER_115200_8N1 ; SIO 1A: SERIAL LINE CONFIG
|
||||
SIO1ACTCC .SET -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1BCLK .SET 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1BCFG .SET SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG
|
||||
SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .SET TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .SET TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
;
|
||||
IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .SET IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .SET $10 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .SET $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .SET $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .SET TRUE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .SET TRUE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .SET $20 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .SET SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
;
|
||||
PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
|
||||
LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
LPT0BASE .SET $18 ; LPT 0: REGISTERS BASE ADR
|
||||
LPT1BASE .SET $00 ; LPT 1: REGISTERS BASE ADR
|
||||
;
|
||||
PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
PPACNT .SET 1 ; PPA: NUMBER OF PPA DEVICES (1-2)
|
||||
PPATRACE .SET 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPAMODE .SET PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
|
||||
PPA0BASE .SET LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
PPA1BASE .SET LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
;
|
||||
IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
IMMCNT .SET 1 ; IMM: NUMBER OF IMM DEVICES (1-2)
|
||||
IMMTRACE .SET 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IMMMODE .SET IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
|
||||
IMM0BASE .SET LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
IMM1BASE .SET LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
;
|
||||
SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
SYQCNT .SET 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2)
|
||||
SYQTRACE .SET 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SYQMODE .SET IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
|
||||
SYQ0BASE .SET LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
SYQ1BASE .SET LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
;
|
||||
PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
;
|
||||
UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
;
|
||||
SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
||||
;
|
||||
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .SET AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
||||
;
|
||||
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .SET DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
346
Source/HBIOS/cfg_SBC.asm
Normal file
346
Source/HBIOS/cfg_SBC.asm
Normal file
@@ -0,0 +1,346 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: SBC
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD,
|
||||
; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
|
||||
; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE
|
||||
; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A
|
||||
; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "RetroBrew SBC", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "cfg_MASTER.asm"
|
||||
;
|
||||
PLATFORM .SET PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .SET 8000000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .SET 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .SET SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .SET MM_SBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
MPCL_RAM .SET $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
|
||||
MPCL_ROM .SET $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
|
||||
;
|
||||
RTCIO .SET $70 ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .SET $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .SET $B0 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .SET TRUE ; ENABLE CTC PERIODIC TIMER
|
||||
CTCMODE .SET CTCMODE_CTR ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
|
||||
CTCPRE .SET 256 ; PRESCALE CONSTANT (1-256)
|
||||
CTCPRECH .SET 2 ; PRESCALE CHANNEL (0-3)
|
||||
CTCTIMCH .SET 3 ; TIMER CHANNEL (0-3)
|
||||
CTCOSC .SET 614400 ; CTC CLOCK FREQUENCY
|
||||
;
|
||||
PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
;
|
||||
WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
;
|
||||
FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .SET FALSE ; ENABLES STATUS LED
|
||||
LEDMODE .SET LEDMODE_RTC ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .SET RTCIO ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .SET 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .SET $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .SET $FF ; SSER: STATUS PORT
|
||||
SSERDATA .SET $FF ; SSER: DATA PORT
|
||||
SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
;
|
||||
UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .SET 7 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .SET TRUE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .SET $68 ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .SET $80 ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .SET SER_300_8N1 ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .SET $18 ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .SET $C0 ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .SET $C8 ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .SET $D0 ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .SET $D8 ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .SET FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
;
|
||||
Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
;
|
||||
SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .SET 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
SIO0MODE .SET SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .SET $B0 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .SET (4915200/8) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .SET DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .SET (4915200/8) ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
VDUSIZ .SET V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
|
||||
CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
CVDUMODE .SET CVDUMODE_ECB ; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
|
||||
CVDUMON .SET CVDUMON_EGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
|
||||
GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .SET TMSMODE_SCG ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VGASIZ .SET V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
|
||||
VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .SET TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .SET TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .SET FDMODE_DIO3 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
RFCNT .SET 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
|
||||
;
|
||||
IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .SET IDEMODE_DIO ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .SET $20 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .SET $20 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .SET $28 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .SET FALSE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .SET FALSE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .SET $60 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .SET $20 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .SET $14 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .SET SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
;
|
||||
PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
HDSKTRACE .SET 1 ; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
;
|
||||
PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
;
|
||||
PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
;
|
||||
IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
;
|
||||
SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
;
|
||||
PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO4BASE .SET $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
|
||||
PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIOZBASE .SET $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
|
||||
PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
PIOSBASE .SET $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
|
||||
;
|
||||
UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
UFBASE .SET $0C ; UF: REGISTERS BASE ADR
|
||||
;
|
||||
SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .SET SNMODE_VGM ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
||||
;
|
||||
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .SET AYMODE_SCG ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
||||
;
|
||||
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .SET DMAMODE_ECB ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
391
Source/HBIOS/cfg_SCZ180.asm
Normal file
391
Source/HBIOS/cfg_SCZ180.asm
Normal file
@@ -0,0 +1,391 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: SCZ180
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD,
|
||||
; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
|
||||
; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE
|
||||
; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A
|
||||
; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "Small Computer", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "cfg_MASTER.asm"
|
||||
;
|
||||
PLATFORM .SET PLT_SCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .SET SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .SET MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
RAMBIAS .SET ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
|
||||
MPGSEL_0 .SET $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_1 .SET $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_2 .SET $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_3 .SET $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGENA .SET $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
|
||||
;
|
||||
Z180_BASE .SET $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
|
||||
Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
|
||||
Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3)
|
||||
Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
|
||||
Z180_TIMER .SET TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
|
||||
;
|
||||
RTCIO .SET $0C ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .SET $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .SET $88 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER
|
||||
;
|
||||
PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
;
|
||||
WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
;
|
||||
FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED)
|
||||
LEDMODE .SET LEDMODE_SC ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .SET $0E ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .SET TRUE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .SET $AA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .SET 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .SET $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .SET $FF ; SSER: STATUS PORT
|
||||
SSERDATA .SET $FF ; SSER: DATA PORT
|
||||
SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
DUARTCNT .SET 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
DUART0BASE .SET $A0 ; DUART 0: BASE ADDRESS OF CHIP
|
||||
DUART0ACFG .SET DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG
|
||||
DUART0BCFG .SET DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG
|
||||
DUART1BASE .SET $40 ; DUART 1: BASE ADDRESS OF CHIP
|
||||
DUART1ACFG .SET DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
|
||||
DUART1BCFG .SET DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
|
||||
;
|
||||
UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .SET 4 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .SET $80 ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .SET $88 ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .SET $A0 ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .SET $A8 ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
ASCIINTS .SET TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
ASCISWAP .SET FALSE ; ASCI: SWAP CHANNELS
|
||||
ASCIBOOT .SET 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
ASCI0CFG .SET DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG
|
||||
ASCI1CFG .SET DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG
|
||||
;
|
||||
Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
;
|
||||
SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .SET 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
SIO0MODE .SET SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .SET 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .SET SER_115200_8N1 ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .SET 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .SET SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1MODE .SET SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO1BASE .SET $84 ; SIO 1: REGISTERS BASE ADR
|
||||
SIO1ACLK .SET 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1ACFG .SET SER_115200_8N1 ; SIO 1A: SERIAL LINE CONFIG
|
||||
SIO1ACTCC .SET -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1BCLK .SET 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1BCFG .SET SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG
|
||||
SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .SET TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .SET TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
;
|
||||
IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .SET IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .SET $10 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .SET $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .SET $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .SET TRUE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .SET TRUE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .SET $20 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .SET SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .SET TRUE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
CHTRACE .SET 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHUSBTRACE .SET 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHSDTRACE .SET 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHCNT .SET 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2)
|
||||
CH0BASE .SET $3E ; CH 0: BASE I/O ADDRESS
|
||||
CH0USBENABLE .SET TRUE ; CH 0: ENABLE USB DISK
|
||||
CH0SDENABLE .SET FALSE ; CH 0: ENABLE SD DISK
|
||||
CH1BASE .SET $3C ; CH 1: BASE I/O ADDRESS
|
||||
CH1USBENABLE .SET TRUE ; CH 1: ENABLE USB DISK
|
||||
CH1SDENABLE .SET FALSE ; CH 1: ENABLE SD DISK
|
||||
;
|
||||
PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
|
||||
LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
LPT0BASE .SET $18 ; LPT 0: REGISTERS BASE ADR
|
||||
LPT1BASE .SET $00 ; LPT 1: REGISTERS BASE ADR
|
||||
;
|
||||
PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
PPACNT .SET 1 ; PPA: NUMBER OF PPA DEVICES (1-2)
|
||||
PPATRACE .SET 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPAMODE .SET PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
|
||||
PPA0BASE .SET LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
PPA1BASE .SET LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
;
|
||||
IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
IMMCNT .SET 1 ; IMM: NUMBER OF IMM DEVICES (1-2)
|
||||
IMMTRACE .SET 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IMMMODE .SET IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
|
||||
IMM0BASE .SET LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
IMM1BASE .SET LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
;
|
||||
SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
SYQCNT .SET 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2)
|
||||
SYQTRACE .SET 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SYQMODE .SET IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
|
||||
SYQ0BASE .SET LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
SYQ1BASE .SET LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
;
|
||||
PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
;
|
||||
UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
;
|
||||
SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
||||
;
|
||||
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .SET AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
||||
;
|
||||
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .SET DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
312
Source/HBIOS/cfg_Z80RETRO.asm
Normal file
312
Source/HBIOS/cfg_Z80RETRO.asm
Normal file
@@ -0,0 +1,312 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: Z80RETRO
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD,
|
||||
; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
|
||||
; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE
|
||||
; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A
|
||||
; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "Z80Retro", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "cfg_MASTER.asm"
|
||||
;
|
||||
PLATFORM .SET PLT_Z80RETRO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .SET 14745600 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .SET SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .SET MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
MPGSEL_0 .SET $60 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_1 .SET $61 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_2 .SET $62 ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_3 .SET $63 ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGENA .SET $64 ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
|
||||
;
|
||||
RTCIO .SET $70 ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .SET $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .SET TRUE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .SET $40 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER (too fast for RomWBW right now)
|
||||
CTCMODE .SET CTCMODE_CTR ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
|
||||
CTCPRE .SET 256 ; PRESCALE CONSTANT (1-256)
|
||||
CTCPRECH .SET 0 ; PRESCALE CHANNEL (0-3)
|
||||
CTCTIMCH .SET 1 ; TIMER CHANNEL (0-3)
|
||||
CTCOSC .SET 7372800 ; CTC CLOCK FREQUENCY
|
||||
;
|
||||
PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
;
|
||||
WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
;
|
||||
FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .SET FALSE ; ENABLES STATUS LED
|
||||
LEDMODE .SET LEDMODE_RTC ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .SET $00 ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .SET 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .SET $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .SET $FF ; SSER: STATUS PORT
|
||||
SSERDATA .SET $FF ; SSER: DATA PORT
|
||||
SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
;
|
||||
UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .SET 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .SET $FF ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .SET $FF ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .SET $FF ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .SET $FF ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .SET FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
;
|
||||
Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
;
|
||||
SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .SET 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
SIO0MODE .SET SIOMODE_Z80R ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .SET CPUOSC/2 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .SET DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .SET CPUOSC/2 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1MODE .SET SIOMODE_Z80R ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO1BASE .SET $84 ; SIO 1: REGISTERS BASE ADR
|
||||
SIO1ACLK .SET CPUOSC/2 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1ACFG .SET DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG
|
||||
SIO1ACTCC .SET -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1BCLK .SET CPUOSC/2 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1BCFG .SET DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG
|
||||
SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .SET TMSMODE_NONE ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .SET TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .SET TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .SET FDMODE_ZETA2 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .SET 1 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
;
|
||||
IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
;
|
||||
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .SET $60 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .SET SDMODE_Z80R ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
;
|
||||
PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
;
|
||||
PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
PPPBASE .SET $60 ; PPP: PPI REGISTERS BASE ADDRESS
|
||||
PPPSDENABLE .SET TRUE ; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
|
||||
PPPSDTRACE .SET 1 ; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPPCONENABLE .SET TRUE ; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
;
|
||||
LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
;
|
||||
PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
;
|
||||
IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
;
|
||||
SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
;
|
||||
PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
PIOSBASE .SET $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
|
||||
;
|
||||
UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
;
|
||||
SN76489ENABLE .SET FALSE ; SN76489 SOUND DRIVER
|
||||
AY38910ENABLE .SET FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER
|
||||
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .SET DMAMODE_NONE ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
282
Source/HBIOS/cfg_ZETA.asm
Normal file
282
Source/HBIOS/cfg_ZETA.asm
Normal file
@@ -0,0 +1,282 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: ZETA
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD,
|
||||
; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
|
||||
; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE
|
||||
; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A
|
||||
; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "Zeta", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "cfg_MASTER.asm"
|
||||
;
|
||||
PLATFORM .SET PLT_ZETA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .SET BIOS_WBW ; BIOS_[WBW|UNA]: HARDWARE BIOS
|
||||
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .SET 8000000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .SET 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .SET SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .SET MM_SBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
MPCL_RAM .SET $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
|
||||
MPCL_ROM .SET $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
|
||||
;
|
||||
RTCIO .SET $70 ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .SET $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT
|
||||
;
|
||||
PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
;
|
||||
WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
;
|
||||
FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .SET FALSE ; ENABLES STATUS LED
|
||||
LEDMODE .SET LEDMODE_RTC ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .SET RTCIO ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .SET 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .SET $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .SET $FF ; SSER: STATUS PORT
|
||||
SSERDATA .SET $FF ; SSER: DATA PORT
|
||||
SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
;
|
||||
UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .SET 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .SET $68 ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .SET $FF ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .SET SER_300_8N1 ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .SET $FF ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .SET $FF ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .SET FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
;
|
||||
Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
;
|
||||
SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
;
|
||||
XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .SET TMSMODE_NONE ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .SET TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .SET TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .SET FDMODE_ZETA ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .SET 1 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
;
|
||||
IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
;
|
||||
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .SET $60 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .SET SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
;
|
||||
PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
;
|
||||
PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
PPPBASE .SET $60 ; PPP: PPI REGISTERS BASE ADDRESS
|
||||
PPPSDENABLE .SET TRUE ; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
|
||||
PPPSDTRACE .SET 1 ; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPPCONENABLE .SET TRUE ; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
;
|
||||
LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
;
|
||||
PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
;
|
||||
IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
;
|
||||
SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
;
|
||||
PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
PIOSBASE .SET $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
|
||||
;
|
||||
UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
;
|
||||
SN76489ENABLE .SET FALSE ; SN76489 SOUND DRIVER
|
||||
AY38910ENABLE .SET FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER
|
||||
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .SET DMAMODE_NONE ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
293
Source/HBIOS/cfg_ZETA2.asm
Normal file
293
Source/HBIOS/cfg_ZETA2.asm
Normal file
@@ -0,0 +1,293 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: ZETA2
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD,
|
||||
; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
|
||||
; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE
|
||||
; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A
|
||||
; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
|
||||
;
|
||||
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
|
||||
;
|
||||
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
|
||||
; |
|
||||
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
|
||||
; |
|
||||
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
|
||||
; |
|
||||
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
|
||||
;
|
||||
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
|
||||
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
|
||||
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
|
||||
; OVERRIDE THESE SETTINGS AS DESIRED.
|
||||
;
|
||||
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
|
||||
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
|
||||
; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
|
||||
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
|
||||
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
|
||||
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
|
||||
;
|
||||
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
|
||||
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
|
||||
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
|
||||
;
|
||||
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
|
||||
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
|
||||
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "Zeta 2", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "cfg_MASTER.asm"
|
||||
;
|
||||
PLATFORM .SET PLT_ZETA2 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .SET 8000000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .SET SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .SET MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
MPGSEL_0 .SET $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_1 .SET $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_2 .SET $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_3 .SET $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGENA .SET $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
|
||||
;
|
||||
RTCIO .SET $70 ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .SET $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .SET TRUE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .SET $20 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .SET TRUE ; ENABLE CTC PERIODIC TIMER
|
||||
CTCMODE .SET CTCMODE_CTR ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
|
||||
CTCPRE .SET 256 ; PRESCALE CONSTANT (1-256)
|
||||
CTCPRECH .SET 0 ; PRESCALE CHANNEL (0-3)
|
||||
CTCTIMCH .SET 1 ; TIMER CHANNEL (0-3)
|
||||
CTCOSC .SET 921600 ; CTC CLOCK FREQUENCY
|
||||
;
|
||||
PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
;
|
||||
WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
;
|
||||
FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .SET FALSE ; ENABLES STATUS LED
|
||||
LEDMODE .SET LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .SET RTCIO ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .SET 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .SET $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .SET $FF ; SSER: STATUS PORT
|
||||
SSERDATA .SET $FF ; SSER: DATA PORT
|
||||
SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
;
|
||||
UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .SET 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .SET $68 ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .SET $FF ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .SET SER_300_8N1 ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .SET $FF ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .SET $FF ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .SET FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
;
|
||||
Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
;
|
||||
SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
;
|
||||
XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .SET TMSMODE_NONE ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .SET TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .SET TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .SET FDMODE_ZETA2 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .SET 1 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
;
|
||||
IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
;
|
||||
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .SET $60 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .SET SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
;
|
||||
PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
;
|
||||
PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
PPPBASE .SET $60 ; PPP: PPI REGISTERS BASE ADDRESS
|
||||
PPPSDENABLE .SET TRUE ; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
|
||||
PPPSDTRACE .SET 1 ; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPPCONENABLE .SET TRUE ; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
;
|
||||
LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
;
|
||||
PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
;
|
||||
IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
;
|
||||
SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
;
|
||||
PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
PIOSBASE .SET $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
|
||||
;
|
||||
UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
;
|
||||
SN76489ENABLE .SET FALSE ; SN76489 SOUND DRIVER
|
||||
AY38910ENABLE .SET FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER
|
||||
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .SET DMAMODE_NONE ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
|
||||
VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
@@ -1,350 +0,0 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW 3.X CONFIGURATION DEFAULTS FOR DUODYNE
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
|
||||
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
|
||||
; UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
|
||||
; FOR THE PLATFORM.
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "Duodyne", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_DUO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .EQU FALSE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .EQU SPD_UNSUP ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .EQU 8000000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .EQU SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
MPGSEL_0 .EQU $50 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_1 .EQU $51 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_2 .EQU $52 ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_3 .EQU $53 ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGENA .EQU $54 ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
|
||||
;
|
||||
RTCIO .EQU $94 ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .EQU TRUE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .EQU $60 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .EQU TRUE ; ENABLE CTC PERIODIC TIMER
|
||||
CTCMODE .EQU CTCMODE_CTR ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
|
||||
CTCPRE .EQU 256 ; PRESCALE CONSTANT (1-256)
|
||||
CTCPRECH .EQU 2 ; PRESCALE CHANNEL (0-3)
|
||||
CTCTIMCH .EQU 3 ; TIMER CHANNEL (0-3)
|
||||
CTCOSC .EQU (7372800/8) ; CTC CLOCK FREQUENCY
|
||||
;
|
||||
PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .EQU $56 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
;
|
||||
WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
;
|
||||
FPLED_ENABLE .EQU TRUE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .EQU $42 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .EQU TRUE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .EQU $42 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .EQU TRUE ; ENABLES STATUS LED
|
||||
LEDMODE .EQU LEDMODE_RTC ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .EQU RTCIO ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .EQU $88 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .EQU TRUE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .EQU $88 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .EQU FALSE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .EQU $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .EQU FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .EQU $FF ; SSER: STATUS PORT
|
||||
SSERDATA .EQU $FF ; SSER: DATA PORT
|
||||
SSERIRDY .EQU %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .EQU FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .EQU %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .EQU FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
;
|
||||
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .EQU 4 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .EQU 7372800 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .EQU $58 ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .EQU $A8 ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .EQU SER_300_8N1 ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .EQU $70 ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .EQU $78 ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
;
|
||||
Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
;
|
||||
SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .EQU 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
SIO0MODE .EQU SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .EQU $60 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .EQU (7372800/4) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .EQU 0 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .EQU (7372800/4) ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .EQU 1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
VDUSIZ .EQU V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
|
||||
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
CVDUMODE .EQU CVDUMODE_MBC ; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
|
||||
CVDUMON .EQU CVDUMON_CGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
|
||||
GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .EQU TRUE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .EQU TMSMODE_DUO ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .EQU TRUE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VGASIZ .EQU V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
|
||||
VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .EQU FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .EQU TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .EQU TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
;
|
||||
FDENABLE .EQU TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .EQU FDMODE_DUO ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
RFCNT .EQU 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
|
||||
;
|
||||
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .EQU IDEMODE_DIO ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .EQU $20 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .EQU $20 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .EQU $28 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .EQU FALSE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .EQU FALSE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .EQU TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .EQU $88 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .EQU $20 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .EQU $14 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .EQU TRUE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
CHTRACE .EQU 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHUSBTRACE .EQU 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHSDTRACE .EQU 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHCNT .EQU 1 ; CH: NUMBER OF BOARDS TO DETECT (1-2)
|
||||
CH0BASE .EQU $4E ; CH 0: BASE I/O ADDRESS
|
||||
CH0USBENABLE .EQU TRUE ; CH 0: ENABLE USB DISK
|
||||
CH0SDENABLE .EQU TRUE ; CH 0: ENABLE SD DISK
|
||||
CH1BASE .EQU $FF ; CH 1: BASE I/O ADDRESS
|
||||
CH1USBENABLE .EQU FALSE ; CH 1: ENABLE USB DISK
|
||||
CH1SDENABLE .EQU FALSE ; CH 1: ENABLE SD DISK
|
||||
;
|
||||
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
ESPCONENABLE .EQU TRUE ; ESP: ENABLE ESP32 CONSOLE IO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
HDSKTRACE .EQU 1 ; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
;
|
||||
PIOENABLE .EQU TRUE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .EQU $68 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .EQU $6C ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .EQU TRUE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
LPTMODE .EQU LPTMODE_SPP ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
|
||||
LPTCNT .EQU 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
LPTTRACE .EQU 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
LPT0BASE .EQU $48 ; LPT 0: REGISTERS BASE ADR
|
||||
LPT1BASE .EQU $EC ; LPT 1: REGISTERS BASE ADR
|
||||
;
|
||||
PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
PPACNT .EQU 1 ; PPA: NUMBER OF PPA DEVICES (1-2)
|
||||
PPATRACE .EQU 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPAMODE .EQU PPAMODE_SPP ; PPA: DRIVER MODE: PPAMODE_[NONE|MG014]
|
||||
PPA0BASE .EQU LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
PPA1BASE .EQU LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
;
|
||||
IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
IMMCNT .EQU 1 ; IMM: NUMBER OF IMM DEVICES (1-2)
|
||||
IMMTRACE .EQU 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IMMMODE .EQU IMMMODE_SPP ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
|
||||
IMM0BASE .EQU LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
IMM1BASE .EQU LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
;
|
||||
SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
SYQCNT .EQU 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2)
|
||||
SYQTRACE .EQU 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SYQMODE .EQU IMMMODE_SPP ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
|
||||
SYQ0BASE .EQU LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
SYQ1BASE .EQU LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
;
|
||||
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO4BASE .EQU $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
|
||||
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIOZBASE .EQU $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
|
||||
PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
PIOSBASE .EQU $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
|
||||
;
|
||||
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
UFBASE .EQU $0C ; UF: REGISTERS BASE ADR
|
||||
;
|
||||
SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .EQU SNMODE_DUO ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
|
||||
;
|
||||
AY38910ENABLE .EQU TRUE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .EQU AYMODE_DUO ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
||||
;
|
||||
SPKENABLE .EQU TRUE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .EQU TRUE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .EQU $40 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .EQU DMAMODE_DUO ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
@@ -1,330 +0,0 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW 3.X CONFIGURATION DEFAULTS FOR DYNO
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
|
||||
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
|
||||
; UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
|
||||
; FOR THE PLATFORM.
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "Dyno", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_DYNO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .EQU SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
RAMBIAS .EQU ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
|
||||
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
|
||||
;
|
||||
Z180_BASE .EQU $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
|
||||
Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
|
||||
Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3)
|
||||
Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
|
||||
Z180_TIMER .EQU TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
|
||||
;
|
||||
RTCIO .EQU $0C ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER
|
||||
;
|
||||
PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
;
|
||||
WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
;
|
||||
FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED)
|
||||
LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .EQU FALSE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .EQU $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .EQU FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .EQU FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .EQU TRUE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .EQU $FF ; SSER: STATUS PORT
|
||||
SSERDATA .EQU $FF ; SSER: DATA PORT
|
||||
SSERIRDY .EQU %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .EQU FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .EQU %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .EQU FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
DUARTCNT .EQU 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
DUART0BASE .EQU $A0 ; DUART 0: BASE ADDRESS OF CHIP
|
||||
DUART0ACFG .EQU DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG
|
||||
DUART0BCFG .EQU DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG
|
||||
DUART1BASE .EQU $40 ; DUART 1: BASE ADDRESS OF CHIP
|
||||
DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
|
||||
DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
|
||||
;
|
||||
UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .EQU 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .EQU $FF ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .EQU $FF ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .EQU DEFSERCFG ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .EQU $FF ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .EQU $FF ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
ASCISWAP .EQU FALSE ; ASCI: SWAP CHANNELS
|
||||
ASCIBOOT .EQU 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG
|
||||
ASCI1CFG .EQU DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG
|
||||
;
|
||||
Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
;
|
||||
SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .EQU SER_115200_8N1 ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .EQU 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .EQU SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR
|
||||
SIO1ACLK .EQU 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1ACFG .EQU SER_115200_8N1 ; SIO 1A: SERIAL LINE CONFIG
|
||||
SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1BCLK .EQU 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1BCFG .EQU SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG
|
||||
SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .EQU TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .EQU FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .EQU FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .EQU TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .EQU TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .EQU FDMODE_DYNO ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
;
|
||||
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .EQU IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .EQU $10 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .EQU $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .EQU $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .EQU TRUE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .EQU TRUE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .EQU $4C ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
;
|
||||
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
;
|
||||
PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
;
|
||||
IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
;
|
||||
SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
;
|
||||
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
;
|
||||
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
;
|
||||
SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .EQU SNMODE_NONE ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
||||
;
|
||||
AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .EQU AYMODE_NONE ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
||||
;
|
||||
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .EQU DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
@@ -1,362 +0,0 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW 2.X CONFIGURATION DEFAULTS FOR SC Z180 VARIANTS (SC126, SC130, ETC.)
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
|
||||
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
|
||||
; UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
|
||||
; FOR THE PLATFORM.
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "MiniITX"
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_EPITX ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .EQU SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
RAMBIAS .EQU ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
|
||||
;
|
||||
Z180_BASE .EQU $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
|
||||
Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
|
||||
Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3)
|
||||
Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
|
||||
Z180_TIMER .EQU TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
|
||||
;
|
||||
RTCIO .EQU $0C ; RTC LATCH REGISTER ADR - TODO
|
||||
;
|
||||
KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER
|
||||
;
|
||||
PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
;
|
||||
WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
;
|
||||
FPENABLE .EQU FALSE ; ENABLES FRONT PANEL SWITCHES
|
||||
FPBASE .EQU $00 ; FRONT PANEL I/O PORT BASE ADDRESS
|
||||
DIAGENABLE .EQU TRUE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
|
||||
DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS
|
||||
DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
|
||||
;
|
||||
FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .EQU FALSE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED)
|
||||
LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .EQU FALSE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .EQU $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .EQU FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
; TODO - ADD PS/2 BITBANGER
|
||||
VDAEMU_SERKBD .EQU $00 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .EQU FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .EQU $FF ; SSER: STATUS PORT
|
||||
SSERDATA .EQU $FF ; SSER: DATA PORT
|
||||
SSERIRDY .EQU %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .EQU FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .EQU %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .EQU FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
DUARTCNT .EQU 2 ; DUART: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
DUART0BASE .EQU $A0 ; DUART 0: BASE ADDRESS OF CHIP
|
||||
DUART0ACFG .EQU DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG
|
||||
DUART0BCFG .EQU DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG
|
||||
DUART1BASE .EQU $40 ; DUART 1: BASE ADDRESS OF CHIP
|
||||
DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
|
||||
DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
|
||||
;
|
||||
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .EQU 2 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .EQU $A0 ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .EQU $A8 ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .EQU DEFSERCFG ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .EQU $FF ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .EQU $FF ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
ASCISWAP .EQU FALSE ; ASCI: SWAP CHANNELS
|
||||
ASCIBOOT .EQU 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG
|
||||
ASCI1CFG .EQU DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG
|
||||
;
|
||||
Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
;
|
||||
SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .EQU SER_115200_8N1 ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .EQU 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .EQU SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR
|
||||
SIO1ACLK .EQU 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1ACFG .EQU SER_115200_8N1 ; SIO 1A: SERIAL LINE CONFIG
|
||||
SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1BCLK .EQU 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1BCFG .EQU SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG
|
||||
SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .EQU TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .EQU FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .EQU FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .EQU TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .EQU TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .EQU TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .EQU FDMODE_EPFDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
;
|
||||
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .EQU IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .EQU $10 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .EQU $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .EQU $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .EQU TRUE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .EQU TRUE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .EQU $20 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .EQU SDMODE_EPITX ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .EQU $40 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
|
||||
SDTRACE .EQU 2 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
CHTRACE .EQU 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHUSBTRACE .EQU 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHSDTRACE .EQU 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHCNT .EQU 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2)
|
||||
CH0BASE .EQU $3E ; CH 0: BASE I/O ADDRESS
|
||||
CH0USBENABLE .EQU TRUE ; CH 0: ENABLE USB DISK
|
||||
CH0SDENABLE .EQU FALSE ; CH 0: ENABLE SD DISK
|
||||
CH1BASE .EQU $3C ; CH 1: BASE I/O ADDRESS
|
||||
CH1USBENABLE .EQU TRUE ; CH 1: ENABLE USB DISK
|
||||
CH1SDENABLE .EQU FALSE ; CH 1: ENABLE SD DISK
|
||||
;
|
||||
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
LPTMODE .EQU LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
|
||||
LPTCNT .EQU 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
LPTTRACE .EQU 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
LPT0BASE .EQU $0C ; LPT 0: REGISTERS BASE ADR
|
||||
LPT1BASE .EQU $00 ; LPT 1: REGISTERS BASE ADR
|
||||
;
|
||||
PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
PPACNT .EQU 1 ; PPA: NUMBER OF PPA DEVICES (1-2)
|
||||
PPATRACE .EQU 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPAMODE .EQU PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
|
||||
PPA0BASE .EQU LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
PPA1BASE .EQU LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
;
|
||||
IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
IMMCNT .EQU 1 ; IMM: NUMBER OF IMM DEVICES (1-2)
|
||||
IMMTRACE .EQU 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IMMMODE .EQU IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
|
||||
IMM0BASE .EQU LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
IMM1BASE .EQU LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
;
|
||||
SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
SYQCNT .EQU 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2)
|
||||
SYQTRACE .EQU 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SYQMODE .EQU IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
|
||||
SYQ0BASE .EQU LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
SYQ1BASE .EQU LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
;
|
||||
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
;
|
||||
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
;
|
||||
SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .EQU SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
||||
;
|
||||
AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .EQU AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
||||
;
|
||||
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .EQU DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
@@ -1,365 +0,0 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW 3.X CONFIGURATION DEFAULTS FOR S100 FPGA Z80
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
|
||||
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
|
||||
; UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
|
||||
; FOR THE PLATFORM.
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "S100 FPGA Z80", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_FZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .EQU 8000000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .EQU SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .EQU 0 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
|
||||
;
|
||||
RTCIO .EQU $C0 ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER
|
||||
CTCMODE .EQU CTCMODE_TIM16 ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
|
||||
CTCPRE .EQU 256 ; PRESCALE CONSTANT (1-256)
|
||||
CTCPRECH .EQU 2 ; PRESCALE CHANNEL (0-3)
|
||||
CTCTIMCH .EQU 3 ; TIMER CHANNEL (0-3)
|
||||
CTCOSC .EQU CPUOSC ; CTC CLOCK FREQUENCY
|
||||
;
|
||||
PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
SKZDIV .EQU DIV_1 ; UART CLK (CLK2) DIVIDER FOR Z80-512K
|
||||
;
|
||||
WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
WDOGIO .EQU $6E ; WATCHDOG REGISTER ADR
|
||||
;
|
||||
FPLED_ENABLE .EQU TRUE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .EQU $FF ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED)
|
||||
LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .EQU FALSE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .EQU $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .EQU FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .EQU FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .EQU TRUE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .EQU TRUE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .EQU $34 ; SSER: STATUS PORT
|
||||
SSERDATA .EQU $35 ; SSER: DATA PORT
|
||||
SSERIRDY .EQU %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .EQU FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .EQU %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .EQU TRUE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
DUARTCNT .EQU 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
DUART0BASE .EQU $A0 ; DUART 0: BASE ADDRESS OF CHIP
|
||||
DUART0ACFG .EQU DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG
|
||||
DUART0BCFG .EQU DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG
|
||||
DUART1BASE .EQU $40 ; DUART 1: BASE ADDRESS OF CHIP
|
||||
DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
|
||||
DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
|
||||
;
|
||||
UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .EQU 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .EQU $FF ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .EQU $FF ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .EQU DEFSERCFG ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .EQU $FF ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .EQU $FF ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
;
|
||||
Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
ACIADEBUG .EQU FALSE ; ACIA: ENABLE DEBUG OUTPUT
|
||||
ACIACNT .EQU 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
ACIA0BASE .EQU $80 ; ACIA 0: REGISTERS BASE ADR
|
||||
ACIA0CLK .EQU CPUOSC ; ACIA 0: OSC FREQ IN HZ
|
||||
ACIA0DIV .EQU 1 ; ACIA 0: SERIAL CLOCK DIVIDER
|
||||
ACIA0CFG .EQU DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
ACIA1BASE .EQU $40 ; ACIA 1: REGISTERS BASE ADR
|
||||
ACIA1CLK .EQU CPUOSC ; ACIA 1: OSC FREQ IN HZ
|
||||
ACIA1DIV .EQU 1 ; ACIA 1: SERIAL CLOCK DIVIDER
|
||||
ACIA1CFG .EQU DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .EQU CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR
|
||||
SIO1ACLK .EQU CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1ACFG .EQU DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG
|
||||
SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1BCLK .EQU CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1BCFG .EQU DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG
|
||||
SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .EQU TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .EQU FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .EQU TRUE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .EQU TRUE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .EQU FALSE ; MD: ENABLE ROM DISK
|
||||
MDRAM .EQU TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
;
|
||||
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .EQU IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .EQU $10 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .EQU $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .EQU $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .EQU TRUE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .EQU TRUE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .EQU TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .EQU $30 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .EQU SDMODE_FZ80 ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .EQU 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
CHTRACE .EQU 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHUSBTRACE .EQU 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHSDTRACE .EQU 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHCNT .EQU 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2)
|
||||
CH0BASE .EQU $3E ; CH 0: BASE I/O ADDRESS
|
||||
CH0USBENABLE .EQU TRUE ; CH 0: ENABLE USB DISK
|
||||
CH0SDENABLE .EQU FALSE ; CH 0: ENABLE SD DISK
|
||||
CH1BASE .EQU $3C ; CH 1: BASE I/O ADDRESS
|
||||
CH1USBENABLE .EQU TRUE ; CH 1: ENABLE USB DISK
|
||||
CH1SDENABLE .EQU FALSE ; CH 1: ENABLE SD DISK
|
||||
;
|
||||
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
LPTMODE .EQU LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
|
||||
LPTCNT .EQU 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
LPTTRACE .EQU 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
LPT0BASE .EQU $0C ; LPT 0: REGISTERS BASE ADR
|
||||
LPT1BASE .EQU $00 ; LPT 1: REGISTERS BASE ADR
|
||||
;
|
||||
PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
PPACNT .EQU 1 ; PPA: NUMBER OF PPA DEVICES (1-2)
|
||||
PPATRACE .EQU 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPAMODE .EQU PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
|
||||
PPA0BASE .EQU LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
PPA1BASE .EQU LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
;
|
||||
IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
IMMCNT .EQU 1 ; IMM: NUMBER OF IMM DEVICES (1-2)
|
||||
IMMTRACE .EQU 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IMMMODE .EQU IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
|
||||
IMM0BASE .EQU LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
IMM1BASE .EQU LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
;
|
||||
SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
SYQCNT .EQU 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2)
|
||||
SYQTRACE .EQU 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SYQMODE .EQU IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
|
||||
SYQ0BASE .EQU LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
SYQ1BASE .EQU LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
;
|
||||
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
;
|
||||
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
;
|
||||
SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .EQU SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
||||
;
|
||||
AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .EQU AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
||||
;
|
||||
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .EQU DMAMODE_RC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
@@ -1,362 +0,0 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW 3.X CONFIGURATION DEFAULTS FOR GENESIS MODULES STD BUS BASED Z180 VARIANTS
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
|
||||
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
|
||||
; UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
|
||||
; FOR THE PLATFORM.
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "GM STD BUS Z180", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_GMZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
|
||||
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .EQU SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
RAMBIAS .EQU ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
|
||||
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
|
||||
;
|
||||
Z180_BASE .EQU $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
|
||||
Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
|
||||
Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3)
|
||||
Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
|
||||
Z180_TIMER .EQU TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
|
||||
;
|
||||
RTCIO .EQU $84 ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER
|
||||
;
|
||||
PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
;
|
||||
WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
;
|
||||
FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .EQU FALSE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED)
|
||||
LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .EQU FALSE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .EQU FALSE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .EQU $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .EQU TRUE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
GM7303BASE .EQU $30 ; BASE ADDRESS FOR GM3703 BOARD
|
||||
GM7303DSKACT .EQU TRUE ; ENABLE DISK ACTIVITY OF GM7303 LCD DISPLAY
|
||||
;
|
||||
BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .EQU TRUE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .EQU $FF ; SSER: STATUS PORT
|
||||
SSERDATA .EQU $FF ; SSER: DATA PORT
|
||||
SSERIRDY .EQU %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .EQU FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .EQU %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .EQU FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
DUARTCNT .EQU 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
DUART0BASE .EQU $A0 ; DUART 0: BASE ADDRESS OF CHIP
|
||||
DUART0ACFG .EQU DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG
|
||||
DUART0BCFG .EQU DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG
|
||||
DUART1BASE .EQU $40 ; DUART 1: BASE ADDRESS OF CHIP
|
||||
DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
|
||||
DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
|
||||
;
|
||||
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .EQU 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .EQU $80 ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .EQU $88 ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .EQU DEFSERCFG ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .EQU $A0 ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .EQU $A8 ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
ASCISWAP .EQU FALSE ; ASCI: SWAP CHANNELS
|
||||
ASCIBOOT .EQU 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG
|
||||
ASCI1CFG .EQU DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG
|
||||
;
|
||||
Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
;
|
||||
SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .EQU SER_115200_8N1 ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .EQU 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .EQU SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR
|
||||
SIO1ACLK .EQU 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1ACFG .EQU SER_115200_8N1 ; SIO 1A: SERIAL LINE CONFIG
|
||||
SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1BCLK .EQU 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1BCFG .EQU SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG
|
||||
SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .EQU TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .EQU FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .EQU FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .EQU TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .EQU TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
;
|
||||
IDEENABLE .EQU TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .EQU IDEMODE_GIDE ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
|
||||
IDE0BASE .EQU $20 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .EQU $20 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .EQU $28 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .EQU TRUE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .EQU TRUE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
|
||||
IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
|
||||
IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .EQU $20 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .EQU SDMODE_GM ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM]
|
||||
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
CHTRACE .EQU 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHUSBTRACE .EQU 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHSDTRACE .EQU 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHCNT .EQU 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2)
|
||||
CH0BASE .EQU $3E ; CH 0: BASE I/O ADDRESS
|
||||
CH0USBENABLE .EQU TRUE ; CH 0: ENABLE USB DISK
|
||||
CH0SDENABLE .EQU FALSE ; CH 0: ENABLE SD DISK
|
||||
CH1BASE .EQU $3C ; CH 1: BASE I/O ADDRESS
|
||||
CH1USBENABLE .EQU TRUE ; CH 1: ENABLE USB DISK
|
||||
CH1SDENABLE .EQU FALSE ; CH 1: ENABLE SD DISK
|
||||
;
|
||||
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
LPTMODE .EQU LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
|
||||
LPTCNT .EQU 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
LPTTRACE .EQU 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
LPT0BASE .EQU $18 ; LPT 0: REGISTERS BASE ADR
|
||||
LPT1BASE .EQU $00 ; LPT 1: REGISTERS BASE ADR
|
||||
;
|
||||
PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
PPACNT .EQU 1 ; PPA: NUMBER OF PPA DEVICES (1-2)
|
||||
PPATRACE .EQU 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPAMODE .EQU PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
|
||||
PPA0BASE .EQU LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
PPA1BASE .EQU LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
;
|
||||
IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
IMMCNT .EQU 1 ; IMM: NUMBER OF IMM DEVICES (1-2)
|
||||
IMMTRACE .EQU 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IMMMODE .EQU IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
|
||||
IMM0BASE .EQU LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
IMM1BASE .EQU LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
;
|
||||
SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
SYQCNT .EQU 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2)
|
||||
SYQTRACE .EQU 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SYQMODE .EQU IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
|
||||
SYQ0BASE .EQU LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
SYQ1BASE .EQU LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
;
|
||||
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
;
|
||||
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
;
|
||||
SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .EQU SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
||||
;
|
||||
AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .EQU AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
||||
;
|
||||
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .EQU DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
@@ -1,355 +0,0 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW 3.X CONFIGURATION DEFAULTS FOR HEATHKIT Z80
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
|
||||
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
|
||||
; UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
|
||||
; FOR THE PLATFORM.
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "HEATHKIT", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_HEATH ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .EQU 16384000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .EQU 1 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .EQU SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
|
||||
;
|
||||
RTCIO .EQU $C0 ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER
|
||||
CTCMODE .EQU CTCMODE_TIM16 ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
|
||||
CTCPRE .EQU 256 ; PRESCALE CONSTANT (1-256)
|
||||
CTCPRECH .EQU 2 ; PRESCALE CHANNEL (0-3)
|
||||
CTCTIMCH .EQU 3 ; TIMER CHANNEL (0-3)
|
||||
CTCOSC .EQU CPUOSC ; CTC CLOCK FREQUENCY
|
||||
;
|
||||
PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
SKZDIV .EQU DIV_1 ; UART CLK (CLK2) DIVIDER FOR Z80-512K
|
||||
;
|
||||
WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
WDOGIO .EQU $6E ; WATCHDOG REGISTER ADR
|
||||
;
|
||||
FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .EQU FALSE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED)
|
||||
LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .EQU FALSE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .EQU TRUE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .EQU FALSE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .EQU $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .EQU FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .EQU FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .EQU $FF ; SSER: STATUS PORT
|
||||
SSERDATA .EQU $FF ; SSER: DATA PORT
|
||||
SSERIRDY .EQU %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .EQU FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .EQU %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .EQU FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
DUARTCNT .EQU 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
DUART0BASE .EQU $A0 ; DUART 0: BASE ADDRESS OF CHIP
|
||||
DUART0ACFG .EQU DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG
|
||||
DUART0BCFG .EQU DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG
|
||||
DUART1BASE .EQU $40 ; DUART 1: BASE ADDRESS OF CHIP
|
||||
DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
|
||||
DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
|
||||
;
|
||||
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .EQU 4 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .EQU $E8 ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .EQU $E0 ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .EQU DEFSERCFG ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .EQU $D8 ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .EQU $D0 ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
;
|
||||
Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
ACIADEBUG .EQU FALSE ; ACIA: ENABLE DEBUG OUTPUT
|
||||
ACIACNT .EQU 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
ACIA0BASE .EQU $80 ; ACIA 0: REGISTERS BASE ADR
|
||||
ACIA0CLK .EQU CPUOSC ; ACIA 0: OSC FREQ IN HZ
|
||||
ACIA0DIV .EQU 1 ; ACIA 0: SERIAL CLOCK DIVIDER
|
||||
ACIA0CFG .EQU DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
ACIA1BASE .EQU $40 ; ACIA 1: REGISTERS BASE ADR
|
||||
ACIA1CLK .EQU CPUOSC ; ACIA 1: OSC FREQ IN HZ
|
||||
ACIA1DIV .EQU 1 ; ACIA 1: SERIAL CLOCK DIVIDER
|
||||
ACIA1CFG .EQU DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .EQU CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR
|
||||
SIO1ACLK .EQU CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1ACFG .EQU DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG
|
||||
SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1BCLK .EQU CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1BCFG .EQU DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG
|
||||
SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .EQU TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .EQU TRUE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .EQU FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .EQU TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .EQU TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .EQU TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
;
|
||||
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .EQU IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .EQU $10 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .EQU $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .EQU $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .EQU TRUE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .EQU TRUE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .EQU TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .EQU $20 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .EQU 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
;
|
||||
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
LPTMODE .EQU LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
|
||||
LPTCNT .EQU 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
LPTTRACE .EQU 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
LPT0BASE .EQU $0C ; LPT 0: REGISTERS BASE ADR
|
||||
LPT1BASE .EQU $00 ; LPT 1: REGISTERS BASE ADR
|
||||
;
|
||||
PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
PPACNT .EQU 1 ; PPA: NUMBER OF PPA DEVICES (1-2)
|
||||
PPATRACE .EQU 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPAMODE .EQU PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
|
||||
PPA0BASE .EQU LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
PPA1BASE .EQU LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
;
|
||||
IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
IMMCNT .EQU 1 ; IMM: NUMBER OF IMM DEVICES (1-2)
|
||||
IMMTRACE .EQU 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IMMMODE .EQU IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
|
||||
IMM0BASE .EQU LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
IMM1BASE .EQU LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
;
|
||||
SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
SYQCNT .EQU 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2)
|
||||
SYQTRACE .EQU 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SYQMODE .EQU IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
|
||||
SYQ0BASE .EQU LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
SYQ1BASE .EQU LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
;
|
||||
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
;
|
||||
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
;
|
||||
SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .EQU SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
||||
;
|
||||
AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .EQU AYMODE_MSX ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
||||
;
|
||||
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .EQU DMAMODE_RC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
@@ -1,337 +0,0 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW 3.X CONFIGURATION DEFAULTS FOR MBC
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
|
||||
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
|
||||
; UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
|
||||
; FOR THE PLATFORM.
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "Nhyodyne", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_MBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .EQU SPD_HILO ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .EQU SPD_LOW ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .EQU 8000000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .EQU SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .EQU MM_MBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
|
||||
MPCL_ROM .EQU $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
|
||||
;
|
||||
RTCIO .EQU $70 ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .EQU TRUE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .EQU $B0 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .EQU TRUE ; ENABLE CTC PERIODIC TIMER
|
||||
CTCMODE .EQU CTCMODE_CTR ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
|
||||
CTCPRE .EQU 256 ; PRESCALE CONSTANT (1-256)
|
||||
CTCPRECH .EQU 2 ; PRESCALE CHANNEL (0-3)
|
||||
CTCTIMCH .EQU 3 ; TIMER CHANNEL (0-3)
|
||||
CTCOSC .EQU (4915200/8) ; CTC CLOCK FREQUENCY
|
||||
;
|
||||
PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
;
|
||||
WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
;
|
||||
FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .EQU TRUE ; ENABLES STATUS LED
|
||||
LEDMODE .EQU LEDMODE_RTC ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .EQU RTCIO ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .EQU FALSE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .EQU $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .EQU FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .EQU $FF ; SSER: STATUS PORT
|
||||
SSERDATA .EQU $FF ; SSER: DATA PORT
|
||||
SSERIRDY .EQU %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .EQU FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .EQU %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .EQU FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
;
|
||||
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .EQU 3 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .EQU $68 ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .EQU $80 ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .EQU SER_300_8N1 ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .EQU $88 ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .EQU $FF ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
;
|
||||
Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
;
|
||||
SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .EQU 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
SIO0MODE .EQU SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .EQU $B0 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .EQU (4915200/8) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .EQU (4915200/8) ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
VDUSIZ .EQU V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
|
||||
CVDUENABLE .EQU TRUE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
CVDUMODE .EQU CVDUMODE_MBC ; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
|
||||
CVDUMON .EQU CVDUMON_CGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
|
||||
GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .EQU TRUE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .EQU TMSMODE_MBC ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .EQU TRUE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VGASIZ .EQU V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
|
||||
VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .EQU FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .EQU TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .EQU TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
;
|
||||
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .EQU FDMODE_MBC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
RFCNT .EQU 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
|
||||
;
|
||||
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .EQU IDEMODE_DIO ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .EQU $20 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .EQU $20 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .EQU $28 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .EQU FALSE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .EQU FALSE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .EQU $60 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .EQU $20 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .EQU $14 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .EQU SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
;
|
||||
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
ESPCONENABLE .EQU TRUE ; ESP: ENABLE ESP32 CONSOLE IO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
HDSKTRACE .EQU 1 ; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
;
|
||||
PIOENABLE .EQU TRUE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
LPTMODE .EQU LPTMODE_SPP ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
|
||||
LPTCNT .EQU 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
LPTTRACE .EQU 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
LPT0BASE .EQU $E8 ; LPT 0: REGISTERS BASE ADR
|
||||
LPT1BASE .EQU $EC ; LPT 1: REGISTERS BASE ADR
|
||||
;
|
||||
PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
PPACNT .EQU 1 ; PPA: NUMBER OF PPA DEVICES (1-2)
|
||||
PPATRACE .EQU 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPAMODE .EQU PPAMODE_SPP ; PPA: DRIVER MODE: PPAMODE_[NONE|MG014]
|
||||
PPA0BASE .EQU LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
PPA1BASE .EQU LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
;
|
||||
IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
IMMCNT .EQU 1 ; IMM: NUMBER OF IMM DEVICES (1-2)
|
||||
IMMTRACE .EQU 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IMMMODE .EQU IMMMODE_SPP ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
|
||||
IMM0BASE .EQU LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
IMM1BASE .EQU LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
;
|
||||
SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
SYQCNT .EQU 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2)
|
||||
SYQTRACE .EQU 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SYQMODE .EQU IMMMODE_SPP ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
|
||||
SYQ0BASE .EQU LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
SYQ1BASE .EQU LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
;
|
||||
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO4BASE .EQU $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
|
||||
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIOZBASE .EQU $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
|
||||
PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
PIOSBASE .EQU $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
|
||||
;
|
||||
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
UFBASE .EQU $0C ; UF: REGISTERS BASE ADR
|
||||
;
|
||||
SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .EQU SNMODE_NONE ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
||||
;
|
||||
AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .EQU AYMODE_MBC ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
||||
;
|
||||
SPKENABLE .EQU TRUE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .EQU DMAMODE_MBC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
@@ -1,333 +0,0 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW 3.X CONFIGURATION FOR MARK IV
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
|
||||
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
|
||||
; UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
|
||||
; FOR THE PLATFORM.
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "Mark IV", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_MK4 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .EQU SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
RAMBIAS .EQU ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
|
||||
;
|
||||
Z180_BASE .EQU $40 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
|
||||
Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
|
||||
Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3)
|
||||
Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
|
||||
Z180_TIMER .EQU TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
|
||||
;
|
||||
MK4_IDE .EQU $80 ; MK4: IDE REGISTERS BASE ADR
|
||||
MK4_XAR .EQU $88 ; MK4: EXTERNAL ADDRESS REGISTER (XAR) ADR
|
||||
MK4_SD .EQU $89 ; MK4: SD CARD CONTROL REGISTER ADR
|
||||
MK4_RTC .EQU $8A ; MK4: RTC LATCH REGISTER ADR
|
||||
;
|
||||
RTCIO .EQU MK4_RTC ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .EQU $B0 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER
|
||||
;
|
||||
PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
;
|
||||
WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
;
|
||||
FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED)
|
||||
LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .EQU FALSE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .EQU $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .EQU FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .EQU $FF ; SSER: STATUS PORT
|
||||
SSERDATA .EQU $FF ; SSER: DATA PORT
|
||||
SSERIRDY .EQU %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .EQU FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .EQU %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .EQU FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
;
|
||||
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .EQU 6 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .EQU TRUE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .EQU $18 ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .EQU $80 ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .EQU SER_300_8N1 ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .EQU $C0 ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .EQU $C8 ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .EQU $D0 ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .EQU $D8 ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
ASCISWAP .EQU FALSE ; ASCI: SWAP CHANNELS
|
||||
ASCIBOOT .EQU 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG
|
||||
ASCI1CFG .EQU DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG
|
||||
;
|
||||
Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
;
|
||||
SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .EQU 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
SIO0MODE .EQU SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .EQU $B0 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .EQU (4915200/8) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .EQU (4915200/8) ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
VDUSIZ .EQU V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
|
||||
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
CVDUMODE .EQU CVDUMODE_ECB ; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
|
||||
CVDUMON .EQU CVDUMON_EGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
|
||||
GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .EQU TMSMODE_SCG ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .EQU FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VGASIZ .EQU V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
|
||||
VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .EQU FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .EQU TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .EQU TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .EQU FDMODE_DIDE ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
RFCNT .EQU 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
|
||||
;
|
||||
IDEENABLE .EQU TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .EQU IDEMODE_MK4 ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .EQU $80 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .EQU $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .EQU $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .EQU TRUE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .EQU TRUE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .EQU IDEMODE_DIDE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .EQU $20 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .EQU $28 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .EQU $28 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .EQU FALSE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .EQU FALSE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .EQU IDEMODE_DIDE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .EQU $30 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .EQU $38 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .EQU $38 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .EQU FALSE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .EQU FALSE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .EQU 2 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .EQU $14 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .EQU $20 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .EQU SDMODE_MK4 ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .EQU TRUE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
;
|
||||
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
PPPBASE .EQU $60 ; PPP: PPI REGISTERS BASE ADDRESS
|
||||
PPPSDENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
|
||||
PPPSDTRACE .EQU 1 ; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPPCONENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
LPTMODE .EQU LPTMODE_NONE ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
|
||||
LPTCNT .EQU 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
LPTTRACE .EQU 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
LPT0BASE .EQU $E8 ; LPT 0: REGISTERS BASE ADR
|
||||
LPT1BASE .EQU $EC ; LPT 1: REGISTERS BASE ADR
|
||||
;
|
||||
PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
;
|
||||
IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
;
|
||||
SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
;
|
||||
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO4BASE .EQU $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
|
||||
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIOZBASE .EQU $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
|
||||
PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
PIOSBASE .EQU $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
|
||||
;
|
||||
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
UFBASE .EQU $0C ; UF: REGISTERS BASE ADR
|
||||
;
|
||||
SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .EQU SNMODE_VGM ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
||||
;
|
||||
AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .EQU AYMODE_SCG ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
||||
;
|
||||
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .EQU DMAMODE_ECB ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
@@ -1,360 +0,0 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW 3.X CONFIGURATION DEFAULTS FOR MONSPUTER Z80
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
|
||||
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
|
||||
; UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
|
||||
; FOR THE PLATFORM.
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "Monsputer", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_MON ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .EQU 4000000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .EQU SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .EQU MM_MON ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
;
|
||||
RTCIO .EQU $C0 ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER
|
||||
CTCMODE .EQU CTCMODE_TIM16 ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
|
||||
CTCPRE .EQU 256 ; PRESCALE CONSTANT (1-256)
|
||||
CTCPRECH .EQU 2 ; PRESCALE CHANNEL (0-3)
|
||||
CTCTIMCH .EQU 3 ; TIMER CHANNEL (0-3)
|
||||
CTCOSC .EQU CPUOSC ; CTC CLOCK FREQUENCY
|
||||
;
|
||||
PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
SKZDIV .EQU DIV_1 ; UART CLK (CLK2) DIVIDER FOR Z80-512K
|
||||
;
|
||||
WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
WDOGIO .EQU $6E ; WATCHDOG REGISTER ADR
|
||||
;
|
||||
FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED)
|
||||
LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .EQU FALSE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .EQU $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .EQU FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .EQU FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .EQU $FF ; SSER: STATUS PORT
|
||||
SSERDATA .EQU $FF ; SSER: DATA PORT
|
||||
SSERIRDY .EQU %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .EQU FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .EQU %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .EQU FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
DUARTCNT .EQU 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
DUART0BASE .EQU $A0 ; DUART 0: BASE ADDRESS OF CHIP
|
||||
DUART0ACFG .EQU DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG
|
||||
DUART0BCFG .EQU DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG
|
||||
DUART1BASE .EQU $40 ; DUART 1: BASE ADDRESS OF CHIP
|
||||
DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
|
||||
DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
|
||||
;
|
||||
UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .EQU 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .EQU $FF ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .EQU $FF ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .EQU DEFSERCFG ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .EQU $FF ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .EQU $FF ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
;
|
||||
Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
ACIADEBUG .EQU FALSE ; ACIA: ENABLE DEBUG OUTPUT
|
||||
ACIACNT .EQU 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
ACIA0BASE .EQU $80 ; ACIA 0: REGISTERS BASE ADR
|
||||
ACIA0CLK .EQU CPUOSC ; ACIA 0: OSC FREQ IN HZ
|
||||
ACIA0DIV .EQU 1 ; ACIA 0: SERIAL CLOCK DIVIDER
|
||||
ACIA0CFG .EQU DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
ACIA1BASE .EQU $40 ; ACIA 1: REGISTERS BASE ADR
|
||||
ACIA1CLK .EQU CPUOSC ; ACIA 1: OSC FREQ IN HZ
|
||||
ACIA1DIV .EQU 1 ; ACIA 1: SERIAL CLOCK DIVIDER
|
||||
ACIA1CFG .EQU DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .EQU CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR
|
||||
SIO1ACLK .EQU CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1ACFG .EQU DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG
|
||||
SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1BCLK .EQU CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1BCFG .EQU DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG
|
||||
SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .EQU TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .EQU FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .EQU FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .EQU TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .EQU TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
;
|
||||
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .EQU IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .EQU $10 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .EQU $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .EQU $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .EQU TRUE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .EQU TRUE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .EQU $20 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .EQU 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
CHTRACE .EQU 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHUSBTRACE .EQU 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHSDTRACE .EQU 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHCNT .EQU 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2)
|
||||
CH0BASE .EQU $3E ; CH 0: BASE I/O ADDRESS
|
||||
CH0USBENABLE .EQU TRUE ; CH 0: ENABLE USB DISK
|
||||
CH0SDENABLE .EQU FALSE ; CH 0: ENABLE SD DISK
|
||||
CH1BASE .EQU $3C ; CH 1: BASE I/O ADDRESS
|
||||
CH1USBENABLE .EQU TRUE ; CH 1: ENABLE USB DISK
|
||||
CH1SDENABLE .EQU FALSE ; CH 1: ENABLE SD DISK
|
||||
;
|
||||
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
LPTMODE .EQU LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
|
||||
LPTCNT .EQU 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
LPTTRACE .EQU 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
LPT0BASE .EQU $0C ; LPT 0: REGISTERS BASE ADR
|
||||
LPT1BASE .EQU $00 ; LPT 1: REGISTERS BASE ADR
|
||||
;
|
||||
PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
PPACNT .EQU 1 ; PPA: NUMBER OF PPA DEVICES (1-2)
|
||||
PPATRACE .EQU 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPAMODE .EQU PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
|
||||
PPA0BASE .EQU LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
PPA1BASE .EQU LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
;
|
||||
IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
IMMCNT .EQU 1 ; IMM: NUMBER OF IMM DEVICES (1-2)
|
||||
IMMTRACE .EQU 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IMMMODE .EQU IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
|
||||
IMM0BASE .EQU LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
IMM1BASE .EQU LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
;
|
||||
SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
SYQCNT .EQU 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2)
|
||||
SYQTRACE .EQU 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SYQMODE .EQU IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
|
||||
SYQ0BASE .EQU LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
SYQ1BASE .EQU LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
;
|
||||
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
;
|
||||
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
;
|
||||
SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .EQU SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
||||
;
|
||||
AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .EQU AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
||||
;
|
||||
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .EQU DMAMODE_RC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
@@ -1,326 +0,0 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW 3.X CONFIGURATION FOR N8
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
|
||||
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
|
||||
; UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
|
||||
; FOR THE PLATFORM.
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "RetroBrew N8", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_N8 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .EQU SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .EQU MM_N8 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
RAMBIAS .EQU 0 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
|
||||
;
|
||||
Z180_BASE .EQU $40 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
|
||||
Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
|
||||
Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3)
|
||||
Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
|
||||
Z180_TIMER .EQU TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
|
||||
;
|
||||
N8_PPI0 .EQU $80 ; N8: FIRST PARALLEL PORT REGISTERS BASE ADR
|
||||
N8_PPI1 .EQU $84 ; N8: SECOND PARALLEL PORT REGISTERS BASE ADR
|
||||
N8_RTC .EQU $88 ; N8: RTC LATCH REGISTER ADR
|
||||
N8_ACR .EQU $94 ; N8: AUXILLARY CONTROL REGISTER (ACR) ADR
|
||||
N8_RMAP .EQU $96 ; N8: ROM PAGE REGISTER ADR
|
||||
N8_DEFACR .EQU $1B ; N8: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE)
|
||||
;
|
||||
RTCIO .EQU N8_RTC ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .EQU $B0 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER
|
||||
;
|
||||
PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
;
|
||||
WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
;
|
||||
FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .EQU FALSE ; ENABLES STATUS LED
|
||||
LEDMODE .EQU LEDMODE_RTC ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .EQU RTCIO ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .EQU N8_PPI0 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .EQU N8_PPI0 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .EQU FALSE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .EQU $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .EQU FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .EQU $FF ; SSER: STATUS PORT
|
||||
SSERDATA .EQU $FF ; SSER: DATA PORT
|
||||
SSERIRDY .EQU %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .EQU FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .EQU %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .EQU FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
;
|
||||
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .EQU 5 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .EQU TRUE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .EQU $80 ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .EQU $C0 ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .EQU DEFSERCFG ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .EQU $C8 ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .EQU $D0 ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .EQU $D8 ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
ASCISWAP .EQU FALSE ; ASCI: SWAP CHANNELS
|
||||
ASCIBOOT .EQU 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG
|
||||
ASCI1CFG .EQU DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG
|
||||
;
|
||||
Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
;
|
||||
SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .EQU 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
SIO0MODE .EQU SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .EQU $B0 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .EQU (4915200/8) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .EQU (4915200/8) ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
VDUSIZ .EQU V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
|
||||
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
CVDUMODE .EQU CVDUMODE_ECB ; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
|
||||
CVDUMON .EQU CVDUMON_EGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
|
||||
GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .EQU TRUE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .EQU TMSMODE_N8 ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .EQU FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VGASIZ .EQU V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
|
||||
VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .EQU FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .EQU TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .EQU TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .EQU TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .EQU FDMODE_N8 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
RFCNT .EQU 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
|
||||
;
|
||||
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .EQU IDEMODE_DIO ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .EQU $20 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .EQU $20 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .EQU $28 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .EQU FALSE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .EQU FALSE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .EQU N8_PPI0 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .EQU SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .EQU N8_PPI0 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
;
|
||||
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
;
|
||||
PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
;
|
||||
IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
;
|
||||
SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
;
|
||||
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO4BASE .EQU $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
|
||||
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIOZBASE .EQU $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
|
||||
PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
PIOSBASE .EQU N8_PPI0 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
|
||||
;
|
||||
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
FIFO_BASE .EQU $0C ; UF: REGISTERS BASE ADR
|
||||
;
|
||||
SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .EQU SNMODE_VGM ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
||||
;
|
||||
AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .EQU AYMODE_N8 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
||||
;
|
||||
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .EQU DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
@@ -1,365 +0,0 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW 3.X CONFIGURATION DEFAULTS FOR NABU Z80 W/ OPTION BOARD
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
|
||||
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
|
||||
; UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
|
||||
; FOR THE PLATFORM.
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "NABU Personal Computer", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_NABU ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .EQU 3580000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .EQU SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
|
||||
;
|
||||
RTCIO .EQU $C0 ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER
|
||||
CTCMODE .EQU CTCMODE_TIM16 ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
|
||||
CTCPRE .EQU 256 ; PRESCALE CONSTANT (1-256)
|
||||
CTCPRECH .EQU 2 ; PRESCALE CHANNEL (0-3)
|
||||
CTCTIMCH .EQU 3 ; TIMER CHANNEL (0-3)
|
||||
CTCOSC .EQU CPUOSC ; CTC CLOCK FREQUENCY
|
||||
;
|
||||
PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
SKZDIV .EQU DIV_1 ; UART CLK (CLK2) DIVIDER FOR Z80-512K
|
||||
;
|
||||
WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
WDOGIO .EQU $6E ; WATCHDOG REGISTER ADR
|
||||
;
|
||||
FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .EQU FALSE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .EQU TRUE ; ENABLES STATUS LED (SINGLE LED)
|
||||
LEDMODE .EQU LEDMODE_NABU ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .EQU $00 ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .EQU FALSE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .EQU $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .EQU FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .EQU FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
|
||||
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .EQU TRUE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .EQU $FF ; SSER: STATUS PORT
|
||||
SSERDATA .EQU $FF ; SSER: DATA PORT
|
||||
SSERIRDY .EQU %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .EQU FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .EQU %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .EQU FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
DUARTCNT .EQU 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
DUART0BASE .EQU $A0 ; DUART 0: BASE ADDRESS OF CHIP
|
||||
DUART0ACFG .EQU DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG
|
||||
DUART0BCFG .EQU DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG
|
||||
DUART1BASE .EQU $40 ; DUART 1: BASE ADDRESS OF CHIP
|
||||
DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
|
||||
DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
|
||||
;
|
||||
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .EQU 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .EQU $48 ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .EQU $FF ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .EQU DEFSERCFG ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .EQU $FF ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .EQU $FF ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
;
|
||||
Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
ACIADEBUG .EQU FALSE ; ACIA: ENABLE DEBUG OUTPUT
|
||||
ACIACNT .EQU 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
ACIA0BASE .EQU $80 ; ACIA 0: REGISTERS BASE ADR
|
||||
ACIA0CLK .EQU CPUOSC ; ACIA 0: OSC FREQ IN HZ
|
||||
ACIA0DIV .EQU 1 ; ACIA 0: SERIAL CLOCK DIVIDER
|
||||
ACIA0CFG .EQU DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
ACIA1BASE .EQU $40 ; ACIA 1: REGISTERS BASE ADR
|
||||
ACIA1CLK .EQU CPUOSC ; ACIA 1: OSC FREQ IN HZ
|
||||
ACIA1DIV .EQU 1 ; ACIA 1: SERIAL CLOCK DIVIDER
|
||||
ACIA1CFG .EQU DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .EQU CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR
|
||||
SIO1ACLK .EQU CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1ACFG .EQU DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG
|
||||
SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1BCLK .EQU CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1BCFG .EQU DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG
|
||||
SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .EQU TRUE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .EQU TMSMODE_NABU ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .EQU TRUE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .EQU TRUE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .EQU FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .EQU TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .EQU TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
;
|
||||
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .EQU IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .EQU $10 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .EQU $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .EQU $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .EQU TRUE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .EQU TRUE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .EQU TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .EQU $60 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .EQU 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
CHTRACE .EQU 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHUSBTRACE .EQU 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHSDTRACE .EQU 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHCNT .EQU 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2)
|
||||
CH0BASE .EQU $3E ; CH 0: BASE I/O ADDRESS
|
||||
CH0USBENABLE .EQU TRUE ; CH 0: ENABLE USB DISK
|
||||
CH0SDENABLE .EQU FALSE ; CH 0: ENABLE SD DISK
|
||||
CH1BASE .EQU $3C ; CH 1: BASE I/O ADDRESS
|
||||
CH1USBENABLE .EQU TRUE ; CH 1: ENABLE USB DISK
|
||||
CH1SDENABLE .EQU FALSE ; CH 1: ENABLE SD DISK
|
||||
;
|
||||
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
LPTMODE .EQU LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
|
||||
LPTCNT .EQU 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
LPTTRACE .EQU 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
LPT0BASE .EQU $0C ; LPT 0: REGISTERS BASE ADR
|
||||
LPT1BASE .EQU $00 ; LPT 1: REGISTERS BASE ADR
|
||||
;
|
||||
PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
PPACNT .EQU 1 ; PPA: NUMBER OF PPA DEVICES (1-2)
|
||||
PPATRACE .EQU 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPAMODE .EQU PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
|
||||
PPA0BASE .EQU LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
PPA1BASE .EQU LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
;
|
||||
IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
IMMCNT .EQU 1 ; IMM: NUMBER OF IMM DEVICES (1-2)
|
||||
IMMTRACE .EQU 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IMMMODE .EQU IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
|
||||
IMM0BASE .EQU LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
IMM1BASE .EQU LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
;
|
||||
SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
SYQCNT .EQU 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2)
|
||||
SYQTRACE .EQU 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SYQMODE .EQU IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
|
||||
SYQ0BASE .EQU LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
SYQ1BASE .EQU LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
;
|
||||
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
;
|
||||
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
;
|
||||
SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .EQU SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
||||
;
|
||||
AY38910ENABLE .EQU TRUE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .EQU AYMODE_NABU ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
||||
;
|
||||
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .EQU DMAMODE_RC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
@@ -1,366 +0,0 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW 3.X CONFIGURATION DEFAULTS FOR RCBUS Z180 CPU
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
|
||||
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
|
||||
; UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
|
||||
; FOR THE PLATFORM.
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "RCBus", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_RCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .EQU SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
RAMBIAS .EQU ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
|
||||
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
|
||||
;
|
||||
Z180_BASE .EQU $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
|
||||
Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
|
||||
Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3)
|
||||
Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
|
||||
Z180_TIMER .EQU TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
|
||||
;
|
||||
RTCIO .EQU $0C ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER
|
||||
;
|
||||
PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
;
|
||||
WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
;
|
||||
FPENABLE .EQU FALSE ; ENABLES FRONT PANEL SWITCHES
|
||||
FPBASE .EQU $00 ; FRONT PANEL I/O PORT BASE ADDRESS
|
||||
DIAGENABLE .EQU TRUE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
|
||||
DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS
|
||||
DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
|
||||
;
|
||||
FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .EQU TRUE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED)
|
||||
LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .EQU TRUE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .EQU $AA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .EQU FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .EQU $FF ; SSER: STATUS PORT
|
||||
SSERDATA .EQU $FF ; SSER: DATA PORT
|
||||
SSERIRDY .EQU %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .EQU FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .EQU %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .EQU FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
DUARTCNT .EQU 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
DUART0BASE .EQU $A0 ; DUART 0: BASE ADDRESS OF CHIP
|
||||
DUART0ACFG .EQU DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG
|
||||
DUART0BCFG .EQU DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG
|
||||
DUART1BASE .EQU $40 ; DUART 1: BASE ADDRESS OF CHIP
|
||||
DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
|
||||
DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
|
||||
;
|
||||
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .EQU 4 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .EQU $80 ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .EQU $88 ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .EQU DEFSERCFG ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .EQU $A0 ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .EQU $A8 ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
ASCISWAP .EQU FALSE ; ASCI: SWAP CHANNELS
|
||||
ASCIBOOT .EQU 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG
|
||||
ASCI1CFG .EQU DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG
|
||||
;
|
||||
Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
;
|
||||
SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .EQU SER_115200_8N1 ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .EQU 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .EQU SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR
|
||||
SIO1ACLK .EQU 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1ACFG .EQU SER_115200_8N1 ; SIO 1A: SERIAL LINE CONFIG
|
||||
SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1BCLK .EQU 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1BCFG .EQU SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG
|
||||
SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .EQU TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .EQU FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .EQU FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .EQU TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .EQU TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
;
|
||||
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .EQU IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .EQU $10 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .EQU $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .EQU $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .EQU TRUE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .EQU TRUE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .EQU $20 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .EQU 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .EQU TRUE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
CHTRACE .EQU 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHUSBTRACE .EQU 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHSDTRACE .EQU 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHCNT .EQU 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2)
|
||||
CH0BASE .EQU $3E ; CH 0: BASE I/O ADDRESS
|
||||
CH0USBENABLE .EQU TRUE ; CH 0: ENABLE USB DISK
|
||||
CH0SDENABLE .EQU FALSE ; CH 0: ENABLE SD DISK
|
||||
CH1BASE .EQU $3C ; CH 1: BASE I/O ADDRESS
|
||||
CH1USBENABLE .EQU TRUE ; CH 1: ENABLE USB DISK
|
||||
CH1SDENABLE .EQU FALSE ; CH 1: ENABLE SD DISK
|
||||
;
|
||||
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
LPTMODE .EQU LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
|
||||
LPTCNT .EQU 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
LPTTRACE .EQU 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
LPT0BASE .EQU $0C ; LPT 0: REGISTERS BASE ADR
|
||||
LPT1BASE .EQU $00 ; LPT 1: REGISTERS BASE ADR
|
||||
;
|
||||
PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
PPACNT .EQU 1 ; PPA: NUMBER OF PPA DEVICES (1-2)
|
||||
PPATRACE .EQU 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPAMODE .EQU PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
|
||||
PPA0BASE .EQU LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
PPA1BASE .EQU LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
;
|
||||
IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
IMMCNT .EQU 1 ; IMM: NUMBER OF IMM DEVICES (1-2)
|
||||
IMMTRACE .EQU 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IMMMODE .EQU IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
|
||||
IMM0BASE .EQU LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
IMM1BASE .EQU LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
;
|
||||
SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
SYQCNT .EQU 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2)
|
||||
SYQTRACE .EQU 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SYQMODE .EQU IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
|
||||
SYQ0BASE .EQU LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
SYQ1BASE .EQU LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
;
|
||||
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
;
|
||||
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
;
|
||||
SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .EQU SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
||||
;
|
||||
AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .EQU AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
||||
;
|
||||
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .EQU DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
@@ -1,370 +0,0 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW 3.X CONFIGURATION DEFAULTS FOR RCBUS Z280 CPU
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
|
||||
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
|
||||
; UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
|
||||
; FOR THE PLATFORM.
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "RCBus", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_RCZ280 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .EQU CPU_Z280 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .EQU 24000000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .EQU SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
RAMBIAS .EQU ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
|
||||
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
|
||||
;
|
||||
Z280_MEMLOWAIT .EQU 0 ; Z280: LOW 8MB MEMORY WAIT STATES (0-3)
|
||||
Z280_MEMHIWAIT .EQU 0 ; Z280: HIGH 8MB MEMORY WAIT STATES (0-3)
|
||||
Z280_IOWAIT .EQU 1 ; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
|
||||
Z280_INTWAIT .EQU 0 ; Z280: INT ACK WAIT STATUS (0-3)
|
||||
Z280_TIMER .EQU TRUE ; Z280: ENABLE INTERNAL Z280 SYSTEM PERIODIC TIMER
|
||||
;
|
||||
RTCIO .EQU $C0 ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER
|
||||
;
|
||||
PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
;
|
||||
WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
;
|
||||
FPLED_ENABLE .EQU TRUE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED)
|
||||
LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .EQU TRUE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .EQU $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .EQU FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .EQU $FF ; SSER: STATUS PORT
|
||||
SSERDATA .EQU $FF ; SSER: DATA PORT
|
||||
SSERIRDY .EQU %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .EQU FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .EQU %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .EQU FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
DUARTCNT .EQU 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
DUART0BASE .EQU $A0 ; DUART 0: BASE ADDRESS OF CHIP
|
||||
DUART0ACFG .EQU DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG
|
||||
DUART0BCFG .EQU DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG
|
||||
DUART1BASE .EQU $40 ; DUART 1: BASE ADDRESS OF CHIP
|
||||
DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
|
||||
DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
|
||||
;
|
||||
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .EQU 4 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .EQU $80 ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .EQU $88 ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .EQU DEFSERCFG ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .EQU $A0 ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .EQU $A8 ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
;
|
||||
Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
Z2UOSC .EQU 1843200 ; Z2U: OSC FREQUENCY IN MHZ
|
||||
Z2UOSCEXT .EQU TRUE ; Z2U: USE EXTERNAL OSCILLATOR
|
||||
Z2U0BASE .EQU $10 ; Z2U 0: BASE I/O ADDRESS
|
||||
Z2U0CFG .EQU DEFSERCFG ; Z2U 0: SERIAL LINE CONFIG
|
||||
Z2U0HFC .EQU FALSE ; Z2U 0: ENABLE HARDWARE FLOW CONTROL
|
||||
;
|
||||
ACIAENABLE .EQU TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
ACIADEBUG .EQU FALSE ; ACIA: ENABLE DEBUG OUTPUT
|
||||
ACIACNT .EQU 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
ACIA0BASE .EQU $80 ; ACIA 0: REGISTERS BASE ADR
|
||||
ACIA0CLK .EQU 7372800 ; ACIA 0: OSC FREQ IN HZ
|
||||
ACIA0DIV .EQU 1 ; ACIA 0: SERIAL CLOCK DIVIDER
|
||||
ACIA0CFG .EQU DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
ACIA1BASE .EQU $40 ; ACIA 1: REGISTERS BASE ADR
|
||||
ACIA1CLK .EQU 7372800 ; ACIA 1: OSC FREQ IN HZ
|
||||
ACIA1DIV .EQU 1 ; ACIA 1: SERIAL CLOCK DIVIDER
|
||||
ACIA1CFG .EQU DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .EQU 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR
|
||||
SIO1ACLK .EQU 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1ACFG .EQU DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG
|
||||
SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1BCLK .EQU 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1BCFG .EQU DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG
|
||||
SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .EQU TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .EQU FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .EQU FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .EQU TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .EQU TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
;
|
||||
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .EQU IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .EQU $10 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .EQU $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .EQU $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .EQU TRUE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .EQU TRUE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .EQU $20 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .EQU 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .EQU TRUE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
CHTRACE .EQU 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHUSBTRACE .EQU 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHSDTRACE .EQU 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHCNT .EQU 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2)
|
||||
CH0BASE .EQU $3E ; CH 0: BASE I/O ADDRESS
|
||||
CH0USBENABLE .EQU TRUE ; CH 0: ENABLE USB DISK
|
||||
CH0SDENABLE .EQU FALSE ; CH 0: ENABLE SD DISK
|
||||
CH1BASE .EQU $3C ; CH 1: BASE I/O ADDRESS
|
||||
CH1USBENABLE .EQU TRUE ; CH 1: ENABLE USB DISK
|
||||
CH1SDENABLE .EQU FALSE ; CH 1: ENABLE SD DISK
|
||||
;
|
||||
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
LPTMODE .EQU LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
|
||||
LPTCNT .EQU 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
LPTTRACE .EQU 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
LPT0BASE .EQU $0C ; LPT 0: REGISTERS BASE ADR
|
||||
LPT1BASE .EQU $00 ; LPT 1: REGISTERS BASE ADR
|
||||
;
|
||||
PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
PPACNT .EQU 1 ; PPA: NUMBER OF PPA DEVICES (1-2)
|
||||
PPATRACE .EQU 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPAMODE .EQU PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
|
||||
PPA0BASE .EQU LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
PPA1BASE .EQU LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
;
|
||||
IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
IMMCNT .EQU 1 ; IMM: NUMBER OF IMM DEVICES (1-2)
|
||||
IMMTRACE .EQU 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IMMMODE .EQU IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
|
||||
IMM0BASE .EQU LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
IMM1BASE .EQU LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
;
|
||||
SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
SYQCNT .EQU 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2)
|
||||
SYQTRACE .EQU 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SYQMODE .EQU IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
|
||||
SYQ0BASE .EQU LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
SYQ1BASE .EQU LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
;
|
||||
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
;
|
||||
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
;
|
||||
SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .EQU SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
||||
;
|
||||
AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .EQU AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
||||
;
|
||||
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .EQU DMAMODE_Z280 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
@@ -1,365 +0,0 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW 3.X CONFIGURATION DEFAULTS FOR RCBUS Z80
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
|
||||
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
|
||||
; UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
|
||||
; FOR THE PLATFORM.
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "RCBus", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_RCZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .EQU 7372800 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .EQU 1 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .EQU SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
|
||||
;
|
||||
RTCIO .EQU $C0 ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .EQU TRUE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER
|
||||
CTCMODE .EQU CTCMODE_TIM16 ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
|
||||
CTCPRE .EQU 256 ; PRESCALE CONSTANT (1-256)
|
||||
CTCPRECH .EQU 2 ; PRESCALE CHANNEL (0-3)
|
||||
CTCTIMCH .EQU 3 ; TIMER CHANNEL (0-3)
|
||||
CTCOSC .EQU CPUOSC ; CTC CLOCK FREQUENCY
|
||||
;
|
||||
PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
SKZDIV .EQU DIV_1 ; UART CLK (CLK2) DIVIDER FOR Z80-512K
|
||||
;
|
||||
WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
WDOGIO .EQU $6E ; WATCHDOG REGISTER ADR
|
||||
;
|
||||
FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED)
|
||||
LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .EQU TRUE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .EQU $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .EQU FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .EQU $FF ; SSER: STATUS PORT
|
||||
SSERDATA .EQU $FF ; SSER: DATA PORT
|
||||
SSERIRDY .EQU %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .EQU FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .EQU %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .EQU FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
DUARTCNT .EQU 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
DUART0BASE .EQU $A0 ; DUART 0: BASE ADDRESS OF CHIP
|
||||
DUART0ACFG .EQU DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG
|
||||
DUART0BCFG .EQU DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG
|
||||
DUART1BASE .EQU $40 ; DUART 1: BASE ADDRESS OF CHIP
|
||||
DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
|
||||
DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
|
||||
;
|
||||
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .EQU 4 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .EQU $80 ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .EQU $88 ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .EQU DEFSERCFG ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .EQU $A0 ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .EQU $A8 ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
;
|
||||
Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .EQU TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
ACIADEBUG .EQU FALSE ; ACIA: ENABLE DEBUG OUTPUT
|
||||
ACIACNT .EQU 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
ACIA0BASE .EQU $80 ; ACIA 0: REGISTERS BASE ADR
|
||||
ACIA0CLK .EQU CPUOSC ; ACIA 0: OSC FREQ IN HZ
|
||||
ACIA0DIV .EQU 1 ; ACIA 0: SERIAL CLOCK DIVIDER
|
||||
ACIA0CFG .EQU DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
ACIA1BASE .EQU $40 ; ACIA 1: REGISTERS BASE ADR
|
||||
ACIA1CLK .EQU CPUOSC ; ACIA 1: OSC FREQ IN HZ
|
||||
ACIA1DIV .EQU 1 ; ACIA 1: SERIAL CLOCK DIVIDER
|
||||
ACIA1CFG .EQU DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .EQU CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR
|
||||
SIO1ACLK .EQU CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1ACFG .EQU DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG
|
||||
SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1BCLK .EQU CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1BCFG .EQU DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG
|
||||
SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .EQU TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .EQU FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .EQU FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .EQU TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .EQU TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
;
|
||||
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .EQU IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .EQU $10 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .EQU $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .EQU $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .EQU TRUE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .EQU TRUE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .EQU $20 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .EQU 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .EQU TRUE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
CHTRACE .EQU 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHUSBTRACE .EQU 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHSDTRACE .EQU 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHCNT .EQU 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2)
|
||||
CH0BASE .EQU $3E ; CH 0: BASE I/O ADDRESS
|
||||
CH0USBENABLE .EQU TRUE ; CH 0: ENABLE USB DISK
|
||||
CH0SDENABLE .EQU FALSE ; CH 0: ENABLE SD DISK
|
||||
CH1BASE .EQU $3C ; CH 1: BASE I/O ADDRESS
|
||||
CH1USBENABLE .EQU TRUE ; CH 1: ENABLE USB DISK
|
||||
CH1SDENABLE .EQU FALSE ; CH 1: ENABLE SD DISK
|
||||
;
|
||||
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
LPTMODE .EQU LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
|
||||
LPTCNT .EQU 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
LPTTRACE .EQU 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
LPT0BASE .EQU $0C ; LPT 0: REGISTERS BASE ADR
|
||||
LPT1BASE .EQU $00 ; LPT 1: REGISTERS BASE ADR
|
||||
;
|
||||
PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
PPACNT .EQU 1 ; PPA: NUMBER OF PPA DEVICES (1-2)
|
||||
PPATRACE .EQU 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPAMODE .EQU PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
|
||||
PPA0BASE .EQU LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
PPA1BASE .EQU LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
;
|
||||
IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
IMMCNT .EQU 1 ; IMM: NUMBER OF IMM DEVICES (1-2)
|
||||
IMMTRACE .EQU 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IMMMODE .EQU IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
|
||||
IMM0BASE .EQU LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
IMM1BASE .EQU LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
;
|
||||
SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
SYQCNT .EQU 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2)
|
||||
SYQTRACE .EQU 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SYQMODE .EQU IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
|
||||
SYQ0BASE .EQU LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
SYQ1BASE .EQU LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
;
|
||||
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
;
|
||||
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
;
|
||||
SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .EQU SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
||||
;
|
||||
AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .EQU AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
||||
;
|
||||
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .EQU DMAMODE_RC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
@@ -1,314 +0,0 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW 3.X CONFIGURATION FOR RHYOPHYRE
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
|
||||
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
|
||||
; UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
|
||||
; FOR THE PLATFORM.
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "Rhyophyre", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_RPH ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU TRUE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .EQU SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .EQU MM_RPH ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
RAMBIAS .EQU 0 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
|
||||
;
|
||||
Z180_BASE .EQU $40 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
|
||||
Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
|
||||
Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3)
|
||||
Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
|
||||
Z180_TIMER .EQU TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
|
||||
;
|
||||
RPH_PPI0 .EQU $88 ; RPH: FIRST PARALLEL PORT REGISTERS BASE ADR
|
||||
RPH_RTC .EQU $84 ; RPH: RTC LATCH REGISTER ADR
|
||||
RPH_ACR .EQU $80 ; RPH: AUXILLARY CONTROL REGISTER (ACR) ADR
|
||||
RPH_DEFACR .EQU $20 ; RPH: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE)
|
||||
;
|
||||
RTCIO .EQU RPH_RTC ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .EQU $B0 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER
|
||||
;
|
||||
PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
;
|
||||
WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
;
|
||||
FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .EQU FALSE ; ENABLES STATUS LED
|
||||
LEDMODE .EQU LEDMODE_RTC ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .EQU RTCIO ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .EQU RPH_PPI0 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .EQU RPH_PPI0 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .EQU FALSE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .EQU $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .EQU FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .EQU $FF ; SSER: STATUS PORT
|
||||
SSERDATA .EQU $FF ; SSER: DATA PORT
|
||||
SSERIRDY .EQU %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .EQU FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .EQU %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .EQU FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
;
|
||||
UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .EQU 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .EQU $FF ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .EQU $FF ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .EQU DEFSERCFG ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .EQU $FF ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .EQU $FF ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
ASCISWAP .EQU FALSE ; ASCI: SWAP CHANNELS
|
||||
ASCIBOOT .EQU 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG
|
||||
ASCI1CFG .EQU DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG
|
||||
;
|
||||
Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
;
|
||||
SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
;
|
||||
XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
VDUSIZ .EQU V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
|
||||
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
CVDUMODE .EQU CVDUMODE_ECB ; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
|
||||
CVDUMON .EQU CVDUMON_EGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
|
||||
GDCENABLE .EQU TRUE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
GDCMODE .EQU GDCMODE_RPH ; GDC: GDC MODE: GDCMODE_[NONE|ECB|RPH]
|
||||
GDCMON .EQU GDCMON_EGA ; GDC: GDC MONITOR SETUP: GDCMON_[NONE|CGA|EGA]
|
||||
TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .EQU TMSMODE_N8 ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .EQU FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VGASIZ .EQU V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
|
||||
VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .EQU FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .EQU TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .EQU TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .EQU FDMODE_N8 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
RFCNT .EQU 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
|
||||
;
|
||||
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .EQU IDEMODE_DIO ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .EQU $20 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .EQU $20 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .EQU $28 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .EQU FALSE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .EQU FALSE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .EQU TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .EQU RPH_PPI0 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .EQU SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .EQU RPH_PPI0 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
;
|
||||
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .EQU FALSE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .EQU FALSE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
;
|
||||
PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
;
|
||||
IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
;
|
||||
SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
;
|
||||
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO4BASE .EQU $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
|
||||
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIOZBASE .EQU $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
|
||||
PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
PIOSBASE .EQU RPH_PPI0 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
|
||||
;
|
||||
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
FIFO_BASE .EQU $0C ; UF: REGISTERS BASE ADR
|
||||
;
|
||||
SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .EQU SNMODE_NONE ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
||||
;
|
||||
AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .EQU AYMODE_N8 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
||||
;
|
||||
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .EQU DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
@@ -1,350 +0,0 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW 3.X CONFIGURATION DEFAULTS FOR S100 Z180
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
|
||||
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
|
||||
; UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
|
||||
; FOR THE PLATFORM.
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "S100", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_S100 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .EQU SER_57600_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
RAMBIAS .EQU ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
|
||||
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
|
||||
;
|
||||
Z180_BASE .EQU $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
|
||||
Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
|
||||
Z180_MEMWAIT .EQU 1 ; Z180: MEMORY WAIT STATES (0-3)
|
||||
Z180_IOWAIT .EQU 2 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
|
||||
Z180_TIMER .EQU TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
|
||||
;
|
||||
RTCIO .EQU $0C ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER
|
||||
;
|
||||
PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
;
|
||||
WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
;
|
||||
FPLED_ENABLE .EQU TRUE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .EQU TRUE ; ENABLES STATUS LED (SINGLE LED)
|
||||
LEDMODE .EQU LEDMODE_SC ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .EQU FALSE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .EQU $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .EQU FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .EQU $FF ; SSER: STATUS PORT
|
||||
SSERDATA .EQU $FF ; SSER: DATA PORT
|
||||
SSERIRDY .EQU %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .EQU FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .EQU %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .EQU FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
DUARTCNT .EQU 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
DUART0BASE .EQU $A0 ; DUART 0: BASE ADDRESS OF CHIP
|
||||
DUART0ACFG .EQU DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG
|
||||
DUART0BCFG .EQU DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG
|
||||
DUART1BASE .EQU $40 ; DUART 1: BASE ADDRESS OF CHIP
|
||||
DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
|
||||
DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
|
||||
;
|
||||
UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .EQU 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .EQU $FF ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .EQU $FF ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .EQU DEFSERCFG ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .EQU $FF ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .EQU $FF ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
ASCISWAP .EQU FALSE ; ASCI: SWAP CHANNELS
|
||||
ASCIBOOT .EQU 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG
|
||||
ASCI1CFG .EQU DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG
|
||||
;
|
||||
Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
;
|
||||
SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .EQU SER_115200_8N1 ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .EQU 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .EQU SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR
|
||||
SIO1ACLK .EQU 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1ACFG .EQU SER_115200_8N1 ; SIO 1A: SERIAL LINE CONFIG
|
||||
SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1BCLK .EQU 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1BCFG .EQU SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG
|
||||
SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .EQU TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .EQU FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .EQU FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .EQU TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .EQU TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
;
|
||||
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .EQU IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .EQU $10 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .EQU $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .EQU $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .EQU TRUE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .EQU TRUE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .EQU $20 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .EQU SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
;
|
||||
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
LPTMODE .EQU LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
|
||||
LPTCNT .EQU 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
LPTTRACE .EQU 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
LPT0BASE .EQU $18 ; LPT 0: REGISTERS BASE ADR
|
||||
LPT1BASE .EQU $00 ; LPT 1: REGISTERS BASE ADR
|
||||
;
|
||||
PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
PPACNT .EQU 1 ; PPA: NUMBER OF PPA DEVICES (1-2)
|
||||
PPATRACE .EQU 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPAMODE .EQU PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
|
||||
PPA0BASE .EQU LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
PPA1BASE .EQU LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
;
|
||||
IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
IMMCNT .EQU 1 ; IMM: NUMBER OF IMM DEVICES (1-2)
|
||||
IMMTRACE .EQU 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IMMMODE .EQU IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
|
||||
IMM0BASE .EQU LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
IMM1BASE .EQU LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
;
|
||||
SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
SYQCNT .EQU 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2)
|
||||
SYQTRACE .EQU 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SYQMODE .EQU IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
|
||||
SYQ0BASE .EQU LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
SYQ1BASE .EQU LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
;
|
||||
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
;
|
||||
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
;
|
||||
SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .EQU SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
||||
;
|
||||
AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .EQU AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
||||
;
|
||||
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .EQU DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
@@ -1,315 +0,0 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW 3.X CONFIGURATION DEFAULTS FOR SBC
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
|
||||
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
|
||||
; UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
|
||||
; FOR THE PLATFORM.
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "RetroBrew SBC", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .EQU 8000000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .EQU SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .EQU MM_SBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
|
||||
MPCL_ROM .EQU $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
|
||||
;
|
||||
RTCIO .EQU $70 ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .EQU $B0 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .EQU TRUE ; ENABLE CTC PERIODIC TIMER
|
||||
CTCMODE .EQU CTCMODE_CTR ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
|
||||
CTCPRE .EQU 256 ; PRESCALE CONSTANT (1-256)
|
||||
CTCPRECH .EQU 2 ; PRESCALE CHANNEL (0-3)
|
||||
CTCTIMCH .EQU 3 ; TIMER CHANNEL (0-3)
|
||||
CTCOSC .EQU 614400 ; CTC CLOCK FREQUENCY
|
||||
;
|
||||
PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
;
|
||||
WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
;
|
||||
FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .EQU FALSE ; ENABLES STATUS LED
|
||||
LEDMODE .EQU LEDMODE_RTC ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .EQU RTCIO ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .EQU FALSE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .EQU $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .EQU FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .EQU $FF ; SSER: STATUS PORT
|
||||
SSERDATA .EQU $FF ; SSER: DATA PORT
|
||||
SSERIRDY .EQU %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .EQU FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .EQU %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .EQU FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
;
|
||||
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .EQU 7 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .EQU TRUE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .EQU $68 ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .EQU $80 ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .EQU SER_300_8N1 ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .EQU $18 ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .EQU $C0 ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .EQU $C8 ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .EQU $D0 ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .EQU $D8 ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
;
|
||||
Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
;
|
||||
SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .EQU 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
SIO0MODE .EQU SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .EQU $B0 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .EQU (4915200/8) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .EQU (4915200/8) ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
VDUSIZ .EQU V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
|
||||
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
CVDUMODE .EQU CVDUMODE_ECB ; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
|
||||
CVDUMON .EQU CVDUMON_EGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
|
||||
GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .EQU TMSMODE_SCG ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .EQU FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VGASIZ .EQU V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
|
||||
VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .EQU FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .EQU TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .EQU TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .EQU FDMODE_DIO3 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
RFCNT .EQU 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
|
||||
;
|
||||
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .EQU IDEMODE_DIO ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .EQU $20 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .EQU $20 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .EQU $28 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .EQU FALSE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .EQU FALSE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .EQU $60 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .EQU $20 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .EQU $14 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .EQU SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
;
|
||||
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
HDSKTRACE .EQU 1 ; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
;
|
||||
PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
;
|
||||
PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
;
|
||||
IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
;
|
||||
SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
;
|
||||
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO4BASE .EQU $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
|
||||
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIOZBASE .EQU $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
|
||||
PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
PIOSBASE .EQU $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
|
||||
;
|
||||
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
UFBASE .EQU $0C ; UF: REGISTERS BASE ADR
|
||||
;
|
||||
SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .EQU SNMODE_VGM ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
||||
;
|
||||
AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .EQU AYMODE_SCG ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
||||
;
|
||||
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .EQU DMAMODE_ECB ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
@@ -1,360 +0,0 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW 3.X CONFIGURATION DEFAULTS FOR SC Z180 VARIANTS (SC126, SC130, ETC.)
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
|
||||
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
|
||||
; UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
|
||||
; FOR THE PLATFORM.
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "Small Computer", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_SCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .EQU SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
RAMBIAS .EQU ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
|
||||
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
|
||||
;
|
||||
Z180_BASE .EQU $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
|
||||
Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
|
||||
Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3)
|
||||
Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
|
||||
Z180_TIMER .EQU TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
|
||||
;
|
||||
RTCIO .EQU $0C ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER
|
||||
;
|
||||
PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
;
|
||||
WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
;
|
||||
FPLED_ENABLE .EQU TRUE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED)
|
||||
LEDMODE .EQU LEDMODE_SC ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .EQU TRUE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .EQU $AA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .EQU FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .EQU $FF ; SSER: STATUS PORT
|
||||
SSERDATA .EQU $FF ; SSER: DATA PORT
|
||||
SSERIRDY .EQU %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .EQU FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .EQU %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .EQU FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
DUARTCNT .EQU 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
DUART0BASE .EQU $A0 ; DUART 0: BASE ADDRESS OF CHIP
|
||||
DUART0ACFG .EQU DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG
|
||||
DUART0BCFG .EQU DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG
|
||||
DUART1BASE .EQU $40 ; DUART 1: BASE ADDRESS OF CHIP
|
||||
DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
|
||||
DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
|
||||
;
|
||||
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .EQU 4 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .EQU $80 ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .EQU $88 ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .EQU DEFSERCFG ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .EQU $A0 ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .EQU $A8 ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
ASCISWAP .EQU FALSE ; ASCI: SWAP CHANNELS
|
||||
ASCIBOOT .EQU 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG
|
||||
ASCI1CFG .EQU DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG
|
||||
;
|
||||
Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
;
|
||||
SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .EQU SER_115200_8N1 ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .EQU 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .EQU SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR
|
||||
SIO1ACLK .EQU 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1ACFG .EQU SER_115200_8N1 ; SIO 1A: SERIAL LINE CONFIG
|
||||
SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1BCLK .EQU 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1BCFG .EQU SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG
|
||||
SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .EQU TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .EQU FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .EQU FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .EQU TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .EQU TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
;
|
||||
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .EQU IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .EQU $10 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .EQU $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .EQU $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .EQU TRUE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .EQU TRUE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .EQU $20 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .EQU SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .EQU TRUE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
CHTRACE .EQU 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHUSBTRACE .EQU 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHSDTRACE .EQU 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
CHCNT .EQU 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2)
|
||||
CH0BASE .EQU $3E ; CH 0: BASE I/O ADDRESS
|
||||
CH0USBENABLE .EQU TRUE ; CH 0: ENABLE USB DISK
|
||||
CH0SDENABLE .EQU FALSE ; CH 0: ENABLE SD DISK
|
||||
CH1BASE .EQU $3C ; CH 1: BASE I/O ADDRESS
|
||||
CH1USBENABLE .EQU TRUE ; CH 1: ENABLE USB DISK
|
||||
CH1SDENABLE .EQU FALSE ; CH 1: ENABLE SD DISK
|
||||
;
|
||||
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
LPTMODE .EQU LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
|
||||
LPTCNT .EQU 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
LPTTRACE .EQU 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
LPT0BASE .EQU $18 ; LPT 0: REGISTERS BASE ADR
|
||||
LPT1BASE .EQU $00 ; LPT 1: REGISTERS BASE ADR
|
||||
;
|
||||
PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
PPACNT .EQU 1 ; PPA: NUMBER OF PPA DEVICES (1-2)
|
||||
PPATRACE .EQU 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPAMODE .EQU PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
|
||||
PPA0BASE .EQU LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
PPA1BASE .EQU LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
;
|
||||
IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
IMMCNT .EQU 1 ; IMM: NUMBER OF IMM DEVICES (1-2)
|
||||
IMMTRACE .EQU 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IMMMODE .EQU IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
|
||||
IMM0BASE .EQU LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
IMM1BASE .EQU LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
;
|
||||
SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
SYQCNT .EQU 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2)
|
||||
SYQTRACE .EQU 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SYQMODE .EQU IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
|
||||
SYQ0BASE .EQU LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
SYQ1BASE .EQU LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
;
|
||||
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
;
|
||||
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
;
|
||||
SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .EQU SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
||||
;
|
||||
AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .EQU AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
||||
;
|
||||
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .EQU DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
@@ -1,281 +0,0 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW 3.X CONFIGURATION DEFAULTS FOR SIMPLE Z80 RETRO
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
|
||||
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
|
||||
; UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
|
||||
; FOR THE PLATFORM.
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "Z80Retro", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_Z80RETRO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .EQU 14745600 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .EQU SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
MPGSEL_0 .EQU $60 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_1 .EQU $61 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_2 .EQU $62 ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_3 .EQU $63 ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGENA .EQU $64 ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
|
||||
;
|
||||
RTCIO .EQU $70 ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .EQU TRUE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .EQU $40 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER (too fast for RomWBW right now)
|
||||
CTCMODE .EQU CTCMODE_CTR ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
|
||||
CTCPRE .EQU 256 ; PRESCALE CONSTANT (1-256)
|
||||
CTCPRECH .EQU 0 ; PRESCALE CHANNEL (0-3)
|
||||
CTCTIMCH .EQU 1 ; TIMER CHANNEL (0-3)
|
||||
CTCOSC .EQU 7372800 ; CTC CLOCK FREQUENCY
|
||||
;
|
||||
PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
;
|
||||
WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
;
|
||||
FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .EQU FALSE ; ENABLES STATUS LED
|
||||
LEDMODE .EQU LEDMODE_RTC ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .EQU $00 ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .EQU FALSE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .EQU $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .EQU FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .EQU FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .EQU $FF ; SSER: STATUS PORT
|
||||
SSERDATA .EQU $FF ; SSER: DATA PORT
|
||||
SSERIRDY .EQU %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .EQU FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .EQU %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .EQU FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
;
|
||||
UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .EQU 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .EQU $FF ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .EQU $FF ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .EQU DEFSERCFG ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .EQU $FF ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .EQU $FF ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
;
|
||||
Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
;
|
||||
SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .EQU 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
SIO0MODE .EQU SIOMODE_Z80R ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .EQU CPUOSC/2 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .EQU CPUOSC/2 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1MODE .EQU SIOMODE_Z80R ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR
|
||||
SIO1ACLK .EQU CPUOSC/2 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1ACFG .EQU DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG
|
||||
SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1BCLK .EQU CPUOSC/2 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1BCFG .EQU DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG
|
||||
SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .EQU TMSMODE_NONE ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .EQU FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .EQU FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .EQU TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .EQU TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .EQU FDMODE_ZETA2 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .EQU 1 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
;
|
||||
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
;
|
||||
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .EQU $60 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .EQU SDMODE_Z80R ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
;
|
||||
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
;
|
||||
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
PPPBASE .EQU $60 ; PPP: PPI REGISTERS BASE ADDRESS
|
||||
PPPSDENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
|
||||
PPPSDTRACE .EQU 1 ; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPPCONENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
;
|
||||
LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
;
|
||||
PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
;
|
||||
IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
;
|
||||
SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
;
|
||||
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
PIOSBASE .EQU $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
|
||||
;
|
||||
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
;
|
||||
SN76489ENABLE .EQU FALSE ; SN76489 SOUND DRIVER
|
||||
AY38910ENABLE .EQU FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER
|
||||
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .EQU DMAMODE_NONE ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
@@ -1,251 +0,0 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW 3.X CONFIGURATION DEFAULTS FOR ZETA V1
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
|
||||
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
|
||||
; UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
|
||||
; FOR THE PLATFORM.
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "Zeta", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_ZETA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; BIOS_[WBW|UNA]: HARDWARE BIOS
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .EQU 8000000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .EQU SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .EQU MM_SBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
|
||||
MPCL_ROM .EQU $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
|
||||
;
|
||||
RTCIO .EQU $70 ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
|
||||
;
|
||||
PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
;
|
||||
WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
;
|
||||
FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .EQU FALSE ; ENABLES STATUS LED
|
||||
LEDMODE .EQU LEDMODE_RTC ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .EQU RTCIO ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .EQU FALSE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .EQU $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .EQU FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .EQU $FF ; SSER: STATUS PORT
|
||||
SSERDATA .EQU $FF ; SSER: DATA PORT
|
||||
SSERIRDY .EQU %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .EQU FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .EQU %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .EQU FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
;
|
||||
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .EQU 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .EQU $68 ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .EQU $FF ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .EQU SER_300_8N1 ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .EQU $FF ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .EQU $FF ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
;
|
||||
Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
;
|
||||
SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
;
|
||||
XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .EQU TMSMODE_NONE ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .EQU FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .EQU FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .EQU TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .EQU TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .EQU TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .EQU FDMODE_ZETA ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .EQU 1 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
;
|
||||
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
;
|
||||
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .EQU $60 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
;
|
||||
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
;
|
||||
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
PPPBASE .EQU $60 ; PPP: PPI REGISTERS BASE ADDRESS
|
||||
PPPSDENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
|
||||
PPPSDTRACE .EQU 1 ; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPPCONENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
;
|
||||
LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
;
|
||||
PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
;
|
||||
IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
;
|
||||
SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
;
|
||||
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
PIOSBASE .EQU $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
|
||||
;
|
||||
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
;
|
||||
SN76489ENABLE .EQU FALSE ; SN76489 SOUND DRIVER
|
||||
AY38910ENABLE .EQU FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER
|
||||
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .EQU DMAMODE_NONE ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
|
||||
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
@@ -1,262 +0,0 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW 3.X CONFIGURATION DEFAULTS FOR ZETA V2
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
|
||||
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
|
||||
; UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
|
||||
; FOR THE PLATFORM.
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "Zeta 2", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_ZETA2 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
|
||||
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
|
||||
;
|
||||
CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .EQU 8000000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .EQU SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
|
||||
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
|
||||
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
|
||||
;
|
||||
RTCIO .EQU $70 ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .EQU TRUE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .EQU $20 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .EQU TRUE ; ENABLE CTC PERIODIC TIMER
|
||||
CTCMODE .EQU CTCMODE_CTR ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
|
||||
CTCPRE .EQU 256 ; PRESCALE CONSTANT (1-256)
|
||||
CTCPRECH .EQU 0 ; PRESCALE CHANNEL (0-3)
|
||||
CTCTIMCH .EQU 1 ; TIMER CHANNEL (0-3)
|
||||
CTCOSC .EQU 921600 ; CTC CLOCK FREQUENCY
|
||||
;
|
||||
PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER
|
||||
PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS
|
||||
;
|
||||
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
;
|
||||
WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
;
|
||||
FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED
|
||||
FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED
|
||||
;
|
||||
DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .EQU FALSE ; ENABLES STATUS LED
|
||||
LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU]
|
||||
LEDPORT .EQU RTCIO ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL
|
||||
LCDENABLE .EQU FALSE ; ENABLE LCD DISPLAY
|
||||
LCDBASE .EQU $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
|
||||
LCDDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
|
||||
GM7303ENABLE .EQU FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
|
||||
;
|
||||
BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE
|
||||
SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE
|
||||
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
|
||||
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .EQU $FF ; SSER: STATUS PORT
|
||||
SSERDATA .EQU $FF ; SSER: DATA PORT
|
||||
SSERIRDY .EQU %00000001 ; SSER: INPUT READY BIT MASK
|
||||
SSERIINV .EQU FALSE ; SSER: INPUT READY BIT INVERTED
|
||||
SSERORDY .EQU %00000010 ; SSER: OUTPUT READY BIT MASK
|
||||
SSEROINV .EQU FALSE ; SSER: OUTPUT READY BIT INVERTED
|
||||
;
|
||||
DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
;
|
||||
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTCNT .EQU 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
|
||||
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
|
||||
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
|
||||
UART0BASE .EQU $68 ; UART 0: REGISTERS BASE ADR
|
||||
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
|
||||
UART1BASE .EQU $FF ; UART 1: REGISTERS BASE ADR
|
||||
UART1CFG .EQU SER_300_8N1 ; UART 1: SERIAL LINE CONFIG
|
||||
UART2BASE .EQU $FF ; UART 2: REGISTERS BASE ADR
|
||||
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
|
||||
UART3BASE .EQU $FF ; UART 3: REGISTERS BASE ADR
|
||||
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
|
||||
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
|
||||
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
|
||||
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
|
||||
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
|
||||
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
|
||||
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
|
||||
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
|
||||
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
|
||||
;
|
||||
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
;
|
||||
Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
;
|
||||
SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
;
|
||||
XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .EQU TMSMODE_NONE ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
||||
TMS80COLS .EQU FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
||||
TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
||||
EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
||||
FVENABLE .EQU FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
||||
;
|
||||
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .EQU TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .EQU TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .EQU TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .EQU FDMODE_ZETA2 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .EQU 1 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
;
|
||||
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
;
|
||||
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .EQU $60 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
|
||||
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT
|
||||
;
|
||||
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
;
|
||||
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
PPPBASE .EQU $60 ; PPP: PPI REGISTERS BASE ADDRESS
|
||||
PPPSDENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
|
||||
PPPSDTRACE .EQU 1 ; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPPCONENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
||||
;
|
||||
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
;
|
||||
LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
;
|
||||
PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
;
|
||||
IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
;
|
||||
SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
;
|
||||
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
PIOSBASE .EQU $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
|
||||
;
|
||||
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
;
|
||||
SN76489ENABLE .EQU FALSE ; SN76489 SOUND DRIVER
|
||||
AY38910ENABLE .EQU FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER
|
||||
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .EQU DMAMODE_NONE ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
||||
;
|
||||
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
|
||||
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
||||
@@ -46,28 +46,29 @@
|
||||
;
|
||||
; INCLUDE FILE NESTING:
|
||||
;
|
||||
; hbios.asm
|
||||
; - std.asm
|
||||
; - ver.inc
|
||||
; - hbios.inc
|
||||
; - build.inc
|
||||
; - config/<plt>_<cfg>.asm
|
||||
; - cfg_<plt>.asm
|
||||
; - [z180.inc|z280.inc]
|
||||
; - [eipc.inc]
|
||||
; - <drivers>.asm
|
||||
; - <fonts>.asm
|
||||
; - util.asm
|
||||
; - time.asm
|
||||
; - bcd.asm
|
||||
; - decode.asm
|
||||
; - encode.asm
|
||||
; - [xio|mio].asm
|
||||
; - unlzsa2s.asm
|
||||
; - std.asm
|
||||
; - ../ver.inc
|
||||
; - build.inc
|
||||
; - Config/<plt>_std.asm
|
||||
; - cfg_<plt>.asm
|
||||
; - cfg_MASTER.asm
|
||||
; - hbios.inc
|
||||
; - [z180.inc]
|
||||
; - [z280.inc]
|
||||
; - [eipc.inc]
|
||||
; - util.asm
|
||||
; - time.asm
|
||||
; - bcd.asm
|
||||
; - decode.asm
|
||||
; - encode.asm
|
||||
; - [xio.asm]
|
||||
; - [mio.asm]
|
||||
; - [unlzsa2s.asm]
|
||||
; - <drivers...>.asm
|
||||
; - <fonts...>.asm
|
||||
;
|
||||
; MEMORY LAYOUT:
|
||||
;
|
||||
;
|
||||
; DESCRIPTION START LENGTH
|
||||
; ----------------------------- ------- -------
|
||||
; Page Zero 0x0000 0x0100
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user