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Pegasys-RomWBW
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ZRC and ZZRCC Image Creation Updates 

- Modified ZRC and ZZRCC image creation scripts to allow up to 0x1B8 of boot code.
patch v3.4.0-dev.8
Wayne Warthen 2 years ago
parent
bbc84f0c2d
commit
3247e67ed4
10 changed files with 18 additions and 18 deletions
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  1. 8
      Source/ZRC/Build.cmd
  2. 8
      Source/ZRC/ZRC Disk Layout.txt
  3. BIN
      Source/ZRC/zrc_cfldr.bin
  4. BIN
      Source/ZRC/zrc_ptbl.bin
  5. 8
      Source/ZZRCC/Build.cmd
  6. 8
      Source/ZZRCC/ZZRCC Disk Layout.txt
  7. BIN
      Source/ZZRCC/zzrcc_cfldr.bin
  8. BIN
      Source/ZZRCC/zzrcc_ptbl.bin
  9. 2
      Source/ver.inc
  10. 2
      Source/ver.lib

8
Source/ZRC/Build.cmd
View File

@ -14,8 +14,8 @@ goto :eof
:build_zrc :build_zrc
srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x0 0x100 zrc_cfldr.bin -binary -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x100 0x200 zrc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x0 0x200 zrc_cfldr.bin -binary -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x1B8 0x200 zrc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ80_zrc.rom -binary -offset 0x24000 -o temp.dat -binary srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ80_zrc.rom -binary -offset 0x24000 -o temp.dat -binary
move temp.dat ..\..\Binary\hd1k_zrc_prefix.dat move temp.dat ..\..\Binary\hd1k_zrc_prefix.dat
@ -27,8 +27,8 @@ goto :eof
:build_zrc_ram :build_zrc_ram
srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x0 0x100 zrc_cfldr.bin -binary -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x100 0x200 zrc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x0 0x200 zrc_cfldr.bin -binary -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x1B8 0x200 zrc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ80_zrc_ram.rom -binary -offset 0x24000 -o temp.dat -binary srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ80_zrc_ram.rom -binary -offset 0x24000 -o temp.dat -binary
move temp.dat ..\..\Binary\hd1k_zrc_ram_prefix.dat move temp.dat ..\..\Binary\hd1k_zrc_ram_prefix.dat

8
Source/ZRC/ZRC Disk Layout.txt
View File

@ -4,8 +4,8 @@ ZRC Disk Prefix Layout
---- Bytes ---- --- Sectors --- ---- Bytes ---- --- Sectors ---
Start Length Start Length Description Start Length Start Length Description
------- ------- ------- ------- --------------------------- ------- ------- ------- ------- ---------------------------
0x00000 0x00100 0 0.5 CF Boot Loader
0x00100 0x00100 0.5 0.5 RomWBW Partition Table
0x00000 0x001BE 0 1 CF Boot Loader
0x001B8 0x00048 RomWBW Partition Table
0x00200 0x1EE00 1 247 Unused 0x00200 0x1EE00 1 247 Unused
0x1F000 0x01000 248 8 ZRC Monitor v0.7 0x1F000 0x01000 248 8 ZRC Monitor v0.7
0x20000 0x04000 256 32 Unused 0x20000 0x04000 256 32 Unused
@ -17,9 +17,9 @@ Notes
----- -----
- At startup CPLD ROM is mapped to Z80 CPU address space 0x0000-0x003F, CPU begins execution at 0x0000 - At startup CPLD ROM is mapped to Z80 CPU address space 0x0000-0x003F, CPU begins execution at 0x0000
- CPLD ROM (CF bootstrap mode) reads CF Boot Loader (256B) from start of CF (MBR) to 0xB000 and runs it
- CPLD ROM (CF bootstrap mode) reads CF Boot Loader (512B) from start of CF (MBR) to 0xB000 and runs it
- CF Boot Loader reads ZRC Monitor (4KB) from sectors 0xF8-0xFF of CF to 0xB400 and runs it - CF Boot Loader reads ZRC Monitor (4KB) from sectors 0xF8-0xFF of CF to 0xB400 and runs it
- ZRC Monitor reads 512KB (RomWBW) from sectors 0x120-0x51F of CF into first 512KB of physical RAM - ZRC Monitor reads 512KB (RomWBW) from sectors 0x120-0x51F of CF into first 512KB of physical RAM
- ZRC Monitor maps first 32KB of physical RAM to first 32KB of CPU RAM and starts execution at 0x0000 - ZRC Monitor maps first 32KB of physical RAM to first 32KB of CPU RAM and starts execution at 0x0000
-- WBW 2:30 PM 10/8/2023
-- WBW 3:30 PM 10/12/2023

BIN
Source/ZRC/zrc_cfldr.bin
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Binary file not shown.

BIN
Source/ZRC/zrc_ptbl.bin
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Binary file not shown.

8
Source/ZZRCC/Build.cmd
View File

@ -17,8 +17,8 @@ goto :eof
:build_zzrcc :build_zzrcc
srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x0 0x100 zzrcc_cfldr.bin -binary -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x100 0x200 zzrcc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x0 0x200 zzrcc_cfldr.bin -binary -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x1B8 0x200 zzrcc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrcc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrcc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ280_zzrcc.rom -binary -offset 0x24000 -o temp.dat -binary srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ280_zzrcc.rom -binary -offset 0x24000 -o temp.dat -binary
move temp.dat ..\..\Binary\hd1k_zzrcc_prefix.dat move temp.dat ..\..\Binary\hd1k_zzrcc_prefix.dat
@ -30,8 +30,8 @@ goto :eof
:build_zzrcc_ram :build_zzrcc_ram
srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x0 0x100 zzrcc_cfldr.bin -binary -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x100 0x200 zzrcc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x0 0x200 zzrcc_cfldr.bin -binary -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x1B8 0x200 zzrcc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrcc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrcc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ280_zzrcc_ram.rom -binary -offset 0x24000 -o temp.dat -binary srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ280_zzrcc_ram.rom -binary -offset 0x24000 -o temp.dat -binary
move temp.dat ..\..\Binary\hd1k_zzrcc_ram_prefix.dat move temp.dat ..\..\Binary\hd1k_zzrcc_ram_prefix.dat

8
Source/ZZRCC/ZZRCC Disk Layout.txt
View File

@ -4,8 +4,8 @@ ZZRCC Disk Prefix Layout
---- Bytes ---- --- Sectors --- ---- Bytes ---- --- Sectors ---
Start Length Start Length Description Start Length Start Length Description
------- ------- ------- ------- --------------------------- ------- ------- ------- ------- ---------------------------
0x00000 0x00100 0 0.5 CF Boot Loader
0x00100 0x00100 0.5 0.5 RomWBW Partition Table
0x00000 0x001BE 0 1 CF Boot Loader
0x001B8 0x00048 RomWBW Partition Table
0x00200 0x1EE00 1 247 Unused 0x00200 0x1EE00 1 247 Unused
0x1F000 0x01000 248 8 ZZRCC Monitor v0.5 0x1F000 0x01000 248 8 ZZRCC Monitor v0.5
0x20000 0x04000 256 32 Unused 0x20000 0x04000 256 32 Unused
@ -17,9 +17,9 @@ Notes
----- -----
- At startup CPLD ROM is mapped to Z280 CPU address space 0x0000-0x003F, CPU begins execution at 0x0000 - At startup CPLD ROM is mapped to Z280 CPU address space 0x0000-0x003F, CPU begins execution at 0x0000
- CPLD ROM (CF bootstrap mode) reads CF Boot Loader (256B) from start of CF (MBR) to 0xB000 and runs it
- CPLD ROM (CF bootstrap mode) reads CF Boot Loader (512B) from start of CF (MBR) to 0xB000 and runs it
- CF Boot Loader reads ZZRCC Monitor (4KB) from sectors 0xF8-0xFF of CF to 0xB400 and runs it - CF Boot Loader reads ZZRCC Monitor (4KB) from sectors 0xF8-0xFF of CF to 0xB400 and runs it
- ZZRCC Monitor reads 512KB (RomWBW) from sectors 0x120-0x51F of CF into first 512KB of physical RAM - ZZRCC Monitor reads 512KB (RomWBW) from sectors 0x120-0x51F of CF into first 512KB of physical RAM
- ZZRCC Monitor maps first 32KB of physical RAM to first 32KB of CPU RAM and starts execution at 0x0000 - ZZRCC Monitor maps first 32KB of physical RAM to first 32KB of CPU RAM and starts execution at 0x0000
-WBW 2:36 PM 10/8/2023
-WBW 3:30 PM 10/12/2023

BIN
Source/ZZRCC/zzrcc_cfldr.bin
View File

Binary file not shown.

BIN
Source/ZZRCC/zzrcc_ptbl.bin
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Binary file not shown.

2
Source/ver.inc
View File

@ -2,7 +2,7 @@
#DEFINE RMN 4 #DEFINE RMN 4
#DEFINE RUP 0 #DEFINE RUP 0
#DEFINE RTP 0 #DEFINE RTP 0
#DEFINE BIOSVER "3.4.0-dev.7"
#DEFINE BIOSVER "3.4.0-dev.8"
#define rmj RMJ #define rmj RMJ
#define rmn RMN #define rmn RMN
#define rup RUP #define rup RUP

2
Source/ver.lib
View File

@ -3,5 +3,5 @@ rmn equ 4
rup equ 0 rup equ 0
rtp equ 0 rtp equ 0
biosver macro biosver macro
db "3.4.0-dev.7"
db "3.4.0-dev.8"
endm endm

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