Add CPU Speed Control for HEATH Platform

Doc/ChangeLog.txt

@@ -35,6 +35,8 @@ Version 3.5
 - WBW: Support for Hitachi HD44780-based LCD display
 - DRJ: Added support for Genesis STD Bus Z180 platform
 - MAP: Improved section Disk Management in User Guide document
+- WBW: Add CPU speed selection for HEATH platform to HBIOS
+- WBW: Add Warm/Cold reboot options to CPUSPD utility
 
 Version 3.4
 -----------

ReadMe.md

@@ -3,7 +3,7 @@
 **RomWBW ReadMe** \
 Version 3.5 \
 Wayne Warthen  ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \
-06 Sep 2024
+11 Sep 2024
 
 # Overview
 

ReadMe.txt

@@ -1,6 +1,6 @@
 RomWBW ReadMe
 Wayne Warthen (wwarthen@gmail.com)
-06 Sep 2024
+11 Sep 2024
 
 
 

Source/Apps/cpuspd/cpuspd.asm

@@ -23,6 +23,12 @@ rtc_port	.equ	$70		; RTC latch port adr
 restart		.equ	$0000		; CP/M restart vector
 bdos		.equ	$0005		; BDOS invocation vector
 ;
+bf_sysreset	.equ	$F0		; restart system
+;
+bf_sysres_int	.equ	$00		; reset hbios internal
+bf_sysres_warm	.equ	$01		; warm start (restart boot loader)
+bf_sysres_cold	.equ	$02		; cold start
+;
 ident		.equ	$FFFE		; loc of RomWBW HBIOS ident ptr
 ;
 ;=======================================================================
@@ -113,6 +119,10 @@ main1:
 ;
 main2:
 	ret	z		; if end, nothing to do
+	cp	'W'		; warm boot?
+	jp	z,wboot		; if so, do it
+	cp	'C'		; cold boot?
+	jp	z,cboot		; if so, do it
 	cp	','		; no new speed?
 	jr	z,main2a	; go to wait states
 	; parse speed string (half, full, double)
@@ -161,6 +171,9 @@ parse_spd:
 	ld	c,2			; assume double speed
 	cp	'D'			; check it
 	jr	z,parse_spd1		; if equal, done
+	ld	c,3			; assume quad speed
+	cp	'Q'			; check it
+	jr	z,parse_spd1		; if equal, done
 	or	a			; clear CF
 	ccf				; set CF to indicate error
 	ret
@@ -222,6 +235,9 @@ show_spd:
 	ld	de,str_dbl
 	cp	2
 	jr	z,show_spd1
+	ld	de,str_quad
+	cp	3
+	jr	z,show_spd1
 	jp	err_invalid
 show_spd1:
 	call	prtstr
@@ -267,6 +283,24 @@ usage:
 	or	$FF
 	ret
 ;
+; Handle Warm Boot
+;
+wboot:
+	ld	de,str_warmboot		; message
+	call	prtstr			; display it
+	ld	b,bf_sysreset		; system restart
+	ld	c,bf_sysres_warm	; warm start
+	call	$fff0			; call hbios
+;
+; Handle Cold Boot
+;
+cboot:
+	ld	de,str_coldboot		; message
+	call	prtstr			; display it
+	ld	b,bf_sysreset		; system restart
+	ld	c,bf_sysres_cold	; cold start
+	call	$fff0			; call hbios
+;
 ; Error Handlers
 ;
 err_una:
@@ -510,9 +544,6 @@ prtd3m2:
 	call	prtchr
 prtd3m3:
 	ret
-
-
-
 ;
 ; Get the next non-blank character from (HL).
 ;
@@ -665,7 +696,7 @@ delay1:
 ; Constants
 ;=======================================================================
 ;
-str_banner		.db	"RomWBW CPU Speed Selector v0.6, 29-Dec-2023",0
+str_banner		.db	"RomWBW CPU Speed Selector v1.0, 11-Sep-2024",0
 str_spacer		.db	"  ",0
 str_oscspd		.db	" MHz Oscillator",0
 str_cpuspd		.db	"  CPU speed is ",0
@@ -674,8 +705,11 @@ str_mhz			.db	" MHz",0
 str_slow		.db	" (Half)",0
 str_full		.db	" (Full)",0
 str_dbl			.db	" (Double)",0
+str_quad		.db	" (Quad)",0
 str_memws		.db	" Memory Wait State(s)",0
 str_iows		.db	" I/O Wait State(s)",0
+str_warmboot		.db	"\r\n\r\nWarm booting...",0
+str_coldboot		.db	"\r\n\r\nCold booting...",0
 str_err_una		.db	"  ERROR: UNA not supported by application",0
 str_err_inv		.db	"  ERROR: Invalid BIOS (signature missing)",0
 str_err_ver		.db	"  ERROR: Unexpected HBIOS version",0
@@ -684,8 +718,10 @@ str_err_not_sup		.db	"  ERROR: Platform or configuration does not support CPU sp
 str_err_invalid		.db	"  ERROR: Invalid configuration!",0
 str_err_api		.db	"  ERROR: HBIOS API error!",0
 str_usage		.db	"  Usage: CPUSPD <cpuspd>,<memws>,<iows>\r\n"
+			.db	"         CPUSPD (W)armBoot\r\n"
+			.db	"         CPUSPD (C)oldBoot\r\n"
 			.db	"\r\n"
-			.db	"         <cpuspd>: \"Half\", \"Full\", or \"Double\"\r\n"
+			.db	"         <cpuspd>: (H)alf | (F)ull | (D)ouble | (Q)uad\r\n"
 			.db	"         <memws>:  Memory wait states\r\n"
 			.db	"         <iows>:   I/O wait states\r\n"
 			.db	"\r\n"

Source/Doc/Applications.md

@@ -1138,7 +1138,8 @@ reinitialised and the data previously stored will be lost.
 | Disk-based          |Yes|
 
 The `CPUSPD` application is used to change the running speed and wait
-states of a RomWBW system.
+states of a RomWBW system.  It can also be used to invoke a warm or
+cold reboot of the system.
 
 The functionality is highly dependent on the capabilities of your system.
 
@@ -1150,8 +1151,10 @@ configuration.
 #### Syntax
 
 | `CPUSPD [`*`<speed>`*`[,[`*`<memws>`*`][,[`*`<iows>`*`]]]`
+| `CPUSPD (W)armBoot`
+| `CPUSPD (C)oldBoot`
 
-*`<speed>`* is one of HALF, FULL, or DOUBLE.  
+*`<speed>`* is one of (H)alf, (F)ull, (D)ouble, or (Q)uad.  
 *`<memws>`* is a number specifying the desired memory wait states.  
 *`<iows>`* is a number specifying the desired I/O wait states.
 

Source/HBIOS/hbios.asm

@@ -1647,6 +1647,14 @@ Z280_INITZ:
 	OUT	(EIPC_SCDP),A		; SET SYSTEM CONTROL DATA PORT (SCDP)
 #ENDIF
 ;
+; HEATH BARE METAL INIT
+;
+#IF (PLATFORM == PLT_HEATH)
+	XOR	A			; 16 MHZ OPERATION?
+	OUT	(H8P_SPDIO),A		; IMPLEMENT IT
+	LD	(H8P_SPEED),A		; UPDATE FP SHADOW
+#ENDIF
+;
 ;--------------------------------------------------------------------------------------------------
 ; PLATFORM MEMORY MANAGEMENT INITIALIZATION
 ;--------------------------------------------------------------------------------------------------
@@ -5208,9 +5216,9 @@ SYS_GETCPUSPD:
 ;
 #IF (((PLATFORM == PLT_SBC) | (PLATFORM == PLT_MBC)) & (CPUSPDCAP==SPD_HILO))
 	LD	A,(HB_RTCVAL)
-#IF (PLATFORM == PLT_SBC)
+  #IF (PLATFORM == PLT_SBC)
 	XOR	%00001000		; SBC SPEED BIT IS INVERTED
-#ENDIF
+  #ENDIF
 	BIT	3,A
 	LD	L,0			; ASSUME HALF SPEED
 	JR	Z,SYS_GETCPUSPD1
@@ -5222,6 +5230,16 @@ SYS_GETCPUSPD1:
 	RET
 #ENDIF
 ;
+#IF (PLATFORM == PLT_HEATH)
+	LD	A,(H8P_SPEED)		; GET HEATH SPEED BITS SHADOW
+	XOR	$03			; CONVERT TO HBIOS VALUE
+	LD	L,A			; PUT IN L FOR RETURN
+	LD	DE,$FFFF		; UNKNOWN WAIT STATES
+;
+	XOR	A
+	RET
+#ENDIF
+;
 #IF (CPUFAM == CPU_Z180)
 	LD	HL,0			; INIT CPU SPEED TO HALF
 	LD	A,(HB_CPUTYPE)		; LOAD CPUTYPE
@@ -5369,7 +5387,7 @@ SYS_SETSECS:
 ;
 ; SET SYSTEM CPU SPEED ATTRIBUTES
 ;   ON ENTRY:
-;     L: CLOCK MULT (0:HALF, 1:FULL, 2: DOUBLE)
+;     L: CLOCK MULT (0:HALF, 1:FULL, 2: DOUBLE, 3: QUAD)
 ;     D: MEMORY WAIT STATES
 ;     E: I/O WAIT STATES
 ;
@@ -5435,6 +5453,48 @@ SYS_SETCPUSPD3:
 	RET
 #ENDIF
 ;
+#IF (PLATFORM == PLT_HEATH)
+	; PORT $30:
+	;   0=16MHZ, 1=8MHZ, 2=4MHZ, 3=2MHZ
+	LD	A,L			; REQUESTED SPEED TO ACCUM
+	XOR	$03			; CONVERT TO HEATH BITS
+	AND	$03			; ONLY 2 LS BITS
+	OUT	(H8P_SPDIO),A		; DO IT
+	LD	(H8P_SPEED),A		; UPDATE FP SHADOW
+;
+	; UPDATE CPUKHZ/CPMHZ
+	LD	HL,(HB_CPUOSC)		; START WITH OSC VALUE IN KHZ
+	LD	B,A			; USE BITS FOR LOOP COUNT
+	OR	A			; CHECK FOR ZERO
+	JR	Z,SYS_SETCPUSPD2	; IF SO, SKIP ADJUSTMENT LOOP
+SYS_SETCPUSPD1:
+	SRL	H			; DIVIDE
+	RR	L			; ... BY TWO
+	DJNZ	SYS_SETCPUSPD1		; LOOP AS NEEDED
+;
+SYS_SETCPUSPD2:
+;
+; HL SHOULD NOW HAVE FINAL CPU RUNNING SPEED IN KHZ.
+; UPDATE CB_CPUMHZ/CB_CPUKHZ WITH THIS VALUE.
+;
+	LD	(CB_CPUKHZ),HL		; UPDATE CPUKHZ
+	LD	DE,1000			; SET UP TO DIV BY 1000 FOR MHZ
+	CALL	DIV16			; BC=CPU MHZ, HL=REMAINDER
+	LD	DE,500			; SET UP TO ROUND UP
+	XOR	A			; IF WITHIN 500 KHZ
+	SBC	HL,DE			; REMAINDER - 500
+	CCF				; COMPLEMENT CF
+	ADC	A,C			; C -> A; ADD CF FOR ROUNDING
+	LD	(CB_CPUMHZ),A		; SAVE IT
+;
+	;  REINIT DELAY ROUTINE
+	LD	A,(CB_CPUMHZ)		; CPU SPEED TO ACCUM AND INIT
+	CALL	DELAY_INIT		; .. SPEED COMPENSATED DELAY
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET
+#ENDIF
+;
 #IF (CPUFAM == CPU_Z180)
 	; VERIFY THAT REQUESTED SETTINGS ARE ALLOWED BY HARDWARE
 	LD	A,L			; GET SPEED REQUESTED

Source/ver.inc

@@ -2,7 +2,7 @@
 #DEFINE	RMN	5
 #DEFINE	RUP	0
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.5.0-dev.79"
+#DEFINE BIOSVER	"3.5.0-dev.80"
 #define rmj	RMJ
 #define rmn	RMN
 #define rup	RUP

Source/ver.lib

@@ -3,5 +3,5 @@ rmn	equ	5
 rup	equ	0
 rtp	equ	0
 biosver	macro
-	db	"3.5.0-dev.79"
+	db	"3.5.0-dev.80"
 	endm