Browse Source

Configuration Files Cleanup

pull/48/head
Wayne Warthen 7 years ago
parent
commit
522b72d9df
  1. 1
      Doc/ChangeLog.txt
  2. 2
      ReadMe.txt
  3. 2
      Source/CBIOS/ver.inc
  4. 5
      Source/HBIOS/Build.ps1
  5. 23
      Source/HBIOS/Config/EZZ80_std.asm
  6. 51
      Source/HBIOS/Config/MK4_std.asm
  7. 29
      Source/HBIOS/Config/N8_std.asm
  8. 53
      Source/HBIOS/Config/RCZ180_ext.asm
  9. 52
      Source/HBIOS/Config/RCZ180_nat.asm
  10. 42
      Source/HBIOS/Config/RCZ80_std.asm
  11. 33
      Source/HBIOS/Config/SBC_simh.asm
  12. 47
      Source/HBIOS/Config/SBC_std.asm
  13. 53
      Source/HBIOS/Config/SC126_std.asm
  14. 19
      Source/HBIOS/Config/UNA_std.asm
  15. 27
      Source/HBIOS/Config/ZETA2_std.asm
  16. 27
      Source/HBIOS/Config/ZETA_std.asm
  17. 4
      Source/HBIOS/ay.asm
  18. 227
      Source/HBIOS/cfg_ezz80.asm
  19. 182
      Source/HBIOS/cfg_master.asm
  20. 246
      Source/HBIOS/cfg_mk4.asm
  21. 235
      Source/HBIOS/cfg_n8.asm
  22. 237
      Source/HBIOS/cfg_rcz180.asm
  23. 248
      Source/HBIOS/cfg_rcz80.asm
  24. 243
      Source/HBIOS/cfg_sbc.asm
  25. 232
      Source/HBIOS/cfg_sc126.asm
  26. 28
      Source/HBIOS/cfg_una.asm
  27. 155
      Source/HBIOS/cfg_zeta.asm
  28. 115
      Source/HBIOS/cfg_zeta2.asm
  29. 40
      Source/HBIOS/hbios.asm
  30. 7
      Source/HBIOS/ide.asm
  31. 20
      Source/HBIOS/plt_ezz80.inc
  32. 22
      Source/HBIOS/plt_mk4.inc
  33. 28
      Source/HBIOS/plt_n8.inc
  34. 18
      Source/HBIOS/plt_rcz180.inc
  35. 12
      Source/HBIOS/plt_rcz80.inc
  36. 28
      Source/HBIOS/plt_sbc.inc
  37. 12
      Source/HBIOS/plt_sc126.inc
  38. 4
      Source/HBIOS/plt_una.inc
  39. 14
      Source/HBIOS/plt_zeta.inc
  40. 21
      Source/HBIOS/plt_zeta2.inc
  41. 2
      Source/HBIOS/sd.asm
  42. 87
      Source/HBIOS/std.asm
  43. 12
      Source/HBIOS/tms.asm
  44. 8
      Source/HBIOS/uf.asm
  45. 2
      Source/HBIOS/ver.inc
  46. 11
      Source/Images/BuildHD.ps1
  47. BIN
      Source/Images/hd_cpm3/s0/u0/BDOS3.SPR
  48. BIN
      Source/Images/hd_cpm3/s0/u0/BNKBDOS3.SPR
  49. BIN
      Source/Images/hd_cpm3/s0/u0/CCP.COM
  50. BIN
      Source/Images/hd_cpm3/s0/u0/COPYSYS.COM
  51. BIN
      Source/Images/hd_cpm3/s0/u0/CPMLDR.REL
  52. BIN
      Source/Images/hd_cpm3/s0/u0/DATE.COM
  53. BIN
      Source/Images/hd_cpm3/s0/u0/DEVICE.COM
  54. BIN
      Source/Images/hd_cpm3/s0/u0/DIR.COM
  55. BIN
      Source/Images/hd_cpm3/s0/u0/DUMP.COM
  56. BIN
      Source/Images/hd_cpm3/s0/u0/ED.COM
  57. BIN
      Source/Images/hd_cpm3/s0/u0/ERASE.COM
  58. BIN
      Source/Images/hd_cpm3/s0/u0/GENCOM.COM
  59. BIN
      Source/Images/hd_cpm3/s0/u0/GENCPM.COM
  60. BIN
      Source/Images/hd_cpm3/s0/u0/GET.COM
  61. BIN
      Source/Images/hd_cpm3/s0/u0/HELP.COM
  62. BIN
      Source/Images/hd_cpm3/s0/u0/HELP.HLP
  63. BIN
      Source/Images/hd_cpm3/s0/u0/HEXCOM.CPM
  64. BIN
      Source/Images/hd_cpm3/s0/u0/PATCH.COM
  65. BIN
      Source/Images/hd_cpm3/s0/u0/PIP.COM
  66. BIN
      Source/Images/hd_cpm3/s0/u0/PUT.COM
  67. BIN
      Source/Images/hd_cpm3/s0/u0/R.COM
  68. 39
      Source/Images/hd_cpm3/s0/u0/README.1ST
  69. BIN
      Source/Images/hd_cpm3/s0/u0/RENAME.COM
  70. BIN
      Source/Images/hd_cpm3/s0/u0/RESBDOS3.SPR
  71. BIN
      Source/Images/hd_cpm3/s0/u0/SAVE.COM
  72. BIN
      Source/Images/hd_cpm3/s0/u0/SET.COM
  73. BIN
      Source/Images/hd_cpm3/s0/u0/SETDEF.COM
  74. BIN
      Source/Images/hd_cpm3/s0/u0/SHOW.COM
  75. BIN
      Source/Images/hd_cpm3/s0/u0/SUBMIT.COM
  76. BIN
      Source/Images/hd_cpm3/s0/u0/TYPE.COM
  77. BIN
      Source/Images/hd_cpm3/s0/u0/W.COM
  78. BIN
      Source/Images/hd_cpm3/s1/u0/ANAGRAM.COM
  79. 2
      Source/Images/hd_cpm3/s1/u0/CHAPTER1.DOC
  80. 2
      Source/Images/hd_cpm3/s1/u0/CHAPTER2.DOC
  81. 2
      Source/Images/hd_cpm3/s1/u0/CHAPTER3.DOC
  82. 74
      Source/Images/hd_cpm3/s1/u0/DIARY.DOC
  83. BIN
      Source/Images/hd_cpm3/s1/u0/DICTSORT.COM
  84. BIN
      Source/Images/hd_cpm3/s1/u0/FIND.COM
  85. BIN
      Source/Images/hd_cpm3/s1/u0/HOMONYMS.TXT
  86. 358
      Source/Images/hd_cpm3/s1/u0/HYEXCEPT.TXT
  87. BIN
      Source/Images/hd_cpm3/s1/u0/HYPHEN.COM
  88. BIN
      Source/Images/hd_cpm3/s1/u0/LOOKUP.COM
  89. BIN
      Source/Images/hd_cpm3/s1/u0/MAINDICT.CMP
  90. BIN
      Source/Images/hd_cpm3/s1/u0/MARKFIX.COM
  91. BIN
      Source/Images/hd_cpm3/s1/u0/MOVEPRN.COM
  92. 1877
      Source/Images/hd_cpm3/s1/u0/PATCH.LST
  93. 143
      Source/Images/hd_cpm3/s1/u0/PRINT.TST
  94. 2141
      Source/Images/hd_cpm3/s1/u0/READ.ME
  95. 15
      Source/Images/hd_cpm3/s1/u0/README
  96. BIN
      Source/Images/hd_cpm3/s1/u0/REVIEW.COM
  97. 22
      Source/Images/hd_cpm3/s1/u0/RULER.DOC
  98. 17
      Source/Images/hd_cpm3/s1/u0/SAMPLE1.DOC
  99. 15
      Source/Images/hd_cpm3/s1/u0/SAMPLE2.DOC
  100. 5
      Source/Images/hd_cpm3/s1/u0/SAMPLE3.DOC

1
Doc/ChangeLog.txt

@ -10,6 +10,7 @@ Version 2.9.2
- WBW: Add RC2014 Z180 AY sound support to TUNE app - WBW: Add RC2014 Z180 AY sound support to TUNE app
- WBW: Add RC2014 AY sound support to AY driver - WBW: Add RC2014 AY sound support to AY driver
- WBW: Add SC126 platform - WBW: Add SC126 platform
- WBW: Config files cleanup
Version 2.9.1 Version 2.9.1
------------- -------------

2
ReadMe.txt

@ -7,7 +7,7 @@
*********************************************************************** ***********************************************************************
Wayne Warthen (wwarthen@gmail.com) Wayne Warthen (wwarthen@gmail.com)
Version 2.9.2-pre.4, 2019-08-11
Version 2.9.2-pre.5, 2019-08-15
https://www.retrobrewcomputers.org/ https://www.retrobrewcomputers.org/
RomWBW is a ROM-based implementation of CP/M-80 2.2 and Z-System for RomWBW is a ROM-based implementation of CP/M-80 2.2 and Z-System for

2
Source/CBIOS/ver.inc

@ -2,4 +2,4 @@
#DEFINE RMN 9 #DEFINE RMN 9
#DEFINE RUP 2 #DEFINE RUP 2
#DEFINE RTP 0 #DEFINE RTP 0
#DEFINE BIOSVER "2.9.2-pre.4"
#DEFINE BIOSVER "2.9.2-pre.5"

5
Source/HBIOS/Build.ps1

@ -123,7 +123,7 @@ $TimeStamp = '"' + (Get-Date -Format 'yyyy-MM-dd') + '"'
# Function to run TASM and throw an exception if an error occurs. # Function to run TASM and throw an exception if an error occurs.
Function Asm($Component, $Opt, $Architecture=$CPUType, $Output="${Component}.bin", $List="${Component}.lst") Function Asm($Component, $Opt, $Architecture=$CPUType, $Output="${Component}.bin", $List="${Component}.lst")
{ {
$Cmd = "tasm -t${Architecture} -g3 ${Opt} ${Component}.asm ${Output} ${List}"
$Cmd = "tasm -t${Architecture} -g3 -e ${Opt} ${Component}.asm ${Output} ${List}"
$Cmd | write-host $Cmd | write-host
Invoke-Expression $Cmd | write-host Invoke-Expression $Cmd | write-host
if ($LASTEXITCODE -gt 0) {throw "TASM returned exit code $LASTEXITCODE"} if ($LASTEXITCODE -gt 0) {throw "TASM returned exit code $LASTEXITCODE"}
@ -150,8 +150,7 @@ Function Concat($InputFileList, $OutputFile)
; ;
#DEFINE TIMESTAMP ${TimeStamp} #DEFINE TIMESTAMP ${TimeStamp}
; ;
PLATFORM .EQU PLT_${Platform} ; HARDWARE PLATFORM
ROMSIZE .EQU ${ROMSize} ; SIZE OF ROM IN KB
ROMSIZE .EQU ${ROMSize}
; ;
#INCLUDE "${ConfigFile}" #INCLUDE "${ConfigFile}"
; ;

23
Source/HBIOS/Config/EZZ80_std.asm

@ -3,7 +3,26 @@
; EASY Z80 STANDARD CONFIGURATION ; EASY Z80 STANDARD CONFIGURATION
;================================================================================================== ;==================================================================================================
; ;
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
; YOUR FILE IN THE BUILD PROCESS.
;
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
; SETTINGS.
;
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
;
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
; DIRECTORIES ABOVE THIS ONE).
;
#include "cfg_ezz80.asm" #include "cfg_ezz80.asm"
; ;
CPUOSC .SET 10000000 ; CPU OSC FREQ
DEFSERCFG .SET SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG
CPUOSC .SET 10000000 ; CPU OSC FREQ IN MHZ
DEFSERCFG .SET SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)

51
Source/HBIOS/Config/MK4_std.asm

@ -3,28 +3,47 @@
; MARK IV STANDARD CONFIGURATION ; MARK IV STANDARD CONFIGURATION
;================================================================================================== ;==================================================================================================
; ;
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
; YOUR FILE IN THE BUILD PROCESS.
;
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
; SETTINGS.
;
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
;
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
; DIRECTORIES ABOVE THIS ONE).
;
#include "cfg_mk4.asm" #include "cfg_mk4.asm"
; ;
Z180_CLKDIV .SET 1 ; 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .SET 0 ; MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 1 ; ADD (0-3) I/O WAIT STATES ABOVE 1 W/S BUILT-IN
Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
; ;
FDENABLE .SET FALSE ; TRUE FOR FLOPPY DEVICE SUPPORT
FDMODE .SET FDMODE_DIDE ; FDMODE_DIO, FDMODE_DIDE, FDMODE_DIO3
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
; ;
IDEENABLE .SET TRUE ; TRUE FOR IDE DEVICE SUPPORT
IDEMODE .SET IDEMODE_MK4 ; IDEMODE_MK4, IDEMODE_DIO, IDEMODE_DIDE
VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
CVDUENABLE .SET TRUE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
VGAENABLE .SET TRUE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
; ;
PPIDEENABLE .SET FALSE ; TRUE FOR PPIDE DEVICE SUPPORT
PPIDEMODE .SET PPIDEMODE_MFP ; PPIDEMODE_MFP, PPPIDEMODE_DIO3
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .SET FDMODE_DIDE ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3]
; ;
SDENABLE .SET TRUE ; TRUE FOR SD DEVICE SUPPORT
SDMODE .SET SDMODE_MK4 ; SDMODE_MK4, SDMODE_DSD
IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
IDEMODE .SET IDEMODE_MK4 ; IDE: DRIVER MODE: IDEMODE_[DIO|DIDE]
; ;
PRPENABLE .SET TRUE ; TRUE FOR PROPIO BOARD SUPPORT (VIDEO, KBD, & SD CARD)
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDEMODE .SET PPIDEMODE_MFP ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC]
; ;
VGAENABLE .SET TRUE ; TRUE FOR VGA BOARD VIDEO & KBD SUPPORT
CVDUENABLE .SET TRUE ; TRUE FOR CVDU BOARD VIDEO & KBD SUPPORT
VDUENABLE .SET FALSE ; TRUE FOR VDU BOARD VIDEO & KBD SUPPORT
SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_MK4 ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC126]
; ;
CRTACT .SET FALSE ; TRUE TO ACTIVATE CRT AT STARTUP (BOOT ON CRT)
PRPENABLE .SET TRUE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)

29
Source/HBIOS/Config/N8_std.asm

@ -3,12 +3,31 @@
; N8 STANDARD CONFIGURATION ; N8 STANDARD CONFIGURATION
;================================================================================================== ;==================================================================================================
; ;
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
; YOUR FILE IN THE BUILD PROCESS.
;
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
; SETTINGS.
;
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
;
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
; DIRECTORIES ABOVE THIS ONE).
;
#include "cfg_n8.asm" #include "cfg_n8.asm"
; ;
Z180_CLKDIV .SET 1 ; 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .SET 1 ; MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 3 ; ADD (0-3) I/O WAIT STATES ABOVE 1 W/S BUILT-IN
Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .SET 1 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 3 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
; ;
SDMODE .SET SDMODE_CSIO ; FOR N8 PROTOTYPE (DATECODE 2511), USE SDMODE_N8
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
; ;
CRTACT .SET FALSE ; TRUE TO ACTIVATE CRT AT STARTUP (BOOT ON CRT)
SDMODE .SET SDMODE_CSIO ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)

53
Source/HBIOS/Config/RCZ180_ext.asm

@ -1,27 +1,48 @@
; ;
;================================================================================================== ;==================================================================================================
; RC2014 W/ Z180 CPU USING EXTERNAL MEMORY MANAGER -- 512K RAM/ROM MODULE
; RC2014 Z180 STANDARD CONFIGURATION (EXTERNAL 512K RAM/ROM BANKED MEMORY MODULE)
;================================================================================================== ;==================================================================================================
; ;
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
; YOUR FILE IN THE BUILD PROCESS.
;
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
; SETTINGS.
;
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
;
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
; DIRECTORIES ABOVE THIS ONE).
;
#include "cfg_rcz180.asm" #include "cfg_rcz180.asm"
; ;
MEMMGR .SET MM_Z2 ; 512K RAM/ROM MODULE MEM MGR
Z180_CLKDIV .SET 1 ; 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .SET 0 ; MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 1 ; ADD (0-3) I/O WAIT STATES ABOVE 1 W/S BUILT-IN
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ
DEFSERCFG .SET SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
MEMMGR .SET MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
;
Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
; ;
CPUOSC .SET 18432000 ; CPU OSC FREQ
DEFSERCFG .SET SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG
DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
; ;
ASCIENABLE .SET TRUE ; TRUE FOR Z180 ASCI SUPPORT
SIOENABLE .SET FALSE ; TRUE TO AUTO-DETECT ZILOG SIO/2
ACIAENABLE .SET FALSE ; TRUE TO AUTO-DETECT MOTOROLA 6850 ACIA
ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
; ;
FDENABLE .SET FALSE ; TRUE FOR FLOPPY SUPPORT
FDMODE .SET FDMODE_RCWDC ; FDMODE_RCSMC, FDMODE_RCWDC
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3]
; ;
IDEENABLE .SET TRUE ; TRUE FOR IDE DEVICE SUPPORT (CF MODULE)
IDEMODE .SET IDEMODE_RC ; TYPE OF CF MODULE: IDEMODE_RC, IDEMODE_SMB
PPIDEENABLE .SET FALSE ; TRUE FOR PPIDE DEVICE SUPPORT (PPIDE MODULE)
IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
IDEMODE .SET IDEMODE_RC ; IDE: DRIVER MODE: IDEMODE_[DIO|DIDE]
; ;
DSRTCENABLE .SET FALSE ; DS-1302 CLOCK DRIVER
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)

52
Source/HBIOS/Config/RCZ180_nat.asm

@ -1,26 +1,48 @@
; ;
;================================================================================================== ;==================================================================================================
; RC2014 W/ Z180 CPU USING NATIVE Z180 MEMORY MANAGER
; RC2014 Z180 STANDARD CONFIGURATION (NATIVE Z180 LINEAR MEMORY)
;================================================================================================== ;==================================================================================================
; ;
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
; YOUR FILE IN THE BUILD PROCESS.
;
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
; SETTINGS.
;
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
;
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
; DIRECTORIES ABOVE THIS ONE).
;
#include "cfg_rcz180.asm" #include "cfg_rcz180.asm"
; ;
Z180_CLKDIV .SET 1 ; 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .SET 0 ; MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 1 ; ADD (0-3) I/O WAIT STATES ABOVE 1 W/S BUILT-IN
CPUOSC .SET 18432000 ; CPU FAMILY: CPU_[Z80|Z180]
DEFSERCFG .SET SER_38400_8N1 ; HARDWARE BIOS: BIOS_[WBW|UNA]
;
MEMMGR .SET MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
;
Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
; ;
CPUOSC .SET 18432000 ; CPU OSC FREQ
DEFSERCFG .SET SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG
DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
; ;
ASCIENABLE .SET TRUE ; TRUE FOR Z180 ASCI SUPPORT
SIOENABLE .SET FALSE ; TRUE TO AUTO-DETECT ZILOG SIO/2
ACIAENABLE .SET FALSE ; TRUE TO AUTO-DETECT MOTOROLA 6850 ACIA
ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
; ;
FDENABLE .SET FALSE ; TRUE FOR FLOPPY SUPPORT
FDMODE .SET FDMODE_RCWDC ; FDMODE_RCSMC, FDMODE_RCWDC
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3]
; ;
IDEENABLE .SET TRUE ; TRUE FOR IDE DEVICE SUPPORT (CF MODULE)
IDEMODE .SET IDEMODE_RC ; TYPE OF CF MODULE: IDEMODE_RC, IDEMODE_SMB
PPIDEENABLE .SET FALSE ; TRUE FOR PPIDE DEVICE SUPPORT (PPIDE MODULE)
IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
IDEMODE .SET IDEMODE_RC ; IDE: DRIVER MODE: IDEMODE_[DIO|DIDE]
; ;
DSRTCENABLE .SET FALSE ; DS-1302 CLOCK DRIVER
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)

42
Source/HBIOS/Config/RCZ80_std.asm

@ -1,21 +1,41 @@
; ;
;================================================================================================== ;==================================================================================================
; RC2014 STANDARD CONFIGURATION
; RC2014 Z80 STANDARD CONFIGURATION
;================================================================================================== ;==================================================================================================
; ;
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
; YOUR FILE IN THE BUILD PROCESS.
;
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
; SETTINGS.
;
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
;
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
; DIRECTORIES ABOVE THIS ONE).
;
#include "cfg_rcz80.asm" #include "cfg_rcz80.asm"
; ;
CPUOSC .SET 7372800 ; CPU OSC FREQ
DEFSERCFG .SET SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE)
CPUOSC .SET 7372800 ; CPU OSC FREQ IN MHZ
DEFSERCFG .SET SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
; ;
SIOENABLE .SET TRUE ; TRUE TO AUTO-DETECT ZILOG SIO/2
ACIAENABLE .SET TRUE ; TRUE TO AUTO-DETECT MOTOROLA 6850 ACIA
ACIAENABLE .SET TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
; ;
FDENABLE .SET FALSE ; TRUE FOR FLOPPY SUPPORT
FDMODE .SET FDMODE_RCWDC ; FDMODE_RCSMC, FDMODE_RCWDC
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3]
; ;
IDEENABLE .SET TRUE ; TRUE FOR IDE DEVICE SUPPORT (CF MODULE)
IDEMODE .SET IDEMODE_RC ; TYPE OF CF MODULE: IDEMODE_RC, IDEMODE_SMB
PPIDEENABLE .SET FALSE ; TRUE FOR PPIDE DEVICE SUPPORT (PPIDE MODULE)
IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
IDEMODE .SET IDEMODE_RC ; IDE: DRIVER MODE: IDEMODE_[DIO|DIDE]
; ;
DSRTCENABLE .SET FALSE ; DS-1302 CLOCK DRIVER
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)

33
Source/HBIOS/Config/SBC_simh.asm

@ -3,12 +3,35 @@
; SBC SIMH EMULATOR CONFIGURATION ; SBC SIMH EMULATOR CONFIGURATION
;================================================================================================== ;==================================================================================================
; ;
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
; YOUR FILE IN THE BUILD PROCESS.
;
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
; SETTINGS.
;
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
;
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
; DIRECTORIES ABOVE THIS ONE).
;
#DEFINE PLATFORM_NAME "SBC (simh)"
;
#include "cfg_sbc.asm" #include "cfg_sbc.asm"
; ;
INTMODE .SET 1 ; INT MODE 1
HTIMENABLE .SET TRUE ; SIMH TIMER
INTMODE .SET 1 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
;
HTIMENABLE .SET TRUE ; ENABLE SIMH TIMER SUPPORT
;
SIMRTCENABLE .SET TRUE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
; ;
DSRTCENABLE .SET FALSE ; DS-1302 CLOCK DRIVER
SIMRTCENABLE .SET TRUE ; SIMH CLOCK DRIVER
DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
; ;
HDSKENABLE .SET TRUE ; TRUE FOR SIMH HDSK SUPPORT
HDSKENABLE .SET TRUE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)

47
Source/HBIOS/Config/SBC_std.asm

@ -3,26 +3,43 @@
; SBC STANDARD CONFIGURATION ; SBC STANDARD CONFIGURATION
;================================================================================================== ;==================================================================================================
; ;
#include "cfg_sbc.asm"
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
; YOUR FILE IN THE BUILD PROCESS.
;
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
; SETTINGS.
;
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
; ;
FDENABLE .SET FALSE ; TRUE FOR FLOPPY DEVICE SUPPORT
FDMODE .SET FDMODE_DIO3 ; FDMODE_DIO, FDMODE_DIDE, FDMODE_DIO3
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
; DIRECTORIES ABOVE THIS ONE).
;
#include "cfg_sbc.asm"
; ;
IDEENABLE .SET FALSE ; TRUE FOR IDE DEVICE SUPPORT
IDEMODE .SET IDEMODE_DIO ; IDEMODE_DIO, IDEMODE_DIDE
CRTACT .SET TRUE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
; ;
PPIDEENABLE .SET TRUE ; TRUE FOR PPIDE DEVICE SUPPORT
PPIDEMODE .SET PPIDEMODE_SBC ; PPIDEMODE_SBC, PPPIDEMODE_DIO3, PPIDEMODE_MFP
VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
CVDUENABLE .SET TRUE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
VGAENABLE .SET TRUE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
; ;
SDENABLE .SET FALSE ; TRUE FOR SD DEVICE SUPPORT
SDMODE .SET SDMODE_PPI ; SDMODE_JUHA, SDMODE_PPI, SDMODE_DSD
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .SET FDMODE_DIO3 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3]
; ;
PRPENABLE .SET TRUE ; TRUE FOR PROPIO BOARD SUPPORT (VIDEO, KBD, & SD CARD)
IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
IDEMODE .SET IDEMODE_DIO ; IDE: DRIVER MODE: IDEMODE_[DIO|DIDE]
; ;
VGAENABLE .SET TRUE ; TRUE FOR VGA BOARD VIDEO & KBD SUPPORT
CVDUENABLE .SET TRUE ; TRUE FOR CVDU BOARD VIDEO & KBD SUPPORT
VDUENABLE .SET FALSE ; TRUE FOR VDU BOARD VIDEO & KBD SUPPORT
VDUSIZ .SET V80X24 ; DEFAULT VDU FORMAT IF ACTIVE
PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDEMODE .SET PPIDEMODE_SBC ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC]
; ;
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC126]
; ;
CRTACT .SET TRUE ; TRUE TO ACTIVATE CRT AT STARTUP (BOOT ON CRT)
PRPENABLE .SET TRUE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)

53
Source/HBIOS/Config/SC126_std.asm

@ -1,29 +1,46 @@
; ;
;================================================================================================== ;==================================================================================================
; SC126
; SC126 STANDARD CONFIGURATION
;================================================================================================== ;==================================================================================================
; ;
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
; YOUR FILE IN THE BUILD PROCESS.
;
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
; SETTINGS.
;
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
;
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
; DIRECTORIES ABOVE THIS ONE).
;
#include "cfg_sc126.asm" #include "cfg_sc126.asm"
; ;
Z180_CLKDIV .SET 1 ; 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .SET 0 ; MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 1 ; ADD (0-3) I/O WAIT STATES ABOVE 1 W/S BUILT-IN
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ
DEFSERCFG .SET SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
; ;
CPUOSC .SET 18432000 ; CPU OSC FREQ
DEFSERCFG .SET SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG
ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
; ;
ASCIENABLE .SET TRUE ; TRUE FOR Z180 ASCI SUPPORT
SIOENABLE .SET FALSE ; TRUE TO AUTO-DETECT ZILOG SIO/2
ACIAENABLE .SET FALSE ; TRUE TO AUTO-DETECT MOTOROLA 6850 ACIA
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3]
; ;
FDENABLE .SET FALSE ; TRUE FOR FLOPPY SUPPORT
FDMODE .SET FDMODE_RCWDC ; FDMODE_RCSMC, FDMODE_RCWDC
IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
IDEMODE .SET IDEMODE_RC ; IDE: DRIVER MODE: IDEMODE_[DIO|DIDE]
; ;
IDEENABLE .SET TRUE ; TRUE FOR IDE DEVICE SUPPORT (CF MODULE)
IDEMODE .SET IDEMODE_RC ; TYPE OF CF MODULE: IDEMODE_RC, IDEMODE_SMB
PPIDEENABLE .SET FALSE ; TRUE FOR PPIDE DEVICE SUPPORT (PPIDE MODULE)
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
; ;
SDENABLE .SET TRUE ; TRUE FOR SD SUPPORT
SDMODE .SET SDMODE_SC126 ; SDMODE_JUHA, SDMODE_CSIO, SDMODE_UART, SDMODE_PPI, SDMODE_DSD
SDTRACE .SET 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
SDCSIOFAST .SET TRUE ; TABLE-DRIVEN BIT INVERTER
SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)

19
Source/HBIOS/Config/UNA_std.asm

@ -3,5 +3,24 @@
; UNA STANDARD CONFIGURATION ; UNA STANDARD CONFIGURATION
;================================================================================================== ;==================================================================================================
; ;
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
; YOUR FILE IN THE BUILD PROCESS.
;
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
; SETTINGS.
;
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
;
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
; DIRECTORIES ABOVE THIS ONE).
;
#include "cfg_una.asm" #include "cfg_una.asm"
; ;

27
Source/HBIOS/Config/ZETA2_std.asm

@ -3,12 +3,31 @@
; ZETA2 STANDARD CONFIGURATION ; ZETA2 STANDARD CONFIGURATION
;================================================================================================== ;==================================================================================================
; ;
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
; YOUR FILE IN THE BUILD PROCESS.
;
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
; SETTINGS.
;
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
;
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
; DIRECTORIES ABOVE THIS ONE).
;
#include "cfg_zeta2.asm" #include "cfg_zeta2.asm"
; ;
PPIDEENABLE .SET FALSE ; TRUE FOR PPIDE DEVICE SUPPORT
CRTACT .SET TRUE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
; ;
SDENABLE .SET FALSE ; TRUE FOR SD DEVICE SUPPORT
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
; ;
PPPENABLE .SET TRUE ; TRUE FOR PROPIO BOARD SUPPORT (VIDEO, KBD, & SD CARD)
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
; ;
CRTACT .SET TRUE ; TRUE TO ACTIVATE CRT AT STARTUP (BOOT ON CRT)
PPPENABLE .SET TRUE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)

27
Source/HBIOS/Config/ZETA_std.asm

@ -3,12 +3,31 @@
; ZETA STANDARD CONFIGURATION ; ZETA STANDARD CONFIGURATION
;================================================================================================== ;==================================================================================================
; ;
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
; YOUR FILE IN THE BUILD PROCESS.
;
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
; SETTINGS.
;
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
;
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
; DIRECTORIES ABOVE THIS ONE).
;
#include "cfg_zeta.asm" #include "cfg_zeta.asm"
; ;
PPIDEENABLE .SET FALSE ; TRUE FOR PPIDE DEVICE SUPPORT
CRTACT .SET TRUE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
; ;
SDENABLE .SET FALSE ; TRUE FOR SD DEVICE SUPPORT
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
; ;
PPPENABLE .SET TRUE ; TRUE FOR PROPIO BOARD SUPPORT (VIDEO, KBD, & SD CARD)
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
; ;
CRTACT .SET TRUE ; TRUE TO ACTIVATE CRT AT STARTUP (BOOT ON CRT)
PPPENABLE .SET TRUE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)

4
Source/HBIOS/ay.asm

@ -11,8 +11,8 @@ AY_ACR .EQU $9C
#ENDIF #ENDIF
; ;
#IF (AYMODE == AYMODE_N8) #IF (AYMODE == AYMODE_N8)
AY_RSEL .EQU N8_PSG+0
AY_RDAT .EQU N8_PSG+1
AY_RSEL .EQU $9C
AY_RDAT .EQU $9D
AY_ACR .EQU N8_DEFACR AY_ACR .EQU N8_DEFACR
#ENDIF #ENDIF
; ;

227
Source/HBIOS/cfg_ezz80.asm

@ -3,107 +3,130 @@
; ROMWBW 2.X CONFIGURATION DEFAULTS FOR EASY Z80 ; ROMWBW 2.X CONFIGURATION DEFAULTS FOR EASY Z80
;================================================================================================== ;==================================================================================================
; ;
; BUILD CONFIGURATION OPTIONS
;
CPUOSC .EQU 10000000 ; CPU OSC FREQ
MEMMGR .EQU MM_Z2 ; MM_NONE, MM_SBC, MM_Z2, MM_N8, MM_Z180
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!!
DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE)
INTMODE .EQU 2 ; 0=NONE, 1=INT MODE 1, 2=INT MODE 2
DIAGENABLE .EQU FALSE ; TRUE FOR DIAGNOSTIC CODE PORT OUTPUT
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
; UNDER THIS DIRECTORY.
;
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
; FOR THE PLATFORM.
;
#DEFINE PLATFORM_NAME "EASYZ80"
;
PLATFORM .EQU PLT_EZZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SC126]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
;
BOOTTYPE .EQU BT_MENU ; BT_[MENU|AUTO], IF AUTO, BOOT DEFAULT AFTER TIMEOUT
BOOT_TIMEOUT .EQU 20 ; AUTO BOOT TIMEOUT IN SECONDS, 0 FOR IMMEDIATE BOOT
BOOT_DEFAULT .EQU 'Z' ; AUTO BOOT SELECTION TO INVOKE AT TIMEOUT
;
CPUOSC .EQU 10000000 ; CPU OSC FREQ IN MHZ
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
;
RTC .EQU $C0 ; RTC LATCH REGISTER ADR
WDOG .EQU $6F ; WATCHDOG REGISTER ADR
;
CTCENABLE .EQU TRUE ; ENABLE ZILOG CTC SUPPORT
CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS
;
DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS
; ;
CRTACT .EQU FALSE ; CRT ACTIVATION AT STARTUP
VDAEMU .EQU EMUTYP_ANSI ; DEFAULT VDA EMULATION (EMUTYP_TTY, EMUTYP_ANSI, ...)
;
DSKYENABLE .EQU FALSE ; TRUE FOR DSKY SUPPORT (DO NOT COMBINE WITH PPIDE)
;
HTIMENABLE .EQU FALSE ; TRUE FOR SIMH TIMER SUPPORT
SIMRTCENABLE .EQU FALSE ; SIMH CLOCK DRIVER
DSRTCENABLE .EQU FALSE ; DS-1302 CLOCK DRIVER
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTCMODE_STD, DSRTCMODE_MFPIC
DSRTCCHG .EQU FALSE ; DS-1302 CONFIGURE CHARGE ON (TRUE) OR OFF (FALSE)
;
ASCIENABLE .EQU FALSE ; TRUE FOR Z180 ASCI SUPPORT
UARTENABLE .EQU FALSE ; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
UARTOSC .EQU 1843200 ; UART OSC FREQUENCY
ACIAENABLE .EQU FALSE ; TRUE FOR MOTOROLA 6850 ACIA SUPPORT
;
SIOENABLE .EQU TRUE ; TRUE FOR ZILOG SIO SUPPORT
SIODEBUG .EQU FALSE ; PS
SIOCNT .EQU 2 ; 1 OR 2 SIO CHIPS (EACH CHIP HAS 2 CHANNELS)
SIO0MODE .EQU SIOMODE_EZZ80 ; TYPE OF FIRST SIO TO DETECT: SIOMODE_RC/SMB/ZP/EZZ80
SIO0BASE .EQU $80 ; IO PORT ADDRESS BASE FOR FIRST SIO CHIP
SIO0ACLK .EQU 1843200 ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
SIO0ADIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
SIO0ACFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG
SIO0BCLK .EQU 1843200 ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
SIO0BDIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
SIO0BCFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG
SIO1MODE .EQU SIOMODE_RC ; TYPE OF SECOND SIO TO DETECT: SIOMODE_RC, SIOMODE_SMB
SIO1BASE .EQU $84 ; IO PORT ADDRESS BASE FOR SECOND SIO CHIP
SIO1ACLK .EQU 7372800 ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
SIO1ADIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
SIO1ACFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG
SIO1BCLK .EQU 7372800 ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
SIO1BDIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
SIO1BCFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG
;
VDUENABLE .EQU FALSE ; TRUE FOR VDU BOARD SUPPORT
CVDUENABLE .EQU FALSE ; TRUE FOR CVDU BOARD SUPPORT
NECENABLE .EQU FALSE ; TRUE FOR uPD7220 BOARD SUPPORT
TMSENABLE .EQU FALSE ; TRUE FOR N8 (TMS9918) VIDEO/KBD SUPPORT
VGAENABLE .EQU FALSE ; TRUE FOR VGA VIDEO/KBD SUPPORT
;
SPKENABLE .EQU FALSE ; TRUE FOR RTC LATCH IOBIT SOUND
AYENABLE .EQU FALSE ; TRUE FOR AY PSG SOUND
AYMODE .EQU AYMODE_RCZ80 ; AYMODE_[SCG/N8/RCZ80/RCZ180]
;
MDENABLE .EQU TRUE ; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENABLED)
MDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE)
;
FDENABLE .EQU FALSE ; TRUE FOR FLOPPY SUPPORT
FDMODE .EQU FDMODE_RCWDC ; FDMODE_DIO, FDMODE_ZETA, FDMODE_DIDE, FDMODE_N8, FDMODE_DIO3
FDTRACE .EQU 1 ; 0=SILENT, 1=FATAL ERRORS, 2=ALL ERRORS, 3=EVERYTHING (ONLY RELEVANT IF FDENABLE = TRUE)
FDMEDIA .EQU FDM144 ; FDM720, FDM144, FDM360, FDM120 (ONLY RELEVANT IF FDENABLE = TRUE)
FDMEDIAALT .EQU FDM720 ; ALTERNATE MEDIA TO TRY, SAME CHOICES AS ABOVE (ONLY RELEVANT IF FDMAUTO = TRUE)
FDMAUTO .EQU TRUE ; SELECT BETWEEN MEDIA OPTS ABOVE AUTOMATICALLY
;
RFENABLE .EQU FALSE ; TRUE FOR RAM FLOPPY SUPPORT
;
IDEENABLE .EQU TRUE ; TRUE FOR IDE SUPPORT
IDEMODE .EQU IDEMODE_RC ; IDEMODE_DIO, IDEMODE_DIDE, IDEMODE_RC
IDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
IDE8BIT .EQU TRUE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
;
PPIDEENABLE .EQU FALSE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_RC ; PPIDEMODE_SBC, PPPIDEMODE_DIO3, PPIDEMODE_MFP, PPIDEMODE_N8, PPIDEMODE_RC
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
;
SDENABLE .EQU FALSE ; TRUE FOR SD SUPPORT
SDMODE .EQU SDMODE_PPI ; SDMODE_JUHA, SDMODE_CSIO, SDMODE_UART, SDMODE_PPI, SDMODE_DSD
SDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
SDCSIOFAST .EQU FALSE ; TABLE-DRIVEN BIT INVERTER
;
PRPENABLE .EQU FALSE ; TRUE FOR PROPIO SUPPORT
;
PPPENABLE .EQU FALSE ; TRUE FOR PARPORTPROP SUPPORT
PPPSDENABLE .EQU TRUE ; TRUE FOR PARPORTPROP SD SUPPORT
PPPSDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPPENABLE = TRUE)
PPPCONENABLE .EQU TRUE ; TRUE FOR PROPIO CONSOLE SUPPORT (PS/2 KBD & VGA VIDEO)
;
HDSKENABLE .EQU FALSE ; TRUE FOR SIMH HDSK SUPPORT
;
TERMENABLE .EQU FALSE ; TERM PSEUDO DEVICE, WILL BE ENABLED IF A VDA IS ENABLED
;
BOOTTYPE .EQU BT_MENU ; BT_MENU (WAIT FOR KEYPRESS), BT_AUTO (BOOT_DEFAULT AFTER BOOT_TIMEOUT SECS)
BOOT_TIMEOUT .EQU 20 ; APPROX TIMEOUT IN SECONDS FOR AUTOBOOT, 0 FOR IMMEDIATE
BOOT_DEFAULT .EQU 'Z' ; SELECTION TO INVOKE AT TIMEOUT
;
PIO_4P .EQU FALSE ; TRUE FOR ECB-4PIO PIO SUPPORT
PIO_ZP .EQU FALSE ; TRUE FOR ECB-ZILOG PERIPHERALS BOARD
PPI_SBC .EQU FALSE ; TRUE FOR SBC V2 8255 (IF NOT BEING USED FOR PPIDE)
;
UFENABLE .EQU FALSE ; TRUE FOR ECB USB-FIFO SUPPORT
DSKYENABLE .EQU FALSE ; ENABLES DSKY (DO NOT COMBINE WITH PPIDE)
;
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
;
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
;
DSRTCENABLE .EQU FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
;
UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
;
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
;
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
;
SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
SIO0MODE .EQU SIOMODE_EZZ80 ; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .EQU 1843200 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0ADIV .EQU 1 ; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO0ACFG .EQU DEFSERCFG ; AIO 0A: SERIAL LINE CONFIG
SIO0BCLK .EQU 1843200 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0BDIV .EQU 1 ; SIO 0B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR
SIO1ACLK .EQU 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO1ADIV .EQU 1 ; SIO 1A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO1ACFG .EQU DEFSERCFG ; AIO 1A: SERIAL LINE CONFIG
SIO1BCLK .EQU 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO1BDIV .EQU 1 ; SIO 1B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO1BCFG .EQU DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG
;
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
NECENABLE .EQU FALSE ; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
;
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
;
AYENABLE .EQU FALSE ; AY: ENABLE AY PSG SOUND DRIVER
AYMODE .EQU AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG/N8/RCZ80/RCZ180]
;
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
;
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3]
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
FDMEDIA .EQU FDM144 ; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
FDMEDIAALT .EQU FDM720 ; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
;
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
;
IDEENABLE .EQU TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
IDEMODE .EQU IDEMODE_RC ; IDE: DRIVER MODE: IDEMODE_[DIO|DIDE]
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
IDE8BIT .EQU TRUE ; IDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDEMODE .EQU PPIDEMODE_RC ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC]
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC126]
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
;
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
;
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
;
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
;
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
;
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)

182
Source/HBIOS/cfg_master.asm

@ -0,0 +1,182 @@
;
;==================================================================================================
; ROMWBW 2.X CONFIGURATION MASTER
;==================================================================================================
;
; THIS FILE IS *NOT* A REAL CONFIGURATION FILE. IT IS A MASTER TEMPLATE FILE
; CONTAINING ALL POSSIBLE CONFIGURATION SETTINGS ACROSS ALL PLATFORMS. IT IS
; USED ONLY AS A REFERENCE TO HELP MANAGE THE FULL SET OF POSSIBLE SETTINGS AND
; KEEP THINGS CONSISTENT.
;
#DEFINE PLATFORM_NAME "ROMWBW"
;
PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SC126]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
;
BOOTTYPE .EQU BT_MENU ; BT_[MENU|AUTO], IF AUTO, BOOT DEFAULT AFTER TIMEOUT
BOOT_TIMEOUT .EQU 20 ; AUTO BOOT TIMEOUT IN SECONDS, 0 FOR IMMEDIATE BOOT
BOOT_DEFAULT .EQU 'Z' ; AUTO BOOT SELECTION TO INVOKE AT TIMEOUT
;
CPUOSC .EQU 8000000 ; CPU OSC FREQ IN MHZ
INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
MEMMGR .EQU MM_NONE ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
RAMBIAS .EQU 0 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
MPCL_ROM .EQU $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
;
Z180_BASE .EQU $40 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
;
N8_PPI0 .EQU $80 ; N8: FIRST PARALLEL PORT REGISTERS BASE ADR
N8_PPI1 .EQU $84 ; N8: SECOND PARALLEL PORT REGISTERS BASE ADR
N8_RTC .EQU $88 ; N8: RTC LATCH REGISTER ADR
N8_ACR .EQU $94 ; N8: AUXILLARY CONTROL REGISTER (ACR) ADR
N8_RMAP .EQU $96 ; N8: ROM PAGE REGISTER ADR
N8_DEFACR .EQU $1B ; N8: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE)
;
MK4_IDE .EQU $80 ; MK4: IDE REGISTERS BASE ADR
MK4_XAR .EQU $88 ; MK4: EXTERNAL ADDRESS REGISTER (XAR) ADR
MK4_SD .EQU $89 ; MK4: SD CARD CONTROL REGISTER ADR
MK4_RTC .EQU $8A ; MK4: RTC LATCH REGISTER ADR
;
RTC .EQU $70 ; RTC LATCH REGISTER ADR
WDOG .EQU $6F ; WATCHDOG REGISTER ADR
PPIBASE .EQU $60 ; PRIMARY PARALLEL PORT REGISTERS BASE ADR
;
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
CTCBASE .EQU $20 ; CTC BASE I/O ADDRESS
;
DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS
;
DSKYENABLE .EQU FALSE ; ENABLES DSKY (DO NOT COMBINE WITH PPIDE)
;
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
;
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
;
DSRTCENABLE .EQU FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
;
UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
;
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
;
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
ACIADEBUG .EQU FALSE ; ACIA: ENABLE DEBUG OUTPUT
ACIACNT .EQU 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
ACIA0BASE .EQU $80 ; ACIA 0: REGISTERS BASE ADR
ACIA0CLK .EQU CPUOSC ; ACIA 0: OSC FREQ IN HZ
ACIA0DIV .EQU 1 ; ACIA 0: SERIAL CLOCK DIVIDER
ACIA0CFG .EQU DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM)
ACIA1BASE .EQU $40 ; ACIA 1: REGISTERS BASE ADR
ACIA1CLK .EQU CPUOSC ; ACIA 1: OSC FREQ IN HZ
ACIA1DIV .EQU 1 ; ACIA 1: SERIAL CLOCK DIVIDER
ACIA1CFG .EQU DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM)
;
SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0ADIV .EQU 1 ; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO0ACFG .EQU DEFSERCFG ; AIO 0A: SERIAL LINE CONFIG
SIO0BCLK .EQU CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0BDIV .EQU 1 ; SIO 0B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR
SIO1ACLK .EQU CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO1ADIV .EQU 1 ; SIO 1A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO1ACFG .EQU DEFSERCFG ; AIO 1A: SERIAL LINE CONFIG
SIO1BCLK .EQU CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO1BDIV .EQU 1 ; SIO 1B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO1BCFG .EQU DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG
;
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
VDUSIZ .EQU V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
NECENABLE .EQU FALSE ; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
TMSMODE .EQU TMSMODE_NONE ; TMS: DRIVER MODE: TMSMODE_[SCG/N8]
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
;
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
;
AYENABLE .EQU FALSE ; AY: ENABLE AY PSG SOUND DRIVER
AYMODE .EQU AYMODE_NONE ; AY: DRIVER MODE: AYMODE_[SCG/N8/RCZ80/RCZ180]
;
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
;
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .EQU FDMODE_NONE ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3]
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
FDMEDIA .EQU FDM144 ; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
FDMEDIAALT .EQU FDM720 ; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
;
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
RFCNT .EQU 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-2)
;
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
IDEMODE .EQU IDEMODE_NONE ; IDE: DRIVER MODE: IDEMODE_[DIO|DIDE]
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
IDE8BIT .EQU FALSE ; IDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDEMODE .EQU PPIDEMODE_NONE ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC]
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_NONE ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC126]
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
;
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
;
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
PPPSDENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
PPPSDTRACE .EQU 1 ; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPPCONENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
;
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
HDSKTRACE .EQU 1 ; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
;
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
PIO4BASE .EQU $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
PIOZBASE .EQU $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
;
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
UFBASE .EQU $0C ; UF: REGISTERS BASE ADR

246
Source/HBIOS/cfg_mk4.asm

@ -3,119 +3,137 @@
; ROMWBW 2.X CONFIGURATION FOR MARK IV ; ROMWBW 2.X CONFIGURATION FOR MARK IV
;================================================================================================== ;==================================================================================================
; ;
; BUILD CONFIGURATION OPTIONS
;
CPUOSC .EQU 18432000 ; CPU OSC FREQ
MEMMGR .EQU MM_Z180 ; MM_NONE, MM_SBC, MM_Z2, MM_N8, MM_Z180
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!!
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE)
INTMODE .EQU 2 ; 0=NONE, 1=INT MODE 1, 2=INT MODE 2
DIAGENABLE .EQU FALSE ; TRUE FOR DIAGNOSTIC CODE PORT OUTPUT
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
; UNDER THIS DIRECTORY.
;
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
; FOR THE PLATFORM.
;
#DEFINE PLATFORM_NAME "MARK IV"
;
PLATFORM .EQU PLT_MK4 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SC126]
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
;
BOOTTYPE .EQU BT_MENU ; BT_[MENU|AUTO], IF AUTO, BOOT DEFAULT AFTER TIMEOUT
BOOT_TIMEOUT .EQU 20 ; AUTO BOOT TIMEOUT IN SECONDS, 0 FOR IMMEDIATE BOOT
BOOT_DEFAULT .EQU 'Z' ; AUTO BOOT SELECTION TO INVOKE AT TIMEOUT
;
CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
RAMBIAS .EQU 512 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
;
Z180_BASE .EQU $40 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
;
MK4_IDE .EQU $80 ; MK4: IDE REGISTERS BASE ADR
MK4_XAR .EQU $88 ; MK4: EXTERNAL ADDRESS REGISTER (XAR) ADR
MK4_SD .EQU $89 ; MK4: SD CARD CONTROL REGISTER ADR
MK4_RTC .EQU $8A ; MK4: RTC LATCH REGISTER ADR
;
RTC .EQU MK4_RTC ; RTC LATCH REGISTER ADR
;
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
;
DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS
; ;
CRTACT .EQU FALSE ; CRT ACTIVATION AT STARTUP
VDAEMU .EQU EMUTYP_ANSI ; DEFAULT VDA EMULATION (EMUTYP_TTY, EMUTYP_ANSI, ...)
;
DSKYENABLE .EQU FALSE ; TRUE FOR DSKY SUPPORT (DO NOT COMBINE WITH PPIDE)
;
HTIMENABLE .EQU FALSE ; TRUE FOR SIMH TIMER SUPPORT
SIMRTCENABLE .EQU FALSE ; SIMH CLOCK DRIVER
DSRTCENABLE .EQU TRUE ; DS-1302 CLOCK DRIVER
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTCMODE_STD, DSRTCMODE_MFPIC
DSRTCCHG .EQU FALSE ; DS-1302 CONFIGURE CHARGE ON (TRUE) OR OFF (FALSE)
;
ASCIENABLE .EQU TRUE ; TRUE FOR Z180 ASCI SUPPORT
UARTENABLE .EQU TRUE ; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
UARTOSC .EQU 1843200 ; UART OSC FREQUENCY
UARTSBC .EQU FALSE ; ENABLE SBC/ZETA ONBOARD UART DETECTION
UARTCAS .EQU TRUE ; ENABLE ECB CASSETTE UART DETECTION
UARTMFP .EQU FALSE ; ENABLE MF/PIC UART DETECTION
UART4 .EQU TRUE ; ENABLE 4UART UART DETECTION
SIOENABLE .EQU FALSE ; TRUE FOR ZILOG SIO/2 SUPPORT
ACIAENABLE .EQU FALSE ; TRUE FOR MOTOROLA 6850 ACIA SUPPORT
;
VDUENABLE .EQU FALSE ; TRUE FOR VDU BOARD SUPPORT
CVDUENABLE .EQU FALSE ; TRUE FOR CVDU BOARD SUPPORT
NECENABLE .EQU FALSE ; TRUE FOR uPD7220 BOARD SUPPORT
TMSENABLE .EQU FALSE ; TRUE FOR N8 (TMS9918) VIDEO/KBD SUPPORT
TMSMODE .EQU TMSMODE_SCG ; TMSMODE_[SCG/N8]
VGAENABLE .EQU FALSE ; TRUE FOR VGA VIDEO/KBD SUPPORT
;
SPKENABLE .EQU FALSE ; TRUE FOR RTC LATCH IOBIT SOUND
AYENABLE .EQU FALSE ; TRUE FOR AY PSG SOUND
AYMODE .EQU AYMODE_SCG ; AYMODE_[SCG/N8/RCZ80/RCZ180]
;
MDENABLE .EQU TRUE ; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENABLED)
MDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE)
;
FDENABLE .EQU FALSE ; TRUE FOR FLOPPY SUPPORT
FDMODE .EQU FDMODE_N8 ; FDMODE_DIO, FDMODE_ZETA, FDMODE_DIDE, FDMODE_N8, FDMODE_DIO3
FDTRACE .EQU 1 ; 0=SILENT, 1=FATAL ERRORS, 2=ALL ERRORS, 3=EVERYTHING (ONLY RELEVANT IF FDENABLE = TRUE)
FDMEDIA .EQU FDM144 ; FDM720, FDM144, FDM360, FDM120 (ONLY RELEVANT IF FDENABLE = TRUE)
FDMEDIAALT .EQU FDM720 ; ALTERNATE MEDIA TO TRY, SAME CHOICES AS ABOVE (ONLY RELEVANT IF FDMAUTO = TRUE)
FDMAUTO .EQU TRUE ; SELECT BETWEEN MEDIA OPTS ABOVE AUTOMATICALLY
;
RFENABLE .EQU FALSE ; TRUE FOR RAM FLOPPY SUPPORT
RFCNT .EQU 1 ; NUMBER OF RAM FLOPPY UNITS
;
IDEENABLE .EQU TRUE ; TRUE FOR IDE SUPPORT
IDEMODE .EQU IDEMODE_MK4 ; IDEMODE_DIO, IDEMODE_DIDE, IDEMODE_MK4
IDECNT .EQU 2 ; NUMBER OF IDE UNITS
IDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
IDE8BIT .EQU TRUE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
;
PPIDEENABLE .EQU FALSE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_DIO3 ; PPIDEMODE_SBC, PPPIDEMODE_DIO3, PPIDEMODE_MFP, PPIDEMODE_N8, PPIDEMODE_RC
PPIDECNT .EQU 1 ; NUMBER OF PPIDE UNITS
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
PPIDESLOW .EQU FALSE ; ADD DELAYS TO HELP PROBLEMATIC HARDWARE (TRY THIS IF PPIDE IS UNRELIABLE)
;
SDENABLE .EQU TRUE ; TRUE FOR SD SUPPORT
SDMODE .EQU SDMODE_MK4 ; SDMODE_JUHA, SDMODE_CSIO, SDMODE_UART, SDMODE_PPI, SDMODE_DSD, SDMODE_MK4
SDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
SDCSIOFAST .EQU TRUE ; TABLE-DRIVEN BIT INVERTER
;
PRPENABLE .EQU FALSE ; TRUE FOR PROPIO SUPPORT
PRPSDENABLE .EQU TRUE ; TRUE FOR PROPIO SD SUPPORT
PRPSDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PRPSDENABLE = TRUE)
PRPCONENABLE .EQU TRUE ; TRUE FOR PROPIO CONSOLE SUPPORT (PS/2 KBD & VGA VIDEO)
;
PPPENABLE .EQU FALSE ; TRUE FOR PARPORTPROP SUPPORT
PPPSDENABLE .EQU TRUE ; TRUE FOR PARPORTPROP SD SUPPORT
PPPSDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPPENABLE = TRUE)
PPPCONENABLE .EQU TRUE ; TRUE FOR PROPIO CONSOLE SUPPORT (PS/2 KBD & VGA VIDEO)
;
HDSKENABLE .EQU FALSE ; TRUE FOR SIMH HDSK SUPPORT
HDSKTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
;
PPKTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPKENABLE = TRUE)
KBDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF KBDENABLE = TRUE)
PPKKBLOUT .EQU KBD_US ; KEYBOARD LANGUAGE (US/DE)
KBDKBLOUT .EQU KBD_US ; KEYBOARD LANGUAGE (US/DE)
;
TERMENABLE .EQU FALSE ; TERM PSEUDO DEVICE, WILL BE ENABLED IF A VDA IS ENABLED
ANSITRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF ANSIENABLE = TRUE)
;
BOOTTYPE .EQU BT_MENU ; BT_MENU (WAIT FOR KEYPRESS), BT_AUTO (BOOT_DEFAULT AFTER BOOT_TIMEOUT SECS)
BOOT_TIMEOUT .EQU 20 ; APPROX TIMEOUT IN SECONDS FOR AUTOBOOT, 0 FOR IMMEDIATE
BOOT_DEFAULT .EQU 'Z' ; SELECTION TO INVOKE AT TIMEOUT
;
; 18.432MHz OSC @ FULL SPEED
;
Z180_CLKDIV .EQU 1 ; 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .EQU 0 ; MEMORY WAIT STATES (0-3)
Z180_IOWAIT .EQU 1 ; ADD (0-3) I/O WAIT STATES ABOVE 1 W/S BUILT-IN
;
; 18.432MHz OSC @ DOUBLE SPEED
;
;Z180_CLKDIV .EQU 2 ; 0=OSC/2, 1=OSC, 2=OSC*2
;Z180_MEMWAIT .EQU 1 ; MEMORY WAIT STATES (0-3)
;Z180_IOWAIT .EQU 1 ; ADD (0-3) I/O WAIT STATES ABOVE 1 W/S BUILT-IN
;
PIO_4P .EQU FALSE ; TRUE FOR ECB-4PIO PIO SUPPORT
PIO_ZP .EQU FALSE ; TRUE FOR ECB-ZILOG PERIPHERALS BOARD
PPI_SBC .EQU FALSE ; TRUE FOR SBC V2 8255 (IF NOT BEING USED FOR PPIDE)
;
UFENABLE .EQU FALSE ; TRUE FOR ECB USB-FIFO SUPPORT
DSKYENABLE .EQU FALSE ; ENABLES DSKY (DO NOT COMBINE WITH PPIDE)
;
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
;
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
;
DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
;
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
UARTCAS .EQU TRUE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU TRUE ; UART: AUTO-DETECT 4UART UART
;
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
;
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
;
SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
;
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
VDUSIZ .EQU V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
NECENABLE .EQU FALSE ; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
TMSMODE .EQU TMSMODE_SCG ; TMS: DRIVER MODE: TMSMODE_[SCG/N8]
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
;
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
;
AYENABLE .EQU FALSE ; AY: ENABLE AY PSG SOUND DRIVER
AYMODE .EQU AYMODE_SCG ; AY: DRIVER MODE: AYMODE_[SCG/N8/RCZ80/RCZ180]
;
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
;
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .EQU FDMODE_N8 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3]
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
FDMEDIA .EQU FDM144 ; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
FDMEDIAALT .EQU FDM720 ; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
;
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
RFCNT .EQU 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-2)
;
IDEENABLE .EQU TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
IDEMODE .EQU IDEMODE_MK4 ; IDE: DRIVER MODE: IDEMODE_[DIO|DIDE]
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
IDE8BIT .EQU TRUE ; IDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDEMODE .EQU PPIDEMODE_DIO3 ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC]
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_MK4 ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC126]
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU TRUE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
;
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
;
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
PPPSDENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
PPPSDTRACE .EQU 1 ; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPPCONENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
;
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
;
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
PIO4BASE .EQU $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
PIOZBASE .EQU $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
;
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
UFBASE .EQU $0C ; UF: REGISTERS BASE ADR

235
Source/HBIOS/cfg_n8.asm

@ -3,108 +3,137 @@
; ROMWBW 2.X CONFIGURATION FOR N8 ; ROMWBW 2.X CONFIGURATION FOR N8
;================================================================================================== ;==================================================================================================
; ;
; BUILD CONFIGURATION OPTIONS
;
CPUOSC .EQU 18432000 ; CPU OSC FREQ
MEMMGR .EQU MM_N8 ; MM_NONE, MM_SBC, MM_Z2, MM_N8, MM_Z180
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!!
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE)
INTMODE .EQU 2 ; 0=NONE, 1=INT MODE 1, 2=INT MODE 2
DIAGENABLE .EQU FALSE ; TRUE FOR DIAGNOSTIC CODE PORT OUTPUT
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
; UNDER THIS DIRECTORY.
;
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
; FOR THE PLATFORM.
;
#DEFINE PLATFORM_NAME "N8"
;
PLATFORM .EQU PLT_N8 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SC126]
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
;
BOOTTYPE .EQU BT_MENU ; BT_[MENU|AUTO], IF AUTO, BOOT DEFAULT AFTER TIMEOUT
BOOT_TIMEOUT .EQU 20 ; AUTO BOOT TIMEOUT IN SECONDS, 0 FOR IMMEDIATE BOOT
BOOT_DEFAULT .EQU 'Z' ; AUTO BOOT SELECTION TO INVOKE AT TIMEOUT
;
CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
MEMMGR .EQU MM_N8 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
RAMBIAS .EQU 0 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
;
Z180_BASE .EQU $40 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .EQU 1 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .EQU 3 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
;
N8_PPI0 .EQU $80 ; N8: FIRST PARALLEL PORT REGISTERS BASE ADR
N8_PPI1 .EQU $84 ; N8: SECOND PARALLEL PORT REGISTERS BASE ADR
N8_RTC .EQU $88 ; N8: RTC LATCH REGISTER ADR
N8_ACR .EQU $94 ; N8: AUXILLARY CONTROL REGISTER (ACR) ADR
N8_RMAP .EQU $96 ; N8: ROM PAGE REGISTER ADR
N8_DEFACR .EQU $1B ; N8: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE)
;
RTC .EQU N8_RTC ; RTC LATCH REGISTER ADR
PPIBASE .EQU N8_PPI0 ; PRIMARY PARALLEL PORT REGISTERS BASE ADR
;
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
;
DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS
; ;
CRTACT .EQU FALSE ; CRT ACTIVATION AT STARTUP
VDAEMU .EQU EMUTYP_ANSI ; DEFAULT VDA EMULATION (EMUTYP_TTY, EMUTYP_ANSI, ...)
;
DSKYENABLE .EQU FALSE ; TRUE FOR DSKY SUPPORT (DO NOT COMBINE WITH PPIDE)
;
HTIMENABLE .EQU FALSE ; TRUE FOR SIMH TIMER SUPPORT
SIMRTCENABLE .EQU FALSE ; SIMH CLOCK DRIVER
DSRTCENABLE .EQU TRUE ; DS-1302 CLOCK DRIVER
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTCMODE_STD, DSRTCMODE_MFPIC
DSRTCCHG .EQU FALSE ; DS-1302 CONFIGURE CHARGE ON (TRUE) OR OFF (FALSE)
;
ASCIENABLE .EQU TRUE ; TRUE FOR Z180 ASCI SUPPORT
UARTENABLE .EQU TRUE ; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
UARTOSC .EQU 1843200 ; UART OSC FREQUENCY
UARTSBC .EQU FALSE ; ENABLE SBC/ZETA ONBOARD UART DETECTION
UARTCAS .EQU TRUE ; ENABLE ECB CASSETTE UART DETECTION
UARTMFP .EQU FALSE ; ENABLE MF/PIC UART DETECTION
UART4 .EQU TRUE ; ENABLE 4UART UART DETECTION
SIOENABLE .EQU FALSE ; TRUE FOR ZILOG SIO/2 SUPPORT
ACIAENABLE .EQU FALSE ; TRUE FOR MOTOROLA 6850 ACIA SUPPORT
;
VDUENABLE .EQU FALSE ; TRUE FOR VDU BOARD SUPPORT
CVDUENABLE .EQU FALSE ; TRUE FOR CVDU BOARD SUPPORT
NECENABLE .EQU FALSE ; TRUE FOR uPD7220 BOARD SUPPORT
TMSENABLE .EQU TRUE ; TRUE FOR N8 (TMS9918) VIDEO/KBD SUPPORT
TMSMODE .EQU TMSMODE_N8 ; TMSMODE_[SCG/N8]
VGAENABLE .EQU FALSE ; TRUE FOR VGA VIDEO/KBD SUPPORT
;
SPKENABLE .EQU FALSE ; TRUE FOR RTC LATCH IOBIT SOUND
AYENABLE .EQU TRUE ; TRUE FOR AY PSG SOUND
AYMODE .EQU AYMODE_N8 ; AYMODE_[SCG/N8/RCZ80/RCZ180]
;
MDENABLE .EQU TRUE ; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENABLED)
MDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE)
;
FDENABLE .EQU TRUE ; TRUE FOR FLOPPY SUPPORT
FDMODE .EQU FDMODE_N8 ; FDMODE_DIO, FDMODE_ZETA, FDMODE_DIDE, FDMODE_N8, FDMODE_DIO3
FDTRACE .EQU 1 ; 0=SILENT, 1=FATAL ERRORS, 2=ALL ERRORS, 3=EVERYTHING (ONLY RELEVANT IF FDENABLE = TRUE)
FDMEDIA .EQU FDM144 ; FDM720, FDM144, FDM360, FDM120 (ONLY RELEVANT IF FDENABLE = TRUE)
FDMEDIAALT .EQU FDM720 ; ALTERNATE MEDIA TO TRY, SAME CHOICES AS ABOVE (ONLY RELEVANT IF FDMAUTO = TRUE)
FDMAUTO .EQU TRUE ; SELECT BETWEEN MEDIA OPTS ABOVE AUTOMATICALLY
;
RFENABLE .EQU FALSE ; TRUE FOR RAM FLOPPY SUPPORT
RFCNT .EQU 1 ; NUMBER OF RAM FLOPPY UNITS
;
IDEENABLE .EQU FALSE ; TRUE FOR IDE SUPPORT
IDEMODE .EQU IDEMODE_DIO ; IDEMODE_DIO, IDEMODE_DIDE
IDECNT .EQU 1 ; NUMBER OF IDE UNITS
IDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
;
PPIDEENABLE .EQU FALSE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_N8 ; PPIDEMODE_SBC, PPPIDEMODE_DIO3, PPIDEMODE_MFP, PPIDEMODE_N8, PPIDEMODE_RC
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
;
SDENABLE .EQU TRUE ; TRUE FOR SD SUPPORT
SDMODE .EQU SDMODE_CSIO ; SDMODE_JUHA, SDMODE_CSIO, SDMODE_UART, SDMODE_PPI, SDMODE_DSD
SDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
SDCSIOFAST .EQU FALSE ; TABLE-DRIVEN BIT INVERTER
;
PRPENABLE .EQU FALSE ; TRUE FOR PROPIO SUPPORT
PRPSDENABLE .EQU TRUE ; TRUE FOR PROPIO SD SUPPORT
PRPSDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PRPSDENABLE = TRUE)
PRPCONENABLE .EQU TRUE ; TRUE FOR PROPIO CONSOLE SUPPORT (PS/2 KBD & VGA VIDEO)
;
PPPENABLE .EQU FALSE ; TRUE FOR PARPORTPROP SUPPORT
PPPSDENABLE .EQU TRUE ; TRUE FOR PARPORTPROP SD SUPPORT
PPPSDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPPENABLE = TRUE)
PPPCONENABLE .EQU TRUE ; TRUE FOR PROPIO CONSOLE SUPPORT (PS/2 KBD & VGA VIDEO)
;
HDSKENABLE .EQU FALSE ; TRUE FOR SIMH HDSK SUPPORT
;
PPKTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPKENABLE = TRUE)
KBDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF KBDENABLE = TRUE)
PPKKBLOUT .EQU KBD_US ; KEYBOARD LANGUAGE (US/DE)
KBDKBLOUT .EQU KBD_US ; KEYBOARD LANGUAGE (US/DE)
;
TERMENABLE .EQU FALSE ; TERM PSEUDO DEVICE, WILL BE ENABLED IF A VDA IS ENABLED
ANSITRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF ANSIENABLE = TRUE)
;
BOOTTYPE .EQU BT_MENU ; BT_MENU (WAIT FOR KEYPRESS), BT_AUTO (BOOT_DEFAULT AFTER BOOT_TIMEOUT SECS)
BOOT_TIMEOUT .EQU 20 ; APPROX TIMEOUT IN SECONDS FOR AUTOBOOT, 0 FOR IMMEDIATE
BOOT_DEFAULT .EQU 'Z' ; SELECTION TO INVOKE AT TIMEOUT
;
Z180_CLKDIV .EQU 1 ; 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .EQU 1 ; MEMORY WAIT STATES (0-3)
Z180_IOWAIT .EQU 3 ; ADD (0-3) I/O WAIT STATES ABOVE 1 W/S BUILT-IN
;
PIO_4P .EQU FALSE ; TRUE FOR ECB-4PIO PIO SUPPORT
PIO_ZP .EQU FALSE ; TRUE FOR ECB-ZILOG PERIPHERALS BOARD
PPI_SBC .EQU FALSE ; TRUE FOR SBC V2 8255 (IF NOT BEING USED FOR PPIDE)
;
UFENABLE .EQU FALSE ; TRUE FOR ECB USB-FIFO SUPPORT
DSKYENABLE .EQU FALSE ; ENABLES DSKY (DO NOT COMBINE WITH PPIDE)
;
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
;
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
;
DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
;
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
UARTCAS .EQU TRUE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU TRUE ; UART: AUTO-DETECT 4UART UART
;
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
;
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
;
SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
;
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
VDUSIZ .EQU V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
NECENABLE .EQU FALSE ; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
TMSENABLE .EQU TRUE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
TMSMODE .EQU TMSMODE_N8 ; TMS: DRIVER MODE: TMSMODE_[SCG/N8]
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
;
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
;
AYENABLE .EQU TRUE ; AY: ENABLE AY PSG SOUND DRIVER
AYMODE .EQU AYMODE_N8 ; AY: DRIVER MODE: AYMODE_[SCG/N8/RCZ80/RCZ180]
;
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
;
FDENABLE .EQU TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .EQU FDMODE_N8 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3]
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
FDMEDIA .EQU FDM144 ; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
FDMEDIAALT .EQU FDM720 ; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
;
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
RFCNT .EQU 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-2)
;
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
IDEMODE .EQU IDEMODE_DIO ; IDE: DRIVER MODE: IDEMODE_[DIO|DIDE]
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
IDE8BIT .EQU FALSE ; IDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDEMODE .EQU PPIDEMODE_N8 ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC]
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC126]
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
;
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
;
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
;
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
;
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
PIO4BASE .EQU $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
PIOZBASE .EQU $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
;
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
FIFO_BASE .EQU $0C ; UF: REGISTERS BASE ADR

237
Source/HBIOS/cfg_rcz180.asm

@ -3,113 +3,134 @@
; ROMWBW 2.X CONFIGURATION DEFAULTS FOR RC2014 ; ROMWBW 2.X CONFIGURATION DEFAULTS FOR RC2014
;================================================================================================== ;==================================================================================================
; ;
; BUILD CONFIGURATION OPTIONS
;
CPUOSC .EQU 18432000 ; CPU OSC FREQ
MEMMGR .EQU MM_Z180 ; MM_NONE, MM_SBC, MM_Z2, MM_N8, MM_Z180
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!!
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE)
INTMODE .EQU 2 ; 0=NONE, 1=INT MODE 1, 2=INT MODE 2
DIAGENABLE .EQU TRUE ; TRUE FOR DIAGNOSTIC CODE PORT OUTPUT
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
; UNDER THIS DIRECTORY.
;
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
; FOR THE PLATFORM.
;
#DEFINE PLATFORM_NAME "RC2014"
;
PLATFORM .EQU PLT_RCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SC126]
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
;
BOOTTYPE .EQU BT_MENU ; BT_[MENU|AUTO], IF AUTO, BOOT DEFAULT AFTER TIMEOUT
BOOT_TIMEOUT .EQU 20 ; AUTO BOOT TIMEOUT IN SECONDS, 0 FOR IMMEDIATE BOOT
BOOT_DEFAULT .EQU 'Z' ; AUTO BOOT SELECTION TO INVOKE AT TIMEOUT
;
CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
RAMBIAS .EQU 512 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
;
Z180_BASE .EQU $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
;
RTC .EQU $0C ; RTC LATCH REGISTER ADR
;
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
;
DIAGENABLE .EQU TRUE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS
; ;
CRTACT .EQU FALSE ; CRT ACTIVATION AT STARTUP
VDAEMU .EQU EMUTYP_ANSI ; DEFAULT VDA EMULATION (EMUTYP_TTY, EMUTYP_ANSI, ...)
;
DSKYENABLE .EQU FALSE ; TRUE FOR DSKY SUPPORT (DO NOT COMBINE WITH PPIDE)
;
HTIMENABLE .EQU FALSE ; TRUE FOR SIMH TIMER SUPPORT
SIMRTCENABLE .EQU FALSE ; SIMH CLOCK DRIVER
DSRTCENABLE .EQU FALSE ; DS-1302 CLOCK DRIVER
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTCMODE_STD, DSRTCMODE_MFPIC
DSRTCCHG .EQU FALSE ; DS-1302 CONFIGURE CHARGE ON (TRUE) OR OFF (FALSE)
;
ASCIENABLE .EQU TRUE ; TRUE FOR Z180 ASCI SUPPORT
UARTENABLE .EQU FALSE ; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
UARTOSC .EQU 1843200 ; UART OSC FREQUENCY
ACIAENABLE .EQU FALSE ; TRUE FOR MOTOROLA 6850 ACIA SUPPORT
;
SIOENABLE .EQU TRUE ; TRUE FOR ZILOG SIO SUPPORT
SIODEBUG .EQU FALSE ; PS
SIOCNT .EQU 2 ; 1 OR 2 SIO CHIPS (EACH CHIP HAS 2 CHANNELS)
SIO0MODE .EQU SIOMODE_RC ; TYPE OF FIRST SIO TO DETECT: SIOMODE_RC/SMB/ZP/EZZ80
SIO0BASE .EQU $80 ; IO PORT ADDRESS BASE FOR FIRST SIO CHIP
SIO0ACLK .EQU 7372800 ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
SIO0ADIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
SIO0ACFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG
SIO0BCLK .EQU 7372800 ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
SIO0BDIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
SIO0BCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG
SIO1MODE .EQU SIOMODE_RC ; TYPE OF SECOND SIO TO DETECT: SIOMODE_RC, SIOMODE_SMB
SIO1BASE .EQU $84 ; IO PORT ADDRESS BASE FOR SECOND SIO CHIP
SIO1ACLK .EQU 7372800 ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
SIO1ADIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
SIO1ACFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG
SIO1BCLK .EQU 7372800 ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
SIO1BDIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
SIO1BCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG
;
VDUENABLE .EQU FALSE ; TRUE FOR VDU BOARD SUPPORT
CVDUENABLE .EQU FALSE ; TRUE FOR CVDU BOARD SUPPORT
NECENABLE .EQU FALSE ; TRUE FOR uPD7220 BOARD SUPPORT
TMSENABLE .EQU FALSE ; TRUE FOR N8 (TMS9918) VIDEO/KBD SUPPORT
VGAENABLE .EQU FALSE ; TRUE FOR VGA VIDEO/KBD SUPPORT
;
SPKENABLE .EQU FALSE ; TRUE FOR RTC LATCH IOBIT SOUND
AYENABLE .EQU FALSE ; TRUE FOR AY PSG SOUND
AYMODE .EQU AYMODE_RCZ180 ; AYMODE_[SCG/N8/RCZ80/RCZ180]
;
MDENABLE .EQU TRUE ; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENABLED)
MDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE)
;
FDENABLE .EQU FALSE ; TRUE FOR FLOPPY SUPPORT
FDMODE .EQU FDMODE_RCWDC ; FDMODE_DIO, FDMODE_ZETA, FDMODE_DIDE, FDMODE_N8, FDMODE_DIO3
FDTRACE .EQU 1 ; 0=SILENT, 1=FATAL ERRORS, 2=ALL ERRORS, 3=EVERYTHING (ONLY RELEVANT IF FDENABLE = TRUE)
FDMEDIA .EQU FDM144 ; FDM720, FDM144, FDM360, FDM120 (ONLY RELEVANT IF FDENABLE = TRUE)
FDMEDIAALT .EQU FDM720 ; ALTERNATE MEDIA TO TRY, SAME CHOICES AS ABOVE (ONLY RELEVANT IF FDMAUTO = TRUE)
FDMAUTO .EQU TRUE ; SELECT BETWEEN MEDIA OPTS ABOVE AUTOMATICALLY
;
RFENABLE .EQU FALSE ; TRUE FOR RAM FLOPPY SUPPORT
;
IDEENABLE .EQU FALSE ; TRUE FOR IDE SUPPORT
IDEMODE .EQU IDEMODE_RC ; IDEMODE_DIO, IDEMODE_DIDE, IDEMODE_RC
IDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
IDE8BIT .EQU TRUE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
;
PPIDEENABLE .EQU FALSE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_RC ; PPIDEMODE_SBC, PPPIDEMODE_DIO3, PPIDEMODE_MFP, PPIDEMODE_N8, PPIDEMODE_RC
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
;
SDENABLE .EQU FALSE ; TRUE FOR SD SUPPORT
SDMODE .EQU SDMODE_PPI ; SDMODE_JUHA, SDMODE_CSIO, SDMODE_UART, SDMODE_PPI, SDMODE_DSD
SDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
SDCSIOFAST .EQU FALSE ; TABLE-DRIVEN BIT INVERTER
;
PRPENABLE .EQU FALSE ; TRUE FOR PROPIO SUPPORT
;
PPPENABLE .EQU FALSE ; TRUE FOR PARPORTPROP SUPPORT
PPPSDENABLE .EQU TRUE ; TRUE FOR PARPORTPROP SD SUPPORT
PPPSDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPPENABLE = TRUE)
PPPCONENABLE .EQU TRUE ; TRUE FOR PROPIO CONSOLE SUPPORT (PS/2 KBD & VGA VIDEO)
;
HDSKENABLE .EQU FALSE ; TRUE FOR SIMH HDSK SUPPORT
;
TERMENABLE .EQU FALSE ; TERM PSEUDO DEVICE, WILL BE ENABLED IF A VDA IS ENABLED
;
BOOTTYPE .EQU BT_MENU ; BT_MENU (WAIT FOR KEYPRESS), BT_AUTO (BOOT_DEFAULT AFTER BOOT_TIMEOUT SECS)
BOOT_TIMEOUT .EQU 20 ; APPROX TIMEOUT IN SECONDS FOR AUTOBOOT, 0 FOR IMMEDIATE
BOOT_DEFAULT .EQU 'Z' ; SELECTION TO INVOKE AT TIMEOUT
;
; 18.432MHz OSC @ FULL SPEED
;
Z180_CLKDIV .EQU 1 ; 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .EQU 0 ; MEMORY WAIT STATES (0-3)
Z180_IOWAIT .EQU 1 ; ADD (0-3) I/O WAIT STATES ABOVE 1 W/S BUILT-IN
;
PIO_4P .EQU FALSE ; TRUE FOR ECB-4PIO PIO SUPPORT
PIO_ZP .EQU FALSE ; TRUE FOR ECB-ZILOG PERIPHERALS BOARD
PPI_SBC .EQU FALSE ; TRUE FOR SBC V2 8255 (IF NOT BEING USED FOR PPIDE)
;
UFENABLE .EQU FALSE ; TRUE FOR ECB USB-FIFO SUPPORT
DSKYENABLE .EQU FALSE ; ENABLES DSKY (DO NOT COMBINE WITH PPIDE)
;
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
;
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
;
DSRTCENABLE .EQU FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
;
UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
;
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
;
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
;
SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0ADIV .EQU 1 ; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO0ACFG .EQU DEFSERCFG ; AIO 0A: SERIAL LINE CONFIG
SIO0BCLK .EQU 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0BDIV .EQU 1 ; SIO 0B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR
SIO1ACLK .EQU 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO1ADIV .EQU 1 ; SIO 1A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO1ACFG .EQU DEFSERCFG ; AIO 1A: SERIAL LINE CONFIG
SIO1BCLK .EQU 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO1BDIV .EQU 1 ; SIO 1B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO1BCFG .EQU DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG
;
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
NECENABLE .EQU FALSE ; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
;
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
;
AYENABLE .EQU FALSE ; AY: ENABLE AY PSG SOUND DRIVER
AYMODE .EQU AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG/N8/RCZ80/RCZ180]
;
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
;
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3]
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
FDMEDIA .EQU FDM144 ; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
FDMEDIAALT .EQU FDM720 ; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
;
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
;
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
IDEMODE .EQU IDEMODE_RC ; IDE: DRIVER MODE: IDEMODE_[DIO|DIDE]
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
IDE8BIT .EQU TRUE ; IDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDEMODE .EQU PPIDEMODE_RC ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC]
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC126]
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
;
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
;
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
;
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
;
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
;
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)

248
Source/HBIOS/cfg_rcz80.asm

@ -1,122 +1,140 @@
; ;
;================================================================================================== ;==================================================================================================
; ROMWBW 2.X CONFIGURATION DEFAULTS FOR RC2014
; ROMWBW 2.X CONFIGURATION DEFAULTS FOR RC2014 Z80
;================================================================================================== ;==================================================================================================
; ;
; BUILD CONFIGURATION OPTIONS
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
; UNDER THIS DIRECTORY.
; ;
CPUOSC .EQU 7372800 ; CPU OSC FREQ
MEMMGR .EQU MM_Z2 ; MM_NONE, MM_SBC, MM_Z2, MM_N8, MM_Z180
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!!
DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE)
INTMODE .EQU 1 ; 0=NONE, 1=INT MODE 1, 2=INT MODE 2
DIAGENABLE .EQU TRUE ; TRUE FOR DIAGNOSTIC CODE PORT OUTPUT
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
; FOR THE PLATFORM.
;
#DEFINE PLATFORM_NAME "RC2014"
;
PLATFORM .EQU PLT_RCZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SC126]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
;
BOOTTYPE .EQU BT_MENU ; BT_[MENU|AUTO], IF AUTO, BOOT DEFAULT AFTER TIMEOUT
BOOT_TIMEOUT .EQU 20 ; AUTO BOOT TIMEOUT IN SECONDS, 0 FOR IMMEDIATE BOOT
BOOT_DEFAULT .EQU 'Z' ; AUTO BOOT SELECTION TO INVOKE AT TIMEOUT
;
CPUOSC .EQU 7372800 ; CPU OSC FREQ IN MHZ
INTMODE .EQU 1 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
;
RTC .EQU $C0 ; RTC LATCH REGISTER ADR
;
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
;
DIAGENABLE .EQU TRUE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS
; ;
CRTACT .EQU FALSE ; CRT ACTIVATION AT STARTUP
VDAEMU .EQU EMUTYP_ANSI ; DEFAULT VDA EMULATION (EMUTYP_TTY, EMUTYP_ANSI, ...)
;
DSKYENABLE .EQU FALSE ; TRUE FOR DSKY SUPPORT (DO NOT COMBINE WITH PPIDE)
;
HTIMENABLE .EQU FALSE ; TRUE FOR SIMH TIMER SUPPORT
SIMRTCENABLE .EQU FALSE ; SIMH CLOCK DRIVER
DSRTCENABLE .EQU FALSE ; DS-1302 CLOCK DRIVER
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTCMODE_STD, DSRTCMODE_MFPIC
DSRTCCHG .EQU FALSE ; DS-1302 CONFIGURE CHARGE ON (TRUE) OR OFF (FALSE)
;
ASCIENABLE .EQU FALSE ; TRUE FOR Z180 ASCI SUPPORT
UARTENABLE .EQU FALSE ; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
UARTOSC .EQU 1843200 ; UART OSC FREQUENCY
;
ACIAENABLE .EQU TRUE ; TRUE FOR MOTOROLA 6850 ACIA SUPPORT
ACIADEBUG .EQU FALSE ; PS
ACIACNT .EQU 1 ; 1 OR 2 ACIA CHIPS
ACIA0MODE .EQU ACIAMODE_RC ; TYPE OF FIRST ACIA TO DETECT: SIOMODE_RC
ACIA0BASE .EQU $80 ; IO PORT ADDRESS BASE FOR FIRST ACIA CHIP
ACIA0CLK .EQU CPUOSC ; 7372800 - ACIA FIXED OSC FREQUENCY
ACIA0DIV .EQU 1 ; 1=RC2014
ACIA0CFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG
ACIA1MODE .EQU ACIAMODE_RC ; TYPE OF SECOND ACIA TO DETECT: SIOMODE_RC
ACIA1BASE .EQU $40 ; IO PORT ADDRESS BASE FOR SECOND ACIA CHIP
ACIA1CLK .EQU CPUOSC ; 7372800 - ACIA FIXED OSC FREQUENCY
ACIA1DIV .EQU 1 ; 1=RC2014
ACIA1CFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG
;
SIOENABLE .EQU TRUE ; TRUE FOR ZILOG SIO SUPPORT
SIODEBUG .EQU FALSE ; PS
SIOCNT .EQU 2 ; 1 OR 2 SIO CHIPS (EACH CHIP HAS 2 CHANNELS)
SIO0MODE .EQU SIOMODE_RC ; TYPE OF FIRST SIO TO DETECT: SIOMODE_RC/SMB/ZP/EZZ80
SIO0BASE .EQU $80 ; IO PORT ADDRESS BASE FOR FIRST SIO CHIP
SIO0ACLK .EQU CPUOSC ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
SIO0ADIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
SIO0ACFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG
SIO0BCLK .EQU CPUOSC ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
SIO0BDIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
SIO0BCFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG
SIO1MODE .EQU SIOMODE_RC ; TYPE OF SECOND SIO TO DETECT: SIOMODE_RC, SIOMODE_SMB
SIO1BASE .EQU $84 ; IO PORT ADDRESS BASE FOR SECOND SIO CHIP
SIO1ACLK .EQU CPUOSC ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
SIO1ADIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
SIO1ACFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG
SIO1BCLK .EQU CPUOSC ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
SIO1BDIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
SIO1BCFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG
;
VDUENABLE .EQU FALSE ; TRUE FOR VDU BOARD SUPPORT
CVDUENABLE .EQU FALSE ; TRUE FOR CVDU BOARD SUPPORT
NECENABLE .EQU FALSE ; TRUE FOR uPD7220 BOARD SUPPORT
TMSENABLE .EQU FALSE ; TRUE FOR N8 (TMS9918) VIDEO/KBD SUPPORT
VGAENABLE .EQU FALSE ; TRUE FOR VGA VIDEO/KBD SUPPORT
;
SPKENABLE .EQU FALSE ; TRUE FOR RTC LATCH IOBIT SOUND
AYENABLE .EQU FALSE ; TRUE FOR AY PSG SOUND
AYMODE .EQU AYMODE_RCZ80 ; AYMODE_[SCG/N8/RCZ80/RCZ180]
;
MDENABLE .EQU TRUE ; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENABLED)
MDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE)
;
FDENABLE .EQU FALSE ; TRUE FOR FLOPPY SUPPORT
FDMODE .EQU FDMODE_RCWDC ; FDMODE_DIO, FDMODE_ZETA, FDMODE_DIDE, FDMODE_N8, FDMODE_DIO3
FDTRACE .EQU 1 ; 0=SILENT, 1=FATAL ERRORS, 2=ALL ERRORS, 3=EVERYTHING (ONLY RELEVANT IF FDENABLE = TRUE)
FDMEDIA .EQU FDM144 ; FDM720, FDM144, FDM360, FDM120 (ONLY RELEVANT IF FDENABLE = TRUE)
FDMEDIAALT .EQU FDM720 ; ALTERNATE MEDIA TO TRY, SAME CHOICES AS ABOVE (ONLY RELEVANT IF FDMAUTO = TRUE)
FDMAUTO .EQU TRUE ; SELECT BETWEEN MEDIA OPTS ABOVE AUTOMATICALLY
;
RFENABLE .EQU FALSE ; TRUE FOR RAM FLOPPY SUPPORT
;
IDEENABLE .EQU FALSE ; TRUE FOR IDE SUPPORT
IDEMODE .EQU IDEMODE_RC ; IDEMODE_DIO, IDEMODE_DIDE, IDEMODE_RC
IDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
IDE8BIT .EQU TRUE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
;
PPIDEENABLE .EQU FALSE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_RC ; PPIDEMODE_SBC, PPPIDEMODE_DIO3, PPIDEMODE_MFP, PPIDEMODE_N8, PPIDEMODE_RC
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
;
SDENABLE .EQU FALSE ; TRUE FOR SD SUPPORT
SDMODE .EQU SDMODE_PPI ; SDMODE_JUHA, SDMODE_CSIO, SDMODE_UART, SDMODE_PPI, SDMODE_DSD
SDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
SDCSIOFAST .EQU FALSE ; TABLE-DRIVEN BIT INVERTER
;
PRPENABLE .EQU FALSE ; TRUE FOR PROPIO SUPPORT
;
PPPENABLE .EQU FALSE ; TRUE FOR PARPORTPROP SUPPORT
PPPSDENABLE .EQU TRUE ; TRUE FOR PARPORTPROP SD SUPPORT
PPPSDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPPENABLE = TRUE)
PPPCONENABLE .EQU TRUE ; TRUE FOR PROPIO CONSOLE SUPPORT (PS/2 KBD & VGA VIDEO)
;
HDSKENABLE .EQU FALSE ; TRUE FOR SIMH HDSK SUPPORT
;
TERMENABLE .EQU FALSE ; TERM PSEUDO DEVICE, WILL BE ENABLED IF A VDA IS ENABLED
;
BOOTTYPE .EQU BT_MENU ; BT_MENU (WAIT FOR KEYPRESS), BT_AUTO (BOOT_DEFAULT AFTER BOOT_TIMEOUT SECS)
BOOT_TIMEOUT .EQU 20 ; APPROX TIMEOUT IN SECONDS FOR AUTOBOOT, 0 FOR IMMEDIATE
BOOT_DEFAULT .EQU 'Z' ; SELECTION TO INVOKE AT TIMEOUT
;
PIO_4P .EQU FALSE ; TRUE FOR ECB-4PIO PIO SUPPORT
PIO_ZP .EQU FALSE ; TRUE FOR ECB-ZILOG PERIPHERALS BOARD
PPI_SBC .EQU FALSE ; TRUE FOR SBC V2 8255 (IF NOT BEING USED FOR PPIDE)
;
UFENABLE .EQU FALSE ; TRUE FOR ECB USB-FIFO SUPPORT
DSKYENABLE .EQU FALSE ; ENABLES DSKY (DO NOT COMBINE WITH PPIDE)
;
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
;
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
;
DSRTCENABLE .EQU FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
;
UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
;
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
;
ACIAENABLE .EQU TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
ACIADEBUG .EQU FALSE ; ACIA: ENABLE DEBUG OUTPUT
ACIACNT .EQU 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
ACIA0BASE .EQU $80 ; ACIA 0: REGISTERS BASE ADR
ACIA0CLK .EQU CPUOSC ; ACIA 0: OSC FREQ IN HZ
ACIA0DIV .EQU 1 ; ACIA 0: SERIAL CLOCK DIVIDER
ACIA0CFG .EQU DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM)
ACIA1BASE .EQU $40 ; ACIA 1: REGISTERS BASE ADR
ACIA1CLK .EQU CPUOSC ; ACIA 1: OSC FREQ IN HZ
ACIA1DIV .EQU 1 ; ACIA 1: SERIAL CLOCK DIVIDER
ACIA1CFG .EQU DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM)
;
SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0ADIV .EQU 1 ; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO0ACFG .EQU DEFSERCFG ; AIO 0A: SERIAL LINE CONFIG
SIO0BCLK .EQU CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0BDIV .EQU 1 ; SIO 0B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR
SIO1ACLK .EQU CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO1ADIV .EQU 1 ; SIO 1A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO1ACFG .EQU DEFSERCFG ; AIO 1A: SERIAL LINE CONFIG
SIO1BCLK .EQU CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO1BDIV .EQU 1 ; SIO 1B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO1BCFG .EQU DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG
;
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
NECENABLE .EQU FALSE ; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
;
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
;
AYENABLE .EQU FALSE ; AY: ENABLE AY PSG SOUND DRIVER
AYMODE .EQU AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG/N8/RCZ80/RCZ180]
;
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
;
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3]
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
FDMEDIA .EQU FDM144 ; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
FDMEDIAALT .EQU FDM720 ; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
;
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
;
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
IDEMODE .EQU IDEMODE_RC ; IDE: DRIVER MODE: IDEMODE_[DIO|DIDE]
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
IDE8BIT .EQU TRUE ; IDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDEMODE .EQU PPIDEMODE_RC ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC]
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC126]
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
;
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
;
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
;
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
;
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
;
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)

243
Source/HBIOS/cfg_sbc.asm

@ -3,116 +3,137 @@
; ROMWBW 2.X CONFIGURATION DEFAULTS FOR SBC ; ROMWBW 2.X CONFIGURATION DEFAULTS FOR SBC
;================================================================================================== ;==================================================================================================
; ;
; BUILD CONFIGURATION OPTIONS
;
CPUOSC .EQU 8000000 ; CPU OSC FREQ
MEMMGR .EQU MM_SBC ; MM_NONE, MM_SBC, MM_Z2, MM_N8, MM_Z180
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!!
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE)
INTMODE .EQU 0 ; 0=NONE, 1=INT MODE 1, 2=INT MODE 2
DIAGENABLE .EQU FALSE ; TRUE FOR DIAGNOSTIC CODE PORT OUTPUT
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
; UNDER THIS DIRECTORY.
;
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
; FOR THE PLATFORM.
;
#DEFINE PLATFORM_NAME "SBC"
;
PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SC126]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
;
BOOTTYPE .EQU BT_MENU ; BT_[MENU|AUTO], IF AUTO, BOOT DEFAULT AFTER TIMEOUT
BOOT_TIMEOUT .EQU 20 ; AUTO BOOT TIMEOUT IN SECONDS, 0 FOR IMMEDIATE BOOT
BOOT_DEFAULT .EQU 'Z' ; AUTO BOOT SELECTION TO INVOKE AT TIMEOUT
;
CPUOSC .EQU 8000000 ; CPU OSC FREQ IN MHZ
INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
MEMMGR .EQU MM_SBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
MPCL_ROM .EQU $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
;
RTC .EQU $70 ; RTC LATCH REGISTER ADR
PPIBASE .EQU $60 ; PRIMARY PARALLEL PORT REGISTERS BASE ADR
;
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
;
DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS
; ;
CRTACT .EQU FALSE ; CRT ACTIVATION AT STARTUP
VDAEMU .EQU EMUTYP_ANSI ; DEFAULT VDA EMULATION (EMUTYP_TTY, EMUTYP_ANSI, ...)
;
DSKYENABLE .EQU FALSE ; TRUE FOR DSKY SUPPORT (DO NOT COMBINE WITH PPIDE)
;
HTIMENABLE .EQU FALSE ; TRUE FOR SIMH TIMER SUPPORT
SIMRTCENABLE .EQU FALSE ; SIMH CLOCK DRIVER
DSRTCENABLE .EQU TRUE ; DS-1302 CLOCK DRIVER
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTCMODE_STD, DSRTCMODE_MFPIC
DSRTCCHG .EQU FALSE ; DS-1302 CONFIGURE CHARGE ON (TRUE) OR OFF (FALSE)
;
ASCIENABLE .EQU FALSE ; TRUE FOR Z180 ASCI SUPPORT
UARTENABLE .EQU TRUE ; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
UARTOSC .EQU 1843200 ; UART OSC FREQUENCY
UARTSBC .EQU TRUE ; ENABLE SBC/ZETA ONBOARD UART DETECTION
UARTCAS .EQU TRUE ; ENABLE ECB CASSETTE UART DETECTION
UARTMFP .EQU TRUE ; ENABLE MF/PIC UART DETECTION
UART4 .EQU TRUE ; ENABLE 4UART UART DETECTION
ACIAENABLE .EQU FALSE ; TRUE FOR MOTOROLA 6850 ACIA SUPPORT
;
SIOENABLE .EQU TRUE ; TRUE FOR ZILOG SIO SUPPORT
SIODEBUG .EQU FALSE ; PS
SIOCNT .EQU 1 ; 1 OR 2 SIO CHIPS (EACH CHIP HAS 2 CHANNELS)
SIO0MODE .EQU SIOMODE_ZP ; TYPE OF FIRST SIO TO DETECT: SIOMODE_RC/SMB/ZP/EZZ80
SIO0BASE .EQU $B0 ; IO PORT ADDRESS BASE FOR FIRST SIO CHIP
SIO0ACLK .EQU 4915200 ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
SIO0ADIV .EQU 8 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
SIO0ACFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG
SIO0BCLK .EQU 4915200 ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
SIO0BDIV .EQU 8 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
SIO0BCFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG
;
VDUENABLE .EQU FALSE ; TRUE FOR VDU BOARD SUPPORT
CVDUENABLE .EQU FALSE ; TRUE FOR CVDU BOARD SUPPORT
NECENABLE .EQU FALSE ; TRUE FOR uPD7220 BOARD SUPPORT
TMSENABLE .EQU FALSE ; TRUE FOR N8 (TMS9918) VIDEO/KBD SUPPORT
TMSMODE .EQU TMSMODE_SCG ; TMSMODE_[SCG/N8]
VGAENABLE .EQU FALSE ; TRUE FOR VGA VIDEO/KBD SUPPORT
VDUSIZ .EQU V80X25 ; VDU DISPLAY FORMAT V80X24, V80X25, V80X30
;
SPKENABLE .EQU FALSE ; TRUE FOR RTC LATCH IOBIT SOUND
AYENABLE .EQU FALSE ; TRUE FOR AY PSG SOUND
AYMODE .EQU AYMODE_SCG ; AYMODE_[SCG/N8/RCZ80/RCZ180]
;
MDENABLE .EQU TRUE ; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENABLED)
MDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE)
;
FDENABLE .EQU FALSE ; TRUE FOR FLOPPY SUPPORT
FDMODE .EQU FDMODE_DIO3 ; FDMODE_DIO, FDMODE_ZETA, FDMODE_DIDE, FDMODE_N8, FDMODE_DIO3
FDTRACE .EQU 1 ; 0=SILENT, 1=FATAL ERRORS, 2=ALL ERRORS, 3=EVERYTHING (ONLY RELEVANT IF FDENABLE = TRUE)
FDMEDIA .EQU FDM144 ; FDM720, FDM144, FDM360, FDM120 (ONLY RELEVANT IF FDENABLE = TRUE)
FDMEDIAALT .EQU FDM720 ; ALTERNATE MEDIA TO TRY, SAME CHOICES AS ABOVE (ONLY RELEVANT IF FDMAUTO = TRUE)
FDMAUTO .EQU TRUE ; SELECT BETWEEN MEDIA OPTS ABOVE AUTOMATICALLY
;
RFENABLE .EQU FALSE ; TRUE FOR RAM FLOPPY SUPPORT
RFCNT .EQU 1 ; NUMBER OF RAM FLOPPY UNITS (MAX IS 2)
;
IDEENABLE .EQU FALSE ; TRUE FOR IDE SUPPORT
IDEMODE .EQU IDEMODE_DIO ; IDEMODE_DIO, IDEMODE_DIDE
IDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
;
PPIDEENABLE .EQU FALSE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_SBC ; PPIDEMODE_SBC, PPPIDEMODE_DIO3, PPIDEMODE_MFP, PPIDEMODE_N8, PPIDEMODE_RC
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
;
SDENABLE .EQU FALSE ; TRUE FOR SD SUPPORT
SDMODE .EQU SDMODE_JUHA ; SDMODE_JUHA, SDMODE_CSIO, SDMODE_UART, SDMODE_PPI, SDMODE_DSD
SDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
SDCSIOFAST .EQU FALSE ; TABLE-DRIVEN BIT INVERTER
;
PRPENABLE .EQU FALSE ; TRUE FOR PROPIO SUPPORT
PRPSDENABLE .EQU TRUE ; TRUE FOR PROPIO SD SUPPORT
PRPSDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PRPSDENABLE = TRUE)
PRPCONENABLE .EQU TRUE ; TRUE FOR PROPIO CONSOLE SUPPORT (PS/2 KBD & VGA VIDEO)
;
PPPENABLE .EQU FALSE ; TRUE FOR PARPORTPROP SUPPORT
PPPSDENABLE .EQU TRUE ; TRUE FOR PARPORTPROP SD SUPPORT
PPPSDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPPENABLE = TRUE)
PPPCONENABLE .EQU TRUE ; TRUE FOR PROPIO CONSOLE SUPPORT (PS/2 KBD & VGA VIDEO)
;
HDSKENABLE .EQU FALSE ; TRUE FOR SIMH HDSK SUPPORT
HDSKTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
;
PPKTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPKENABLE = TRUE)
KBDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF KBDENABLE = TRUE)
PPKKBLOUT .EQU KBD_US ; KEYBOARD LANGUAGE (US/DE)
KBDKBLOUT .EQU KBD_US ; KEYBOARD LANGUAGE (US/DE)
;
TERMENABLE .EQU FALSE ; TERM PSEUDO DEVICE, WILL BE ENABLED IF A VDA IS ENABLED
ANSITRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF ANSIENABLE = TRUE)
;
BOOTTYPE .EQU BT_MENU ; BT_MENU (WAIT FOR KEYPRESS), BT_AUTO (BOOT_DEFAULT AFTER BOOT_TIMEOUT SECS)
BOOT_TIMEOUT .EQU 20 ; APPROX TIMEOUT IN SECONDS FOR AUTOBOOT, 0 FOR IMMEDIATE
BOOT_DEFAULT .EQU 'Z' ; SELECTION TO INVOKE AT TIMEOUT
;
PIO_4P .EQU FALSE ; TRUE FOR ECB-4PIO PIO SUPPORT
PIO_ZP .EQU FALSE ; TRUE FOR ECB-ZILOG PERIPHERALS BOARD
PPI_SBC .EQU FALSE ; TRUE FOR SBC V2 8255 (IF NOT BEING USED FOR PPIDE)
;
UFENABLE .EQU FALSE ; TRUE FOR ECB USB-FIFO SUPPORT
DSKYENABLE .EQU FALSE ; ENABLES DSKY (DO NOT COMBINE WITH PPIDE)
;
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
;
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
;
DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
;
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTSBC .EQU TRUE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
UARTCAS .EQU TRUE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU TRUE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU TRUE ; UART: AUTO-DETECT 4UART UART
;
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
;
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
;
SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
SIOCNT .EQU 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
SIO0MODE .EQU SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
SIO0BASE .EQU $B0 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .EQU 4915200 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0ADIV .EQU 8 ; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO0ACFG .EQU DEFSERCFG ; AIO 0A: SERIAL LINE CONFIG
SIO0BCLK .EQU 4915200 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0BDIV .EQU 8 ; SIO 0B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
;
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
VDUSIZ .EQU V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
NECENABLE .EQU FALSE ; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
TMSMODE .EQU TMSMODE_SCG ; TMS: DRIVER MODE: TMSMODE_[SCG/N8]
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
;
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
;
AYENABLE .EQU FALSE ; AY: ENABLE AY PSG SOUND DRIVER
AYMODE .EQU AYMODE_SCG ; AY: DRIVER MODE: AYMODE_[SCG/N8/RCZ80/RCZ180]
;
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
;
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .EQU FDMODE_DIO3 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3]
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
FDMEDIA .EQU FDM144 ; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
FDMEDIAALT .EQU FDM720 ; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
;
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
RFCNT .EQU 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-2)
;
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
IDEMODE .EQU IDEMODE_DIO ; IDE: DRIVER MODE: IDEMODE_[DIO|DIDE]
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
IDE8BIT .EQU FALSE ; IDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDEMODE .EQU PPIDEMODE_SBC ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC]
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC126]
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
;
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
;
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
;
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
HDSKTRACE .EQU 1 ; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
;
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
PIO4BASE .EQU $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
PIOZBASE .EQU $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
;
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
UFBASE .EQU $0C ; UF: REGISTERS BASE ADR

232
Source/HBIOS/cfg_sc126.asm

@ -3,113 +3,129 @@
; ROMWBW 2.X CONFIGURATION DEFAULTS FOR SC126 ; ROMWBW 2.X CONFIGURATION DEFAULTS FOR SC126
;================================================================================================== ;==================================================================================================
; ;
; BUILD CONFIGURATION OPTIONS
;
CPUOSC .EQU 18432000 ; CPU OSC FREQ
MEMMGR .EQU MM_Z180 ; MM_NONE, MM_SBC, MM_Z2, MM_N8, MM_Z180
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!!
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE)
INTMODE .EQU 2 ; 0=NONE, 1=INT MODE 1, 2=INT MODE 2
DIAGENABLE .EQU TRUE ; TRUE FOR DIAGNOSTIC CODE PORT OUTPUT
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
; UNDER THIS DIRECTORY.
;
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
; FOR THE PLATFORM.
;
#DEFINE PLATFORM_NAME "SC126"
;
PLATFORM .EQU PLT_SC126 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SC126]
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
;
BOOTTYPE .EQU BT_MENU ; BT_[MENU|AUTO], IF AUTO, BOOT DEFAULT AFTER TIMEOUT
BOOT_TIMEOUT .EQU 20 ; AUTO BOOT TIMEOUT IN SECONDS, 0 FOR IMMEDIATE BOOT
BOOT_DEFAULT .EQU 'Z' ; AUTO BOOT SELECTION TO INVOKE AT TIMEOUT
;
CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
RAMBIAS .EQU 512 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
;
Z180_BASE .EQU $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
;
RTC .EQU $0C ; RTC LATCH REGISTER ADR
;
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
;
DIAGENABLE .EQU TRUE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
DIAGPORT .EQU $0D ; DIAGNOSTIC PORT ADDRESS DIAGPORT .EQU $0D ; DIAGNOSTIC PORT ADDRESS
; ;
CRTACT .EQU FALSE ; CRT ACTIVATION AT STARTUP
VDAEMU .EQU EMUTYP_ANSI ; DEFAULT VDA EMULATION (EMUTYP_TTY, EMUTYP_ANSI, ...)
;
DSKYENABLE .EQU FALSE ; TRUE FOR DSKY SUPPORT (DO NOT COMBINE WITH PPIDE)
;
HTIMENABLE .EQU FALSE ; TRUE FOR SIMH TIMER SUPPORT
SIMRTCENABLE .EQU FALSE ; SIMH CLOCK DRIVER
DSRTCENABLE .EQU TRUE ; DS-1302 CLOCK DRIVER
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTCMODE_STD, DSRTCMODE_MFPIC
DSRTCCHG .EQU FALSE ; DS-1302 CONFIGURE CHARGE ON (TRUE) OR OFF (FALSE)
;
ASCIENABLE .EQU TRUE ; TRUE FOR Z180 ASCI SUPPORT
UARTENABLE .EQU FALSE ; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
UARTOSC .EQU 1843200 ; UART OSC FREQUENCY
ACIAENABLE .EQU FALSE ; TRUE FOR MOTOROLA 6850 ACIA SUPPORT
;
SIOENABLE .EQU TRUE ; TRUE FOR ZILOG SIO SUPPORT
SIODEBUG .EQU FALSE ; PS
SIOCNT .EQU 2 ; 1 OR 2 SIO CHIPS (EACH CHIP HAS 2 CHANNELS)
SIO0MODE .EQU SIOMODE_RC ; TYPE OF FIRST SIO TO DETECT: SIOMODE_RC/SMB/ZP/EZZ80
SIO0BASE .EQU $80 ; IO PORT ADDRESS BASE FOR FIRST SIO CHIP
SIO0ACLK .EQU 7372800 ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
SIO0ADIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
SIO0ACFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG
SIO0BCLK .EQU 7372800 ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
SIO0BDIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
SIO0BCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG
SIO1MODE .EQU SIOMODE_RC ; TYPE OF SECOND SIO TO DETECT: SIOMODE_RC, SIOMODE_SMB
SIO1BASE .EQU $84 ; IO PORT ADDRESS BASE FOR SECOND SIO CHIP
SIO1ACLK .EQU 7372800 ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
SIO1ADIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
SIO1ACFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG
SIO1BCLK .EQU 7372800 ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
SIO1BDIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
SIO1BCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG
;
VDUENABLE .EQU FALSE ; TRUE FOR VDU BOARD SUPPORT
CVDUENABLE .EQU FALSE ; TRUE FOR CVDU BOARD SUPPORT
NECENABLE .EQU FALSE ; TRUE FOR uPD7220 BOARD SUPPORT
TMSENABLE .EQU FALSE ; TRUE FOR N8 (TMS9918) VIDEO/KBD SUPPORT
VGAENABLE .EQU FALSE ; TRUE FOR VGA VIDEO/KBD SUPPORT
;
SPKENABLE .EQU FALSE ; TRUE FOR RTC LATCH IOBIT SOUND
AYENABLE .EQU FALSE ; TRUE FOR AY PSG SOUND
AYMODE .EQU AYMODE_RCZ180 ; AYMODE_[SCG/N8/RCZ80/RCZ180]
;
MDENABLE .EQU TRUE ; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENABLED)
MDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE)
;
FDENABLE .EQU FALSE ; TRUE FOR FLOPPY SUPPORT
FDMODE .EQU FDMODE_RCWDC ; FDMODE_DIO, FDMODE_ZETA, FDMODE_DIDE, FDMODE_N8, FDMODE_DIO3
FDTRACE .EQU 1 ; 0=SILENT, 1=FATAL ERRORS, 2=ALL ERRORS, 3=EVERYTHING (ONLY RELEVANT IF FDENABLE = TRUE)
FDMEDIA .EQU FDM144 ; FDM720, FDM144, FDM360, FDM120 (ONLY RELEVANT IF FDENABLE = TRUE)
FDMEDIAALT .EQU FDM720 ; ALTERNATE MEDIA TO TRY, SAME CHOICES AS ABOVE (ONLY RELEVANT IF FDMAUTO = TRUE)
FDMAUTO .EQU TRUE ; SELECT BETWEEN MEDIA OPTS ABOVE AUTOMATICALLY
;
RFENABLE .EQU FALSE ; TRUE FOR RAM FLOPPY SUPPORT
;
IDEENABLE .EQU FALSE ; TRUE FOR IDE SUPPORT
IDEMODE .EQU IDEMODE_RC ; IDEMODE_DIO, IDEMODE_DIDE, IDEMODE_RC
IDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
IDE8BIT .EQU TRUE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
;
PPIDEENABLE .EQU FALSE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_RC ; PPIDEMODE_SBC, PPPIDEMODE_DIO3, PPIDEMODE_MFP, PPIDEMODE_N8, PPIDEMODE_RC
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
;
SDENABLE .EQU TRUE ; TRUE FOR SD SUPPORT
SDMODE .EQU SDMODE_SC126 ; SDMODE_JUHA, SDMODE_CSIO, SDMODE_UART, SDMODE_PPI, SDMODE_DSD
SDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
SDCSIOFAST .EQU FALSE ; TABLE-DRIVEN BIT INVERTER
;
PRPENABLE .EQU FALSE ; TRUE FOR PROPIO SUPPORT
;
PPPENABLE .EQU FALSE ; TRUE FOR PARPORTPROP SUPPORT
PPPSDENABLE .EQU TRUE ; TRUE FOR PARPORTPROP SD SUPPORT
PPPSDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPPENABLE = TRUE)
PPPCONENABLE .EQU TRUE ; TRUE FOR PROPIO CONSOLE SUPPORT (PS/2 KBD & VGA VIDEO)
;
HDSKENABLE .EQU FALSE ; TRUE FOR SIMH HDSK SUPPORT
;
TERMENABLE .EQU FALSE ; TERM PSEUDO DEVICE, WILL BE ENABLED IF A VDA IS ENABLED
;
BOOTTYPE .EQU BT_MENU ; BT_MENU (WAIT FOR KEYPRESS), BT_AUTO (BOOT_DEFAULT AFTER BOOT_TIMEOUT SECS)
BOOT_TIMEOUT .EQU 20 ; APPROX TIMEOUT IN SECONDS FOR AUTOBOOT, 0 FOR IMMEDIATE
BOOT_DEFAULT .EQU 'Z' ; SELECTION TO INVOKE AT TIMEOUT
;
; 18.432MHz OSC @ FULL SPEED
;
Z180_CLKDIV .EQU 1 ; 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .EQU 0 ; MEMORY WAIT STATES (0-3)
Z180_IOWAIT .EQU 1 ; ADD (0-3) I/O WAIT STATES ABOVE 1 W/S BUILT-IN
;
PIO_4P .EQU FALSE ; TRUE FOR ECB-4PIO PIO SUPPORT
PIO_ZP .EQU FALSE ; TRUE FOR ECB-ZILOG PERIPHERALS BOARD
PPI_SBC .EQU FALSE ; TRUE FOR SBC V2 8255 (IF NOT BEING USED FOR PPIDE)
;
UFENABLE .EQU FALSE ; TRUE FOR ECB USB-FIFO SUPPORT
DSKYENABLE .EQU FALSE ; ENABLES DSKY (DO NOT COMBINE WITH PPIDE)
;
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
;
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
;
DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
;
UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
;
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
;
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
;
SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0ADIV .EQU 1 ; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO0ACFG .EQU SER_115200_8N1 ; AIO 0A: SERIAL LINE CONFIG
SIO0BCLK .EQU 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0BDIV .EQU 1 ; SIO 0B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO0BCFG .EQU SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG
SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR
SIO1ACLK .EQU 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO1ADIV .EQU 1 ; SIO 1A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO1ACFG .EQU SER_115200_8N1 ; AIO 1A: SERIAL LINE CONFIG
SIO1BCLK .EQU 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO1BDIV .EQU 1 ; SIO 1B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO1BCFG .EQU SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG
;
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
NECENABLE .EQU FALSE ; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
;
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
;
AYENABLE .EQU FALSE ; AY: ENABLE AY PSG SOUND DRIVER
AYMODE .EQU AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG/N8/RCZ80/RCZ180]
;
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
;
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3]
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
FDMEDIA .EQU FDM144 ; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
FDMEDIAALT .EQU FDM720 ; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
;
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
;
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
IDEMODE .EQU IDEMODE_RC ; IDE: DRIVER MODE: IDEMODE_[DIO|DIDE]
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
IDE8BIT .EQU TRUE ; IDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDEMODE .EQU PPIDEMODE_RC ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC]
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_SC126 ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC126]
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
;
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
;
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
;
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
;
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
;
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)

28
Source/HBIOS/cfg_una.asm

@ -3,14 +3,26 @@
; ROMWBW 2.X CONFIGURATION DEFAULTS FOR UNA ; ROMWBW 2.X CONFIGURATION DEFAULTS FOR UNA
;================================================================================================== ;==================================================================================================
; ;
; BUILD CONFIGURATION OPTIONS
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
; UNDER THIS DIRECTORY.
; ;
CPUOSC .EQU 18432000 ; CPU OSC FREQ
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!!
INTMODE .EQU 0 ; 0=NONE, 1=INT MODE 1, 2=INT MODE 2
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
; FOR THE PLATFORM.
; ;
DSKYENABLE .EQU FALSE ; TRUE FOR DSKY SUPPORT (DO NOT COMBINE WITH PPIDE)
#DEFINE PLATFORM_NAME "UNA"
; ;
BOOTTYPE .EQU BT_MENU ; BT_MENU (WAIT FOR KEYPRESS), BT_AUTO (BOOT_DEFAULT AFTER BOOT_TIMEOUT SECS)
BOOT_TIMEOUT .EQU 21 ; APPROX TIMEOUT IN SECONDS FOR AUTOBOOT, 0 FOR IMMEDIATE
BOOT_DEFAULT .EQU 'Z' ; SELECTION TO INVOKE AT TIMEOUT
PLATFORM .EQU PLT_UNA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SC126]
BIOS .EQU BIOS_UNA ; HARDWARE BIOS: BIOS_[WBW|UNA]
;
BOOTTYPE .EQU BT_MENU ; BT_[MENU|AUTO], IF AUTO, BOOT DEFAULT AFTER TIMEOUT
BOOT_TIMEOUT .EQU 20 ; AUTO BOOT TIMEOUT IN SECONDS, 0 FOR IMMEDIATE BOOT
BOOT_DEFAULT .EQU 'Z' ; AUTO BOOT SELECTION TO INVOKE AT TIMEOUT
;
CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ
INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
;
DSKYENABLE .EQU FALSE ; ENABLES DSKY (DO NOT COMBINE WITH PPIDE)

155
Source/HBIOS/cfg_zeta.asm

@ -3,89 +3,112 @@
; ROMWBW 2.X CONFIGURATION DEFAULTS FOR ZETA V1 ; ROMWBW 2.X CONFIGURATION DEFAULTS FOR ZETA V1
;================================================================================================== ;==================================================================================================
; ;
; BUILD CONFIGURATION OPTIONS
;
CPUOSC .EQU 20000000 ; CPU OSC FREQ
MEMMGR .EQU MM_SBC ; MM_NONE, MM_SBC, MM_Z2, MM_N8, MM_Z180
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!!
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE)
INTMODE .EQU 0 ; 0=NONE, 1=INT MODE 1, 2=INT MODE 2
DIAGENABLE .EQU FALSE ; TRUE FOR DIAGNOSTIC CODE PORT OUTPUT
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
; UNDER THIS DIRECTORY.
;
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
; FOR THE PLATFORM.
;
#DEFINE PLATFORM_NAME "ZETA"
;
PLATFORM .EQU PLT_ZETA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SC126]
CPUFAM .EQU CPU_Z80 ; CPU_[Z80|Z180]: CPU FAMILY
BIOS .EQU BIOS_WBW ; BIOS_[WBW|UNA]: HARDWARE BIOS
;
BOOTTYPE .EQU BT_MENU ; BT_[MENU|AUTO] IF AUTO, BOOT DEFAULT AFTER TIMEOUT
BOOT_TIMEOUT .EQU 20 ; AUTO BOOT TIMEOUT IN SECONDS, 0 FOR IMMEDIATE BOOT
BOOT_DEFAULT .EQU 'Z' ; AUTO BOOT SELECTION TO INVOKE AT TIMEOUT
;
CPUOSC .EQU 20000000 ; CPU OSC FREQ IN MHZ
INTMODE .EQU 0 ; INTERRUPT MODE: 0=NONE, 1=MODE 1, 2=MODE 2
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
MEMMGR .EQU MM_SBC ; MM_[SBC|Z2|N8|Z180]: MEMORY MANAGER
MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
MPCL_ROM .EQU $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
;
RTC .EQU $70 ; RTC LATCH REGISTER ADR
PPIBASE .EQU $60 ; PRIMARY PARALLEL PORT REGISTERS BASE ADR
;
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
;
DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS
; ;
CRTACT .EQU FALSE ; CRT ACTIVATION AT STARTUP
VDAEMU .EQU EMUTYP_ANSI ; DEFAULT VDA EMULATION (EMUTYP_TTY, EMUTYP_ANSI, ...)
DSKYENABLE .EQU FALSE ; ENABLES DSKY (DO NOT COMBINE WITH PPIDE)
;
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
;
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
;
DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
; ;
DSKYENABLE .EQU FALSE ; TRUE FOR DSKY SUPPORT (DO NOT COMBINE WITH PPIDE)
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTSBC .EQU TRUE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
; ;
HTIMENABLE .EQU FALSE ; TRUE FOR SIMH TIMER SUPPORT
SIMRTCENABLE .EQU FALSE ; SIMH CLOCK DRIVER
DSRTCENABLE .EQU TRUE ; DS-1302 CLOCK DRIVER
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTCMODE_STD, DSRTCMODE_MFPIC
DSRTCCHG .EQU FALSE ; DS-1302 CONFIGURE CHARGE ON (TRUE) OR OFF (FALSE)
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
; ;
ASCIENABLE .EQU FALSE ; TRUE FOR Z180 ASCI SUPPORT
UARTENABLE .EQU TRUE ; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
UARTOSC .EQU 1843200 ; UART OSC FREQUENCY
UARTSBC .EQU TRUE ; ENABLE SBC/ZETA ONBOARD UART DETECTION
UARTCAS .EQU FALSE ; ENABLE ECB CASSETTE UART DETECTION
UARTMFP .EQU FALSE ; ENABLE MF/PIC UART DETECTION
UART4 .EQU FALSE ; ENABLE 4UART UART DETECTION
SIOENABLE .EQU FALSE ; TRUE FOR ZILOG SIO/2 SUPPORT
SIOMODE .EQU SIOMODE_RC ; SIOMODE_RC, SIOMODE_SMB
ACIAENABLE .EQU FALSE ; TRUE FOR MOTOROLA 6850 ACIA SUPPORT
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
; ;
VDUENABLE .EQU FALSE ; TRUE FOR VDU BOARD SUPPORT
CVDUENABLE .EQU FALSE ; TRUE FOR CVDU BOARD SUPPORT
NECENABLE .EQU FALSE ; TRUE FOR uPD7220 BOARD SUPPORT
TMSENABLE .EQU FALSE ; TRUE FOR N8 (TMS9918) VIDEO/KBD SUPPORT
VGAENABLE .EQU FALSE ; TRUE FOR VGA VIDEO/KBD SUPPORT
SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
; ;
SPKENABLE .EQU FALSE ; TRUE FOR RTC LATCH IOBIT SOUND
AYENABLE .EQU FALSE ; TRUE FOR AY PSG SOUND
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
NECENABLE .EQU FALSE ; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
; ;
MDENABLE .EQU TRUE ; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENABLED)
MDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE)
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
; ;
FDENABLE .EQU TRUE ; TRUE FOR FLOPPY SUPPORT
FDMODE .EQU FDMODE_ZETA ; FDMODE_DIO, FDMODE_ZETA, FDMODE_DIDE, FDMODE_N8, FDMODE_DIO3
FDTRACE .EQU 1 ; 0=SILENT, 1=FATAL ERRORS, 2=ALL ERRORS, 3=EVERYTHING (ONLY RELEVANT IF FDENABLE = TRUE)
FDMEDIA .EQU FDM144 ; FDM720, FDM144, FDM360, FDM120 (ONLY RELEVANT IF FDENABLE = TRUE)
FDMEDIAALT .EQU FDM720 ; ALTERNATE MEDIA TO TRY, SAME CHOICES AS ABOVE (ONLY RELEVANT IF FDMAUTO = TRUE)
FDMAUTO .EQU TRUE ; SELECT BETWEEN MEDIA OPTS ABOVE AUTOMATICALLY
AYENABLE .EQU FALSE ; AY: ENABLE AY PSG SOUND DRIVER
; ;
RFENABLE .EQU FALSE ; TRUE FOR RAM FLOPPY SUPPORT
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
; ;
IDEENABLE .EQU FALSE ; TRUE FOR IDE SUPPORT
FDENABLE .EQU TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .EQU FDMODE_ZETA ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3]
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
FDMEDIA .EQU FDM144 ; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
FDMEDIAALT .EQU FDM720 ; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
; ;
PPIDEENABLE .EQU FALSE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_SBC ; PPIDEMODE_SBC, PPPIDEMODE_DIO3, PPIDEMODE_MFP, PPIDEMODE_N8, PPIDEMODE_RC
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
; ;
SDENABLE .EQU FALSE ; TRUE FOR SD SUPPORT
SDMODE .EQU SDMODE_PPI ; SDMODE_JUHA, SDMODE_CSIO, SDMODE_UART, SDMODE_PPI, SDMODE_DSD
SDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
SDCSIOFAST .EQU FALSE ; TABLE-DRIVEN BIT INVERTER
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
; ;
PRPENABLE .EQU FALSE ; TRUE FOR PROPIO SUPPORT
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDEMODE .EQU PPIDEMODE_SBC ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC]
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
; ;
PPPENABLE .EQU FALSE ; TRUE FOR PARPORTPROP SUPPORT
PPPSDENABLE .EQU TRUE ; TRUE FOR PARPORTPROP SD SUPPORT
PPPSDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPPENABLE = TRUE)
PPPCONENABLE .EQU TRUE ; TRUE FOR PROPIO CONSOLE SUPPORT (PS/2 KBD & VGA VIDEO)
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC126]
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
; ;
HDSKENABLE .EQU FALSE ; TRUE FOR SIMH HDSK SUPPORT
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
; ;
TERMENABLE .EQU FALSE ; TERM PSEUDO DEVICE, WILL BE ENABLED IF A VDA IS ENABLED
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
PPPSDENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
PPPSDTRACE .EQU 1 ; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPPCONENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
; ;
BOOTTYPE .EQU BT_MENU ; BT_MENU (WAIT FOR KEYPRESS), BT_AUTO (BOOT_DEFAULT AFTER BOOT_TIMEOUT SECS)
BOOT_TIMEOUT .EQU 20 ; APPROX TIMEOUT IN SECONDS FOR AUTOBOOT, 0 FOR IMMEDIATE
BOOT_DEFAULT .EQU 'Z' ; SELECTION TO INVOKE AT TIMEOUT
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
; ;
PIO_4P .EQU FALSE ; TRUE FOR ECB-4PIO PIO SUPPORT
PIO_ZP .EQU FALSE ; TRUE FOR ECB-ZILOG PERIPHERALS BOARD
PPI_SBC .EQU FALSE ; TRUE FOR SBC V2 8255 (IF NOT BEING USED FOR PPIDE)
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
; ;
UFENABLE .EQU FALSE ; TRUE FOR ECB USB-FIFO SUPPORT
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)

115
Source/HBIOS/cfg_zeta2.asm

@ -3,11 +3,116 @@
; ROMWBW 2.X CONFIGURATION DEFAULTS FOR ZETA V2 ; ROMWBW 2.X CONFIGURATION DEFAULTS FOR ZETA V2
;================================================================================================== ;==================================================================================================
; ;
; BUILD CONFIGURATION OPTIONS
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
; UNDER THIS DIRECTORY.
; ;
#INCLUDE "cfg_zeta.asm" ; USE ZETA CONFIG TO START
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
; FOR THE PLATFORM.
; ;
MEMMGR .SET MM_Z2 ; MM_NONE, MM_SBC, MM_Z2, MM_N8, MM_Z180
INTMODE .SET 2 ; 0=NONE, 1=INT MODE 1, 2=INT MODE 2
#DEFINE PLATFORM_NAME "ZETA V2"
; ;
FDMODE .SET FDMODE_ZETA2 ; FDMODE_DIO, FDMODE_ZETA, FDMODE_DIDE, FDMODE_N8, FDMODE_DIO3
PLATFORM .EQU PLT_ZETA2 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SC126]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
;
BOOTTYPE .EQU BT_MENU ; BT_[MENU|AUTO], IF AUTO, BOOT DEFAULT AFTER TIMEOUT
BOOT_TIMEOUT .EQU 20 ; AUTO BOOT TIMEOUT IN SECONDS, 0 FOR IMMEDIATE BOOT
BOOT_DEFAULT .EQU 'Z' ; AUTO BOOT SELECTION TO INVOKE AT TIMEOUT
;
CPUOSC .EQU 20000000 ; CPU OSC FREQ IN MHZ
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
;
RTC .EQU $70 ; RTC LATCH REGISTER ADR
PPIBASE .EQU $60 ; PRIMARY PARALLEL PORT REGISTERS BASE ADR
;
CTCENABLE .EQU TRUE ; ENABLE ZILOG CTC SUPPORT
CTCBASE .EQU $20 ; CTC BASE I/O ADDRESS
;
DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS
;
DSKYENABLE .EQU FALSE ; ENABLES DSKY (DO NOT COMBINE WITH PPIDE)
;
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
;
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
;
DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
;
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTSBC .EQU TRUE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
;
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
;
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
;
SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
;
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
NECENABLE .EQU FALSE ; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
;
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
;
AYENABLE .EQU FALSE ; AY: ENABLE AY PSG SOUND DRIVER
;
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
;
FDENABLE .EQU TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .EQU FDMODE_ZETA2 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3]
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
FDMEDIA .EQU FDM144 ; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
FDMEDIAALT .EQU FDM720 ; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
;
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
;
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
;
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDEMODE .EQU PPIDEMODE_SBC ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC]
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC126]
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
;
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
;
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
PPPSDENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
PPPSDTRACE .EQU 1 ; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPPCONENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
;
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
;
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
;
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)

40
Source/HBIOS/hbios.asm

@ -44,6 +44,25 @@
; THAT AN OS IMAGES FILE IS APPENDED TO THE END OF THE IMAGE AND IS LAUNCHED ; THAT AN OS IMAGES FILE IS APPENDED TO THE END OF THE IMAGE AND IS LAUNCHED
; AFTER HBIOS IS INSTALLED. ; AFTER HBIOS IS INSTALLED.
; ;
; INCLUDE FILE NESTING:
;
; hbios.asm
; - std.asm
; - ver.inc
; - hbios.inc
; - build.inc
; - config/<plt>_<cfg>.asm
; - cfg_<plt>.asm
; - <drivers>.asm
; - util.asm
; - time.asm
; - bcd.asm
; - decode.asm
; - encode.asm
; - [xio|mio].asm
; - dsky.asm
;
;
; INCLUDE GENERIC STUFF ; INCLUDE GENERIC STUFF
; ;
#INCLUDE "std.asm" #INCLUDE "std.asm"
@ -95,6 +114,15 @@ MODCNT .SET MODCNT + 1
; ;
; ;
; ;
#IF (CTCENABLE)
CTCA .EQU CTCBASE + 0 ; CTC: CHANNEL A REGISTER ADR
CTCB .EQU CTCBASE + 1 ; CTC: CHANNEL B REGISTER ADR
CTCC .EQU CTCBASE + 2 ; CTC: CHANNEL C REGISTER ADR
CTCD .EQU CTCBASE + 3 ; CTC: CHANNEL D REGISTER ADR
#ENDIF
;
;
;
#IFNDEF APPBOOT #IFNDEF APPBOOT
; ;
.ORG 0 .ORG 0
@ -1186,7 +1214,7 @@ PSCNX .EQU $ + 1
; START OF THE IVT, SO THE FIRST FOUR ENTIRES OF THE ; START OF THE IVT, SO THE FIRST FOUR ENTIRES OF THE
; IVT CORRESPOND TO CTC CHANNELS A-D ; IVT CORRESPOND TO CTC CHANNELS A-D
LD A,0 LD A,0
OUT (CTCBASE),A ; SETUP CTC BASE INT VECTOR
OUT (CTCA),A ; SETUP CTC BASE INT VECTOR
; ;
; CTCA IS SLAVED (WIRED) TO TO CTCB TO ACT AS A PRESCALER ; CTCA IS SLAVED (WIRED) TO TO CTCB TO ACT AS A PRESCALER
; CONFIGURE CHANNEL B FOR 50HZ PERIODIC INTERRUPTS ; CONFIGURE CHANNEL B FOR 50HZ PERIODIC INTERRUPTS
@ -1241,9 +1269,9 @@ PSCNX .EQU $ + 1
; START OF THE IVT, SO THE FIRST FOUR ENTIRES OF THE ; START OF THE IVT, SO THE FIRST FOUR ENTIRES OF THE
; IVT CORRESPOND TO CTC CHANNELS A-D ; IVT CORRESPOND TO CTC CHANNELS A-D
LD A,0 LD A,0
OUT (CTCBASE),A ; SETUP CTC BASE INT VECTOR
OUT (CTCA),A ; SETUP CTC BASE INT VECTOR
; ;
; CTCC IS SLAVED (WIRED) TO TO CTCD TO ACT AS A PRESCALER
; CTCC IS SLAVED (WIRED) TO CTCD TO ACT AS A PRESCALER
; CONFIGURE CHANNEL D FOR 50HZ PERIODIC INTERRUPTS ; CONFIGURE CHANNEL D FOR 50HZ PERIODIC INTERRUPTS
; CTC CLK = 921,200HZ ; CTC CLK = 921,200HZ
; CTCC TIME CONSTANT = 256 ; CTCC TIME CONSTANT = 256
@ -1428,7 +1456,7 @@ HB_PCPU:
; IF PLATFORM HAS A CONFIG JUMPER, CHECK TO SEE IF IT IS JUMPERED. ; IF PLATFORM HAS A CONFIG JUMPER, CHECK TO SEE IF IT IS JUMPERED.
; IF SO, BYPASS SWITCH TO CRT CONSOLE (FAILSAFE MODE) ; IF SO, BYPASS SWITCH TO CRT CONSOLE (FAILSAFE MODE)
; ;
#IF ((PLATFORM != PLT_N8) & (PLATFORM != PLT_MK4) & (PLATFORM != PLT_RCZ80) & (PLATFORM != PLT_RCZ180) & (PLATFORM != PLT_EZZ80))
#IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_ZETA) | (PLATFORM == PLT_ZETA2))
IN A,(RTC) ; RTC PORT, BIT 6 HAS STATE OF CONFIG JUMPER IN A,(RTC) ; RTC PORT, BIT 6 HAS STATE OF CONFIG JUMPER
BIT 6,A ; BIT 6 HAS CONFIG JUMPER STATE BIT 6,A ; BIT 6 HAS CONFIG JUMPER STATE
JR Z,INITSYS3 ; Z=SHORTED, BYPASS CONSOLE SWITCH JR Z,INITSYS3 ; Z=SHORTED, BYPASS CONSOLE SWITCH
@ -2798,9 +2826,9 @@ SIZ_PIO .EQU $ - ORG_PIO
; ;
#IF (UFENABLE) #IF (UFENABLE)
ORG_UF .EQU $ ORG_UF .EQU $
#INCLUDE "usbfifo.asm"
#INCLUDE "uf.asm"
SIZ_UF .EQU $ - ORG_UF SIZ_UF .EQU $ - ORG_UF
.ECHO "USB-FIFO occupies "
.ECHO "UF occupies "
.ECHO SIZ_UF .ECHO SIZ_UF
.ECHO " bytes.\n" .ECHO " bytes.\n"
#ENDIF #ENDIF

7
Source/HBIOS/ide.asm

@ -110,7 +110,8 @@ IDE_DEVCNT .EQU 2 ; ASSUME ONLY PRIMARY INTERFACE
IDE_IO_BASE .EQU $20 ; DEFAULT IO BASE (NOTE OVERRIDES BELOW) IDE_IO_BASE .EQU $20 ; DEFAULT IO BASE (NOTE OVERRIDES BELOW)
; ;
#IF (IDEMODE == IDEMODE_MK4) #IF (IDEMODE == IDEMODE_MK4)
IDE_IO_BASE .SET MK4_IDE
IDE_IO_BASE .SET $80
IDE_XAR .EQU $88 ; EXTERNAL ADDRESS REGISTER (XAR)#ENDIF
#ENDIF #ENDIF
#IF (IDEMODE == IDEMODE_RC) #IF (IDEMODE == IDEMODE_RC)
@ -806,11 +807,11 @@ IDE_RESET:
#IF (IDEMODE == IDEMODE_MK4) #IF (IDEMODE == IDEMODE_MK4)
; USE HARDWARE RESET LINE ; USE HARDWARE RESET LINE
LD A,$80 ; HIGH BIT OF XAR IS IDE RESET LD A,$80 ; HIGH BIT OF XAR IS IDE RESET
OUT (MK4_XAR),A
OUT (IDE_XAR),A
LD DE,2 ; DELAY 32US (SPEC IS >= 25US) LD DE,2 ; DELAY 32US (SPEC IS >= 25US)
CALL VDELAY CALL VDELAY
XOR A ; CLEAR RESET BIT XOR A ; CLEAR RESET BIT
OUT (MK4_XAR),A
OUT (IDE_XAR),A
#ENDIF #ENDIF
#IF ((IDEMODE == IDEMODE_RC) | (IDEMODE == IDEMODE_SMB)) #IF ((IDEMODE == IDEMODE_RC) | (IDEMODE == IDEMODE_SMB))

20
Source/HBIOS/plt_ezz80.inc

@ -1,20 +0,0 @@
;
; EASY Z80 HARDWARE DEFINITIONS
;
#DEFINE PLATFORM_NAME "EASYZ80"
;
MPGSEL_0 .EQU $78 ; BANK_0 PAGE SELECT REGISTER (WRITE ONLY)
MPGSEL_1 .EQU $79 ; BANK_1 PAGE SELECT REGISTER (WRITE ONLY)
MPGSEL_2 .EQU $7A ; BANK_2 PAGE SELECT REGISTER (WRITE ONLY)
MPGSEL_3 .EQU $7B ; BANK_3 PAGE SELECT REGISTER (WRITE ONLY)
MPGENA .EQU $7C ; PAGING ENABLE REGISTER - BIT 0 = 1 (WRITE ONLY)
;
RTC .EQU $C0 ; RTC PORT address
;
WDOG .EQU $6F ; WATCHDOG
;
CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS
CTCA .EQU CTCBASE + 0 ; CTC CHANNEL A
CTCB .EQU CTCBASE + 1 ; CTC CHANNEL B
CTCC .EQU CTCBASE + 2 ; CTC CHANNEL C
CTCD .EQU CTCBASE + 3 ; CTC CHANNEL D

22
Source/HBIOS/plt_mk4.inc

@ -1,22 +0,0 @@
;
; MARK IV HARDWARE DEFINITIONS
;
#DEFINE PLATFORM_NAME "MARK IV"
;
RAMBIAS .EQU 512 ; RAM STARTS AT 512K
;
MK4_BASE .EQU $80 ; I/O BASE ADDRESS FOR ONBOARD PERIPHERALS
;
MK4_IDE .EQU MK4_BASE + $00 ; IDE REGISTERS ($00-$07, $0E-$0F)
MK4_XAR .EQU MK4_BASE + $08 ; EXTERNAL ADDRESS REGISTER (XAR)
MK4_SD .EQU MK4_BASE + $09 ; SD CARD CONTROL REGISTER
MK4_RTC .EQU MK4_BASE + $0A ; RTC INTERFACE REGISTER
;
RTC .EQU MK4_RTC ; GENERIC ALIAS FOR RTC PORT
;
Z180_BASE .EQU $40 ; I/O BASE ADDRESS FOR INTERNAL Z180 REGISTERS
;
;
FIFO_BASE .EQU $0C ; ECB USB-FIFO DEFAULT PORT
;
#INCLUDE "z180.inc"

28
Source/HBIOS/plt_n8.inc

@ -1,28 +0,0 @@
;
; N8 HARDWARE DEFINITIONS
;
#DEFINE PLATFORM_NAME "N8"
;
RAMBIAS .EQU 0 ; RAM STARTS AT 0K
;
N8_BASE .EQU $80 ; I/O BASE ADDRESS FOR ONBOARD PERIPHERALS
;
N8_PPI0 .EQU N8_BASE + $00 ; FIRST PARALLEL PORT
N8_PPI1 .EQU N8_BASE + $04 ; SECOND PARALLEL PORT
N8_RTC .EQU N8_BASE + $08 ; RTC LATCH AND BUFFER
N8_FDC .EQU N8_BASE + $0C ; FLOPPY DISK CONTROLLER
N8_UTIL .EQU N8_BASE + $10 ; FLOPPY DISK UTILITY
N8_ACR .EQU N8_BASE + $14 ; AUXILLARY CONTROL REGISTER
N8_RMAP .EQU N8_BASE + $16 ; ROM PAGE REGISTER
N8_VDP .EQU N8_BASE + $18 ; VIDEO DISPLAY PROCESSOR (TMS9918A)
N8_PSG .EQU N8_BASE + $1C ; PROGRAMMABLE SOUND GENERATOR (AY-3-8910)
;
N8_DEFACR .EQU $1B ; DEFAULT VALUE FOR ACR REGISTER
;
RTC .EQU N8_RTC ; GENERIC ALIAS FOR RTC PORT
PPIBASE .EQU N8_PPI0 ; GENERIC ALIAS FOR PRIMARY PARALLEL PORT
;
FIFO_BASE .EQU $0C ; ECB USB-FIFO DEFAULT PORT
;
Z180_BASE .EQU $40 ; I/O BASE ADDRESS FOR INTERNAL Z180 REGISTERS
#INCLUDE "z180.inc"

18
Source/HBIOS/plt_rcz180.inc

@ -1,18 +0,0 @@
;
; RC2014 Z180 HARDWARE DEFINITIONS
;
#DEFINE PLATFORM_NAME "RC2014"
;
RAMBIAS .EQU 512 ; RAM STARTS AT 512K
;
MPGSEL_0 .EQU $78 ; BANK_0 PAGE SELECT REGISTER (WRITE ONLY)
MPGSEL_1 .EQU $79 ; BANK_1 PAGE SELECT REGISTER (WRITE ONLY)
MPGSEL_2 .EQU $7A ; BANK_2 PAGE SELECT REGISTER (WRITE ONLY)
MPGSEL_3 .EQU $7B ; BANK_3 PAGE SELECT REGISTER (WRITE ONLY)
MPGENA .EQU $7C ; PAGING ENABLE REGISTER - BIT 0 = 1 (WRITE ONLY)
;
RTC .EQU $0C ; ADDRESS OF RTC LATCH AND INPUT PORT
;
Z180_BASE .EQU $C0 ; I/O BASE ADDRESS FOR INTERNAL Z180 REGISTERS
;
#INCLUDE "z180.inc"

12
Source/HBIOS/plt_rcz80.inc

@ -1,12 +0,0 @@
;
; RC2014 HARDWARE DEFINITIONS
;
#DEFINE PLATFORM_NAME "RC2014"
;
MPGSEL_0 .EQU $78 ; BANK_0 PAGE SELECT REGISTER (WRITE ONLY)
MPGSEL_1 .EQU $79 ; BANK_1 PAGE SELECT REGISTER (WRITE ONLY)
MPGSEL_2 .EQU $7A ; BANK_2 PAGE SELECT REGISTER (WRITE ONLY)
MPGSEL_3 .EQU $7B ; BANK_3 PAGE SELECT REGISTER (WRITE ONLY)
MPGENA .EQU $7C ; PAGING ENABLE REGISTER - BIT 0 = 1 (WRITE ONLY)
;
RTC .EQU $C0 ; RTC PORT address

28
Source/HBIOS/plt_sbc.inc

@ -1,28 +0,0 @@
;
; SBC HARDWARE DEFINITIONS
;
#DEFINE PLATFORM_NAME "SBC"
;
SBC_BASE .EQU $60 ; I/O BASE ADDRESS FOR ONBOARD PERIPHERALS
;
#IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_ZETA))
; BIT 7 OF MPCL_ROM SELECTS ROM/RAM (0=ROM, 1=RAM)
MPCL_RAM .EQU SBC_BASE + $18 ; MEMORY PAGER CONFIG LATCH - RAM (WRITE ONLY)
MPCL_ROM .EQU SBC_BASE + $1C ; MEMORY PAGER CONFIG LATCH - ROM (WRITE ONLY)
#ENDIF
;
#IF (PLATFORM == PLT_ZETA2)
MPGSEL_0 .EQU SBC_BASE + $18 ; BANK_0 PAGE SELECT REGISTER (WRITE ONLY)
MPGSEL_1 .EQU SBC_BASE + $19 ; BANK_1 PAGE SELECT REGISTER (WRITE ONLY)
MPGSEL_2 .EQU SBC_BASE + $1A ; BANK_2 PAGE SELECT REGISTER (WRITE ONLY)
MPGSEL_3 .EQU SBC_BASE + $1B ; BANK_3 PAGE SELECT REGISTER (WRITE ONLY)
MPGENA .EQU SBC_BASE + $1C ; PAGING ENABLE REGISTER - BIT 0 = 1 (WRITE ONLY)
#ENDIF
;
RTC .EQU SBC_BASE + $10 ; ADDRESS OF RTC LATCH AND INPUT PORT
PPIBASE .EQU SBC_BASE + $00 ; PPI 82C55 I/O IS DECODED TO PORT 60-67
PIOZBASE .EQU $88 ; ZILOG PERIPHERALS DEFAULT PIO DEFAULT
PIO4BASE .EQU $90 ; ECB-4PIO DEFAULT PIO DEFAULT
;
;
FIFO_BASE .EQU $0C ; ECB USB-FIFO DEFAULT PORT

12
Source/HBIOS/plt_sc126.inc

@ -1,12 +0,0 @@
;
; SC126 Z180 HARDWARE DEFINITIONS
;
#DEFINE PLATFORM_NAME "SC126"
;
RAMBIAS .EQU 512 ; RAM STARTS AT 512K
;
RTC .EQU $0C ; ADDRESS OF RTC LATCH AND INPUT PORT
;
Z180_BASE .EQU $C0 ; I/O BASE ADDRESS FOR INTERNAL Z180 REGISTERS
;
#INCLUDE "z180.inc"

4
Source/HBIOS/plt_una.inc

@ -1,4 +0,0 @@
;
; UNA HARDWARE DEFINITIONS
;
#DEFINE PLATFORM_NAME "UNA"

14
Source/HBIOS/plt_zeta.inc

@ -1,14 +0,0 @@
;
; ZETA HARDWARE DEFINITIONS
;
;
#DEFINE PLATFORM_NAME "ZETA"
;
SBC_BASE .EQU $60 ; I/O BASE ADDRESS FOR ONBOARD PERIPHERALS
;
; BIT 7 OF MPCL_ROM SELECTS ROM/RAM (0=ROM, 1=RAM)
MPCL_RAM .EQU SBC_BASE + $18 ; MEMORY PAGER CONFIG LATCH - RAM (WRITE ONLY)
MPCL_ROM .EQU SBC_BASE + $1C ; MEMORY PAGER CONFIG LATCH - ROM (WRITE ONLY)
;
RTC .EQU SBC_BASE + $10 ; ADDRESS OF RTC LATCH AND INPUT PORT
PPIBASE .EQU SBC_BASE + $00 ; PPI 82C55 I/O IS DECODED TO PORT 60-67

21
Source/HBIOS/plt_zeta2.inc

@ -1,21 +0,0 @@
;
; ZETA 2 HARDWARE DEFINITIONS
;
#DEFINE PLATFORM_NAME "ZETA V2"
;
SBC_BASE .EQU $60 ; I/O BASE ADDRESS FOR ONBOARD PERIPHERALS
;
MPGSEL_0 .EQU SBC_BASE + $18 ; BANK_0 PAGE SELECT REGISTER (WRITE ONLY)
MPGSEL_1 .EQU SBC_BASE + $19 ; BANK_1 PAGE SELECT REGISTER (WRITE ONLY)
MPGSEL_2 .EQU SBC_BASE + $1A ; BANK_2 PAGE SELECT REGISTER (WRITE ONLY)
MPGSEL_3 .EQU SBC_BASE + $1B ; BANK_3 PAGE SELECT REGISTER (WRITE ONLY)
MPGENA .EQU SBC_BASE + $1C ; PAGING ENABLE REGISTER - BIT 0 = 1 (WRITE ONLY)
;
RTC .EQU SBC_BASE + $10 ; ADDRESS OF RTC LATCH AND INPUT PORT
PPIBASE .EQU SBC_BASE + $00 ; PPI 82C55 I/O IS DECODED TO PORT 60-67
;
CTCBASE .EQU $20 ; CTC BASE I/O ADDRESS
CTCA .EQU CTCBASE + 0 ; CTC CHANNEL A
CTCB .EQU CTCBASE + 1 ; CTC CHANNEL B
CTCC .EQU CTCBASE + 2 ; CTC CHANNEL C
CTCD .EQU CTCBASE + 3 ; CTC CHANNEL D

2
Source/HBIOS/sd.asm

@ -187,7 +187,7 @@ SD_DO .EQU %00000001 ; RTC:0 IS DATA OUT (CARD -> CPU)
; ;
#IF (SDMODE == SDMODE_MK4) ; MARK IV (CSIO STYLE INTERFACE) #IF (SDMODE == SDMODE_MK4) ; MARK IV (CSIO STYLE INTERFACE)
SD_DEVCNT .EQU 1 ; NUMBER OF PHYSICAL UNITS (SOCKETS) SD_DEVCNT .EQU 1 ; NUMBER OF PHYSICAL UNITS (SOCKETS)
SD_OPRREG .EQU MK4_SD ; DEDICATED MK4 SDCARD REGISTER
SD_OPRREG .EQU $89 ; DEDICATED MK4 SDCARD REGISTER
SD_OPRDEF .EQU %00000000 ; QUIESCENT STATE SD_OPRDEF .EQU %00000000 ; QUIESCENT STATE
SD_CS .EQU %00000100 ; SELECT ACTIVE SD_CS .EQU %00000100 ; SELECT ACTIVE
SD_CNTR .EQU Z180_CNTR SD_CNTR .EQU Z180_CNTR

87
Source/HBIOS/std.asm

@ -1,12 +1,11 @@
; The purpose of this file is to define generic symbols and to include ; The purpose of this file is to define generic symbols and to include
; The purpose of this file is to define generic symbols and to include
; the appropriate std-*.inc file to bring in platform specifics.
; the requested build configuraton file to bring in platform specifics.
; There are several classes of systems supported by SBC.
; There are several hardware platforms supported by SBC.
; 1. SBC Z80 SBC (v1 or v2) w/ ECB interface ; 1. SBC Z80 SBC (v1 or v2) w/ ECB interface
; 2. ZETA Standalone Z80 SBC w/ SBC compatibility ; 2. ZETA Standalone Z80 SBC w/ SBC compatibility
; 3. ZETA2 Second version of ZETA with enhanced memory bank switching ; 3. ZETA2 Second version of ZETA with enhanced memory bank switching
; 4. N8 MSX-compatible Z180 SBC w/ onboard video and sound
; 4. N8 MSX-ish Z180 SBC w/ onboard video and sound
; 5. MK4 Mark IV Z180 based SBC w/ ECB interface ; 5. MK4 Mark IV Z180 based SBC w/ ECB interface
; 6. UNA Any Z80/Z180 computer with UNA BIOS ; 6. UNA Any Z80/Z180 computer with UNA BIOS
; 7. RCZ80 RC2014 based system with 512K banked RAM/ROM card ; 7. RCZ80 RC2014 based system with 512K banked RAM/ROM card
@ -14,12 +13,6 @@
; 9. EZZ80 Easy Z80, Z80 SBC w/ RC2014 bus and CTC ; 9. EZZ80 Easy Z80, Z80 SBC w/ RC2014 bus and CTC
; 10. SC126 SC126 Z180 based system ; 10. SC126 SC126 Z180 based system
; All the classes require certain generic definitions, and these are
; defined here prior to the inclusion of platform specific .inc files.
; It is unfortunate, but all the possible config items must be defined
; here because the config gets read before the specific std-*.inc's
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; ;
; INCLUDE VERSION ; INCLUDE VERSION
@ -106,11 +99,6 @@ DSRTCMODE_NONE .EQU 0 ; NO DSRTC
DSRTCMODE_STD .EQU 1 ; ORIGINAL DSRTC CIRCUIT (SBC, ZETA, MK4) DSRTCMODE_STD .EQU 1 ; ORIGINAL DSRTC CIRCUIT (SBC, ZETA, MK4)
DSRTCMODE_MFPIC .EQU 2 ; MF/PIC VARIANT DSRTCMODE_MFPIC .EQU 2 ; MF/PIC VARIANT
; ;
; ACIA MODE SELECTIONS
;
ACIAMODE_NONE .EQU 0
ACIAMODE_RC .EQU 1 ; RC2014 ACIA MODULE (SPENCER OWEN)
;
; SIO MODE SELECTIONS ; SIO MODE SELECTIONS
; ;
SIOMODE_NONE .EQU 0 SIOMODE_NONE .EQU 0
@ -271,6 +259,11 @@ SER_1843200_8N1 .EQU SER_BAUD1843200 | SER_DATA8 | SER_PARNONE | SER_STOP1
SER_3686400_8N1 .EQU SER_BAUD3686400 | SER_DATA8 | SER_PARNONE | SER_STOP1 SER_3686400_8N1 .EQU SER_BAUD3686400 | SER_DATA8 | SER_PARNONE | SER_STOP1
SER_7372800_8N1 .EQU SER_BAUD7372800 | SER_DATA8 | SER_PARNONE | SER_STOP1 SER_7372800_8N1 .EQU SER_BAUD7372800 | SER_DATA8 | SER_PARNONE | SER_STOP1
; ;
; TERMENABLE CONTROLS INCLUSION OF TERMINAL PSEUDO-DEVICE DRIVER
; IT IS SET TO TRUE BY THE INCLUSION OF ANY VDA DRIVER.
;
TERMENABLE .EQU FALSE ; TERM PSEUDO DEVICE, WILL AUTO-ENABLE IF A VDA IS ENABLED
;
; ECB-VDU MODES ; ECB-VDU MODES
; ;
V80X24 .EQU 0 V80X24 .EQU 0
@ -293,64 +286,19 @@ FORCECON .EQU 0 ; DEFAULT IS TO FOLLOW NORMAL SEQUENCE
; ;
#INCLUDE "build.inc" ; INCLUDE USER CONFIG, ADD VARIANT, TIMESTAMP, & ROMSIZE #INCLUDE "build.inc" ; INCLUDE USER CONFIG, ADD VARIANT, TIMESTAMP, & ROMSIZE
; ;
#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180) | (PLATFORM == PLT_SC126))
CPUFAM .EQU CPU_Z180
#ELSE
CPUFAM .EQU CPU_Z80
#ENDIF
;
#IF (PLATFORM == PLT_UNA)
BIOS .EQU BIOS_UNA
#ELSE
BIOS .EQU BIOS_WBW
#ENDIF
;
; INCLUDE PLATFORM SPECIFIC HARDWARE DEFINITIONS
;
#IF (PLATFORM == PLT_SBC)
#INCLUDE "plt_sbc.inc"
#ENDIF
;
#IF (PLATFORM == PLT_ZETA)
#INCLUDE "plt_zeta.inc"
#ENDIF
;
#IF (PLATFORM == PLT_ZETA2)
#INCLUDE "plt_zeta2.inc"
#ENDIF
; INCLUDE Z180 REGISTER DEFINITIONS
; ;
#IF (PLATFORM == PLT_N8)
#INCLUDE "plt_n8.inc"
#ENDIF
;
#IF (PLATFORM == PLT_MK4)
#INCLUDE "plt_mk4.inc"
#ENDIF
;
#IF (PLATFORM == PLT_UNA)
#INCLUDE "plt_una.inc"
#ENDIF
;
#IF (PLATFORM == PLT_RCZ80)
#INCLUDE "plt_rcz80.inc"
#ENDIF
;
#IF (PLATFORM == PLT_RCZ180)
#INCLUDE "plt_rcz180.inc"
#ENDIF
;
#IF (PLATFORM == PLT_EZZ80)
#INCLUDE "plt_ezz80.inc"
#IF (BIOS == BIOS_WBW)
#IF (CPUFAM == CPU_Z180)
#INCLUDE "z180.inc"
#ENDIF #ENDIF
;
#IF (PLATFORM == PLT_SC126)
#INCLUDE "plt_sc126.inc"
#ENDIF #ENDIF
; ;
; SETUP DEFAULT CPU SPEED VALUES ; SETUP DEFAULT CPU SPEED VALUES
; ;
CPUKHZ .EQU CPUOSC / 1000 ; CPU FREQ IN KHZ CPUKHZ .EQU CPUOSC / 1000 ; CPU FREQ IN KHZ
; ;
#IF (BIOS == BIOS_WBW)
#IF (CPUFAM == CPU_Z180) #IF (CPUFAM == CPU_Z180)
#IF (Z180_CLKDIV == 0) #IF (Z180_CLKDIV == 0)
CPUKHZ .SET CPUKHZ / 2 ; ADJUST FOR HALF SPEED OPERATION CPUKHZ .SET CPUKHZ / 2 ; ADJUST FOR HALF SPEED OPERATION
@ -359,6 +307,7 @@ CPUKHZ .SET CPUKHZ / 2 ; ADJUST FOR HALF SPEED OPERATION
CPUKHZ .SET CPUKHZ * 2 ; ADJUST FOR DOUBLE SPEED OPERATION CPUKHZ .SET CPUKHZ * 2 ; ADJUST FOR DOUBLE SPEED OPERATION
#ENDIF #ENDIF
#ENDIF #ENDIF
#ENDIF
; ;
CPUMHZ .EQU CPUKHZ / 1000 ; CPU FREQ IN MHZ CPUMHZ .EQU CPUKHZ / 1000 ; CPU FREQ IN MHZ
; ;
@ -472,10 +421,10 @@ INT_SIO1 .EQU 14 ; ZILOG SIO 1, CHANNEL A & B
; Z80-BASED SYSTEMS ; Z80-BASED SYSTEMS
INT_CTC0A .EQU 0 ; ZILOG CTC #0, CHANNEL A
INT_CTC0B .EQU 1 ; ZILOG CTC #0, CHANNEL B
INT_CTC0C .EQU 2 ; ZILOG CTC #0, CHANNEL C
INT_CTC0D .EQU 3 ; ZILOG CTC #0, CHANNEL D
INT_CTC0A .EQU 0 ; ZILOG CTC 0, CHANNEL A
INT_CTC0B .EQU 1 ; ZILOG CTC 0, CHANNEL B
INT_CTC0C .EQU 2 ; ZILOG CTC 0, CHANNEL C
INT_CTC0D .EQU 3 ; ZILOG CTC 0, CHANNEL D
INT_SIO0 .EQU 7 ; ZILOG SIO 0, CHANNEL A & B INT_SIO0 .EQU 7 ; ZILOG SIO 0, CHANNEL A & B
INT_SIO1 .EQU 8 ; ZILOG SIO 1, CHANNEL A & B INT_SIO1 .EQU 8 ; ZILOG SIO 1, CHANNEL A & B
INT_PIO0A .EQU 9 ; ZILOG PIO 0, CHANNEL A INT_PIO0A .EQU 9 ; ZILOG PIO 0, CHANNEL A

12
Source/HBIOS/tms.asm

@ -16,13 +16,13 @@
; ;
#IF (TMSMODE == TMSMODE_N8) #IF (TMSMODE == TMSMODE_N8)
TMS_DATREG .EQU N8_BASE + $18 ; READ/WRITE DATA
TMS_CMDREG .EQU N8_BASE + $19 ; READ STATUS / WRITE REG SEL
TMS_DATREG .EQU $98 ; READ/WRITE DATA
TMS_CMDREG .EQU $99 ; READ STATUS / WRITE REG SEL
TMS_PPIA .EQU N8_BASE + $04 ; PPI PORT A
TMS_PPIB .EQU N8_BASE + $05 ; PPI PORT B
TMS_PPIC .EQU N8_BASE + $06 ; PPI PORT C
TMS_PPIX .EQU N8_BASE + $07 ; PPI CONTROL PORT
TMS_PPIA .EQU $84 ; PPI PORT A
TMS_PPIB .EQU $85 ; PPI PORT B
TMS_PPIC .EQU $86 ; PPI PORT C
TMS_PPIX .EQU $87 ; PPI CONTROL PORT
#ENDIF #ENDIF

8
Source/HBIOS/usbfifo.asm → Source/HBIOS/uf.asm

@ -13,9 +13,9 @@
; UF_PREINIT SETUP THE DISPATCH TABLE ENTRY AND INITIALIZE HARDWARE ; UF_PREINIT SETUP THE DISPATCH TABLE ENTRY AND INITIALIZE HARDWARE
; UF_INIT ANNOUNCE DEVICE DESCRIPTION AND PORT ; UF_INIT ANNOUNCE DEVICE DESCRIPTION AND PORT
; ;
FIFO_DATA .EQU (FIFO_BASE+0) ; READ/WRITE DATA
FIFO_STATUS .EQU (FIFO_BASE+1) ; READ/WRITE STATUS
FIFO_SEND_IMM .EQU (FIFO_BASE+2) ; WRITE PORT TO FORCE BUFFER FLUSH
FIFO_DATA .EQU (UFBASE+0) ; READ/WRITE DATA
FIFO_STATUS .EQU (UFBASE+1) ; READ/WRITE STATUS
FIFO_SEND_IMM .EQU (UFBASE+2) ; WRITE PORT TO FORCE BUFFER FLUSH
FIFO_BUFFER .EQU FALSE ; OPTION TO BUFFER OUTPUT FOR 17ms FIFO_BUFFER .EQU FALSE ; OPTION TO BUFFER OUTPUT FOR 17ms
; ;
UF_USB_ACTIVE .DB 0 ; USB CABLE CONNECTED STATUS FLAG UF_USB_ACTIVE .DB 0 ; USB CABLE CONNECTED STATUS FLAG
@ -58,7 +58,7 @@ UF_INIT:
CALL NEWLINE ; PRINT DEVICE CALL NEWLINE ; PRINT DEVICE
PRTS("USB-FIFO: $") PRTS("USB-FIFO: $")
PRTS("IO=0x$") PRTS("IO=0x$")
LD A,FIFO_BASE ; PRINT PORT
LD A,UFBASE ; PRINT PORT
CALL PRTHEXBYTE CALL PRTHEXBYTE
LD A,(UF_USB_ACTIVE) ; PRINT CABLE STATUS LD A,(UF_USB_ACTIVE) ; PRINT CABLE STATUS
OR A OR A

2
Source/HBIOS/ver.inc

@ -2,4 +2,4 @@
#DEFINE RMN 9 #DEFINE RMN 9
#DEFINE RUP 2 #DEFINE RUP 2
#DEFINE RTP 0 #DEFINE RTP 0
#DEFINE BIOSVER "2.9.2-pre.4"
#DEFINE BIOSVER "2.9.2-pre.5"

11
Source/Images/BuildHD.ps1

@ -10,7 +10,8 @@ $Blank = ([byte[]](0xE5) * (128KB * 65))
if (!(Test-Path('Blank.tmp'))) {Set-Content -Value $Blank -Encoding byte -Path 'Blank.tmp'} if (!(Test-Path('Blank.tmp'))) {Set-Content -Value $Blank -Encoding byte -Path 'Blank.tmp'}
"Creating hard disk images..." "Creating hard disk images..."
for ($Dsk=0; $Dsk -lt 2; $Dsk++)
#for ($Dsk=0; $Dsk -lt 2; $Dsk++)
foreach ($Dsk in @("hd0","hd1","hd_cpm3"))
{ {
"Generating Hard Disk ${Dsk}..." "Generating Hard Disk ${Dsk}..."
for ($Slice=0; $Slice -lt 4; $Slice++) for ($Slice=0; $Slice -lt 4; $Slice++)
@ -19,17 +20,17 @@ for ($Dsk=0; $Dsk -lt 2; $Dsk++)
copy Blank.tmp slice${Slice}.tmp copy Blank.tmp slice${Slice}.tmp
for ($Usr=0; $Usr -lt 16; $Usr++) for ($Usr=0; $Usr -lt 16; $Usr++)
{ {
if (Test-Path ("hd${Dsk}/s${Slice}/u${Usr}/*"))
if (Test-Path ("${Dsk}/s${Slice}/u${Usr}/*"))
{ {
$Cmd = "cpmcp -f wbw_hd0 slice${Slice}.tmp hd${Dsk}/s${Slice}/u${Usr}/*.* ${Usr}:"
$Cmd = "cpmcp -f wbw_hd0 slice${Slice}.tmp ${Dsk}/s${Slice}/u${Usr}/*.* ${Usr}:"
$Cmd $Cmd
Invoke-Expression $Cmd Invoke-Expression $Cmd
} }
} }
} }
"Combining slices into final disk image hd${Dsk}..."
&$env:COMSPEC /c copy /b slice*.tmp ..\..\Binary\hd${Dsk}.img
"Combining slices into final disk image ${Dsk}..."
&$env:COMSPEC /c copy /b slice*.tmp ..\..\Binary\${Dsk}.img
Remove-Item slice*.tmp Remove-Item slice*.tmp
} }

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39
Source/Images/hd_cpm3/s0/u0/README.1ST

@ -0,0 +1,39 @@
CP/M 3
======
This archive contains an almost complete build of CP/M 3.
If you have the source distribution, the file MAKING.DOC explains how to
set up the build environment on your computer.
Differences from Digital Research CP/M 3
========================================
All the CP/M 3 patches described in the document CPM3FIX.PAT have been
applied to the source code, except those to INITDIR. Patches 1-18 (except
nos. 5 and 9) were applied.
CP/M 3 is now fully Year 2000 compliant. This affects the programs
DATE.COM, DIR.COM and SHOW.COM.
Dates can be displayed in US, UK or Year-Month-Day format. This is set by
SETDEF:
SETDEF [US]
SETDEF [UK]
SETDEF [YMD] respectively.
The CCP has a further bug fix: A command sequence such as:
C1
:C2
:C3
will now not execute the command C3 if the command C1 failed.
What's missing?
===============
INITDIR.COM - because it is written in PL/I and I can't make the
PL/I compiler at <http://cdl.uta.edu/cpm> compile it.
Apparently a more recent version of the compiler is
required.

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2
Source/Images/hd_cpm3/s1/u0/CHAPTER1.DOC

@ -0,0 +1,2 @@
Thió ió chapteò 1.


2
Source/Images/hd_cpm3/s1/u0/CHAPTER2.DOC

@ -0,0 +1,2 @@
Thió ió chapteò 2.


2
Source/Images/hd_cpm3/s1/u0/CHAPTER3.DOC

@ -0,0 +1,2 @@
Thió ió chapteò 3.


74
Source/Images/hd_cpm3/s1/u0/DIARY.DOC

@ -0,0 +1,74 @@
Trið Diary
Septembeò 10
Whaô  á wonderfuì citù Londoî is¡ We'vå beeî herå twï  dayó  anä �
havå  beeî  literallù runninç froí onå touò  tï  another®   We'rå �
prettù  exhausted¬ anä looë ferwarä tï explorinç á fe÷ sightó  oî �
ouò own.
Thió  morninç wå tooë á touò thaô begaî aô Trafalgaò Square®   Wå �
tooë  thå  undergrounä (theiò worä foò subway©  froí  ouò  hotel® �
We'vå  founä  thå  Londoî undergrounä tï bå á greaô  waù  tï  geô �
arounä  anä  lesó  costlù thaî taxis® Wå haä  á  whirlwinä  touò �
seeinç  Parliament¬  thå Toweò oæ London¬ Toweò Bridge¬  anä  thå �
changinç  oæ thå guarä aô thå palace® Mosô impressivå  werå  thå �
crowî jeweló iî thå Toweò oæ London.
Wå  havå beiî tourinç sï mucè thaô thió afternoon¬ wå decideä  tï �
dï  á  littlå  shopping®   Wå wenô tï onå  oæ  thå  worlä  famouó �
departmenô  stores® Thå enormitù oæ thå placå waó  overwhelming® �
Wå founä wå werå morå comfortablå shoppinç inthå smalleò shops® É �
boughô á wooì scaræ anä á teá set.
Hydå Parë ió walkinç distancå froí ouò hotel® Sï aô thå enä oæ á �
hectiã day¬ wå decideä á strolì througè thå parë waó jusô whaô wå �
needed®   Wå endeä uð sittinç oî á parë bencè foò abouô aî  hour® �
Thå peoplå-watchinç waó fun® Alì thå classiã Englisè  characteró �
passeä  beforå uó ­­ meî iî derbù ható anä piî  stripes¬  nannieó �
pushinç babù carriages¬ anä bobbieó amonç them.
Ouò  morninç  touò  guidå saiä nï visiô  tï  Londoî  ió  completå �
withouô  teá  aô thå Ritú Hotel® Sï froí Hydå Park wå  walkeä  á �
shorô distancå uð Picadillù anä haä á mosô memorablå testime® Iô �
waó  reallù á smalì meal¬ witè hoô disheó beinç offereä witè  thå �
usuaì farå oæ scones¬ cookies¬ anä cakes.
Afteò sufficientlù stuffinç ourselveó aô teatime¬ wå walkeä á biô �
more® Buô thå Londoî rusè houò goô tï uó sï wå decideä tï taëe iî �
á moviå ratheò thaî trù tï geô bacë tï thå hotel® Somehow¬  I'vå �
gotteî enougè energù tï writå thió entrù iî mù trið diary®   I'vå �
haä á trulù wonderfuì daù® É lovå thió city.
Septembeò 12
I'vå  goô tï catcè uð oî twï dayó oæ diarù entries® Wå  wenô  tï �
thå theateò lasô night¬ anä goô bacë tï thå hoteì toï latå tï  dï �
anù writing.
Yesterday¬  wå tooë á breaë froí organizeä tours¬ anä decideä  tï �
visiô  severaì  Londoî siteó oî ouò own® Iî thå morninç  wå  wenô  tï �
Westminsteò  Abbey® Wå boughô á guidebooë anä tooë  á  leisurelù �
touò oæ thå church®
Iî thå afternoon¬ wå visiteä thå Britisè Museum® Thå placå ió sï �
hugå  thaô iô ió impossiblå tï eveî thinë oæ coverinç iô  alì  iî �Šonå afternoon® Buô wå tooë á quicë touò anä sa÷ thå Magná Carta¬ �
thå Rosettá Stone¬ anä á hugå collectioî oæ originaì  manuscriptó �
anä  musicaì scoreó ­­ Bach¬ Handel¬ Beethoven¬  Keats¬  Shelley¬ �
Dickenó, anä manù more.
Today¬  wå lefô Londoî anä tooë á daù touò tï Stratforä-oî-Avon¬  thå �
birthplacå  oæ Williaí Shakespeare® Wå wenô bù buó witè á  largå �
grouð  buô thå touò guidå waó sï welì informeä thaô iô  waó  welì �
wortè  it® Wå covereä á loô iî onå daù anä eveî tooë timå foò  á �
leisurelù luncè aô á locaì hotel.
Stratforä-oî-Avoî   ió  á  picturesquå  littlå  towî  anä   stilì �
maintainó  itó  Elizabethaî  flavor®   Mosô  buildingó  arå   thå �
originaló  anä havå beeî verù welì preserved® Wå enjoyeä  seeinç �
alì thå siteó relateä tï Shakespeare'ó life.
Tomorro÷ ió ouò lasô daù iî London® We'lì havå tï makå thå  mosô �
oæ it!


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358
Source/Images/hd_cpm3/s1/u0/HYEXCEPT.TXT

@ -0,0 +1,358 @@
CON-TROL-LABLE
EQ-UABLE
IN-SA-TIABLE
NE-GO-TIABLE
SO-CIABLE
TURN-TABLE
UN-CON-TROLLABLE
UN-SO-CIABLE
DE-PEND-ENT
IN-DE-PEND-ENT
ANY-THING
BAL-DING
DAR-LING
DUMP-LING
ERR-ING
EVE-NING
EVERY-THING
FAR-THING
FOUND-LING
INK-LING
MAIN-SPRING
NEST-LING
OFF-SPRING
PLAY-THING
SAP-LING
SHOE-STRING
SIB-LING
SOME-THING
STAR-LING
STER-LING
UN-ERR-ING
UP-SWING
WEAK-LING
YEAR-LING
CIV-I-LIZE
CRYS-TAL-LIZE
IM-MO-BI-LIZE
ME-TA-BO-LIZE
MO-BI-LIZE
MO-NOP-O-LIZE
STA-BI-LI*ZE
TAN-TA-LIZE
UN-CIV-I-LIZED
PAL-ATE
IN-CLEM-ENT
BAR-ON-ESS
LI-ON-ESS
EU-LOGY
PED-A-GOGY
LUS-CIOUS
AT-MOS-PHERE
MET-AL
NON-METAL
PET-AL
POST-AL
RENT-AL
CAT-ION
COM-BAT-IVE
STAT-URE
BECK-ON
BES-TIAL
COM-A-TOSE
COME-BACK
CO-ME-DIAN
COMP-TROLLER
CONE-FLOWER
CO-NUN-DRUM
EQUIPPED
HANDLE-BAR
INCH-WORM
INK-BLOT
INN-KEEPER
IN-TE-RIOR
MIN-IS-TER
MIN-IS-TRY
NONE-THE-LESS
QUA-DRILLE
SOM-ER-SAULT
SU-PE-RIOR
U-NA-NIM-ITY
U-NAN-I-MOUS
UNC-TUOUS
DEBT-OR
AC-KNOW-LEDGE
DE-DUCT-I*BLE
EX-ACT-I-TUDE
IN-EX-ACT-I-TUDE
PRE-DICT-*ABLE
RE-SPECT-*ABLE
UN-PRE-DICT-ABLE
VICT-UAL
NEEDLE-WORK
IDLER
BUFF-ER
OFF-BEAT
OFF-HAND
OFF-PRINT
OFF-SHOOT
OFF-SHORE
STIFF-EN
LEFT-IST
LEFT-OVER
LIFT-OFF
SOFT-HEARTED
EGG-SHELL
EGG-PLANT
EGG-NOG
EGG-HEAD
COGNAC
FOR-EIGN-ER
VIGNETTE
HOGS-HEAD
CHILD-ISH
ELD-EST
GOLD-EN
HOLD-OUT
HOLD-OVER
HOLD-UP
SELF-ISH
BULL-ISH
CREST-FALLEN
DIS-TILL-*E*RY
FALL-OUT
LULL-ABY
ROLL-AWAY
SELL-OUT
WALL-EYE
PSALM-IST
ELSE-WHERE
FALSE-HOOD
CON-SULT-ANT
VOLT-AGE
RE-SOLV-ABLE
RE-VOLV-ER
SOLV-ABLE
UN-SOLV-ABLE
BEACH-COMBER
BOMB-ER
CLIMB-ER
PLUMB-ER
DAMP-EN
DAMP-EST
CLINCH-ER
LAUNCH-ER
LUNCH-EON
RANCH-ER
TRENCH-ANT
AN-NOUNCER
BOUNCER
FENCER
HENCE-FORTH
MINCE-MEAT
SI-LENCER
BIND-ERY
BOUND-ARY
COM-MEND-*A-*T*ORY
DE-PEND-ABLE
EX-PEND-ABLE
FIEND-ISH
LAND-OWNER
OUT-LAND-ISH
ROUND-ABOUT
SEND-OFF
STAND-OUT
UN-DER-STAND-ABLE
CHANGE-OVER
HANG-OUT
HANG-OVER
HA-RANGUE
ME-RINGUE
ORANGE-ADE
TONGUE
VENGE-ANCE
SENSE-LESS
AC-COUNT-ANT
ANT-ACID
ANT-EATER
COUNT-ESS
PER-CENT-*AGE
REP-RE-SENTATIVE
ANT-HILL
PENT-HOUSE
AC-CEPT-ABLE
AC-CEPTOR
ADAPT-ABLE
ADAPT-ER
CRYPT-ANALYSIS
IN-TER-RU*P*T-*I*BLE
AN-TIQ-UI*TY
INEQ-UITY
INIQ-UITY
LIQ-UEFY
LIQ-UID
LIQ-UI-D*A*T*E
LIQ-UI-D*A-*T*ION
LIQ-UOR
PRE-REQ-UI-SITE
REQ-UI-SI-TION
SUB-SEQUENCE
U-BIQ-UI-TOUS
AB-SORB-ENT
CARB-ON
HERBAL
IM-PERT-TURB-ABLE
ARCH-ERY
ARCH-AN-GEL
RE-SEARCH-ER
UN-SEARCH-ABLE
AC-CORD-ANCE
BOARD-ER
CHORDAL
HARD-EN
HARD-EST
HAZ-ARD-OUS
JEOP-ARD-IZE
RE-CORDER
STAND-ARD-IZE
STEW-ARD-ESS
YARD-AGE
SURF-ER
MORGUE
CURL-I-CUE
AF-FIRM-*A*T*IVE
CON-FORM-*ITY
DE-FORM-ITY
IN-FORM-A*NT
NON-CON-FORM-IST
CAV-ERN-OUS
DIS-CERN-IBLE
MOD-ERN-IZE
TURN-ABOUT
TURN-OVER
UN-GOV-ERN-ABLE
WEST-ERN-IZE
HARP-IST
SHARPEN
TORQUE
COARS-EN
IR-RE-VERS-IBLE
NURSE-MAID
NURS-ERY
RE-HEARS-AL
RE-VERS-IBLE
WORS-EN
ART-IST
CON-VERT-IBLE
COURT-YARD
FORE-SHORT-EN
HEART-ACHE
HEART-ILY
SHORT-EN
APART-HEID
COURT-HOUSE
EARTH-EN-WARE
NORTH-EAST
NORTH-ERN
PORT-HOLE
NERV-OUS
OB-SERV-A*BLE
OB-SERVER
PRE-SERV-*A*T*I*VE
SERV-ER
SERV-ICE-ABLE
PRE-SCHOOL
CON-DE-SCEND
CRE-SCENDO
DE-CRE-SCENDO
DE-SCEND-ENT
DE-SCENT
PLEB-I-SCITE
RE-SCIND
SEA-SCAPE
ASKANCE
SNAKE-SKIN
WHISK-ER
COLE-SLAW
RATTLE-SNAKE
CLASS-IFY
CLASS-ROOM
CROSS-OVER
DIS-MISS-*AL
EX-PRESS-*I*BLE
IM-PASS-ABLE
LESS-EN
PASS-ABLE
TOSS-UP
UN-CLASS-I-FIED
AR-MI-STICE
ASTIG-MA-TISM
ASTIR
ASTONISH-MENT
BLAST-OFF
BY-STAND-ER
CANDLE-STICK
CAST-AWAY
CAST-OFF
CON-TEST-ANT
CO-STAR
DE-TEST-ABLE
DI-GEST-IBLE
EAST-ERN
EX-IST-ENCE
FORE-STALL
IN-CON-TEST-ABLE
IN-DI-GES*T-*I*BLE
IN-EX-HAUST-IBLE
LIFE-STYLE
LIME-STONE
LIVE-STOCK
MILE-STONE
NON-EX-IST-ENT
PER-SIST-ENT
PHO-TO-STAT
RE-START-ED
RE-STATE-MENT
RE-STORE
SHY-STER
SIDE-STEP
SMOKE-STACK
SUG-GEST-*I*BLE
THERMO-STAT
WASTE-BAS-KET
WASTE-LAND
MAST-HEAD
POST-HU-MOUS
PRIEST-HOOD
SIDE-SWIPE
WATT-METER
BE-TWEEN
KIB-ITZER
BUZZ-ER
AL-GO-RITHM
BIB-LI-OG-RAPHY
BI-NO-MIAL
CEN-TER
COM-PUT-A*BIL-ITY
DEC-LA-RA-TION
DE-GREE
ES-TAB-LISH
GEN-ER-ATOR
HAP-HAZARD
NEG-LI-GIBLE
PE-RI-ODIC
POLY-NO-MIAL
PRE-VIOUS
PROB-ABIL-ITY
PROB-ABLE
PRO-CE-DURE
PUB-LI-CA-TION
PUB-LISH
RE-PLACE-MENT
WHEN-EVER


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Source/Images/hd_cpm3/s1/u0/PATCH.LST

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Source/Images/hd_cpm3/s1/u0/PRINT.TST

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.hePRINT.TST Features of Your Printer
.f1 WordStar
.f2 Print test
.f3 Page #
.oj on
WordStaò anä Youò Printer
WordStar‚  workó  witè á widå rangå oæ printeró anä offeró  yoõ  á �
varietù oæ prinô enhancements® Whetheò youò printeò caî producå �
thå  prinô enhancementó outlineä iî thió documenô dependó oî  itó �
capabilities®   Pleaså notå thaô noô alì printeró arå capablå  oæ �
showinç alì thå exampleó below.
Speciaì Printinç Capabilities
WordStaò supportó thå followinç speciaì printinç capabilities:
ª Boldface¬ Doublå strike
* Italics/Alternatå ribboî color
* Strikå out
* Overprinô (aó iî co^te)
* Noncontinuouó underline¬ anä
.ul on
* Continuouó underline
.ul off
* SuperScript¬ SubScript
* anä almosô anù combinatioî -­ WordStar
Characteò Width
Somå  printeró  wilì  supporô  WordStar‚  commandó  foò   variablå �
characteò widths®�
.cw 24
µ characteró peò inch® (.C× 24)
.cw 20
¶ characteró peò inch® (.C× 20)
.cw 14
8.¶ characteró peò inch® (.C× 14)
.cw 12
1° characteró peò inch® (.C× 12)
.cw 10
1² characteró peò inch® (.C× 10)
.cw 7
17.± characteró peò inch® (.C× 7)
.cw 12
Youò printeò caî alsï bå seô tï "toggle¢ betweeî normaì pitcè anä �
alternatå pitch:
     Thió  sentencå ió printeä witè thå normaì 1°-pitcè  setting¬ �
     theî toggleä tï 1² pitch¬ theî bacë tï normal.
.cw 7

Yoõ caî alsï changå thå normaì anä alternatå characteò widths:
.cw 14
.rm 55
     Thå  "normal¢ characteò widtè ió 1´ (8.¶ cpi©  anä �
     thå alternatå characteò widtè ió · (17.± cpi).
.pa Š.rm 65
.cw 10

.cw 12
Linå Height
Yoõ caî alsï uså differenô linå heights.
.lh 16
Thió ió aî examplå oæ variablå linå height® (.LÈ 1¶ ­ ³ lpi)
.lh 12
Thió ió aî examplå oæ variablå linå height® (.LÈ 1² ­ ´ lpi)
.lh 8
Thió ió aî examplå oæ variablå linå height® (.LÈ ¸ ­ ¶ lpi)
.lh 6
Thió ió aî examplå oæ variablå linå heighô® (.LÈ ¶ ­ ¸ lpi)
.lh 8
Proportionaì Printing
.ps on
.uj on
WordStar‚  alsï supportó proportionaì printinç foò  mosô  printeró �
thaô  havå  it®   Yoõ  selecô  proportionaì  fontó  bù   changinç �
characteò widthó aó iî thå followinç examples:�
.cw 22
Thió ió characteò widtè 22.
.cw 11
Thió ió characteò widtè 11.
.cw 9
Thió ió characteò widtè 9.
.cw 7
Thió ió characteò widtè 7.
.uj dis
.ps off
.cw 12
Other
Phantoí Spacå¬ Phantoí Rubout
WordStaò maù allo÷ yoõ tï prinô speciaì characteró (foò  example¬ �
á  paragrapè  sigî  oò centó sign© bù  usinç  thå  phantoí  spacå �
commanä (^PF© oò thå phantoí rubouô commanä (^PG© iî á  document® �
Foò  youò  printer¬ thå phantoí spacå characteò isº  ¬  anä  thå �
phantoí rubouô characteò isº .
Switchinç tï Drafô Mode
.lq off
Doô matriø printeò driveró allo÷ switchinç froí NLÑ (neaò  letteò �
quality© modå tï drafô modå foò fasteò printing.
.lq on
Microspacå Justification
.uj on
WordStar‚   allowó  microspacå  justification¬  iæ  youò   printeò �
supportó  it¬ tï producå evenlù spaceä wordó iî  justifieä  text® �
Microspacinç spreadó thå whitå spacå betweeî wordó (anä sometimeó �
betweeî thå letteró oæ eacè word© aó evenlù aó possible®
.uj dis
.pa ŠLookinç Aô Thió Filå Onscreen
Iæ  yoõ wanô tï seå thå embeddeä commandó thaô produceä thå  texô �
yoõ arå no÷ reading¬ follo÷ theså steps:
1 Aô thå Openinç Menu¬ presó D‚ tï ediô á document.
² Aô thå prompô foò filename¬ typå print.tsô anä presó Enter.
Noticå thaô thå texô onscreeî includeó somå characteró thaô don'ô �
appeaò  iî  thå  printeä copy® Foò example¬ á  headinç  linå  ió �
identifieä  bù  thå  doô  commanä .he®   Wordó  iî  boldfacå  arå �
surroundeä bù ^Â anä appeaò eitheò highlighteä oò iî á  differenô �
coloò oî youò screen.
Tï continuå viewinç thå contentó oæ thió file¬ ¬ presó ^C® Presó �
^R‚ tï movå iî thå otheò direction.


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Source/Images/hd_cpm3/s1/u0/READ.ME

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Source/Images/hd_cpm3/s1/u0/README

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This disk contains an updated printer driver file for your
WordStar, CP/M Edition, Release 4. This file corrects problems
you may have experienced with form feeds, page length, and right-
justified proportional spacing.
Follow the instructions on page xxii of the WordStar Reference
Guide for creating a new WSPRINT.OVR file. Substitute a copy of
this WSPRINT disk (make sure it is a boot disk) for the copy of
your original PRINT disk in step 2.


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Thå Ruleò Line
Thió  documenô  ió seô uð tï teacè yoõ abouô ruleò  lines®   Thió �
texô  waó writteî usinç thå defaulô lefô anä righô marginó  oæ  ± �
anä  65®   Wå didn'ô changå anù tabó here® Next¬  wå  wanteä  tï �
changå  botè  marginó  tï  indenô thå texô®  Wå  useä  doô �
commands® Witè doô commands¬ thå ne÷ marginó arå saveä wheî  yoõ �
exiô anä savå thå document.�
.lm10
.rm45
         Ne÷  marginó  changå thå  ruleò  anä �
         text®   Watcè thå ruleò linå aó  yoõ �
         movå  thå cursoò througè thió  text® �
         WordStaò wilì continuå tï holä theså �
         marginó untiì yoõ enteò anotheò  doô �
         ãommand.
.lm1
.rm65
Margiî  changeó brinç thå ruleò anä thå texô bacë tï thå  defaulô �
settingó oncå again.


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Source/Images/hd_cpm3/s1/u0/SAMPLE1.DOC

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Itinerary
Depart Datå Time Arrive Date Time
Florence 10¯3± 08:30 a Rome 10¯31 05:3µ p
Romå 11¯05 08:00 a Naples 11/05 12:2· p
Noô includeä iî thå rateó are
.lm10
.rm55
         Transfeò  services¬ sightseeing¬ mealó  excepô �
         aó specified¬ tipó tï statioî porters¬  wines¬ �
         spirits¬   mineraì waters¬  laundry¬   theateò �
         tickets¬ anä otheò itemó oæ á similaò personaì �
         nature®


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Source/Images/hd_cpm3/s1/u0/SAMPLE2.DOC

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Excursions
Daù ±
Florencå-Romeº Leavå aô 8:3° aí bù deluxå motorcoach® Arrivå aô �
Romå iî thå afternoon®
Daù ²
Romeº   Morninç  anä afternooî citù  sightseeinç  bù  motorcoach® �
Englisè speakinç guidå optional.
Farå iî firsô clasó hotelsº $100.00® Batè optionaìº $25.00®


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Daù 8
Romå-Naplesº   Deparô  aô 8:0° aí bù CIAÔ deluxå  motorcoacè  viá �
Formia®   Arrivå  Napleó  aô  luncè  time®   Afternooî   optionaì �
excursioî tï Phlegreaî Fieldó anä Sulphuò Mine®


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