Support DS1501 RTC

jpelletier provided a DS1501 RTC driver.  This commit integrates the driver into HBIOS.

.github/workflows/commit.yml

@@ -24,7 +24,6 @@ jobs:
           sudo apt-get install libncurses-dev
           sudo apt-get install srecord
           make dist
-          make clean
           rm -rf .git*
 
       - name: List Output
@@ -64,7 +63,6 @@ jobs:
           export TZ='America/Los_Angeles'
           brew install srecord
           make dist
-          make clean
           rm -rf .git*
 
       - name: List Output

.github/workflows/release.yml

@@ -27,7 +27,6 @@ jobs:
         run: |
           sudo apt-get install libncurses-dev
           make dist
-          make clean
           rm -rf .git*
       
       - name: Upload Artifact

.gitignore

@@ -96,7 +96,7 @@ Tools/unix/zx/zx
 !Source/ZRC/*.bin
 !Source/ZZR/*.bin
 !Source/ZZR/*.hex
-!Tools/cpm/bin/*
+!Tools/cpm/**
 !Tools/unix/zx/*
 !Tools/zx/*
 

Binary/Apps/Makefile

@@ -7,5 +7,5 @@ include $(TOOLS)/Makefile.inc
 all::
 	mkdir -p Tunes
 
-clobber::
+clean::
 	@rm -f *.bin *.com *.img *.rom *.pdf *.log *.eeprom *.ovr *.hlp *.doc *.COM *.BIN Tunes/*.mym Tunes/*.pt? Tunes/*.vgm

Binary/Apps/Test/Makefile

@@ -3,5 +3,5 @@ MOREDIFF := $(shell $(TOOLS)/unix/casefn.sh *.com)
 
 include $(TOOLS)/Makefile.inc
 
-clobber::
+clean::
 	@rm -f *.com

Binary/CPM3/Makefile

@@ -3,5 +3,5 @@ MOREDIFF := $(shell $(TOOLS)/unix/casefn.sh *.spr)
 
 include $(TOOLS)/Makefile.inc
 
-clobber::
-	@rm -f *.spr
+clean::
+	@rm -f *.spr *.com *.sys *.dat cpm3fix.pat readme.1st

Binary/Makefile

@@ -4,5 +4,5 @@ SUBDIRS = Apps CPM3 ZPM3
 
 include $(TOOLS)/Makefile.inc
 
-clobber::
-	@rm -f *.bin *.com *.img *.rom *.upd *.hex *.pdf *.log *.eeprom *.dat
+clean::
+	@rm -f *.bin *.com *.img *.rom *.upd *.hex *.pdf *.log *.eeprom *.dat

Binary/ZPM3/Makefile

@@ -3,5 +3,5 @@ MOREDIFF := $(shell $(TOOLS)/unix/casefn.sh *.spr)
 
 include $(TOOLS)/Makefile.inc
 
-clobber::
-	@rm -f *.spr
+clean::
+	@rm -f *.spr *.com *.sys *.dat *.zpm

Build.cmd

@@ -3,4 +3,4 @@ setlocal
 
 pushd Source && call Build %* || exit /b & popd
 
-pause
+if "%*" == "" pause

CODE_OF_CONDUCT.md

@@ -0,0 +1,128 @@
+# Contributor Covenant Code of Conduct
+
+## Our Pledge
+
+We as members, contributors, and leaders pledge to make participation in our
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+nationality, personal appearance, race, religion, or sexual identity
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+
+We pledge to act and interact in ways that contribute to an open, welcoming,
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+
+## Our Standards
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+
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+Community leaders are responsible for clarifying and enforcing our standards of
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+Community leaders have the right and responsibility to remove, edit, or reject
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+## Scope
+
+This Code of Conduct applies within all community spaces, and also applies when
+an individual is officially representing the community in public spaces.
+Examples of representing our community include using an official e-mail address,
+posting via an official social media account, or acting as an appointed
+representative at an online or offline event.
+
+## Enforcement
+
+Instances of abusive, harassing, or otherwise unacceptable behavior may be
+reported to the community leaders responsible for enforcement at
+wwarthen@gmail.com.
+All complaints will be reviewed and investigated promptly and fairly.
+
+All community leaders are obligated to respect the privacy and security of the
+reporter of any incident.
+
+## Enforcement Guidelines
+
+Community leaders will follow these Community Impact Guidelines in determining
+the consequences for any action they deem in violation of this Code of Conduct:
+
+### 1. Correction
+
+**Community Impact**: Use of inappropriate language or other behavior deemed
+unprofessional or unwelcome in the community.
+
+**Consequence**: A private, written warning from community leaders, providing
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+
+### 2. Warning
+
+**Community Impact**: A violation through a single incident or series
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+like social media. Violating these terms may lead to a temporary or
+permanent ban.
+
+### 3. Temporary Ban
+
+**Community Impact**: A serious violation of community standards, including
+sustained inappropriate behavior.
+
+**Consequence**: A temporary ban from any sort of interaction or public
+communication with the community for a specified period of time. No public or
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+
+### 4. Permanent Ban
+
+**Community Impact**: Demonstrating a pattern of violation of community
+standards, including sustained inappropriate behavior,  harassment of an
+individual, or aggression toward or disparagement of classes of individuals.
+
+**Consequence**: A permanent ban from any sort of public interaction within
+the community.
+
+## Attribution
+
+This Code of Conduct is adapted from the [Contributor Covenant][homepage],
+version 2.0, available at
+https://www.contributor-covenant.org/version/2/0/code_of_conduct.html.
+
+Community Impact Guidelines were inspired by [Mozilla's code of conduct
+enforcement ladder](https://github.com/mozilla/diversity).
+
+[homepage]: https://www.contributor-covenant.org
+
+For answers to common questions about this code of conduct, see the FAQ at
+https://www.contributor-covenant.org/faq. Translations are available at
+https://www.contributor-covenant.org/translations.

Doc/ChangeLog.txt

@@ -62,6 +62,8 @@ Version 3.1.1
 - WBW: ZPMLDR and ZPM3 fixes, credit to Lars Nelson for finding ZPM3 source!
 - DDW: Add support for MBC sound card
 - WBW: Add support for "romless" booting
+- L?N: Fixes for ZCPR-D&J (buffer overflow, default drive/user)
+- J?P: Add support for DS1501 RTC
 
 Version 3.1
 -----------

LICENSE

@@ -0,0 +1,661 @@
+                    GNU AFFERO GENERAL PUBLIC LICENSE
+                       Version 3, 19 November 2007
+
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+
+  Each time you convey a covered work, the recipient automatically
+receives a license from the original licensors, to run, modify and
+propagate that work, subject to this License.  You are not responsible
+for enforcing compliance by third parties with this License.
+
+  An "entity transaction" is a transaction transferring control of an
+organization, or substantially all assets of one, or subdividing an
+organization, or merging organizations.  If propagation of a covered
+work results from an entity transaction, each party to that
+transaction who receives a copy of the work also receives whatever
+licenses to the work the party's predecessor in interest had or could
+give under the previous paragraph, plus a right to possession of the
+Corresponding Source of the work from the predecessor in interest, if
+the predecessor has it or can get it with reasonable efforts.
+
+  You may not impose any further restrictions on the exercise of the
+rights granted or affirmed under this License.  For example, you may
+not impose a license fee, royalty, or other charge for exercise of
+rights granted under this License, and you may not initiate litigation
+(including a cross-claim or counterclaim in a lawsuit) alleging that
+any patent claim is infringed by making, using, selling, offering for
+sale, or importing the Program or any portion of it.
+
+  11. Patents.
+
+  A "contributor" is a copyright holder who authorizes use under this
+License of the Program or a work on which the Program is based.  The
+work thus licensed is called the contributor's "contributor version".
+
+  A contributor's "essential patent claims" are all patent claims
+owned or controlled by the contributor, whether already acquired or
+hereafter acquired, that would be infringed by some manner, permitted
+by this License, of making, using, or selling its contributor version,
+but do not include claims that would be infringed only as a
+consequence of further modification of the contributor version.  For
+purposes of this definition, "control" includes the right to grant
+patent sublicenses in a manner consistent with the requirements of
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+
+  Each contributor grants you a non-exclusive, worldwide, royalty-free
+patent license under the contributor's essential patent claims, to
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+propagate the contents of its contributor version.
+
+  In the following three paragraphs, a "patent license" is any express
+agreement or commitment, however denominated, not to enforce a patent
+(such as an express permission to practice a patent or covenant not to
+sue for patent infringement).  To "grant" such a patent license to a
+party means to make such an agreement or commitment not to enforce a
+patent against the party.
+
+  If you convey a covered work, knowingly relying on a patent license,
+and the Corresponding Source of the work is not available for anyone
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+publicly available network server or other readily accessible means,
+then you must either (1) cause the Corresponding Source to be so
+available, or (2) arrange to deprive yourself of the benefit of the
+patent license for this particular work, or (3) arrange, in a manner
+consistent with the requirements of this License, to extend the patent
+license to downstream recipients.  "Knowingly relying" means you have
+actual knowledge that, but for the patent license, your conveying the
+covered work in a country, or your recipient's use of the covered work
+in a country, would infringe one or more identifiable patents in that
+country that you have reason to believe are valid.
+
+  If, pursuant to or in connection with a single transaction or
+arrangement, you convey, or propagate by procuring conveyance of, a
+covered work, and grant a patent license to some of the parties
+receiving the covered work authorizing them to use, propagate, modify
+or convey a specific copy of the covered work, then the patent license
+you grant is automatically extended to all recipients of the covered
+work and works based on it.
+
+  A patent license is "discriminatory" if it does not include within
+the scope of its coverage, prohibits the exercise of, or is
+conditioned on the non-exercise of one or more of the rights that are
+specifically granted under this License.  You may not convey a covered
+work if you are a party to an arrangement with a third party that is
+in the business of distributing software, under which you make payment
+to the third party based on the extent of your activity of conveying
+the work, and under which the third party grants, to any of the
+parties who would receive the covered work from you, a discriminatory
+patent license (a) in connection with copies of the covered work
+conveyed by you (or copies made from those copies), or (b) primarily
+for and in connection with specific products or compilations that
+contain the covered work, unless you entered into that arrangement,
+or that patent license was granted, prior to 28 March 2007.
+
+  Nothing in this License shall be construed as excluding or limiting
+any implied license or other defenses to infringement that may
+otherwise be available to you under applicable patent law.
+
+  12. No Surrender of Others' Freedom.
+
+  If conditions are imposed on you (whether by court order, agreement or
+otherwise) that contradict the conditions of this License, they do not
+excuse you from the conditions of this License.  If you cannot convey a
+covered work so as to satisfy simultaneously your obligations under this
+License and any other pertinent obligations, then as a consequence you may
+not convey it at all.  For example, if you agree to terms that obligate you
+to collect a royalty for further conveying from those to whom you convey
+the Program, the only way you could satisfy both those terms and this
+License would be to refrain entirely from conveying the Program.
+
+  13. Remote Network Interaction; Use with the GNU General Public License.
+
+  Notwithstanding any other provision of this License, if you modify the
+Program, your modified version must prominently offer all users
+interacting with it remotely through a computer network (if your version
+supports such interaction) an opportunity to receive the Corresponding
+Source of your version by providing access to the Corresponding Source
+from a network server at no charge, through some standard or customary
+means of facilitating copying of software.  This Corresponding Source
+shall include the Corresponding Source for any work covered by version 3
+of the GNU General Public License that is incorporated pursuant to the
+following paragraph.
+
+  Notwithstanding any other provision of this License, you have
+permission to link or combine any covered work with a work licensed
+under version 3 of the GNU General Public License into a single
+combined work, and to convey the resulting work.  The terms of this
+License will continue to apply to the part which is the covered work,
+but the work with which it is combined will remain governed by version
+3 of the GNU General Public License.
+
+  14. Revised Versions of this License.
+
+  The Free Software Foundation may publish revised and/or new versions of
+the GNU Affero General Public License from time to time.  Such new versions
+will be similar in spirit to the present version, but may differ in detail to
+address new problems or concerns.
+
+  Each version is given a distinguishing version number.  If the
+Program specifies that a certain numbered version of the GNU Affero General
+Public License "or any later version" applies to it, you have the
+option of following the terms and conditions either of that numbered
+version or of any later version published by the Free Software
+Foundation.  If the Program does not specify a version number of the
+GNU Affero General Public License, you may choose any version ever published
+by the Free Software Foundation.
+
+  If the Program specifies that a proxy can decide which future
+versions of the GNU Affero General Public License can be used, that proxy's
+public statement of acceptance of a version permanently authorizes you
+to choose that version for the Program.
+
+  Later license versions may give you additional or different
+permissions.  However, no additional obligations are imposed on any
+author or copyright holder as a result of your choosing to follow a
+later version.
+
+  15. Disclaimer of Warranty.
+
+  THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
+APPLICABLE LAW.  EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
+HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY
+OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,
+THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+PURPOSE.  THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM
+IS WITH YOU.  SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
+ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
+
+  16. Limitation of Liability.
+
+  IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
+WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
+THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
+GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
+USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
+DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
+PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
+EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
+SUCH DAMAGES.
+
+  17. Interpretation of Sections 15 and 16.
+
+  If the disclaimer of warranty and limitation of liability provided
+above cannot be given local legal effect according to their terms,
+reviewing courts shall apply local law that most closely approximates
+an absolute waiver of all civil liability in connection with the
+Program, unless a warranty or assumption of liability accompanies a
+copy of the Program in return for a fee.
+
+                     END OF TERMS AND CONDITIONS
+
+            How to Apply These Terms to Your New Programs
+
+  If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
+  To do so, attach the following notices to the program.  It is safest
+to attach them to the start of each source file to most effectively
+state the exclusion of warranty; and each file should have at least
+the "copyright" line and a pointer to where the full notice is found.
+
+    <one line to give the program's name and a brief idea of what it does.>
+    Copyright (C) <year>  <name of author>
+
+    This program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU Affero General Public License as published
+    by the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU Affero General Public License for more details.
+
+    You should have received a copy of the GNU Affero General Public License
+    along with this program.  If not, see <https://www.gnu.org/licenses/>.
+
+Also add information on how to contact you by electronic and paper mail.
+
+  If your software can interact with users remotely through a computer
+network, you should also make sure that it provides a way for users to
+get its source.  For example, if your program is a web application, its
+interface could display a "Source" link that leads users to an archive
+of the code.  There are many ways you could offer source, and different
+solutions will be better for different programs; see section 13 for the
+specific requirements.
+
+  You should also get your employer (if you work as a programmer) or school,
+if any, to sign a "copyright disclaimer" for the program, if necessary.
+For more information on this, and how to apply and follow the GNU AGPL, see
+<https://www.gnu.org/licenses/>.

Makefile

@@ -1,20 +1,19 @@
 all:
-	$(MAKE) --directory Tools/unix
+	$(MAKE) --directory Tools
 	$(MAKE) --directory Source
 
 clean:
-	$(MAKE) --directory Tools/unix clean
+	$(MAKE) --directory Tools clean
 	$(MAKE) --directory Source clean
 	$(MAKE) --directory Binary clean
+	rm -f make.log
 
-clobber:
-	$(MAKE) --directory Tools/unix clobber
-	$(MAKE) --directory Source  clobber
-	$(MAKE) --directory Binary clobber
-	rm -f typescript
+clobber: clean
 
 diff:
 	$(MAKE) --directory Source diff
 
 dist:
-	$(MAKE) ROM_PLATFORM=dist
+	$(MAKE) ROM_PLATFORM=dist 2>&1 | tee make.log
+	$(MAKE) --directory Source clean
+	$(MAKE) --directory Tools clean

ReadMe.md

@@ -3,7 +3,7 @@
 ## Z80/Z180 System Software
 
 Version 3.1 Pre-release  
-21 Mar 2022
+09 Jul 2022
 
 Wayne Warthen <wwarthen@gmail.com>
 
@@ -418,7 +418,7 @@ therefore, globally available.
 
 Some custom applications do not fit on the ROM disk. They are found on
 the disk image files or the individual files can be found in the
-Binary\\Apps directory of the distribution.
+Binary\Apps directory of the distribution.
 
 | Application | Description                                                 |
 |-------------|-------------------------------------------------------------|
@@ -924,7 +924,7 @@ documents.
 Note that the build scripts for RomWBW create the default disk images
 supplied with RomWBW. It is relatively easy to customize the contents of
 the disk images that are part of RomWBW. This is described in more
-detail in the Source\\Images directory of the distribution.
+detail in the Source\Images directory of the distribution.
 
 ## FAT Filesystem Transfers
 
@@ -945,7 +945,7 @@ however. Longer filenames will show up as a truncated version.
 
 The `FAT` application is not on your ROM disk because it is too large to
 fit. You will find it on all of the pre-built disk images as well as in
-the Binary\\Apps directory of the distribution.
+the Binary\Apps directory of the distribution.
 
 For advanced users, it is possible to create a hybrid disk that contains
 CP/M slices at the beginning and a FAT filesystem after. Such a hybrid
@@ -953,7 +953,7 @@ disk can be used to boot an operating system and still have access to
 FAT files on the FAT portion of the disk. David Reese has prepared a
 document describing how to do this. It is called
 “SC126_How-To_No_2\_Preparing_an_SD_Card_for_Use_with_SC126_Rev_1-5.pdf”
-and can be found in the Doc\\Contrib directory of the distribution.
+and can be found in the Doc\Contrib directory of the distribution.
 
 # Startup Command Processing
 
@@ -1164,7 +1164,7 @@ system on your disk.
     CP/M 3 uses a multi-step boot process involving multiple files. The
     CP/M 3 boot files are not included on the ROM disk due to space
     constraints. You will need to transfer the files to your system from
-    the RomWBW distribution directory Binary\\CPM3.
+    the RomWBW distribution directory Binary\CPM3.
 
     After this is done, you will need to use `SYSCOPY` to place the CP/M
     3 loader image on the boot tracks of all CP/M 3 boot disks/slices.
@@ -1182,7 +1182,7 @@ system on your disk.
     ZPM3 uses a multi-step boot process involving multiple files. The
     ZPM3 boot files are not included on the ROM disk due to space
     constraints. You will need to transfer the files to your system from
-    the RomWBW distribution directory Binary\\ZPM3.
+    the RomWBW distribution directory Binary\ZPM3.
 
     After this is done, you will need to use `SYSCOPY` to place the ZPM3
     loader image on the boot tracks of all ZPM3 boot disks/slices. The
@@ -1225,8 +1225,7 @@ For example: `B>COPY ASSIGN.COM C:`
 Some RomWBW custom applications are too large to fit on the ROM disk. If
 you are using any of these you will need to transfer them to your system
 and then update all copies. These applications are found in the
-Binary\\Apps directory of the distribution and in all of the disk
-images.
+Binary\Apps directory of the distribution and in all of the disk images.
 
 -   FAT.COM
 -   TUNE.COM

ReadMe.txt

@@ -1,6 +1,6 @@
 RomWBW Getting Started
 Wayne Warthen (mailto:wwarthen@gmail.com)
-21 Mar 2022
+09 Jul 2022
 
 
 
@@ -17,7 +17,7 @@ RomWBW
 Z80/Z180 System Software
 
 Version 3.1 Pre-release
-21 Mar 2022
+09 Jul 2022
 
 Wayne Warthen wwarthen@gmail.com
 
@@ -213,15 +213,23 @@ disk devices.
 
 The following ROM applications are available at the boot loader prompt:
 
-  Application    
-  -------------- --------------------------------------------------------
-  Monitor        Z80 system debug monitor w/ Intel Hex loader
-  Forth          Brad Rodriguez’s ANSI compatible Forth language
-  Basic          Nascom 8K BASIC language
-  Tasty BASIC    Dimitri Theuling’s Tiny BASIC implementation
-  Play           A simple video game (requires ANSI terminal emulation)
-  Network Boot   Boot through Wiznet MT011 device
-  Flash Update   Upload and flash a new ROMWBW image using xmodem
+  --------------------------------------------------------------------------
+  Application   
+  ------------- ------------------------------------------------------------
+  Monitor       Z80 system debug monitor w/ Intel Hex loader
+
+  Forth         Brad Rodriguez’s ANSI compatible Forth language
+
+  Basic         Nascom 8K BASIC language
+
+  Tasty BASIC   Dimitri Theuling’s Tiny BASIC implementation
+
+  Play          A simple video game (requires ANSI terminal emulation)
+
+  Network Boot  Boot through Wiznet MT011 device
+
+  Flash Update  Upload and flash a new ROMWBW image using xmodem
+  --------------------------------------------------------------------------
 
 In general, the command to exit these applications and restart the
 system is BYE. The exceptions are the Monitor which uses B and Play
@@ -467,11 +475,15 @@ Some custom applications do not fit on the ROM disk. They are found on
 the disk image files or the individual files can be found in the
 Binary\Apps directory of the distribution.
 
+  --------------------------------------------------------------------------
   Application   Description
-  ------------- -------------------------------------------------------------
+  ------------- ------------------------------------------------------------
   TUNE          Play .PT2, .PT3, .MYM audio files.
+
   FAT           Access MS-DOS FAT filesystems from RomWBW (based on FatFs).
+
   INTTEST       Test interrupt vector hooking.
+  --------------------------------------------------------------------------
 
 Additional documentation on all of these applications can be found in
 “RomWBW Applications.pdf” in the Doc directory of the distribution.
@@ -667,14 +679,21 @@ The following table shows the disk image files available. Note that the
 images in the “Hard” column are fine for use on CF Cards, SD Cards, as
 well as real spinning hard disks.
 
-  Floppy         Hard           Description
-  -------------- -------------- ------------------------------
-  fd_cpm22.img   hd_cpm22.img   DRI CP/M 2.2 boot disk
-  fd_zsdos.img   hd_zsdos.img   ZSDOS 1.1 boot disk
-  fd_nzcom.img   hd_nzcom.img   NZCOM boot disk
-  fd_cpm3.img    hd_cpm3.img    DRI CP/M 3 boot disk
-  fd_zpm3.img    hd_zpm3.img    ZPM3 boot disk
-  fd_ws4.img     hd_ws4.img     WordStar v4 application disk
+  -----------------------------------------------------------------------
+  Floppy          Hard            Description
+  --------------- --------------- ---------------------------------------
+  fd_cpm22.img    hd_cpm22.img    DRI CP/M 2.2 boot disk
+
+  fd_zsdos.img    hd_zsdos.img    ZSDOS 1.1 boot disk
+
+  fd_nzcom.img    hd_nzcom.img    NZCOM boot disk
+
+  fd_cpm3.img     hd_cpm3.img     DRI CP/M 3 boot disk
+
+  fd_zpm3.img     hd_zpm3.img     ZPM3 boot disk
+
+  fd_ws4.img      hd_ws4.img      WordStar v4 application disk
+  -----------------------------------------------------------------------
 
 In addition to the disk images above, there is also a special hard disk
 image called hd_combo.img. This image contains all of the images above,
@@ -685,14 +704,21 @@ system options.
 
 This is the layout of the hd_combo disk image:
 
-  Slice     Description
-  --------- ------------------------------
-  Slice 0   DRI CP/M 2.2 boot disk
-  Slice 1   ZSDOS 1.1 boot disk
-  Slice 2   NZCOM boot disk
-  Slice 3   DRI CP/M 3 boot disk
-  Slice 4   ZPM3 boot disk
-  Slice 5   WordStar v4 application disk
+  ------------------------------------------------------------------------
+  Slice   Description
+  ------- ----------------------------------------------------------------
+  Slice 0 DRI CP/M 2.2 boot disk
+
+  Slice 1 ZSDOS 1.1 boot disk
+
+  Slice 2 NZCOM boot disk
+
+  Slice 3 DRI CP/M 3 boot disk
+
+  Slice 4 ZPM3 boot disk
+
+  Slice 5 WordStar v4 application disk
+  ------------------------------------------------------------------------
 
 Note that unlike the ROM firmware, you do not need to choose a disk
 image specific to your hardware. Because the RomWBW firmware provides a

Readme.unix

@@ -34,22 +34,19 @@ By default, this will generate all of the standard configurations of
 RomWBW for all platforms.  If you just want to build the ROM for a
 specific platform and configuration you can use
 
-	make ROM_PLATFORM=<platform> ROM_CONFIG=<config> [ROMSIZE=<size>]
+	make ROM_PLATFORM=<platform> ROM_CONFIG=<config>
 
 where <platform> is one of the supported platforms such as SBC, RCZ80, 
-etc. and <config> is a configuration of that platform.  A ROM size may
-optionally be specified and must be one of 128, 256, 512, or 1024.  It
-defaults to 512.  For example, to build the "126" configuration of
-the "SCZ180" platform:
+etc. and <config> is a configuration of that platform.  For example,
+to build the "126" configuration of the "SCZ180" platform:
 
 	make ROM_PLATFORM=SCZ180 ROM_CONFIG=126
 
 Please be aware that the make-based build does have a few deficiencies.
 
 First and most important, the Makefiles do not handle reruns very well.
-To ensure a full buld, use "make clobber" from the top level directory
-before running the actual build.  For those used to using "make clean",
-you can do that but it is not as thorough as "make clobber".
+To ensure a full buld, use "make clean" from the top level directory
+before running the actual build.
 
 Second, there are some build failures that will not stop the make 
 process.  Most of this is because real CP/M 2.2 tools are used in 
@@ -57,7 +54,7 @@ places and CP/M 2.2 does not allow programs to return a result code.
 
 Third, not all dependencies are properly handled.  So, changes to some
 files will not cause things to rebuild as appropriate.  In general, I
-recommend doing a "make clobber" before running "make" to ensure that
+recommend doing a "make clean" before running "make" to ensure that
 everything is fully rebuilt.
 
 For macOS users, you may encounter a failure reading or writing files.
@@ -78,7 +75,7 @@ running.  To disable this feature:
 DISCLAIMER: You do this at your own risk.  I highly recommend that you
 return the settings back to normal immediately after doing a build.
 
-Heavy use is made of make's include facility and pattern rules. the 
+Heavy use is made of make's include facility and pattern rules. The 
 master rule set is in Tools/Makefile.inc.  Changes here will affect 
 almost every Makefile, and where exceptions are needed, the overrides 
 are applied in the lower Makefiles.
@@ -102,10 +99,10 @@ Credit:
 	hacked to do case-insensitivity. These are not marked, and are 
 	not extensive.
 
-	zx is from the distributed version, and also has local hacks 
+	zxcc is from the distributed version, and also has local hacks 
 	for case insensitivity.
 
-	Both zx and cpmtools ship with an overly complicated makefile 
+	Both zxcc and cpmtools ship with an overly complicated makefile 
 	generation system and this is ignored.
 
 	This whole Linux build framework is the work of Curt Mayer, 

Source/Apps/Test/ps2info/ps2info.asm

@@ -6,12 +6,21 @@
 ; Simple utility that performs simple tests of an 8242 PS/2 controller,
 ; keyboard, and mouse.
 ;
+; WBW 2022-03-28: Add menu driven port selection
+;                 Add support for RHYOPHYRE
+; WBW 2022-04-01: Add menu for test functions
+; WBW 2022-04-02: Fix prtchr register saving/recovery
+;
 ;=======================================================================
 ;
 ; PS/2 Keyboard/Mouse controller port addresses (adjust as needed)
 ;
-iocmd	.equ	$E3	; PS/2 controller command port address
-iodat	.equ	$E2	; PS/2 controller data port address
+; MBC:
+iocmd_mbc	.equ	$E3	; PS/2 controller command port address
+iodat_mbc	.equ	$E2	; PS/2 controller data port address
+; RPH:
+iocmd_rph	.equ	$8D	; PS/2 controller command port address
+iodat_rph	.equ	$8C	; PS/2 controller data port address
 ;
 cpumhz	.equ	8	; for time delay calculations (not critical)
 ;
@@ -37,6 +46,8 @@ bdos	.equ	$0005			; BDOS invocation vector
 	call	crlf
 	ld	de,str_banner		; banner
 	call	prtstr
+;
+	call	setup
 ;
 	call	main			; do the real work
 ;
@@ -50,52 +61,95 @@ exit:
 	ld	sp,(stksav)		; restore stack
 	jp	restart			; return to CP/M via restart
 ;
+;=======================================================================
+; Select and setup for hardware
+;=======================================================================
+;
+setup:
+	call	crlf2
+	ld	de,str_hwmenu
+	call	prtstr
+setup1:
+	ld	c,$06			; BDOS direct console I/O
+	ld	e,$FF			; Subfunction = read
+	call	bdos
+	cp	0
+	jr	z,setup1
+	call	upcase
+	call	prtchr
+	cp	'1'			; MBC
+	jr	z,setup_mbc
+	cp	'2'			; RHYOPHYRE
+	jr	z,setup_rph
+	cp	'X'
+	jr	z,exit
+	jr	setup
+;
+setup_mbc:
+	ld	a,iocmd_mbc
+	ld	(iocmd),a
+	ld	a,iodat_mbc
+	ld	(iodat),a
+	ld	de,str_mbc
+	jr	setup2
+;
+setup_rph:
+	ld	a,iocmd_rph
+	ld	(iocmd),a
+	ld	a,iodat_rph
+	ld	(iodat),a
+	ld	de,str_rph
+	jr	setup2
+;
+setup2:
+	call	prtstr
+	call	crlf2
+	ld	de,str_cmdport
+	call	prtstr
+	;ld	a,iocmd
+	ld	a,(iocmd)
+	call	prthex
+	call	crlf
+	ld	de,str_dataport
+	call	prtstr
+	;ld	a,iodat
+	ld	a,(iodat)
+	call	prthex
+;
+	xor	a
+	ret
 ;
 ;=======================================================================
 ; Main Program
 ;=======================================================================
 ;
 main:
-;
-; Display active controller port addresses
-;
 	call	crlf2
-	ld	de,str_cmdport
+	ld	de,str_menu
 	call	prtstr
-	ld	a,iocmd
-	call	prthex
-	call	crlf
-	ld	de,str_dataport
-	call	prtstr
-	ld	a,iodat
-	call	prthex
-;
-	call	test_ctlr
-	jr	z,main0			; continue if ctlr OK
-	ld	de,str_kbd_failed
-	call	crlf2
-	call	prtstr
-	jr	mainz			; bail out if ctlr fails
-;
-main0:
-	call	test_kbd
-	jr	z,main1			; completed all tests, continue
-	ld	de,str_kbd_failed
-	call	crlf2
-	call	prtstr
-;
 main1:
-	call	test_mse
-	jr	z,main2			; completed all tests, continue
-	ld	de,str_mse_failed
-	call	crlf2
-	call	prtstr
+	ld	c,$06			; BDOS direct console I/O
+	ld	e,$FF			; Subfunction = read
+	call	bdos
+	cp	0
+	jr	z,main1
+	call	upcase
+	call	prtchr
+	cp	'X'
+	jp	z,exit
+	call	main2
+	jr	main
 ;
 main2:
-	call	test_kbdmse
-;
-mainz:
-	xor	a
+	; Dispatch to test functions
+	cp	'C'			; Test Controller
+	jp	z,test_ctlr
+	cp	'K'			; Test Keyboard
+	jp	z,test_kbd
+	cp	'M'			; Test Mouse
+	jp	z,test_mse
+	cp	'B'			; Test Both
+	jp	z,test_kbdmse
 	ret
 ;
 ; Test 8242 PS/2 Controller
@@ -109,10 +163,8 @@ test_ctlr:
 	ret	nz
 ;
 	call	ctlr_test_p1
-	;ret	nz
 ;
 	call	ctlr_test_p2
-	;ret	nz
 ;
 	ret
 ;
@@ -123,13 +175,15 @@ test_kbd:
 ; First, we attempt to contact the controller and keyboard, then
 ; print the keyboard identity and scan codes supported
 ;
-	; Run test series with translation off
 	call	crlf2
 	ld	de,str_basic
 	call	prtstr
+;
+	call	ctlr_test
+	jr	nz,test_kbd_fail
 ;
 	call	test_kbd_basic
-	ret	nz
+	jr	nz,test_kbd_fail
 ;
 ; We make two passes through the test series with different controller
 ; setup values.  The first time is with scan code translation off and
@@ -155,59 +209,83 @@ test_kbd:
 ;
 	ret
 ;
+test_kbd_fail:
+	ld	de,str_kbd_failed
+	call	crlf2
+	call	prtstr
+	ret
+;
 ; Test Mouse
 ;
 test_mse:
 	call	crlf2
 	ld	de,str_basic_mse
 	call	prtstr
+;
+	call	ctlr_test
+	jr	nz,test_mse_fail
 ;
 	ld	a,$10			; kbd disabled, mse enabled, no ints
 	call	ctlr_setup
-	ret	nz
+	jr	nz,test_mse_fail
 ;
 	call	mse_reset
-	ret	nz
+	jr	nz,test_mse_fail
 ;
 	call	mse_ident
-	ret	nz
+	jr	nz,test_mse_fail
 ;
 	call	mse_stream
-	ret	nz
+	jr	nz,test_mse_fail
 ;
 	call	mse_echo
 ;	
 	xor	a			; signal success
 	ret
 ;
+test_mse_fail:
+	ld	de,str_mse_failed
+	call	crlf2
+	call	prtstr
+	ret
+;
 ; Test Everything
 ;
 test_kbdmse:
 	call	crlf2
 	ld	de,str_kbdmse
 	call	prtstr
+;
+	call	ctlr_test
+	jr	nz,test_kbdmse_fail
 ;
 	ld	a,$00			; kbd enabled, mse enabled, no ints
 	call	ctlr_setup
-	ret	nz
+	jr	nz,test_kbdmse_fail
 ;
 	call	kbd_reset
-	ret	nz
+	jr	nz,test_kbdmse_fail
 ;
 	ld	a,2
 	call	kbd_setsc
 ;
 	call	mse_reset
-	ret	nz
+	jr	nz,test_kbdmse_fail
 ;
 	call	mse_stream
-	ret	nz
+	jr	nz,test_kbdmse_fail
 ;
 	call	kbdmse_echo
 ;	
 	xor	a			; signal success
 	ret
 ;
+test_kbdmse_fail:
+	ld	de,str_kbdmse_failed
+	call	crlf2
+	call	prtstr
+	ret
+;
 ; Perform basic keyboard tests, display keyboard identity, and
 ; inventory the supported scan code sets.
 ;
@@ -782,7 +860,9 @@ wait_write:
 	ld	a,(timeout)		; setup timeout constant
 	ld	b,a
 wait_write1:
-	in	a,(iocmd)		; get status
+	ld	a,(iocmd)		; cmd port
+	ld	c,a			; ... to C
+	in	a,(c)			; get status
 	ld	c,a			; save status
 	and	$02			; isolate input buf status bit
 	ret	z			; 0 means ready, all done
@@ -804,7 +884,9 @@ wait_read:
 	ld	a,(timeout)		; setup timeout constant
 	ld	b,a
 wait_read1:
-	in	a,(iocmd)		; get status
+	ld	a,(iocmd)		; cmd port
+	ld	c,a			; ... to C
+	in	a,(c)			; get status
 	ld	c,a			; save status
 	and	$01			; isolate input buf status bit
 	xor	$01			; invert so 0 means ready
@@ -824,7 +906,9 @@ check_read:
 ; Check for data ready to read
 ;   A=0 indicates data available (ZF set)
 ;
-	in	a,(iocmd)		; get status
+	ld	a,(iocmd)		; cmd port
+	ld	c,a			; ... to C
+	in	a,(c)			; get status
 	and	$01			; isolate input buf status bit
 	xor	$01			; invert so 0 means ready
 	ret
@@ -834,7 +918,9 @@ check_read_kbd:
 ; Check for keyboard data ready to read
 ;   A=0 indicates data available (ZF set)
 ;
-	in	a,(iocmd)		; get status
+	ld	a,(iocmd)		; cmd port
+	ld	c,a			; ... to C
+	in	a,(c)			; get status
 	and	%00100001		; isolate input buf status bit
 	cp	%00000001		; data ready, not mouse
 	ret
@@ -844,7 +930,9 @@ check_read_mse:
 ; Check for mouse data ready to read
 ;   A=0 indicates data available (ZF set)
 ;
-	in	a,(iocmd)		; get status
+	ld	a,(iocmd)		; cmd port
+	ld	c,a			; ... to C
+	in	a,(c)			; get status
 	and	%00100001		; isolate input buf status bit
 	cp	%00100001		; data ready, is mouse
 	ret
@@ -860,8 +948,10 @@ put_cmd:
 	scf				; else, signal timeout error
 	ret				; and bail out
 put_cmd1:
+	ld	a,(iocmd)		; cmd port
+	ld	c,a			; ... to C
 	ld	a,e			; recover value to write
-	out	(iocmd),a		; write it
+	out	(c),a			; write it
 	or	a			; clear CF for success
 	ret
 ;
@@ -889,8 +979,10 @@ put_data:
 	scf				; else, signal timeout error
 	ret				; and bail out
 put_data1:
+	ld	a,(iodat)		; data port
+	ld	c,a			; ... to C
 	ld	a,e			; recover value to write
-	out	(iodat),a		; write it
+	out	(c),a			; write it
 	or	a			; clear CF for success
 	ret
 ;
@@ -947,7 +1039,9 @@ get_data:
 	scf				; else signal timeout error
 	ret				; and bail out
 get_data1:
-	in	a,(iodat)		; get data byte
+	ld	a,(iodat)		; data port
+	ld	c,a			; ... to C
+	in	a,(c)			; get data byte
 	or	a			; clear CF for success
 	ret
 ;
@@ -1020,11 +1114,11 @@ err_ret:
 ; Utility Routines
 ;=======================================================================
 ;
-;
 ; Print character in A without destroying any registers
 ;
 prtchr:
-	push	bc		; save registers
+	push	af		; save registers
+	push	bc
 	push	de
 	push	hl
 	ld	e,a		; character to print in E
@@ -1033,6 +1127,7 @@ prtchr:
 	pop	hl		; restore registers
 	pop	de
 	pop	bc
+	pop	af
 	ret
 ;
 prtdot:
@@ -1044,6 +1139,16 @@ prtdot:
 	pop	af		; restore af
 	ret			; done
 ;
+; Uppercase character in A
+;
+upcase:
+	cp	'a'			; below 'a'?
+	ret	c			; if so, nothing to do
+	cp	'z'+1			; above 'z'?
+	ret	nc			; if so, nothing to do
+	and	~$20			; convert character to lower
+	ret				; done
+;
 ; Print a zero terminated string at (de) without destroying any registers
 ;
 prtstr:
@@ -1239,7 +1344,21 @@ delay1:
 ; Constants
 ;=======================================================================
 ;
-str_banner		.db	"PS/2 Keyboard/Mouse Information v0.4, 7-Jan-2022",0
+str_banner		.db	"PS/2 Keyboard/Mouse Information v0.6a, 2-Apr-2022",0
+str_hwmenu		.db	"PS/2 Controller Port Options:\r\n\r\n"
+			.db	"  1 - MBC\r\n"
+			.db	"  2 - RHYOPHYRE\r\n"
+			.db	"  X - Exit Application\r\n"
+			.db	"\r\nSelection? ",0
+str_mbc			.db	"MBC",0
+str_rph			.db	"RHYOPHYRE",0
+str_menu		.db	"PS/2 Testing Options:\r\n\r\n"
+			.db	"  C - Test PS/2 Controller\r\n"
+			.db	"  K - Test PS/2 Keyboard\r\n"
+			.db	"  M - Test PS/2 Mouse\r\n"
+			.db	"  B - Test Both PS/2 Keyboard and Mouse Together\r\n"
+			.db	"  X - Exit Application\r\n"
+			.db	"\r\nSelection? ",0
 str_exit		.db	"Done, Thank you for using PS/2 Keyboard/Mouse Information!",0
 str_cmdport		.db	"Controller Command Port: ",0
 str_dataport		.db	"Controller Data Port: ",0
@@ -1312,6 +1431,11 @@ str_mse_failed		.db	"***** MOUSE HARDWARE ERROR *****",13,10,13,10
 			.db	"the completion of the full set of mouse tests.",13,10
 			.db	"Check your hardware and verify the port",13,10
 			.db	"addresses being used for the controller",0
+str_kbdmse_failed	.db	"***** KEYBOARD/MOUSE HARDWARE ERROR *****",13,10,13,10
+			.db	"A basic hardware or configuration issue prevented",13,10
+			.db	"the completion of the full set of keyboard/mouse tests.",13,10
+			.db	"Check your hardware and verify the port",13,10
+			.db	"addresses being used for the controller",0
 ;
 ;=======================================================================
 ; Working data
@@ -1321,6 +1445,9 @@ stksav		.dw	0		; stack pointer saved at start
 		.fill	stksiz,0	; stack
 stack		.equ	$		; stack top
 ;
+iocmd		.db	0
+iodat		.db	0
+;
 workbuf		.fill	8
 workbuf_len	.db	0
 ;

Source/Apps/Test/rzsz/rz.asm

@@ -327,9 +327,9 @@ bdos_s:		call	bdos
 		ret
 
 ;----------------------------------------------------------------------------
-;		S u b r	o u t i	n e
+;		Search for 0 terminated string starting at HL
 
-sub_476:	push	af
+Search0:	push	af
 loc_477:	push	bc
 		xor	a
 		ld	b,a
@@ -361,7 +361,7 @@ text495h:	.db	0,0,0
 
 sub_4A4:	ld	de,file_fcb
 		ld	hl,byte_4F8
-		ld	(hl),3Ah
+		ld	(hl),':'
 		inc	hl
 		xor	a
 		ld	b,0Dh
@@ -370,14 +370,14 @@ sub_4A4:	ld	de,file_fcb
 		call	sub_16C4
 		dec	de
 		ld	a,(de)
-		add	a,40h
+		add	a,'A'-1
 		ld	(byte_4F4),a
 		dec	de
 		ld	a,(de)
 		ld	de,byte_4F5
 		call	sub_16E7
-		ld	a,24h
-		ld	(byte_507),a
+		ld	a,'$'
+		ld	(term_fn),a
 		ld	de,text4F2h
 		ld	c,C_WRITESTR
 		call	bdos		; Output string
@@ -386,13 +386,13 @@ sub_4A4:	ld	de,file_fcb
 		or	l
 		ret	z
 		ld	b,1
-		call	sub_476
+		call	Search0
 		dec	hl
-		ld	(hl),24h
+		ld	(hl),'$'
 		ld	de,(byte_2CD4)
 		ld	c,C_WRITESTR
 		call	bdos		; Output string
-		ld	de,text508h
+		ld	de,newline
 		ld	c,C_WRITESTR
 		jp	bdos		; Output string
 
@@ -418,8 +418,8 @@ byte_4F8:	.db	0 ;
 		.db	0 ;
 		.db	0 ;
 		.db	20h ;
-byte_507:	.db	0			
-text508h:	.text	"\r\n$"
+term_fn:	.db	0			
+newline:	.text	"\r\n$"
 
 ;----------------------------------------------------------------------------
 ;		S u b r	o u t i	n e
@@ -1278,7 +1278,7 @@ loc_9AE:	ld	a,(byte_8AF)
 		ret	z
 		push	hl
 		ld	b,1
-		call	sub_476
+		call	Search0
 		dec	hl
 		ld	(hl),20h
 		pop	hl

Source/Apps/Tune/tune.asm

@@ -44,6 +44,7 @@
 ;   2020-09-03 [E?B] Add support for Ed Brindley YM/AY Sound Card v6
 ;   2021-08-13 [WBW] Add support for LiNC Z50 Sound Card
 ;   2021-08-17 [WBW] When playing via HBIOS, call BF_SNDRESET at end
+;   2022-03-20 [DDW] Add support for MBC PSG module
 ;_______________________________________________________________________________
 ;
 ; ToDo:
@@ -653,7 +654,7 @@ TMP		.DB	0	; work around use of undocumented Z80
 HBIOSMD		.DB	0	; NON-ZERO IF USING HBIOS SOUND DRIVER, ZERO OTHERWISE
 OCTAVEADJ	.DB	0	; AMOUNT TO ADJUST OCTAVE UP OR DOWN
 
-MSGBAN		.DB	"Tune Player for RomWBW v3.4, 17-Aug-2021",0
+MSGBAN		.DB	"Tune Player for RomWBW v3.5, 20-Mar-2022",0
 MSGUSE		.DB	"Copyright (C) 2021, Wayne Warthen, GNU GPL v3",13,10
 		.DB	"PTxPlayer Copyright (C) 2004-2007 S.V.Bulba",13,10
 		.DB	"MYMPlay by Marq/Lieves!Tuore",13,10,13,10

Source/Apps/VGM/vgmplay.asm

@@ -1,16 +1,17 @@
 ;------------------------------------------------------------------------------
-; SN76489 + AY-3-8910 + YM2162 VGM player for CP/M
+; SN76489 + AY-3-8910 + YM2162 + YM2151 VGM player for CP/M
 ;------------------------------------------------------------------------------
 ;
 ; Based on VGM player by J.B. Langston
 ; https://github.com/jblang/SN76489
 ;
 ; Enhanced with multi-chip support by Marco Maccaferri
+; YM2151 support from Ed Brindley
 ;
 ; YM2162/YM3484, GD3 support, VGM Chip identification, 
 ; default file type, basic file size checking added by Phil Summers
 ;
-; Bugs: YM2612 Mute not working.
+; Bugs: YM2151 playback untested & no mute.
 ;
 ; Assemble with:
 ;
@@ -20,84 +21,145 @@
 ; Device and system specific definitions
 ;------------------------------------------------------------------------------
 ;
-P8X180          .EQU    0                   ; System configuration
+P8X180          .EQU    0           	        ; System configuration
 RC2014          .EQU    0
 SBCECB		.EQU	1
-
+MBC		.EQU	0
+;
                 .IF P8X180
-RSEL            .EQU    82H                 ; Primary AY-3-8910 Register selection
-RDAT            .EQU    83H                 ; Primary AY-3-8910 Register data
-RSEL2           .EQU    88H                 ; Secondary AY-3-8910 Register selection
-RDAT2           .EQU    89H                 ; Secondary AY-3-8910 Register data
-PSGREG          .EQU    84H                 ; Primary SN76489
-PSG2REG         .EQU    8AH                 ; Secondary SN76489
-FRAME_DLY       .EQU    48                  ; Frame delay (~ 1/44100)
+RSEL            .EQU    82H			; Primary AY-3-8910 Register selection
+RDAT            .EQU    83H			; Primary AY-3-8910 Register data
+RSEL2           .EQU    88H			; Secondary AY-3-8910 Register selection
+RDAT2           .EQU    89H			; Secondary AY-3-8910 Register data
+PSG1REG         .EQU    84H			; Primary SN76489
+PSG2REG         .EQU    8AH			; Secondary SN76489
+YM2151_SEL1	.EQU	0B0H			; Primary YM2151 register selection
+YM2151_DAT1	.EQU	0B1H			; Primary YM2151 register data
+YM2151_SEL2	.EQU	0B2H			; Secondary YM2151 register selection
+YM2151_DAT2	.EQU	0B3H			; Secondary YM2151 register data
+FRAME_DLY       .EQU    48			; Frame delay (~ 1/44100)
                 .ENDIF
-
+;
                 .IF RC2014
-RSEL            .EQU    0D8H                ; Primary AY-3-8910 Register selection
-RDAT            .EQU    0D0H                ; Primary AY-3-8910 Register data
-RSEL2           .EQU    0A0H                ; Secondary AY-3-8910 Register selection
-RDAT2           .EQU    0A1H                ; Secondary AY-3-8910 Register data
-PSGREG          .EQU    0FFH                ; Primary SN76489
-PSG2REG         .EQU    0FBH                ; Secondary SN76489
-FRAME_DLY       .EQU    15                  ; Frame delay (~ 1/44100)
+RSEL            .EQU    0D8H			; Primary AY-3-8910 Register selection
+RDAT            .EQU    0D0H			; Primary AY-3-8910 Register data
+RSEL2           .EQU    0A0H			; Secondary AY-3-8910 Register selection
+RDAT2           .EQU    0A1H			; Secondary AY-3-8910 Register data
+PSG1REG         .EQU    0FFH			; Primary SN76489
+PSG2REG         .EQU    0FBH			; Secondary SN76489
+YM2151_SEL1	.EQU	0FEH			; Primary YM2151 register selection
+YM2151_DAT1	.EQU	0FFH			; Primary YM2151 register data
+YM2151_SEL2	.EQU	0D0H			; Secondary YM2151 register selection
+YM2151_DAT2	.EQU	0D1H			; Secondary YM2151 register data
+FRAME_DLY       .EQU    15			; Frame delay (~ 1/44100)
                 .ENDIF
-
+;
                 .IF SBCECB
 RSEL            .EQU    0D8H			; Primary AY-3-8910 Register selection
 RDAT            .EQU    0D0H			; Primary AY-3-8910 Register data
 RSEL2           .EQU    0A0H			; Secondary AY-3-8910 Register selection
 RDAT2           .EQU    0A1H			; Secondary AY-3-8910 Register data
+YMSEL		.EQU	0C0H			; Primary YM2162 11000000 a1=0 a0=0
+YMDAT		.EQU	0C1H			; Primary YM2162 11000001 a1=0 a0=1
+YM2SEL		.EQU	0C2H			; Secondary YM2162 11000010 a1=1 a0=0
+YM2DAT		.EQU	0C3H			; Secondary YM2162 11000011 a1=1 a0=1
+PSG1REG         .EQU    0C6H			; Primary SN76489
+PSG2REG         .EQU    0C7H			; Secondary SN76489
+YM2151_SEL1	.EQU	0FEH			; Primary YM2151 register selection
+YM2151_DAT1	.EQU	0FFH			; Primary YM2151 register data
+YM2151_SEL2	.EQU	0FEH			; Secondary YM2151 register selection
+YM2151_DAT2	.EQU	0FFH			; Secondary YM2151 register data
+FRAME_DLY       .EQU    8  			; Frame delay (~ 1/44100)
+                .ENDIF
+;
+		.IF MBC
+RSEL            .EQU    0A0H			; Primary AY-3-8910 Register selection
+RDAT            .EQU    0A1H			; Primary AY-3-8910 Register data
+RSEL           	.EQU    0D8H			; Secondary AY-3-8910 Register selection
+RDAT           	.EQU    0D0H			; Secondary AY-3-8910 Register data
 YMSEL		.EQU	0C0H			; 11000000 a1=0 a0=0
 YMDAT		.EQU	0C1H			; 11000001 a1=0 a0=1
 YM2SEL		.EQU	0C2H			; 11000010 a1=1 a0=0
 YM2DAT		.EQU	0C3H			; 11000011 a1=1 a0=1
 PSGREG          .EQU    0C6H			; Primary SN76489
 PSG2REG         .EQU    0C7H			; Secondary SN76489
+YM2151_SEL1	.EQU	0FEH			; Primary YM2151 register selection
+YM2151_DAT1	.EQU	0FFH			; Primary YM2151 register data
+YM2151_SEL2	.EQU	0FEH			; Secondary YM2151 register selection
+YM2151_DAT2	.EQU	0FFH			; Secondary YM2151 register data
 FRAME_DLY       .EQU    10  			; Frame delay (~ 1/44100)
-
-#DEFINE SBCV2004
-HB_RTCVAL	.EQU	0FFEEH	
-RTCIO		.EQU	070H
-
                 .ENDIF
+;
+;------------------------------------------------------------------------------
+; Your customer overrides can go in here i.e. ports 
+;------------------------------------------------------------------------------
+;
+;RSEL            .SET    09AH			; Primary AY-3-8910 Register selection
+;RDAT            .SET    09BH			; Primary AY-3-8910 Register data
+;
+;------------------------------------------------------------------------------
+; Frame delay overide values for different processor speeds. 
+;------------------------------------------------------------------------------
+;
+;FRAME_DLY       .SET    10  			; 1Mhz	; not 
+;FRAME_DLY       .SET    10  			; 2Mhz	; implemented
+;FRAME_DLY       .SET    10  			; 4Mhz	; yet
+;FRAME_DLY       .SET    15  			; 8Mhz
+;FRAME_DLY       .SET    10  			; 10Mhz
+;FRAME_DLY       .SET    20  			; 12Mhz
+;
+;------------------------------------------------------------------------------
+; Frame delay values for pal/ntsc
+;------------------------------------------------------------------------------
+;
+D60		.EQU	735
+D50		.EQU	882
+;
+;------------------------------------------------------------------------------
+; Processor speed control for SBCV2004+
+;------------------------------------------------------------------------------
+;
+;#DEFINE 	SBCV2004			; My SBC board at 12Mhz needs this to switch to
+HB_RTCVAL	.EQU	0FFEEH			; 6MHz for it to work with the ECB-VGM reliably.
+RTCIO		.EQU	070H						
 
-
+;------------------------------------------------------------------------------
+; YM2162 Register write macros
+;------------------------------------------------------------------------------
+;
 #DEFINE	setreg(reg,val) \
 #DEFCONT \	ld	a,reg 
 #DEFCONT \	out	(YMSEL),a 
-#DEFCONT \	nop
-#DEFCONT \	nop
 #DEFCONT \	ld	a,val 
 #DEFCONT \	out	(YMDAT),a 
-#DEFCONT \	nop
-#DEFCONT \	nop
-
+#DEFCONT \	in	a,(YMSEL)
+#DEFCONT \	rlca
+#DEFCONT \	jp	c,$-3
+;
 #DEFINE	setreg2(reg,val) \
 #DEFCONT \	ld	a,reg 
 #DEFCONT \	out	(YM2SEL),a 
-#DEFCONT \	nop
-#DEFCONT \	nop
 #DEFCONT \	ld	a,val 
-#DEFCONT \	out	(YM2DAT),a 
-#DEFCONT \	nop
-#DEFCONT \	nop
-
-D50		.EQU	500			; 900			;735
-D60		.EQU	600			; 1000			;882
+#DEFCONT \	out	(YM2DAT),a
+#DEFCONT \	in	a,(YMSEL)
+#DEFCONT \	rlca
+#DEFCONT \	jp	c,$-3 
 
 ;------------------------------------------------------------------------------
 ; VGM Codes
 ;------------------------------------------------------------------------------
 
 VGM_GG_W	.EQU	04FH			; GAME GEAR PSG STEREO. WRITE DD TO PORT 0X06
-VGM_PSG_W	.EQU	050H			; PSG (SN76489/SN76496) WRITE VALUE DD
-VGM_YM2612_W	.EQU	052H			; YM2612 WRITE VALUE DD
+VGM_PSG1_W	.EQU	050H			; PSG (SN76489/SN76496) #1 WRITE VALUE DD
+VGM_PSG2_W	.EQU	030H			; PSG (SN76489/SN76496) #2 WRITE VALUE DD
+VGM_YM26121_W	.EQU	052H			; YM2612 #1 WRITE VALUE DD
+VGM_YM26122_W	.EQU	053H			; YM2612 #2 WRITE VALUE DD
 VGM_WNS		.EQU	061H			; WAIT N SAMPLES
 VGM_W735	.EQU	062H			; WAIT 735 SAMPLES (1/60TH SECOND)
 VGM_W882	.EQU	063H			; WAIT 882 SAMPLES (1/50TH SECOND)
 VGM_ESD		.EQU	066H			; END OF SOUND DATA
+VGM_YM21511_W	.EQU	054H			; YM2612 #1 WRITE VALUE DD
+VGM_YM21512_W	.EQU	0A4H			; YM2612 #2WRITE VALUE DD
 
 ;------------------------------------------------------------------------------
 ; Generic CP/M definitions
@@ -168,13 +230,12 @@ L1              LD      B,FRAME_DLY
 ; Program Exit
 ;------------------------------------------------------------------------------
 ;
-EXIT
+EXIT:		CALL	VGMDEVICES		; Display devices used
+		CALL	VGMMUTE			; Mute Devices
+		
 #IFDEF SBCV2004
 		CALL	FASTIO
 #ENDIF
-		CALL	VGMDEVICES		; Display devices used
-		CALL	VGMMUTE			; Mute Devices
-		
 		LD	DE,MSG_EXIT		
 EXIT_ERR:	CALL	PRTSTR			; Generic message or error
                 LD      SP, (OLDSTACK)		; Exit to CP/M
@@ -266,7 +327,7 @@ VGMINFO:	LD	DE,MSG_BADF		; Check valid file
 		EX	DE,HL
 		PUSH	BC
 		POP	DE
-;		CALL	PRTHEX32
+;		CALL	PRTHEX32		; Debug
 
 		LD	HL,(VGMDATA+16H)	; Is GD3 in range?
 		LD	A,H
@@ -296,6 +357,9 @@ VGMINFO:	LD	DE,MSG_BADF		; Check valid file
 		ADD	HL,DE
 
 		CALL	CRLF
+		LD	DE,MSG_TRACK
+		CALL	PRTSTR
+
 GD3_NXT:	LD	A,(HL)			; Print English Track
 		OR	A
 		INC	HL
@@ -311,7 +375,9 @@ GD3_NXT1:	LD	A,(HL)			; Skip Japanese Track
 		JR	NZ,GD3_NXT1
 ;		JR	GD3_NXT1
 
-		CALL	CRLF
+		LD 	DE,MSG_TITLE
+		CALL	PRTSTR
+
 GD3_NXT2:	LD	A,(HL)			; Print English Title
 		OR	A
 		INC	HL
@@ -349,20 +415,22 @@ NEXT            LD      A, (HL)
 NEXT1           CP      VGM_GG_W		; Game Gear SN76489 stereo. Ignored
                 JR      NZ, PSG
 		LD	IX,VGM_DEV
-		SET	6,(IX+0)
-                INC     HL
-                JR      NEXT
+		SET	0,(IX+1)
+		INC     HL
+		JR      NEXT
 
-PSG             CP      VGM_PSG_W		; Write byte to SN76489.
+;	SN76489 SECTION
+
+PSG             CP      VGM_PSG1_W		; Write byte to SN76489.
                 JR      NZ, PSG2
                 LD      A, (HL)
 		INC	HL
-                OUT     (PSGREG), A
+                OUT     (PSG1REG), A
 		LD	IX,VGM_DEV
 		SET	0,(IX+0)
                 JR      NEXT
 
-PSG2            CP      30H			; Write byte to second SN76489.
+PSG2            CP      VGM_PSG2_W		; Write byte to second SN76489.
                 JR      NZ, AY
                 LD      A, (HL)
                 INC     HL
@@ -371,10 +439,10 @@ PSG2            CP      30H			; Write byte to second SN76489.
 		SET	1,(IX+0)
                 JR      NEXT
 
-;	AY SECTION
+;	AY-3-8910 SECTION
 
 AY              CP      0A0H
-		JR	NZ,YM
+		JR	NZ,YM2162_1
 		LD      A, (HL)
                 INC     HL
                 BIT     7, A			; Bit 7=1 for second AY-3-8910
@@ -395,10 +463,10 @@ AY1		OUT     (RSEL), A
 		SET	3,(IX+0)
                 JR      NEXT
 
-;	YM SECTION
+;	YM2612 SECTION
 
-YM:		CP      052H
-                JR      NZ, YM2
+YM2162_1	CP      VGM_YM26121_W
+                JR      NZ, YM2162_2
 		LD	A,(HL)
 		OUT	(YMSEL),A
 		INC	HL
@@ -409,9 +477,8 @@ YM:		CP      052H
 		SET	4,(IX+0)
 		JP	NEXT
 ;
-YM2:		CP      053H
-                JR      NZ,WAITNN
-
+YM2162_2	CP      VGM_YM26122_W
+                JR      NZ,YM2151_1
 		LD	A,(HL)
 		OUT	(YM2SEL),A
 		INC	HL
@@ -419,10 +486,36 @@ YM2:		CP      053H
 		OUT	(YM2DAT),A
 		INC	HL
 		LD	IX,VGM_DEV
-		SET	4,(IX+0)
+		SET	4,(IX+0)		; 2nd channel 
+		JP	NEXT
+
+;	YM2151 SECTION
+
+YM2151_1	CP      VGM_YM21511_W
+                JR      NZ,YM2151_2
+		LD	A,(HL)
+		OUT	(YM2151_SEL1),A
+		INC	HL
+		LD	A,(HL)
+		OUT	(YM2151_DAT1),A
+		INC	HL
+		LD	IX,VGM_DEV
+		SET	6,(IX+0)
+		JP	NEXT
+;
+YM2151_2	CP      VGM_YM21512_W
+                JR      NZ,WAITNN
+		LD	A,(HL)
+		OUT	(YM2151_SEL2),A
+		INC	HL
+		LD	A,(HL)
+		OUT	(YM2151_DAT2),A
+		INC	HL
+		LD	IX,VGM_DEV
+		SET	7,(IX+0)
 		JP	NEXT
 ;	
-WAITNN:         CP      61H			; Wait nn samples
+WAITNN		CP      VGM_WNS			; Wait nn samples
                 JR      NZ, WAIT60
                 LD      A, (HL)
                 INC     HL
@@ -437,14 +530,14 @@ WAITNN:         CP      61H			; Wait nn samples
 WAIT60          CP      VGM_W735		; Wait 735 samples (60Hz)
                 JR      NZ, WAIT50
                 LD      (VGMPOS), HL
-                LD      HL, D50
+                LD      HL, D60
                 LD      (VGMDLY), HL
                 RET
 ;
 WAIT50          CP      VGM_W882		; Wait 882 samples (50Hz)
                 JR      NZ, WAIT1
                 LD      (VGMPOS), HL
-                LD      HL, D60
+                LD      HL, D50
                 LD      (VGMDLY), HL
                 RET
 ;
@@ -458,8 +551,8 @@ WAIT1           CP      70H			; WAIT 0-15 SAMPLES
                 LD      (VGMDLY), HL
                 RET
 ;
-UNK:		LD	IX,VGM_DEV		; Set flag for
-		SET	6,(IX+0)		; unknown device
+UNK		LD	IX,VGM_DEV		; Set flag for
+		SET	0,(IX+1)		; unknown device
 		INC	HL			; Try and skip
 		JP	NEXT
 ;
@@ -489,24 +582,38 @@ VGMDEVICES:	LD	DE,MSG_PO		; Played on ...
 		SRL	A
 		PUSH	AF
 ;
-		LD	DE,MSG_YM		; YM-2612 Devices
+		LD	DE,MSG_YM2612		; YM-2612 Devices
 		CALL	CHKDEV
 ;
 		POP	AF
 		SRL	A
 		SRL	A
+		PUSH	AF
+;
+		LD	DE,MSG_YM2151		; YM-2151 Devices
+		CALL	CHKDEV
+;
+		POP	AF
+;		SRL	A
+;		SRL	A
 ;		PUSH	AF
 ;
+		LD	A,(IX+1)
 		LD	DE,MSG_UNK		; Unknown Device Code detected
 ;		CALL	CHKDEV
 ;
 CHKDEV:		AND	%00000011		; Display 
-		SRL	A			; number of
-		ADC	A,'0'			; devices
-		CP	'0'
-		RET	Z			; Skip if not
-		CALL	PRTCHR			; used.
-		CALL	PRTSTR
+		RET	Z			; number of
+		SRL	A			; devices
+		ADC	A,'0'
+		CALL	PRTCHR			; Skip if not
+		CALL	PRTSTR			; used.
+		RET
+
+DEBUG:		PUSH	AF
+		LD	A,'*'
+		CALL	PRTCHR
+		POP	AF
 		RET
 ;
 ;------------------------------------------------------------------------------
@@ -518,16 +625,16 @@ VGMMUTE:	LD	A,(IX+0)		; Only mute devices used.
 		JR	Z,SKIP1
 
 		LD      A, 9FH              	; Mute all channels on psg
-                OUT     (PSGREG), A
+                OUT     (PSG1REG), A
                 OUT     (PSG2REG), A
                 LD      A, 0BFH
-                OUT     (PSGREG), A
+                OUT     (PSG1REG), A
                 OUT     (PSG2REG), A
                 LD      A, 0DFH
-                OUT     (PSGREG), A
+                OUT     (PSG1REG), A
                 OUT     (PSG2REG), A
                 LD      A, 0FFH
-                OUT     (PSGREG), A
+                OUT     (PSG1REG), A
                 OUT     (PSG2REG), A
 
 SKIP1:		LD	A,(IX+0)
@@ -554,11 +661,12 @@ SKIP1:		LD	A,(IX+0)
                 OUT     (RDAT2), A
 		CALL	FASTIO
 
-SKIP2:		LD	A,(IX+0)
+SKIP2:		LD	A,(IX+0)		; mute all channels on ym2612
 		AND	%00110000
 		JP	Z,SKIP3
 
 		setreg($22,$00)			; lfo off
+
 		setreg($27,$00)			; Disable independant Channel 3
 		setreg($28,$00)			; note off ch 1
 		setreg($28,$01)			; note off ch 2
@@ -573,9 +681,240 @@ SKIP2:		LD	A,(IX+0)
 		setreg($b6,$00)
 		setreg2($b4,$00)		; sound off ch 4-6
 		setreg2($b5,$00)
-		setreg2($b6,$00)		
+		setreg2($b6,$00)
+
+		setreg($40,$7f)			; ch 1-3 total level minimum
+		setreg($41,$7f)
+		setreg($42,$7f)
+		setreg($44,$7f)
+		setreg($45,$7f)
+		setreg($46,$7f)
+		setreg($48,$7f)
+		setreg($49,$7f)
+		setreg($4a,$7f)
+		setreg($4c,$7f)
+		setreg($4d,$7f)
+		setreg($4e,$7f)
+
+		setreg2($40,$7f)		; ch 4-6 total level minimum
+		setreg2($41,$7f)
+		setreg2($42,$7f)
+		setreg2($44,$7f)
+		setreg2($45,$7f)
+		setreg2($46,$7f)
+		setreg2($48,$7f)
+		setreg2($49,$7f)
+		setreg2($4a,$7f)
+		setreg2($4c,$7f)
+		setreg2($4d,$7f)
+		setreg2($4e,$7f)
+
+#if (0)
+
+		setreg($2a,$00)			; dac value
+
+		setreg($24,$00)			; timer A frequency
+		setreg($25,$00)			; timer A frequency
+		setreg($26,$00)			; time B frequency
+
+		setreg($30,$00)			; ch 1-3 multiply & detune
+		setreg($31,$00)
+		setreg($32,$00)
+		setreg($34,$00)
+		setreg($35,$00)
+		setreg($36,$00)
+		setreg($38,$00)
+		setreg($39,$00)
+		setreg($3a,$00)
+		setreg($3c,$00)
+		setreg($3d,$00)
+		setreg($3e,$00)
+
+		setreg2($30,$00)		; ch 4-6 multiply & detune
+		setreg2($31,$00)
+		setreg2($32,$00)
+		setreg2($34,$00)
+		setreg2($35,$00)
+		setreg2($36,$00)
+		setreg2($38,$00)
+		setreg2($39,$00)
+		setreg2($3a,$00)
+		setreg2($3c,$00)
+		setreg2($3d,$00)
+		setreg2($3e,$00)
+
+		setreg($50,$00)			; ch 1-3 attack rate and scaling
+		setreg($51,$00)
+		setreg($52,$00)
+		setreg($54,$00)
+		setreg($55,$00)
+		setreg($56,$00)
+		setreg($58,$00)
+		setreg($59,$00)
+		setreg($5a,$00)
+		setreg($5c,$00)
+		setreg($5d,$00)
+		setreg($5e,$00)
+
+		setreg2($50,$00)		; ch 4-6 attack rate and scaling
+		setreg2($51,$00)
+		setreg2($52,$00)
+		setreg2($54,$00)
+		setreg2($55,$00)
+		setreg2($56,$00)
+		setreg2($58,$00)
+		setreg2($59,$00)
+		setreg2($5a,$00)
+		setreg2($5c,$00)
+		setreg2($5d,$00)
+		setreg2($5e,$00)
+
+		setreg($60,$00)			; ch 1-3 decay rate and am enable
+		setreg($61,$00)
+		setreg($62,$00)
+		setreg($64,$00)
+		setreg($65,$00)
+		setreg($66,$00)
+		setreg($68,$00)
+		setreg($69,$00)
+		setreg($6a,$00)
+		setreg($6c,$00)
+		setreg($6d,$00)
+		setreg($6e,$00)
+
+		setreg2($60,$00)		; ch 4-6 decay rate and am enable
+		setreg2($61,$00)
+		setreg2($62,$00)
+		setreg2($64,$00)
+		setreg2($65,$00)
+		setreg2($66,$00)
+		setreg2($68,$00)
+		setreg2($69,$00)
+		setreg2($6a,$00)
+		setreg2($6c,$00)
+		setreg2($6d,$00)
+		setreg2($6e,$00)
+
+		setreg($70,$00)			; ch 1-3 sustain rate
+		setreg($71,$00)
+		setreg($72,$00)
+		setreg($74,$00)
+		setreg($75,$00)
+		setreg($76,$00)
+		setreg($78,$00)
+		setreg($79,$00)
+		setreg($7a,$00)
+		setreg($7c,$00)
+		setreg($7d,$00)
+		setreg($7e,$00)
+
+		setreg2($70,$00)		; ch 4-6 sustain rate
+		setreg2($71,$00)
+		setreg2($72,$00)
+		setreg2($74,$00)
+		setreg2($75,$00)
+		setreg2($76,$00)
+		setreg2($78,$00)
+		setreg2($79,$00)
+		setreg2($7a,$00)
+		setreg2($7c,$00)
+		setreg2($7d,$00)
+		setreg2($7e,$00)
+
+		setreg($80,$00)			; ch 1-3 release rate and sustain level
+		setreg($81,$00)
+		setreg($82,$00)
+		setreg($84,$00)
+		setreg($85,$00)
+		setreg($86,$00)
+		setreg($88,$00)
+		setreg($89,$00)
+		setreg($8a,$00)
+		setreg($8c,$00)
+		setreg($8d,$00)
+		setreg($8e,$00)
+
+		setreg2($80,$00)		; ch 4-6 release rate and sustain level
+		setreg2($81,$00)
+		setreg2($82,$00)
+		setreg2($84,$00)
+		setreg2($85,$00)
+		setreg2($86,$00)
+		setreg2($88,$00)
+		setreg2($89,$00)
+		setreg2($8a,$00)
+		setreg2($8c,$00)
+		setreg2($8d,$00)
+		setreg2($8e,$00)
+
+		setreg($90,$00)			; ch 1-3 ssg-eg
+		setreg($91,$00)
+		setreg($92,$00)
+		setreg($94,$00)
+		setreg($95,$00)
+		setreg($96,$00)
+		setreg($98,$00)
+		setreg($99,$00)
+		setreg($9a,$00)
+		setreg($9c,$00)
+		setreg($9d,$00)
+		setreg($9e,$00)
+
+		setreg2($90,$00)		; ch 4-6 ssg-eg
+		setreg2($91,$00)
+		setreg2($92,$00)
+		setreg2($94,$00)
+		setreg2($95,$00)
+		setreg2($96,$00)
+		setreg2($98,$00)
+		setreg2($99,$00)
+		setreg2($9a,$00)
+		setreg2($9c,$00)
+		setreg2($9d,$00)
+		setreg2($9e,$00)
+
+		setreg($a0,$00)			; ch 1-3 frequency
+		setreg($a1,$00)
+		setreg($a2,$00)
+		setreg($a4,$00)
+		setreg($a5,$00)
+		setreg($a6,$00)
+;		setreg($a8,$00)			; ch 3 special mode
+;		setreg($a9,$00)
+;		setreg($aa,$00)
+;		setreg($ac,$00)
+;		setreg($ad,$00)
+;		setreg($ae,$00)
+
+		setreg2($a0,$00)		; ch 4-6 frequency
+		setreg2($a1,$00)
+		setreg2($a2,$00)
+		setreg2($a4,$00)
+		setreg2($a5,$00)
+		setreg2($a6,$00)
+;		setreg2($a8,$00)		; ch 3 special mode
+;		setreg2($a9,$00)
+;		setreg2($aa,$00)
+;		setreg2($ac,$00)
+;		setreg2($ad,$00)
+;		setreg2($ae,$00)
+
+		setreg($b0,$00)			; ch 1-3 algorith + feedback
+		setreg($b1,$00)
+		setreg($b2,$00)
+		setreg2($b0,$00)		; ch 4-6 algorith + feedback
+		setreg2($b1,$00)
+		setreg2($b2,$00)
+
+#endif
 		
-SKIP3:		RET
+SKIP3:		LD	A,(IX+0)		; For YM2151 ... Unimplemented
+		AND	%11000000
+		JP	Z,SKIP4
+
+		; MUTE YM2151
+
+SKIP4		RET
 ;
 ;------------------------------------------------------------------------------
 ; Hardware specific routines.
@@ -609,18 +948,21 @@ FASTIO:
 ; Strings and constants.
 ;------------------------------------------------------------------------------
 ;
-MSG_WELC:	.DB	"VGM Player for RomWBW v0.2, 27-Nov-2021",CR,LF
+MSG_WELC:	.DB	"VGM Player for RomWBW v0.3, 2-Jul-2022",CR,LF
 ;		.DB	"J.B. Langston/Marco Maccaferri/Phil Summers",CR,LF
 		.DB	0
 MSG_BADF:	.DB	"Not a VGM file",CR,LF,0
 MSG_PO		.DB	"Played on : ",0
-MSG_YM:		.DB	"xYM-2612 ",0
+MSG_YM2612:	.DB	"xYM-2612 ",0
 MSG_SN:		.DB	"xSN76489 ",0
 MSG_AY:		.DB	"xAY-3-8910 ",0
-MSG_UNK		.DB	"xUnsupported device encountered", CR, LF, 0
+MSG_YM2151:	.DB	"xYM-2151 ",0
+MSG_UNK:	.DB	"xUnsupported device encountered", CR, LF, 0
 MSG_EXIT:	.DB	"FINISHED.",CR,LF,0
 MSG_NOFILE:     .DB	"File not found", CR, LF, 0
 MSG_MEM:	.DB	"File to big", CR, LF, 0
+MSG_TITLE:	.DB	" from: ",0
+MSG_TRACK	.DB	"Playing: ",0
 ;
 ;------------------------------------------------------------------------------
 ; Variables
@@ -629,7 +971,8 @@ MSG_MEM:	.DB	"File to big", CR, LF, 0
 VGMPOS          .DW     0
 VGMDLY          .DW     0
 VGMUNK_F	.DB	0		; Flag for unknown device
-VGM_DEV		.DB	%00000000	; UUYYAASS
+VGM_DEV		.DB	%00000000	; yyYYAASS
+		.DB	%00000000	; Unimplemented device flags
 
 OLDSTACK        .DW     0		; original stack pointer
                 .DS     40H		; space for stack

Source/Apps/assign.asm

@@ -244,7 +244,7 @@ initcpm3:
 ; The CP/M 3 drvtbl is in common memory, but the XDPHs are not.
 ; So, here we temporarily swap the bank to the CP/M 3 system
 ; bank.  We cannot use the CP/M Direct BIOS call because it
-; explicitly blocks use of SELMEM, so we are foreced to use
+; explicitly blocks use of SELMEM, so we are forced to use
 ; HBIOS call.  The CP/M 3 system bank is always the HBIOS
 ; user bank.
 ;

Source/Apps/rtc.asm

@@ -29,6 +29,8 @@
 ;
 ;[2021/07/10] v1.7 Support MBC (AJL)
 ;
+;[2022/03/27] v1.8 Support RHYOPHYRE
+;
 ; Constants
 ;
 mask_data	.EQU	%10000000	; RTC data line
@@ -46,6 +48,7 @@ PORT_SCZ180	.EQU	$0C		; RTC port for SCZ180
 PORT_DYNO	.EQU	$0C		; RTC port for DYNO
 PORT_RCZ280	.EQU	$C0		; RTC port for RCZ280
 PORT_MBC	.EQU	$70		; RTC port for MBC
+PORT_RPH	.EQU	$84		; RTC port for RHYOPHYRE
 
 
 BDOS		.EQU	5		; BDOS invocation vector
@@ -1126,6 +1129,11 @@ HINIT:
 	LD	DE,PLT_MBC
 	CP	13		; MBC
 	JR	Z,RTC_INIT2
+;
+	LD	C,PORT_RPH
+	LD	DE,PLT_RPH
+	CP	14		; RHYOPHYRE
+	JR	Z,RTC_INIT2
 ;
 	; Unknown platform
 	LD	DE,PLTERR	; BIOS error message
@@ -1622,7 +1630,7 @@ TESTING_BIT_DELAY_OVER:
 
 RTC_HELP_MSG:
 	.DB	0Ah, 0Dh		; line feed and carriage return
-	.TEXT	"RTC: Version 1.7"
+	.TEXT	"RTC: Version 1.8"
 	.DB	0Ah, 0Dh		; line feed and carriage return
 	.TEXT	"Commands: E)xit T)ime st(A)rt S)et R)aw L)oop C)harge N)ocharge D)elay I)nit G)et P)ut B)oot W)arm-start H)elp"
 	.DB	0Ah, 0Dh		; line feed and carriage return
@@ -1751,6 +1759,7 @@ PLT_SCZ180	.TEXT	", SC Z180 RTC Module Latch Port 0x0C\r\n$"
 PLT_DYNO	.TEXT	", DYNO RTC Module Latch Port 0x0C\r\n$"
 PLT_RCZ280	.TEXT	", RC2014 Z280 RTC Module Latch Port 0xC0\r\n$"
 PLT_MBC		.TEXT	", MBC RTC Latch Port 0x70\r\n$"
+PLT_RPH		.TEXT	", RHYOPHYRE RTC Latch Port 0x84\r\n$"
 
 ;
 ; Generic FOR-NEXT loop algorithm

Source/Apps/sysgen.z80

@@ -22,7 +22,7 @@ DREADF	EQU	20		; DISK READ FUNCTION
 ;
 CR	EQU	0DH		; CARRIAGE RETURN
 LF	EQU	0AH		; LINE FEED
-STKSIZE	EQU	16		; SIZE OF LOCAL STACK
+STKSIZE	EQU	32		; SIZE OF LOCAL STACK
 ;
 WBOOT	EQU	1		; ADDRESS OF WARM BOOT (OTHER PATCH ENTRY
 ;

Source/BPBIOS/Makefile

@@ -30,7 +30,7 @@ zcpr33n.rel zcpr33t.rel:
 
 all:: $(HD0IMG)
 
-clobber::
+clean::
 	@rm -f $(HD0IMG)
 
 %.img: zcpr33n.rel zcpr33t.rel

Source/BPBIOS/diskdefs

@@ -311,6 +311,7 @@ diskdef wbw_rom1024
 end
 
 # RomWBW 720K floppy media
+
 diskdef wbw_fd720
   seclen 512
   tracks 160
@@ -323,6 +324,7 @@ diskdef wbw_fd720
 end
 
 # RomWBW 1.44M floppy media
+
 diskdef wbw_fd144
   seclen 512
   tracks 160
@@ -335,6 +337,7 @@ diskdef wbw_fd144
 end
 
 # RomWBW 360K floppy media
+
 diskdef wbw_fd360
   seclen 512
   tracks 80
@@ -347,6 +350,7 @@ diskdef wbw_fd360
 end
 
 # RomWBW 1.20M floppy media
+
 diskdef wbw_fd120
   seclen 512
   tracks 160
@@ -359,7 +363,8 @@ diskdef wbw_fd120
 end
 
 # RomWBW 8320KB Hard Disk Slice (512 directory entry format)
-# Legacy format, 512 dir entries, 16,630 sectors / slice
+# Legacy format: 512 dir entries, 16,630 sectors / slice
+
 diskdef wbw_hd512
   seclen 512
   tracks 1040
@@ -372,6 +377,9 @@ diskdef wbw_hd512
 end
 
 # First 4 slices of wbw_hd512
+# Assumes first slice (slice 0) starts at sector 0
+# Offset of any slice (in tracks) = (1040 * <slice_num>)
+
 diskdef wbw_hd512_0
   seclen 512
   tracks 1040
@@ -380,45 +388,50 @@ diskdef wbw_hd512_0
   maxdir 512
   skew 0
   boottrk 16
+  offset 0T
   os 2.2
 end
 
 diskdef wbw_hd512_1
   seclen 512
-  tracks 2080
+  tracks 1040
   sectrk 16
   blocksize 4096
   maxdir 512
   skew 0
-  boottrk 1056
+  boottrk 16
+  offset 1040T
   os 2.2
 end
 
 diskdef wbw_hd512_2
   seclen 512
-  tracks 3120
+  tracks 1040
   sectrk 16
   blocksize 4096
   maxdir 512
   skew 0
-  boottrk 2096
+  boottrk 16
+  offset 2080T
   os 2.2
 end
 
 diskdef wbw_hd512_3
   seclen 512
-  tracks 4160
+  tracks 1040
   sectrk 16
   blocksize 4096
   maxdir 512
   skew 0
-  boottrk 3136
+  boottrk 16
+  offset 3120T
   os 2.2
 end
 
 # RomWBW 8MB Hard Disk (1024 directory entry format)
-# New format, 1024 dir entries, 16,384 sectors / slice
+# New format: 1024 dir entries, 16,384 sectors / slice
 # Pure filesystem image, no MBR prefix
+
 diskdef wbw_hd1024
   seclen 512
   tracks 1024
@@ -431,110 +444,124 @@ diskdef wbw_hd1024
 end
 
 # First 4 slices of wbw_hd1024
-# Assumes 1MB prefix (2048 sectors)
+# Assumes standard 1MB prefix
+# Offset of any slice (in tracks) = 128 + (1024 * <slice_num)
+
 diskdef wbw_hd1024_0
   seclen 512
-  tracks 1040
+  tracks 1024
   sectrk 16
   blocksize 4096
   maxdir 1024
   skew 0
-  boottrk 130
+  boottrk 2
+  offset 128T
   os 2.2
 end
 
 diskdef wbw_hd1024_1
   seclen 512
-  tracks 2064
+  tracks 1024
   sectrk 16
   blocksize 4096
   maxdir 1024
   skew 0
-  boottrk 1154
+  boottrk 2
+  offset 1152T
   os 2.2
 end
 
 diskdef wbw_hd1024_2
   seclen 512
-  tracks 3112
+  tracks 1024
   sectrk 16
   blocksize 4096
   maxdir 1024
   skew 0
-  boottrk 2178
+  boottrk 2
+  offset 2176T
   os 2.2
 end
 
 diskdef wbw_hd1024_3
   seclen 512
-  tracks 4136
+  tracks 1024
   sectrk 16
   blocksize 4096
   maxdir 1024
   skew 0
-  boottrk 3202
+  boottrk 2
+  offset 3200T
   os 2.2
 end
 
 # SmallZ80 Hard Disk Image
 # 5 slices
+
 diskdef smz80_hd0
   seclen 512
-  tracks 1034
+  tracks 1024
   sectrk 16
   blocksize 4096
   maxdir 1024
   skew 0
-  boottrk 10
+  boottrk 0
+  offset 10T
   os 2.2
 end
 
 diskdef smz80_hd1
   seclen 512
-  tracks 2058
+  tracks 1024
   sectrk 16
   blocksize 4096
   maxdir 1024
   skew 0
-  boottrk 1034
+  boottrk 0
+  offset 1034T
   os 2.2
 end
 
 diskdef smz80_hd2
   seclen 512
-  tracks 1034
+  tracks 1024
   sectrk 16
   blocksize 4096
   maxdir 1024
   skew 0
-  boottrk 2058
+  boottrk 0
+  offset 2058T
   os 2.2
 end
 
 diskdef smz80_hd3
   seclen 512
-  tracks 4106
+  tracks 1024
   sectrk 16
   blocksize 4096
   maxdir 1024
   skew 0
-  boottrk 3082
+  boottrk 0
+  offset 3082T
   os 2.2
 end
 
 diskdef smz80_hd4
   seclen 512
-  tracks 5130
+  tracks 1024
   sectrk 16
   blocksize 4096
   maxdir 1024
   skew 0
-  boottrk 4106
+  boottrk 0
+  offset 4106T
   os 2.2
 end
 
-# RC2014 standard hard disk image
+# RC2014 standard (Grant Searle) hard disk image
 # Slices A-P
+# Offset of slice (in tracks) = (512 * <slice_num>)
+
 diskdef rc2014a
   seclen 512
   tracks 512
@@ -542,155 +569,171 @@ diskdef rc2014a
   blocksize 4096
   maxdir 512
   boottrk 1
+  offset 0T
   os 2.2
 end
 
 diskdef rc2014b
   seclen 512
-  tracks 1024
+  tracks 512
   sectrk 32
   blocksize 4096
   maxdir 512
-  boottrk 512
+  boottrk 0
+  offset 512T
   os 2.2
 end
 
 diskdef rc2014c
   seclen 512
-  tracks 1536
+  tracks 512
   sectrk 32
   blocksize 4096
   maxdir 512
-  boottrk 1024
+  boottrk 0
+  offset 1024T
   os 2.2
 end
 
 diskdef rc2014d
   seclen 512
-  tracks 2048
+  tracks 512
   sectrk 32
   blocksize 4096
   maxdir 512
-  boottrk 1536
+  boottrk 0
+  offset 1536T
   os 2.2
 end
 
 diskdef rc2014e
   seclen 512
-  tracks 2560
+  tracks 512
   sectrk 32
   blocksize 4096
   maxdir 512
-  boottrk 2048
+  boottrk 0
+  offset 2048T
   os 2.2
 end
 
 diskdef rc2014f
   seclen 512
-  tracks 3072
+  tracks 512
   sectrk 32
   blocksize 4096
   maxdir 512
-  boottrk 2560
+  boottrk 0
+  offset 2560T
   os 2.2
 end
 
 diskdef rc2014g
   seclen 512
-  tracks 3584
+  tracks 512
   sectrk 32
   blocksize 4096
   maxdir 512
-  boottrk 3072
+  boottrk 0
+  offset 3072T
   os 2.2
 end
 
 diskdef rc2014h
   seclen 512
-  tracks 4096
+  tracks 512
   sectrk 32
   blocksize 4096
   maxdir 512
-  boottrk 3584
+  boottrk 0
+  offset 3584T
   os 2.2
 end
 
 diskdef rc2014i
   seclen 512
-  tracks 4608
+  tracks 512
   sectrk 32
   blocksize 4096
   maxdir 512
-  boottrk 4096
+  boottrk 0
+  offset 4096T
   os 2.2
 end
 
 diskdef rc2014j
   seclen 512
-  tracks 5120
+  tracks 512
   sectrk 32
   blocksize 4096
   maxdir 512
-  boottrk 4608
+  boottrk 0
+  offset 4608T
   os 2.2
 end
 
 diskdef rc2014k
   seclen 512
-  tracks 5632
+  tracks 512
   sectrk 32
   blocksize 4096
   maxdir 512
-  boottrk 5120
+  boottrk 0
+  offset 5120T
   os 2.2
 end
 
 diskdef rc2014l
   seclen 512
-  tracks 6144
+  tracks 512
   sectrk 32
   blocksize 4096
   maxdir 512
-  boottrk 5632
+  boottrk 0
+  offset 5632T
   os 2.2
 end
 
 diskdef rc2014m
   seclen 512
-  tracks 6656
+  tracks 512
   sectrk 32
   blocksize 4096
   maxdir 512
-  boottrk 6144
+  boottrk 0
+  offset 6144T
   os 2.2
 end
 
 diskdef rc2014n
   seclen 512
-  tracks 7168
+  tracks 512
   sectrk 32
   blocksize 4096
   maxdir 512
-  boottrk 6656
+  boottrk 0
+  offset 6656T
   os 2.2
 end
 
 diskdef rc2014o
   seclen 512
-  tracks 7680
+  tracks 512
   sectrk 32
   blocksize 4096
   maxdir 512
-  boottrk 7168
+  boottrk 0
+  offset 7168T
   os 2.2
 end
 
 diskdef rc2014p
   seclen 512
-  tracks 7808
+  tracks 128
   sectrk 32
   blocksize 4096
   maxdir 512
-  boottrk 7680
+  boottrk 0
+  offset 7680T
   os 2.2
 end

Source/CBIOS/cbios.asm

@@ -144,6 +144,43 @@ CBXSIZ	.EQU	$ - CBX
 	.ECHO	" bytes.\n"
 ;
 ;==================================================================================================
+; TIMDAT ROUTINE FOR QP/M
+;==================================================================================================
+;
+#IFDEF PLTWBW
+  #IF QPMTIMDAT
+;
+TIMDAT:
+	; GET CURRENT DATE/TIME FROM RTC INTO BUFFER
+	LD	B,BF_RTCGETTIM		; HBIOS GET TIME FUNCTION
+	LD	HL,CLKDAT		; POINTER TO BUFFER
+	RST	08			; DO IT
+;
+	; CONVERT ALL BYTES FROM BCD TO BINARY
+	LD	HL,CLKDAT		; BUFFER
+	LD	B,7			; DO 7 BYTES
+TIMDAT1:
+	LD	A,(HL)
+	CALL	BCD2BYTE
+	LD	(HL),A
+	INC	HL
+	DJNZ	TIMDAT1
+;
+	; SWAP BYTES 0 & 2 TO MAKE BUFFER INTO QP/M ORDER
+	LD	A,(CLKDAT+0)
+	PUSH	AF
+	LD	A,(CLKDAT+2)
+	LD	(CLKDAT+0),A
+	POP	AF
+	LD	(CLKDAT+2),A
+;
+	LD	HL,CLKDAT		; RETURN BUFFER ADDRESS
+	RET
+;
+  #ENDIF
+#ENDIF
+;
+;==================================================================================================
 ; CHARACTER DEVICE MAPPING
 ;==================================================================================================
 ;
@@ -346,11 +383,13 @@ BOOT:
 #ENDIF
 	CALL	RESCPM		; RESET CPM
 ;
-#IF DEBUG
+#IF AUTOSUBMIT
+  #IF DEBUG
 	CALL	PRTSTRD
 	.DB	"\r\nPerforming Auto Submit...$"
-#ENDIF
+  #ENDIF
 	CALL	AUTOSUB		; PREP AUTO SUBMIT, IF APPROPRIATE
+#ENDIF
 ;
 #IF DEBUG
 	CALL	PRTSTRD
@@ -393,6 +432,8 @@ WBOOT:
 #ENDIF
 ;
 #IFDEF PLTUNA
+	LD	SP,STACK		; STACK FOR INITIALIZATION
+
 	; RESTORE COMMAND PROCESSOR FROM UNA BIOS CACHE
 	LD	BC,$01FB		; UNA FUNC = SET BANK
 	LD	DE,(BNKBIOS)		; UBIOS_PAGE (SEE PAGES.INC)
@@ -1587,6 +1628,7 @@ LBA_IO:
 ;
 DSK_IO2:
 	PUSH	BC			; SAVE INCOMING FUNCTION, UNIT
+	RES	7,D			; CLEAR LBA BIT FOR UNA
 	LD	B,C			; UNIT TO B
 	LD	C,$41			; UNA SET LBA
 	RST	08			; CALL UNA
@@ -1718,6 +1760,12 @@ SLICE		.DB	0		; CURRENT SLICE
 SPS		.DW	0		; SECTORS PER SLICE
 STKSAV		.DW	0		; TEMP SAVED STACK POINTER
 ;
+#IFDEF PLTWBW
+  #IF QPMTIMDAT
+CLKDAT		.FILL	7,0		; RTC CLOCK DATA BUFFER
+  #ENDIF
+#ENDIF
+;
 #IFDEF PLTWBW
 BNKBIOS		.DB	0		; BIOS BANK ID
 BNKUSER		.DB	0		; USER BANK ID
@@ -2317,6 +2365,17 @@ INIT3:
 	LD	DE,STR_TPA2		; AND TPA SUFFIX
 	CALL	WRITESTR
 	CALL	NEWLINE			; FORMATTING
+;
+; SETUP QP/M TIMDAT ROUTINE VECTOR IN ZERO PAGE AT 0x0010
+;
+#IFDEF PLTWBW
+  #IF QPMTIMDAT
+	LD	A,$C3			; JP INSTRUCTION
+	LD	($0010),A		; STORE AT 0x0008
+	LD	HL,TIMDAT		; ROUTINE ADDRESS
+	LD	($0011),HL		; SET VECTOR
+  #ENDIF
+#ENDIF
 ;
 	RET				; DONE
 ;
@@ -2328,6 +2387,9 @@ ERR_BIOMEM:
 ;
 ;
 ;__________________________________________________________________________________________________
+;
+#IF AUTOSUBMIT
+;
 AUTOSUB:
 ;
 	; SETUP AUTO SUBMIT COMMAND (IF REQUIRED FILES EXIST)
@@ -2359,6 +2421,8 @@ AUTOSUB:
 	LDIR				; PATCH COMMAND LINE INTO CCP
 	RET				; DONE
 ;
+#ENDIF
+;
 ;
 ;__________________________________________________________________________________________________
 DEV_INIT:

Source/CBIOS/config.asm

@@ -2,6 +2,8 @@
 ; CBIOS BUILD CONFIGURATION OPTIONS
 ;
 CLRRAMDISK	.EQU	CLR_AUTO	; CLR_ALWAYS, CLR_NEVER, CLR_AUTO (CLEAR IF INVALID DIR AREA)
+AUTOSUBMIT	.EQU	TRUE		; PROCESS PROFILE.SUB AT STARTUP
+QPMTIMDAT	.EQU	TRUE		; SUPPORT QP/M TIMDAT ROUTINE
 WRTCACHE	.EQU	TRUE		; ENABLE WRITE CACHING IN CBIOS (DE)BLOCKING ALGORITHM
 DSKTRACE	.EQU	FALSE		; ENABLE TRACING OF CBIOS DISK FUNCTION CALLS
 DEBUG		.EQU	FALSE		; MISCELLANEOUS DEBUG TRACING

Source/CBIOS/util.asm

@@ -460,7 +460,52 @@ HEXCONV:
 	DAA	
 	ADC	A,40H
 	DAA	
-	RET	
+	RET
+;
+;****************************
+;	A(BCD) => A(BIN)
+;	[00H..99H] -> [0..99]
+;****************************
+;
+BCD2BYTE:
+	PUSH	BC
+	LD	C,A
+	AND	0F0H
+	SRL	A
+	LD	B,A
+	SRL	A
+	SRL	A
+	ADD	A,B
+	LD	B,A
+	LD	A,C
+	AND	0FH
+	ADD	A,B
+	POP	BC
+	RET
+;
+;*****************************
+;	 A(BIN) =>  A(BCD)
+;	[0..99] => [00H..99H]
+;*****************************
+;
+BYTE2BCD:
+	PUSH	BC
+	LD	B,10
+	LD	C,-1
+BYTE2BCD1:
+	INC	C
+	SUB	B
+	JR	NC,BYTE2BCD1
+	ADD	A,B
+	LD	B,A
+	LD	A,C
+	ADD	A,A
+	ADD	A,A
+	ADD	A,A
+	ADD	A,A
+	OR	B
+	POP	BC
+	RET
 ;
 ; PRINT A BYTE BUFFER IN HEX POINTED TO BY DE
 ; REGISTER A HAS SIZE OF BUFFER

Source/CPM3/Makefile

@@ -13,6 +13,7 @@ OTHERS = cpmldr.rel biosldr.rel cpm3res.sys cpm3bnk.sys loader.bin cpmldr.bin
 OTHERS += biosldrc.rel biosldrd.rel
 NODELETE = ccp.com gencpm.com genres.dat genbnk.dat bdos3.spr bnkbdos3.spr resbdos3.spr
 NODELETE += readme.1st cpm3fix.pat
+NODIFF = zpmbios3
 
 DEST = ../../Binary/CPM3
 TOOLS = ../../Tools

Source/Doc/Architecture.md

@@ -1399,7 +1399,7 @@ If the driver is able to generate the requested note, a success (0) is
 returned, otherwise a non-zero error state will be returned.
 
 The sound chip resolution and its oscillator limit the range and
-accuracy of the notes played. The typically range of the AY-3-8910
+accuracy of the notes played. The typical range of the AY-3-8910
 is six octaves, Bb2/A#2-A7, where each value is a unique tone. Values
 above and below can still be played but each quarter tone step may not
 result in a note change.
@@ -1409,18 +1409,18 @@ to the corresponding octave and note.
 
 | Note  | Oct 0 | Oct 1 | Oct 2 | Oct 3 | Oct 4 | Oct 5 | Oct 6 | Oct 7 |
 |:----- | -----:| -----:| -----:| -----:| -----:| -----:| -----:| -----:|
-| Bb/A# |   0   |   48  |  96   |  144  |  192  |  240  |  288  |  336  |
+| C     |   X   |   8   |   56  |  104  |  152  |  200  |  248  |  296  |
+| C#/Db |   X   |   12  |   60  |  108  |  156  |  204  |  252  |  300  |
+| D     |   X   |   16  |   64  |  112  |  160  |  208  |  256  |  304  |
+| D#/Eb |   X   |   20  |   68  |  116  |  164  |  212  |  260  |  308  |
+| E     |   X   |   24  |   72  |  120  |  168  |  216  |  264  |  312  |
+| F     |   X   |   28  |   76  |  124  |  172  |  220  |  268  |  316  |
+| F#/Gb |   X   |   32  |   80  |  128  |  176  |  224  |  272  |  320  |
+| G     |   X   |   36  |   84  |  132  |  180  |  228  |  276  |  324  |
+| G#/Ab |   X   |   40  |   88  |  136  |  184  |  232  |  280  |  328  |
+| A     |   X   |   44  |   92  |  140  |  188  |  236  |  284  |  332  |
+| A#/Bb |   0   |   48  |   96  |  144  |  192  |  240  |  288  |  336  |
 | B     |   4   |   52  |  100  |  148  |  196  |  244  |  292  |  340  |
-| C     |   8   |   56  |  104  |  152  |  200  |  248  |  296  |  344  |
-| C#/Db |   12  |   60  |  108  |  156  |  204  |  252  |  300  |  348  |
-| D     |   16  |   64  |  112  |  160  |  208  |  256  |  304  |  352  |
-| Eb/D# |   20  |   68  |  116  |  164  |  212  |  260  |  308  |  356  |
-| E     |   24  |   72  |  120  |  168  |  216  |  264  |  312  |  360  |
-| F     |   28  |   76  |  124  |  172  |  220  |  268  |  316  |  364  |
-| F#/Gb |   32  |   80  |  128  |  176  |  224  |  272  |  320  |  368  |
-| G     |   36  |   84  |  132  |  180  |  228  |  276  |  324  |  372  |
-| Ab/G# |   40  |   88  |  136  |  184  |  232  |  280  |  328  |  376  |
-| A     |   44  |   92  |  140  |  188  |  236  |  284  |  332  |  380  |
 
 ### Function 0x54 -- Sound Play (SNDPLAY)
 

Source/Fonts/fonts.txt

@@ -1,15 +1,36 @@
 Font files for ROMWBW.
 
-There are three fonts associated with ROMWBW supported hardware - ECB-SCG, ECB-CVDU and the ECB-VGA3.
+8x8: 8x8 cell, mostly IBM CGA, first 16 differ, thin font
+8x11: 8x11 cell, possibly VT-100?
+8x16: 8x16 cell, IBM MDA
+CGA: 8x16 cell, IBM CGA, normal (thick) CGA font, rows 8-15 are unused padding
 
-Name            Format      Size    Board & Display Mode
-------------------------------------------------------------------------------------
-font8x8u.bin    8x8         2048    ECB-SCG, ECB-VGA3 (80x60)     
-font8x11u.bin   8x11        2816    ECB-VGA3 (80x43)
-font8x16u.bin   8x16        4096    ECB-CVDU (80x25), ECB-VGA3 (80x24, 80x25, 80x30), MBC-VDC
-fontcgau.bin	8x8         4096    ECB-CVDU (80x25), MBC-VDC
+There are multiple fonts associated with ROMWBW supported hardware:
 
-For inclusion in HBIOS the .bin format files must be convert to assembler .asm format.
+	Board		Driver		Chip
+	--------	--------	--------
+	ECB-SCG		tms.asm		9918
+	ECB-VDU		vdu.asm		6545
+	ECB-CVDU	cvdu.asm	8563
+	ECB-VGA3	vga.asm		6445
+	MBC-VDC		cvdu.asm	8568
+	MBC-VDP		tms.asm		9938/9958
+
+Name            Font    Storage	    Size    Board & Display Mode
+--------------------------------------------------------------------------------------------
+font8x8u.bin    6x8     8x8         2048    ECB-SCG, ECB-VGA3 (80x60), MBC-VDP
+font8x11u.bin   8x11    8x11        2816    ECB-VGA3 (80x43)
+font8x16u.bin   8x14    8x16        4096    ECB-CVDU (80x25), ECB-VGA3 (80x24, 80x25, 80x30), MBC-VDC
+fontcgau.bin    8x8     8x16        4096    ECB-CVDU (80x25), MBC-VDC
+
+Notes:
+
+- The CGA font is roughly equivalent to the 8x8 font, but padded out to 8x16.  Scan lines
+  8-15 are unused.  The CVDU driver (8563 chip) always uses fonts defined in an 8x16 cell.
+  When the CVDU is configured for use with a CGA monitor, an 8x8 character cell is used,
+  but the font definition must still be 8x16.  The CGA font is used for this.
+
+For inclusion in HBIOS the .bin format files must be converted to assembler .asm format.
 This is acheived using the fonttool utility and is completed automatically as part of the build process.
 i.e. fonts files are converted to .asm format and then copied to the HBIOS directory. 
 

Source/HBIOS/Build.cmd

@@ -4,7 +4,7 @@ setlocal
 if "%1" == "dist" goto :dist
 
 ::
-:: Build [<platform> [<config> [<romsize> [<romname>]]]]
+:: Build [<platform> [<config> [<romname>]]]
 ::
 
 set TOOLS=../../Tools
@@ -28,11 +28,21 @@ PowerShell -ExecutionPolicy Unrestricted .\Build.ps1 %* || exit /b
 ::
 :: Below, we process the command file created by the PowerShell script.
 :: This sets the environment variables: Platform, Config, ROMName,
-:: ROMSize, & CPUType.
+:: & CPUType.
 ::
 
 call build_env.cmd
 
+::
+:: Create a small app that is used to export key build variables of the build.
+:: Then run the app to output a file with the variables.  Finally, read the
+:: file into variables usable in this batch file.
+::
+
+tasm -t80 -g3 -dCMD hbios_env.asm hbios_env.com hbios_env.lst || exit /b
+zxcc hbios_env >hbios_env.cmd
+call hbios_env.cmd
+
 ::
 :: Start of the actual build process for a given ROM.
 ::
@@ -183,33 +193,34 @@ goto :eof
 
 :dist
 
-call Build SBC std 512 || exit /b
-call Build SBC simh 512 || exit /b
-call Build MBC std 512 || exit /b
-call Build ZETA std 512 || exit /b
-call Build ZETA2 std 512 || exit /b
-call Build N8 std 512 || exit /b
-call Build MK4 std 512 || exit /b
-call Build RCZ80 std 512 || exit /b
-call Build RCZ80 skz 512 || exit /b
-call Build RCZ80 kio 512 || exit /b
-call Build RCZ80 mt 512 || exit /b
-call Build RCZ80 duart 512 || exit /b
-call Build RCZ80 zrc 512 || exit /b
-call Build RCZ80 zrc_ram 0 || exit /b
-call Build RCZ180 ext 512 || exit /b
-call Build RCZ180 nat 512 || exit /b
-call Build RCZ280 ext 512 || exit /b
-call Build RCZ280 nat 512 || exit /b
-call Build RCZ280 nat_zz 512 || exit /b
-call Build RCZ280 nat_zzr 256 || exit /b
-call Build SCZ180 126 512 || exit /b
-call Build SCZ180 130 512 || exit /b
-call Build SCZ180 131 512 || exit /b
-call Build SCZ180 140 512 || exit /b
-call Build EZZ80 std 512 || exit /b
-call Build EZZ80 tz80 512 || exit /b
-call Build DYNO std 512 || exit /b
-call Build UNA std 512 || exit /b
+call Build SBC std || exit /b
+call Build SBC simh || exit /b
+call Build MBC std || exit /b
+call Build ZETA std || exit /b
+call Build ZETA2 std || exit /b
+call Build N8 std || exit /b
+call Build MK4 std || exit /b
+call Build RCZ80 std || exit /b
+call Build RCZ80 skz || exit /b
+call Build RCZ80 kio || exit /b
+call Build RCZ80 mt || exit /b
+call Build RCZ80 duart || exit /b
+call Build RCZ80 zrc || exit /b
+call Build RCZ80 zrc_ram || exit /b
+call Build RCZ180 ext || exit /b
+call Build RCZ180 nat || exit /b
+call Build RCZ280 ext || exit /b
+call Build RCZ280 nat || exit /b
+call Build RCZ280 nat_zz || exit /b
+call Build RCZ280 nat_zzr || exit /b
+call Build SCZ180 126 || exit /b
+call Build SCZ180 130 || exit /b
+call Build SCZ180 131 || exit /b
+call Build SCZ180 140 || exit /b
+call Build EZZ80 std || exit /b
+call Build EZZ80 tz80 || exit /b
+call Build DYNO std || exit /b
+call Build UNA std || exit /b
+call Build RPH std || exit /b
 
 goto :eof

Source/HBIOS/Build.ps1

@@ -1,4 +1,4 @@
-param([string]$Platform = "", [string]$Config = "", [int]$RomSize = 512, [string]$ROMName = "")
+param([string]$Platform = "", [string]$Config = "", [string]$ROMName = "")
 
 # If a PowerShell exception occurs, just stop the script immediately.
 $ErrorAction = 'Stop'
@@ -28,7 +28,7 @@ $ErrorAction = 'Stop'
 #
 
 $PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "EZZ80", "UNA"
-$PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO"
+$PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO", "RPH"
 $PlatformListZ280 = "RCZ280"
 
 #
@@ -67,19 +67,6 @@ while ($true)
 	$Config = (Read-Host -prompt "Configuration").Trim()
 }
 
-#
-# Establish the ROM size (in KB).  It may have been passed in on the command line.  Validate
-# $RomSize and loop requesting a new value as long as it is not valid.  The valid ROM sizes
-# are just hard-coded for now.  The ROM size does nothing more than determine the size of the
-# ROM disk portion of the ROM image.
-#
-
-while ($true)
-{
-	if (($RomSize -eq 0) -or ($RomSize -eq 128) -or ($RomSize -eq 256) -or ($RomSize -eq 512) -or ($RomSize -eq 1024)) {break}
-	$RomSize = (Read-Host -prompt "ROM Size [0|128|256|512|1024]").Trim()
-}
-
 #
 # TASM should be invoked with the proper CPU type.  Below, the CPU type is inferred
 # from the platform.
@@ -103,7 +90,7 @@ while ($ROMName -eq "")
 }
 
 # Current date/time is queried here to be subsequently imbedded in image
-$TimeStamp = '"' + (Get-Date -Format 'yyyy-MM-dd') + '"'
+$TimeStamp = (Get-Date -Format 'yyyy-MM-dd')
 
 #
 # Since TASM has no mechanism to include files dynamically based on variables, a file
@@ -115,9 +102,8 @@ $TimeStamp = '"' + (Get-Date -Format 'yyyy-MM-dd') + '"'
 @"
 ; RomWBW Configured for ${Platform} ${Config}, $(Get-Date -Format "s")
 ;
-#DEFINE		TIMESTAMP	${TimeStamp}
-;
-ROMSIZE		.EQU		${ROMSize}
+#DEFINE		TIMESTAMP	"${TimeStamp}"
+#DEFINE		CONFIG		"${Platform}_${Config}"
 ;
 #INCLUDE "${ConfigFile}"
 ;
@@ -134,6 +120,5 @@ ROMSIZE		.EQU		${ROMSize}
 set Platform=${Platform}
 set Config=${Config}
 set ROMName=${ROMName}
-set ROMSize=${ROMSize}
 set CPUType=${CPUType}
 "@ | Out-File "build_env.cmd" -Encoding ASCII

Source/HBIOS/Build.sh

@@ -6,50 +6,42 @@ set -e
 export ROM_PLATFORM
 export ROM_CONFIG
 export ROMSIZE
+export CPUFAM
 
 if [ "${ROM_PLATFORM}" == "dist" ] ; then
 	echo "!!!DISTRIBUTION BUILD!!!"
-	ROM_PLATFORM="DYNO"; ROM_CONFIG="std"; ROMSIZE="512"; bash Build.sh
-	ROM_PLATFORM="EZZ80"; ROM_CONFIG="std"; ROMSIZE="512"; bash Build.sh
-	ROM_PLATFORM="EZZ80"; ROM_CONFIG="tz80"; ROMSIZE="512"; bash Build.sh
-	ROM_PLATFORM="MK4"; ROM_CONFIG="std"; ROMSIZE="512"; bash Build.sh
-	ROM_PLATFORM="N8"; ROM_CONFIG="std"; ROMSIZE="512"; bash Build.sh
-	ROM_PLATFORM="RCZ180"; ROM_CONFIG="ext"; ROMSIZE="512"; bash Build.sh
-	ROM_PLATFORM="RCZ180"; ROM_CONFIG="nat"; ROMSIZE="512"; bash Build.sh
-	ROM_PLATFORM="RCZ280"; ROM_CONFIG="ext"; ROMSIZE="512"; bash Build.sh
-	ROM_PLATFORM="RCZ280"; ROM_CONFIG="nat"; ROMSIZE="512"; bash Build.sh
-	ROM_PLATFORM="RCZ280"; ROM_CONFIG="nat_zz"; ROMSIZE="512"; bash Build.sh
-	ROM_PLATFORM="RCZ280"; ROM_CONFIG="nat_zzr"; ROMSIZE="256"; bash Build.sh
-	ROM_PLATFORM="RCZ80"; ROM_CONFIG="kio"; ROMSIZE="512"; bash Build.sh
-	ROM_PLATFORM="RCZ80"; ROM_CONFIG="mt"; ROMSIZE="512"; bash Build.sh
-	ROM_PLATFORM="RCZ80"; ROM_CONFIG="duart"; ROMSIZE="512"; bash Build.sh
-	ROM_PLATFORM="RCZ80"; ROM_CONFIG="std"; ROMSIZE="512"; bash Build.sh
-	ROM_PLATFORM="RCZ80"; ROM_CONFIG="skz"; ROMSIZE="512"; bash Build.sh
-	ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc"; ROMSIZE="512"; bash Build.sh
-	ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc_ram"; ROMSIZE="0"; bash Build.sh
-	ROM_PLATFORM="SBC"; ROM_CONFIG="std"; ROMSIZE="512"; bash Build.sh
-	ROM_PLATFORM="SBC"; ROM_CONFIG="simh"; ROMSIZE="512"; bash Build.sh
-	ROM_PLATFORM="MBC"; ROM_CONFIG="std"; ROMSIZE="512"; bash Build.sh
-	ROM_PLATFORM="SCZ180"; ROM_CONFIG="126"; ROMSIZE="512"; bash Build.sh
-	ROM_PLATFORM="SCZ180"; ROM_CONFIG="130"; ROMSIZE="512"; bash Build.sh
-	ROM_PLATFORM="SCZ180"; ROM_CONFIG="131"; ROMSIZE="512"; bash Build.sh
-	ROM_PLATFORM="SCZ180"; ROM_CONFIG="140"; ROMSIZE="512"; bash Build.sh
-	ROM_PLATFORM="UNA"; ROM_CONFIG="std"; ROMSIZE="512"; bash Build.sh
-	ROM_PLATFORM="ZETA"; ROM_CONFIG="std"; ROMSIZE="512"; bash Build.sh
-	ROM_PLATFORM="ZETA2"; ROM_CONFIG="std"; ROMSIZE="512"; bash Build.sh
+	ROM_PLATFORM="DYNO"; ROM_CONFIG="std"; bash Build.sh
+	ROM_PLATFORM="EZZ80"; ROM_CONFIG="std"; bash Build.sh
+	ROM_PLATFORM="EZZ80"; ROM_CONFIG="tz80"; bash Build.sh
+	ROM_PLATFORM="MK4"; ROM_CONFIG="std"; bash Build.sh
+	ROM_PLATFORM="N8"; ROM_CONFIG="std"; bash Build.sh
+	ROM_PLATFORM="RCZ180"; ROM_CONFIG="ext"; bash Build.sh
+	ROM_PLATFORM="RCZ180"; ROM_CONFIG="nat"; bash Build.sh
+	ROM_PLATFORM="RCZ280"; ROM_CONFIG="ext"; bash Build.sh
+	ROM_PLATFORM="RCZ280"; ROM_CONFIG="nat"; bash Build.sh
+	ROM_PLATFORM="RCZ280"; ROM_CONFIG="nat_zz"; bash Build.sh
+	ROM_PLATFORM="RCZ280"; ROM_CONFIG="nat_zzr"; bash Build.sh
+	ROM_PLATFORM="RCZ80"; ROM_CONFIG="kio"; bash Build.sh
+	ROM_PLATFORM="RCZ80"; ROM_CONFIG="mt"; bash Build.sh
+	ROM_PLATFORM="RCZ80"; ROM_CONFIG="duart"; bash Build.sh
+	ROM_PLATFORM="RCZ80"; ROM_CONFIG="std"; bash Build.sh
+	ROM_PLATFORM="RCZ80"; ROM_CONFIG="skz"; bash Build.sh
+	ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc"; bash Build.sh
+	ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc_ram"; bash Build.sh
+	ROM_PLATFORM="RPH"; ROM_CONFIG="std"; bash Build.sh
+	ROM_PLATFORM="SBC"; ROM_CONFIG="std"; bash Build.sh
+	ROM_PLATFORM="SBC"; ROM_CONFIG="simh"; bash Build.sh
+	ROM_PLATFORM="MBC"; ROM_CONFIG="std"; bash Build.sh
+	ROM_PLATFORM="SCZ180"; ROM_CONFIG="126"; bash Build.sh
+	ROM_PLATFORM="SCZ180"; ROM_CONFIG="130"; bash Build.sh
+	ROM_PLATFORM="SCZ180"; ROM_CONFIG="131"; bash Build.sh
+	ROM_PLATFORM="SCZ180"; ROM_CONFIG="140"; bash Build.sh
+	ROM_PLATFORM="UNA"; ROM_CONFIG="std"; bash Build.sh
+	ROM_PLATFORM="ZETA"; ROM_CONFIG="std"; bash Build.sh
+	ROM_PLATFORM="ZETA2"; ROM_CONFIG="std"; bash Build.sh
 	exit
 fi
 
-###if [ $1 == '-d' ] ; then
-###	shift
-###	diffdir=$1
-###	shift
-###	if [ -f $diffdir/build.inc ] ; then
-###		timestamp=$(grep TIMESTAMP $diffdir/build.inc | awk '{print $3}' | tr -d '\015"')
-###		echo diff build using $timestamp
-###	fi
-###fi
-
 # prompt if no match
 platforms=($(find Config -name \*.asm -print | \
 	sed -e 's,Config/,,' -e 's/_.*$//' | sort -u))
@@ -68,36 +60,41 @@ done
 
 CONFIGFILE=Config/${ROM_PLATFORM}_${ROM_CONFIG}.asm
 
-if [ -z "${ROMSIZE}" ] ; then
-	ROMSIZE="512"
-fi
-
-while [ ! '(' "${ROMSIZE}" = 1024 -o "${ROMSIZE}" = 512 -o "${ROMSIZE}" = 256 -o "${ROMSIZE}" = 128 -o "${ROMSIZE}" = 0 ')' ] ; do
-	echo -n "Romsize :"
-	read ROMSIZE
-done
-
 if [ -z "${ROMNAME}" ] ; then
 	ROMNAME=${ROM_PLATFORM}_${ROM_CONFIG}
 fi
 
+echo -e "\n\nBuilding $ROM_PLATFORM $ROM_CONFIG\n\n"
+
 TIMESTAMP=$(date +%Y-%m-%d)
 
-CONFIGFILE=Config/${ROM_PLATFORM}_${ROM_CONFIG}.asm
+if [ "$1" = "-d" ] ; then
+	shift
+	diffdir=$1
+	shift
+	if [ -f $diffdir/build.inc ] ; then
+		timestamp=$(grep TIMESTAMP $diffdir/build.inc | awk '{print $3}' | tr -d '\015"')
+		echo diff build using $timestamp
+	fi
+fi
 
-echo Building $ROMNAME for $ROM_PLATFORM $ROM_CONFIG $ROMSIZE
+CONFIGFILE=Config/${ROM_PLATFORM}_${ROM_CONFIG}.asm
 
 cat <<- EOF > build.inc
 ; RomWBW Configured for ${ROM_PLATFORM} ${ROM_CONFIG} ${TIMESTAMP}
 ;
 #DEFINE	TIMESTAMP	"${TIMESTAMP}"
-;
-ROMSIZE		.EQU	${ROMSIZE}
+#DEFINE CONFIG		"${ROM_PLATFORM}_${ROM_CONFIG}"
 ;
 #INCLUDE "${CONFIGFILE}"
 ;
 EOF
 
+make hbios_env.sh
+source hbios_env.sh
+
+echo Creating ${ROMSIZE}K ROM named ${ROMNAME}.rom
+
 export OBJECTS
 OBJECTS="${ROMNAME}.rom"
 if [ "${ROM_PLATFORM}" != "UNA" ] ; then

Source/HBIOS/Clean.cmd

@@ -14,3 +14,4 @@ if exist *.sys del *.sys
 if exist build.inc del build.inc
 if exist font*.asm del font*.asm
 if exist build_env.cmd del build_env.cmd
+if exist hbios_env.cmd del hbios_env.cmd

Source/HBIOS/Config/EZZ80_tz80.asm

@@ -22,8 +22,6 @@
 ; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
 ; DIRECTORIES ABOVE THIS ONE).
 ;
-#DEFINE PLATFORM_NAME "TINYZ80"
-;
 #include "cfg_ezz80.asm"
 ;
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP

Source/HBIOS/Config/MBC_std.asm

@@ -22,7 +22,6 @@
 ; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
 ; DIRECTORIES ABOVE THIS ONE).
 ;
-#DEFINE PLATFORM_NAME "Multi Board Computer"
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;
 #include "cfg_mbc.asm"

Source/HBIOS/Config/RCZ280_nat_zz.asm

@@ -22,8 +22,6 @@
 ; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
 ; DIRECTORIES ABOVE THIS ONE).
 ;
-#DEFINE	PLATFORM_NAME	"ZZ80MB"
-;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;
 #include "Config/RCZ280_nat.asm"

Source/HBIOS/Config/RCZ280_nat_zzr.asm

@@ -22,8 +22,6 @@
 ; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
 ; DIRECTORIES ABOVE THIS ONE).
 ;
-#DEFINE	PLATFORM_NAME	"ZZRCC"
-;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;
 #include "Config/RCZ280_nat.asm"
@@ -31,6 +29,7 @@
 CPUOSC		.SET	14745600	; CPU OSC FREQ IN MHZ
 ;
 RAMSIZE		.SET	256		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.SET	256		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE_CHK	.SET	256		; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
 ;
 RAMLOC		.SET	18		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE

Source/HBIOS/Config/RCZ80_duart.asm

@@ -24,8 +24,6 @@
 ;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;
-#DEFINE	PLATFORM_NAME	"RC2014 (DUART)"
-;
 #include "Config/RCZ80_std.asm"
 ;
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP

Source/HBIOS/Config/RCZ80_kio.asm

@@ -22,8 +22,6 @@
 ; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
 ; DIRECTORIES ABOVE THIS ONE).
 ;
-#DEFINE	PLATFORM_NAME	"RC2014 (KIO)"
-;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;
 #include "Config/RCZ80_std.asm"

Source/HBIOS/Config/RCZ80_mt.asm

@@ -24,8 +24,6 @@
 ;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;
-#DEFINE	PLATFORM_NAME	"RC2014 (MT)"
-;
 #include "Config/RCZ80_std.asm"
 ;
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP

Source/HBIOS/Config/RCZ80_skz.asm

@@ -22,8 +22,6 @@
 ; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
 ; DIRECTORIES ABOVE THIS ONE).
 ;
-#DEFINE	PLATFORM_NAME	"RC2014 (SKZ)"
-;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;
 #include "Config/RCZ80_std.asm"

Source/HBIOS/Config/RCZ80_zrc_ram.asm

@@ -31,6 +31,7 @@ CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 CPUOSC		.SET	7372800		; CPU OSC FREQ IN MHZ
 ;
 RAMSIZE		.SET	2048		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.SET	0		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
 MEMMGR		.SET	MM_ZRC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
 ;
 MDROM		.SET	FALSE		; MD: ENABLE ROM DISK

Source/HBIOS/Config/RPH_std.asm

@@ -0,0 +1,41 @@
+;
+;==================================================================================================
+;   RHYOPHYRE STANDARD CONFIGURATION
+;==================================================================================================
+;
+; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
+; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
+; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
+; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
+; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
+; YOUR FILE IN THE BUILD PROCESS.
+;
+; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
+; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
+; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
+; SETTINGS.
+;
+; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
+; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
+; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
+; DIRECTORIES ABOVE THIS ONE).
+;
+#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
+;
+#include "cfg_rph.asm"
+;
+CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
+;
+INTMODE		.SET	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+;
+Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
+Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+;
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+;
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+;
+PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)

Source/HBIOS/Config/SBC_simh.asm

@@ -24,8 +24,6 @@
 ;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;
-#DEFINE		PLATFORM_NAME	"SBC (simh)"
-;
 #include "cfg_sbc.asm"
 ;
 INTMODE		.SET	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2

Source/HBIOS/Config/SCZ180_126.asm

@@ -22,8 +22,6 @@
 ; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
 ; DIRECTORIES ABOVE THIS ONE).
 ;
-#DEFINE	PLATFORM_NAME	"SC126"
-;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;
 #include "cfg_scz180.asm"

Source/HBIOS/Config/SCZ180_130.asm

@@ -22,8 +22,6 @@
 ; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
 ; DIRECTORIES ABOVE THIS ONE).
 ;
-#DEFINE	PLATFORM_NAME	"SC130"
-;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;
 #include "cfg_scz180.asm"

Source/HBIOS/Config/SCZ180_131.asm

@@ -22,8 +22,6 @@
 ; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
 ; DIRECTORIES ABOVE THIS ONE).
 ;
-#DEFINE	PLATFORM_NAME	"SC131"
-;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;
 #include "cfg_scz180.asm"

Source/HBIOS/Config/SCZ180_140.asm

@@ -22,8 +22,6 @@
 ; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
 ; DIRECTORIES ABOVE THIS ONE).
 ;
-#DEFINE		PLATFORM_NAME	"SC140"
-;
 #include "cfg_scz180.asm"
 ;
 CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ

Source/HBIOS/Makefile

@@ -1,30 +1,36 @@
 
-MOREDIFF = camel80.bin game.bin hbios_rom.bin nascom.bin prefix.bin usrrom.bin \
+MOREDIFF = game.bin hbios_rom.bin nascom.bin usrrom.bin \
 	dbgmon.bin hbios_app.bin imgpad2.bin osimg1.bin osimg2.bin romldr.bin \
-	eastaegg.bin hbios_img.bin osimg.bin tastybasic.bin \
-	game.bin updater.bin usrrom.bin
+	eastaegg.bin hbios_img.bin osimg.bin game.bin updater.bin usrrom.bin
 
 SUBDIRS =
 DEST = ../../Binary
 TOOLS =../../Tools
-OTHERS =  *.img *.rom *.com *.upd *.bin *.z80 cpm.sys zsys.sys Build.inc font*.asm *.dat
-include $(TOOLS)/Makefile.inc
+OTHERS =  *.img *.rom *.com *.upd *.bin *.z80 cpm.sys zsys.sys Build.inc font*.asm *.dat hbios_env.sh
 
-FONTS := font8x11c.asm font8x11u.asm font8x16c.asm font8x16u.asm font8x8c.asm font8x8u.asm fontcgac.asm fontcgau.asm
+# DIFFMAKE = 1
 
-ifneq ($(findstring $(ROM_PLATFORM), N8 MK4 RCZ180 SCZ180 DYNO),)
-	TASM=$(BINDIR)/uz80as -t hd64180
-endif
-
-ifneq ($(findstring $(ROM_PLATFORM), RCZ280),)
-	TASM=$(BINDIR)/uz80as -t z280
-endif
+# DIFFPATH = $(DIFFTO)/Binary
 
 ifeq ($(DIFFMAKE),1)
 	DIFFBUILD := -d $(DIFFTO)/Source/HBIOS
 endif
 
-DIFFPATH = $(DIFFTO)/Binary
+ifeq ($(OBJECTS),)
+start:
+	chmod +x Build.sh
+	bash Build.sh $(DIFFBUILD)
+endif
+
+include $(TOOLS)/Makefile.inc
+
+FONTS := font8x11c.asm font8x11u.asm font8x16c.asm font8x16u.asm font8x8c.asm font8x8u.asm fontcgac.asm fontcgau.asm
+
+ifeq ($(CPUFAM),2)
+	TASM=$(BINDIR)/uz80as -t hd64180
+else ifeq ($(CPUFAM),3)
+	TASM=$(BINDIR)/uz80as -t z280
+endif
 
 DEPS=prereq dbgmon.bin romldr.bin nascom.bin tastybasic.bin game.bin eastaegg.bin updater.bin usrrom.bin imgpad2.bin
 
@@ -38,19 +44,15 @@ endif
 
 ROMNAME=${ROM_PLATFORM}_${ROM_CONFIG}
 
-#$(info DEPS=$(DEPS))
-#$(info ROM_PLATFORM=$(ROM_PLATFORM))
-#$(info ROM_CONFIG=$(ROM_CONFIG))
-#$(info ROMSIZE=$(ROMSIZE))
-#$(info ROMNAME=$(ROMNAME))
+# $(info DEPS=$(DEPS))
+# $(info ROM_PLATFORM=$(ROM_PLATFORM))
+# $(info ROM_CONFIG=$(ROM_CONFIG))
+# $(info ROMSIZE=$(ROMSIZE))
+# $(info ROMNAME=$(ROMNAME))
+# $(info CPUFAM=$(CPUFAM))
+# $(info TASM=$(TASM))
 
-all::
-	if [ -z "$(OBJECTS)" ] ; then \
-		chmod +x Build.sh ; \
-		bash Build.sh ; \
-	fi
-
-$(ROMNAME).rom $(ROMNAME).com $(ROMNAME).img &: $(ROMDEPS)
+$(OBJECTS) : $(ROMDEPS)
 	cat romldr.bin dbgmon.bin ../ZSDOS/zsys_$(BIOS).bin ../CPM22/cpm_$(BIOS).bin >osimg.bin
 	cat romldr.bin dbgmon.bin ../ZSDOS/zsys_$(BIOS).bin >osimg_small.bin
 	if [ $(ROM_PLATFORM) != UNA ] ; then \
@@ -98,6 +100,12 @@ hbios_app.bin:	hbios.asm build.inc  $(DEPS)
 hbios_img.bin:	hbios.asm build.inc  $(DEPS)
 	$(TASM) -dIMGBOOT hbios.asm hbios_img.bin hbios_img.lst
 
+hbios_env.com:	hbios_env.asm build.inc
+	$(TASM) -dBASH hbios_env.asm hbios_env.com hbios_env.lst
+	
+hbios_env.sh: hbios_env.com
+	$(ZXCC) hbios_env.com >hbios_env.sh
+
 romldr.bin:	build.inc
 dbgmon.bin:	build.inc
 nascom.bin:	build.inc

Source/HBIOS/ansi.asm

@@ -280,6 +280,8 @@ ANSI_STSTR:	; STATE == STRING DATA
 ;==================================================================================================
 ;
 ANSI_C0DISP:
+	CP	$07		; BEL
+	JP	Z,ANSI_BEL
 	CP	$08		; BS: BACKSPACE
 	JP	Z,ANSI_BS
 	CP	$09		; HT: TAB
@@ -615,6 +617,9 @@ ANSI_FF:
 	CALL	ANSI_VDADISP	; PERFORM FILL
 	JP	ANSI_XY		; HOME CURSOR AND RETURN
 ;
+ANSI_BEL:
+	JP	SND_BEEP	; BEEP THE SPEAKER
+;
 ANSI_BS:
 	LD	A,(ANSI_COL)	; GET CURRENT COLUMN
 	DEC	A		; BACK IT UP BY ONE

Source/HBIOS/asci.asm

@@ -75,10 +75,14 @@ ASCI1_BASE	.EQU	Z180_BASE + 1	; RELATIVE TO Z180 INTERNAL IO PORTS
 ;
 ASCI_RTS	.EQU	%00010000	; ~RTS BIT OF CNTLA REG
 ;
-#IF (INTMODE == 2)
+#IF (ASCIINTS)
+;
+  #IF (INTMODE == 2)
 ;
 ASCI0_IVT	.EQU	IVT(INT_SER0)
 ASCI1_IVT	.EQU	IVT(INT_SER1)
+;
+  #ENDIF
 ;
 #ENDIF
 ;
@@ -115,25 +119,29 @@ ASCI_PREINIT2:
 	ADD	IY,DE			; BUMP IY TO NEXT ENTRY
 	DJNZ	ASCI_PREINIT0		; LOOP UNTIL DONE
 ;
-#IF (INTMODE >= 1)
+#IF (ASCIINTS)
+;
+  #IF (INTMODE >= 1)
 	; SETUP INT VECTORS AS APPROPRIATE
 	LD	A,(ASCI_DEV)		; GET DEVICE COUNT
 	OR	A			; SET FLAGS
 	JR	Z,ASCI_PREINIT3		; IF ZERO, NO ASCI DEVICES, ABORT
 ;
-#IF (INTMODE == 1)
+    #IF (INTMODE == 1)
 	; ADD IM1 INT CALL LIST ENTRY
 	LD	HL,ASCI_INT		; GET INT VECTOR
 	CALL	HB_ADDIM1		; ADD TO IM1 CALL LIST
-#ENDIF
+    #ENDIF
 ;
-#IF (INTMODE == 2)
+    #IF (INTMODE == 2)
 	; SETUP IM2 VECTORS
 	LD	HL,ASCI_INT0
 	LD	(ASCI0_IVT),HL		; IVT INDEX
 	LD	HL,ASCI_INT1
 	LD	(ASCI1_IVT),HL		; IVT INDEX
-#ENDIF
+    #ENDIF
+;
+  #ENDIF
 ;
 #ENDIF
 ;
@@ -188,7 +196,9 @@ ASCI_INIT1:
 ;
 ; RECEIVE INTERRUPT HANDLER
 ;
-#IF (INTMODE > 0)
+#IF (ASCIINTS)
+;
+  #IF (INTMODE > 0)
 ;
 ; IM1 ENTRY POINT
 ;
@@ -232,10 +242,10 @@ ASCI_INTRCV1:
 	ADD	A,8			; BUMP TO RDR PORT
 	LD	C,A			; PUT IN C, B IS STILL ZERO
 	IN	A,(C)			; READ PORT
-  #IF (ASCIBOOT != 0)
+    #IF (ASCIBOOT != 0)
 	CP	ASCIBOOT		; REBOOT REQUEST?
 	JP	Z,SYS_RESCOLD		; IF SO, DO IT, NO RETURN
-  #ENDIF
+    #ENDIF
 	LD	B,A			; SAVE BYTE READ
 	LD	L,(IY+6)		; SET HL TO
 	LD	H,(IY+7)		; ... START OF BUFFER STRUCT
@@ -292,6 +302,8 @@ ASCI_INTRCV3:
 ASCI_INTRCV4:
 	OR	$FF			; NZ SET TO INDICATE INT HANDLED
 	RET				; AND RETURN
+;
+  #ENDIF
 ;
 #ENDIF
 ;
@@ -309,7 +321,7 @@ ASCI_FNTBL:
 	.ECHO	"*** INVALID ASCI FUNCTION TABLE ***\n"
 #ENDIF
 ;
-#IF (INTMODE == 0)
+#IF ((!ASCIINTS) | (INTMODE == 0))
 ;
 ASCI_IN:
 	CALL	ASCI_IST		; CHECK FOR CHAR READY
@@ -395,7 +407,7 @@ ASCI_OUT:
 ;
 ;
 ;
-#IF (INTMODE == 0)
+#IF ((!ASCIINTS) | (INTMODE == 0))
 ;
 ASCI_IST:
 	CALL	ASCI_ICHK		; ASCI INPUT CHECK
@@ -522,7 +534,7 @@ ASCI_INITGO:
 	OUT	(C),L			; WRITE CNTLB VALUE
 	INC	C			; BUMP TO
 	INC	C			; ... STAT REG, B IS STILL 0
-#IF (INTMODE > 0)
+#IF ((ASCIINTS) & (INTMODE > 0))
 	LD	A,$08			; SET RIE BIT ON
 #ELSE
 	XOR	A			; CLEAR RIE/TIE
@@ -534,7 +546,7 @@ ASCI_INITGO:
 	LD	A,$66			; STATIC VALUE FOR ASEXT
 	OUT	(C),A			; WRITE ASEXT REG
 ;
-#IF (INTMODE > 0)
+#IF ((ASCIINTS) & (INTMODE > 0))
 ;
 	; RESET THE RECEIVE BUFFER
 	LD	E,(IY+6)
@@ -609,6 +621,24 @@ ASCI_DETECT:
 ; DUE TO ENCODING BAUD IS ALWAYS DIVISIBLE BY 75
 ; Z180 DIVISOR IS ALWAYS A FACTOR OF 160
 ;
+; CNTLB=	XXPXDSSS
+; FAILSAVE = 	00100000
+;
+; PS (PRESCALE): 0=/10, 1=/30
+; DR (DIVIDE RATIO): 0=/16, 1=/64
+; SS2	SS1	SS0
+; ---	---	---
+; 0	0	0	/1
+; 0	0	1	/2
+; 0	1	0	/4
+; 0	1	1	/8
+; 1	0	0	/16
+; 1	0	1	/32
+; 1	1	0	/64
+;
+; FAILSAFE: CLOCK / 30 / 16 / 1 = CLOCK / 480
+;	IF CLOCK=18432000, BAUD=38400
+;
 ; X := CPU_HZ / 160 / 75 ==> SIMPLIFIED ==> X := CPU_KHZ / 12
 ; X := X / (BAUD / 75)
 ; IF X % 3 == 0, THEN (PS := 1, X := X / 3) ELSE PS=0
@@ -769,7 +799,7 @@ ASCI_STR_ASCIB	.DB	"ASCI W/BRG$"
 ;
 ASCI_DEV	.DB	0		; DEVICE NUM USED DURING INIT
 ;
-#IF (INTMODE == 0)
+#IF ((!ASCIINTS) | (INTMODE == 0))
 ;
 ASCI0_RCVBUF	.EQU	0
 ASCI1_RCVBUF	.EQU	0

Source/HBIOS/ay38910.asm

@@ -327,7 +327,8 @@ AY_NOTE:
 	LD	H, (HL)			; SO WE CAN UPDATE IT FOR THE REQUIRED OCTAVE
 	LD	L, A
 ;
-	LD	A,AY_SCALE-1		; THE NOTE TABLE PERIOD DATA HAS BEEN
+	;LD	A,AY_SCALE - 1		; THE NOTE TABLE PERIOD DATA HAS BEEN
+	LD	A,AY_SCALE		; THE NOTE TABLE PERIOD DATA HAS BEEN
 	ADD	A,C			; PRESCALED TO MAINTAIN RANGE SO ALLOW
 	LD	B,A			; FOR THIS WHEN CHANGING OCTAVE
 AY_NOTE1:
@@ -534,7 +535,7 @@ AY_EI:
 AY_WRTPSG:
 	CALL	AY_DI
 #IFDEF SBCV2004
-	LD	A,(RTCVAL)		; GET CURRENT RTC LATCH VALUE
+	LD	A,(HB_RTCVAL)		; GET CURRENT RTC LATCH VALUE
 	OR	%00001000		; SBC-V2-004 CHANGE
 	OUT	(RTCIO),A		; TO HALF CLOCK SPEED
 #ENDIF
@@ -553,7 +554,7 @@ AY_WRTPSG:
 	OUT0	(Z180_DCNTL),A		; AND RESTORE IT
 #ENDIF
 #IFDEF SBCV2004
-	LD	A,(RTCVAL)		; SBC-V2-004 CHANGE TO
+	LD	A,(HB_RTCVAL)		; SBC-V2-004 CHANGE TO
 	OUT	(RTCIO),A		; NORMAL CLOCK SPEED
 #ENDIF
 	JP	AY_EI
@@ -565,7 +566,7 @@ AY_WRTPSG:
 AY_RDPSG:
 	CALL	AY_DI
 #IFDEF SBCV2004
-	LD	A,(RTCVAL)		; GET CURRENT RTC LATCH VALUE
+	LD	A,(HB_RTCVAL)		; GET CURRENT RTC LATCH VALUE
 	OR	%00001000		; SBC-V2-004 CHANGE
 	OUT	(RTCIO),A		; TO HALF CLOCK SPEED
 #ENDIF
@@ -584,7 +585,7 @@ AY_RDPSG:
 	OUT0	(Z180_DCNTL),A		; AND RESTORE IT
 #ENDIF
 #IFDEF SBCV2004
-	LD	A,(RTCVAL)		; SBC-V2-004 CHANGE TO
+	LD	A,(HB_RTCVAL)		; SBC-V2-004 CHANGE TO
 	OUT	(RTCIO),A		; NORMAL CLOCK SPEED
 #ENDIF
 	JP	AY_EI
@@ -617,51 +618,51 @@ AYT_REGWR		.DB	"\r\nOUT AY-3-8910 $"
 ; ASSUMING A CLOCK OF 1843200 THIS MAPS TO A0#
 ;
 AY3NOTETBL:
-	.DW	AY_RATIO / 2913
-	.DW	AY_RATIO / 2956
-	.DW	AY_RATIO / 2999
-	.DW	AY_RATIO / 3042
-	.DW	AY_RATIO / 3086
-	.DW	AY_RATIO / 3131
-	.DW	AY_RATIO / 3177
-	.DW	AY_RATIO / 3223
-	.DW	AY_RATIO / 3270
-	.DW	AY_RATIO / 3318
-	.DW	AY_RATIO / 3366
-	.DW	AY_RATIO / 3415
-	.DW	AY_RATIO / 3464
-	.DW	AY_RATIO / 3515
-	.DW	AY_RATIO / 3566
-	.DW	AY_RATIO / 3618
-	.DW	AY_RATIO / 3670
-	.DW	AY_RATIO / 3724
-	.DW	AY_RATIO / 3778
-	.DW	AY_RATIO / 3833
-	.DW	AY_RATIO / 3889
-	.DW	AY_RATIO / 3945
-	.DW	AY_RATIO / 4003
-	.DW	AY_RATIO / 4061
-	.DW	AY_RATIO / 4120
-	.DW	AY_RATIO / 4180
-	.DW	AY_RATIO / 4241
-	.DW	AY_RATIO / 4302
-	.DW	AY_RATIO / 4365
-	.DW	AY_RATIO / 4428
-	.DW	AY_RATIO / 4493
-	.DW	AY_RATIO / 4558
-	.DW	AY_RATIO / 4624
-	.DW	AY_RATIO / 4692
-	.DW	AY_RATIO / 4760
-	.DW	AY_RATIO / 4829
-	.DW	AY_RATIO / 4899
-	.DW	AY_RATIO / 4971
-	.DW	AY_RATIO / 5043
-	.DW	AY_RATIO / 5116
-	.DW	AY_RATIO / 5191
-	.DW	AY_RATIO / 5266
-	.DW	AY_RATIO / 5343
-	.DW	AY_RATIO / 5421
-	.DW	AY_RATIO / 5499
-	.DW	AY_RATIO / 5579
-	.DW	AY_RATIO / 5661
-	.DW	AY_RATIO / 5743
+	.DW	AY_RATIO / 2913		; A0#/B0b	178977250 / 2913 = 61440; PROOF: 61440 >> 3 = 7680, 3579545 / 7680 / 16 = 29.13
+	.DW	AY_RATIO / 2956		;
+	.DW	AY_RATIO / 2999		;
+	.DW	AY_RATIO / 3042		;
+	.DW	AY_RATIO / 3086		; B0
+	.DW	AY_RATIO / 3131		; 
+	.DW	AY_RATIO / 3177		; 
+	.DW	AY_RATIO / 3223		; 
+	.DW	AY_RATIO / 3270		; C1
+	.DW	AY_RATIO / 3318		; 
+	.DW	AY_RATIO / 3366		; 
+	.DW	AY_RATIO / 3415		; 
+	.DW	AY_RATIO / 3464		; C1#/D1b
+	.DW	AY_RATIO / 3515		; 
+	.DW	AY_RATIO / 3566		; 
+	.DW	AY_RATIO / 3618		; 
+	.DW	AY_RATIO / 3670		; D1
+	.DW	AY_RATIO / 3724		; 
+	.DW	AY_RATIO / 3778		; 
+	.DW	AY_RATIO / 3833		; 
+	.DW	AY_RATIO / 3889		; D1#/E1b
+	.DW	AY_RATIO / 3945		; 
+	.DW	AY_RATIO / 4003		; 
+	.DW	AY_RATIO / 4061		; 
+	.DW	AY_RATIO / 4120		; E1
+	.DW	AY_RATIO / 4180		; 
+	.DW	AY_RATIO / 4241		; 
+	.DW	AY_RATIO / 4302		; 
+	.DW	AY_RATIO / 4365		; F1
+	.DW	AY_RATIO / 4428		; 
+	.DW	AY_RATIO / 4493		; 
+	.DW	AY_RATIO / 4558		; 
+	.DW	AY_RATIO / 4624		; F1#/G1b
+	.DW	AY_RATIO / 4692		; 
+	.DW	AY_RATIO / 4760		; 
+	.DW	AY_RATIO / 4829		; 
+	.DW	AY_RATIO / 4899		; G1
+	.DW	AY_RATIO / 4971		; 
+	.DW	AY_RATIO / 5043		; 
+	.DW	AY_RATIO / 5116		; 
+	.DW	AY_RATIO / 5191		; G1#/A1b
+	.DW	AY_RATIO / 5266		; 
+	.DW	AY_RATIO / 5343		; 
+	.DW	AY_RATIO / 5421		; 
+	.DW	AY_RATIO / 5499		; A1
+	.DW	AY_RATIO / 5579		; 
+	.DW	AY_RATIO / 5661		; 
+	.DW	AY_RATIO / 5743		; 

Source/HBIOS/cfg_dyno.asm

@@ -11,11 +11,11 @@
 ; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
 ; FOR THE PLATFORM.
 ;
-#DEFINE PLATFORM_NAME "DYNO"
+#DEFINE PLATFORM_NAME "Dyno", " [", CONFIG, "]"
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_DYNO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
+PLATFORM	.EQU	PLT_DYNO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -24,6 +24,7 @@ USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
 TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
 ;
 BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
 ;
 CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
@@ -32,8 +33,9 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
 RAMBIAS		.EQU	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
@@ -82,6 +84,9 @@ DSRTCENABLE	.EQU	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
 DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
+DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+;
 BQRTCENABLE	.EQU	TRUE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
 BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
 ;
@@ -100,6 +105,7 @@ DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 UARTENABLE	.EQU	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 ASCISWAP	.EQU	FALSE		; ASCI: SWAP CHANNELS
 ASCIBOOT	.EQU	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
 ASCI0CFG	.EQU	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
@@ -115,9 +121,9 @@ XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-NECENABLE	.EQU	FALSE		; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|RC|RCV9958|RCKBD]
+TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|RC|RCV9958|RCKBD]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 ;
@@ -181,6 +187,8 @@ HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
 ;
+LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP

Source/HBIOS/cfg_ezz80.asm

@@ -11,11 +11,11 @@
 ; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
 ; FOR THE PLATFORM.
 ;
-#DEFINE PLATFORM_NAME "EASYZ80"
+#DEFINE PLATFORM_NAME "Easy-Z80", " [", CONFIG, "]"
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_EZZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
+PLATFORM	.EQU	PLT_EZZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -24,6 +24,7 @@ USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
 TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
 ;
 BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
 ;
 CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
@@ -32,8 +33,9 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
@@ -88,6 +90,9 @@ DSRTCENABLE	.EQU	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
 DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
+DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+;
 BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
 BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
 ;
@@ -153,9 +158,9 @@ XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-NECENABLE	.EQU	FALSE		; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|RC|RCV9958|RCKBD]
+TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|RC|RCV9958|RCKBD]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 ;
@@ -223,6 +228,11 @@ HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
 ;
+LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTCNT		.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
+LPT0BASE	.EQU	$E4		; LPT 0: REGISTERS BASE ADR
+LPT1BASE	.EQU	$E8		; LPT 1: REGISTERS BASE ADR
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP

Source/HBIOS/cfg_master.asm

@@ -8,11 +8,11 @@
 ; USED ONLY AS A REFERENCE TO HELP MANAGE THE FULL SET OF POSSIBLE SETTINGS AND
 ; KEEP THINGS CONSISTENT.
 ;
-#DEFINE PLATFORM_NAME "ROMWBW"
+#DEFINE PLATFORM_NAME "RomWBW", " [", CONFIG, "]"
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
+PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -21,6 +21,7 @@ USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
 TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
 ;
 BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
 ;
 CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
@@ -29,8 +30,9 @@ INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
-MEMMGR		.EQU	MM_NONE		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
+MEMMGR		.EQU	MM_NONE		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
 RAMBIAS		.EQU	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
@@ -60,6 +62,11 @@ N8_ACR		.EQU	$94		; N8: AUXILLARY CONTROL REGISTER (ACR) ADR
 N8_RMAP		.EQU	$96		; N8: ROM PAGE REGISTER ADR
 N8_DEFACR	.EQU	$1B		; N8: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE)
 ;
+RPH_PPI0	.EQU	$88		; RPH: FIRST PARALLEL PORT REGISTERS BASE ADR
+RPH_RTC		.EQU	$84		; RPH: RTC LATCH REGISTER ADR
+RPH_ACR		.EQU	$80		; RPH: AUXILLARY CONTROL REGISTER (ACR) ADR
+RPH_DEFACR	.EQU	$00		; RPH: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE)
+;
 MK4_IDE		.EQU	$80		; MK4: IDE REGISTERS BASE ADR
 MK4_XAR		.EQU	$88		; MK4: EXTERNAL ADDRESS REGISTER (XAR) ADR
 MK4_SD		.EQU	$89		; MK4: SD CARD CONTROL REGISTER ADR
@@ -117,6 +124,9 @@ DSRTCENABLE	.EQU	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
 DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
+DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+;
 BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
 BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
 ;
@@ -153,6 +163,7 @@ UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 ASCISWAP	.EQU	FALSE		; ASCI: SWAP CHANNELS
 ASCIBOOT	.EQU	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
 ASCI0CFG	.EQU	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
@@ -205,9 +216,11 @@ VDUSIZ		.EQU	V80X25		; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 CVDUMODE	.EQU	CVDUMODE_ECB	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
 CVDUMON		.EQU	CVDUMON_CGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
-NECENABLE	.EQU	FALSE		; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+GDCMODE		.EQU	GDCMODE_RPH	; GDC: GDC MODE: GDCMODE_[NONE|ECB|RPH]
+GDCMON		.EQU	GDCMON_EGA      ; GDC: GDC MONITOR SETUP: GDCMON_[NONE|CGA|EGA]
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|RC|RCV9958|RCKBD]
+TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|RC|RCV9958|RCKBD]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
@@ -260,7 +273,7 @@ PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 PPIDE1BASE	.EQU	$20		; PPIDE 1: PPI REGISTERS BASE ADR
 PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
 PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE2BASE	.EQU	$44		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2BASE	.EQU	$14		; PPIDE 2: PPI REGISTERS BASE ADR
 PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
@@ -291,6 +304,11 @@ PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
 PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
 PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
 ;
+LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTCNT		.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
+LPT0BASE	.EQU	$E8		; LPT 0: REGISTERS BASE ADR
+LPT1BASE	.EQU	$EC		; LPT 1: REGISTERS BASE ADR
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO4BASE	.EQU	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)

Source/HBIOS/cfg_mbc.asm

@@ -11,11 +11,11 @@
 ; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
 ; FOR THE PLATFORM.
 ;
-#DEFINE PLATFORM_NAME "Multi Board Computer"
+#DEFINE PLATFORM_NAME "Nhyodyne", " [", CONFIG, "]"
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_MBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
+PLATFORM	.EQU	PLT_MBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -24,6 +24,7 @@ USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
 TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
 ;
 BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
 ;
 CPUSPDCAP	.EQU	SPD_HILO	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_LOW		; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
@@ -32,8 +33,9 @@ INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
-MEMMGR		.EQU	MM_MBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
+MEMMGR		.EQU	MM_MBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
 ;
@@ -87,6 +89,9 @@ DSRTCENABLE	.EQU	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
 DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
+DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+;
 BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
 BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
 ;
@@ -141,9 +146,9 @@ VDUSIZ		.EQU	V80X25		; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
 CVDUENABLE	.EQU	TRUE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 CVDUMODE	.EQU	CVDUMODE_MBC	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
 CVDUMON		.EQU	CVDUMON_CGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
-NECENABLE	.EQU	FALSE		; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
-TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_SCG	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|RC|RCV9958|RCKBD]
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.EQU	TRUE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.EQU	TMSMODE_MBC	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|RC|RCV9958|RCKBD]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
@@ -197,7 +202,7 @@ PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 PPIDE1BASE	.EQU	$20		; PPIDE 1: PPI REGISTERS BASE ADR
 PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
 PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE2BASE	.EQU	$44		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2BASE	.EQU	$14		; PPIDE 2: PPI REGISTERS BASE ADR
 PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
@@ -223,6 +228,11 @@ PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
 PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
 PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
 ;
+LPTENABLE	.EQU	TRUE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTCNT		.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
+LPT0BASE	.EQU	$E8		; LPT 0: REGISTERS BASE ADR
+LPT1BASE	.EQU	$EC		; LPT 1: REGISTERS BASE ADR
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO4BASE	.EQU	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
@@ -238,9 +248,9 @@ AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
 SN7CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
 SNMODE		.EQU	SNMODE_NONE	; DRIVER MODE: SNMODE_[NONE|RC2014|VGM]
 ;
-AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
-AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
-AYMODE		.EQU	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
+AY38910ENABLE	.EQU	TRUE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.EQU	3579545 / 2	; DEFAULT TO CPUOSC / 4
+AYMODE		.EQU	AYMODE_MBC	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
 ;
 SPKENABLE	.EQU	TRUE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_mk4.asm

@@ -11,11 +11,11 @@
 ; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
 ; FOR THE PLATFORM.
 ;
-#DEFINE PLATFORM_NAME "MARK IV"
+#DEFINE PLATFORM_NAME "Mark IV", " [", CONFIG, "]"
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_MK4		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
+PLATFORM	.EQU	PLT_MK4		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -24,6 +24,7 @@ USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
 TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
 ;
 BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
 ;
 CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
@@ -32,8 +33,9 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
 RAMBIAS		.EQU	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 ;
@@ -93,6 +95,9 @@ DSRTCENABLE	.EQU	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
 DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
+DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+;
 BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
 BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
 ;
@@ -122,6 +127,7 @@ UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 ASCISWAP	.EQU	FALSE		; ASCI: SWAP CHANNELS
 ASCIBOOT	.EQU	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
 ASCI0CFG	.EQU	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
@@ -140,9 +146,9 @@ VDUSIZ		.EQU	V80X25		; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 CVDUMODE	.EQU	CVDUMODE_ECB	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
 CVDUMON		.EQU	CVDUMON_EGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
-NECENABLE	.EQU	FALSE		; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_SCG	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|RC|RCV9958|RCKBD]
+TMSMODE		.EQU	TMSMODE_SCG	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|RC|RCV9958|RCKBD]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
@@ -189,7 +195,7 @@ IDE2B8BIT	.EQU	FALSE		; IDE 2B (MASTER): 8 BIT XFER
 PPIDEENABLE	.EQU	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
 PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 PPIDECNT	.EQU	2		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
-PPIDE0BASE	.EQU	$44		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0BASE	.EQU	$14		; PPIDE 0: PPI REGISTERS BASE ADR
 PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
 PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 PPIDE1BASE	.EQU	$20		; PPIDE 1: PPI REGISTERS BASE ADR
@@ -224,6 +230,11 @@ PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
 PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
 PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
 ;
+LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTCNT		.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
+LPT0BASE	.EQU	$E8		; LPT 0: REGISTERS BASE ADR
+LPT1BASE	.EQU	$EC		; LPT 1: REGISTERS BASE ADR
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO4BASE	.EQU	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)

Source/HBIOS/cfg_n8.asm

@@ -11,11 +11,11 @@
 ; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
 ; FOR THE PLATFORM.
 ;
-#DEFINE PLATFORM_NAME "N8"
+#DEFINE PLATFORM_NAME "N8", " [", CONFIG, "]"
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_N8		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
+PLATFORM	.EQU	PLT_N8		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -24,6 +24,7 @@ USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
 TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
 ;
 BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
 ;
 CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
@@ -32,8 +33,9 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
-MEMMGR		.EQU	MM_N8		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
+MEMMGR		.EQU	MM_N8		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 RAMBIAS		.EQU	0		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 RAMLOC		.EQU	0		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
 ;
@@ -95,6 +97,9 @@ DSRTCENABLE	.EQU	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
 DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
+DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+;
 BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
 BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
 ;
@@ -124,6 +129,7 @@ UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 ASCISWAP	.EQU	FALSE		; ASCI: SWAP CHANNELS
 ASCIBOOT	.EQU	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
 ASCI0CFG	.EQU	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
@@ -142,9 +148,9 @@ VDUSIZ		.EQU	V80X25		; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 CVDUMODE	.EQU	CVDUMODE_ECB	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
 CVDUMON		.EQU	CVDUMON_EGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
-NECENABLE	.EQU	FALSE		; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	TRUE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_N8	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|RC|RCV9958|RCKBD]
+TMSMODE		.EQU	TMSMODE_N8	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|RC|RCV9958|RCKBD]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
@@ -222,6 +228,8 @@ PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
 PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
 PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
 ;
+LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO4BASE	.EQU	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)

Source/HBIOS/cfg_rcz180.asm

@@ -11,11 +11,11 @@
 ; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
 ; FOR THE PLATFORM.
 ;
-#DEFINE PLATFORM_NAME "RC2014"
+#DEFINE PLATFORM_NAME "RC2014", " [", CONFIG, "]"
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
+PLATFORM	.EQU	PLT_RCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -24,6 +24,7 @@ USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
 TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
 ;
 BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
 ;
 CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
@@ -32,8 +33,9 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
 RAMBIAS		.EQU	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
@@ -90,6 +92,9 @@ DSRTCENABLE	.EQU	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
 DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
+DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+;
 BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
 BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
 ;
@@ -125,6 +130,7 @@ UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 ASCISWAP	.EQU	FALSE		; ASCI: SWAP CHANNELS
 ASCIBOOT	.EQU	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
 ASCI0CFG	.EQU	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
@@ -159,9 +165,9 @@ XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-NECENABLE	.EQU	FALSE		; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_RC	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|RC|RCV9958|RCKBD]
+TMSMODE		.EQU	TMSMODE_RC	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|RC|RCV9958|RCKBD]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 ;
@@ -238,6 +244,8 @@ PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
 PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
 PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
 ;
+LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP

Source/HBIOS/cfg_rcz280.asm

@@ -11,11 +11,11 @@
 ; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
 ; FOR THE PLATFORM.
 ;
-#DEFINE PLATFORM_NAME "RC2014"
+#DEFINE PLATFORM_NAME "RC2014", " [", CONFIG, "]"
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RCZ280	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
+PLATFORM	.EQU	PLT_RCZ280	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
 CPUFAM		.EQU	CPU_Z280	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -24,6 +24,7 @@ USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
 TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
 ;
 BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
 ;
 CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
@@ -32,8 +33,9 @@ INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
 RAMBIAS		.EQU	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
@@ -95,6 +97,9 @@ DSRTCENABLE	.EQU	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
 DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
+DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+;
 BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
 BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
 ;
@@ -175,9 +180,9 @@ XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-NECENABLE	.EQU	FALSE		; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_RC	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|RC|RCV9958|RCKBD]
+TMSMODE		.EQU	TMSMODE_RC	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|RC|RCV9958|RCKBD]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 ;
@@ -254,6 +259,8 @@ PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
 PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
 PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
 ;
+LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP

Source/HBIOS/cfg_rcz80.asm

@@ -11,11 +11,11 @@
 ; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
 ; FOR THE PLATFORM.
 ;
-#DEFINE PLATFORM_NAME "RC2014"
+#DEFINE PLATFORM_NAME "RC2014", " [", CONFIG, "]"
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RCZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
+PLATFORM	.EQU	PLT_RCZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -24,6 +24,7 @@ USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
 TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
 ;
 BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
 ;
 CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
@@ -32,8 +33,9 @@ INTMODE		.EQU	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
@@ -89,6 +91,9 @@ DSRTCENABLE	.EQU	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
 DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
+DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+;
 BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
 BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
 ;
@@ -164,9 +169,9 @@ XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-NECENABLE	.EQU	FALSE		; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_RC	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|RC|RCV9958|RCKBD]
+TMSMODE		.EQU	TMSMODE_RC	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|RC|RCV9958|RCKBD]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 ;
@@ -243,6 +248,11 @@ PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
 PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
 PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
 ;
+LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTCNT		.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
+LPT0BASE	.EQU	$E4		; LPT 0: REGISTERS BASE ADR
+LPT1BASE	.EQU	$E8		; LPT 1: REGISTERS BASE ADR
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP

Source/HBIOS/cfg_rph.asm

@@ -0,0 +1,256 @@
+;
+;==================================================================================================
+;   ROMWBW 2.X CONFIGURATION FOR RHYOPHYRE
+;==================================================================================================
+;
+; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
+; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
+; UNDER THIS DIRECTORY.
+;
+; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
+; FOR THE PLATFORM.
+;
+#DEFINE PLATFORM_NAME "Rhyophyre", " [", CONFIG, "]"
+;
+#INCLUDE "hbios.inc"
+;
+PLATFORM	.EQU	PLT_RPH		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.EQU	TRUE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+;
+BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+;
+CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
+INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;
+RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
+MEMMGR		.EQU	MM_RPH		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+RAMBIAS		.EQU	0		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMLOC		.EQU	0		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
+;
+Z180_BASE	.EQU	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
+Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
+Z180_MEMWAIT	.EQU	0		; Z180: MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.EQU	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+Z180_TIMER	.EQU	TRUE		; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
+;
+RPH_PPI0	.EQU	$88		; RPH: FIRST PARALLEL PORT REGISTERS BASE ADR
+RPH_RTC		.EQU	$84		; RPH: RTC LATCH REGISTER ADR
+RPH_ACR		.EQU	$80		; RPH: AUXILLARY CONTROL REGISTER (ACR) ADR
+RPH_DEFACR	.EQU	$20		; RPH: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE)
+;
+RTCIO		.EQU	RPH_RTC		; RTC LATCH REGISTER ADR
+;
+KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+;
+CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.EQU	$B0		; CTC BASE I/O ADDRESS
+CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
+SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+;
+WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+;
+DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
+DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
+DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
+;
+LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED
+LEDMODE		.EQU	LEDMODE_RTC	; LEDMODE_[STD|RTC]
+LEDPORT		.EQU	RTCIO		; STATUS LED PORT ADDRESS
+LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+;
+DSKYENABLE	.EQU	FALSE		; ENABLES DSKY
+DSKYMODE	.EQU	DSKYMODE_V1	; DSKY VERSION: DSKYMODE_[V1|NG]
+DSKYPPIBASE	.EQU	RPH_PPI0		; BASE I/O ADDRESS OF DSKY PPI
+DSKYOSC		.EQU	3000000		; OSCILLATOR FREQ FOR DSKYNG (IN HZ)
+;
+BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYENABLE	.EQU	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+;
+DSRTCENABLE	.EQU	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
+DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+;
+DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+;
+BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+;
+INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+;
+RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
+HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+;
+DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+;
+DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+;
+UARTENABLE	.EQU	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
+UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
+UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
+UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
+UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
+UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+;
+ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+ASCISWAP	.EQU	FALSE		; ASCI: SWAP CHANNELS
+ASCIBOOT	.EQU	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
+ASCI0CFG	.EQU	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
+ASCI1CFG	.EQU	DEFSERCFG	; ASCI 1: SERIAL LINE CONFIG
+;
+Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+;
+ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+;
+SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+;
+XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+;
+VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+VDUSIZ		.EQU	V80X25		; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
+CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+CVDUMODE	.EQU	CVDUMODE_ECB	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
+CVDUMON		.EQU	CVDUMON_EGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
+GDCENABLE	.EQU	TRUE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+GDCMODE		.EQU	GDCMODE_RPH	; GDC: GDC MODE: GDCMODE_[NONE|ECB|RPH]
+GDCMON		.EQU	GDCMON_EGA      ; GDC: GDC MONITOR SETUP: GDCMON_[NONE|CGA|EGA]
+TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.EQU	TMSMODE_N8	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|RC|RCV9958|RCKBD]
+TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
+;
+MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+;
+FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.EQU	FDMODE_N8	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
+FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
+FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+;
+RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+RFCNT		.EQU	1		; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
+;
+IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.EQU	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT		.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.EQU	IDEMODE_DIO	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE0BASE	.EQU	$20		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.EQU	$20		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.EQU	$28		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.EQU	FALSE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.EQU	FALSE		; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.EQU	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE1BASE	.EQU	$00		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.EQU	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.EQU	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.EQU	TRUE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.EQU	TRUE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.EQU	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE2BASE	.EQU	$00		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.EQU	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.EQU	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.EQU	TRUE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.EQU	TRUE		; IDE 2B (MASTER): 8 BIT XFER
+;
+PPIDEENABLE	.EQU	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.EQU	RPH_PPI0	; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1BASE	.EQU	$00		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE2BASE	.EQU	$00		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+;
+SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.EQU	SDMODE_CSIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT]
+SDPPIBASE	.EQU	RPH_PPI0	; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
+SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+;
+PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPSDENABLE	.EQU	FALSE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PRPCONENABLE	.EQU	FALSE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+;
+PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+;
+HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+;
+LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+;
+PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO4BASE	.EQU	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
+PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIOZBASE	.EQU	$88		; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
+PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+PIOSBASE	.EQU	RPH_PPI0		; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
+;
+UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+FIFO_BASE	.EQU	$0C		; UF: REGISTERS BASE ADR
+;
+SN76489ENABLE	.EQU	FALSE		; SN76489 SOUND DRIVER
+AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
+SNMODE		.EQU	SNMODE_NONE	; DRIVER MODE: SNMODE_[NONE|RC2014|VGM]
+;
+AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
+AYMODE		.EQU	AYMODE_N8	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
+;
+SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+;
+DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)

Source/HBIOS/cfg_sbc.asm

@@ -11,11 +11,11 @@
 ; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
 ; FOR THE PLATFORM.
 ;
-#DEFINE PLATFORM_NAME "SBC"
+#DEFINE PLATFORM_NAME "Single Board Computer", " [", CONFIG, "]"
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
+PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -24,6 +24,7 @@ USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
 TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
 ;
 BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
 ;
 CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
@@ -32,8 +33,9 @@ INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
-MEMMGR		.EQU	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
+MEMMGR		.EQU	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
 ;
@@ -87,6 +89,9 @@ DSRTCENABLE	.EQU	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
 DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
+DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+;
 BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
 BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
 ;
@@ -141,9 +146,9 @@ VDUSIZ		.EQU	V80X25		; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 CVDUMODE	.EQU	CVDUMODE_ECB	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
 CVDUMON		.EQU	CVDUMON_EGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
-NECENABLE	.EQU	FALSE		; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_SCG	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|RC|RCV9958|RCKBD]
+TMSMODE		.EQU	TMSMODE_SCG	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|RC|RCV9958|RCKBD]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
@@ -197,7 +202,7 @@ PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 PPIDE1BASE	.EQU	$20		; PPIDE 1: PPI REGISTERS BASE ADR
 PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
 PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE2BASE	.EQU	$44		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2BASE	.EQU	$14		; PPIDE 2: PPI REGISTERS BASE ADR
 PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
@@ -223,6 +228,11 @@ PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
 PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
 PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
 ;
+LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTCNT		.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
+LPT0BASE	.EQU	$E8		; LPT 0: REGISTERS BASE ADR
+LPT1BASE	.EQU	$EC		; LPT 1: REGISTERS BASE ADR
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO4BASE	.EQU	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)

Source/HBIOS/cfg_scz180.asm

@@ -11,11 +11,11 @@
 ; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
 ; FOR THE PLATFORM.
 ;
-#DEFINE PLATFORM_NAME "SCZ180"
+#DEFINE PLATFORM_NAME "Small Computer", " [", CONFIG, "]"
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_SCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
+PLATFORM	.EQU	PLT_SCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -24,6 +24,7 @@ USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
 TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
 ;
 BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
 ;
 CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
@@ -32,8 +33,9 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
 RAMBIAS		.EQU	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 ;
@@ -85,6 +87,9 @@ DSRTCENABLE	.EQU	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
 DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
+DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+;
 BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
 BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
 ;
@@ -120,6 +125,7 @@ UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 ASCISWAP	.EQU	FALSE		; ASCI: SWAP CHANNELS
 ASCIBOOT	.EQU	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
 ASCI0CFG	.EQU	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
@@ -154,9 +160,9 @@ XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-NECENABLE	.EQU	FALSE		; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_RC	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|RC|RCV9958|RCKBD]
+TMSMODE		.EQU	TMSMODE_RC	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|RC|RCV9958|RCKBD]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 ;
@@ -233,6 +239,8 @@ PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
 PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
 PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
 ;
+LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP

Source/HBIOS/cfg_una.asm

@@ -11,11 +11,12 @@
 ; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
 ; FOR THE PLATFORM.
 ;
-#DEFINE PLATFORM_NAME "UNA"
+#DEFINE PLATFORM_NAME "UNA", " [", CONFIG, "]"
 ;
 #INCLUDE "../UBIOS/ubios.inc"
 ;
-;PLATFORM	.EQU	PLT_UNA		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
+;PLATFORM	.EQU	PLT_UNA		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_UNA	; HARDWARE BIOS: BIOS_[WBW|UNA]
 ;
 BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
@@ -26,6 +27,7 @@ CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ;
 RTCIO		.EQU	$70		; RTC LATCH REGISTER ADR
 ;

Source/HBIOS/cfg_zeta.asm

@@ -11,11 +11,11 @@
 ; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
 ; FOR THE PLATFORM.
 ;
-#DEFINE PLATFORM_NAME "ZETA"
+#DEFINE PLATFORM_NAME "Zeta", " [", CONFIG, "]"
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_ZETA	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
+PLATFORM	.EQU	PLT_ZETA	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; BIOS_[WBW|UNA]: HARDWARE BIOS
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -24,6 +24,7 @@ USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
 TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
 ;
 BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
 ;
 CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
@@ -32,8 +33,9 @@ INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
-MEMMGR		.EQU	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
+MEMMGR		.EQU	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
 ;
@@ -74,6 +76,9 @@ DSRTCENABLE	.EQU	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
 DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
+DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+;
 BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
 BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
 ;
@@ -114,9 +119,9 @@ XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-NECENABLE	.EQU	FALSE		; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|RC|RCV9958|RCKBD]
+TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|RC|RCV9958|RCKBD]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 ;
@@ -163,9 +168,8 @@ PPPCONENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
-PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
-PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+;
+LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
 ;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)

Source/HBIOS/cfg_zeta2.asm

@@ -11,11 +11,11 @@
 ; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
 ; FOR THE PLATFORM.
 ;
-#DEFINE PLATFORM_NAME "ZETA V2"
+#DEFINE PLATFORM_NAME "Zeta 2", " [", CONFIG, "]"
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_ZETA2	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
+PLATFORM	.EQU	PLT_ZETA2	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -24,6 +24,7 @@ USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
 TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
 ;
 BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
 ;
 CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
@@ -32,8 +33,9 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
@@ -85,6 +87,9 @@ DSRTCENABLE	.EQU	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
 DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
+DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+;
 BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
 BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
 ;
@@ -125,9 +130,9 @@ XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-NECENABLE	.EQU	FALSE		; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|RC|RCV9958|RCKBD]
+TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|RC|RCV9958|RCKBD]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 ;
@@ -175,6 +180,8 @@ HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
 PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
 ;
+LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP

Source/HBIOS/dbgmon.asm

@@ -38,6 +38,8 @@ ENA_XM	.EQU	FALSE			; NO ROOM FOR BOTH DSKY+XMODEM
 ENA_XM	.EQU	TRUE			; INCLUDE XMODEM IF SPACE AVAILABLE
 #ENDIF
 ;
+ENA_MBC6502	.EQU	FALSE		; ENABLE OR DISABLE MBC6502 OPTION
+;
 #INCLUDE "util.asm"
 ;
 ;__UART_ENTRY_________________________________________________________________
@@ -69,6 +71,8 @@ UART_ENTRY:
 ; R XXXX		- RUN A PROGRAM AT ADDRESS XXXX
 ; S XX			- SET ACTIVE BANK TO XX
 ; T XXXX 		- X-MODEM TRANSFER TO MEMORY LOCATION XXXX
+; U 			- SET BANK TO PREVIOUS BANK
+; 6 XX                  - TRANSFER CONTROL TO MBC6502 UNIT XX
 ; X			- EXIT MONITOR
 ;
 ;__COMMAND_PARSE______________________________________________________________
@@ -126,6 +130,12 @@ SERIALCMDLOOP:
 #IF (BIOS == BIOS_WBW)
 	CP	'S'			; IS IT A "S" (Y/N)
 	JP	Z,SETBNK		; SET BANK COMMAND
+	CP	'U'			; IS IT A "U" (Y/N)
+	JP	Z,UNSETBNK		; UNSET (REVERT) BANK COMMAND		
+  #IF ((PLATFORM = PLT_MBC) & ENA_MBC6502)
+	CP	'6'			; IS IT A "6" (Y/N)
+	JP	Z,MBC6502		; TRANSFER TO MBC6502 COMMAND
+  #ENDIF
 #ENDIF
 	CP	'X'			; IS IT A "X" (Y/N)
 	JP	Z,EXIT			; EXIT COMMAND
@@ -218,6 +228,8 @@ SETBNK:
 	LD	HL,TXT_IMERR
 	CALL	PRTSTR
 #ELSE
+	LD	A,($FFE0)		; GET AND SAVE
+	LD	(BNKSAV),A		; CURRENT BANK
 	CALL	BYTEPARM		; GET BANK NUMBER
 	JP	C,ERR			; HANDLE DATA ENTRY ERROR
 	LD	C,A			; PUT IN C FOR FOR FUNC CALL
@@ -226,6 +238,25 @@ SETBNK:
 #ENDIF
 	JP	SERIALCMDLOOP		; NEXT COMMAND
 ;
+;__UNSETBNK___________________________________________________________________
+;
+;	PERFORM UNSET BANK ACTION - REVERT TO BANK BEFORE PREVIOUS SET
+;_____________________________________________________________________________
+;
+UNSETBNK:
+#IF (INTMODE == 1)
+	LD	HL,TXT_IMERR
+	CALL	PRTSTR
+#ELSE
+	LD	A,(BNKSAV)
+	LD	C,A			; PUT IN C FOR FOR FUNC CALL
+	LD	B,BF_SYSSETBNK		; SET BANK FUNCTION
+	CALL	$FFF0			; C HAS BANK, DO IT
+#ENDIF
+	JP	SERIALCMDLOOP		; NEXT COMMAND
+;
+BNKSAV	.DB	00H			; OLD BANK FROM BEFORE SET
+;
 #ENDIF
 ;
 ;__RUN________________________________________________________________________
@@ -358,7 +389,8 @@ XMLOAD:	CALL	WORDPARM		; GET STARTING LOCATION
 	CALL	NEWLINE
 ;
 	LD	BC,$F8F0		; GET CPU SPEED
-	RST	08			; AND MULTIPLY
+	CALL	$FFF0			; CALL HBIOS
+;	RST	08			; AND MULTIPLY
 	LD	A,L			; BY 4
 	PUSH	AF
 	ADD	A,A			; TO CREATE
@@ -769,6 +801,30 @@ HELP:
 	CALL	PRTSTR			; DISPLAY IT
 	JP	SERIALCMDLOOP		; AND BACK TO COMMAND LOOP
 ;
+;__MBC6502____________________________________________________________________
+;
+;	TRANSFER CONTROL TO MBC6502
+;_____________________________________________________________________________
+;
+;
+#IF (BIOS == BIOS_WBW)
+  #IF ((PLATFORM = PLT_MBC) & ENA_MBC6502)
+MBC6502:
+	CALL	BYTEPARM		; GET BYTE VALUE (FILL VALUE) INTO A
+	CPL				; UNIT 0 = FFH, 1 = FEH ETC
+	LD	C,A
+;
+	IN	A,(C)			; EXECUTE
+	NOP				; TRANSFER
+;
+	LD	A,($FFE0)		; GET PREVIOUS BANK
+	OUT	(MPCL_RAM),A		; SET RAM PAGE SELECTOR
+	OUT	(MPCL_ROM),A		; SET ROM PAGE SELECTOR
+;
+	JP	SERIALCMDLOOP		; AND BACK TO COMMAND LOOP
+  #ENDIF
+#ENDIF
+;
 ;__ERR________________________________________________________________________
 ;
 ;	SYNTAX ERROR
@@ -1205,9 +1261,17 @@ TXT_HELP	.TEXT	"\r\nMonitor Commands (all values in hex):"
 		.TEXT	"\r\nP xxxx           - Program RAM at address xxxx"
 		.TEXT	"\r\nR xxxx [[yy] [zzzz]]  - Run code at address xxxx"
 		.TEXT	"\r\n                        Pass yy and zzzz to register A and BC"
+#IF (BIOS == BIOS_WBW)
 		.TEXT	"\r\nS xx             - Set bank to xx"
+		.TEXT	"\r\nU                - Set bank to previous bank"
+#ENDIF
 #IF (ENA_XM)
 		.TEXT	"\r\nT xxxx           - X-modem transfer to memory location xxxx"
+#ENDIF
+#IF (BIOS == BIOS_WBW)
+  #IF ((PLATFORM == PLT_MBC) & ENA_MBC6502)
+		.TEXT	"\r\n6 xx             - Transfer control to MBC6502 unit xx"
+  #ENDIF
 #ENDIF
 		.TEXT	"\r\nX                - Exit monitor"
 		.TEXT	"$"

Source/HBIOS/ds1501rtc.asm

@@ -0,0 +1,397 @@
+
+;
+;==================================================================================================
+; Maxim DS1501/DS1511 Y2K-Compliant Watchdog RTC Driver
+;==================================================================================================
+;
+; THIS DRIVER CODE WAS CONTRIBUTED TO ROMWBW BY JPELLETIER 3:59 PM 7/24/2022
+;
+;  Register Addresses (HEX / BCD):
+;
+;  +---+-----+---------------+-------------------+------------------+----------------+
+;  |ADR|  D7 | D6  | D5 | D4 | D3 | D2 | D1 | D0 | RANGE            | REGISTER       |
+;  +---+-----+---------------+-------------------+------------------+----------------+
+;  | 0 |  0  |     10-Second |          1-Second |            00-59 | Seconds        |
+;  +---+-----+-----+---------+-------------------+------------------+----------------+
+;  | 1 |  0  |     10-Minute |          1-Minute |            00-59 | Minutes        |
+;  +---+-----+-----+---------+-------------------+------------------+----------------+
+;  | 2 |  0  |  0  | 10-Hour |            1-Hour |            00-23 | Hours          |
+;  +---+-----+-----+----+----+-------------------+------------------+----------------+
+;  | 3 |  0  |  0  |  0 |  0 |  0 |  Day Of Week |            01-07 | Day Of Week    |
+;  +---+-----+-----+----+----+----+--------------+------------------+----------------+
+;  | 4 |  0  |  0  | 10-Date |            1-Date |            01-31 | Date           |
+;  +---+-----+-----+----+----+-------------------+------------------+----------------+
+;  | 5 |/EOSC|/E32K|BB32|10Mo|           1-Month |            01-12 | Month          |
+;  +---+-----+-----+----+----+-------------------+------------------+----------------+
+;  | 6 |             10-Year |            1-Year |            00-99 | Year           |
+;  +---+-----+-----+----+----+----+----+----+----+------------------+----------------+
+;  | 7 |          10-Century |         1-Century |            00-39 | Century        |
+;  +---+-----+-----+----+----+----+----+----+----+------------------+----------------+
+;  | 8 |  AM1|     10-Second |          1-Second |            00-59 | Seconds Alarm  |
+;  +---+-----+---------------+-------------------+------------------+----------------+
+;  | 9 |  AM2|     10-Minute |          1-Minute |            00-59 | Minutes Alarm  |
+;  +---+-----+-----+---------+-------------------+------------------+----------------+
+;  | A |  AM3|  0  | 10-Hour |            1-Hour |            00-23 | Hours Alarm    |
+;  +---+-----+-----+----+----+-------------------+------------------+----------------+
+;  | B |  AM4|DY/DT| 10-date |          Day/Date |        1-7/01-31 | Day/Date Alarm |
+;  +---+-----+-----+----+----+----+--------------+------------------+----------------+
+;  | C |          0.1-Second |       0.01-Second |            00-99 | Watchdog       |
+;  +---+-----+-----+---------+-------------------+------------------+----------------+
+;  | D |           10-Second |          1-Second |            00-99 | Watchdog       |
+;  +---+-----+-----+---------+-------------------+------------------+----------------+
+;  | E | BLF1| BLF2| PRS| PAB| TDF| KSF| WDF|IRQF|                  | ControlA       |
+;  +---+-----+-----+----+----+----+----+----+----+------------------+----------------+
+;  | F |   TE|   CS| BME| TPE| TIE| KIE| WDE| WDS|                  | ControlB       |
+;  +---+-----+-----+----+----+----+----+----+----+------------------+----------------+
+;  |10 |           Extended RAM Address          |            00-FF | RAM Address    |
+;  +---+-----+-----+----+----+----+----+----+----+------------------+----------------+
+;  |11 |                 Reserved                |                  |                |
+;  +---+-----+-----+----+----+----+----+----+----+------------------+----------------+
+;  |12 |                 Reserved                |                  |                |
+;  +---+--+--+-----+----+----+----+----+----+----+------------------+----------------+
+;  |13 |             Extended RAM Data           |            00-FF | RAM Data       |
+;  +---+--+--+-----+----+----+----+----+----+----+------------------+----------------+
+;  |14-1F |              Reserved                |                  |                |
+;  +------+--+-----+----+----+----+----+----+----+------------------+----------------+
+
+;  * = Unused bits; unwritable and read as 0.
+;  0 = should be set to 0 for valid time/calendar range.
+;  Clock calendar data is BCD. Automatic leap year adjustment.
+;  Day-Of-Week coded as Sunday = 1 through Saturday = 7.
+
+; Constants
+
+;By defining 2 bases, this allows some flexibility for address decoding
+DS1501NVM_BASE      .EQU    DS1501RTC_BASE + $10
+
+DS1501RTC_SEC	    .EQU	DS1501RTC_BASE + $00
+DS1501RTC_MIN	    .EQU	DS1501RTC_BASE + $01
+DS1501RTC_HOUR	    .EQU	DS1501RTC_BASE + $02
+DS1501RTC_WEEK_DAY	.EQU	DS1501RTC_BASE + $03
+DS1501RTC_DAY	    .EQU	DS1501RTC_BASE + $04
+DS1501RTC_MONTH	    .EQU	DS1501RTC_BASE + $05
+DS1501RTC_YEAR	    .EQU	DS1501RTC_BASE + $06
+DS1501RTC_CENT      .EQU	DS1501RTC_BASE + $07
+DS1501RTC_SEC_ALM	.EQU	DS1501RTC_BASE + $08
+DS1501RTC_MIN_ALM	.EQU	DS1501RTC_BASE + $09
+DS1501RTC_HOUR_ALM	.EQU	DS1501RTC_BASE + $0A
+DS1501RTC_DAY_ALM	.EQU	DS1501RTC_BASE + $0B
+DS1501RTC_WDOG1     .EQU	DS1501RTC_BASE + $0C
+DS1501RTC_WDOG2 	.EQU	DS1501RTC_BASE + $0D
+DS1501RTC_CONTROLA	.EQU	DS1501RTC_BASE + $0E
+DS1501RTC_CONTROLB	.EQU	DS1501RTC_BASE + $0F
+
+DS1501RTC_RAMADDR	.EQU	DS1501NVM_BASE + $00
+DS1501RTC_RAMDATA	.EQU	DS1501NVM_BASE + $03
+
+DS1501RTC_HIGH	.EQU	%11110000
+DS1501RTC_LOW	.EQU	%00001111
+
+;ControlA bit masks
+;BLF1| BLF2| PRS| PAB| TDF| KSF| WDF|IRQF
+DS1501RTC_IRQF	.EQU	%00000001
+DS1501RTC_WDF	.EQU	%00000010
+DS1501RTC_KSF	.EQU	%00000100
+DS1501RTC_TDF	.EQU	%00001000
+DS1501RTC_PAB	.EQU	%00010000
+DS1501RTC_PRS 	.EQU	%00100000
+DS1501RTC_BLF2  .EQU	%01000000
+DS1501RTC_BLF1	.EQU	%10000000
+
+;ControlB bit masks
+;TE| CS| BME| TPE| TIE| KIE| WDE| WDS|
+DS1501RTC_WDS 	.EQU	%00000001
+DS1501RTC_WDE	.EQU	%00000010
+DS1501RTC_KIE	.EQU	%00000100
+DS1501RTC_TIE	.EQU	%00001000
+DS1501RTC_TPE	.EQU	%00010000
+DS1501RTC_BME 	.EQU	%00100000
+DS1501RTC_CS    .EQU	%01000000
+DS1501RTC_TE	.EQU	%10000000
+
+DS1501RTC_BUFSIZE	.EQU	6		; 6 BYTE BUFFER (YYMMDDHHMMSS)
+
+; RTC Device Initialization Entry
+
+DS1501RTC_INIT:
+	CALL	NEWLINE				; Formatting
+	PRTS("DS1501RTC: IO=0x$")
+	LD	A, DS1501RTC_BASE
+	CALL	PRTHEXBYTE
+
+	CALL	NEWLINE				; Formatting
+	PRTS("DS1501NVM: IO=0x$")
+	LD	A, DS1501NVM_BASE
+	CALL	PRTHEXBYTE
+
+    IN	A,(DS1501RTC_CONTROLB)      ;clear any pending interrupt flags
+
+	XOR	A				; Zero A
+    OR      DS1501RTC_TE            ;enable time updates
+    OUT	(DS1501RTC_CONTROLB), A
+
+	CALL	DS1501RTC_LOAD
+	; DISPLAY CURRENT TIME
+	PRTS("  $")
+	LD	A, (DS1501RTC_BUF_MON)
+	CALL	PRTHEXBYTE
+	PRTS("/$")
+	LD	A, (DS1501RTC_BUF_DAY)
+	CALL	PRTHEXBYTE
+	PRTS("/$")
+	LD	A, (DS1501RTC_BUF_YEAR)
+	CALL	PRTHEXBYTE
+	PRTS(" $")
+	LD	A, (DS1501RTC_BUF_HOUR)
+	CALL	PRTHEXBYTE
+	PRTS(":$")
+	LD	A, (DS1501RTC_BUF_MIN)
+	CALL	PRTHEXBYTE
+	PRTS(":$")
+	LD	A, (DS1501RTC_BUF_SEC)
+	CALL	PRTHEXBYTE
+
+	LD	BC,DS1501RTC_DISPATCH
+	CALL	RTC_SETDISP
+
+	XOR	A				; Signal success
+	RET
+
+; RTC Device Function Dispatch Entry
+;   A: Result (OUT), 0=OK, Z=OK, NZ=Error
+;   B: Function (IN)
+
+DS1501RTC_DISPATCH:
+	LD	A, B				; Get requested function
+	AND	$0F				; Isolate Sub-Function
+	JP	Z, DS1501RTC_GETTIM			; Get Time
+	DEC	A
+	JP	Z, DS1501RTC_SETTIM			; Set Time
+	DEC	A
+	JP	Z, DS1501RTC_GETBYT			; Get NVRAM Byte Value
+	DEC	A
+	JP	Z, DS1501RTC_SETBYT			; Set NVRAM Byte Value
+	DEC	A
+	JP	Z, DS1501RTC_GETBLK			; Get NVRAM Data Block Value
+	DEC	A
+	JP	Z, DS1501RTC_SETBLK			; Set NVRAM Data Block Value
+	DEC	A
+	JP	Z, DS1501RTC_GETALM			; Get Alarm
+	DEC	A
+	JP	Z, DS1501RTC_SETALM			; Set Alarm
+;
+; NVRAM FUNCTIONS ARE NOT IMPLEMENTED YET
+;
+DS1501RTC_GETBYT:
+DS1501RTC_SETBYT:
+DS1501RTC_GETBLK:
+DS1501RTC_SETBLK:
+	CALL	PANIC
+
+; RTC Get Time
+;   A: Result (OUT), 0=OK, Z=OK, NZ=Error
+;   HL: Date/Time Buffer (OUT)
+; Buffer format is BCD: YYMMDDHHMMSS
+; 24 hour time format is assumed
+;
+DS1501RTC_GETTIM:
+	EX	DE, HL
+	CALL	DS1501RTC_LOAD
+	; Now copy to read destination (Interbank Save)
+	LD	A, BID_BIOS			; Copy from BIOS bank
+	LD	(HB_SRCBNK), A			; Set it
+	LD	A, (HB_INVBNK)			; Copy to current user bank
+	LD	(HB_DSTBNK), A			; Set it
+	LD	BC, DS1501RTC_BUFSIZE		; Length is 6 bytes
+#IF (INTMODE == 1)
+	DI
+#ENDIF
+	CALL	HB_BNKCPY			; Copy the clock data
+#IF (INTMODE == 1)
+	EI
+#ENDIF
+;
+	; CLEAN UP AND RETURN
+	XOR	A				; SIGNAL SUCCESS
+	RET					; AND RETURN
+;
+; RTC Set Time
+;   A: Result (OUT), 0=OK, Z=OK, NZ=Error
+;   HL: Date/Time Buffer (IN)
+; Buffer Format is BCD: YYMMDDHHMMSS
+; 24 hour time format is assumed
+;
+DS1501RTC_SETTIM:
+;
+	; Copy incoming time data to our time buffer
+	LD	A, (HB_INVBNK)			; Copy from current user bank
+	LD	(HB_SRCBNK), A			; Set it
+	LD	A, BID_BIOS			; Copy to BIOS bank
+	LD	(HB_DSTBNK), A			; Set it
+	LD	DE, DS1501RTC_BUF			; Destination Address
+	LD	BC, DS1501RTC_BUFSIZE		; Length is 6 bytes
+#IF (INTMODE == 1)
+	DI
+#ENDIF
+	CALL	HB_BNKCPY			; Copy the clock data
+#IF (INTMODE == 1)
+	EI
+#ENDIF
+	; Write to clock
+	LD	HL, DS1501RTC_BUF
+	CALL	DS1501RTC_SUSPEND
+	LD	A, (HL)
+	OUT	(DS1501RTC_YEAR), A			; Write Year
+	INC	HL
+	LD	A, (HL)
+	OUT	(DS1501RTC_MONTH), A		; Write Month
+	INC	HL
+	LD	A, (HL)
+	OUT	(DS1501RTC_DAY), A			; Write Day
+	INC	HL
+	LD	A, (HL)
+	OUT	(DS1501RTC_HOUR), A			; Write Hour
+	INC	HL
+	LD	A, (HL)
+	OUT	(DS1501RTC_MIN), A			; Write Minute
+	INC	HL
+	LD	A, (HL)
+	OUT	(DS1501RTC_SEC), A			; Write Second
+	CALL	DS1501RTC_RESUME
+	; clean up and return
+	XOR	A				; Signal success
+	RET					; And return
+
+; RTC Get Alarm
+;   A: Result (OUT), 0=OK, Z=OK, NZ=Error
+;   HL: Date/Time Buffer (OUT)
+; Buffer format is BCD: YYMMDDHHMMSS
+; 24 hour time format is assumed
+;
+DS1501RTC_GETALM:
+	EX	DE, HL
+	LD	HL, DS1501RTC_BUF
+	PUSH	HL				; Save address of source buffer
+	CALL	DS1501RTC_SUSPEND
+	XOR	A
+	LD	(HL), A				; Read Year
+	INC	HL
+	LD	(HL), A				; Read Month
+	INC	HL
+	IN	A, (DS1501RTC_DAY_ALM)		; Read Day
+	LD	(HL), A
+	INC	HL
+	IN	A, (DS1501RTC_HOUR_ALM)		; Read Hour
+	LD	(HL), A
+	INC	HL
+	IN	A, (DS1501RTC_MIN_ALM)		; Read Minute
+	LD	(HL), A
+	INC	HL
+	IN	A, (DS1501RTC_SEC_ALM)		; Read Second
+	LD	(HL), A
+	CALL	DS1501RTC_RESUME
+	POP	HL				; Restore address of source buffer
+	; Now copy to read destination (Interbank Save)
+	LD	A, BID_BIOS			; Copy from BIOS bank
+	LD	(HB_SRCBNK), A			; Set it
+	LD	A, (HB_INVBNK)			; Copy to current user bank
+	LD	(HB_DSTBNK), A			; Set it
+	LD	BC, DS1501RTC_BUFSIZE		; Length is 6 bytes
+#IF (INTMODE == 1)
+	DI
+#ENDIF
+	CALL	HB_BNKCPY			; Copy the clock data
+#IF (INTMODE == 1)
+	EI
+#ENDIF
+;
+	; CLEAN UP AND RETURN
+	XOR	A				; SIGNAL SUCCESS
+	RET					; AND RETURN
+;
+; RTC Set Alarm
+;   A: Result (OUT), 0=OK, Z=OK, NZ=Error
+;   HL: Date/Time Buffer (IN)
+; Buffer Format is BCD: YYMMDDHHMMSS
+; 24 hour time format is assumed
+;
+DS1501RTC_SETALM:
+	; Copy incoming time data to our time buffer
+	LD	A, (HB_INVBNK)			; Copy from current user bank
+	LD	(HB_SRCBNK), A			; Set it
+	LD	A, BID_BIOS			; Copy to BIOS bank
+	LD	(HB_DSTBNK), A			; Set it
+	LD	DE, DS1501RTC_BUF			; Destination Address
+	LD	BC, DS1501RTC_BUFSIZE		; Length is 6 bytes
+#IF (INTMODE == 1)
+	DI
+#ENDIF
+	CALL	HB_BNKCPY			; Copy the clock data
+#IF (INTMODE == 1)
+	EI
+#ENDIF
+	; Write to clock
+	LD	HL, DS1501RTC_BUF_DAY
+	CALL	DS1501RTC_SUSPEND
+	LD	A, (HL)
+	OUT	(DS1501RTC_DAY_ALM), A		; Write Day
+	INC	HL
+	LD	A, (HL)
+	OUT	(DS1501RTC_HOUR_ALM), A		; Write Hour
+	INC	HL
+	LD	A, (HL)
+	OUT	(DS1501RTC_MIN_ALM), A		; Write Minute
+	INC	HL
+	LD	A, (HL)
+	OUT	(DS1501RTC_SEC_ALM), A		; Write Second
+	CALL	DS1501RTC_RESUME
+	; clean up and return
+	XOR	A				; Signal success
+	RET					; And return
+
+DS1501RTC_SUSPEND:
+	IN	A, (DS1501RTC_CONTROLB)		; Suspend Clock
+	AND	~DS1501RTC_TE
+	OUT	(DS1501RTC_CONTROLB), A
+	RET
+
+DS1501RTC_RESUME:
+	IN	A, (DS1501RTC_CONTROLB)		; Resume Clock
+	OR	DS1501RTC_TE
+	OUT	(DS1501RTC_CONTROLB), A
+	RET
+
+DS1501RTC_LOAD:
+	LD	HL, DS1501RTC_BUF
+	PUSH	HL				; Save address of source buffer
+	CALL	DS1501RTC_SUSPEND
+	IN	A, (DS1501RTC_YEAR)			; Read Year
+	LD	(HL), A
+	INC	HL
+	IN	A, (DS1501RTC_MONTH)		; Read Month
+	LD	(HL), A
+	INC	HL
+	IN	A, (DS1501RTC_DAY)			; Read Day
+	LD	(HL), A
+	INC	HL
+	IN	A, (DS1501RTC_HOUR)			; Read Hour
+	LD	(HL), A
+	INC	HL
+	IN	A, (DS1501RTC_MIN)			; Read Minute
+	LD	(HL), A
+	INC	HL
+	IN	A, (DS1501RTC_SEC)			; Read Second
+	LD	(HL), A
+	CALL	DS1501RTC_RESUME
+	POP	HL				; Restore address of source buffer
+	RET
+
+; Working Variables
+
+DS1501RTC_BUF:
+DS1501RTC_BUF_YEAR:	.DB	0		; Year
+DS1501RTC_BUF_MON:	.DB	0		; Month
+DS1501RTC_BUF_DAY:	.DB	0		; Day
+DS1501RTC_BUF_HOUR:	.DB	0		; Hour
+DS1501RTC_BUF_MIN:	.DB	0		; Minute
+DS1501RTC_BUF_SEC:	.DB	0		; Second

Source/HBIOS/dsrtc.asm

@@ -66,28 +66,28 @@
 ; RTC LATCH WRITE
 ; ---------------
 ;
-; BIT	SBC	SBC-004	MFPIC	N8	N8-CSIO	MK4	SC130	SC131	SC126		MBC
-; -----	-------	-------	-------	-------	-------	-------	-------	-------	---------------	-------
-; D7	RTC_OUT RTC_OUT	--	RTC_OUT RTC_OUT	RTC_OUT	--	--	RTC_OUT,I2C_SDA	RTC_OUT
-; D6	RTC_CLK RTC_CLK	--	RTC_CLK RTC_CLK	RTC_CLK	--	--	RTC_CLK		RTC_CLK
-; D5	/RTC_WE /RTC_WE	--	/RTC_WE /RTC_WE	/RTC_WE	--	--	/RTC_WE		/RTC_WE
-; D4	RTC_CE	RTC_CE	--	RTC_CE  RTC_CE	RTC_CE	--	--	RTC_CE		RTC_CE
-; D3	NC	CLKSEL	/RTC_CE	NC	NC	NC	--	--	/SPI_CS2	CLKSEL
-; D2	NC	SPK	RTC_CLK	SPI_CS	SPI_CS	NC	/SPI_CS1/SPI_CS1/SPI_CS1	SPK
-; D1	--	--	RTC_WE	SPI_CLK	NC	NC	--	--	FS		LED1
-; D0	--	--	RTC_OUT	SPI_DI	NC	NC	--	--	I2C_SCL		LED0
+; BIT	SBC	SBC-004	MFPIC	N8	N8-CSIO	MK4	SC130	SC131	SC126		MBC	RPH
+; -----	-------	-------	-------	-------	-------	-------	-------	-------	---------------	------- -------
+; D7	RTC_OUT RTC_OUT	--	RTC_OUT RTC_OUT	RTC_OUT	--	--	RTC_OUT,I2C_SDA	RTC_OUT	RTC_OUT
+; D6	RTC_CLK RTC_CLK	--	RTC_CLK RTC_CLK	RTC_CLK	--	--	RTC_CLK		RTC_CLK	RTC_CLK
+; D5	/RTC_WE /RTC_WE	--	/RTC_WE /RTC_WE	/RTC_WE	--	--	/RTC_WE		/RTC_WE	/RTC_WE
+; D4	RTC_CE	RTC_CE	--	RTC_CE  RTC_CE	RTC_CE	--	--	RTC_CE		RTC_CE	RTC_CE
+; D3	NC	CLKSEL	/RTC_CE	NC	NC	NC	--	--	/SPI_CS2	CLKSEL	--
+; D2	NC	SPK	RTC_CLK	SPI_CS	SPI_CS	NC	/SPI_CS1/SPI_CS1/SPI_CS1	SPK	--
+; D1	--	--	RTC_WE	SPI_CLK	NC	NC	--	--	FS		LED1	--
+; D0	--	--	RTC_OUT	SPI_DI	NC	NC	--	--	I2C_SCL		LED0	--
 ;
 ; RTC LATCH READ
 ; --------------
 ;
-; D7	--	--	--	--	--	--	--	--	I2C_SDA		--
-; D6	CFG	CFG	--	SPI_DO	CFG	--	--	--	--		CFG
-; D5	--	--	--	--	--	--	--	--	--		--
-; D4	--	--	--	--	--	--	--	--	--		--
-; D3	--	--	--	--	--	--	--	--	--		--
-; D2	--	--	--	--	--	--	--	--	--		--
-; D1	----	--	--	--	--	--	--	--	--		CLKSEL
-; D0	RTC_IN	RTC_IN	RTC_IN	RTC_IN	RTC_IN	RTC_IN	--	--	RTC_IN		RTC_IN
+; D7	--	--	--	--	--	--	--	--	I2C_SDA		--	--
+; D6	CFG	CFG	--	SPI_DO	CFG	--	--	--	--		CFG	--
+; D5	--	--	--	--	--	--	--	--	--		--	--
+; D4	--	--	--	--	--	--	--	--	--		--	--
+; D3	--	--	--	--	--	--	--	--	--		--	--
+; D2	--	--	--	--	--	--	--	--	--		--	--
+; D1	----	--	--	--	--	--	--	--	--		CLKSEL	--
+; D0	RTC_IN	RTC_IN	RTC_IN	RTC_IN	RTC_IN	RTC_IN	--	--	RTC_IN		RTC_IN	RTC_IN
 ;
 #IF (DSRTCMODE == DSRTCMODE_STD)
 ;
@@ -118,7 +118,7 @@ DS2d8k		.EQU	%10101011	; 2 DIODES 8K RESISTOR
 ;
 #IF (DSRTCMODE == DSRTCMODE_MFPIC)
 ;
-DSRTC_IO	.EQU	$43		; RTC PORT ON MF/PIC
+DSRTC_IO	.EQU	$13		; RTC PORT ON MF/PIC
 ;
 DSRTC_DATA	.EQU	%00000001	; BIT 0 IS RTC DATA OUT
 DSRTC_CLK	.EQU	%00000100	; BIT 2 IS RTC CLOCK (CLK)

Source/HBIOS/gdc.asm

@@ -0,0 +1,331 @@
+;======================================================================
+;	UPD7220 GRAPHICS DEVICE CONTROLLER
+;======================================================================
+;
+;======================================================================
+; GDC DRIVER - CONSTANTS
+;======================================================================
+;
+#IF (GDCMODE == GDCMODE_ECB)
+GDC_BASE	.EQU	$??		; GDC BASE I/O PORT
+GDC_DAC_BASE	.EQU	$??		; RAMDAC BASE I/O PORT
+#ENDIF
+;
+#IF (GDCMODE == GDCMODE_RPH)
+GDC_KBDDATA	.EQU	$8C		; KBD CTLR DATA PORT
+GDC_KBDST	.EQU	$8D		; KBD CTLR STATUS/CMD PORT
+GDC_BASE	.EQU	$90		; GDC BASE I/O PORT
+GDC_DAC_BASE	.EQU	$98		; RAMDAC BASE I/O PORT
+#ENDIF
+;
+GDC_STAT	.EQU	GDC_BASE + 0		; STATUS PORT
+GDC_CMD		.EQU	GDC_BASE + 1		; COMMAND PORT
+GDC_PARAM	.EQU	GDC_BASE + 0		; PARAM PORT
+GDC_READ	.EQU	GDC_BASE + 1		; READ PORT
+GDC_DAC_WR	.EQU	GDC_DAC_BASE + 0	; RAMDAC ADR WRITE
+GDC_DAC_RD      .EQU	GDC_DAC_BASE + 3	; RAMDAC ADR READ
+GDC_DAC_PALRAM  .EQU	GDC_DAC_BASE + 1	; RAMDAC PALETTE RAM
+GDC_DAC_PIXMSK  .EQU	GDC_DAC_BASE + 2	; RAMDAC PIXEL READ MASK
+GDC_DAC_OVL_WR  .EQU	GDC_DAC_BASE + 4	; RAMDAC OVERLAY WRITE
+GDC_DAC_OVL_RD  .EQU	GDC_DAC_BASE + 7	; RAMDAC OVERLAY READ
+GDC_DAC_OVL_RAM .EQU	GDC_DAC_BASE + 5	; RAMDAC OVERLAY RAM
+;
+GDC_ROWS	.EQU	25
+GDC_COLS	.EQU	80
+;
+; *** TODO: CGA AND EGA ARE PLACEHOLDERS.  THESE EQUATES SHOULD
+; BE USED TO ALLOW FOR MULTIPLE MONITOR TIMINGS AND/OR FONT
+; DEFINITIONS.
+;
+#IF (GDCMON == GDCMON_CGA)
+  #DEFINE	USEFONTCGA
+  #DEFINE	GDC_FONT FONTCGA
+#ENDIF
+;
+#IF (GDCMON == GDCMON_EGA)
+  #DEFINE	USEFONT8X16
+  #DEFINE	GDC_FONT FONT8X16
+#ENDIF
+;
+TERMENABLE	.SET	TRUE		; INCLUDE TERMINAL PSEUDODEVICE DRIVER
+;
+;======================================================================
+; GDC DRIVER - INITIALIZATION
+;======================================================================
+;
+GDC_INIT:
+	LD	IY,GDC_IDAT		; POINTER TO INSTANCE DATA
+	
+	CALL	NEWLINE
+	PRTS("GDC: MODE=$")
+#IF (GDCMODE == GDCMODE_ECB)
+	PRTS("ECB$")
+#ENDIF
+#IF (GDCMODE == GDCMODE_RPH)
+	PRTS("RPH$")
+#ENDIF
+;
+#IF (GDCMON == GDCMON_CGA)
+	PRTS(" CGA$")
+#ENDIF	
+#IF (GDCMON == GDCMON_EGA)
+	PRTS(" EGA$")
+#ENDIF	
+;
+	PRTS(" IO=0x$")
+	LD	A,GDC_BASE
+	CALL	PRTHEXBYTE
+	CALL	GDC_PROBE		; CHECK FOR HW PRESENCE
+	JR	Z,GDC_INIT1		; CONTINUE IF HW PRESENT
+;
+	; HARDWARE NOT PRESENT
+	PRTS(" NOT PRESENT$")
+	OR	$FF			; SIGNAL FAILURE
+	RET
+;
+GDC_INIT1:
+	CALL 	GDC_CRTINIT		; SETUP THE GDC CHIP REGISTERS
+	CALL	GDC_VDARES		; RESET GDC
+	CALL	KBD_INIT		; INITIALIZE KEYBOARD DRIVER
+
+	; ADD OURSELVES TO VDA DISPATCH TABLE
+	LD	BC,GDC_FNTBL		; BC := FUNCTION TABLE ADDRESS
+	LD	DE,GDC_IDAT		; DE := GDC INSTANCE DATA PTR
+	CALL	VDA_ADDENT		; ADD ENTRY, A := UNIT ASSIGNED
+
+	; INITIALIZE EMULATION
+	LD	C,A			; C := ASSIGNED VIDEO DEVICE NUM
+	LD	DE,GDC_FNTBL		; DE := FUNCTION TABLE ADDRESS
+	LD	HL,GDC_IDAT		; HL := GDC INSTANCE DATA PTR
+	CALL	TERM_ATTACH		; DO IT
+
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+;======================================================================
+; GDC DRIVER - VIDEO DISPLAY ADAPTER (VDA) FUNCTIONS
+;======================================================================
+;
+GDC_FNTBL:
+	.DW	GDC_VDAINI
+	.DW	GDC_VDAQRY
+	.DW	GDC_VDARES
+	.DW	GDC_VDADEV
+	.DW	GDC_VDASCS
+	.DW	GDC_VDASCP
+	.DW	GDC_VDASAT
+	.DW	GDC_VDASCO
+	.DW	GDC_VDAWRC
+	.DW	GDC_VDAFIL
+	.DW	GDC_VDACPY
+	.DW	GDC_VDASCR
+	.DW	KBD_STAT
+	.DW	KBD_FLUSH
+	.DW	KBD_READ
+	.DW	GDC_VDARDC
+#IF (($ - GDC_FNTBL) != (VDA_FNCNT * 2))
+	.ECHO	"*** INVALID GDC FUNCTION TABLE ***\n"
+	!!!!!
+#ENDIF
+;
+GDC_VDAINI:
+	; RESET VDA
+	CALL	GDC_VDARES		; RESET VDA
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+GDC_VDAQRY:	; VIDEO INFORMATION QUERY
+	LD	C,$00		; MODE ZERO IS ALL WE KNOW
+	LD	D,GDC_ROWS	; ROWS
+	LD	E,GDC_COLS	; COLS
+	LD	HL,0		; EXTRACTION OF CURRENT BITMAP DATA NOT SUPPORTED YET
+	XOR	A		; SIGNAL SUCCESS
+	RET
+;
+GDC_VDARES:	; VIDEO SYSTEM RESET
+	; *** TODO: RESET VIDEO SYSTEM HERE, CLEAR SCREEN,
+	; CURSOR TO TOP LEFT, CLEAR ATTRIBUTES
+	XOR	A
+	RET
+;
+GDC_VDADEV:	; VIDEO DEVICE INFORMATION
+	LD	D,VDADEV_GDC	; D := DEVICE TYPE
+	LD	E,0		; E := PHYSICAL UNIT IS ALWAYS ZERO
+	LD	H,0		; H := 0, DRIVER HAS NO MODES
+	LD	L,GDC_BASE	; L := BASE I/O ADDRESS
+	XOR	A		; SIGNAL SUCCESS
+	RET
+;
+GDC_VDASCS:	; SET CURSOR STYLE
+	CALL	SYSCHK		; NOT IMPLEMENTED (YET)
+	LD	A,ERR_NOTIMPL
+	OR	A
+	RET
+
+GDC_VDASCP:	; SET CURSOR POSITION
+	CALL	GDC_XY		; SET CURSOR POSITION
+	XOR	A		; SIGNAL SUCCESS
+	RET
+
+GDC_VDASAT:	; SET ATTRIBUTES
+	LD	A,E		; GET THE INCOMING ATTRIBUTE
+	LD	(GDC_ATTR),A	; AND SAVE FOR LATER
+	XOR	A		; SIGNAL SUCCESS
+	RET
+
+GDC_VDASCO:	; SET COLOR
+	LD	A,E		; GET THE INCOMING COLOR
+	LD	(GDC_COLOR),A	; AND SAVE FOR LATER
+	XOR	A		; SIGNAL SUCCESS
+	RET
+
+GDC_VDAWRC:	; WRITE CHARACTER
+	LD	A,E		; CHARACTER TO WRITE GOES IN A
+	CALL	GDC_PUTCHAR	; PUT IT ON THE SCREEN
+	XOR	A		; SIGNAL SUCCESS
+	RET
+
+GDC_VDAFIL:	; FILL WITH CHARACTER
+	LD	A,E		; FILL CHARACTER GOES IN A
+	EX	DE,HL		; FILL LENGTH GOES IN DE
+	CALL	GDC_FILL	; DO THE FILL
+	XOR	A		; SIGNAL SUCCESS
+	RET
+
+GDC_VDACPY:	; COPY CHARACTERS/ATTRIBUTES
+	; LENGTH IN HL, SOURCE ROW/COL IN DE, DEST IS GDC_POS
+	; BLKCPY USES: HL=SOURCE, DE=DEST, BC=COUNT
+	PUSH	HL		; SAVE LENGTH
+	CALL	GDC_XY2IDX	; ROW/COL IN DE -> SOURCE ADR IN HL
+	POP	BC		; RECOVER LENGTH IN BC
+	LD	DE,(GDC_POS)	; PUT DEST IN DE
+	JP	GDC_BLKCPY	; DO A BLOCK COPY
+
+GDC_VDASCR:	; SCROLL ENTIRE SCREEN
+	LD	A,E		; LOAD E INTO A
+	OR	A		; SET FLAGS
+	RET	Z		; IF ZERO, WE ARE DONE
+	PUSH	DE		; SAVE E
+	JP	M,GDC_VDASCR1	; E IS NEGATIVE, REVERSE SCROLL
+	CALL	GDC_SCROLL	; SCROLL FORWARD ONE LINE
+	POP	DE		; RECOVER E
+	DEC	E		; DECREMENT IT
+	JR	GDC_VDASCR	; LOOP
+GDC_VDASCR1:
+	CALL	GDC_RSCROLL	; SCROLL REVERSE ONE LINE
+	POP	DE		; RECOVER E
+	INC	E		; INCREMENT IT
+	JR	GDC_VDASCR	; LOOP
+;
+GDC_VDARDC:	; READ CHAR/ATTR VALUE FROM VIDEO BUFFER
+	OR	$FF		; UNSUPPORTED FUNCTION
+	RET
+;
+;======================================================================
+; GDC DRIVER - PRIVATE DRIVER FUNCTIONS
+;======================================================================
+;
+;----------------------------------------------------------------------
+; PROBE FOR GDC HARDWARE
+;----------------------------------------------------------------------
+;
+; ON RETURN, ZF SET INDICATES HARDWARE FOUND
+;
+; *** TODO: IMPLEMENT THIS
+;
+GDC_PROBE:
+	XOR	A			; SIGNAL SUCCESS
+	RET				; RETURN WITH ZF SET BASED ON CP
+;
+;----------------------------------------------------------------------
+; DISPLAY CONTROLLER CHIP INITIALIZATION
+;----------------------------------------------------------------------
+;
+; *** TODO: IMPLEMENT THIS
+;
+GDC_CRTINIT:
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+;----------------------------------------------------------------------
+; SET CURSOR POSITION TO ROW IN D AND COLUMN IN E
+;----------------------------------------------------------------------
+;
+GDC_XY:
+	CALL	GDC_XY2IDX		; CONVERT ROW/COL TO BUF IDX
+	LD	(GDC_POS),HL		; SAVE THE RESULT (DISPLAY POSITION)
+	; *** TODO: MOVE THE CURSOR
+	RET
+;
+;----------------------------------------------------------------------
+; CONVERT XY COORDINATES IN DE INTO LINEAR INDEX IN HL
+; D=ROW, E=COL
+;----------------------------------------------------------------------
+;
+GDC_XY2IDX:
+	LD	A,E			; SAVE COLUMN NUMBER IN A
+	LD	H,D			; SET H TO ROW NUMBER
+	LD	E,GDC_COLS		; SET E TO ROW LENGTH
+	CALL	MULT8			; MULTIPLY TO GET ROW OFFSET
+	LD	E,A			; GET COLUMN BACK
+	ADD	HL,DE			; ADD IT IN
+	RET				; RETURN
+;
+;----------------------------------------------------------------------
+; WRITE VALUE IN A TO CURRENT VDU BUFFER POSITION, ADVANCE CURSOR
+;----------------------------------------------------------------------
+;
+GDC_PUTCHAR:
+	; *** TODO: IMPLEMENT THIS
+	RET
+;
+;----------------------------------------------------------------------
+; FILL AREA IN BUFFER WITH SPECIFIED CHARACTER AND CURRENT COLOR/ATTRIBUTE
+; STARTING AT THE CURRENT FRAME BUFFER POSITION
+;   A: FILL CHARACTER
+;   DE: NUMBER OF CHARACTERS TO FILL
+;----------------------------------------------------------------------
+;
+GDC_FILL:
+	; *** TODO: IMPLEMENT THIS
+	RET
+;
+;----------------------------------------------------------------------
+; SCROLL ENTIRE SCREEN FORWARD BY ONE LINE (CURSOR POSITION UNCHANGED)
+;----------------------------------------------------------------------
+;
+GDC_SCROLL:
+	; *** TODO: IMPLEMENT THIS
+	RET
+;
+;----------------------------------------------------------------------
+; REVERSE SCROLL ENTIRE SCREEN BY ONE LINE (CURSOR POSITION UNCHANGED)
+;----------------------------------------------------------------------
+;
+GDC_RSCROLL:
+	; *** TODO: IMPLEMENT THIS
+	RET
+;
+;----------------------------------------------------------------------
+; BLOCK COPY BC BYTES FROM HL TO DE
+;----------------------------------------------------------------------
+;
+GDC_BLKCPY:
+	; *** TODO: IMPLEMENT THIS
+	RET
+;
+;==================================================================================================
+;   GDC DRIVER - DATA
+;==================================================================================================
+;
+GDC_ATTR	.DB	0	; CURRENT ATTRIBUTES
+GDC_COLOR	.DB	0	; CURRENT COLOR
+GDC_POS		.DW 	0	; CURRENT DISPLAY POSITION
+;
+;==================================================================================================
+;   GDC DRIVER - INSTANCE DATA
+;==================================================================================================
+;
+GDC_IDAT:
+	.DB	GDC_KBDST
+	.DB	GDC_KBDDATA

Source/HBIOS/hbios.asm

@@ -219,6 +219,7 @@ RTCDEF		.SET	RTCDEF | %00001000	; INITIAL SPEED LOW
 ;
 	.FILL	(000H - $),0FFH		; RST 0
 	JP	HB_START
+	.DB	0			; SIG PTR STARTS AT $0004
 	.DW	ROM_SIG
 	.FILL	(008H - $),0FFH		; RST 8
 	JP	HB_INVOKE		; INVOKE HBIOS FUNCTION
@@ -556,6 +557,28 @@ HBX_RAMX:
 HBX_MMA	.DB	0			; TEMPORARY STORAGE FOR REG A
 #ENDIF
 ;
+#IF (MEMMGR == MM_RPH)
+	BIT	7,A			; TEST BIT 7 FOR RAM VS. ROM
+	JR	Z,HBX_ROM		; IF NOT SET, SELECT ROM PAGE
+;
+HBX_RAM:
+	AND	%00011111		; AVOID WRAPPING BITS
+	RLCA				; SCALE SELECTOR TO
+	RLCA				; ... GO FROM Z180 4K PAGE SIZE
+	RLCA				; ... TO DESIRED 32K PAGE SIZE
+	OUT0	(Z180_BBR),A		; WRITE TO BANK BASE
+	LD	A,RPH_DEFACR | 80H	; SELECT RAM BY SETTING BIT 7
+	OUT0	(RPH_ACR),A		; ... IN RPH ACR REGISTER
+	RET				; DONE
+;
+HBX_ROM:
+	OR	RPH_DEFACR		; COMBINE WITH DEFAULT BITS
+	OUT0	(RPH_ACR),A		; BANK INDEX TO RPH ACR REGISTER
+	XOR	A			; ZERO ACCUM
+	OUT0	(Z180_BBR),A		; ZERO BANK BASE
+	RET				; DONE
+#ENDIF
+;
 ;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
 ; Copy Data - Possibly between banks.  This resembles CP/M 3, but
 ;  usage of the HL and DE registers is reversed.
@@ -1101,6 +1124,11 @@ Z280_BOOTERR	.TEXT	"\r\n\r\n*** Application mode boot not supported under Z280 n
 	OUT0	(N8_ACR),A		; ... REGISTER IS INITIALIZED
 #ENDIF
 ;
+#IF (PLATFORM == PLT_RPH)
+	LD	A,RPH_DEFACR		; ENSURE RPH ACR
+	OUT0	(RPH_ACR),A		; ... REGISTER IS INITIALIZED
+#ENDIF
+;
 #IF (DIAGENABLE)
 	LD	A,%00000001
 	OUT	(DIAGPORT),A
@@ -1238,7 +1266,7 @@ Z280_INITZ:
 	LD	A,$F0
 	OUT0	(Z180_DCNTL),A
 
-  #IF ((MEMMGR == MM_Z180) | (MEMMGR == MM_N8))
+  #IF ((MEMMGR == MM_Z180) | (MEMMGR == MM_N8) | (MEMMGR == MM_RPH))
 	; Z180 MMU SETUP
 	LD	A,$80
 	OUT0	(Z180_CBAR),A		; SETUP FOR 32K/32K BANK CONFIG
@@ -1919,20 +1947,20 @@ HB_CPUSPD2:
 ;
 	LD	HL,(HB_CPUOSC)	; INIT HL TO CPU OSC FREQ (KHZ)
 ;
-  #IF (Z180_CLKDIV == 0)
 	; ADJUST HL TO REFLECT HALF SPEED OPERATION
 	SRL	H		; ADJUST HL ASSUMING
 	RR	L		; HALF SPEED OPERATION
-  #ENDIF
 ;	
-  #IF (Z180_CLKDIV == 1)
+  #IF (Z180_CLKDIV >= 1)
 	LD	A,(HB_CPUTYPE)	; GET CPU TYPE
 	CP	2		; Z8S180 REV K OR BETTER?
 	JR	C,HB_CPU3	; IF NOT, NOT POSSIBLE!
 	; SET CLOCK DIVIDE TO 1 RESULTING IN FULL XTAL SPEED
 	LD	A,$80
 	OUT0	(Z180_CCR),A
-	; HL ALREADY REFLECTS FULL SPEED OPERATION
+	; ADJUST HL TO REFLECT FULL SPEED OPERATION
+	SLA	L
+	RL	H
   #ENDIF
 ;
   #IF (Z180_CLKDIV >= 2)
@@ -2200,6 +2228,21 @@ NOT_REC_M0:
 	DIAG(%01111111)
 	LED(%00000011)
 ;
+;
+;
+;
+#IF (BOOT_DELAY > 100)
+	.ECHO	"*** ERROR: INVALID BOOT_DELAY (BOOT_DELAY > 100)!!!\n"
+	!!!	; FORCE AN ASSEMBLY ERROR
+#ENDIF
+;
+#IF (BOOT_DELAY > 0)
+	LD	B,BOOT_DELAY * 2	; SCALE TO 1/2 SEC
+HB_BOOTDLY:
+	CALL	LDELAY			; 1/2 SECOND DELAY
+	DJNZ	HB_BOOTDLY		; LOOP TILL DONE
+#ENDIF
+;
 ; PRIOR TO THIS POINT, CONSOLE I/O WAS NOT AVAILABLE UNLESS DIRECTED TO DEBUG OUTPUT I.E. XIO
 ; NOW THAT HBIOS IS READY, SET THE CONSOLE UNIT TO ACTIVATE CONSOLE I/O
 ; VIA HBIOS.
@@ -2257,6 +2300,18 @@ NXTMIO:	LD	A,(HL)
 	CALL	PRTSTRD
 	.TEXT	"HBIOS MUTEX ENABLED$"
 #ENDIF
+;
+; DISPLAY RECOVERY MODE MESSAGE
+;
+#IF (BT_REC_TYPE != BT_REC_NONE)
+	LD	A,(HB_BOOT_REC)		; IF WE ARE IN RECOVERY MODE
+	OR	A			; DISPLAY RECOVERY MODE MESSAGE
+	JR	Z,NOT_REC_M2
+	CALL	NEWLINE
+	CALL	PRTSTRD
+	.TEXT	"RECOVERY MODE$"
+#ENDIF
+NOT_REC_M2:
 ;
 	DIAG(%11111111)
 ;
@@ -2419,6 +2474,9 @@ HB_Z280BUS1:
 #ENDIF
 #IF (MEMMGR == MM_MBC)
 	.TEXT	"MBC$"
+#ENDIF
+#IF (MEMMGR == MM_RPH)
+	.TEXT	"RPH$"
 #ENDIF
 	CALL	PRTSTRD
 	.TEXT	" MMU$"
@@ -2769,6 +2827,10 @@ INITSYS4:
 	LDCTL	(C),HL
 #ENDIF
 ;
+#IFDEF TESTING
+	CALL	SND_BEEP
+#ENDIF
+;
 #IFNDEF ROMBOOT
 ;
 	; COPY OS IMAGE: BID_USR:<IMG START> --> BID_USR:0
@@ -2874,6 +2936,9 @@ HB_PCINITTBL:
 #IF (PIOENABLE)
 	.DW	PIO_PREINIT
 #ENDIF
+#IF LPTENABLE)
+	.DW	LPT_PREINIT
+#ENDIF
 #IF (PIO_4P | PIO_ZP)
 	.DW	PIO_PREINIT
 #ENDIF
@@ -2926,9 +2991,24 @@ HB_INITTBL:
 #IF (ACIAENABLE)
 	.DW	ACIA_INIT
 #ENDIF
+#IF (PIOENABLE)
+	.DW	PIO_INIT
+#ENDIF
+#IF (LPTENABLE)
+	.DW	LPT_INIT
+#ENDIF
+#IF (PIO_4P | PIO_ZP)
+	.DW	PIO_INIT
+#ENDIF
+#IF (UFENABLE)
+	.DW	UF_INIT
+#ENDIF
 #IF (DSRTCENABLE)
 	.DW	DSRTC_INIT
 #ENDIF
+#IF (DS1501RTCENABLE)
+	.DW	DS1501RTC_INIT
+#ENDIF
 #IF (BQRTCENABLE)
 	.DW	BQRTC_INIT
 #ENDIF
@@ -2954,8 +3034,8 @@ HB_INITTBL:
 #IF (VGAENABLE)
 	.DW	VGA_INIT
 #ENDIF
-#IF (NECENABLE)
-	.DW	NEC_INIT
+#IF (GDCENABLE)
+	.DW	GDC_INIT
 #ENDIF
 #IF (TMSENABLE)
 	.DW	TMS_INIT
@@ -2993,15 +3073,6 @@ HB_INITTBL:
 #IF (PPPENABLE)
 	.DW	PPP_INIT
 #ENDIF
-#IF (PIOENABLE)
-	.DW	PIO_INIT
-#ENDIF
-#IF (PIO_4P | PIO_ZP)
-	.DW	PIO_INIT
-#ENDIF
-#IF (UFENABLE)
-	.DW	UF_INIT
-#ENDIF
 
 ;
 HB_INITTBLLEN	.EQU	(($ - HB_INITTBL) / 2)
@@ -3647,7 +3718,7 @@ SND_ADDENT:
 ;	WORD	UNIT SPECIFIC DATA (TYPICALLY A DEVICE INSTANCE DATA ADDRESS)
 ;
 SND_FNCNT	.EQU	8		; NUMBER OF SND FUNCS (FOR RANGE CHECK)
-SND_MAX		.EQU	3		; UP TO 2 UNITS
+SND_MAX		.EQU	4		; UP TO 4 UNITS
 SND_SIZ		.EQU	SND_MAX * 4	; EACH ENTRY IS 4 BYTES
 ;
 		.DB	SND_FNCNT	; SND FUNCTION COUNT (FOR RANGE CHECK)
@@ -3656,6 +3727,49 @@ SND_CNT		.DB	0		; ENTRY COUNT PREFIX
 SND_TBL		.FILL	SND_SIZ,0	; SPACE FOR ENTRIES
 ;
 ;==================================================================================================
+;   SPEAKER BEEP ROUTINE
+;==================================================================================================
+;
+; ROUTINE TO BEEP THE DEAULT SOUND UNIT
+; NEED TO CHECK FOR EXISTENCE OF SOUND UNIT
+; WHICH CHANNEL SHOULD BE USED?  IS THERE A GOOD DEFAULT CHANNEL?
+;
+SND_BEEP:
+	; CHECK FOR AT LEAST 1 SOUND DEVICE
+	LD	A,(SND_CNT)		; GET SOUND UNIT COUNT
+	OR	A			; CHECK FOR ZERO
+	RET	Z			; BAIL OUT IF NO SOUND UNITS
+	
+	; PLAY A BEEP ON SOUND DEVICE UNIT 0
+	LD	B,$50			; SOUND RESET FUNCTION
+	LD	C,0			; SOUND UNIT NUMBER
+	CALL	SND_DISPATCH		; DO IT
+	LD	B,$51			; VOLUME
+	LD	C,0			; SOUND UNIT NUMBER
+	LD	L,$FF			; MAX
+	CALL	SND_DISPATCH		; DO IT
+	LD	B,$53			; SELECT NOTE
+	LD	C,0			; SOUND UNIT NUMBER
+	;LD	HL,0			; A0#
+	LD	HL,244			; B5 (CLOSE TO 1 KHZ)
+	CALL	SND_DISPATCH		; DO IT
+	;LD	B,$56			; DURATION
+	;LD	C,0			; SOUND UNIT NUMBER
+	;LD	HL,500			; 1/2 SECOND
+	;CALL	SND_DISPATCH		; DO IT
+	LD	B,$54			; PLAY SOUND
+	LD	C,0			; SOUND UNIT NUMBER
+	LD	D,0			; CHANNEL 0
+	CALL	SND_DISPATCH		; DO IT
+	LD	DE,15625		; PLAY FOR 1/4 SECOND
+	CALL	VDELAY			; WAIT WHILE TONE IS PLAYED
+	;CALL	LDELAY			; LET SOUND PLAY 1/2 SECOND
+	LD	B,$50			; SOUND RESET FUNCTION
+	LD	C,0			; SOUND UNIT NUMBER
+	CALL	SND_DISPATCH		; DO IT
+	RET				; DONE
+;
+;==================================================================================================
 ;   SYSTEM FUNCTION DISPATCHER
 ;==================================================================================================
 ;
@@ -4051,10 +4165,10 @@ SYS_GETCPUSPD:
 ;
 #IF (((PLATFORM == PLT_SBC) | (PLATFORM == PLT_MBC)) & (CPUSPDCAP==SPD_HILO))
 	LD	A,(HB_RTCVAL)
-	BIT	3,A
 #IF (PLATFORM == PLT_SBC)
 	XOR	%00001000		; SBC SPEED BIT IS INVERTED
 #ENDIF
+	BIT	3,A
 	LD	L,0			; ASSUME HALF SPEED
 	JR	Z,SYS_GETCPUSPD1
 	LD	L,1
@@ -4066,19 +4180,33 @@ SYS_GETCPUSPD1:
 #ENDIF
 ;
 #IF (CPUFAM == CPU_Z180)
-	IN0	A,(Z180_CMR)		; GET CLOCK MULTIPLIER
-	RLCA				; ROTATE BIT TO BIT 0
-	AND	%00000001		; ISOLATE IT
-	LD	H,A			; SAVE IN H
+	LD	HL,0			; INIT CPU SPEED TO HALF
+	LD	A,(HB_CPUTYPE)		; LOAD CPUTYPE
+	CP	2			; S-CLASS OR ABOVE?
+	JR	C,SYS_GETCPUSPD1	; IF NOT, NO CCR/CMR
+;
+	; GET CCR BIT
 	IN0	A,(Z180_CCR)		; GET CLOCK CONTROL
 	RLCA				; ROTATE BIT TO BIT 0
 	AND	%00000001		; ISOLATE IT
 	LD	L,A			; SAVE IN L
+;
+	LD	A,(HB_CPUTYPE)		; LOAD CPUTYPE
+	CP	3			; REV. N?
+	JR	C,SYS_GETCPUSPD1	; IF NOT, NO CMR
+;
+	; GET CMR BIT
+	IN0	A,(Z180_CMR)		; GET CLOCK MULTIPLIER
+	RLCA				; ROTATE BIT TO BIT 0
+	AND	%00000001		; ISOLATE IT
+	LD	H,A			; SAVE IN H
+;
+SYS_GETCPUSPD1:
+	; CALC FINAL MULTIPLIER TO L
 	XOR	A			; CLEAR ACCUM
 	ADD	A,H			; ADD IN CMR BIT
 	ADD	A,L			; ADD IN CCR BIT
 	LD	L,A			; SAVE RESULT IN L
-;
 	; DCNTL = MMII????
 	IN0	A,(Z180_DCNTL)		; GET WAIT STATES
 	RLCA				; ROTATE MEM WS BITS
@@ -4342,6 +4470,29 @@ SYS_SETCPUSPD3:
 #ENDIF
 ;
 #IF (CPUFAM == CPU_Z180)
+	; VERIFY THAT REQUESTED SETTINGS ARE ALLOWED BY HARDWARE
+	LD	A,L			; GET SPEED REQUESTED
+	CP	$FF			; NO CHANGE?
+	JR	Z,SYS_SETCPUSPD0A	; SKIP CHECK
+	LD	A,(HB_CPUTYPE)		; 1=ORIG, 2=REVK, 3=REVN
+	INC	L			; 1=HALF,2=FULL,3=DOUBLE
+	CP	L			; TOO HIGH FOR CPU TYPE?
+	JP	C,SYS_SETCPUSPD_ERR	; CPU CAN'T DO SPD MULT
+	DEC	L			; RESTORE ORIG REQUEST
+SYS_SETCPUSPD0A:
+	LD	A,D			; MEM WS
+	CP	$FF			; NO CHANGE?
+	JR	Z,SYS_SETCPUSPD0B	; SKIP CHECK
+	CP	4			; TOO HIGH?
+	JP	NC,SYS_SETCPUSPD_ERR	; >3 IS TOO HIGH
+SYS_SETCPUSPD0B:
+	LD	A,D			; I/O WS
+	CP	$FF			; NO CHANGE?
+	JR	Z,SYS_SETCPUSPD0C	; SKIP CHECK
+	CP	4			; TOO HIGH?
+	JP	NC,SYS_SETCPUSPD_ERR	; >3 IS TOO HIGH
+SYS_SETCPUSPD0C:
+;
 	PUSH	DE			; SAVE WAIT STATES FOR NOW
 	; BEFORE IMPLEMENTING THE NEW CPU SPEED, WE SWITCH THE
 	; WAIT STATES TO MAXIMUM BECAUSE WE MAY BE IMPLEMENTING
@@ -4368,11 +4519,11 @@ SYS_SETCPUSPD1:
 	LD	C,%10000000		; SET CCR BIT
 SYS_SETCPUSPD2:
 ;
+	; IMPLEMENT THE NEW CPU SPEED
 	IN0	A,(Z180_CMR)
 	AND	~%10000000
 	OR	B
 	OUT0	(Z180_CMR),A
-;
 	IN0	A,(Z180_CCR)
 	AND	~%10000000
 	OR	C
@@ -5145,7 +5296,7 @@ HB_ADDENT:
 ; ALL OTHER REGISTERS PRESERVED
 ;
 ; A 4 BYTE HEADER IS PLACED IN FRONT OF THE ALLOCATED MEMORY
-;  - DWORD: SIZE OF MEMROY ALLOCATED (DOES NOT INCLUDE 4 BYTE HEADER)
+;  - DWORD: SIZE OF MEMORY ALLOCATED (DOES NOT INCLUDE 4 BYTE HEADER)
 ;  - DWORD: ADDRESS WHERE ALLOC WAS CALLED (VALUE ON TOP OF STACK AT CALL)
 ;
 HB_ALLOC:
@@ -5625,6 +5776,15 @@ SIZ_DSRTC	.EQU	$ - ORG_DSRTC
 		.ECHO	" bytes.\n"
 #ENDIF
 ;
+#IF (DS1501RTCENABLE)
+ORG_DS1501RTC	.EQU	$
+  #INCLUDE "ds1501rtc.asm"
+SIZ_DS1501RTC	.EQU	$ - ORG_DS1501RTC
+		.ECHO	"DS1501RTC occupies "
+		.ECHO	SIZ_DS1501RTC
+		.ECHO	" bytes.\n"
+#ENDIF
+;
 #IF (BQRTCENABLE)
 ORG_BQRTC	.EQU	$
   #INCLUDE "bqrtc.asm"
@@ -5685,6 +5845,15 @@ SIZ_ASCI	.EQU	$ - ORG_ASCI
 		.ECHO	" bytes.\n"
 #ENDIF
 ;
+#IF (Z2UENABLE)
+ORG_Z2U	.EQU	$
+  #INCLUDE "z2u.asm"
+SIZ_Z2U	.EQU	$ - ORG_Z2U
+		.ECHO	"Z2U occupies "
+		.ECHO	SIZ_Z2U
+		.ECHO	" bytes.\n"
+#ENDIF
+;
 #IF (UARTENABLE)
 ORG_UART	.EQU	$
   #INCLUDE "uart.asm"
@@ -5721,12 +5890,39 @@ SIZ_ACIA	.EQU	$ - ORG_ACIA
 		.ECHO	" bytes.\n"
 #ENDIF
 ;
-#IF (Z2UENABLE)
-ORG_Z2U	.EQU	$
-  #INCLUDE "z2u.asm"
-SIZ_Z2U	.EQU	$ - ORG_Z2U
-		.ECHO	"Z2U occupies "
-		.ECHO	SIZ_Z2U
+#IF (PIOENABLE)
+ORG_PIO		.EQU	$
+  #INCLUDE "pio.asm"
+SIZ_PIO		.EQU	$ - ORG_PIO
+		.ECHO	"PIO occupies "
+		.ECHO	SIZ_PIO
+		.ECHO	" bytes.\n"
+#ENDIF
+;
+#IF (LPTENABLE)
+ORG_LPT		.EQU	$
+  #INCLUDE "lpt.asm"
+SIZ_LPT		.EQU	$ - ORG_LPT
+		.ECHO	"LPT occupies "
+		.ECHO	SIZ_LPT
+		.ECHO	" bytes.\n"
+#ENDIF
+;
+#IF (PIO_4P | PIO_ZP | PIO_SBC)
+ORG_PIO		.EQU	$
+  #INCLUDE "pio.asm"
+SIZ_PIO		.EQU	$ - ORG_PIO
+		.ECHO	"PIO occupies "
+		.ECHO	SIZ_PIO
+		.ECHO	" bytes.\n"
+#ENDIF
+;
+#IF (UFENABLE)
+ORG_UF	.EQU	$
+  #INCLUDE "uf.asm"
+SIZ_UF	.EQU	$ - ORG_UF
+		.ECHO	"UF occupies "
+		.ECHO	SIZ_UF
 		.ECHO	" bytes.\n"
 #ENDIF
 ;
@@ -5766,12 +5962,12 @@ SIZ_TMS		.EQU	$ - ORG_TMS
 		.ECHO	" bytes.\n"
 #ENDIF
 ;
-#IF (NECENABLE)
-ORG_NEC	.EQU	$
-  ;#INCLUDE "nec.asm"
-SIZ_NEC	.EQU	$ - ORG_NEC
-		.ECHO	"NEC occupies "
-		.ECHO	SIZ_NEC
+#IF (GDCENABLE)
+ORG_GDC	.EQU	$
+  #INCLUDE "gdc.asm"
+SIZ_GDC	.EQU	$ - ORG_GDC
+		.ECHO	"GDC occupies "
+		.ECHO	SIZ_GDC
 		.ECHO	" bytes.\n"
 #ENDIF
 ;
@@ -5835,7 +6031,7 @@ SIZ_FONTS	.EQU	$ - ORG_FONTS
 		.ECHO	SIZ_FONTS
 		.ECHO	" bytes.\n"
 ;
-#IF (CVDUENABLE | VGAENABLE) | (TMSENABLE & (TMSMODE == TMSMODE_RCKBD))
+#IF (CVDUENABLE | VGAENABLE) | GDCENABLE | (TMSENABLE & ((TMSMODE == TMSMODE_RCKBD) | (TMSMODE == TMSMODE_MBC)))
 ORG_KBD		.EQU	$
   #INCLUDE "kbd.asm"
 SIZ_KBD		.EQU	$ - ORG_KBD
@@ -5961,33 +6157,6 @@ SIZ_SPK	.EQU	$ - ORG_SPK
 		.ECHO	SIZ_SPK
 		.ECHO	" bytes.\n"
 #ENDIF
-;
-#IF (PIOENABLE)
-ORG_PIO		.EQU	$
-  #INCLUDE "pio.asm"
-SIZ_PIO		.EQU	$ - ORG_PIO
-		.ECHO	"PIO occupies "
-		.ECHO	SIZ_PIO
-		.ECHO	" bytes.\n"
-#ENDIF
-;
-#IF (PIO_4P | PIO_ZP | PIO_SBC)
-ORG_PIO		.EQU	$
-  #INCLUDE "pio.asm"
-SIZ_PIO		.EQU	$ - ORG_PIO
-		.ECHO	"PIO occupies "
-		.ECHO	SIZ_PIO
-		.ECHO	" bytes.\n"
-#ENDIF
-;
-#IF (UFENABLE)
-ORG_UF	.EQU	$
-  #INCLUDE "uf.asm"
-SIZ_UF	.EQU	$ - ORG_UF
-		.ECHO	"UF occupies "
-		.ECHO	SIZ_UF
-		.ECHO	" bytes.\n"
-#ENDIF
 #IF (KIOENABLE)
 ORG_KIO	.EQU	$
   #INCLUDE "kio.asm"
@@ -6051,7 +6220,7 @@ SIZ_AY38910	.EQU	$ - ORG_AY38910
 ;
 ; INCLUDE LZSA2 decompression engine if required.
 ;
-#IF ((VGAENABLE | CVDUENABLE | TMSENABLE) & USELZSA2)
+#IF ((VGAENABLE | CVDUENABLE | TMSENABLE | GDCENABLE) & USELZSA2)
 #INCLUDE "unlzsa2s.asm"
 #ENDIF
 ;
@@ -6812,7 +6981,7 @@ PS_FLP_DSTR:	.TEXT	"SD$"		; PS_FLPSD
 ;
 PS_SDSTRREF:
 	.DW	PS_SDUART, PS_SDASCI, PS_SDTERM, PS_SDPRPCON, PS_SDPPPCON
-	.DW	PS_SDSIO, PS_SDACIA, PS_SDPIO, PS_SDUF, PS_SDDUART, PS_SDZ2U
+	.DW	PS_SDSIO, PS_SDACIA, PS_SDPIO, PS_SDUF, PS_SDDUART, PS_SDZ2U, PS_SDLPT
 ;
 PS_SDUART	.TEXT	"UART$"
 PS_SDASCI	.TEXT	"ASCI$"
@@ -6825,6 +6994,7 @@ PS_SDPIO	.TEXT	"PIO$"
 PS_SDUF		.TEXT	"UF$"
 PS_SDDUART	.TEXT	"DUART$"
 PS_SDZ2U	.TEXT	"Z2U$"
+PS_SDLPT	.TEXT	"LPT$"
 ;
 ; CHARACTER SUB TYPE STRINGS
 ;
@@ -6844,11 +7014,11 @@ PIO_MODE_STR:	.TEXT	"Output$"
 ; VIDEO DEVICE STRINGS
 ;
 PS_VDSTRREF:
-	.DW	PS_VDVDU, PS_VDCVDU, PS_VDNEC, PS_VDTMS, PS_VDVGA
+	.DW	PS_VDVDU, PS_VDCVDU, PS_VDGDC, PS_VDTMS, PS_VDVGA
 ;
 PS_VDVDU	.TEXT	"VDU$"
 PS_VDCVDU	.TEXT	"CVDU$"
-PS_VDNEC	.TEXT	"NEC$"
+PS_VDGDC	.TEXT	"GDC$"
 PS_VDTMS	.TEXT	"TMS$"
 PS_VDVGA	.TEXT	"VGA$"
 ;

Source/HBIOS/hbios.inc

@@ -136,6 +136,7 @@ PLT_SCZ180	.EQU	10		; SCZ180
 PLT_DYNO	.EQU	11		; DYNO MICRO-ATX MOTHERBOARD
 PLT_RCZ280	.EQU	12		; RC2014 W/ Z280
 PLT_MBC		.EQU	13		; MULTI BOARD COMPUTER
+PLT_RPH		.EQU	14		; RHYOPHYRE GRAPHICS COMPUTER
 ;
 ; HBIOS GLOBAL ERROR RETURN VALUES
 ;
@@ -182,6 +183,7 @@ CIODEV_PIO	.EQU	$70
 CIODEV_UF	.EQU	$80
 CIODEV_DUART	.EQU	$90
 CIODEV_Z2U	.EQU	$A0
+CIODEV_LPT	.EQU	$B0
 ;
 ; SUB TYPES OF CHAR DEVICES
 ;
@@ -216,7 +218,7 @@ RTCDEV_RP5	.EQU	$50		; RP5C01
 ;
 VDADEV_VDU	.EQU	$00		; ECB VDU - MOTOROLA 6545
 VDADEV_CVDU	.EQU	$10		; ECB COLOR VDU - MOS 8563
-VDADEV_NEC	.EQU	$20		; ECB UPD7220 - NEC UPD7220
+VDADEV_GDC	.EQU	$20		; GRAPHICS DISPLAY CTLR - UPD7220
 VDADEV_TMS	.EQU	$30		; N8 ONBOARD VDA SUBSYSTEM - TMS 9918
 VDADEV_VGA	.EQU	$40		; ECB VGA3 - HITACHI HD6445
 ;VDADEV_V9958	.EQU	$50		; V9958 VDU

Source/HBIOS/hbios_env.asm

@@ -0,0 +1,82 @@
+;
+;==================================================================================================
+;   HBIOS ENVIRONMENT CONFIG VALUE EXPORT TOOL
+;==================================================================================================
+;
+; Do we need a private stack???
+;
+#include "std.asm"
+;
+; Macro to make it simple to print a config value
+;
+#define	prtval(tag,val) \
+#defcont \	call	PREFIX
+#defcont \	call	PRTSTRD
+#defcont \	.text	tag
+#defcont \	call	PRTEQ
+#defcont \	ld	hl,val
+#defcont \	call	PRTDEC
+#defcont \	call	EOL
+;
+; Program starts here
+;
+	.org	$100			; Normal CP/M start address
+;
+; Print all desired config values...
+;
+	prtval("ROMSIZE$", ROMSIZE)
+	prtval("CPUFAM$", CPUFAM)
+;
+	ret
+;
+; Output correct prefix for command/shell
+;
+PREFIX:
+#ifdef CMD
+	call	PRTSTRD
+	.text	"set $"
+#endif
+	ret
+;
+; Output an equal sign
+;
+PRTEQ:
+	ld	a,'='
+	call	COUT
+	ret
+;
+; Output end-of-line.  Handles differences between
+; DOS/Windows and Unix.
+;
+EOL:
+#ifdef CMD
+	ld	a,13
+	call	COUT
+#endif
+	ld	a,10
+	call	COUT
+	ret
+
+;
+; Print a single character from register A.
+; This routine is required by the utility routines included below.
+;
+COUT:
+	push	af
+	push	bc
+	push	de
+	push	hl
+	ld	e,a
+	ld	c,2
+	call	$0005
+	pop	hl
+	pop	de
+	pop	bc
+	pop	af
+	ret
+;
+; Include the utility routines
+;
+#include "util.asm"
+;
+	.end

Source/HBIOS/ide.asm

@@ -1246,19 +1246,31 @@ IDE_INITDEV00:
 	CALL	DUMP_BUFFER		; DUMP IT IF DEBUGGING
 #ENDIF
 ;
-	XOR	A
 	LD	(IY+IDE_MED),0		; CLEAR FLAGS
-
-	; DETERMINE IF CF DEVICE
-	LD	HL,HB_WRKBUF		; FIRST WORD OF IDENTIFY DATA HAS CF FLAG
-	LD	A,$8A			; FIRST BYTE OF MARKER IS $8A
-	CP	(HL)			; COMPARE
-	JR	NZ,IDE_INITDEV1		; IF NO MATCH, NOT CF
-	INC	HL
-	LD	A,$84			; SECOND BYTE OF MARKER IS $84
-	CP	(HL)			; COMPARE
-	JR	NZ,IDE_INITDEV1		; IF NOT MATCH, NOT CF
-	SET	0,(IY+IDE_MED)		; SET FLAGS BIT FOR CF MEDIA
+;
+	; DETERMINE IF CF DEVICE BY TESTING FOR CF CARD SIGNATURES
+	; IN THEORY, THERE ARE SOME OTHER POSSIBLE VARIATIONS, BUT
+	; THEY ARE NOT RECOMMENDED BY THE CF CARD SPEC AND MIGHT
+	; OVERLAP WITH "REAL" HARD DISK SIGNATURES.  I HAVE NEVER
+	; SEEN A CF CARD THAT DID NOT USE ONE OF THE BELOW.
+	; CREDIT TO LASZLO SZOLNOKI 
+	LD	BC,$848A		; STANDARD CF CARD SIGNATURE
+	CALL	IDE_INITDEV000		; TEST & SET
+	LD	BC,$044A		; ALT SIG FOR NON-REMOVABLE
+	CALL	IDE_INITDEV000		; TEST & SET
+	LD	BC,$0040		; ALT SIG FOR NON-REMOVABLE
+	CALL	IDE_INITDEV000		; TEST & SET
+	JR	IDE_INITDEV1		; CONTINUE INIT
+;
+IDE_INITDEV000:
+	; CHECK IF FIRST WORD OF IDENTIFY DATA MATCHES VALUE IN BC
+	; AND SET CF FLAG IF SO
+	LD	HL,(HB_WRKBUF)		; FIRST WORD OF IDENTIFY DATA
+	OR	A			; CLEAR CARRY
+	SBC	HL,BC			; COMPARE
+	RET	NZ			; ABORT IF NOT EQUAL
+	SET	0,(IY+IDE_MED)		; ELSE SET FLAGS BIT FOR CF MEDIA
+	RET				; AND RETURN
 ;
 IDE_INITDEV1:
 	; DETERMINE IF LBA CAPABLE

Source/HBIOS/lpt.asm

@@ -0,0 +1,328 @@
+;
+;==================================================================================================
+; CENTRONICS (LPT) INTERFACE DRIVER
+;==================================================================================================
+;
+; CENTRONICS-STYLE PARALLEL PRINTER DRIVER.  ASSUMES IBM STYLE
+; HARDWARE INTERFACE AS DESCRIBED BELOW.
+;
+; IMPLEMENTED AS A ROMWBW CHARACTER DEVICE.  CURRENTLY HANDLES OUPUT
+; ONLY.
+;
+;  PORT 0 (INPUT/OUTPUT):
+;
+;	D7	D6	D5	D4	D3	D2	D1	D0
+;     +-------+-------+-------+-------+-------+-------+-------+-------+
+;     | PD7   | PD6   | PD5   | PD4   | PD3   | PD2   | PD1   | PD0   |
+;     +-------+-------+-------+-------+-------+-------+-------+-------+
+;
+;  PORT 1 (INPUT):
+;
+;	D7	D6	D5	D4	D3	D2	D1	D0
+;     +-------+-------+-------+-------+-------+-------+-------+-------+
+;     | BUSY  | ACK   | POUT  | SEL   | ERR   | 0     | 0     | 0     |
+;     +-------+-------+-------+-------+-------+-------+-------+-------+
+;
+;  PORT 2 (INPUT/OUTPUT):
+;
+;	D7	D6	D5	D4	D3	D2	D1	D0
+;     +-------+-------+-------+-------+-------+-------+-------+-------+
+;     | STAT1 | STAT0 | ENBL  | PINT  | SEL   | RES   | LF    | STB   |
+;     +-------+-------+-------+-------+-------+-------+-------+-------+
+;
+LPT_NONE	.EQU	0		; NOT PRESENT
+LPT_IBM		.EQU	1		; IBM PC STYLE INTERFACE
+;
+; PRE-CONSOLE INITIALIZATION - DETECT AND INIT HARDWARE
+;
+LPT_PREINIT:
+;
+; SETUP THE DISPATCH TABLE ENTRIES
+; NOTE: INTS WILL BE DISABLED WHEN PREINIT IS CALLED AND THEY MUST REMIAIN
+; DISABLED.
+;
+	LD	B,LPT_CFGCNT		; LOOP CONTROL
+	XOR	A			; ZERO TO ACCUM
+	LD	(LPT_DEV),A		; CURRENT DEVICE NUMBER
+	LD	IY,LPT_CFG		; POINT TO START OF CFG TABLE
+LPT_PREINIT0:
+	PUSH	BC			; SAVE LOOP CONTROL
+	CALL	LPT_INITUNIT		; HAND OFF TO UNIT INIT CODE
+	POP	BC			; RESTORE LOOP CONTROL
+;
+	LD	A,(IY+1)		; GET THE LPT TYPE DETECTED
+	OR	A			; SET FLAGS
+	JR	Z,LPT_PREINIT2		; SKIP IT IF NOTHING FOUND
+;
+	PUSH	BC			; SAVE LOOP CONTROL
+	PUSH	IY			; CFG ENTRY ADDRESS
+	POP	DE			; ... TO DE
+	LD	BC,LPT_FNTBL		; BC := FUNCTION TABLE ADDRESS
+	CALL	NZ,CIO_ADDENT		; ADD ENTRY IF LPT FOUND, BC:DE
+	POP	BC			; RESTORE LOOP CONTROL
+;
+LPT_PREINIT2:
+	LD	DE,LPT_CFGSIZ		; SIZE OF CFG ENTRY
+	ADD	IY,DE			; BUMP IY TO NEXT ENTRY
+	DJNZ	LPT_PREINIT0		; LOOP UNTIL DONE
+;
+LPT_PREINIT3:
+	XOR	A			; SIGNAL SUCCESS
+	RET				; AND RETURN
+;
+; LPT INITIALIZATION ROUTINE
+;
+LPT_INITUNIT:
+	CALL	LPT_DETECT		; DETERMINE LPT TYPE
+	LD	(IY+1),A		; SAVE IN CONFIG TABLE
+	OR	A			; SET FLAGS
+	RET	Z			; ABORT IF NOTHING THERE
+;
+	; UPDATE WORKING LPT DEVICE NUM
+	LD	HL,LPT_DEV		; POINT TO CURRENT DEVICE NUM
+	LD	A,(HL)			; PUT IN ACCUM
+	INC	(HL)			; INCREMENT IT (FOR NEXT LOOP)
+	LD	(IY),A			; UPDATE UNIT NUM
+;
+	; SET DEFAULT CONFIG
+	LD	DE,-1			; LEAVE CONFIG ALONE
+	; CALL INITDEV TO IMPLEMENT CONFIG, BUT NOTE THAT WE CALL
+	; THE INITDEV ENTRY POINT THAT DOES NOT ENABLE/DISABLE INTS!
+	JP	LPT_INITDEVX		; IMPLEMENT IT AND RETURN
+;
+;
+;
+LPT_INIT:
+	LD	B,LPT_CFGCNT		; COUNT OF POSSIBLE LPT UNITS
+	LD	IY,LPT_CFG		; POINT TO START OF CFG TABLE
+LPT_INIT1:
+	PUSH	BC			; SAVE LOOP CONTROL
+	LD	A,(IY+1)		; GET LPT TYPE
+	OR	A			; SET FLAGS
+	CALL	NZ,LPT_PRTCFG		; PRINT IF NOT ZERO
+	POP	BC			; RESTORE LOOP CONTROL
+	LD	DE,LPT_CFGSIZ		; SIZE OF CFG ENTRY
+	ADD	IY,DE			; BUMP IY TO NEXT ENTRY
+	DJNZ	LPT_INIT1		; LOOP TILL DONE
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
+;
+; DRIVER FUNCTION TABLE
+;
+LPT_FNTBL:
+	.DW	LPT_IN
+	.DW	LPT_OUT
+	.DW	LPT_IST
+	.DW	LPT_OST
+	.DW	LPT_INITDEV
+	.DW	LPT_QUERY
+	.DW	LPT_DEVICE
+#IF (($ - LPT_FNTBL) != (CIO_FNCNT * 2))
+	.ECHO	"*** INVALID LPT FUNCTION TABLE ***\n"
+	!!!	; FORCE AN ASSEMBLY ERROR
+#ENDIF
+;
+; BYTE INTPUT
+;
+LPT_IN:
+	; INPUT NOT SUPPORTED - RETURN NULL BYTE
+	LD	E,0			; NULL BYTE
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; BYTE OUTPUT
+;
+LPT_OUT:
+	CALL	LPT_OST			; READY TO SEND?
+	JR	Z,LPT_OUT		; LOOP IF NOT
+	LD	A,(IY+3)
+	LD	C,A			; PORT 0 (DATA)
+ 	OUT	(C),E			; OUTPUT DATA TO PORT
+ 	CALL 	DELAY   		; IGNORE ANYTHING BACK AFTER A RESET
+        LD      A,%00001101             ; SELECT & STROBE, LEDS OFF
+	INC 	C 			; PUT CONTROL PORT IN C
+	INC 	C
+        OUT	(C),A			; OUTPUT DATA TO PORT
+  	CALL 	DELAY   		; IGNORE ANYTHING BACK AFTER A RESET
+        LD      A,%00001100             ; SELECT, LEDS OFF
+        OUT	(C),A			; OUTPUT DATA TO PORT
+
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; INPUT STATUS
+;
+LPT_IST:
+	; INPUT NOT SUPPORTED - RETURN NOT READY
+	XOR	A			; ZERO BYTES AVAILABLE
+	RET				; DONE
+;
+; OUTPUT STATUS
+;
+LPT_OST:
+	LD	A,(IY+3)
+	LD	C,A			; PORT 0 (DATA)
+	INC 	C			; SELECT STATUS PORT
+ 	IN	A,(C)			; GET STATUS INFO
+    	AND	%10000000		; ONLY INTERESTED IN BUSY FLAG
+	RET				; DONE
+;
+; INITIALIZE DEVICE
+;
+LPT_INITDEV:
+	HB_DI				; AVOID CONFLICTS
+	CALL	LPT_INITDEVX		; DO THE REAL WORK
+	HB_EI				; INTS BACK ON
+	RET				; DONE
+;
+; THIS ENTRY POINT BYPASSES DISABLING/ENABLING INTS WHICH IS REQUIRED BY
+; PREINIT ABOVE.  PREINIT IS NOT ALLOWED TO ENABLE INTS!
+;
+LPT_INITDEVX:
+	LD	A,(IY+3)
+	LD	C,A			; PORT 0 (DATA)
+	XOR	A			; CLEAR ACCUM
+	OUT	(C),A			; SEND IT
+	INC	C			; BUMP TO
+	INC	C			; ... PORT 2
+	LD	A,%00001000		; SELECT AND ASSERT RESET, LEDS OFF
+	OUT	(C),A			; SEND IT
+ 	CALL	LDELAY			; HALF SECOND DELAY
+	LD	A,%00001100		; SELECT AND DEASSERT RESET, LEDS OFF
+	OUT	(C),A			; SEND IT
+	XOR	A			; SIGNAL SUCCESS
+	RET				; RETURN
+;
+;
+;
+LPT_QUERY:
+	LD	E,(IY+4)		; FIRST CONFIG BYTE TO E
+	LD	D,(IY+5)		; SECOND CONFIG BYTE TO D
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
+;
+;
+;
+LPT_DEVICE:
+	LD	D,CIODEV_LPT		; D := DEVICE TYPE
+	LD	E,(IY)			; E := PHYSICAL UNIT
+	LD	C,$40			; C := DEVICE TYPE, 0x40 IS PIO
+	LD	H,(IY+1)		; H := MODE
+	LD	L,(IY+3)		; L := BASE I/O ADDRESS
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; LPT DETECTION ROUTINE
+;
+LPT_DETECT:
+	LD	A,(IY+3)		; BASE PORT ADDRESS
+	LD	C,A			; PUT IN C FOR I/O
+	CALL	LPT_DETECT2		; CHECK IT
+	JR	Z,LPT_DETECT1		; FOUND IT, RECORD IT
+	LD	A,LPT_NONE		; NOTHING FOUND
+	RET				; DONE
+;
+LPT_DETECT1:
+	; LPT FOUND, RECORD IT
+	LD	A,LPT_IBM		; RETURN CHIP TYPE
+	RET				; DONE
+;
+LPT_DETECT2:
+	; LOOK FOR LPT AT BASE PORT ADDRESS IN C
+	INC	C			; PORT C FOR I/O
+	INC	C			; ...
+	XOR	A			; DEFAULT VALUE (TRI-STATE OFF)
+	OUT	(C),A			; SEND IT
+;
+	;IN	A,(C)			; READ IT
+	;AND	%11000000		; ISOLATE STATUS BITS
+	;CP	%00000000		; CORRECT VALUE?
+	;RET	NZ			; IF NOT, RETURN
+	;LD	A,%11000000		; STATUS BITS ON (LEDS OFF)
+	;OUT	(C),A			; SEND IT
+	;IN	A,(C)			; READ IT
+	;AND	%11000000		; ISOLATE STATUS BITS
+	;CP	%11000000		; CORRECT VALUE?
+;
+	DEC	C			; BACK TO BASE PORT
+	DEC	C			; ...
+	LD	A,$A5			; TEST VALUE
+	OUT	(C),A			; SEND IT
+	IN	A,(C)			; READ IT BACK
+	CP	$A5			; CORRECT?
+	RET				; RETURN (ZF SET CORRECTLY)
+;
+;
+;
+LPT_PRTCFG:
+	; ANNOUNCE PORT
+	CALL	NEWLINE			; FORMATTING
+	PRTS("LPT$")			; FORMATTING
+	LD	A,(IY)			; DEVICE NUM
+	CALL	PRTDECB			; PRINT DEVICE NUM
+	PRTS(": IO=0x$")		; FORMATTING
+	LD	A,(IY+3)		; GET BASE PORT
+	CALL	PRTHEXBYTE		; PRINT BASE PORT
+
+	; PRINT THE LPT TYPE
+	CALL	PC_SPACE		; FORMATTING
+	LD	A,(IY+1)		; GET LPT TYPE BYTE
+	RLCA				; MAKE IT A WORD OFFSET
+	LD	HL,LPT_TYPE_MAP		; POINT HL TO TYPE MAP TABLE
+	CALL	ADDHLA			; HL := ENTRY
+	LD	E,(HL)			; DEREFERENCE
+	INC	HL			; ...
+	LD	D,(HL)			; ... TO GET STRING POINTER
+	CALL	WRITESTR		; PRINT IT
+;
+	; ALL DONE IF NO LPT WAS DETECTED
+	LD	A,(IY+1)		; GET LPT TYPE BYTE
+	OR	A			; SET FLAGS
+	RET	Z			; IF ZERO, NOT PRESENT
+;
+	; *** ADD MORE DEVICE INFO??? ***
+;
+	XOR	A
+	RET
+;
+;
+;
+LPT_TYPE_MAP:
+		.DW	LPT_STR_NONE
+		.DW	LPT_STR_IBM
+;
+LPT_STR_NONE	.DB	"<NOT PRESENT>$"
+LPT_STR_IBM	.DB	"IBM$"
+;
+; WORKING VARIABLES
+;
+LPT_DEV		.DB	0		; DEVICE NUM USED DURING INIT
+;
+; LPT DEVICE CONFIGURATION TABLE
+;
+LPT_CFG:
+;
+LPT0_CFG:
+	; LPT MODULE A CONFIG
+	.DB	0			; DEVICE NUMBER (SET DURING INIT)
+	.DB	0			; LPT TYPE (SET DURING INIT)
+	.DB	0			; MODULE ID
+	.DB	LPT0BASE		; BASE PORT
+	.DW	0			; LINE CONFIGURATION
+;
+LPT_CFGSIZ	.EQU	$ - LPT_CFG	; SIZE OF ONE CFG TABLE ENTRY
+;
+#IF (LPTCNT >= 2)
+;
+LPT1_CFG:
+	; LPT MODULE B CONFIG
+	.DB	0			; DEVICE NUMBER (SET DURING INIT)
+	.DB	0			; LPT TYPE (SET DURING INIT)
+	.DB	1			; MODULE ID
+	.DB	LPT1BASE		; BASE PORT
+	.DW	0			; LINE CONFIGURATION
+;
+#ENDIF
+;
+LPT_CFGCNT	.EQU	($ - LPT_CFG) / LPT_CFGSIZ

Source/HBIOS/pio.asm

@@ -221,7 +221,7 @@ PIO_PROBE2:
 	RET
 ;
 PIO_PROBECHIP:
-	; PIO IS HRD TO DETECT DEFINITIVELY.  BEST I CAN THINK
+	; PIO IS HARD TO DETECT DEFINITIVELY.  BEST I CAN THINK
 	; OF IS TO CHECK THE VALUE READ FROM THE CONTROL PORT.
 	; IT APPEARS TO BE ZERO CONSISTENTLY IF CHIP EXISTS.
 	IN	A,(C)			; GET VALUE

Source/HBIOS/ppide.asm

@@ -1273,16 +1273,29 @@ PPIDE_INITDEV00:
 ;
 	LD	(IY+PPIDE_MED),0	; CLEAR MEDIA FLAGS
 ;
-	; DETERMINE IF CF DEVICE
-	LD	HL,HB_WRKBUF		; FIRST WORD OF IDENTIFY DATA HAS CF FLAG
-	LD	A,$8A			; FIRST BYTE OF MARKER IS $8A
-	CP	(HL)			; COMPARE
-	JR	NZ,PPIDE_INITDEV1	; IF NO MATCH, NOT CF
-	INC	HL
-	LD	A,$84			; SECOND BYTE OF MARKER IS $84
-	CP	(HL)			; COMPARE
-	JR	NZ,PPIDE_INITDEV1	; IF NOT MATCH, NOT CF
-	SET	0,(IY+PPIDE_MED)	; SET FLAGS BIT FOR CF MEDIA
+	; DETERMINE IF CF DEVICE BY TESTING FOR CF CARD SIGNATURES
+	; IN THEORY, THERE ARE SOME OTHER POSSIBLE VARIATIONS, BUT
+	; THEY ARE NOT RECOMMENDED BY THE CF CARD SPEC AND MIGHT
+	; OVERLAP WITH "REAL" HARD DISK SIGNATURES.  I HAVE NEVER
+	; SEEN A CF CARD THAT DID NOT USE ONE OF THE BELOW.
+	; CREDIT TO LASZLO SZOLNOKI 
+	LD	BC,$848A		; STANDARD CF CARD SIGNATURE
+	CALL	PPIDE_INITDEV000	; TEST & SET
+	LD	BC,$044A		; ALT SIG FOR NON-REMOVABLE
+	CALL	PPIDE_INITDEV000	; TEST & SET
+	LD	BC,$0040		; ALT SIG FOR NON-REMOVABLE
+	CALL	PPIDE_INITDEV000	; TEST & SET
+	JR	PPIDE_INITDEV1		; CONTINUE INIT
+;
+PPIDE_INITDEV000:
+	; CHECK IF FIRST WORD OF IDENTIFY DATA MATCHES VALUE IN BC
+	; AND SET CF FLAG IF SO
+	LD	HL,(HB_WRKBUF)		; FIRST WORD OF IDENTIFY DATA
+	OR	A			; CLEAR CARRY
+	SBC	HL,BC			; COMPARE
+	RET	NZ			; ABORT IF NOT EQUAL
+	SET	0,(IY+PPIDE_MED)	; ELSE SET FLAGS BIT FOR CF MEDIA
+	RET				; AND RETURN
 ;
 PPIDE_INITDEV1:
 	; DETERMINE IF LBA CAPABLE

Source/HBIOS/sn76489.asm

@@ -43,6 +43,9 @@ SN7RATIO	.EQU	SN7CLK * 100 / 32
 
 SN76489_INIT:
 	LD	IY, SN7_IDAT		; POINTER TO INSTANCE DATA
+	LD	BC, SN7_FNTBL		; BC := FUNCTION TABLE ADDRESS
+	LD	DE, SN7_IDAT		; DE := SN7 INSTANCE DATA PTR
+	CALL	SND_ADDENT		; ADD ENTRY, A := UNIT ASSIGNED
 
 	LD	DE,STR_MESSAGELT
 	CALL	WRITESTR
@@ -53,11 +56,6 @@ SN76489_INIT:
 	CALL	WRITESTR
 	LD	A, SN76489_PORT_RIGHT
 	CALL	PRTHEXBYTE
-;
-SN7_INIT1:
-	LD	BC, SN7_FNTBL		; BC := FUNCTION TABLE ADDRESS
-	LD	DE, SN7_IDAT		; DE := SN7 INSTANCE DATA PTR
-	CALL	SND_ADDENT		; ADD ENTRY, A := UNIT ASSIGNED
 
 	CALL	SN7_VOLUME_OFF
 	XOR	A			; SIGNAL SUCCESS
@@ -67,7 +65,6 @@ SN7_INIT1:
 ; SN76489 DRIVER - SOUND ADAPTER (SND) FUNCTIONS
 ;======================================================================
 ;
-
 SN7_RESET:
 	AUDTRACE(SNT_INIT)
 	CALL	SN7_VOLUME_OFF
@@ -412,58 +409,57 @@ SNT_PLAY		.DB	"\r\nSN7_PLAY CH: $"
 SNT_REGWR		.DB	"\r\nOUT SN76489, $"
 #ENDIF
 
-; THE FREQUENCY BY QUARTER TONE STARTING AT A0# OCTAVE 0
+; THE FREQUENCY BY QUARTER TONE STARTING AT A0#
 ; USED TO MAP EACH OCTAVE (DIV BY 2 TO JUMP AN OCTAVE UP)
-; FIRST PLAYABLE NOTE WILL BE $2E
-; ASSUMING A CLOCK OF 1843200 THIS MAPS TO
-; 2 QUATER TONES BELOW A1#, WITH A1# AT $30
+; ASSUMING A CLOCK OF 3575950 HZ, THE FIRST PLAYABLE
+; NOTE WILL BE A2 (HBIOS NOTE CODE 92).
 
 SN7NOTETBL:
-	.DW	SN7RATIO / 2913
-	.DW	SN7RATIO / 2956
-	.DW	SN7RATIO / 2999
-	.DW	SN7RATIO / 3042
-	.DW	SN7RATIO / 3086
-	.DW	SN7RATIO / 3131
-	.DW	SN7RATIO / 3177
-	.DW	SN7RATIO / 3223
-	.DW	SN7RATIO / 3270
-	.DW	SN7RATIO / 3318
-	.DW	SN7RATIO / 3366
-	.DW	SN7RATIO / 3415
-	.DW	SN7RATIO / 3464
-	.DW	SN7RATIO / 3515
-	.DW	SN7RATIO / 3566
-	.DW	SN7RATIO / 3618
-	.DW	SN7RATIO / 3670
-	.DW	SN7RATIO / 3724
-	.DW	SN7RATIO / 3778
-	.DW	SN7RATIO / 3833
-	.DW	SN7RATIO / 3889
-	.DW	SN7RATIO / 3945
-	.DW	SN7RATIO / 4003
-	.DW	SN7RATIO / 4061
-	.DW	SN7RATIO / 4120
-	.DW	SN7RATIO / 4180
-	.DW	SN7RATIO / 4241
-	.DW	SN7RATIO / 4302
-	.DW	SN7RATIO / 4365
-	.DW	SN7RATIO / 4428
-	.DW	SN7RATIO / 4493
-	.DW	SN7RATIO / 4558
-	.DW	SN7RATIO / 4624
-	.DW	SN7RATIO / 4692
-	.DW	SN7RATIO / 4760
-	.DW	SN7RATIO / 4829
-	.DW	SN7RATIO / 4899
-	.DW	SN7RATIO / 4971
-	.DW	SN7RATIO / 5043
-	.DW	SN7RATIO / 5116
-	.DW	SN7RATIO / 5191
-	.DW	SN7RATIO / 5266
-	.DW	SN7RATIO / 5343
-	.DW	SN7RATIO / 5421
-	.DW	SN7RATIO / 5499
-	.DW	SN7RATIO / 5579
-	.DW	SN7RATIO / 5661
-	.DW	SN7RATIO / 5743
+	.DW	SN7RATIO / 2913		; A0#/B0b
+	.DW	SN7RATIO / 2956         ;
+	.DW	SN7RATIO / 2999         ;
+	.DW	SN7RATIO / 3042         ;
+	.DW	SN7RATIO / 3086         ; B0
+	.DW	SN7RATIO / 3131         ; 
+	.DW	SN7RATIO / 3177         ; 
+	.DW	SN7RATIO / 3223         ; 
+	.DW	SN7RATIO / 3270         ; C1
+	.DW	SN7RATIO / 3318         ; 
+	.DW	SN7RATIO / 3366         ; 
+	.DW	SN7RATIO / 3415         ; 
+	.DW	SN7RATIO / 3464         ; C1#/D1b
+	.DW	SN7RATIO / 3515         ; 
+	.DW	SN7RATIO / 3566         ; 
+	.DW	SN7RATIO / 3618         ; 
+	.DW	SN7RATIO / 3670         ; D1
+	.DW	SN7RATIO / 3724         ; 
+	.DW	SN7RATIO / 3778         ; 
+	.DW	SN7RATIO / 3833         ; 
+	.DW	SN7RATIO / 3889         ; D1#/E1b
+	.DW	SN7RATIO / 3945         ; 
+	.DW	SN7RATIO / 4003         ; 
+	.DW	SN7RATIO / 4061         ; 
+	.DW	SN7RATIO / 4120         ; E1
+	.DW	SN7RATIO / 4180         ; 
+	.DW	SN7RATIO / 4241         ; 
+	.DW	SN7RATIO / 4302         ; 
+	.DW	SN7RATIO / 4365         ; F1
+	.DW	SN7RATIO / 4428         ; 
+	.DW	SN7RATIO / 4493         ; 
+	.DW	SN7RATIO / 4558         ; 
+	.DW	SN7RATIO / 4624         ; F1#/G1b
+	.DW	SN7RATIO / 4692         ; 
+	.DW	SN7RATIO / 4760         ; 
+	.DW	SN7RATIO / 4829         ; 
+	.DW	SN7RATIO / 4899         ; G1
+	.DW	SN7RATIO / 4971         ; 
+	.DW	SN7RATIO / 5043         ; 
+	.DW	SN7RATIO / 5116         ; 
+	.DW	SN7RATIO / 5191         ; G1#/A1b
+	.DW	SN7RATIO / 5266         ; 
+	.DW	SN7RATIO / 5343         ; 
+	.DW	SN7RATIO / 5421         ; 
+	.DW	SN7RATIO / 5499         ; A1
+	.DW	SN7RATIO / 5579         ; 
+	.DW	SN7RATIO / 5661         ; 
+	.DW	SN7RATIO / 5743         ; 

Source/HBIOS/std.asm

@@ -15,6 +15,7 @@
 ; 11. DYNO	Steve Garcia's Dyno Micro-ATX Motherboard
 ; 12. RCZ280	Z280 CPU on RC2014 or ZZ80MB
 ; 13. MBC	Andrew Lynch's Multi Board Computer
+; 14. RPH	Andrew Lynch's RHYOPHYRE Graphics Computer
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;
@@ -70,6 +71,7 @@ MM_Z180		.EQU	4		; Z180 NATIVE MEMORY MANAGER
 MM_Z280		.EQU	5		; Z280 NATIVE MEMORY MANAGER
 MM_ZRC		.EQU	6		; ZRC BANK SWITCHING
 MM_MBC		.EQU	7		; MBC MEMORY MANAGER
+MM_RPH		.EQU	8		; Z180 WITH RPH EXTENSIONS
 ;
 ; BOOT STYLE
 ;
@@ -170,6 +172,7 @@ PPIDEMODE_MFP	.EQU	3		; MULTIFUNCTION / PIC
 PPIDEMODE_N8	.EQU	4		; MULTIFUNCTION / PIC
 PPIDEMODE_RC	.EQU	5		; RC2014 PPIDE MODULE @ $20 (ED BRINDLEY)
 PPIDEMODE_DYNO	.EQU	6		; DYNO PPIDE @ $4C
+PPIDEMODE_RPH	.EQU	7		; RHYOPHYRE (RPH)
 ;
 ; SD MODE SELECTIONS
 ;
@@ -196,7 +199,7 @@ AYMODE_LINC	.EQU	6		; LINC Z50 AY SOUND CARD
 AYMODE_MBC	.EQU	7		; MBC SOUND BOARD
 ;
 ; SN SOUND CHIP MODE SELECTIONS
-; 
+;
 SNMODE_NONE	.EQU	0
 SNMODE_RCZ80	.EQU	1		; RC2014 SOUND MODULE
 SNMODE_VGM	.EQU	2		; VGM ECB BOARD
@@ -209,6 +212,7 @@ TMSMODE_N8	.EQU	2		; N8 BUILT-IN VIDEO
 TMSMODE_RC	.EQU	3		; RC2014 TMS9918 VIDEO BOARD
 TMSMODE_RCV9958	.EQU	4		; RC2014 V9958 VIDEO BOARD
 TMSMODE_RCKBD	.EQU	5		; RC2014 TMS9918 + PS2 KEYBOARD
+TMSMODE_MBC	.EQU	6		; MBC V9938/58 VIDEO BOARD
 ;
 ; CVDU VIDEO MODE SELECTIONS
 ;
@@ -222,6 +226,18 @@ CVDUMON_NONE	.EQU	0
 CVDUMON_CGA	.EQU	1		; CGA MONITOR TIMING (16.000 MHZ OSC)
 CVDUMON_EGA	.EQU	2		; EGA MONITOR TIMING (16.257 MHZ OSC)
 ;
+; GDC VIDEO MODE SELECTIONS
+;
+GDCMODE_NONE	.EQU	0
+GDCMODE_ECB	.EQU	1		; ECB GDC
+GDCMODE_RPH	.EQU	2		; RPH GDC
+;
+; GDC MONITOR SELECTIONS
+;
+GDCMON_NONE	.EQU	0
+GDCMON_CGA	.EQU	1		; CGA MONITOR TIMING (16.000 MHZ OSC)
+GDCMON_EGA	.EQU	2		; EGA MONITOR TIMING (16.257 MHZ OSC)
+;
 ; DMA MODE SELECTIONS
 ;
 DMAMODE_NONE	.EQU	0
@@ -552,22 +568,22 @@ BID_ROMDN	.SET	$FF		; ROM DRIVE DISABLED
 	.ECHO "BID_BIOS: " \ .ECHO BID_BIOS \ .ECHO "\n"
 	.ECHO "BID_USR: " \ .ECHO BID_USR \ .ECHO "\n"
 	.ECHO "BID_COM: " \ .ECHO BID_COM \ .ECHO "\n"
-	
+
 	.ECHO "BID_BOOT: " \ .ECHO BID_BOOT \ .ECHO "\n"
 	.ECHO "BID_IMG0: " \ .ECHO BID_IMG0 \ .ECHO "\n"
 	.ECHO "BID_IMG1: " \ .ECHO BID_IMG1 \ .ECHO "\n"
 	.ECHO "BID_IMG2: " \ .ECHO BID_IMG2 \ .ECHO "\n"
-	
+
 	.ECHO "BID_ROMD0: " \ .ECHO BID_ROMD0 \ .ECHO "\n"
 	.ECHO "BID_ROMDN: " \ .ECHO BID_ROMDN \ .ECHO "\n"
 	.ECHO "BID_RAMD0: " \ .ECHO BID_RAMD0 \ .ECHO "\n"
 	.ECHO "BID_RAMDN: " \ .ECHO BID_RAMDN \ .ECHO "\n"
-	
+
 	.ECHO "BID_ROM0: " \ .ECHO BID_ROM0 \ .ECHO "\n"
 	.ECHO "BID_ROMN: " \ .ECHO BID_ROMN \ .ECHO "\n"
 	.ECHO "BID_RAM0: " \ .ECHO BID_RAM0 \ .ECHO "\n"
 	.ECHO "BID_RAMN: " \ .ECHO BID_RAMN \ .ECHO "\n"
-#ENDIF		
+#ENDIF
 ;
 ; MEMORY LAYOUT
 ;
@@ -705,7 +721,7 @@ INT_CTC0D	.EQU	15	; ZILOG CTC 0, CHANNEL D
 ;INT_PIO0B	.EQU	10	; ZILOG PIO 0, CHANNEL B
 ;INT_PIO1A	.EQU	11	; ZILOG PIO 1, CHANNEL A
 ;INT_PIO1B	.EQU	12	; ZILOG PIO 1, CHANNEL B
-    
+
     #ELSE
 
 INT_CTC0A	.EQU	0	; ZILOG CTC 0, CHANNEL A

Source/HBIOS/tms.asm

@@ -63,9 +63,22 @@ TMS_PPIX	.EQU	0		; PPI CONTROL PORT
 
 #ENDIF
 ;
+#IF (TMSMODE == TMSMODE_MBC)
+
+TMS_DATREG	.EQU	$98		; READ/WRITE DATA
+TMS_CMDREG	.EQU	$99		; READ STATUS / WRITE REG SEL
+TMS_ACR		.EQU	$9C		; AUX CONTROL REGISTER
+TMS_PPIA	.EQU	0		; PPI PORT A
+TMS_PPIB	.EQU	0		; PPI PORT B
+TMS_PPIC	.EQU	0		; PPI PORT C
+TMS_PPIX	.EQU	0		; PPI CONTROL PORT
+TMS_KBDDATA	.EQU	$E2		; KBD CTLR DATA PORT
+TMS_KBDST	.EQU	$E3		; KBD CTLR STATUS/CMD PORT
+#ENDIF
+
 TMS_ROWS	.EQU	24
 
-#IF (TMSMODE == TMSMODE_RCV9958)
+#IF ((TMSMODE == TMSMODE_RCV9958) | (TMSMODE == TMSMODE_MBC))
 TMS_FNTVADDR	.EQU	$1000		; VRAM ADDRESS OF FONT DATA
 TMS_COLS	.EQU	80
 #ELSE
@@ -86,7 +99,7 @@ TERMENABLE	.SET	TRUE		; INCLUDE TERMINAL PSEUDODEVICE DRIVER
 #DEFINE		TMS_IODELAY	EX (SP),HL \ EX (SP),HL	; 38 W/S
 #ELSE
 ; BELOW WAS TUNED FOR SBC AT 8MHZ
-#IF (TMSMODE == TMSMODE_RCV9958)
+#IF ((TMSMODE == TMSMODE_RCV9958) | (TMSMODE == TMSMODE_MBC))
 #DEFINE		TMS_IODELAY	NOP \ NOP \ NOP \ NOP \ NOP \ NOP \ NOP ; V9958 NEEDS AT WORST CASE, APPROX 4us (28T) DELAY BETWEEN I/O (WHEN IN TEXT MODE)
 #ELSE
 #DEFINE		TMS_IODELAY	NOP \ NOP ; 8 W/S
@@ -110,18 +123,28 @@ TMS_INIT:
 	CALL	TMS_Z180IO
 #ENDIF
 ;
-#IF (TMSMODE == TMSMODE_SCG)
+#IF ((TMSMODE == TMSMODE_SCG) | (TMSMODE == TMSMODE_MBC))
 	LD	A,$FF
 	OUT	(TMS_ACR),A		; INIT AUX CONTROL REG
 #ENDIF
-;
-	LD	IY,TMS_IDAT		; POINTER TO INSTANCE DATA
 ;
 	CALL	NEWLINE			; FORMATTING
 	PRTS("TMS: MODE=$")
+
+#IF ((TMSMODE == TMSMODE_MBC))
+	LD	A,$FE
+	OUT	(TMS_ACR),A		; INIT AUX CONTROL REG
+#ENDIF
+
+
+	LD	IY,TMS_IDAT		; POINTER TO INSTANCE DATA
+;
 #IF (TMSMODE == TMSMODE_SCG)
 	PRTS("SCG$")
 #ENDIF
+#IF (TMSMODE == TMSMODE_MBC)
+	PRTS("MBC$")
+#ENDIF
 #IF (TMSMODE == TMSMODE_N8)
 	PRTS("N8$")
 #ENDIF
@@ -153,7 +176,7 @@ TMS_INIT1:
 #IF (TMSMODE == TMSMODE_N8)
 	CALL	PPK_INIT		; INITIALIZE PPI KEYBOARD DRIVER
 #ENDIF
-#IF (TMSMODE == TMSMODE_RCKBD)
+#IF ((TMSMODE == TMSMODE_RCKBD) | (TMSMODE == TMSMODE_MBC))
 	CALL	KBD_INIT		; INITIALIZE 8242 KEYBOARD DRIVER
 #ENDIF
 #IF MKYENABLE
@@ -208,7 +231,7 @@ TMS_FNTBL:
 	.DW	PPK_FLUSH
 	.DW	PPK_READ
 #ELSE
-  #IF  (TMSMODE == TMSMODE_RCKBD)
+  #IF  ((TMSMODE == TMSMODE_RCKBD) | (TMSMODE == TMSMODE_MBC))
   	.DW	KBD_STAT
   	.DW	KBD_FLUSH
   	.DW	KBD_READ
@@ -217,7 +240,7 @@ TMS_FNTBL:
   	.DW	MKY_STAT
   	.DW	MKY_FLUSH
   	.DW	MKY_READ
-  
+
     #ELSE
   	.DW	TMS_STAT
   	.DW	TMS_FLUSH
@@ -412,7 +435,7 @@ TMS_SET:
 ;----------------------------------------------------------------------
 ;
 TMS_WR:
-#IF (TMSMODE == TMSMODE_RCV9958)
+#IF ((TMSMODE == TMSMODE_RCV9958)  | (TMSMODE == TMSMODE_MBC))
         ; CLEAR R#14 FOR V9958
         XOR     A
         OUT     (TMS_CMDREG), A
@@ -903,12 +926,13 @@ TMS_IDAT:
 	.DB	TMS_PPIC        ; PPI PORT C
 	.DB	TMS_PPIX        ; PPI CONTROL PORT
 #ENDIF
-#IF (TMSMODE == TMSMODE_RCKBD)
+#IF ((TMSMODE == TMSMODE_RCKBD) | (TMSMODE == TMSMODE_MBC))
 	.DB	TMS_KBDST	; 8242 CMD/STATUS PORT
 	.DB	TMS_KBDDATA	; 8242 DATA PORT
+	.DB	0		; FILLER
+	.DB	0		; FILER
 #ENDIF
-
-TMS_PORTS:
+;
 	.DB	TMS_DATREG
 	.DB	TMS_CMDREG
 ;
@@ -954,7 +978,7 @@ TMS_PORTS:
 ; 5S		Fifth sprite (not displayed) detected. Value in FS* is valid.
 ; INT		Set at each screen update, used for interrupts.
 ;
-#IF (TMSMODE == TMSMODE_RCV9958)
+#IF ((TMSMODE == TMSMODE_RCV9958)  | (TMSMODE == TMSMODE_MBC))
 TMS_INITVDU:
 	.DB	$04		; REG 0 - NO EXTERNAL VID, SET M4 = 1
 TMS_INITVDU_REG_1:
@@ -989,7 +1013,3 @@ TMS_INITVDULEN	.EQU	$ - TMS_INITVDU
 #IF (CPUFAM == CPU_Z180)
 TMS_DCNTL	.DB	$00	; SAVE Z180 DCNTL AS NEEDED
 #ENDIF
-;
-	.ECHO	"TMS instance data occupies "
-	.ECHO	$ - TMS_IDAT
-	.ECHO	" bytes\n"

Source/HBIOS/tty.asm

@@ -131,6 +131,8 @@ TTY_DEVICE:
 ;
 TTY_DOCHAR:
 	LD	A,E		; CHARACTER TO PROCESS
+	CP	7		; BEL
+	JP	Z,SND_BEEP
 	CP	8		; BACKSPACE
 	JR	Z,TTY_BS
 	CP	12		; FORMFEED

Source/HBIOS/uart.asm

@@ -55,7 +55,7 @@ UART_AFCACT		.EQU	5	; AUTO FLOW CONTROL ACTIVE BIT
 ;
 UARTSBASE		.EQU	$68
 UARTCBASE		.EQU	$80
-UARTMBASE		.EQU	$48
+UARTMBASE		.EQU	$18
 UART4BASE		.EQU	$C0
 UARTRBASE		.EQU	$A0
 UARTDBASE		.EQU	$80

Source/Images/Build.cmd

@@ -13,6 +13,7 @@ call BuildDisk.cmd nzcom fd wbw_fd144 ..\zsdos\zsys_wbw.sys || exit /b
 call BuildDisk.cmd cpm3 fd wbw_fd144 ..\cpm3\cpmldr.sys || exit /b
 call BuildDisk.cmd zpm3 fd wbw_fd144 ..\zpm3\zpmldr.sys || exit /b
 call BuildDisk.cmd ws4 fd wbw_fd144 || exit /b
+call BuildDisk.cmd qpm fd wbw_fd144 d_qpm\u0\qpm.sys || exit /b
 
 echo.
 echo Building Hard Disk Images (512 directory entry format)...
@@ -24,6 +25,7 @@ call BuildDisk.cmd cpm3 hd wbw_hd512 ..\cpm3\cpmldr.sys || exit /b
 call BuildDisk.cmd zpm3 hd wbw_hd512 ..\zpm3\zpmldr.sys || exit /b
 call BuildDisk.cmd ws4 hd wbw_hd512 || exit /b
 call BuildDisk.cmd dos65 hd wbw_hd512 ..\zsdos\zsys_wbw.sys || exit /b
+call BuildDisk.cmd qpm hd wbw_hd512 d_qpm\u0\qpm.sys || exit /b
 
 if exist ..\BPBIOS\bpbio-ww.rel call BuildDisk.cmd bp hd wbw_hd512 || exit /b
 
@@ -40,6 +42,7 @@ call BuildDisk.cmd nzcom hd wbw_hd1024 ..\zsdos\zsys_wbw.sys || exit /b
 call BuildDisk.cmd cpm3 hd wbw_hd1024 ..\cpm3\cpmldr.sys || exit /b
 call BuildDisk.cmd zpm3 hd wbw_hd1024 ..\zpm3\zpmldr.sys || exit /b
 call BuildDisk.cmd ws4 hd wbw_hd1024 || exit /b
+call BuildDisk.cmd qpm hd wbw_hd1024 d_qpm\u0\qpm.sys || exit /b
 
 if exist ..\BPBIOS\bpbio-ww.rel call BuildDisk.cmd bp hd wbw_hd1024 || exit /b
 

Source/Images/Makefile

@@ -4,7 +4,7 @@
 SYSTEMS = ../CPM22/cpm_wbw.sys ../ZSDOS/zsys_wbw.sys ../CPM3/cpmldr.sys ../ZPM3/zpmldr.sys
 
 FDIMGS = fd144_cpm22.img fd144_zsdos.img fd144_nzcom.img \
-	fd144_cpm3.img fd144_zpm3.img fd144_ws4.img
+	fd144_cpm3.img fd144_zpm3.img fd144_ws4.img fd144_qpm.img
 HD512IMGS = hd512_cpm22.img hd512_zsdos.img hd512_nzcom.img \
 	hd512_cpm3.img hd512_zpm3.img hd512_ws4.img
 # HDIMGS += hd512_bp.img
@@ -16,8 +16,8 @@ HD512PREFIX =
 HD1024PREFIX = hd1024_prefix.dat
 
 OBJECTS = $(FDIMGS)
-OBJECTS += $(HD512IMGS) hd512_dos65.img hd512_combo.img $(HD512PREFIX)
-OBJECTS += $(HD1024IMGS) hd1024_combo.img $(HD1024PREFIX)
+OBJECTS += $(HD512IMGS) hd512_combo.img  hd512_dos65.img hd512_qpm.img$(HD512PREFIX)
+OBJECTS += $(HD1024IMGS) hd1024_combo.img hd1024_qpm.img $(HD1024PREFIX)
 
 OTHERS = blank144 blankhd512 blankhd1024
 
@@ -71,6 +71,7 @@ blankhd1024:
 	@sys= ; \
 	case $@ in \
 		(*cpm22*) sys=../CPM22/cpm_wbw.sys;; \
+		(*qpm*) sys=d_qpm/u0/qpm.sys;; \
 		(*zsdos* | *nzcom* | *dos65*) sys=../ZSDOS/zsys_wbw.sys;; \
 		(*cpm3*) sys=../CPM3/cpmldr.sys;; \
 		(*zpm3*) sys=../ZPM3/zpmldr.sys;; \