Workaround Z280 CPU Bug for LZSA2

The LZSA2 decompressor invoked a known Z280 CPU bug.  A small modification to the code resolves this.

Doc/ChangeLog.txt

@@ -1,7 +1,19 @@
+Version 3.3
+-----------
+- WBW: Support Front Panel switches
+- A?C: Preliminary support for Z80-Retro
+- A?C: Support for SD PIO
+- A?C: Support for Z80-Retro SD interface
+- WBW: Support per-drive floppy configuration
+- WBW: Support for Bill Shen's VGARC
+
 Version 3.2.1
 -------------
 - M?P: Fixed Zeta 2 FDD and CPUSPD config settings
 - WBW: Fixed SURVEY.COM (again)
+- DDW: Updates to DOS/65 binaries in disk images
+- PMS: Updates to VGMPLAY including support for YM2151
+- WBW: Fix for quark delay adjustment being trashed
 
 Version 3.2
 -----------

ReadMe.md

@@ -1,9 +1,9 @@
 
 
 **RomWBW ReadMe** \
-Version 3.2.1 \
+Version 3.3 \
 Wayne Warthen  ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \
-22 Mar 2023
+03 May 2023
 
 # Overview
 

ReadMe.txt

@@ -1,6 +1,6 @@
 RomWBW ReadMe
 Wayne Warthen (wwarthen@gmail.com)
-22 Mar 2023
+03 May 2023
 
 
 

Source/Apps/Survey/survey.mac

@@ -615,6 +615,8 @@ NEXTK:
 	CALL	TYPE
 	DB	' Bytes ROM',TAB,TAB+EOL
 	LHLD	BDOS+1
+	LXI	D,-6
+	DAD	D
 	CALL	BINDEC
 	CALL	TYPE
 	DB	' Bytes in TPA'

Source/Apps/Tune/tune.asm

@@ -45,6 +45,7 @@
 ;   2021-08-13 [WBW] Add support for LiNC Z50 Sound Card
 ;   2021-08-17 [WBW] When playing via HBIOS, call BF_SNDRESET at end
 ;   2022-03-20 [DDW] Add support for MBC PSG module
+;   2023-03-30 [WBW] Fix for quark delay adjustment being trashed
 ;_______________________________________________________________________________
 ;
 ; ToDo:
@@ -301,6 +302,11 @@ GOPT3	LD	A,0			; SETUP value to PT3 sound files
 	JR	GOPTX			; Play PTx file
 
 GOPTX
+	LD	HL,(QDLY)		; Get basic quark delay
+	OR	A			; Clear carry
+	SBC	HL,DE			; Adjust for file type
+	LD	(QDLY),HL		; Save updated quark delay factor
+
 	CALL	CRLF2
 	LD	DE, MSGSONGNAME         ; Print song name message
 	CALL	PRTSTR
@@ -322,10 +328,6 @@ GOPTX2	LD	A,(DE)
 	CALL	CRLF2			; Formatting
 	LD	DE,MSGPLY		; Playing message
 	CALL	PRTSTR			; Print message
-	LD	HL,(QDLY)		; Get basic quark delay
-	OR	A			; Clear carry
-	SBC	HL,DE			; Adjust for file type
-	LD	(QDLY),HL		; Save updated quark delay factor
 	CALL	START			; Do initialization
 PTXLP	CALL	START+5			; Play one quark
 	LD	A,(START+10)		; Get setup byte
@@ -655,8 +657,8 @@ TMP		.DB	0	; work around use of undocumented Z80
 HBIOSMD		.DB	0	; NON-ZERO IF USING HBIOS SOUND DRIVER, ZERO OTHERWISE
 OCTAVEADJ	.DB	0	; AMOUNT TO ADJUST OCTAVE UP OR DOWN
 
-MSGBAN		.DB	"Tune Player for RomWBW v3.5, 20-Mar-2022",0
-MSGUSE		.DB	"Copyright (C) 2021, Wayne Warthen, GNU GPL v3",13,10
+MSGBAN		.DB	"Tune Player for RomWBW v3.5a, 30-Mar-2023",0
+MSGUSE		.DB	"Copyright (C) 2023, Wayne Warthen, GNU GPL v3",13,10
 		.DB	"PTxPlayer Copyright (C) 2004-2007 S.V.Bulba",13,10
 		.DB	"MYMPlay by Marq/Lieves!Tuore",13,10,13,10
 		.DB	"Usage: TUNE <filename>.[PT2|PT3|MYM] [--hbios] [+tn|-tn]",0

Source/Apps/VGM/vgmplay.asm

@@ -12,14 +12,12 @@
 ; default file type, basic file size checking, polled CTC mode
 ; added by Phil Summers
 ;
-; Bugs: YM2151 playback untested & no mute.
-;       CTC polled timing - predicted 44100 divider is too slow
+; Bugs: CTC polled timing - predicted 44100 divider is too slow
 ;
 ; Assemble with:
 ;
 ;   TASM -80 -b VGMPLAY.ASM VGMPLAY.COM
 ;
-;
 ; A VGM file can play 44100 samples a second. This may be sound chip
 ; register commands or PCM data. This player does not support PCM playback
 ; due to the high processor speed and file size required. Typical VGM files
@@ -31,60 +29,59 @@
 ; Device and system specific definitions
 ;------------------------------------------------------------------------------
 ;
-custom		.equ	0           	        ; System configurations
+custom		.equ	0           	; System configurations
 P8X180          .equ    1
 RCBUS           .equ    2
-sbcecb		.equ	3			
+sbcecb		.equ	3		
 MBC		.equ	4
 ;
-plt_romwbw	.equ	1			; Build for ROMWBW?
-plt_type	.equ	sbcecb			; Select build configuration
-debug		.equ	0			; Display port, register, config info
+plt_romwbw	.equ	1		; Build for ROMWBW?
+plt_type	.equ	sbcecb		; Select build configuration
+debug		.equ	0		; Display port, register, config info
 ;
 ;------------------------------------------------------------------------------
 ; Platform specific definitions. If building for ROMWBW, these may be overridden
 ;------------------------------------------------------------------------------
 
 #IF (plt_type=custom)
-RSEL            .equ    09AH			; Primary AY-3-8910 Register selection
-RDAT            .equ    09BH			; Primary AY-3-8910 Register data
-RSEL2           .equ    88H			; Secondary AY-3-8910 Register selection
-RDAT2           .equ    89H			; Secondary AY-3-8910 Register data
+RSEL            .equ    09AH		; Primary AY-3-8910 Register selection
+RDAT            .equ    09BH		; Primary AY-3-8910 Register data
+RSEL2           .equ    88H		; Secondary AY-3-8910 Register selection
+RDAT2           .equ    89H		; Secondary AY-3-8910 Register data
 VGMBASE		.equ	$C0
-YMSEL		.equ	VGMBASE+00H		; Primary YM2162 11000000 a1=0 a0=0
-YMDAT		.equ	VGMBASE+01H		; Primary YM2162 11000001 a1=0 a0=1
-YM2SEL		.equ	VGMBASE+02H		; Secondary YM2162 11000010 a1=1 a0=0
-YM2DAT		.equ	VGMBASE+03H		; Secondary YM2162 11000011 a1=1 a0=1
-PSG1REG         .equ    VGMBASE+08H		; Primary SN76489
-PSG2REG         .equ    VGMBASE+09H		; Secondary SN76489
-ctcbase		.equ	VGMBASE+0CH		; CTC base address
-YM2151_SEL1	.equ	0FEH			; Primary YM2151 register selection
-YM2151_DAT1	.equ	0FFH			; Primary YM2151 register data
-YM2151_SEL2	.equ	0FEH			; Secondary YM2151 register selection
-YM2151_DAT2	.equ	0FFH			; Secondary YM2151 register data
-plt_cpuspd	.equ	6;000000		; Non ROMWBW cpu speed default
-FRAME_DLY       .equ    10  			; Frame delay (~ 1/44100)
-
+YMSEL		.equ	VGMBASE+00H	; Primary YM2162 11000000 a1=0 a0=0
+YMDAT		.equ	VGMBASE+01H	; Primary YM2162 11000001 a1=0 a0=1
+YM2SEL		.equ	VGMBASE+02H	; Secondary YM2162 11000010 a1=1 a0=0
+YM2DAT		.equ	VGMBASE+03H	; Secondary YM2162 11000011 a1=1 a0=1
+PSG1REG         .equ    VGMBASE+04H	; Primary SN76489
+PSG2REG         .equ    VGMBASE+05H	; Secondary SN76489
+YM2151_SEL1	.equ	VGMBASE+08H	; Primary YM2151 register selection
+YM2151_DAT1	.equ	VGMBASE+09H	; Primary YM2151 register data
+YM2151_SEL2	.equ	VGMBASE+0AH	; Secondary YM2151 register selection
+YM2151_DAT2	.equ	VGMBASE+0BH	; Secondary YM2151 register data
+ctcbase		.equ	VGMBASE+0CH	; CTC base address
+plt_cpuspd	.equ	6;000000	; Non ROMWBW cpu speed default
+FRAME_DLY       .equ    10  		; Frame delay (~ 1/44100)
 #ENDIF
 ;
 #IF (plt_type=P8X180)
-RSEL            .equ    82H			; Primary AY-3-8910 Register selection
-RDAT            .equ    83H			; Primary AY-3-8910 Register data
-RSEL2           .equ    88H			; Secondary AY-3-8910 Register selection
-RDAT2           .equ    89H			; Secondary AY-3-8910 Register data
-PSG1REG         .equ    84H			; Primary SN76489
-PSG2REG         .equ    8AH			; Secondary SN76489
-YM2151_SEL1	.equ	0B0H			; Primary YM2151 register selection
-YM2151_DAT1	.equ	0B1H			; Primary YM2151 register data
-YM2151_SEL2	.equ	0B2H			; Secondary YM2151 register selection
-YM2151_DAT2	.equ	0B3H			; Secondary YM2151 register data
-ctcbase		.equ	000H			; CTC base address
-YMSEL		.equ	000H			; Primary YM2162 11000000 a1=0 a0=0
-YMDAT		.equ	000H			; Primary YM2162 11000001 a1=0 a0=1
-YM2SEL		.equ	000H			; Secondary YM2162 11000010 a1=1 a0=0
-YM2DAT		.equ	000H			; Secondary YM2162 11000011 a1=1 a0=1
-FRAME_DLY       .equ    48			; Frame delay (~ 1/44100)
-plt_cpuspd	.equ	20			; Non ROMWBW cpu speed default
+RSEL            .equ    82H		; Primary AY-3-8910 Register selection
+RDAT            .equ    83H		; Primary AY-3-8910 Register data
+RSEL2           .equ    88H		; Secondary AY-3-8910 Register selection
+RDAT2           .equ    89H		; Secondary AY-3-8910 Register data
+PSG1REG         .equ    84H		; Primary SN76489
+PSG2REG         .equ    8AH		; Secondary SN76489
+YM2151_SEL1	.equ	0B0H		; Primary YM2151 register selection
+YM2151_DAT1	.equ	0B1H		; Primary YM2151 register data
+YM2151_SEL2	.equ	0B2H		; Secondary YM2151 register selection
+YM2151_DAT2	.equ	0B3H		; Secondary YM2151 register data
+ctcbase		.equ	000H		; CTC base address
+YMSEL		.equ	000H		; Primary YM2162 11000000 a1=0 a0=0
+YMDAT		.equ	000H		; Primary YM2162 11000001 a1=0 a0=1
+YM2SEL		.equ	000H		; Secondary YM2162 11000010 a1=1 a0=0
+YM2DAT		.equ	000H		; Secondary YM2162 11000011 a1=1 a0=1
+FRAME_DLY       .equ    48		; Frame delay (~ 1/44100)
+plt_cpuspd	.equ	20		; Non ROMWBW cpu speed default
 #ENDIF
 ;
 #IF (plt_type=RCBUS)
@@ -103,7 +100,7 @@ YMSEL		.equ	000H		; UNDEFINED	; Primary YM2162 11000000 a1=0 a0=0
 YMDAT		.equ	000H		; UNDEFINED	; Primary YM2162 11000001 a1=0 a0=1
 YM2SEL		.equ	000H		; UNDEFINED	; Secondary YM2162 11000010 a1=1 a0=0
 YM2DAT		.equ	000H		; UNDEFINED	; Secondary YM2162 11000011 a1=1 a0=1
-plt_cpuspd	.equ	7;372800	; CPUOSC		; Non ROMWBW cpu speed default
+plt_cpuspd	.equ	7;372800	; CPUOSC	; Non ROMWBW cpu speed default
 FRAME_DLY       .equ    12				; Frame delay (~ 1/44100)
 #ENDIF
 ;
@@ -184,7 +181,7 @@ RTCIO		.equ	070H
 ; YM2162 Register write macros - with wait and timeout
 ;------------------------------------------------------------------------------
 ;
-#DEFINE	setreg(reg,val) \
+#DEFINE	s2612reg(reg,val) \
 #DEFCONT \	ld	a,reg 
 #DEFCONT \	out	(YMSEL),a 
 #DEFCONT \	ld	a,val 
@@ -195,7 +192,7 @@ RTCIO		.equ	070H
 #DEFCONT \	jp	nc,$+5
 #DEFCONT \	djnz	$-6
 ;
-#DEFINE	setreg2(reg,val) \
+#DEFINE	s2612reg2(reg,val) \
 #DEFCONT \	ld	a,reg 
 #DEFCONT \	out	(YM2SEL),a 
 #DEFCONT \	ld	a,val 
@@ -205,9 +202,30 @@ RTCIO		.equ	070H
 #DEFCONT \	rlca
 #DEFCONT \	jp	nc,$+5
 #DEFCONT \	djnz	$-6
-
+;
 ;------------------------------------------------------------------------------
-; VGM Codes - see vgmrips.net/wiki/VGM_specification
+; YM2151 Register write macros - with wait and timeout
+;------------------------------------------------------------------------------
+;
+; Status Byte: 	Bit
+;		7       Busy Flag (1=Busy)
+;		6-2     Not Used
+;		1       Timer B Overflow (0=No Overflow, 1=Overflow)
+;		0       Timer A Overflow (0=No Overflow, 1=Overflow)
+;
+#DEFINE	s2151reg(reg,val) \
+#DEFCONT \	ld	a,reg 
+#DEFCONT \	out	(YM2151_SEL1),a 
+#DEFCONT \	ld	a,val 
+#DEFCONT \	out	(YM2151_DAT1),a 
+#DEFCONT \	ld	b,0
+#DEFCONT \	in	a,(YM2151_SEL1)
+#DEFCONT \	rlca
+#DEFCONT \	jp	nc,$+5
+#DEFCONT \	djnz	$-6
+;
+;------------------------------------------------------------------------------
+; VGM Codes - see vgmrips.net/wiki/VGM_Specification
 ;------------------------------------------------------------------------------
 
 VGM_GG_W	.equ	04FH			; GAME GEAR PSG STEREO. WRITE DD TO PORT 0X06
@@ -219,8 +237,8 @@ VGM_WNS		.equ	061H			; WAIT N SAMPLES
 VGM_W735	.equ	062H			; WAIT 735 SAMPLES (1/60TH SECOND)
 VGM_W882	.equ	063H			; WAIT 882 SAMPLES (1/50TH SECOND)
 VGM_ESD		.equ	066H			; END OF SOUND DATA
-VGM_YM21511_W	.equ	054H			; YM2612 #1 WRITE VALUE DD
-VGM_YM21512_W	.equ	0A4H			; YM2612 #2 WRITE VALUE DD
+VGM_YM21511_W	.equ	054H			; YM2151 #1 WRITE VALUE DD
+VGM_YM21512_W	.equ	0A4H			; YM2151 #2 WRITE VALUE DD
 
 ;------------------------------------------------------------------------------
 ; Generic CP/M definitions
@@ -490,7 +508,7 @@ YM2162_2	CP      VGM_YM26122_W
 ;	YM2151 SECTION
 ;
 YM2151_1	CP      VGM_YM21511_W
-                JR      NZ,YM2151_2
+		JR      NZ,YM2151_2
 		LD	A,(HL)
 		OUT	(YM2151_SEL1),A
 		INC	HL
@@ -759,252 +777,254 @@ SKIP1:		LD	A,(IX+0)
                 XOR     A
                 OUT     (RDAT), A
                 OUT     (RDAT2), A
+#IFDEF SBCV2004
 		CALL	FASTIO
+#ENDIF
 
 SKIP2:		LD	A,(IX+0)		; mute all channels on ym2612
 		AND	%00110000
 		JP	Z,SKIP3
 
-		setreg($22,$00)			; lfo off
+		s2612reg($22,$00)		; lfo off
 
-		setreg($27,$00)			; Disable independant Channel 3
-		setreg($28,$00)			; note off ch 1
-		setreg($28,$01)			; note off ch 2
-		setreg($28,$02)			; note off ch 3
-		setreg($28,$04)			; note off ch 4
-		setreg($28,$05)			; note off ch 5
-		setreg($28,$06)			; note off ch 6
-		setreg($2b,$00)			; dac off
+		s2612reg($27,$00)		; Disable independant Channel 3
+		s2612reg($28,$00)		; note off ch 1
+		s2612reg($28,$01)		; note off ch 2
+		s2612reg($28,$02)		; note off ch 3
+		s2612reg($28,$04)		; note off ch 4
+		s2612reg($28,$05)		; note off ch 5
+		s2612reg($28,$06)		; note off ch 6
+		s2612reg($2b,$00)		; dac off
 
-		setreg($b4,$00)			; sound off ch 1-3
-		setreg($b5,$00)
-		setreg($b6,$00)
-		setreg2($b4,$00)		; sound off ch 4-6
-		setreg2($b5,$00)
-		setreg2($b6,$00)
+		s2612reg($b4,$00)		; sound off ch 1-3
+		s2612reg($b5,$00)
+		s2612reg($b6,$00)
+		s2612reg2($b4,$00)		; sound off ch 4-6
+		s2612reg2($b5,$00)
+		s2612reg2($b6,$00)
 
-		setreg($40,$7f)			; ch 1-3 total level minimum
-		setreg($41,$7f)
-		setreg($42,$7f)
-		setreg($44,$7f)
-		setreg($45,$7f)
-		setreg($46,$7f)
-		setreg($48,$7f)
-		setreg($49,$7f)
-		setreg($4a,$7f)
-		setreg($4c,$7f)
-		setreg($4d,$7f)
-		setreg($4e,$7f)
+		s2612reg($40,$7f)		; ch 1-3 total level minimum
+		s2612reg($41,$7f)
+		s2612reg($42,$7f)
+		s2612reg($44,$7f)
+		s2612reg($45,$7f)
+		s2612reg($46,$7f)
+		s2612reg($48,$7f)
+		s2612reg($49,$7f)
+		s2612reg($4a,$7f)
+		s2612reg($4c,$7f)
+		s2612reg($4d,$7f)
+		s2612reg($4e,$7f)
 
-		setreg2($40,$7f)		; ch 4-6 total level minimum
-		setreg2($41,$7f)
-		setreg2($42,$7f)
-		setreg2($44,$7f)
-		setreg2($45,$7f)
-		setreg2($46,$7f)
-		setreg2($48,$7f)
-		setreg2($49,$7f)
-		setreg2($4a,$7f)
-		setreg2($4c,$7f)
-		setreg2($4d,$7f)
-		setreg2($4e,$7f)
+		s2612reg2($40,$7f)		; ch 4-6 total level minimum
+		s2612reg2($41,$7f)
+		s2612reg2($42,$7f)
+		s2612reg2($44,$7f)
+		s2612reg2($45,$7f)
+		s2612reg2($46,$7f)
+		s2612reg2($48,$7f)
+		s2612reg2($49,$7f)
+		s2612reg2($4a,$7f)
+		s2612reg2($4c,$7f)
+		s2612reg2($4d,$7f)
+		s2612reg2($4e,$7f)
 
 #if (0)
 
-		setreg($2a,$00)			; dac value
+		s2612reg($2a,$00)		; dac value
 
-		setreg($24,$00)			; timer A frequency
-		setreg($25,$00)			; timer A frequency
-		setreg($26,$00)			; time B frequency
+		s2612reg($24,$00)		; timer A frequency
+		s2612reg($25,$00)		; timer A frequency
+		s2612reg($26,$00)		; time B frequency
 
-		setreg($30,$00)			; ch 1-3 multiply & detune
-		setreg($31,$00)
-		setreg($32,$00)
-		setreg($34,$00)
-		setreg($35,$00)
-		setreg($36,$00)
-		setreg($38,$00)
-		setreg($39,$00)
-		setreg($3a,$00)
-		setreg($3c,$00)
-		setreg($3d,$00)
-		setreg($3e,$00)
+		s2612reg($30,$00)		; ch 1-3 multiply & detune
+		s2612reg($31,$00)
+		s2612reg($32,$00)
+		s2612reg($34,$00)
+		s2612reg($35,$00)
+		s2612reg($36,$00)
+		s2612reg($38,$00)
+		s2612reg($39,$00)
+		s2612reg($3a,$00)
+		s2612reg($3c,$00)
+		s2612reg($3d,$00)
+		s2612reg($3e,$00)
 
-		setreg2($30,$00)		; ch 4-6 multiply & detune
-		setreg2($31,$00)
-		setreg2($32,$00)
-		setreg2($34,$00)
-		setreg2($35,$00)
-		setreg2($36,$00)
-		setreg2($38,$00)
-		setreg2($39,$00)
-		setreg2($3a,$00)
-		setreg2($3c,$00)
-		setreg2($3d,$00)
-		setreg2($3e,$00)
+		s2612reg2($30,$00)		; ch 4-6 multiply & detune
+		s2612reg2($31,$00)
+		s2612reg2($32,$00)
+		s2612reg2($34,$00)
+		s2612reg2($35,$00)
+		s2612reg2($36,$00)
+		s2612reg2($38,$00)
+		s2612reg2($39,$00)
+		s2612reg2($3a,$00)
+		s2612reg2($3c,$00)
+		s2612reg2($3d,$00)
+		s2612reg2($3e,$00)
 
-		setreg($50,$00)			; ch 1-3 attack rate and scaling
-		setreg($51,$00)
-		setreg($52,$00)
-		setreg($54,$00)
-		setreg($55,$00)
-		setreg($56,$00)
-		setreg($58,$00)
-		setreg($59,$00)
-		setreg($5a,$00)
-		setreg($5c,$00)
-		setreg($5d,$00)
-		setreg($5e,$00)
+		s2612reg($50,$00)		; ch 1-3 attack rate and scaling
+		s2612reg($51,$00)
+		s2612reg($52,$00)
+		s2612reg($54,$00)
+		s2612reg($55,$00)
+		s2612reg($56,$00)
+		s2612reg($58,$00)
+		s2612reg($59,$00)
+		s2612reg($5a,$00)
+		s2612reg($5c,$00)
+		s2612reg($5d,$00)
+		s2612reg($5e,$00)
 
-		setreg2($50,$00)		; ch 4-6 attack rate and scaling
-		setreg2($51,$00)
-		setreg2($52,$00)
-		setreg2($54,$00)
-		setreg2($55,$00)
-		setreg2($56,$00)
-		setreg2($58,$00)
-		setreg2($59,$00)
-		setreg2($5a,$00)
-		setreg2($5c,$00)
-		setreg2($5d,$00)
-		setreg2($5e,$00)
+		s2612reg2($50,$00)		; ch 4-6 attack rate and scaling
+		s2612reg2($51,$00)
+		s2612reg2($52,$00)
+		s2612reg2($54,$00)
+		s2612reg2($55,$00)
+		s2612reg2($56,$00)
+		s2612reg2($58,$00)
+		s2612reg2($59,$00)
+		s2612reg2($5a,$00)
+		s2612reg2($5c,$00)
+		s2612reg2($5d,$00)
+		s2612reg2($5e,$00)
 
-		setreg($60,$00)			; ch 1-3 decay rate and am enable
-		setreg($61,$00)
-		setreg($62,$00)
-		setreg($64,$00)
-		setreg($65,$00)
-		setreg($66,$00)
-		setreg($68,$00)
-		setreg($69,$00)
-		setreg($6a,$00)
-		setreg($6c,$00)
-		setreg($6d,$00)
-		setreg($6e,$00)
+		s2612reg($60,$00)		; ch 1-3 decay rate and am enable
+		s2612reg($61,$00)
+		s2612reg($62,$00)
+		s2612reg($64,$00)
+		s2612reg($65,$00)
+		s2612reg($66,$00)
+		s2612reg($68,$00)
+		s2612reg($69,$00)
+		s2612reg($6a,$00)
+		s2612reg($6c,$00)
+		s2612reg($6d,$00)
+		s2612reg($6e,$00)
 
-		setreg2($60,$00)		; ch 4-6 decay rate and am enable
-		setreg2($61,$00)
-		setreg2($62,$00)
-		setreg2($64,$00)
-		setreg2($65,$00)
-		setreg2($66,$00)
-		setreg2($68,$00)
-		setreg2($69,$00)
-		setreg2($6a,$00)
-		setreg2($6c,$00)
-		setreg2($6d,$00)
-		setreg2($6e,$00)
+		s2612reg2($60,$00)		; ch 4-6 decay rate and am enable
+		s2612reg2($61,$00)
+		s2612reg2($62,$00)
+		s2612reg2($64,$00)
+		s2612reg2($65,$00)
+		s2612reg2($66,$00)
+		s2612reg2($68,$00)
+		s2612reg2($69,$00)
+		s2612reg2($6a,$00)
+		s2612reg2($6c,$00)
+		s2612reg2($6d,$00)
+		s2612reg2($6e,$00)
 
-		setreg($70,$00)			; ch 1-3 sustain rate
-		setreg($71,$00)
-		setreg($72,$00)
-		setreg($74,$00)
-		setreg($75,$00)
-		setreg($76,$00)
-		setreg($78,$00)
-		setreg($79,$00)
-		setreg($7a,$00)
-		setreg($7c,$00)
-		setreg($7d,$00)
-		setreg($7e,$00)
+		s2612reg($70,$00)		; ch 1-3 sustain rate
+		s2612reg($71,$00)
+		s2612reg($72,$00)
+		s2612reg($74,$00)
+		s2612reg($75,$00)
+		s2612reg($76,$00)
+		s2612reg($78,$00)
+		s2612reg($79,$00)
+		s2612reg($7a,$00)
+		s2612reg($7c,$00)
+		s2612reg($7d,$00)
+		s2612reg($7e,$00)
 
-		setreg2($70,$00)		; ch 4-6 sustain rate
-		setreg2($71,$00)
-		setreg2($72,$00)
-		setreg2($74,$00)
-		setreg2($75,$00)
-		setreg2($76,$00)
-		setreg2($78,$00)
-		setreg2($79,$00)
-		setreg2($7a,$00)
-		setreg2($7c,$00)
-		setreg2($7d,$00)
-		setreg2($7e,$00)
+		s2612reg2($70,$00)		; ch 4-6 sustain rate
+		s2612reg2($71,$00)
+		s2612reg2($72,$00)
+		s2612reg2($74,$00)
+		s2612reg2($75,$00)
+		s2612reg2($76,$00)
+		s2612reg2($78,$00)
+		s2612reg2($79,$00)
+		s2612reg2($7a,$00)
+		s2612reg2($7c,$00)
+		s2612reg2($7d,$00)
+		s2612reg2($7e,$00)
 
-		setreg($80,$00)			; ch 1-3 release rate and sustain level
-		setreg($81,$00)
-		setreg($82,$00)
-		setreg($84,$00)
-		setreg($85,$00)
-		setreg($86,$00)
-		setreg($88,$00)
-		setreg($89,$00)
-		setreg($8a,$00)
-		setreg($8c,$00)
-		setreg($8d,$00)
-		setreg($8e,$00)
+		s2612reg($80,$00)		; ch 1-3 release rate and sustain level
+		s2612reg($81,$00)
+		s2612reg($82,$00)
+		s2612reg($84,$00)
+		s2612reg($85,$00)
+		s2612reg($86,$00)
+		s2612reg($88,$00)
+		s2612reg($89,$00)
+		s2612reg($8a,$00)
+		s2612reg($8c,$00)
+		s2612reg($8d,$00)
+		s2612reg($8e,$00)
 
-		setreg2($80,$00)		; ch 4-6 release rate and sustain level
-		setreg2($81,$00)
-		setreg2($82,$00)
-		setreg2($84,$00)
-		setreg2($85,$00)
-		setreg2($86,$00)
-		setreg2($88,$00)
-		setreg2($89,$00)
-		setreg2($8a,$00)
-		setreg2($8c,$00)
-		setreg2($8d,$00)
-		setreg2($8e,$00)
+		s2612reg2($80,$00)		; ch 4-6 release rate and sustain level
+		s2612reg2($81,$00)
+		s2612reg2($82,$00)
+		s2612reg2($84,$00)
+		s2612reg2($85,$00)
+		s2612reg2($86,$00)
+		s2612reg2($88,$00)
+		s2612reg2($89,$00)
+		s2612reg2($8a,$00)
+		s2612reg2($8c,$00)
+		s2612reg2($8d,$00)
+		s2612reg2($8e,$00)
 
-		setreg($90,$00)			; ch 1-3 ssg-eg
-		setreg($91,$00)
-		setreg($92,$00)
-		setreg($94,$00)
-		setreg($95,$00)
-		setreg($96,$00)
-		setreg($98,$00)
-		setreg($99,$00)
-		setreg($9a,$00)
-		setreg($9c,$00)
-		setreg($9d,$00)
-		setreg($9e,$00)
+		s2612reg($90,$00)		; ch 1-3 ssg-eg
+		s2612reg($91,$00)
+		s2612reg($92,$00)
+		s2612reg($94,$00)
+		s2612reg($95,$00)
+		s2612reg($96,$00)
+		s2612reg($98,$00)
+		s2612reg($99,$00)
+		s2612reg($9a,$00)
+		s2612reg($9c,$00)
+		s2612reg($9d,$00)
+		s2612reg($9e,$00)
 
-		setreg2($90,$00)		; ch 4-6 ssg-eg
-		setreg2($91,$00)
-		setreg2($92,$00)
-		setreg2($94,$00)
-		setreg2($95,$00)
-		setreg2($96,$00)
-		setreg2($98,$00)
-		setreg2($99,$00)
-		setreg2($9a,$00)
-		setreg2($9c,$00)
-		setreg2($9d,$00)
-		setreg2($9e,$00)
+		s2612reg2($90,$00)		; ch 4-6 ssg-eg
+		s2612reg2($91,$00)
+		s2612reg2($92,$00)
+		s2612reg2($94,$00)
+		s2612reg2($95,$00)
+		s2612reg2($96,$00)
+		s2612reg2($98,$00)
+		s2612reg2($99,$00)
+		s2612reg2($9a,$00)
+		s2612reg2($9c,$00)
+		s2612reg2($9d,$00)
+		s2612reg2($9e,$00)
 
-		setreg($a0,$00)			; ch 1-3 frequency
-		setreg($a1,$00)
-		setreg($a2,$00)
-		setreg($a4,$00)
-		setreg($a5,$00)
-		setreg($a6,$00)
-;		setreg($a8,$00)			; ch 3 special mode
-;		setreg($a9,$00)
-;		setreg($aa,$00)
-;		setreg($ac,$00)
-;		setreg($ad,$00)
-;		setreg($ae,$00)
+		s2612reg($a0,$00)		; ch 1-3 frequency
+		s2612reg($a1,$00)
+		s2612reg($a2,$00)
+		s2612reg($a4,$00)
+		s2612reg($a5,$00)
+		s2612reg($a6,$00)
+;		s2612reg($a8,$00)		; ch 3 special mode
+;		s2612reg($a9,$00)
+;		s2612reg($aa,$00)
+;		s2612reg($ac,$00)
+;		s2612reg($ad,$00)
+;		s2612reg($ae,$00)
 
-		setreg2($a0,$00)		; ch 4-6 frequency
-		setreg2($a1,$00)
-		setreg2($a2,$00)
-		setreg2($a4,$00)
-		setreg2($a5,$00)
-		setreg2($a6,$00)
-;		setreg2($a8,$00)		; ch 3 special mode
-;		setreg2($a9,$00)
-;		setreg2($aa,$00)
-;		setreg2($ac,$00)
-;		setreg2($ad,$00)
-;		setreg2($ae,$00)
+		s2612reg2($a0,$00)		; ch 4-6 frequency
+		s2612reg2($a1,$00)
+		s2612reg2($a2,$00)
+		s2612reg2($a4,$00)
+		s2612reg2($a5,$00)
+		s2612reg2($a6,$00)
+;		s2612reg2($a8,$00)		; ch 3 special mode
+;		s2612reg2($a9,$00)
+;		s2612reg2($aa,$00)
+;		s2612reg2($ac,$00)
+;		s2612reg2($ad,$00)
+;		s2612reg2($ae,$00)
 
-		setreg($b0,$00)			; ch 1-3 algorith + feedback
-		setreg($b1,$00)
-		setreg($b2,$00)
-		setreg2($b0,$00)		; ch 4-6 algorith + feedback
-		setreg2($b1,$00)
-		setreg2($b2,$00)
+		s2612reg($b0,$00)		; ch 1-3 algorith + feedback
+		s2612reg($b1,$00)
+		s2612reg($b2,$00)
+		s2612reg2($b0,$00)		; ch 4-6 algorith + feedback
+		s2612reg2($b1,$00)
+		s2612reg2($b2,$00)
 
 #endif
 		
@@ -1014,6 +1034,64 @@ SKIP3:		LD	A,(IX+0)		; For YM2151 ... Unimplemented
 
 		; MUTE YM2151
 
+		s2151reg($14,$30)		; disable timer %00110000		
+
+		s2151reg($0f,$00)		; disable noise
+;
+		s2151reg($1b,$00)		; CTx output off, LFO waveform
+
+		s2151reg($08,$00)		; key off all channels
+		s2151reg($08,$01)
+		s2151reg($08,$02)
+		s2151reg($08,$03)
+		s2151reg($08,$04)
+		s2151reg($08,$05)
+		s2151reg($08,$06)
+		s2151reg($08,$07)
+
+		s2151reg($60,$7f)		; total level = silent
+		s2151reg($61,$7f)
+		s2151reg($62,$7f)
+		s2151reg($63,$7f)
+		s2151reg($64,$7f)
+		s2151reg($65,$7f)
+		s2151reg($66,$7f)
+		s2151reg($67,$7f)
+		s2151reg($68,$7f)
+		s2151reg($69,$7f)
+		s2151reg($6A,$7f)
+		s2151reg($6B,$7f)
+		s2151reg($6C,$7f)
+		s2151reg($6D,$7f)
+		s2151reg($6E,$7f)
+		s2151reg($6F,$7f)
+		s2151reg($70,$7f)
+		s2151reg($71,$7f)
+		s2151reg($72,$7f)
+		s2151reg($73,$7f)
+		s2151reg($74,$7f)
+		s2151reg($75,$7f)
+		s2151reg($76,$7f)
+		s2151reg($77,$7f)
+		s2151reg($78,$7f)
+		s2151reg($79,$7f)
+		s2151reg($7A,$7f)
+		s2151reg($7B,$7f)
+		s2151reg($7C,$7f)
+		s2151reg($7D,$7f)
+		s2151reg($7E,$7f)
+		s2151reg($7F,$7f)
+
+		s2151reg($20,$00)		; channel output off, no feedback
+		s2151reg($21,$00)
+		s2151reg($22,$00)
+		s2151reg($23,$00)
+		s2151reg($24,$00)
+		s2151reg($25,$00)
+		s2151reg($26,$00)
+		s2151reg($27,$00)
+;
+
 SKIP4		RET
 ;
 ;------------------------------------------------------------------------------

Source/Apps/VGM/vgmplay.txt

@@ -21,7 +21,7 @@ Supported platforms
 ===================
 
 VGM Player is currently being developed on the ROMWBW platform using the Retrobrew computers
-EBC-SBC-V2 (Z80), ECB-SCG (AY-3-8910) and ECB-VGM (YM2612 and 2xSN76489) board. 
+EBC-SBC-V2 (Z80), ECB-SCG (AY-3-8910) and ECB-VGM (YM2612,YM2151 2xSN76489) board. 
 It can be configured to run with other hardware such as RCBus, P8X180 and nhyodyne MBC.
 
 VGM files can be very big and are limited in size by the available TPA space, which is typically 52k.
@@ -50,13 +50,15 @@ FIELDMAP.VGM - SN76489+YM2612      - Taikou Risshiden: Field Map: Summer
 ITSGAMOV.VGM - SN76489+YM2612      - Puyo Puyo Tsuu: It's Game Over!                              : 16K
 STARTDEM.VGN - 2xSN76489+AY-3-8910 * Exed Exes / Savage Bees: Start Demo ~Main BGM                : 32K
 INCHINA.VGM  - YM2612              * Double Dragon 3: The Rosetta Stone: In China                 : 44K
-
+SURE.VGM     - YM2151              - Martial Age: Sure??                                          : 36K
+SABERDAN.VGM - YM2151              - Road Runner: Sabre Dance (Attract Mode - Stage 4)            : 28K
 * Included in disk images
 
 VGM sources
 ===========
 https://www.smspower.org/forums/15359-VGMPacksGameGearMegaCollection
 https://vgmrips.net/packs/chip/ym2612
+https://vgmrips.net/packs/chip/ym2151 
 https://project2612.org/
 
 VGM Tools

Source/Doc/Applications.md

@@ -1028,3 +1028,81 @@ hardware interface code is specific to RomWBW and the application will
 not operate correctly on non-RomWBW systems.
 
 The source code is provided in the RomWBW distribution.
+
+
+`\clearpage`{=latex}
+
+# VGMPLAY
+
+This application will allow you to play Video Game Music files. VGM 
+files contain music samples from a range of different sound chips 
+that were used in arcade games, game consoles and personal computer 
+systems.
+
+Video Game Music files have a .VGM file extension and each file 
+contains an embedded header that identifies the hardware it is 
+intended for and also the title of the music.
+
+All RomWBW operating system boot disks include a selection of sound
+files in user area 3. Additional music files can be found at:
+
+[VGMRIPS website](https://vgmrips.net)
+
+[PROJECT2612 website](https://project2612.org/)
+
+Sound files are loaded into memory for playback, so the maximum size
+file that can be played is around 52Kb.
+
+Sound chips currently supported are:
+
+* AY-3-8190 (and equivalent YM2149)
+* YM2612 (and equivalent YM3848)
+* SN76489 (single chip mono and dual chip stereo)
+* YM2151 
+
+VGMPLAY supports playback of files with multiple combinations of these
+chips.
+
+## Syntax
+
+`VGMPLAY `*`<filename>`*
+
+*`<filename>`* is the name of a sound file ending in .VGM
+
+## Usage
+
+VGMPLAY does not automatically detect the hardware platform or sound
+hardware that you are using. This means a version customized for your
+system must be assembled before use.
+
+To play a sound file, just use the VGMPLAY command and specify the file
+to play after the command. So, for example, `VGMPLAY TEDDY` will load
+the TEDDY.VGM sound file into memory and begin playing it.
+
+Playback can be stopped by pressing a key. There may be a delay before
+playback stops.
+
+## Notes
+
+The default build configuration for VGMPLAY is:
+
+CPU speed: Autodetected
+
+| chip      | number  | port     | notes
+| --------- | ------- | -------- | ----------
+| AY-3-8910 |  1st    | 09ah     | stereo
+| AY-3-8910 |  2nd    | not set  | stereo
+| YM2612    |  1st    | 0c0h     | stereo
+| YM2612    |  2nd    | 0c4h     | stereo
+| SN76489   |  1st    | 0c8h     | mono/left
+| SN76489   |  2nd    | 0c9h     | mono/right
+| YM2151    |  1st    | 0cah     | stereo
+| YM2151    |  2nd    | 0cbh     | stereo
+
+Inconsistant, garbled or distorted playback can be an indication that
+your CPU clock speed is too high for your sound chip. In this case, if 
+your platform supports speed switching, then the CPUSPD application 
+can be used to reduce your processor speed.
+
+VGMPLAY is still under development. The source code is provided in the 
+RomWBW distribution.

Source/Doc/Basic.h

@@ -1,4 +1,4 @@
-$define{doc_ver}{Version 3.2.1}$
+$define{doc_ver}{Version 3.3}$
 $define{doc_product}{RomWBW}$
 $define{doc_root}{https://github.com/wwarthen/RomWBW/raw/dev/Doc}$
 $ifndef{doc_title}$ $define{doc_title}{Document Title}$ $endif$

Source/Doc/SystemGuide.md

@@ -2123,6 +2123,17 @@ Wait States (D) is the actual number of wait states, not the number
 of wait states added.  The returned Status (A) is a standard HBIOS 
 result code.
 
+#### SYSGET Subfunction 0xF4 -- Get Front Panel Swithes (PANEL)
+
+| **Entry Parameters**                   | **Returned Values**                    |
+|----------------------------------------|----------------------------------------|
+| B: 0xF8                                | A: Status                              |
+| C: 0xF4                                | L: Switches                            |
+
+This function will return the current value of the switches (L) from the
+front panel of the system.  If no front panel is available in the
+system, the returned Status (A) will indicate a No Hardware error.
+
 ### Function 0xF9 -- System Set (SYSSET)
 
 | **Entry Parameters**                   | **Returned Values**                    |
@@ -2206,6 +2217,18 @@ limited set of divisors.  If there is no satisfactory divisor to
 retain the existing baud rate under the new CPU speed, then the baud
 rate of the ASCI port(s) will be affected.
 
+#### SYSSET Subfunction 0xF4 -- Set Front Panel LEDs (PANEL)
+
+| **Entry Parameters**                   | **Returned Values**                    |
+|----------------------------------------|----------------------------------------|
+| B: 0xF9                                | A: Status                              |
+| C: 0xF4                                |                                        |
+| L: LEDs                                |                                        |
+
+This function will set the front panel LEDs based on the bits in L. If 
+no front panel is available in the system, the returned Status (A) will 
+indicate a No Hardware error.
+
 ### Function 0xFA -- System Peek (SYSPEEK)
 
 | **Entry Parameters**                   | **Returned Values**                    |

Source/Doc/UserGuide.md

@@ -201,6 +201,7 @@ below, **carefully** pick the appropriate ROM image for your hardware.
 | [Z80 ZRC CPU Module]^7^                                        | RCBus   | RCZ80_zrc.rom      | 115200        |
 | [Z280 ZZRCC CPU Module]^7^                                     | RCBus   | RCZ280_zzrc.rom    | 115200        |
 | [Z280 ZZ80MB SBC]^7^                                           | RCBus   | RCZ280_zz80mb.rom  | 115200        |
+| [Z80-Retro SBC]^8^                                             | -       | Z80RETRO_std.rom   | 38400         |
 
 | ^1^Designed by Andrew Lynch
 | ^2^Designed by Sergey Kiselev
@@ -209,6 +210,7 @@ below, **carefully** pick the appropriate ROM image for your hardware.
 | ^5^Designed by Stephen Cousins
 | ^6^Designed by Steve Garcia
 | ^7^Designed by Bill Shen
+| ^8^Designed by Peter Wilson
 
 RCBus refers to Spencer Owen's RC2014 bus specification and derivatives
 including RC26, RC40, RC80, and BP80.
@@ -782,6 +784,55 @@ The use of diagnostic levels above 4 are really intended only for
 software developers.  I do not recommend changing this under
 normal circumstances.
 
+## Front Panel
+
+RomWBW supports the concept of a simple front panel.  The following 
+image is a conceptual view of such a front panel.  If your system has a 
+front panel, it should look similar to the [RomWBW Front Panel](#panel).
+
+![RomWBW Front Panel](Graphics/Panel){#panel width=50% }
+
+The LEDs in the top row of the panel are used for multiple purposes.
+They are initially used to display the progress of the
+system boot.  This may help in diagnosing a hardware or configuration
+issue in a system that does not progress far enough to display text
+output on the console.  The meaning of the LEDs is:
+
+|            |                              |
+|------------|------------------------------|
+| `O-------` | System Boot has started      |
+| `OO------` | Common RAM bank activated    |
+| `OOO-----` | HBIOS transitioned to RAM    |
+| `OOOO----` | Basic initialization done    |
+| `OOOOO---` | CPU detection complete       |
+| `OOOOOO--` | System timer configured      |
+| `OOOOOOO-` | Pre-console device init done |
+| `OOOOOOOO` | Console activation           |
+
+Once the system has booted, the LEDs are used to indicate disk device
+activity.  Each LED numbered 7-0 represents disk units 7-0.  As each
+disk device performs I/O, the LED will light.
+
+The second row of the front panel is composed of switches that allow
+you to control a few aspects of the system startup.
+
+The first two switches affect the device used as the console initially.
+Setting the CRT/Serial switch will cause the system to boot directly 
+to an attached CRT device (if available).  Setting the Pri/Sec switch 
+will cause the system to boot to the secondary Serial or CRT device 
+(depending on the setting of the first switch).
+
+The final six switches allow you to cause the system to automatically
+boot into a desired function.  The Auto/Menu switch must be set to
+enable this, otherwise the normal ROM Loader prompt will be used.
+If the Disk/ROM switch is not set, then you can use the last 3
+switches to select a ROM app to auto-start.  If the Disk/ROM switch is
+set, then the system will attempt a disk boot based on the following
+switches.  The Floppy/Hard switch can be used to boot to a Floppy or
+Hard Disk.  In either case, the first Floppy or Hard Disk will be used
+for the boot.  If a Hard Disk boot is selected, then the last three
+switches can be used to select any of the first 8 slices.
+
 # Disk Management
 
 The systems supported by RomWBW all have the ability to use persistent
@@ -3757,6 +3808,7 @@ the RomWBW HBIOS configuration.
    - WDC Floppy Disk Controller w/ 3.5" HD Drives
    - Onboard IDE Hard Disk Interface Module
    - PPIDE Hard Disk Interface Module
+   - VGARC Video & Keyboard Module
  - Serial baud rate is usually determined by hardware for ACIA and
    SIO interfaces
 
@@ -3780,6 +3832,7 @@ the RomWBW HBIOS configuration.
    - WDC Floppy Disk Controller w/ 3.5" HD Drives
    - Onboard IDE Hard Disk Interface Module
    - PPIDE Hard Disk Interface Module
+   - VGARC Video & Keyboard Module
  - Serial baud rate is usually determined by hardware for ACIA and
    SIO interfaces
 
@@ -3803,11 +3856,27 @@ the RomWBW HBIOS configuration.
    - WDC Floppy Disk Controller w/ 3.5" HD Drives
    - Onboard IDE Hard Disk Interface Module
    - PPIDE Hard Disk Interface Module
+   - VGARC Video & Keyboard Module
  - Serial baud rate is usually determined by hardware for ACIA and
    SIO interfaces
 
 `\clearpage`{=latex}
 
+### Z80-Retro SBC
+
+|                   |                  |
+|-------------------|------------------|
+| ROM Image File    | Z80RETRO_std.rom |
+| Console Baud Rate | 38400            |
+| Interrupts        | Mode 2           |
+
+ - CPU speed is assumed to be 14.7456 MHz
+ - Hardware auto-detected:
+   - SIO Serial Interface Module
+   - Onboard CTC
+
+`\clearpage`{=latex}
+
 ## Appendix B - Device Summary
 
 The table below briefly describes each of the possible devices that
@@ -3857,5 +3926,6 @@ may be discovered by RomWBW in your system.
 | USB-FIFO  | Char     | FT232H-based ECB USB FIFO                              |
 | VDU       | Video    | MC6845 Family Video Display Controller                 |
 | VGA       | Video    | HD6445CP4-based Video Display Controller               |
+| VRC       | Video    | VGARC Video Display Controller                         |
 | YM        | Audio    | YM2612 Programmable Sound Generator                    |
 | Z2U       | Char     | Zilog Z280 CPU Built-in Serial Ports                   |

Source/Fonts/Build.cmd

@@ -11,8 +11,8 @@ echo Preparing compressed font files...
 lzsa -f2 -r font8x8u.bin font8x8c.bin || exit /b
 lzsa -f2 -r font8x11u.bin font8x11c.bin || exit /b
 lzsa -f2 -r font8x16u.bin font8x16c.bin || exit /b
-
 lzsa -f2 -r fontcgau.bin fontcgac.bin || exit /b
+lzsa -f2 -r fontvgarcu.bin fontvgarcc.bin || exit /b
 
 fonttool font8x8u.bin > font8x8u.asm || exit /b
 fonttool font8x11u.bin > font8x11u.asm || exit /b
@@ -20,6 +20,7 @@ fonttool font8x16u.bin > font8x16u.asm || exit /b
 fonttool font8x8c.bin > font8x8c.asm || exit /b
 fonttool font8x11c.bin > font8x11c.asm || exit /b
 fonttool font8x16c.bin > font8x16c.asm || exit /b
-
 fonttool fontcgau.bin > fontcgau.asm || exit /b
 fonttool fontcgac.bin > fontcgac.asm || exit /b
+fonttool fontvgarcu.bin > fontvgarcu.asm || exit /b
+fonttool fontvgarcc.bin > fontvgarcc.asm || exit /b

Source/Fonts/Makefile

@@ -1,8 +1,8 @@
 OBJECTS = \
-	font8x8u.asm font8x11u.asm font8x16u.asm fontcgau.asm \
-	font8x8c.asm font8x11c.asm font8x16c.asm fontcgac.asm
+	font8x8u.asm font8x11u.asm font8x16u.asm fontcgau.asm fontvgarcu.asm \
+	font8x8c.asm font8x11c.asm font8x16c.asm fontcgac.asm fontvgarcc.asm
 
-OTHERS = font8x8c.bin font8x11c.bin font8x16c.bin fontcgac.bin
+OTHERS = font8x8c.bin font8x11c.bin font8x16c.bin fontcgac.bin fontvgarcc.bin
 
 TOOLS = ../../Tools
 
@@ -26,5 +26,8 @@ font8x16c.bin: font8x16u.bin
 fontcgac.bin: fontcgau.bin
 	$(BINDIR)/lzsa -f2 -r $< $@
 
+fontvgarcc.bin: fontvgarcu.bin
+	$(BINDIR)/lzsa -f2 -r $< $@
+
 %.asm: %.bin
 	$(BINDIR)/bin2asm $< > $@

Source/HBIOS/API.txt

@@ -117,7 +117,11 @@ GET ($F8):
 						L=Clock Mult (0:Half, 1:Full, 2: Double)
 						D=Memory Wait States
 						E=I/O Wait States
-						
+
+    PANEL ($F4):
+      BC=Function/Subfunction			A=Result
+						L=Switch Values
+
 
 SET ($F9):
   BC=Function/Subfunction                       A=Result
@@ -142,6 +146,11 @@ SET ($F9):
 						E=I/O Wait States
 						
 
+    PANEL ($F4):
+      BC=Function/Subfunction			A=Result
+						L=LED Values
+
+
 PEEK ($FA):
   B=Function                       		A=Result
   D=Bank					E=Byte Value

Source/HBIOS/Build.cmd

@@ -223,5 +223,6 @@ call Build SCZ180 sc503 || exit /b
 call Build DYNO std || exit /b
 call Build UNA std || exit /b
 call Build RPH std || exit /b
+call Build Z80RETRO std || exit /b
 
 goto :eof

Source/HBIOS/Build.ps1

@@ -27,7 +27,7 @@ $ErrorAction = 'Stop'
 # UNA BIOS is simply imbedded, it is not built here.
 #
 
-$PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "UNA"
+$PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "Z80RETRO", "UNA"
 $PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO", "RPH"
 $PlatformListZ280 = "RCZ280"
 

Source/HBIOS/Build.sh

@@ -38,6 +38,7 @@ if [ "${ROM_PLATFORM}" == "dist" ] ; then
 	ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc140"; bash Build.sh
 	ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc503"; bash Build.sh
 	ROM_PLATFORM="UNA"; ROM_CONFIG="std"; bash Build.sh
+	ROM_PLATFORM="Z80RETRO"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="ZETA"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="ZETA2"; ROM_CONFIG="std"; bash Build.sh
 	exit

Source/HBIOS/Config/RCZ180_ext.asm

@@ -29,6 +29,9 @@
 CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
+FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+;
 MEMMGR		.SET	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
 ;
 Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
@@ -46,6 +49,7 @@ SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
 TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
 MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
 ;
 ;

Source/HBIOS/Config/RCZ180_nat.asm

@@ -29,6 +29,9 @@
 CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
+FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+;
 MEMMGR		.SET	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
 ;
 Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
@@ -46,9 +49,9 @@ SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
 TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
 MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
 ;
-;
 AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 AYMODE		.SET	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER

Source/HBIOS/Config/RCZ280_ext.asm

@@ -30,6 +30,9 @@ CPUOSC		.SET	12000000	; CPU OSC FREQ IN MHZ
 INTMODE		.SET	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
+FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+;
 MEMMGR		.SET	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
 ;
 Z280_MEMLOWAIT	.SET	0		; Z280: LOW 8MB MEMORY WAIT STATES (0-3)
@@ -45,6 +48,7 @@ SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
 TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
 MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
 ;
 AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER

Source/HBIOS/Config/RCZ280_nat.asm

@@ -30,6 +30,9 @@ CPUOSC		.SET	12000000	; CPU OSC FREQ IN MHZ
 INTMODE		.SET	3		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
+FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+;
 MEMMGR		.SET	MM_Z280		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 ;
 Z280_MEMLOWAIT	.SET	0		; Z280: LOW 8MB MEMORY WAIT STATES (0-3)
@@ -45,6 +48,7 @@ SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
 TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
 MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
 ;
 AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER

Source/HBIOS/Config/RCZ280_zz80mb.asm

@@ -32,6 +32,9 @@ CPUOSC		.SET	12000000	; CPU OSC FREQ IN MHZ
 INTMODE		.SET	3		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
+FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+;
 MEMMGR		.SET	MM_Z280		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 ;
 RAMLOC		.SET	23		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
@@ -51,7 +54,8 @@ SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
 TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
 MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
-VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+VRCENABLE	.SET	TRUE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
 ;
 AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]

Source/HBIOS/Config/RCZ280_zzrc.asm

@@ -32,6 +32,9 @@ CPUOSC		.SET	14745600	; CPU OSC FREQ IN MHZ
 INTMODE		.SET	3		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
+FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+;
 MEMMGR		.SET	MM_Z280		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 ;
 RAMSIZE		.SET	256		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
@@ -59,7 +62,8 @@ SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
 TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
 MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
-VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+VRCENABLE	.SET	TRUE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
 ;
 AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]

Source/HBIOS/Config/RCZ80_easy.asm

@@ -33,11 +33,12 @@ CPUOSC		.SET	10000000	; CPU OSC FREQ IN MHZ
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 ;
+FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+;
 WDOGMODE	.SET	WDOG_EZZ80	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 WDOGIO		.SET	$6F		; WATCHDOG REGISTER ADR
 ;
-DIAGENABLE	.SET	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
-;
 DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
 ;
@@ -60,6 +61,7 @@ TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
 MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
 ;
 AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER

Source/HBIOS/Config/RCZ80_kio.asm

@@ -30,6 +30,9 @@ CPUOSC		.SET	7372800		; CPU OSC FREQ IN MHZ
 INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
+FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+;
 DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
 KIOENABLE	.SET	TRUE		; ENABLE ZILOG KIO SUPPORT
@@ -55,6 +58,7 @@ TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
 MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
 ;
 AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER

Source/HBIOS/Config/RCZ80_skz.asm

@@ -29,6 +29,9 @@
 CPUOSC		.SET	7372800		; CPU OSC FREQ IN MHZ
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
+FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+;
 SKZENABLE	.SET	TRUE		; ENABLE SERGEY'S Z80-512K FEATURES
 SKZDIV		.SET	DIV_12		; UART CLK (CLK2) DIVIDER FOR Z80-512K
 WDOGMODE	.SET	WDOG_SKZ	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
@@ -50,6 +53,7 @@ TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
 MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
 ;
 AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER

Source/HBIOS/Config/RCZ80_std.asm

@@ -29,6 +29,9 @@
 CPUOSC		.SET	7372800		; CPU OSC FREQ IN MHZ
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
+FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+;
 DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
 ;
@@ -41,6 +44,7 @@ TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
 MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
 ;
 AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
@@ -53,6 +57,7 @@ FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
 SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.SET	SDMODE_PIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|USR]
 SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY
 ;
 PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)

Source/HBIOS/Config/RCZ80_tiny.asm

@@ -33,11 +33,13 @@ CPUOSC		.SET	16000000	; CPU OSC FREQ IN MHZ
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 ;
+FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+;
 EIPCENABLE	.SET	TRUE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 WDOGMODE	.SET	WDOG_EZZ80	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 WDOGIO		.SET	$6F		; WATCHDOG REGISTER ADR
 ;
-DIAGENABLE	.SET	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 LEDENABLE	.SET	TRUE		; ENABLES STATUS LED (SINGLE LED)
 LEDPORT		.SET	$6E		; STATUS LED PORT ADDRESS
 ;
@@ -65,6 +67,7 @@ TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
 MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
 ;
 AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER

Source/HBIOS/Config/RCZ80_zrc.asm

@@ -30,6 +30,9 @@
 CPUOSC		.SET	14745600	; CPU OSC FREQ IN MHZ
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
+FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPSW_ENABLE     .SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+;
 RAMSIZE		.SET	1536		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 MEMMGR		.SET	MM_ZRC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
 ;
@@ -42,7 +45,8 @@ TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
 MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
-VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+VRCENABLE	.SET	TRUE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
 ;
 AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]

Source/HBIOS/Config/RCZ80_zrc_ram.asm

@@ -31,6 +31,9 @@
 CPUOSC		.SET	7372800		; CPU OSC FREQ IN MHZ
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
+FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+;
 RAMSIZE		.SET	2048		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.SET	0		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
 MEMMGR		.SET	MM_ZRC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
@@ -46,6 +49,7 @@ TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
 MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+VRCENABLE	.SET	TRUE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
 ;
 AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER

Source/HBIOS/Config/SBC_max.asm

@@ -35,7 +35,8 @@ USELZSA2	.SET	TRUE		; ENABLE FONT COMPRESSION
 ;
 KIOENABLE	.SET	TRUE		; ENABLE ZILOG KIO SUPPORT
 ;
-DIAGENABLE	.SET	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
+FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
 ;
 DSKYENABLE	.SET	TRUE		; ENABLES DSKY (DO NOT COMBINE WITH PPIDE)
 ;

Source/HBIOS/Config/SBC_simh.asm

@@ -30,6 +30,9 @@ INTMODE		.SET	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 ;
 HTIMENABLE	.SET	TRUE		; ENABLE SIMH TIMER SUPPORT
 ;
+SIMRTCENABLE	.SET	TRUE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+DSRTCENABLE	.SET	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+;
 UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 UARTSBCFORCE	.SET	TRUE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 ;

Source/HBIOS/Config/SCZ180_sc126.asm

@@ -35,8 +35,9 @@ Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
 Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
 Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 ;
-DIAGENABLE	.SET	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
-DIAGPORT	.SET	$0D		; DIAGNOSTIC PORT ADDRESS
+FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+FPLED_IO	.SET	$0D		; FP: PORT ADDRESS FOR FP LEDS
 ;
 DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 INTRTCENABLE	.SET	TRUE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
@@ -50,6 +51,7 @@ TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
 MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
 ;
 AY38910ENABLE	.SET	TRUE		; AY: AY-3-8910 / YM2149 SOUND DRIVER

Source/HBIOS/Config/SCZ180_sc130.asm

@@ -35,8 +35,10 @@ Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
 Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
 Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 ;
+FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+;
 LEDENABLE	.SET	TRUE		; ENABLE STATUS LED (SINGLE LED)
-DIAGENABLE	.SET	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 ;
 DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 INTRTCENABLE	.SET	TRUE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
@@ -50,6 +52,7 @@ TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
 MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
 ;
 AY38910ENABLE	.SET	TRUE		; AY: AY-3-8910 / YM2149 SOUND DRIVER

Source/HBIOS/Config/SCZ180_sc131.asm

@@ -34,8 +34,10 @@ Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
 Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
 Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 ;
+FPLED_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPSW_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+;
 LEDENABLE	.SET	TRUE		; ENABLE STATUS LED (SINGLE LED)
-DIAGENABLE	.SET	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 ;
 DSRTCENABLE	.SET	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 INTRTCENABLE	.SET	TRUE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)

Source/HBIOS/Config/SCZ180_sc140.asm

@@ -34,9 +34,10 @@ Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
 Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
 Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 ;
+FPLED_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPSW_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+;
 LEDENABLE	.SET	TRUE		; ENABLE STATUS LED (SINGLE LED)
-DIAGENABLE	.SET	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
-DIAGPORT	.SET	$A0		; DIAGNOSTIC PORT ADDRESS
 ;
 DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 INTRTCENABLE	.SET	TRUE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)

Source/HBIOS/Config/SCZ180_sc503.asm

@@ -34,9 +34,10 @@ Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
 Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
 Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 ;
+FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+;
 LEDENABLE	.SET	TRUE		; ENABLE STATUS LED (SINGLE LED)
-DIAGENABLE	.SET	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
-DIAGPORT	.SET	$A0		; DIAGNOSTIC PORT ADDRESS
 ;
 DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 INTRTCENABLE	.SET	TRUE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)

Source/HBIOS/Config/Z80RETRO_std.asm

@@ -0,0 +1,35 @@
+;
+;==================================================================================================
+;   ZETA2 STANDARD CONFIGURATION
+;==================================================================================================
+;
+; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
+; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
+; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
+; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
+; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
+; YOUR FILE IN THE BUILD PROCESS.
+;
+; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
+; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
+; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
+; SETTINGS.
+;
+; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
+; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
+; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
+; DIRECTORIES ABOVE THIS ONE).
+;
+#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
+;
+#include "cfg_z80retro.asm"
+;
+CPUOSC		.SET	14745600	; CPU OSC FREQ IN MHZ
+INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+;
+UARTENABLE	.SET	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+;
+SDENABLE	.SET	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)

Source/HBIOS/Makefile

@@ -24,7 +24,8 @@ endif
 
 include $(TOOLS)/Makefile.inc
 
-FONTS := font8x11c.asm font8x11u.asm font8x16c.asm font8x16u.asm font8x8c.asm font8x8u.asm fontcgac.asm fontcgau.asm
+FONTS := font8x11c.asm font8x11u.asm font8x16c.asm font8x16u.asm font8x8c.asm font8x8u.asm \
+	fontcgac.asm fontcgau.asm fontvgarcc.asm fontvgarcu.asm
 
 ifeq ($(CPUFAM),2)
 	TASM=$(BINDIR)/uz80as -t hd64180

Source/HBIOS/ansi.asm

@@ -634,9 +634,9 @@ ANSI_BEL:
 ANSI_BS:
 	LD	A,(ANSI_COL)	; GET CURRENT COLUMN
 	DEC	A		; BACK IT UP BY ONE
-	RET	C		; IF CARRY, MARGIN EXCEEDED, ABORT
+	RET	M		; IF CARRY, MARGIN EXCEEDED, ABORT
 	LD	(ANSI_COL),A	; SAVE NEW COLUMN
-	JP	ANSI_XY		; UDPATE CUSROR AND RETURN
+	JP	ANSI_XY		; UDPATE CURSOR AND RETURN
 ;
 ANSI_CR:
 	XOR	A		; ZERO ACCUM

Source/HBIOS/asci.asm

@@ -53,7 +53,7 @@
 ; ASEXT:
 ; 7 6 5 4 3 2 1 0
 ; R D C X B F D S
-; 0 1 1 0 0 1 1 0   DEFAULT VALUES
+; 0 1 1 0 0 0 0 0   DEFAULT VALUES
 ; | | | | | | | |
 ; | | | | | | | +-- SEND BREAK
 ; | | | | | | +---- BREAK DETECT (RO)
@@ -64,6 +64,10 @@
 ; | +-------------- DCD0 DISABLE
 ; +---------------- RDRF INT INHIBIT
 ;
+ASCI_DEF_CNTLA	.EQU	$64
+ASCI_DEF_CNTLB	.EQU	$20
+ASCI_DEF_ASEXT	.EQU	$60
+;
 ASCI_BUFSZ	.EQU	32		; RECEIVE RING BUFFER SIZE
 ;
 ASCI_NONE	.EQU	0		; NOT PRESENT
@@ -513,17 +517,29 @@ ASCI_INITDEV3:
 	SET	4,C			; SET CNTLB BIT 4 FOR ODD PARITY
 ;
 ASCI_INITDEV4:
+	; SETUP ASEXT
+	LD	A,D			; CONFIG HIGH BYTE
+	AND	%00100000		; BIT 5 IS RTS
+	CPL				; INVERT FOR ASEXT
+	LD	L,A			; MOVE TO L
+	LD	A,ASCI_DEF_ASEXT	; GET ASEXT DEFAULT
+	AND	L			; COMBINE
+	LD	L,A			; AND LEAVE IN L
+;
 	; SAVE CONFIG PERMANENTLY NOW
 	LD	(IY+4),E		; SAVE LOW WORD
 	LD	(IY+5),D		; SAVE HI WORD
 	JR	ASCI_INITGO
 ;
 ASCI_INITSAFE:
-	LD	B,$64			; CNTLA FAILSAFE VALUE
-	LD	C,$20			; CNTLB FAILSAFE VALUE
+	LD	B,ASCI_DEF_CNTLA	; CNTLA FAILSAFE VALUE
+	LD	C,ASCI_DEF_CNTLB	; CNTLB FAILSAFE VALUE
+	LD	L,ASCI_DEF_ASEXT	; ASEXT FAILSAFE VALUE
 ;
 ASCI_INITGO:
 	; IMPLEMENT CONFIGURATION
+	; B = CNTLA, C=CNTLB, L=ASEXT
+	PUSH	HL			; SAVE ASEXT
 	LD	H,B			; H := CNTLA VAL
 	LD	L,C			; L := CNTLB VAL
 	LD	B,0			; MSB OF PORT MUST BE ZERO!
@@ -532,6 +548,7 @@ ASCI_INITGO:
 	INC	C			; BUMP TO
 	INC	C			; ... CNTLB REG, B IS STILL 0
 	OUT	(C),L			; WRITE CNTLB VALUE
+	POP	HL			; RECOVER ASEXT
 	INC	C			; BUMP TO
 	INC	C			; ... STAT REG, B IS STILL 0
 #IF ((ASCIINTS) & (INTMODE > 0))
@@ -543,8 +560,11 @@ ASCI_INITGO:
 	LD	A,$0E			; BUMP TO
 	ADD	A,C			; ... ASEXT REG
 	LD	C,A			; PUT IN C FOR I/O, B IS STILL 0
-	LD	A,$66			; STATIC VALUE FOR ASEXT
-	OUT	(C),A			; WRITE ASEXT REG
+	BIT	0,C			; IS C ADDRESSING AN ODD NUMBERED PORT?
+	JR	NZ,ASCI_INITGOZ		; IF SO, THIS IS SEC SERIAL, NO CTS!
+	OUT	(C),L			; WRITE ASEXT REG
+;
+ASCI_INITGOZ:
 ;
 #IF ((ASCIINTS) & (INTMODE > 0))
 ;

Source/HBIOS/cfg_dyno.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_DYNO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_DYNO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -66,9 +66,12 @@ SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
-DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
-DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
-DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
+FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+;
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
 LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
@@ -146,7 +149,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ACFG	.EQU	SER_115200_8N1	; SIO 0A: SERIAL LINE CONFIG
@@ -154,7 +157,7 @@ SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 SIO0BCLK	.EQU	7372800		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0BCFG	.EQU	SER_115200_8N1	; SIO 0B: SERIAL LINE CONFIG
 SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
 SIO1ACLK	.EQU	7372800		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO1ACFG	.EQU	SER_115200_8N1	; SIO 1A: SERIAL LINE CONFIG
@@ -172,6 +175,7 @@ TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
 TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -183,9 +187,9 @@ FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_DYNO	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
@@ -225,7 +229,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_master.asm

@@ -12,7 +12,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -95,9 +95,12 @@ SKZDIV		.EQU	DIV_1		; UART CLK (CLK2) DIVIDER FOR Z80-512K
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 WDOGIO		.EQU	$6F		; WATCHDOG REGISTER ADR
 ;
-DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
-DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
-DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
+FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+;
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
 LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
@@ -194,7 +197,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
@@ -202,7 +205,7 @@ SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 SIO0BCLK	.EQU	CPUOSC		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
 SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
 SIO1ACLK	.EQU	CPUOSC		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO1ACFG	.EQU	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
@@ -226,6 +229,7 @@ TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|M
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
+VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -237,9 +241,9 @@ FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_NONE	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 RFCNT		.EQU	1		; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
@@ -280,7 +284,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_NONE	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDMODE		.EQU	SDMODE_NONE	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_mbc.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_MBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_MBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -60,9 +60,12 @@ SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
-DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
-DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
-DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
+FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+;
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
 LEDENABLE	.EQU	TRUE		; ENABLES STATUS LED
@@ -132,7 +135,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$B0		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
@@ -154,6 +157,7 @@ TMSMODE		.EQU	TMSMODE_MBC	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MS
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
+VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -166,9 +170,9 @@ FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_MBC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 RFCNT		.EQU	1		; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
@@ -209,7 +213,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_JUHA	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDMODE		.EQU	SDMODE_JUHA	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_mk4.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_MK4		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_MK4		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -66,9 +66,12 @@ SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
-DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
-DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
-DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
+FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+;
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
 LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
@@ -143,7 +146,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$B0		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
@@ -165,6 +168,7 @@ TMSMODE		.EQU	TMSMODE_SCG	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MS
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
+VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -176,9 +180,9 @@ FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_DIDE	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 RFCNT		.EQU	1		; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
@@ -219,7 +223,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MK4	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDMODE		.EQU	SDMODE_MK4	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_n8.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_N8		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_N8		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -68,9 +68,12 @@ SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
-DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
-DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
-DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
+FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+;
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
 LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED
@@ -145,7 +148,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$B0		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
@@ -167,6 +170,7 @@ TMSMODE		.EQU	TMSMODE_N8	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSX
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
+VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -178,9 +182,9 @@ FDENABLE	.EQU	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_N8	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 RFCNT		.EQU	1		; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
@@ -221,7 +225,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_CSIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT]
+SDMODE		.EQU	SDMODE_CSIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	N8_PPI0		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_rcz180.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_RCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -66,9 +66,18 @@ SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
+FPENABLE	.EQU	FALSE		; ENABLES FRONT PANEL SWITCHES
+FPBASE		.EQU	$00		; FRONT PANEL I/O PORT BASE ADDRESS
 DIAGENABLE	.EQU	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
+;
+FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.EQU	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+;
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
 LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
@@ -146,7 +155,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ACFG	.EQU	SER_115200_8N1	; SIO 0A: SERIAL LINE CONFIG
@@ -154,7 +163,7 @@ SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 SIO0BCLK	.EQU	7372800		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0BCFG	.EQU	SER_115200_8N1	; SIO 0B: SERIAL LINE CONFIG
 SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
 SIO1ACLK	.EQU	7372800		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO1ACFG	.EQU	SER_115200_8N1	; SIO 1A: SERIAL LINE CONFIG
@@ -172,6 +181,7 @@ TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
 TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -183,9 +193,9 @@ FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
@@ -225,7 +235,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_rcz280.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RCZ280	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_RCZ280	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z280	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -66,9 +66,12 @@ SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
-DIAGENABLE	.EQU	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
-DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
-DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
+FPLED_ENABLE	.EQU	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+;
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
 LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
@@ -156,7 +159,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
@@ -164,7 +167,7 @@ SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 SIO0BCLK	.EQU	7372800		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
 SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
 SIO1ACLK	.EQU	7372800		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO1ACFG	.EQU	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
@@ -182,6 +185,7 @@ TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
 TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -193,9 +197,9 @@ FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
@@ -235,7 +239,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_rcz80.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RCZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_RCZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -65,9 +65,12 @@ SKZDIV		.EQU	DIV_1		; UART CLK (CLK2) DIVIDER FOR Z80-512K
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 WDOGIO		.EQU	$6E		; WATCHDOG REGISTER ADR
 ;
-DIAGENABLE	.EQU	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
-DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
-DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
+FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+;
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
 LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
@@ -84,8 +87,8 @@ VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
 ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
 KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
 MKYENABLE	.EQU	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
 MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
 ;
@@ -150,7 +153,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
@@ -158,7 +161,7 @@ SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 SIO0BCLK	.EQU	CPUOSC		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
 SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
 SIO1ACLK	.EQU	CPUOSC		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO1ACFG	.EQU	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
@@ -176,6 +179,7 @@ TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
 TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -187,9 +191,9 @@ FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
@@ -229,7 +233,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_rph.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RPH		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_RPH		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	TRUE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -66,9 +66,12 @@ SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
-DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
-DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
-DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
+FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+;
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
 LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED
@@ -156,6 +159,7 @@ TMSMODE		.EQU	TMSMODE_N8	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSX
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
+VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -167,9 +171,9 @@ FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_N8	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 RFCNT		.EQU	1		; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
@@ -210,7 +214,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_CSIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDMODE		.EQU	SDMODE_CSIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	RPH_PPI0	; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_sbc.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -60,9 +60,12 @@ SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
-DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
-DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
-DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
+FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+;
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
 LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED
@@ -132,7 +135,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$B0		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
@@ -154,6 +157,7 @@ TMSMODE		.EQU	TMSMODE_SCG	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MS
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
+VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -161,14 +165,13 @@ MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
 MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
-;
 FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_DIO3	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 RFCNT		.EQU	1		; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
@@ -209,7 +212,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_JUHA	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDMODE		.EQU	SDMODE_JUHA	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_scz180.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_SCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_SCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -66,9 +66,12 @@ SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
-DIAGENABLE	.EQU	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
-DIAGPORT	.EQU	$0D		; DIAGNOSTIC PORT ADDRESS
-DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
+FPLED_ENABLE	.EQU	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.EQU	$0D		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+;
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
 LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
@@ -146,7 +149,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ACFG	.EQU	SER_115200_8N1	; SIO 0A: SERIAL LINE CONFIG
@@ -154,7 +157,7 @@ SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 SIO0BCLK	.EQU	7372800		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0BCFG	.EQU	SER_115200_8N1	; SIO 0B: SERIAL LINE CONFIG
 SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
 SIO1ACLK	.EQU	7372800		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO1ACFG	.EQU	SER_115200_8N1	; SIO 1A: SERIAL LINE CONFIG
@@ -172,6 +175,7 @@ TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
 TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -183,9 +187,9 @@ FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
@@ -225,7 +229,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_SC	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDMODE		.EQU	SDMODE_SC	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_una.asm

@@ -15,10 +15,14 @@
 ;
 #INCLUDE "../UBIOS/ubios.inc"
 ;
-;PLATFORM	.EQU	PLT_UNA		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+;PLATFORM	.EQU	PLT_UNA		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_UNA	; HARDWARE BIOS: BIOS_[WBW|UNA]
 ;
+FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+;
+DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+;
 BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
 ;
 CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
@@ -32,5 +36,3 @@ ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
 RTCIO		.EQU	$70		; RTC LATCH REGISTER ADR
 ;
 DSKYENABLE	.EQU	FALSE		; ENABLES DSKY (DO NOT COMBINE WITH PPIDE)
-
-DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING

Source/HBIOS/cfg_z80retro.asm

@@ -0,0 +1,225 @@
+;
+;==================================================================================================
+;   ROMWBW 2.X CONFIGURATION DEFAULTS FOR SIMPLE Z80 RETRO
+;==================================================================================================
+;
+; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
+; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
+; UNDER THIS DIRECTORY.
+;
+; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
+; FOR THE PLATFORM.
+;
+#DEFINE PLATFORM_NAME "Z80Retro", " [", CONFIG, "]"
+;
+#INCLUDE "hbios.inc"
+;
+PLATFORM	.EQU	PLT_Z80RETRO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
+CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+;
+BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+;
+CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.EQU	14745600	; CPU OSC FREQ IN MHZ
+INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;
+RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MPGSEL_0	.EQU	$60		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_1	.EQU	$61		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_2	.EQU	$62		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_3	.EQU	$63		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
+MPGENA		.EQU	$64		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
+;
+RTCIO		.EQU	$70		; RTC LATCH REGISTER ADR
+;
+KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+;
+CTCENABLE	.EQU	TRUE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.EQU	$40		; CTC BASE I/O ADDRESS
+CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER (too fast for RomWBW right now)
+CTCMODE		.EQU	CTCMODE_CTR	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
+CTCPRE		.EQU	256		; PRESCALE CONSTANT (1-256)
+CTCPRECH	.EQU	0		; PRESCALE CHANNEL (0-3)
+CTCTIMCH	.EQU	1		; TIMER CHANNEL (0-3)
+CTCOSC		.EQU	7372800		; CTC CLOCK FREQUENCY
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
+SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+;
+WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+;
+FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+;
+DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+;
+LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED
+LEDMODE		.EQU	LEDMODE_RTC	; LEDMODE_[STD|RTC]
+LEDPORT		.EQU	$00		; STATUS LED PORT ADDRESS
+LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+;
+DSKYENABLE	.EQU	FALSE		; ENABLES DSKY
+DSKYMODE	.EQU	DSKYMODE_V1	; DSKY VERSION: DSKYMODE_[V1|NG]
+DSKYPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF DSKY PPI
+DSKYOSC		.EQU	3000000		; OSCILLATOR FREQ FOR DSKYNG (IN HZ)
+;
+BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MKYENABLE	.EQU	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+;
+DSRTCENABLE	.EQU	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
+DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+;
+DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+;
+BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+;
+INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+;
+RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
+HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+;
+DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+;
+DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+;
+UARTENABLE	.EQU	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
+UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
+UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
+UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
+UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
+UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
+UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+;
+ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+;
+Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+;
+ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+;
+SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIO0MODE	.EQU	SIOMODE_Z80R	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.EQU	CPUOSC/2	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.EQU	CPUOSC/2	; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1MODE	.EQU	SIOMODE_Z80R	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
+SIO1ACLK	.EQU	CPUOSC/2	; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1ACFG	.EQU	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
+SIO1ACTCC	.EQU	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1BCLK	.EQU	CPUOSC/2	; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1BCFG	.EQU	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
+SIO1BCTCC	.EQU	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+;
+XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+;
+VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
+TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+;
+MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+;
+FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.EQU	FDMODE_ZETA2	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.EQU	1		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+;
+RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+;
+IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+;
+PPIDEENABLE	.EQU	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.EQU	$60		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+;
+SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.EQU	SDMODE_Z80R	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+;
+PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+;
+PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+PPPBASE		.EQU	$60		; PPP: PPI REGISTERS BASE ADDRESS
+PPPSDENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
+PPPSDTRACE	.EQU	1		; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPPCONENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
+;
+HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+;
+LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+;
+PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+PIOSBASE	.EQU	$60		; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
+;
+UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+;
+SN76489ENABLE	.EQU	FALSE		; SN76489 SOUND DRIVER
+AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
+SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+;
+DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+;
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)

Source/HBIOS/cfg_zeta.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_ZETA	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_ZETA	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; BIOS_[WBW|UNA]: HARDWARE BIOS
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -52,9 +52,12 @@ SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
-DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
-DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
-DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
+FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+;
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
 LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED
@@ -126,6 +129,7 @@ TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
 TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -137,9 +141,9 @@ FDENABLE	.EQU	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_ZETA	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	1		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
@@ -153,7 +157,7 @@ PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
 PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_zeta2.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_ZETA2	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_ZETA2	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -63,9 +63,12 @@ SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
-DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
-DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
-DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
+FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+;
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
 LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED
@@ -137,6 +140,7 @@ TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
 TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -148,9 +152,9 @@ FDENABLE	.EQU	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_ZETA2	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	1		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
@@ -164,7 +168,7 @@ PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
 PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/ctc.asm

@@ -9,7 +9,7 @@ CTC_DEFCFG	.EQU	%01010011	; CTC DEFAULT CONFIG
 CTC_CTRCFG	.EQU	%01010111	; CTC COUNTER MODE CONFIG
 CTC_TIM16CFG	.EQU	%00010111	; CTC TIMER/16 MODE CONFIG
 CTC_TIM256CFG	.EQU	%00110111	; CTC TIMER/256 MODE CONFIG
-CTC_TIMCFG	.EQU	%11010111	; CTC TIMER CHANNEL CONFIG
+;CTC_TIMCFG	.EQU	%11010111	; CTC TIMER CHANNEL CONFIG
 		;	 |||||||+-- CONTROL WORD FLAG
 		;	 ||||||+--- SOFTWARE RESET
 		;	 |||||+---- TIME CONSTANT FOLLOWS
@@ -147,18 +147,16 @@ CTCTIVT		.EQU	INT_CTC0A + CTCTIMCH
 ;==================================================================================================
 ;
 CTC_PREINIT:
+	; BLINDLY RESET THE CTC ASSUMING IT IS THERE
+	LD	A,CTC_DEFCFG
+	OUT	(CTCBASE),A
+	OUT	(CTCBASE+1),A
+	OUT	(CTCBASE+2),A
+	OUT	(CTCBASE+3),A
+;
 	CALL	CTC_DETECT		; DO WE HAVE ONE?
 	LD	(CTC_EXIST),A		; SAVE IT
 	RET	NZ			; ABORT IF NONE
-;
-	; RESET ALL CTC CHANNELS
-	LD	B,4			; 4 CHANNELS
-	LD	C,CTCBASE		; FIRST CHANNEL PORT
-CTC_PREINIT1:
-	LD	A,CTC_DEFCFG		; CTC DEFAULT CONFIG
-	OUT	(C),A			; CTC COMMAND
-	INC	C			; NEXT CHANNEL PORT
-	DJNZ	CTC_PREINIT1
 ;
 #IF (CTCTIMER & (INTMODE == 2))
 	; SETUP TIMER INTERRUPT IVT SLOT
@@ -177,12 +175,12 @@ CTC_PREINIT1:
 	; CTC CHANNEL AS A PRESCALER AND ANOTHER AS THE ACTUAL
 	; TIMER INTERRUPT.  THE PRESCALE CHANNEL OUTPUT MUST BE WIRED
 	; TO THE TIMER CHANNEL TRIGGER INPUT VIA HARDWARE.
-	LD	A,CTC_PRECFG		; PRESCALE CHANNEL CONFIGURATION
+	LD	A,CTC_PRECFG		; PRESCALE TIMER CHANNEL CFG
 	OUT	(CTC_PREIO),A		; SETUP PRESCALE CHANNEL
 	LD	A,CTC_DIVHI & $FF	; PRESCALE CHANNEL CONSTANT
 	OUT	(CTC_PREIO),A		; SET PRESCALE CONSTANT
 ;
-	LD	A,CTC_TIMCFG		; TIMER CHANNEL CONTROL WORD VALUE
+	LD	A,CTC_CTRCFG | $80	; TIMER CHANNEL + INT CFG
 	OUT	(CTC_SCLIO),A		; SETUP TIMER CHANNEL
 	LD	A,CTC_DIVLO & $FF	; TIMER CHANNEL CONSTANT
 	OUT	(CTC_SCLIO),A		; SET TIMER CONSTANT
@@ -258,32 +256,33 @@ CTC_PRTCFG1:
 	RET
 ;
 ;==================================================================================================
-; DETECT CTC BY CHECKING REGISTER CAN BE WRITTEN AND READ, AND THEN BY SETTING UP ONE CHANNEL IN 
-; TIMER MODE AND CHECKING IT IS COUNTING DOWN.
+; DETECT CTC BY PROGRAMMING THE FIRST CHANNEL TO COUNT IN TIMER
+; MODE (BASED ON CPU CLOCK).  THEN CHECK IF COUNTER IS ACTUALLY
+; RUNNING.
 ;==================================================================================================
 ;
 CTC_DETECT:
-	LD	A,CTC_TIM256CFG
-	OUT	(CTCBASE),A
-	XOR	A
-	OUT	(CTCBASE),A
-	; CTC SHOULD NOW BE RUNNING WITH TIME CONSTANT 0
-	LD	A,CTC_TIM256CFG		; RESET
-	OUT	(CTCBASE),A
-	IN	A,(CTCBASE)		; SHOULD READ 0 NOW
-	CP	0
-	JR	NZ,CTC_NO
+	LD	A,CTC_TIM16CFG		; RESET & SETUP TIMER MODE
+	OUT	(CTCBASE),A		; SEND TO CTC
 	LD	A,$FF			; TIME CONSTANT $FF
-	OUT	(CTCBASE),A
-	IN	A,(CTCBASE)		; SHOULD NOT BE 0 NOW
-	CP	0
-	JR	Z,CTC_NO
-	XOR	A
-	RET
+	OUT	(CTCBASE),A		; SEND CONSTANT & START CTR
+	NOP				; BRIEF DELAY
+	IN	A,(CTCBASE)		; READ COUNTER
+	LD	C,A			; SAVE VALUE
+	CALL	DLY8			; WAIT A BIT
+	IN	A,(CTCBASE)		; READ COUNTER AGAIN
+	PUSH	AF			; SAVE RESULT
+	LD	A,CTC_DEFCFG		; DEFAULT CHANNEL CFG
+	OUT	(CTCBASE),A		; RESTORE TO DEFAULTS
+	POP	AF			; GET RESULT BACK
+	CP	C			; COMPARE TO PREVIOUS
+	JR	Z,CTC_NO		; IF SAME, FAIL
+	XOR	A			; SIGNAL SUCCESS
+	RET				; AND DONE
 CTC_NO:
-	OR	$FF
-	RET
+	OR	$FF			; SIGNAL FAILURE
+	RET				; AND DONE
 ;
+; CTC DRIVER DATA STORAGE
 ;
-;
-CTC_EXIST	.DB	$FF	
+CTC_EXIST	.DB	$FF		; SET TO ZERO IF EXISTS

Source/HBIOS/cvdu.asm

@@ -902,5 +902,6 @@ CVDU_INIT8563:
 ;==================================================================================================
 ;
 CVDU_IDAT:
+	.DB	KBDMODE_PS2	; PS/2 8242 KEYBOARD CONTROLLER
 	.DB	CVDU_KBDST
 	.DB	CVDU_KBDDATA

Source/HBIOS/dbgmon.asm

@@ -878,6 +878,8 @@ GETLNLOP:
 	JR	Z,GETLNDONE		; YES, EXIT
 	CP	CHR_BS			; IS <BS>?
 	JR	Z,GETLNBS		; IF SO, HANDLE IT
+	CP	CHR_DEL			; IS <DEL>?
+	JR	Z,GETLNBS		; IF SO, HANDLE AS <BS>
 	CP	' '			; UNEXPECTED CONTROL CHAR?
 	JR	C,GETLNLOP		; IF SO, IGNORE IT AND GET NEXT
 	LD	B,A			; SAVE CHAR IN B FOR NOW
@@ -1854,6 +1856,7 @@ CHR_CR		.EQU	0DH
 CHR_LF		.EQU	0AH
 CHR_BS		.EQU	08H
 CHR_ESC		.EQU	1BH
+CHR_DEL		.EQU	7FH
 ;
 ;__________________________________________________________________________________________________
 ;

Source/HBIOS/fd.asm

@@ -109,7 +109,7 @@ FRC_TOSEEKWT	.EQU	-15H		; EB
 ; FD DEVICE CONFIGURATION
 ;
 FD_DEVCNT	.EQU	FDCNT		; 2 DEVICES SUPPORTED
-FD_CFGSIZ	.EQU	8		; SIZE OF CFG TBL ENTRIES
+FD_CFGSIZ	.EQU	9		; SIZE OF CFG TBL ENTRIES
 ;
 ; PER DEVICE DATA OFFSETS
 ;					; OFFSET OF...
@@ -121,25 +121,28 @@ FD_HST		.EQU	4		; HOSTS SEEK POSITION
 FD_HSTTRK	.EQU	FD_HST + 0	; HOST TRACK (WORD)
 FD_HSTSEC	.EQU	FD_HST + 2	; HOST SECTOR (BYTE)
 FD_HSTHD	.EQU	FD_HST + 3	; HOST HEAD (BYTE)
+FD_TYPE		.EQU	8		; FLOPPY DSIK TYPE (BYTE)
 ;
 FD_CFGTBL:
 	; DEVICE 0, PRIMARY MASTER
 	.DB	0			; DEVICE NUMBER
 	.DB	0			; DEVICE STATUS
-	.DB	FDMEDIA			; MEDIA TYPE
+	.DB	$FF			; CURRENT MEDIA TYPE (INIT TO NONE)
 	.DB	$FF			; CURRENT TRACK
 	.DW	0			; HOST TRACK
 	.DB	0			; HOST SECTOR
 	.DB	0			; HOST HEAD
+	.DB	FD0TYPE			; DRIVE TYPE
 #IF (FD_DEVCNT >= 2)
 	; DEVICE 1, PRIMARY SLAVE
 	.DB	1			; DRIVER DEVICE NUMBER
 	.DB	0			; DEVICE STATUS
-	.DB	FDMEDIA			; MEDIA TYPE
+	.DB	$FF			; CURRENT MEDIA TYPE (INIT TO NONE)
 	.DB	$FF			; CURRENT TRACK
 	.DW	0			; HOST TRACK
 	.DB	0			; HOST SECTOR
 	.DB	0			; HOST HEAD
+	.DB	FD1TYPE			; DRIVE TYPE
 #ENDIF
 ;
 #IF ($ - FD_CFGTBL) != (FD_DEVCNT * FD_CFGSIZ)
@@ -199,6 +202,42 @@ FSST_ENTSIZ	.EQU	$ - FSST
 FSST_COUNT	.EQU	(($ - FSST) / FSST_ENTSIZ)	; # ENTRIES IN TABLE
 #ENDIF
 ;
+; FDC DRIVE TYPE MEDIA OPTIONS
+;
+; THIS TABLE LISTS THE TYPES OF MEDIA THAT SHOULD BE ATTEMPTED
+; FOR EACH POSSIBLE DRIVE TYPE.  THE ENTRIES MATCH THE ORDER OF THE
+; FDT_ VALUES DEFINED IN STD.ASM
+;
+FD_MEDIAMAP:
+		.DW	FDMM_NONE	; NO DRIVE TYPE
+		.DW	FDMM_3DD
+		.DW	FDMM_3HD
+		.DW	FDMM_5DD
+		.DW	FDMM_5HD
+		.DW	FDMM_8
+;
+FDMM_NONE	.DB	$FF
+FDMM_3DD	.DB	FDM720, $FF
+FDMM_3HD	.DB	FDM144, FDM720, $FF
+FDMM_5DD	.DB	FDM360, $FF
+FDMM_5HD	.DB	FDM120, FDM360, $FF
+FDMM_8		.DB	FDM111, $FF
+;
+; FDC DRIVE TYPE ATTRIBUTES
+;
+; LOOKUP TABLE TO MAP THE DEVICE ATTRIBUTES BYTE RETURNED
+; BY THE FD_DEVICE FUNCTION BASED ON THE DRIVE TYPE.
+; THE ENTRIES MATCH THE ORDER OF THE
+; FDT_ VALUES DEFINED IN STD.ASM
+;
+FD_DEVATTR:
+		.DB	%11100000	; DRIVE TYPE NONE
+		.DB	%11010100	; DRIVE TYPE 3.5 DD
+		.DB	%11011000	; DRIVE TYPE 3.5 HD
+		.DB	%10110100	; DRIVE TYPE 5.25 DD
+		.DB	%10111000	; DRIVE TYPE 5.25 HD
+		.DB	%10010100	; DRIVE TYPE 8
+;
 ; FDC COMMANDS
 ;
 CFD_READ	.EQU	00000110B	; CMD,HDS/DS,C,H,R,N,EOT,GPL,DTL --> ST0,ST1,ST2,C,H,R,N
@@ -498,21 +537,11 @@ FD_DEFMED:
 FD_DEVICE:
 	LD	D,DIODEV_FD		; D := DEVICE TYPE
 	LD	E,(IY+FD_DEV)		; E := PHYSICAL DEVICE NUMBER
-#IF (FDMEDIA == FDM720)
-	LD	C,%11010100		; 3.5" DS/DD
-#ENDIF
-#IF (FDMEDIA == FDM144)
-	LD	C,%11011000		; 3.5" DS/HD
-#ENDIF
-#IF (FDMEDIA == FDM360)
-	LD	C,%10110100		; 5.25" DS/DD
-#ENDIF
-#IF (FDMEDIA == FDM120)
-	LD	C,%10111000		; 5.25" DS/HD
-#ENDIF
-#IF (FDMEDIA == FDM111)
-	LD	C,%10010100		; 8" DS/DD
-#ENDIF
+
+	LD	A,(IY+FD_TYPE)		; DRIVE TYPE
+	LD	HL,FD_DEVATTR		; DEVICE ATTR TABLE
+	CALL	ADDHLA			; POINT TO ENTRY
+	LD	C,(HL)			; GET IT
 	LD	H,FDMODE		; H := MODE
 	LD	L,FDC_MSR		; L := BASE I/O ADDRESS
 	XOR	A			; SIGNAL SUCCESS
@@ -527,9 +556,7 @@ FD_MEDIA:
 
 #IF (FDMAUTO)
 	; SETUP TO READ TRK 0, HD 0, SEC 0
-	;LD	A,C			; C STILL HAS REQUESTED DRIVE
 	LD	A,(IY+FD_DEV)		; GET DRIVE UNIT
-	;AND	0FH
 	LD	(FCD_DS),A
 	LD	A,0
 	LD	(FCD_C),A
@@ -538,53 +565,77 @@ FD_MEDIA:
 	LD	(FCD_R),A
 	LD	A,DOP_READID
 	LD	(FCD_DOP),A
+#ENDIF
 
-#IF (FDTRACE < 3)
+
+	LD	A,(IY+FD_TYPE)		; GET DRIVE TYPE VALUE
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	LD	HL,FD_MEDIAMAP		; POINT TO MEDIA MAP TABLE
+	ADD	A,A			; TABLE IS WORD SIZED
+	CALL	ADDHLA			; LOOKUP ENTRY
+	LD	A,(HL)			; DEREFERENCE
+	INC	HL
+	LD	H,(HL)
+	LD	L,A
+
+#IF (FDMAUTO)
+  #IF (FDTRACE < 3)
 	; SUPPRESS TRACING FOR MEDIA TESTS
 	LD	A,0
 	LD	(FCD_TRACE),A
-#ENDIF
-
-	LD	B,5
+  #ENDIF
 
+	LD	B,5			; 5 ATTEMPTS
 FD_MEDIARETRY:
-	; TRY PRIMARY MEDIA CHOICE FIRST
-	LD	A,FDMEDIA
-	CALL	FD_TESTMEDIA
-	JR	Z,FD_MEDIA3		; IF SUCCESS, WE ARE DONE
-
-	; TRY ALTERNATE MEDIA CHOICE
-	LD	A,FDMEDIAALT
-	CALL	FD_TESTMEDIA
-	JR	Z,FD_MEDIA3		; IF SUCCESS, WE ARE DONE
-
-	DJNZ	FD_MEDIARETRY
+	PUSH	HL			; SAVE MEDIA MAP PTR
+	CALL	FD_MEDIALOOP		; TRY IT
+	POP	HL			; RECOVER MEDIA MAP PTR
+	JR	Z,FD_MEDIA3		; CONTINUE ON SUCCESS
+	DJNZ	FD_MEDIARETRY		; LOOP TILL DONE
 
+FD_MEDIARETRY1:
 	; NO JOY, RETURN WITH E=0 (NO MEDIA)
-	;LD	HL,(FDDS_MEDIAADR)
-	;LD	(HL),0			; SET TO NO MEDIA
-	LD	(IY+FD_MEDTYP),0	; SET DRIVE = NO MEDIA
-	LD	E,0
+	LD	(IY+FD_MEDTYP),$FF	; SET MEDIA TYPE TO UNDEFINED
+	LD	E,0			; NO MEDIA FLAG
 	LD	A,ERR_NOMEDIA		; SIGNAL ERROR
 	OR	A			; SET FLAGS
 	RET
 
+FD_MEDIALOOP:
+	LD	A,(HL)			; LOAD NEXT MEDIA TYPE TO TRY
+	CP	$FF			; END OF MEDIA TYPES TO TRY?
+	JR	Z,FD_MEDIALOOP1		; NO MORE TO TRY, LOOP EXIT
+	CALL	FD_TESTMEDIA		; TRY IT
+	RET	Z			; RETURN ON SUCCESS
+	INC	HL			; NEXT MEDIA TYPE TO TRY
+	JR	FD_MEDIALOOP		; LOOP
+FD_MEDIALOOP1:
+	OR	$FF			; SIGNAL FAILURE
+	RET				; RETURN
+
 FD_TESTMEDIA:
-	;LD	HL,(FDDS_MEDIAADR)
-	;LD	(HL),A
+	;CALL	PRTHEXBYTE		; *DEBUG*
 	LD	(IY+FD_MEDTYP),A
+	PUSH	HL
 	PUSH	BC
 	CALL	FD_START
 	POP	BC
+	POP	HL
+	;CALL	PRTHEXBYTE		; *DEBUG*
 	RET
 
 FD_MEDIA3:
 
-#IF (FDTRACE < 3)
+  #IF (FDTRACE < 3)
 	; RESTORE TRACING FOR MEDIA TESTS
 	LD	A,FDTRACE
 	LD	(FCD_TRACE),A
-#ENDIF
+  #ENDIF
+#ELSE
+
+	LD	A,(HL)
+	LD	(IY+FD_MEDTYP),A
+
 #ENDIF
 
 FD_MEDIA4:
@@ -778,7 +829,7 @@ FD_DETECT1:
 ;
 FD_INITUNIT:
 	LD	(IY+FD_STAT),0		; CLEAR STATUS
-	LD	(IY+FD_MEDTYP),FDMEDIA	; SET DEFAULT MEDIA TYPE
+	LD	(IY+FD_MEDTYP),$FF	; SET UNKNOWN MEDIA TYPE
 	LD	(IY+FD_CURTRK),$FE	; SPECIAL VALUE FOR CURTRK
 	RET
 ;
@@ -1285,7 +1336,8 @@ FC_SETUPIO:
 	LD	(DE),A
 	INC	DE
 
-	LD	A,(FCD_EOT)
+	;LD	A,(FCD_EOT)
+	LD	A,(FCD_R)		; READ ONLY ONE SECTOR
 	LD	(DE),A
 	INC	DE
 
@@ -1397,15 +1449,17 @@ FC_RESETFDC:
 ; PULSE TERMCT TO TERMINATE ANY ACTIVE EXECUTION PHASE
 ;
 FC_PULSETC:
-#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC) | (FDMODE == FDMODE_DYNO) | (FDMODE == FDMODE_EPFDC) | (FDMODE == FDMODE_MBC))
-	IN	A,(FDC_TC)
-#ELSE
-	LD	A,(FST_DOR)
-	SET	0,A
-	OUT	(FDC_DOR),A
-	RES	0,A
-	OUT	(FDC_DOR),A
-#ENDIF
+; PULSING TC NO LONGER REQUIRED BECAUSE WE ONLY READ A SINGLE SECTOR
+;
+;#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC) | (FDMODE == FDMODE_DYNO) | (FDMODE == FDMODE_EPFDC) | (FDMODE == FDMODE_MBC))
+;	IN	A,(FDC_TC)
+;#ELSE
+;	LD	A,(FST_DOR)
+;	SET	0,A
+;	OUT	(FDC_DOR),A
+;	RES	0,A
+;	OUT	(FDC_DOR),A
+;#ENDIF
 	RET
 ;
 ; SET FST_DOR FOR MOTOR CONTROL ON
@@ -1694,7 +1748,7 @@ FXR_TO:		; TIMEOUT
 ;
 FXR_ABORT:	; EXECUTION ABORTED
 	HB_EI				; INTERRUPTS OK AGAIN
-	JR	FOP_RES			; GET RSEULTS, NO NEED TO PULSE TC
+	JR	FOP_RES			; GET RESULTS, NO NEED TO PULSE TC
 ;
 FXR_END:	; EXECUTION COMPLETED NORMALLY
 	CALL	FC_PULSETC		; PULSE TC TO END EXECUTION
@@ -1828,7 +1882,9 @@ FOP_EVALST1:
 
 	LD	C,FRC_ENDCYL
 	BIT	7,A
-	JR	NZ,FOP_SETFST
+	; THI IS NORMAL BECAUSE WE NOW READ ONLY A SINGLE SECTOR
+	;JR	NZ,FOP_SETFST
+	JR	NZ,FOP_EXIT
 
 	LD	C,FRC_DATAERR
 	BIT	5,A

Source/HBIOS/gdc.asm

@@ -325,5 +325,6 @@ GDC_POS		.DW 	0	; CURRENT DISPLAY POSITION
 ;==================================================================================================
 ;
 GDC_IDAT:
+	.DB	KBDMODE_PS2	; PS/2 8242 KEYBOARD CONTROLLER
 	.DB	GDC_KBDST
 	.DB	GDC_KBDDATA

Source/HBIOS/hbios.inc

@@ -109,11 +109,13 @@ BF_SYSGET_CPUINFO	.EQU	$F0	; GET CPU INFORMATION
 BF_SYSGET_MEMINFO	.EQU	$F1	; GET MEMORY CAPACTITY INFO
 BF_SYSGET_BNKINFO	.EQU	$F2	; GET BANK ASSIGNMENT INFO
 BF_SYSGET_CPUSPD	.EQU	$F3	; GET CLOCK SPEED & WAIT STATES
+BF_SYSGET_PANEL		.EQU	$F4	; GET FRONT PANEL SWITCHES VAL
 ;
 BF_SYSSET_TIMER		.EQU	$D0	; SET TIMER VALUE
 BF_SYSSET_SECS		.EQU	$D1	; SET SECONDS VALUE
 BF_SYSSET_BOOTINFO	.EQU	$E0	; SET BOOT INFORMATION
 BF_SYSSET_CPUSPD	.EQU	$F3	; SET CLOCK SPEED & WAIT STATES
+BF_SYSSET_PANEL		.EQU	$F4	; SET FRONT PANEL LEDS
 ;
 BF_SYSINT_INFO		.EQU	$00	; GET INTERRUPT SYSTEM INFO
 BF_SYSINT_GET		.EQU	$10	; GET INT VECTOR ADDRESS
@@ -137,6 +139,7 @@ PLT_DYNO	.EQU	11		; DYNO MICRO-ATX MOTHERBOARD
 PLT_RCZ280	.EQU	12		; RCBUS W/ Z280
 PLT_MBC		.EQU	13		; MULTI BOARD COMPUTER
 PLT_RPH		.EQU	14		; RHYOPHYRE GRAPHICS COMPUTER
+PLT_Z80RETRO	.EQU	15		; Z80 RETRO COMPUTER
 ;
 ; HBIOS GLOBAL ERROR RETURN VALUES
 ;
@@ -261,6 +264,15 @@ DIAG_08 .EQU 11111111B ; ON
 DIAG_09 .EQU 11111111B ; ON 
 #ENDIF
 ;
+; FRONT PANEL SWITCHES
+;
+SW_CRT		.EQU	%10000000	; CRT/SER CONSOLE
+SW_SEC		.EQU	%01000000	; SEC/PRI CONSOLE
+SW_AUTO		.EQU	%00100000	; AUTO/MENU BOOT
+SW_DISK		.EQU	%00010000	; DISK/ROM
+SW_FLOP		.EQU	%00001000	; FLOP/HD
+SW_OPT		.EQU	%00000111	; SLICE/ROM APP
+;
 ; MEDIA ID VALUES
 ;
 MID_NONE	.EQU	0
@@ -326,7 +338,7 @@ VDADEV_CVDU	.EQU	$10		; ECB COLOR VDU - MOS 8563
 VDADEV_GDC	.EQU	$20		; GRAPHICS DISPLAY CTLR - UPD7220
 VDADEV_TMS	.EQU	$30		; N8 ONBOARD VDA SUBSYSTEM - TMS 9918
 VDADEV_VGA	.EQU	$40		; ECB VGA3 - HITACHI HD6445
-;VDADEV_V9958	.EQU	$50		; V9958 VDU
+VDADEV_VRC	.EQU	$50		; VGARC
 ;
 ; SOUND DEVICE IDS
 ;

Source/HBIOS/kbd.asm

@@ -14,9 +14,10 @@
 ;
 ; DRIVER DATA OFFSETS (FROM IY)
 ;
-KBD_ST		.EQU	0	; BYTE, STATUS PORT NUM (R)
+KBD_MODE	.EQU	0	; BYTE, KEYBOARD MODE (STD OR VRC)
+KBD_ST		.EQU	1	; BYTE, STATUS PORT NUM (R)
 KBD_CMD		.EQU	KBD_ST	; BYTE, CMD PORT NUM (W)
-KBD_DAT		.EQU	1	; BYTE, DATA PORT NUM (R/W)
+KBD_DAT		.EQU	2	; BYTE, DATA PORT NUM (R/W)
 ;
 ; TIMING CONSTANTS
 ;
@@ -69,17 +70,33 @@ KBD_INIT:
 	LD	(KBD_REPEAT),A		; SAVE IT
 	LD	A,KBD_DEFSTATE		; GET DEFAULT STATE
 	LD	(KBD_STATE),A		; SAVE IT
-
+;
+	LD	A,(IY+KBD_MODE)		; GET KBD MODE BYTE
+	CP	KBDMODE_VRC		; VRC?
+	JR	Z,KBD_INIT1		; IF SO, MUST ASSUME PRESENT
+;
 	LD	A,$AA			; CONTROLLER SELF TEST
 	CALL	KBD_PUTCMD		; SEND IT
 	CALL	KBD_GETDATA		; CONTROLLER SHOULD RESPOND WITH $55 (ACK)
-
+;
 	CP	$55			; IS IT THERE?
 	JR	Z,KBD_INIT1		; IF SO, CONTINUE
 	PRTS(" NOT PRESENT$")		; DIAGNOSE PROBLEM
 	RET				; BAIL OUT
-
+;
 KBD_INIT1:
+	PRTS(" MODE=$")			; TAG
+	LD	A,(IY+KBD_MODE)		; GET MODE VALUE
+	LD	DE,KBD_STR_MODEPS2
+	CP	KBDMODE_PS2
+	JR	Z,KBD_INIT2
+	LD	DE,KBD_STR_MODEVRC
+	CP	KBDMODE_VRC
+	JR	Z,KBD_INIT2
+	LD	DE,KBD_STR_MODEUNK
+KBD_INIT2:
+	CALL	WRITESTR
+;
 	LD	A,$60			; SET COMMAND REGISTER
 	CALL	KBD_PUTCMD		; SEND IT
 ;	LD	A,$60			; XLAT ENABLED, MOUSE DISABLED, NO INTS
@@ -88,11 +105,6 @@ KBD_INIT1:
 	
 	CALL	KBD_GETDATA		; GOBBLE UP $AA FROM POWER UP, AS NEEDED
 	
-;	LD	A,$AE			; COMMAND = ENABLE KEYBOARD
-;	CALL	KBD_PUTCMD		; SEND IT
-;	LD	A,$A7			; COMMAND = DISABLE MOUSE
-;	CALL	KBD_PUTCMD		; SEND IT
-	
 	CALL 	KBD_RESET		; RESET THE KEYBOARD
 	CALL	KBD_SETLEDS		; UPDATE LEDS BASED ON CURRENT TOGGLE STATE BITS
 	CALL	KBD_SETRPT		; UPDATE REPEAT RATE BASED ON CURRENT SETTING
@@ -177,6 +189,9 @@ KBD_PUTCMD:
 ; PUT A CMD BYTE FROM A TO THE KEYBOARD INTERFACE WITH TIMEOUT
 ;
 	LD	E,A			; SAVE INCOMING VALUE IN E
+	LD	A,(IY+KBD_MODE)		; GET MODE BYTE
+	CP	KBDMODE_VRC		; VGARC KEYBOARD?
+	JR	Z,KBD_PUTCMD2		; BAIL OUT
 	LD	B,KBD_WAITTO		; SETUP TO LOOP
 KBD_PUTCMD0:
 	CALL	KBD_OST			; GET OUTPUT REGISTER STATUS
@@ -194,6 +209,7 @@ KBD_PUTCMD1:
 #ENDIF
 	LD	C,(IY+KBD_CMD)		; COMMAND PORT
 	OUT	(C),A			; WRITE IT
+KBD_PUTCMD2:
 	XOR	A			; SIGNAL SUCCESS
 	RET
 ;
@@ -203,6 +219,9 @@ KBD_PUTDATA:
 ; PUT A DATA BYTE FROM A TO THE KEYBOARD INTERFACE WITH TIMEOUT
 ;
 	LD	E,A			; SAVE INCOMING VALUE IN E
+	LD	A,(IY+KBD_MODE)		; GET MODE BYTE
+	CP	KBDMODE_VRC		; VGARC KEYBOARD?
+	JR	Z,KBD_PUTDATA2		; BAIL OUT
 	LD	B,KBD_WAITTO		; SETUP TO LOOP
 KBD_PUTDATA0:
 	CALL	KBD_OST			; GET OUTPUT REGISTER STATUS
@@ -219,6 +238,7 @@ KBD_PUTDATA1:
 #ENDIF
 	LD	C,(IY+KBD_DAT)		; DATA PORT
 	OUT	(C),A			; WRITE IT
+KBD_PUTDATA2:
 	XOR	A			; SIGNAL SUCCESS
 	RET
 ;
@@ -681,11 +701,21 @@ KBD_DECNEW:	; START NEW KEYPRESS (CLEAR ALL STATUS BITS)
 	LD	(KBD_STATUS),A		; CLEAR STATUS
 	JP	KBD_DEC1		; RESTART THE ENGINE
 ;
+; DRIVER DATA
+;
+KBD_STR_MODEPS2		.TEXT	"PS2$"
+KBD_STR_MODEVRC		.TEXT	"VRC$"
+KBD_STR_MODEUNK		.TEXT	"???$"
+;
+;
+;
 #IF (KBDKBLOUT == KBD_US)
+;
 ;__________________________________________________________________________________________________
 ;
 ; MAPPING TABLES US/ENGLISH
 ;__________________________________________________________________________________________________
+;
 KBD_MAPSTD:	; SCANCODE IS INDEX INTO TABLE TO RESULTANT LOOKUP KEYCODE
 	.DB	$FF,$E8,$FF,$E4,$E2,$E0,$E1,$EB,$FF,$E9,$E7,$E5,$E3,$09,'`',$FF
 	.DB	$FF,$B4,$B0,$FF,$B2,'q','1',$FF,$FF,$FF,'z','s','a','w','2',$FF
@@ -722,7 +752,9 @@ KBD_MAPNUMPAD:	; KEYCODE TRANSLATION FROM NUMPAD RANGE TO STD ASCII/KEYCODES
 	.DB	$F3,$F7,$F5,$F8,$FF,$F9,$F2,$F6,$F4,$F0,$F1,$2F,$2A,$2D,$2B,$0D
 	.DB	$31,$32,$33,$34,$35,$36,$37,$38,$39,$30,$2E,$2F,$2A,$2D,$2B,$0D
 #ENDIF
+;
 #IF (KBDKBLOUT == KBD_DE)
+;
 ;__________________________________________________________________________________________________
 ;
 ; MAPPING TABLES GERMAN

Source/HBIOS/romldr.asm

@@ -41,6 +41,7 @@ bel	.equ	7	; ASCII bell
 bs	.equ	8	; ASCII backspace
 lf	.equ	10	; ASCII linefeed
 cr	.equ	13	; ASCII carriage return
+del	.equ	127	; ASCII del/rubout
 ;
 cmdbuf	.equ	$80	; cmd buf is in second half of page zero
 cmdmax	.equ	60	; max cmd len (arbitrary), must be < bufsiz
@@ -179,6 +180,30 @@ start1:
 	call	pstr			; do it
 	call	clrbuf			; zero fill the cmd buffer
 ;
+#if (BIOS == BIOS_WBW)
+;
+	ld	b,BF_SYSGET		; HBIOS SysGet
+	ld	c,BF_SYSGET_PANEL	; ... Panel swiches value
+	rst	08			; do it
+	jr	nz,nofp			; no switches, skip over
+	ld	a,l			; put value in A
+	ld	(switches),a		; save it
+;
+	call	nl			; formatting
+	ld	hl,str_switches		; tag
+	call	pstr			; display
+	ld	a,(switches)		; get switches value
+	call	prthexbyte		; display
+;
+	ld	a,(switches)		; get switches value
+	and	SW_AUTO			; auto boot?
+	call	nz,runfp		; process front panel
+;
+nofp:
+	; fall thru
+;
+#endif
+;
 #if (BOOT_TIMEOUT != -1)
 	; Initialize auto command timeout downcounter
 	or	$FF			; auto cmd active value
@@ -211,12 +236,12 @@ prompt:
 	ld	hl,msg_sel		; boot select msg
 	call	DSKY_SHOW		; show on DSKY
 
- #IF (DSKYMODE == DSKYMODE_NG)
+ #if (DSKYMODE == DSKYMODE_NG)
 	call 	DSKY_PUTLED
 	.db 	$3f,$3f,$3f,$3f,$00,$00,$00,$00
 	call 	DSKY_BEEP
 	call 	DSKY_L2ON
- #ENDIF
+ #endif
 
 #endif
 ;
@@ -365,6 +390,125 @@ runcmd2:
 	ld	(bootslice),a		; save boot slice
 	jp	diskboot		; boot the disk unit/slice
 ;
+#if (BIOS == BIOS_WBW)
+;
+;=======================================================================
+; Process Front Panel switches
+;=======================================================================
+;
+runfp:
+	ld	a,(switches)		; get switches value
+	and	SW_DISK			; disk boot?
+	jr	nz,fp_diskboot		; handle disk boot
+;
+fp_romboot:
+	; Handle FP ROM boot
+	ld	a,(switches)		; get switches value
+	and	SW_OPT			; isolate options bits
+	ld	hl,fpapps		; rom apps cmd char list
+	call	addhla			; point to the right one
+	ld	a,(hl)			; get it
+;
+	; Attempt ROM application launch
+	ld	ix,(ra_tbl_loc)		; point to start of ROM app tbl
+	ld	c,a			; save command in C
+fp_romboot1:
+	ld	a,(ix+ra_conkey)	; get match char
+	and	~$80			; clear "hidden entry" bit
+	cp	c			; compare
+	jp	z,romload		; if match, load it
+	ld	de,ra_entsiz		; table entry size
+	add	ix,de			; bump IX to next entry
+	ld	a,(ix)			; check for end
+	or	(ix+1)			; ... of table
+	jr	nz,fp_romboot1		; loop till done
+	ret				; no match, return
+;
+fpapps	.db	"MBFPCZNU"
+;
+fp_diskboot:
+	; get count of disk units
+	ld	b,BF_SYSGET		; HBIOS Get function
+	ld	c,BF_SYSGET_DIOCNT	; HBIOS DIO Count sub fn
+	rst	08			; call HBIOS
+	ld	a,e			; count to A
+	ld	(diskcnt),a		; save it
+	or	a			; set flags
+	ret	z			; bort if no disk units
+	ld	a,(switches)		; get switches value
+	and	SW_FLOP			; floppy switch bit
+	jr	nz,fp_flopboot		; handle auto flop boot
+	; fall thru for auto hd boot
+;
+fp_hdboot:
+	; Find the first hd with media and boot to that unit using
+	; the slice specified by the FP switches.
+	ld	a,(diskcnt)		; get disk count
+	ld	b,a			; init loop counter
+	ld	c,0			; init disk index
+fp_hdboot1:
+	push	bc			; save loop control
+	ld	b,BF_DIODEVICE		; HBIOS Disk Device func
+	rst	08			; unit in C, do it
+	pop	bc			; restore loop control
+	ld	a,d			; device type to A
+	cp	DIODEV_IDE		; type IDE or greater is HD
+	jr	c,fp_hdboot2		; if not, continue loop
+	push	bc			; save loop control
+	ld	b,BF_DIOMEDIA		; HBIOS Sense Media
+	ld	e,1			; perform media discovery
+	rst	08			; do it
+	pop	bc			; restore loop control
+	jr	z,fp_hdboot3		; if has media, go boot it
+fp_hdboot2:
+	inc	c			; else next disk
+	djnz	fp_hdboot1		; loop thru all disks
+	ret				; nothing works, abort
+;
+fp_hdboot3:
+	ld	a,c			; disk unit to A
+	ld	(bootunit),a		; save it
+	ld	a,(switches)		; get switches value
+	and	SW_OPT			; isolate slice value
+	ld	(bootslice),a		; save it
+	jp	diskboot		; do it
+;
+fp_flopboot:
+	; Find the nth floppy drive and boot to that unit.  The
+	; floppy number is based on the option switches.
+	ld	a,(diskcnt)		; get disk count
+	ld	b,a			; init loop counter
+	ld	c,0			; init disk index
+	ld	a,(switches)		; get switches value
+	and	SW_OPT			; isolate option bits
+	ld	e,a			; floppy unit down counter
+	inc	e			; pre-increment for ZF check
+fp_flopboot1:
+	push	bc			; save loop control
+	push	de			; save floppy down ctr
+	ld	b,BF_DIODEVICE		; HBIOS Disk Device func
+	rst	08			; unit in C, do it
+	ld	a,d			; device type to A
+	pop	de			; restore loop control
+	pop	bc			; restore floppy down ctr
+	cp	DIODEV_FD		; type FD?
+	jr	nz,fp_flopboot3		; if not floppy, skip
+	dec	e			; decrement down ctr
+	jr	z,fp_flopboot2		; if ctr expired, boot this unit
+fp_flopboot3:
+	inc	c			; else next disk
+	djnz	fp_flopboot1		; loop thru all disks
+	ret				; nothing works, abort
+;
+fp_flopboot2:
+	ld	a,c			; disk unit to A
+	ld	(bootunit),a		; save it
+	xor	a		;	; zero accum
+	ld	(bootslice),a		; floppy boot slice is always 0
+	jp	diskboot		; do it
+;
+#endif
+;
 ;=======================================================================
 ; Process a DSKY command from key in A
 ;=======================================================================
@@ -1208,20 +1352,24 @@ diskread:
 ;
 clrled:
 #if (BIOS == BIOS_WBW)
-  #if (DIAGENABLE)
-	xor	a		; zero accum
-	out	(DIAGPORT),a	; clear diag leds
+  #if (FPLED_ENABLE)
+	;xor	a			; zero accum
+	;out	(FPLED_IO),a		; clear diag leds
+	ld	b,BF_SYSSET		; HBIOS SysGet
+	ld	c,BF_SYSSET_PANEL	; ... Panel swiches value
+	ld	l,$00			; all LEDs off
+	rst	08			; do it
   #endif
   #if (LEDENABLE)
     #if (LEDMODE == LEDMODE_STD)
-	ld	a,$FF		; led is inverted
-	out	(LEDPORT),a	; clear led
+	ld	a,$FF			; led is inverted
+	out	(LEDPORT),a		; clear led
     #endif
     #if (LEDMODE == LEDMODE_RTC)
 	; Bits 0 and 1 of the RTC latch are for the LEDs.
 	ld	a,(HB_RTCVAL)
 	and	~%00000011
-	out	(RTCIO),a	; clear led
+	out	(RTCIO),a		; clear led
 	ld	(HB_RTCVAL),a
     #endif
   #endif
@@ -1281,6 +1429,8 @@ rdln_nxt:
 	call	cin			; get a character
 	cp	bs			; backspace?
 	jr	z,rdln_bs		; handle it if so
+	cp	del			; del/rubout?
+	jr	z,rdln_bs		; handle as backspace
 	cp	cr			; return?
 	jr	z,rdln_cr		; handle it if so
 ;
@@ -2165,6 +2315,7 @@ str_upd		.db	"XModem Flash Updater",0
 str_user	.db	"User App",0
 str_egg		.db	"",0
 str_net		.db	"Network Boot",0
+str_switches	.db	"FP Switches = 0x",0
 newcon		.db	0
 newspeed	.db	0
 ;
@@ -2191,6 +2342,8 @@ ra_tbl_loc	.dw	0		; points to active ra_tbl
 bootunit	.db	0		; boot disk unit
 bootslice	.db	0		; boot disk slice
 loadcnt		.db	0		; num disk sectors to load
+switches	.db	0		; front panel switches
+diskcnt		.db	0		; disk unit count value
 ;
 ;=======================================================================
 ; Pad remainder of ROM Loader

Source/HBIOS/sd.asm

@@ -282,6 +282,35 @@ SD_INVCS	.EQU	FALSE		; INVERT CS
 #ENDIF
 ;
 ;
+#IF (SDMODE == SDMODE_PIO)		; Z80 PIO
+;
+;	These mappings work for the RCbus Gluino card with an Arduino
+;	shield attached and are the ones also used in other bitbang setups
+;	directly attached to a PIO. It also works on a straight digital I/O
+;	port as the config writes will disappear into oblivion harmlessly
+;	
+;	The Gluino mapping (ie Arduino pin mapping equivalent) is thus
+;	D10 SS, D11 CIPO, D12 COPI, D13 SCL.
+;
+;	For speed reasons MISO/MOSI are mapped to the top and bottom bits.
+;	RomWBW doesn't yet use this fact but the optimized Fuzix routines do.
+;
+SD_DEVMAX	.EQU	1		; NUMBER OF PHYSICAL UNITS (SOCKETS)
+SD_IOBASE	.EQU	$69		; IO BASE ADDRESS FOR SD INTERFACE
+SD_OPRREG	.EQU	SD_IOBASE	; OUTPUT PORT (OUTPUT: CS, CLK, DIN)
+SD_OPRDEF	.EQU	%11111111	; OUTPUT PORT DEFAULT STATE
+SD_INPREG	.EQU	SD_IOBASE	; INPUT REGISTER
+SD_CS0		.EQU	%00001000	; SELECT
+SD_CLK		.EQU	%00010000	; CLOCK
+SD_DI		.EQU	%00000001	; DATA IN (CARD <- CPU) MOSI
+SD_DO		.EQU	%10000000	; DATA OUT (CARD -> CPU) MISO
+SD_CINIT	.EQU	TRUE		; INITIALIZE OUTPUT PORT
+SD_DDR		.EQU	$6B		; DATA DIRECTION REGISTER
+SD_DDRVAL	.EQU	%11100110	; DATA DIRECTION REGISTER VALUE
+SD_INVCS	.EQU	TRUE		; INVERT CS
+#ENDIF
+;
+;
 #IF (SDMODE == SDMODE_USR)		; USER DEFINED HARDWARE CONFIGURATION
 ;
 ; THIS MODE IS INTENDED TO ALLOW A USER TO EASILY CONFIGURE A CUSTOM
@@ -304,6 +333,27 @@ SD_DDRVAL	.EQU	%00001101	; DATA DIRECTION REGISTER VALUE
 SD_INVCS	.EQU	FALSE		; INVERT CS
 #ENDIF
 ;
+#IF (SDMODE == SDMODE_Z80R)		; Z80 Retro
+;
+;	SPLIT OVER TWO REGISTERS TO DRIVE CLK. THE CS LINE IS ON THE GPIO
+;	WHICH IS THE SAME LATCHES THAT CONTROL MMU ON/OFF, SO DON;T GLITCH
+;	THEM WHEN UPDATING!
+;
+SD_DEVMAX	.EQU	1		; NUMBER OF PHYSICAL UNITS (SOCKETS)
+SD_OPRDEF	.EQU	%00000001	; OUTPUT PORT DEFAULT STATE
+SD_OPRMSK	.EQU	%00000101	; OUTPUT PORT MASK
+SD_OPRREG	.EQU	$64		; CS VIA GPIO
+SD_IOBASE	.EQU	$68		; 68/69 FOR OUTPUT
+SD_IOREG	.EQU	SD_IOBASE	; INPUT REGISTER
+SD_IOCLK	.EQU	SD_IOBASE+1	; CLOCK IS OFF A0
+SD_GPIO		.EQU	$64		; MISO IS ON THE GPIO
+SD_CS0		.EQU	%00000100	; SELECT
+SD_DI		.EQU	%00000001	; DATA IN (CARD <- CPU) MOSI
+SD_DO		.EQU	%00000001	; DATA OUT (CARD -> CPU) MISO
+SD_CINIT	.EQU	FALSE		; INITIALIZE OUTPUT PORT
+SD_INVCS	.EQU	FALSE		; INVERT CS
+#ENDIF
+;
 #IF (SD_DEVCNT > SD_DEVMAX)
 	.ECHO	"*** ERROR: SDCNT EXCEEDS MAXIMUM SUPPORTED BY INTERFACE!!!\n"
 	!!!	; FORCE AN ASSEMBLY ERROR
@@ -510,6 +560,22 @@ SD_INIT:
 	CALL	PRTHEXBYTE
 #ENDIF
 ;
+#IF (SDMODE == SDMODE_PIO)
+	PRTS(" MODE=PIO$")
+	PRTS(" IO=0x$")
+	LD	A,SD_IOBASE
+	CALL	PRTHEXBYTE
+#ENDIF
+;
+#IF (SDMODE == SDMODE_Z80R)
+	PRTS(" MODE=Z80R$")
+	PRTS(" IO=0x$")
+	LD	A,SD_IOBASE
+	CALL	PRTHEXBYTE
+	LD	A,SD_OPRDEF
+	LD	(SD_OPRVAL),A
+#ENDIF
+;
 #IF (SDMODE == SDMODE_USR)
 	PRTS(" MODE=USER$")
 	PRTS(" IO=0x$")
@@ -1736,6 +1802,17 @@ SD_SETUP:
 	OUT	(SD_OPRREG),A		; OPRREG == SIO_MCR
 #ENDIF
 ;
+#IF (SDMODE == SDMODE_PIO)
+	LD	A,SD_OPRDEF		; All output bits high
+	OUT	(SD_OPRREG),A
+	LD	A,$CF			; Port B mode 3
+	OUT	(SD_DDR),A
+	LD	A,SD_DDRVAL		; Set the direction bits
+	OUT	(SD_DDR),A
+	LD	A,$07			; No interrupts
+	OUT	(SD_DDR),A
+#ENDIF
+;
 #IF (SDMODE == SDMODE_USR)
   #IF (SD_CINIT == TRUE)
 	LD	A,(SD_OPRMSK)		; GET OUTPUT PORT MASK
@@ -1863,7 +1940,7 @@ SD_DESELECT:
 	AND	~SD_CS0
 #ENDIF
 ; ADJUST BIT(S) FOR INTERFACES USING INVERTED CS BITS
-#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC))
+#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_PIO) | (SDMODE == SDMODE_Z80R))
   #IF ((SDMODE == SDMODE_SC) & (SD_DEVCNT > 1))
 	XOR	SD_CS0 | SD_CS1
   #ELSE
@@ -1910,9 +1987,48 @@ SD_PUT:
 	SET	4,A			; SET TRANSMIT ENABLE
 	OUT0	(SD_CNTR),A
   #ELSE
-    #IF (SDMODE == SDMODE_UART)
+
+    #IF (SDMODE == SDMODE_Z80R)
+	; USE C - THE CALLING CODE FOR COMMAND SEND FAILS TO SAVE HL/DE
+	; WHILST THE OTHER PATHS DO ?
+        LD	C,A
+	RL	C
+	RLA
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	RL	C
+	RLA
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	RL	C
+	RLA
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	RL	C
+	RLA
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	RL	C
+	RLA
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	RL	C
+	RLA
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	RL	C
+	RLA
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	RL	C
+	RLA
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+    #ELSE
+
+      #IF (SDMODE == SDMODE_UART)
 	XOR	$FF			; DI IS INVERTED ON UART
-    #ENDIF
+      #ENDIF
 	LD	C,A			; C=BYTE TO SEND
 	LD	B,8			; SEND 8 BITS (LOOP 8 TIMES)
 	LD	A,(SD_OPRVAL)		; LOAD CURRENT OPR VALUE
@@ -1928,6 +2044,7 @@ SD_PUT1:
 	DJNZ	SD_PUT1			; REPEAT FOR ALL 8 BITS
 	LD	A,(SD_OPRVAL)		; LOAD CURRENT OPR VALUE
 	OUT	(SD_OPRREG),A		; LEAVE WITH CLOCK LOW
+    #ENDIF
   #ENDIF
 #ENDIF
 	RET				; DONE
@@ -1950,34 +2067,83 @@ SD_GET:
 	CALL	MIRROR			; MSB<-->LSB MIRROR BITS
 	LD	A,C			; KEEP RESULT
   #ELSE
+    #IF (SDMODE == SDMODE_Z80R)
+	; MUST PRESERVE HL,DE
+	PUSH	DE
+	LD	A,1
+	LD	C,SD_GPIO
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	IN	B,(C)
+	RR	B
+	RL	E
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	IN	B,(C)
+	RR	B
+	RL	E
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	IN	B,(C)
+	RR	B
+	RL	E
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	IN	B,(C)
+	RR	B
+	RL	E
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	IN	B,(C)
+	RR	B
+	RL	E
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	IN	B,(C)
+	RR	B
+	RL	E
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	IN	B,(C)
+	RR	B
+	RL	E
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	IN	B,(C)
+	RR	B
+	RL	E
+	LD	A,E
+	POP	DE
+    #ELSE
 	LD	B,8			; RECEIVE 8 BITS (LOOP 8 TIMES)
 	LD	A,(SD_OPRVAL)		; LOAD CURRENT OPR VALUE
 SD_GET1:
 	XOR	SD_CLK			; TOGGLE CLOCK
 	OUT	(SD_OPRREG),A		; UPDATE CLOCK
 	IN	A,(SD_INPREG)		; READ THE DATA WHILE CLOCK IS ACTIVE
-    #IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_PPI))
+      #IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_PIO))
 	RLA				; ROTATE INP:7 INTO CF
-    #ENDIF
-    #IF (SDMODE == SDMODE_N8)
+      #ENDIF
+      #IF (SDMODE == SDMODE_N8)
 	RLA				; ROTATE INP:6 INTO CF
 	RLA				; "
-    #ENDIF
-    #IF (SDMODE == SDMODE_UART)
+      #ENDIF
+      #IF (SDMODE == SDMODE_UART)
 	RLA				; ROTATE INP:5 INTO CF
 	RLA				; "
 	RLA				; "
-    #ENDIF
-    #IF (SDMODE == SDMODE_DSD)
+      #ENDIF
+      #IF (SDMODE == SDMODE_DSD)
 	RRA				; ROTATE INP:0 INTO CF
-    #ENDIF
+      #ENDIF
 	RL	C			; ROTATE CF INTO C:0
 	LD	A,(SD_OPRVAL)		; BACK TO INITIAL VALUES (TOGGLE CLOCK)
 	OUT	(SD_OPRREG),A		; DO IT
 	DJNZ	SD_GET1			; REPEAT FOR ALL 8 BITS
 	LD	A,C			; GET BYTE RECEIVED INTO A
-    #IF (SDMODE == SDMODE_UART)
+      #IF (SDMODE == SDMODE_UART)
 	XOR	$FF			; DO IS INVERTED ON UART
+      #ENDIF
     #ENDIF
   #ENDIF
 #ENDIF

Source/HBIOS/sio.asm

@@ -60,13 +60,20 @@ SIO0B_CMD	.EQU	SIO0BASE + $03
 SIO0B_DAT	.EQU	SIO0BASE + $01
 #ENDIF
 ;
-#IF (SIO0MODE == SIOMODE_ZP)		
+#IF (SIO0MODE == SIOMODE_ZP)
 SIO0A_CMD	.EQU	SIO0BASE + $06
 SIO0A_DAT	.EQU	SIO0BASE + $04 
 SIO0B_CMD	.EQU	SIO0BASE + $07
 SIO0B_DAT	.EQU	SIO0BASE + $05
 #ENDIF
 ;
+#IF (SIO0MODE == SIOMODE_Z80R)
+SIO0A_CMD	.EQU	SIO0BASE + $03
+SIO0A_DAT	.EQU	SIO0BASE + $01
+SIO0B_CMD	.EQU	SIO0BASE + $02
+SIO0B_DAT	.EQU	SIO0BASE + $00
+#ENDIF
+;
 #IF (SIOCNT >= 2)
 ;
   #IF (SIO1MODE == SIOMODE_STD)
@@ -97,6 +104,13 @@ SIO1B_CMD	.EQU	SIO1BASE + $07
 SIO1B_DAT	.EQU	SIO1BASE + $05
   #ENDIF
 ;
+#IF (SIO1MODE == SIOMODE_Z80R)
+SIO1A_CMD	.EQU	SIO0BASE + $03
+SIO1A_DAT	.EQU	SIO0BASE + $01 
+SIO1B_CMD	.EQU	SIO0BASE + $02
+SIO1B_DAT	.EQU	SIO0BASE + $00
+#ENDIF
+;
 #ENDIF
 ;
 SIO_PREINIT:
@@ -785,10 +799,14 @@ SIO_INITBROK:
 ;
 ; SET RECEIVE DATA BITS WR3 
 ;	
+	LD	A,D			; HI WORD OF CONFIG
+	AND	%00100000		; BIT 5 IS AUTO-CTS
+	LD	H,A			; SAVE IN H
 	LD	A,L			; DATA BITS
 	AND	$C0			; CLEAR OTHER BITS
-	OR	$21			; CTS/DCD AUTO, RX ENABLE
-;	
+	OR	$01			; RX ENABLE
+	OR	H			; COMBINE WITH AUTO-CTS
+;
 	LD	(SIO_WR3),A
 ;
 ; SAVE CONFIG PERMANENTLY NOW

Source/HBIOS/std.asm

@@ -1,5 +1,5 @@
 ; The purpose of this file is to define generic symbols and to include
-; the requested build configuraton file to bring in platform specifics.
+; the requested build configuration file to bring in platform specifics.
 
 ; There are several hardware platforms supported by SBC.
 ; 1.  SBC	Z80 SBC (v1 or v2) w/ ECB interface
@@ -16,6 +16,7 @@
 ; 12. RCZ280	Z280 CPU on RCBUS or ZZ80MB
 ; 13. MBC	Andrew Lynch's Multi Board Computer
 ; 14. RPH	Andrew Lynch's RHYOPHYRE Graphics Computer
+; 15. Z80RETRO	Peter Wilson's Z80-Retro Computer
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;
@@ -91,6 +92,15 @@ FDM360		.EQU	2		; 5.25" FLOPPY, 360KB, 2 SIDES, 40 TRKS, 9 SECTORS
 FDM120		.EQU	3		; 5.25" FLOPPY, 1.2MB, 2 SIDES, 80 TRKS, 15 SECTORS
 FDM111		.EQU	4		; 8" FLOPPY, 1.11MB, 2 SIDES, 74 TRKS, 15 SECTORS
 ;
+; FLOPPY DISK TYPE
+;
+FDT_NONE	.EQU	0		; NONE
+FDT_3DD		.EQU	1		; 3.5" FLOPPY, DOUBLE DENSITY
+FDT_3HD		.EQU	2		; 3.5" FLOPPY, HIGH DENSITY
+FDT_5DD		.EQU	3		; 5.25" FLOPPY, DOUBLE DENSITY
+FDT_5HD		.EQU	4		; 5.25" FLOPPY, HIGH DNSITY
+FDT_8		.EQU	5		; 8" FLOPPY, DOUBLE DENSITY
+;
 ; ZILOG CTC MODE SELECTIONS
 ;
 CTCMODE_NONE	.EQU	0		; NO CTC
@@ -116,6 +126,7 @@ SIOMODE_STD	.EQU	1		; STD SIO REG CFG (EZZ80, KIO)
 SIOMODE_RC	.EQU	2		; RCBUS SIO MODULE (SPENCER OWEN)
 SIOMODE_SMB	.EQU	3		; RCBUS SIO MODULE (SCOTT BAKER)
 SIOMODE_ZP	.EQU	4		; ECB-ZILOG PERIPHERALS BOARD
+SIOMODE_Z80R	.EQU	5		; SIO A/B SWAPPED
 ;
 ; TYPE OF CONSOLE BELL TO USE
 ;
@@ -182,6 +193,8 @@ SDMODE_MK4	.EQU	7		; MARK IV
 SDMODE_SC	.EQU	8		; SC (Steve Cousins)
 SDMODE_MT	.EQU	9		; MT (Shift register SPI WIZNET for RCBUS)
 SDMODE_USR	.EQU	10		; USER DEFINED (in sd.asm) (NOT COMPLETE)
+SDMODE_PIO	.EQU	11		; Z80 PIO bitbang
+SDMODE_Z80R	.EQU	12		; Z80 Retro
 ;
 ; AY SOUND CHIP MODE SELECTIONS
 ;
@@ -244,6 +257,12 @@ DMAMODE_Z280	.EQU	3		; Z280 INTEGRATED DMA
 DMAMODE_RC	.EQU	4		; RCBUS Z80 DMA
 DMAMODE_MBC	.EQU	5		; MBC
 ;
+; KEYBOARD MODE SELECTIONS
+;
+KBDMODE_NONE	.EQU	0
+KBDMODE_PS2	.EQU	1		; PS/2 KEYBOARD CONTROLLER
+KBDMODE_VRC	.EQU	2		; VGARC KEYBOARD CONTROLLER
+;
 ; SERIAL DEVICE CONFIGURATION CONSTANTS
 ;
 SER_DATA5	.EQU	0 << 0

Source/HBIOS/tms.asm

@@ -942,10 +942,10 @@ TMS_IDAT:
 	.DB	TMS_PPIX        ; PPI CONTROL PORT
 #ENDIF
 #IF ((TMSMODE == TMSMODE_MSXKBD) | (TMSMODE == TMSMODE_MBC))
+	.DB	KBDMODE_PS2	; PS/2 8242 KEYBOARD CONTROLLER
 	.DB	TMS_KBDST	; 8242 CMD/STATUS PORT
 	.DB	TMS_KBDDATA	; 8242 DATA PORT
 	.DB	0		; FILLER
-	.DB	0		; FILER
 #ENDIF
 ;
 	.DB	TMS_DATREG

Source/HBIOS/uart.asm

@@ -739,7 +739,7 @@ UART_DETECT2:
 	LD	A,C			; RETURN RESULT IN A
 	RET
 ;
-; DETERMINE TEH UART CHIP VARIANT AND RETURN IN A
+; DETERMINE THE UART CHIP VARIANT AND RETURN IN A
 ;
 UART_CHIP:
 ;

Source/HBIOS/unlzsa2s.asm

@@ -1,3 +1,4 @@
+;  WARNING: This code does not seem to be working on Z280.  WBW - 5/3/2023
 ;
 ;  Size-optimized LZSA2 decompressor by spke & uniabis (134 bytes)
 ;
@@ -59,8 +60,8 @@
 ;  3. This notice may not be removed or altered from any source distribution.
 ;
 
-;	#DEFINE	BACKWARD_DECOMPRESS						; uncomment for data compressed with option -b (+5 bytes, -3% speed)
-;	#DEFINE	AVOID_SELFMODIFYING_CODE					; uncomment to disallow self-modifying code (-1 byte, -4% speed)
+;	#DEFINE	BACKWARD_DECOMPRESS		; uncomment for data compressed with option -b (+5 bytes, -3% speed)
+;	#DEFINE	AVOID_SELFMODIFYING_CODE	; uncomment to disallow self-modifying code (-1 byte, -4% speed)
 
 	#IFNDEF	BACKWARD_DECOMPRESS
 
@@ -78,7 +79,7 @@
 
 		#DEFINE ADD_OFFSET \
 		#DEFCONT \ ld a,e \ sub l \ ld l,a
-		#DEFCONT \ ld a,d \ sbc h \ ld h,a						; 6*4 = 24t / 6 bytes
+		#DEFCONT \ ld a,d \ sbc h \ ld h,a	; 6*4 = 24t / 6 bytes
 
 		#DEFINE BLOCKCOPY \
 		#DEFCONT \ lddr
@@ -117,7 +118,7 @@ MatchLen:		and %00000111 \ add a,2 \ cp 9
 			call z,ExtendedCode
 
 CopyMatch:		ld c,a
-			push hl						; BC = len, DE = dest, HL = -offset, SP -> [src]
+			push hl		; BC = len, DE = dest, HL = -offset, SP -> [src]
 
 	#IFNDEF	AVOID_SELFMODIFYING_CODE
 PrevOffset		.EQU $+1 \ ld hl,0
@@ -125,8 +126,8 @@ PrevOffset		.EQU $+1 \ ld hl,0
 			push ix \ pop hl
 	#ENDIF
 			ADD_OFFSET
-			BLOCKCOPY					; BC = 0, DE = dest
-			pop hl						; HL = src
+			BLOCKCOPY	; BC = 0, DE = dest
+			pop hl		; HL = src
 
 ReadToken:	ld a,(hl) \ NEXT_HL \ push af
 		and %00011000 \ jr z,NoLiterals
@@ -162,12 +163,16 @@ ExtendedCode:	call ReadNibble \ inc a \ jr z,ExtraByte
 ExtraByte	ld a,15 \ add a,c \ add a,(hl) \ NEXT_HL \ ret nc
 		ld a,(hl) \ NEXT_HL
 		ld b,(hl) \ NEXT_HL \ ret nz
-		pop bc								; RET is not needed, because RET from ReadNibble is sufficient
+		pop bc			; RET is not needed, because RET from ReadNibble is sufficient
 
 
 ReadNibble:	ld c,a
-skipLDCA	xor a \ ex af,af' \ ret m
+skipLDCA	xor a \ nop \ ex af,af' \ ret m		; NOP for Z280 bug
 		ld a,(hl) \ or $F0 \ ex af,af'
 		ld a,(hl) \ NEXT_HL \ or $0F
 		rrca \ rrca \ rrca \ rrca \ ret
 
+; The extraneous NOP instruction above is to workaround a bug in the
+; Z280 processor where ex af,af' can copy rather than swap the flags
+; register.
+; See https://www.retrobrewcomputers.org/forum/index.php?t=msg&goto=10183&

Source/HBIOS/vga.asm

@@ -1039,5 +1039,6 @@ REGS_VGA:
 ;==================================================================================================
 ;
 VGA_IDAT:
+	.DB	KBDMODE_PS2	; PS/2 8242 KEYBOARD CONTROLLER
 	.DB	VGA_KBDST
 	.DB	VGA_KBDDATA

Source/HBIOS/vrc.asm

@@ -0,0 +1,670 @@
+;======================================================================
+;	VIDEO DRIVER FOR VGARC
+;	https://www.retrobrewcomputers.org/doku.php?id=builderpages:plasmo:vgarc1:vgarc1home
+;
+;	WRITTEN BY: WAYNE WARTHEN -- 5/1/2023
+;======================================================================
+;
+; TODO:
+;
+;======================================================================
+; VGARC DRIVER - CONSTANTS
+;======================================================================
+;
+VRC_BASE	.EQU	$00		; FIRST CHAR DATA PORT
+VRC_FONTBASE	.EQU	VRC_BASE + $0C	; FIRST FONT PORT
+VRC_SCROLLIO	.EQU	$F5		; SCROLL REG PORT
+;
+VRC_KBDDATA	.EQU	$F4
+VRC_KBDST	.EQU	$F5
+;
+VRC_ROWS	.EQU	48
+VRC_COLS	.EQU	64
+;
+#DEFINE USEFONTVGARC
+#DEFINE	VRC_FONT FONTVGARC
+;
+TERMENABLE	.SET	TRUE		; INCLUDE TERMINAL PSEUDODEVICE DRIVER
+;
+;======================================================================
+; VRC DRIVER - INITIALIZATION
+;======================================================================
+;
+VRC_INIT:
+	LD	IY,VRC_IDAT		; POINTER TO INSTANCE DATA
+;
+	CALL	NEWLINE			; FORMATTING
+	PRTS("VRC: IO=0x$")
+	LD	A,VRC_BASE
+	CALL	PRTHEXBYTE
+	CALL	VRC_PROBE		; CHECK FOR HW PRESENCE
+	JR	Z,VRC_INIT1		; CONTINUE IF HW PRESENT
+;
+	; HARDWARE NOT PRESENT
+	PRTS(" NOT PRESENT$")
+	OR	$FF			; SIGNAL FAILURE
+	RET
+;
+VRC_INIT1:
+	; RECORD DRIVER ACTIVE
+	OR	$FF
+	LD	(VRC_ACTIVE),A
+	; DISPLAY CONSOLE DIMENSIONS
+	LD	A,VRC_COLS
+	CALL	PC_SPACE
+	CALL	PRTDECB
+	LD	A,'X'
+	CALL	COUT
+	LD	A,VRC_ROWS
+	CALL	PRTDECB
+	PRTS(" TEXT$")
+
+	; HARDWARE INITIALIZATION
+	CALL 	VRC_CRTINIT		; SETUP THE VGARC CHIP REGISTERS
+	CALL	VRC_LOADFONT		; LOAD FONT DATA FROM ROM TO VGARC STORAGE
+	CALL	VRC_VDARES		; RESET
+	CALL	KBD_INIT		; INITIALIZE KEYBOARD DRIVER
+
+	; ADD OURSELVES TO VDA DISPATCH TABLE
+	LD	BC,VRC_FNTBL		; BC := FUNCTION TABLE ADDRESS
+	LD	DE,VRC_IDAT		; DE := VGARC INSTANCE DATA PTR
+	CALL	VDA_ADDENT		; ADD ENTRY, A := UNIT ASSIGNED
+
+	; INITIALIZE EMULATION
+	LD	C,A			; C := ASSIGNED VIDEO DEVICE NUM
+	LD	DE,VRC_FNTBL		; DE := FUNCTION TABLE ADDRESS
+	LD	HL,VRC_IDAT		; HL := VGARC INSTANCE DATA PTR
+	CALL	TERM_ATTACH		; DO IT
+
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+;======================================================================
+; VGARC DRIVER - VIDEO DISPLAY ADAPTER (VDA) FUNCTIONS
+;======================================================================
+;
+VRC_FNTBL:
+	.DW	VRC_VDAINI
+	.DW	VRC_VDAQRY
+	.DW	VRC_VDARES
+	.DW	VRC_VDADEV
+	.DW	VRC_VDASCS
+	.DW	VRC_VDASCP
+	.DW	VRC_VDASAT
+	.DW	VRC_VDASCO
+	.DW	VRC_VDAWRC
+	.DW	VRC_VDAFIL
+	.DW	VRC_VDACPY
+	.DW	VRC_VDASCR
+	.DW	KBD_STAT
+	.DW	KBD_FLUSH
+	.DW	KBD_READ
+	.DW	VRC_VDARDC
+#IF (($ - VRC_FNTBL) != (VDA_FNCNT * 2))
+	.ECHO	"*** INVALID VRC FUNCTION TABLE ***\n"
+	!!!!!
+#ENDIF
+
+VRC_VDAINI:
+	; RESET VDA
+	; CURRENTLY IGNORES VIDEO MODE AND BITMAP DATA
+	CALL	VRC_VDARES	; RESET VDA
+	XOR	A		; SIGNAL SUCCESS
+	RET
+
+VRC_VDAQRY:
+	LD	C,$00		; MODE ZERO IS ALL WE KNOW
+	LD	D,VRC_ROWS	; ROWS
+	LD	E,VRC_COLS	; COLS
+	LD	HL,0		; EXTRACTION OF CURRENT BITMAP DATA NOT SUPPORTED YET
+	XOR	A		; SIGNAL SUCCESS
+	RET
+
+VRC_VDARES:
+	XOR	A		; CLEAR ATTRIBUTES (REV VIDEO OFF)
+	LD	(VRC_ATTR),A	; SAVE IT
+	DEC	A		; INIT CUR NESTING, INIT TO HIDDEN
+	LD	(VRC_CURSOR),A	; SAVE IT
+	LD	HL,0		; ZERO THE SCROLL OFFSET
+	LD	(VRC_OFF),HL	; SAVE VALUE
+	XOR	A		; ZERO
+	LD	(VRC_LOFF),A	; SCROLL OFFSET (LINES)
+	LD	A,' '		; BLANK THE SCREEN
+	LD	DE,VRC_ROWS*VRC_COLS	; FILL ENTIRE BUFFER
+	CALL	VRC_FILL	; DO IT
+	LD	DE,0		; ROW = 0, COL = 0
+	CALL	VRC_XY		; SEND CURSOR TO TOP LEFT
+	CALL	VRC_SHOWCUR	; NOW SHOW THE CURSOR
+;
+	XOR	A		; SIGNAL SUCCESS
+	RET
+
+VRC_VDADEV:
+	LD	D,VDADEV_VRC	; D := DEVICE TYPE
+	LD	E,0		; E := PHYSICAL UNIT IS ALWAYS ZERO
+	LD	H,0		; H := 0, DRIVER HAS NO MODES
+	LD	L,VRC_BASE	; L := BASE I/O ADDRESS
+	XOR	A		; SIGNAL SUCCESS
+	RET
+
+VRC_VDASCS:
+	SYSCHKERR(ERR_NOTIMPL)	; NOT IMPLEMENTED (YET)
+	RET
+
+VRC_VDASCP:
+	CALL	VRC_XY		; SET CURSOR POSITION
+	XOR	A		; SIGNAL SUCCESS
+	RET
+
+VRC_VDASAT:
+	; INCOMING IS:  -----RUB (R=REVERSE, U=UNDERLINE, B=BLINK)
+	;
+	; ALL WE SUPPORT IS REVERSE.  MOVE BIT TO BIT 7 OF ATTR BYTE
+	LD	A,E		; GET ATTR VALUE
+	RRCA			; ROTATE TO BIT 7
+	RRCA
+	RRCA
+	AND	$80		; ENSURE ONLY BIT 7
+	LD	(VRC_ATTR),A	; SAVE IT
+	XOR	A		; SIGNAL SUCCESS
+	RET			; DONE
+
+VRC_VDASCO:
+	; INCOMING IS:  IBGRIBGR (I=INTENSITY, B=BLUE, G=GREEN, R=RED)
+	;
+	; NONE SUPPORTED, IGNORE
+	XOR	A		; SIGNAL SUCCESS
+	RET			; DONE
+
+VRC_VDAWRC:
+	LD	A,E		; CHARACTER TO WRITE GOES IN A
+	CALL	VRC_PUTCHAR	; PUT IT ON THE SCREEN
+	XOR	A		; SIGNAL SUCCESS
+	RET
+
+VRC_VDAFIL:
+	LD	A,E		; FILL CHARACTER GOES IN A
+	EX	DE,HL		; FILL LENGTH GOES IN DE
+	CALL	VRC_FILL	; DO THE FILL
+	XOR	A		; SIGNAL SUCCESS
+	RET
+
+VRC_VDACPY:
+	; LENGTH IN HL, SOURCE ROW/COL IN DE, DEST IS VRC_POS
+	; BLKCPY USES: HL=SOURCE, DE=DEST, BC=COUNT
+	PUSH	HL		; SAVE LENGTH
+	CALL	VRC_XY2IDX	; ROW/COL IN DE -> SOURCE ADR IN HL
+	POP	BC		; RECOVER LENGTH IN BC
+	LD	DE,(VRC_POS)	; PUT DEST IN DE
+	JP	VRC_BLKCPY	; DO A BLOCK COPY
+
+VRC_VDASCR:
+	LD	A,E		; LOAD E INTO A
+	OR	A		; SET FLAGS
+	RET	Z		; IF ZERO, WE ARE DONE
+	PUSH	DE		; SAVE E
+	JP	M,VRC_VDASCR1	; E IS NEGATIVE, REVERSE SCROLL
+	CALL	VRC_SCROLL	; SCROLL FORWARD ONE LINE
+	POP	DE		; RECOVER E
+	DEC	E		; DECREMENT IT
+	JR	VRC_VDASCR	; LOOP
+VRC_VDASCR1:
+	CALL	VRC_RSCROLL	; SCROLL REVERSE ONE LINE
+	POP	DE		; RECOVER E
+	INC	E		; INCREMENT IT
+	JR	VRC_VDASCR	; LOOP
+
+;----------------------------------------------------------------------
+; READ VALUE AT CURRENT VDU BUFFER POSITION
+; RETURN E = CHARACTER, B = COLOUR, C = ATTRIBUTES
+;----------------------------------------------------------------------
+
+VRC_VDARDC:
+	OR	$FF		; UNSUPPORTED FUNCTION
+	RET
+;
+;======================================================================
+; VGARC DRIVER - PRIVATE DRIVER FUNCTIONS
+;======================================================================
+;
+;
+;----------------------------------------------------------------------
+; PROBE FOR VGARC HARDWARE
+;----------------------------------------------------------------------
+;
+; ON RETURN, ZF SET INDICATES HARDWARE FOUND
+;
+VRC_PROBE:
+	LD	C,VRC_BASE + 1		; +1 AVOIDS LEDS
+	LD	B,$00
+	LD	A,$AA
+	OUT	(C),A
+	INC	B
+	LD	A,$55
+	OUT	(C),A
+	DEC	B
+	IN	A,(C)
+	CP	$AA
+	RET	NZ
+	INC	B
+	IN	A,(C)
+	CP	$55
+	RET
+;
+;----------------------------------------------------------------------
+; CRTC DISPLAY CONTROLLER CHIP INITIALIZATION
+;----------------------------------------------------------------------
+;
+VRC_CRTINIT:
+	XOR	A			; ZERO ACCUM
+	LD	A,$80			; ACTIVATE AND ZERO HW SCROLL
+	OUT	(VRC_SCROLLIO),A	; RESET HW SCROLL
+	RET				; DONE
+;
+;----------------------------------------------------------------------
+; LOAD FONT DATA
+;----------------------------------------------------------------------
+;
+VRC_LOADFONT:
+;
+#IF USELZSA2
+	LD	(VRC_STACK),SP		; SAVE STACK
+	LD	HL,(VRC_STACK)		; AND SHIFT IT
+	LD	DE,$2000		; DOWN 4KB TO
+	OR	A			; CREATE A
+	SBC	HL,DE			; DECOMPRESSION BUFFER
+	LD	SP,HL			; HL POINTS TO BUFFER
+	EX	DE,HL			; START OF STACK BUFFER
+	PUSH	DE			; SAVE IT
+	LD	HL,VRC_FONT		; START OF FONT DATA
+	CALL	DLZSA2			; DECOMPRESS TO DE
+	POP	HL			; RECALL STACK BUFFER POSITION
+#ELSE
+	LD	HL,VRC_FONT		; START OF FONT DATA
+#ENDIF
+;
+#IF 0
+	; THIS APPROACH TO LOADING FONTS IS BEST (FASTEST), BUT IS
+	; CAUSING ARTIFACTS ON THE DISPLAYED FONTS WHEN RUN ON A
+	; Z280.  IT IS NOT CLEAR WHAT THE PROBLEM IS (POSSIBLY
+	; Z280 BUG), BUT FOR NOW WE AVOID THIS AND USE AN
+	; ALTERNATIVE APPROACH BELOW.
+	LD	DE,0+(128*8)-1		; LENGTH OF FONT DATA - 1
+	ADD	HL,DE			; ADD TO HL
+	LD	BC,VRC_FONTBASE+3	; WORK BACKWARDS
+	OTDR				; DO 4 PAGES
+	DEC	C
+	OTDR
+	DEC	C
+	OTDR
+	DEC	C
+	OTDR
+	DEC	C
+#ENDIF
+;
+#IF 1
+	; ALTERNATIVE APPROACH TO LOADING FONTS.  THIS ONE AVOIDS
+	; THE USE OF OTDR WHICH SEEMS TO CAUSE PROBLEMS ON Z280.
+	LD	B,0
+	LD	C,VRC_FONTBASE
+VRC_LOADFONT1:
+	LD	A,(HL)
+	OUT	(C),A
+	INC	HL
+	INC	B
+	JR	NZ,VRC_LOADFONT1
+	INC	C
+	LD	A,C
+	CP	VRC_FONTBASE + 4
+	JR	NZ,VRC_LOADFONT1
+#ENDIF
+;
+#IF USELZSA2
+	LD	HL,(VRC_STACK)		; ERASE DECOMPRESS BUFFER
+	LD	SP,HL			; BY RESTORING THE STACK
+	RET				; DONE
+VRC_STACK	.DW	0
+#ELSE
+	RET
+#ENDIF
+;
+;----------------------------------------------------------------------
+; SET CURSOR POSITION TO ROW IN D AND COLUMN IN E
+;----------------------------------------------------------------------
+;
+VRC_XY:
+	PUSH	DE			; SAVE NEW POSITION FOR NOW
+	CALL	VRC_HIDECUR		; HIDE THE CURSOR
+	POP	DE			; RECOVER INCOMING ROW/COL
+	CALL	VRC_XY2IDX		; CONVERT ROW/COL TO BUF IDX
+	LD	(VRC_POS),HL		; SAVE THE RESULT (DISPLAY POSITION)
+	JP	VRC_SHOWCUR		; SHOW THE CURSOR AND EXIT
+;
+;----------------------------------------------------------------------
+; CONVERT XY COORDINATES IN DE INTO LINEAR INDEX IN HL
+; D=ROW, E=COL
+;----------------------------------------------------------------------
+;
+VRC_XY2IDX:
+	LD	A,E			; SAVE COLUMN NUMBER IN A
+	LD	H,D			; SET H TO ROW NUMBER
+	LD	E,VRC_COLS		; SET E TO ROW LENGTH
+	CALL	MULT8			; MULTIPLY TO GET ROW OFFSET, H * E = HL, E=0, B=0
+	LD	E,A			; GET COLUMN BACK
+	ADD	HL,DE			; ADD IT IN
+
+	LD	DE,(VRC_OFF)		; SCREEN OFFSET
+	ADD	HL,DE			; ADJUST
+;
+	PUSH	HL			; SAVE IT
+	LD	DE,VRC_ROWS * VRC_COLS	; DE := BUF SIZE
+	OR	A			; CLEAR CARRY
+	SBC	HL,DE			; SUBTRACT FROM HL
+	JR	C,VRC_XY2IDX1		; BYPASS IF NO WRAP
+	POP	DE			; THROW AWAY TOS
+	RET				; DONE
+VRC_XY2IDX1:
+	POP	HL			; NO WRAP, RESTORE
+	RET				; RETURN
+;
+;----------------------------------------------------------------------
+; SHOW OR HIDE CURSOR
+;----------------------------------------------------------------------
+;
+; VGARC USES HIGH BIT OF CHAR VALUE FOR INVERSE VIDEO.  WE HAVE NO
+; HARDWARE CURSOR, SO WE LEVERAGE THE INVERSE VIDEO TO SHOW A CURSOR.
+; SINCE ANY OPERATION THAT POTENTIALLY OVERWERITES THE CURSOR POSITION
+; COULD DESTROY THE CURSOR, WE HAVE A COUPLE FUNCTIONS TO SHOW AND
+; HIDE THE CURSOR.  A VARIABLE IS USED TO TRACK THE SHOW/HIDE
+; OPERATIONS BECAUSE WE MAY HAVE NESTED CALLS.  ZERO MEANS SHOW
+; REAL CURSOR.  ANY VALUE LESS THAN ZERO MEANS HIDDEN.
+;
+VRC_SHOWCUR:
+	LD	A,(VRC_CURSOR)		; GET CURRENT NESTING VALUE
+	INC	A			; INCREMENT TO SHOW
+	LD	(VRC_CURSOR),A		; SAVE IT
+	RET	NZ			; ALREADY SHOWN, NOTHING TO DO
+;
+	; WE TRANSITIONED FROM NON-ZERO TO ZERO.  NEED TO ACTUALLY
+	; SHOW THE CURSOR NOW.
+;
+	JR	VRC_FLIPCUR
+;
+VRC_HIDECUR:
+	LD	A,(VRC_CURSOR)		; GET CURRENT NESTING VALUE
+	DEC	A			; DECREMENT TO HIDE
+	LD	(VRC_CURSOR),A		; SAVE IT
+	INC	A			; BACK TO ORIGINAL VALUE
+	RET	NZ			; ALREADY HIDDEN, NOTHING TO DO
+;
+	; WE TRANSITIONED FROM ZERO TO NEGATIVE.  NEED TO ACTUALLY
+	; HIDE THE CURSOR NOW.  SINCE SHOWING AND HIDING ARE THE
+	; SAME OPERATION (FLIP REV VID BIT), WE REUSE CODE ABOVE.
+;
+	JR	VRC_FLIPCUR
+;
+VRC_FLIPCUR:
+	; SHOWING OR HIDING THE CURSOR IS THE SAME OPERATION.
+	; SO WE USE COMMON CODE TO FLIP THE REV VID BIT.
+	LD	HL,(VRC_POS)		; CURSOR POSITION
+	LD	B,L			; INVERT FOR I/O
+	LD	C,H
+	IN	A,(C)			; GET VALUE
+	XOR	$80			; FLIP REV VID BIT
+	OUT	(C),A			; WRITE NEW VALUE
+	RET
+;
+;----------------------------------------------------------------------
+; WRITE VALUE IN A TO CURRENT VDU BUFFER POSITION, ADVANCE CURSOR
+;----------------------------------------------------------------------
+;
+VRC_PUTCHAR:
+	; WRITE CHAR AT CURRENT CURSOR POSITION.  SINCE THE CURSOR
+	; IS JUST THE HIGH BIT (REV VIDEO), WE FIRST TURN OFF THE
+	; CURSOR, WRITE THE CHAR, UPDATE THE CURSOR POSITION, AND
+	; FINALLY TURN THE CURSOR BACK ON AT THE NEW POSITION.
+;
+	PUSH	AF			; SAVE INCOMING CHAR
+	CALL	VRC_HIDECUR		; HIDE CURSOR
+	POP	AF
+	LD	HL,(VRC_POS)		; GET CUR BUF POSITION
+	LD	B,L			; INVERT FOR I/O
+	LD	C,H
+	AND	$7F			; SUPPRESS ATTRIBUTE (HI BIT)
+	LD	L,A			; PUT VALUE IN L
+	LD	A,(VRC_ATTR)		; GET CURRENT ATTRIBUTE
+	OR	L			; COMBINE WITH CHAR VALUE
+	OUT	(C),A			; WRITE VALUE TO BUFFER
+;
+	; SET CURSOR AT NEW POSITION
+	LD	HL,(VRC_POS)		; GET CURRENT BUF OFFSET
+	INC	HL			; INCREMENT
+	PUSH	HL			; SAVE IT
+	LD	DE,VRC_ROWS * VRC_COLS	; DE := BUF SIZE
+	OR	A			; CLEAR CARRY
+	SBC	HL,DE			; SUBTRACT FROM HL
+	JR	C,VRC_PUTCHAR1		; BYPASS IF NO WRAP
+	POP	DE			; THROW AWAY TOS
+	LD	HL,0			; BACK TO START
+	JR	VRC_PUTCHAR2		; CONTINUE
+VRC_PUTCHAR1:
+	POP	HL			; NO WRAP, RESTORE
+VRC_PUTCHAR2:
+	LD	(VRC_POS),HL		; SAVE NEW POSITION
+	JP	VRC_SHOWCUR		; SHOW IT AND RETURN
+;
+;----------------------------------------------------------------------
+; FILL AREA IN BUFFER WITH SPECIFIED CHARACTER AND CURRENT COLOR/ATTRIBUTE
+; STARTING AT THE CURRENT FRAME BUFFER POSITION
+;   A: FILL CHARACTER
+;   DE: NUMBER OF CHARACTERS TO FILL
+;----------------------------------------------------------------------
+;
+VRC_FILL:
+	LD	(VRC_FILL1+1),A		; SAVE FILL CHAR
+	PUSH	DE			; SAVE INCOMING DE
+	CALL	VRC_HIDECUR		; HIDE CURSOR
+	POP	DE			; RESTORE INCOMING DE
+	LD	HL,(VRC_POS)		; STARTING POSITION
+;
+VRC_FILL1:
+	LD	A,$FF			; FILL CHAR
+	LD	B,L			; INVERT FOR I/O
+	LD	C,H
+	OUT	(C),A			; PUT CHAR TO BUF
+;
+	DEC	DE			; DECREMENT COUNT
+	LD	A,D			; TEST FOR ZERO
+	OR	E
+	JP	Z,VRC_SHOWCUR		; EXIT VIA SHOW CURSOR IF DONE
+;
+	INC	HL			; INCREMENT
+	PUSH	HL			; SAVE IT
+	LD	BC,VRC_ROWS * VRC_COLS	; BC := BUF SIZE
+	OR	A			; CLEAR CARRY
+	SBC	HL,BC			; SUBTRACT FROM HL
+	JR	C,VRC_FILL2		; BYPASS IF NO WRAP
+	POP	BC			; THROW AWAY TOS
+	LD	HL,0			; BACK TO START
+	JR	VRC_FILL3		; CONTINUE
+VRC_FILL2:
+	POP	HL			; NO WRAP, RESTORE
+VRC_FILL3:
+	LD	(VRC_POS),HL		; SAVE NEW POSITION
+	JR	VRC_FILL1		; LOOP TILL DONE
+;
+;----------------------------------------------------------------------
+; SCROLL ENTIRE SCREEN FORWARD BY ONE LINE (CURSOR POSITION UNCHANGED)
+;----------------------------------------------------------------------
+;
+VRC_SCROLL:
+	; SCROLL DOWN 1 LINE VIA HARDWARE
+	CALL	VRC_HIDECUR		; SUPPRESS CURSOR
+	LD	A,(VRC_LOFF)		; GET LINE OFFSET
+	INC	A			; BUMP
+	CP	VRC_ROWS		; OVERFLOW?
+	JR	C,VRC_SCROLL1		; IF NOT, SKIP
+	XOR	A			; ELSE, BACK TO ZERO
+VRC_SCROLL1:
+	LD	(VRC_LOFF),A		; SAVE NEW VALUE
+	OR	$80			; SET HW SCROLL ENABLE BIT
+	OUT	(VRC_SCROLLIO),A	; DO IT
+;
+	; ADJUST BUFFER OFFSET
+	LD	HL,(VRC_OFF)		; BUFFER OFFSET
+	LD	DE,VRC_COLS		; COLUMNS
+	ADD	HL,DE			; ADD TO GET NEW OFFSET
+	PUSH	HL			; SAVE IT
+	LD	DE,VRC_ROWS * VRC_COLS	; DE := BUF SIZE
+	OR	A			; CLEAR CARRY
+	SBC	HL,DE			; SUBTRACT FROM HL
+	JR	C,VRC_SCROLL2		; BYPASS IF NO WRAP
+	POP	DE			; BURN TOS
+	JR	VRC_SCROLL3		; CONTINUE
+VRC_SCROLL2:
+	POP	HL			; NO WRAP, RESTORE HL
+VRC_SCROLL3:
+	LD	(VRC_OFF),HL		; SAVE NEW OFFSET
+;
+	; FILL EXPOSED LINE
+	LD	HL,(VRC_POS)		; GET CURSOR POS
+	PUSH	HL			; SAVE IT
+	LD	D,VRC_ROWS - 1		; LAST ROW
+	LD	E,0			; FIRST COLUMN
+	CALL	VRC_XY2IDX		; HL = START OF LAST LINE
+	LD	(VRC_POS),HL		; SET FILL POSITION
+	LD	A,' '			; FILL WITH BLANKS
+	LD	DE,VRC_COLS		; FILL ONE LINE
+	CALL	VRC_FILL		; FILL LAST LINE
+	POP	HL			; RECOVER CURSOR POS
+	LD	(VRC_POS),HL		; PUT VALUE BACK
+;
+	; ADJUST CURSOR POSITION 
+	LD	HL,(VRC_POS)		; CURSOR POSITION
+	LD	DE,VRC_COLS		; COLUMNS
+	ADD	HL,DE			; NEW CURSOR POS
+	PUSH	HL			; SAVE IT
+	LD	DE,VRC_ROWS * VRC_COLS	; DE := DISPLAY SIZE
+	OR	A			; CLEAR CARRY
+	SBC	HL,DE			; SUBTRACT FROM HL
+	JR	C,VRC_SCROLL4		; BYPASS IF NO WRAP
+	POP	DE			; BURN TOS
+	JR	VRC_SCROLL5		; CONTINUE
+VRC_SCROLL4:
+	POP	HL			; NO WRAP, RESTORE HL
+VRC_SCROLL5:
+	LD	(VRC_POS),HL		; SAVE NEW CURSOR POS
+	JP	VRC_SHOWCUR		; EXIT VIA SHOW CURSOR
+;
+;----------------------------------------------------------------------
+; REVERSE SCROLL ENTIRE SCREEN BY ONE LINE (CURSOR POSITION UNCHANGED)
+;----------------------------------------------------------------------
+;
+VRC_RSCROLL:
+	; SCROLL UP 1 LINE VIA HARDWARE
+	CALL	VRC_HIDECUR		; SUPPRESS CURSOR
+	LD	A,(VRC_LOFF)		; GET LINE OFFSET
+	DEC	A			; BUMP
+	CP	$FF			; OVERFLOW?
+	JR	NZ,VRC_RSCROLL1		; IF NOT, SKIP
+	LD	A,VRC_ROWS - 1		; ELSE, BACK TO LAST ROW
+VRC_RSCROLL1:
+	LD	(VRC_LOFF),A		; SAVE NEW VALUE
+	OR	$80			; SET HW SCROLL ENABLE BIT
+	OUT	(VRC_SCROLLIO),A	; DO IT
+;
+	; ADJUST BUFFER OFFSET
+	LD	HL,(VRC_OFF)		; BUFFER OFFSET
+	LD	DE,VRC_COLS		; COLUMNS
+	OR	A			; CLEAR CARRY
+	SBC	HL,DE			; SUBTRACT TO GET NEW OFFSET
+	PUSH	HL			; SAVE IT
+	JR	NC,VRC_RSCROLL2		; BYPASS IF NO WRAP
+	LD	DE,VRC_ROWS * VRC_COLS	; DISPLAY SIZE
+	ADD	HL,DE			; HANDLE WRAP
+	POP	DE			; BURN TOS
+	JR	VRC_RSCROLL3		; CONTINUE
+VRC_RSCROLL2:
+	POP	HL			; NO WRAP, RESTORE HL
+VRC_RSCROLL3:
+	LD	(VRC_OFF),HL		; SAVE NEW OFFSET
+;
+	; FILL EXPOSED LINE
+	LD	HL,(VRC_POS)		; GET CURSOR POS
+	PUSH	HL			; SAVE IT
+	LD	D,0			; FIRST ROW
+	LD	E,0			; FIRST COLUMN
+	CALL	VRC_XY2IDX		; HL = START OF FIRST LINE
+	LD	(VRC_POS),HL		; SET FILL POSITION
+	LD	A,' '			; FILL WITH BLANKS
+	LD	DE,VRC_COLS		; FILL ONE LINE
+	CALL	VRC_FILL		; FILL FIRST LINE
+	POP	HL			; RECOVER CURSOR POS
+	LD	(VRC_POS),HL		; PUT VALUE BACK
+;
+	; ADJUST CURSOR POSITION 
+	LD	HL,(VRC_POS)		; CURSOR POSITION
+	LD	DE,VRC_COLS		; COLUMNS
+	OR	A			; CLEAR CARRY
+	SBC	HL,DE			; NEW CURSOR POS
+	PUSH	HL			; SAVE IT
+	JR	NC,VRC_RSCROLL4		; BYPASS IF NO WRAP
+	LD	DE,VRC_ROWS * VRC_COLS	; DISPLAY SIZE
+	ADD	HL,DE			; HANDLE WRAP
+	POP	DE			; BURN TOS
+	JR	VRC_RSCROLL5		; CONTINUE
+VRC_RSCROLL4:
+	POP	HL			; NO WRAP, RESTORE HL
+VRC_RSCROLL5:
+	LD	(VRC_POS),HL		; SAVE NEW CURSOR POS
+	JP	VRC_SHOWCUR		; EXIT VIA SHOW CURSOR
+;
+;----------------------------------------------------------------------
+; BLOCK COPY BC BYTES FROM HL TO DE
+;----------------------------------------------------------------------
+;
+VRC_BLKCPY:
+	PUSH	BC
+	PUSH	HL
+	CALL	VRC_HIDECUR
+	POP	HL
+	POP	BC
+;
+VRC_BLKCPY1:
+	LD	A,B
+	OR	C
+	JP	Z,VRC_SHOWCUR		; EXIT VIA SHOW CURSOR
+;
+	PUSH	BC			; SAVE LOOP CTL
+	LD	B,L			; INVERT FOR I/O
+	LD	C,H
+	IN	A,(C)			; GET SOURCE CHAR
+	LD	B,E			; INVERT FOR I/O
+	LD	C,D
+	OUT	(C),A			; WRITE DEST CHAR
+	POP	BC			; RESTORE LOOP CTL
+;
+	INC	HL			; NEXT SRC CHAR
+	INC	DE			; NEXT DEST CHAR
+	DEC	BC			; DEC COUNT
+	JR	VRC_BLKCPY1		; LOOP TILL DONE
+;
+;==================================================================================================
+;   VGARC DRIVER - DATA
+;==================================================================================================
+;
+VRC_ATTR	.DB	0	; CURRENT COLOR
+VRC_POS		.DW 	0	; CURRENT DISPLAY POSITION
+VRC_OFF		.DW	0	; SCREEN START OFFSET INTO DISP BUF
+VRC_LOFF	.DB	0	; LINE OFFSET INTO DISP BUF
+VRC_CURSOR	.DB	0	; CURSOR NESTING LEVEL
+VRC_ACTIVE	.DB	FALSE	; FLAG FOR DRIVER ACTIVE
+;
+;==================================================================================================
+;   VGA DRIVER - INSTANCE DATA
+;==================================================================================================
+;
+VRC_IDAT:
+	.DB	KBDMODE_VRC	; VGARC KEYBOARD CONTROLLER
+	.DB	VRC_KBDST
+	.DB	VRC_KBDDATA

Source/Images/d_dos65/ReadMe.txt

@@ -4,6 +4,10 @@ This disk is one of several ready-to-run disks provided with RomWBW.
 It contains the files to start and run DOS/65 on an MBC system that
 contains Dan Werner's 6502 processor.
 
+WARNING: This is a work in progress.  Use of this disk image requires
+specific hardware and configuration.  You should contact Dan Werner
+before attempting to use this disk image.
+
 The remainder of this document describes the usage and contents of
 this disk.  It is highly recommended that you review the "RomWBW
 User Guide.pdf" document found in the Doc directory of the

Source/Images/d_dos65/u0/alloc.s19

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Source/Images/d_dos65/u0/asm.s19

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