Workaround CH376 Reset Behavior

I am encountering some CH376 chips that go haywire after a
reset command.  They stop responding for a very long time.
I am seeing this only on "LC Tech" adapters and only on Z80
systems (not Z180).  No idea what is going on, so I am
giving up for now and removing the reset.

.github/workflows/commit.yml

@@ -26,7 +26,7 @@ jobs:
         run: |
           export TZ='America/Los_Angeles'
           sudo apt-get install srecord
-          make dist
+          make distlog
           rm -rf .git*
 
       - name: List Output
@@ -58,7 +58,7 @@ jobs:
         run: |
           export TZ='America/Los_Angeles'
           brew install srecord
-          make dist
+          make distlog
           rm -rf .git*
 
       - name: List Output

.github/workflows/release.yml

@@ -19,7 +19,7 @@ jobs:
           export TZ='America/Los_Angeles'
           sudo apt-get install libncurses-dev
           sudo apt-get install srecord
-          make dist
+          make distlog
           rm -rf .git*
       
       - name: Create Package Archive

.gitignore

@@ -95,8 +95,9 @@ Tools/unix/zx/zx
 !Source/ZPM3/*.[Cc][Oo][Mm]
 !Source/ZSDOS/*.[Cc][Oo][Mm]
 !Source/ZRC/*.bin
-!Source/ZZRC/*.bin
-!Source/ZZRC/*.hex
+!Source/ZRC512/*.bin
+!Source/Z1RCC/*.bin
+!Source/ZZRCC/*.bin
 !Tools/cpm/**
 !Tools/unix/zx/*
 !Tools/zx/*

Doc/ChangeLog.txt

@@ -2,6 +2,10 @@ Version 3.4
 -----------
 NOTE: Changes require HBIOS/CBIOS/Apps sync, version bump to 3.4 to ensure integrity
 - WBW: Device type number moved from upper nibble to full byte
+- A?C: Support for EP ITX-Mini Z180 Platform
+- M?R: Significant improvement in User Guide document
+- J?P: Preliminary support for Monsputer (MON)
+
 
 Version 3.3
 -----------

Makefile

@@ -1,5 +1,8 @@
 .PHONY: tools source clean clobber diff dist
 
+.ONESHELL:
+.SHELLFLAGS = -cex
+
 all: tools source
 
 tools:
@@ -20,6 +23,9 @@ diff:
 	$(MAKE) --directory Source diff
 
 dist:
-	$(MAKE) ROM_PLATFORM=dist 2>&1 | tee make.log
-	$(MAKE) --directory Source clean
+	$(MAKE) ROM_PLATFORM=dist
 	$(MAKE) --directory Tools clean
+	$(MAKE) --directory Source clean
+
+distlog:
+	$(MAKE) dist 2>&1 | tee make.log

ReadMe.md

@@ -3,7 +3,7 @@
 **RomWBW ReadMe** \
 Version 3.4 \
 Wayne Warthen  ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \
-09 Oct 2023
+18 Dec 2023
 
 # Overview
 
@@ -14,15 +14,24 @@ platforms are supported including those produced by these developer
 communities:
 
 - [RetroBrew Computers](https://www.retrobrewcomputers.org)
-- [RC2014](https://rc2014.co.uk),
+  (<https://www.retrobrewcomputers.org>)
+- [RC2014](https://rc2014.co.uk) (<https://rc2014.co.uk>),  
   [RC2014-Z80](https://groups.google.com/g/rc2014-z80)
-- [retro-comp](https://groups.google.com/forum/#!forum/retro-comp)
+  (<https://groups.google.com/g/rc2014-z80>)
+- [Retro Computing](https://groups.google.com/g/retro-comp)
+  (<https://groups.google.com/g/retro-comp>)
 - [Small Computer Central](https://smallcomputercentral.com/)
+  (<https://smallcomputercentral.com/>)
+
+A complete list of the currently supported platforms is found in the
+\[Installation\] section.
 
 General features include:
 
+- Z80 Family CPUs including Z80, Z180, and Z280
 - Banked memory services for several banking designs
-- Disk drivers for RAM, ROM, Floppy, IDE, CF, and SD
+- Disk drivers for RAM, ROM, Floppy, IDE ATA/ATAPI, CF, SD, USB, Zip,
+  Iomega
 - Serial drivers including UART (16550-like), ASCI, ACIA, SIO
 - Video drivers including TMS9918, SY6545, MOS8563, HD6445
 - Keyboard (PS/2) drivers via VT8242 or PPI interfaces
@@ -42,11 +51,11 @@ ROM firmware itself:
 
 A dynamic disk drive letter assignment mechanism allows mapping
 operating system drive letters to any available disk media.
-Additionally, mass storage devices (IDE Disk, CF Card, SD Card) support
-the use of multiple slices (up to 256 per device). Each slice contains a
-complete CP/M filesystem and can be mapped independently to any drive
-letter. This overcomes the inherent size limitations in legacy OSes and
-allows up to 2GB of accessible storage on a single device.
+Additionally, mass storage devices (IDE Disk, CF Card, SD Card, etc.)
+support the use of multiple slices (up to 256 per device). Each slice
+contains a complete CP/M filesystem and can be mapped independently to
+any drive letter. This overcomes the inherent size limitations in legacy
+OSes and allows up to 2GB of accessible storage on a single device.
 
 The pre-built ROM firmware images are generally suitable for most users.
 However, it is also very easy to modify and build custom ROM images that
@@ -66,7 +75,7 @@ changing media.
 By design, RomWBW isolates all of the hardware specific functions in the
 ROM chip itself. The ROM provides a hardware abstraction layer such that
 all of the operating systems and applications on a disk will run on any
-RomWBW-based system. To put it simply, you can take a disk (or CF/SD
+RomWBW-based system. To put it simply, you can take a disk (or CF/SD/USB
 Card) and move it between systems transparently.
 
 A tool is provided that allows you to access a FAT-12/16/32 filesystem.
@@ -76,18 +85,19 @@ OSes such as Windows, MacOS, and Linux very easy.
 
 # Acquiring RomWBW
 
-The [RomWBW Repository](https://github.com/wwarthen/RomWBW) on GitHub is
-the official distribution location for all project source and
-documentation. The fully-built distribution releases are available on
-the [RomWBW Releases Page](https://github.com/wwarthen/RomWBW/releases)
-of the repository. On this page, you will normally see a Development
-Snapshot as well as recent stable releases. Unless you have a specific
-reason, I suggest you stick to the most recent stable release. Expand
-the “Assets” drop-down for the release you want to download, then select
-the asset named RomWBW-vX.X.X-Package.zip. The Package asset includes
-all pre-built ROM and Disk images as well as full source code. The other
-assets contain only source code and do not have the pre-built ROM or
-disk images.
+The [RomWBW Repository](https://github.com/wwarthen/RomWBW)
+(<https://github.com/wwarthen/RomWBW>) on GitHub is the official
+distribution location for all project source and documentation. The
+fully-built distribution releases are available on the [RomWBW Releases
+Page](https://github.com/wwarthen/RomWBW/releases)
+(<https://github.com/wwarthen/RomWBW/releases>) of the repository. On
+this page, you will normally see a Development Snapshot as well as
+recent stable releases. Unless you have a specific reason, I suggest you
+stick to the most recent stable release. Expand the “Assets” drop-down
+for the release you want to download, then select the asset named
+RomWBW-vX.X.X-Package.zip. The Package asset includes all pre-built ROM
+and Disk images as well as full source code. The other assets contain
+only source code and do not have the pre-built ROM or disk images.
 
 All source code and distributions are maintained on GitHub. Code
 contributions are very welcome.

ReadMe.txt

@@ -1,6 +1,6 @@
 RomWBW ReadMe
 Wayne Warthen (wwarthen@gmail.com)
-09 Oct 2023
+18 Dec 2023
 
 
 
@@ -13,15 +13,21 @@ Z80/180/280 retro-computing hardware systems. A wide variety of
 platforms are supported including those produced by these developer
 communities:
 
--   RetroBrew Computers
--   RC2014, RC2014-Z80
--   retro-comp
--   Small Computer Central
+-   RetroBrew Computers (https://www.retrobrewcomputers.org)
+-   RC2014 (https://rc2014.co.uk),
+    RC2014-Z80 (https://groups.google.com/g/rc2014-z80)
+-   Retro Computing (https://groups.google.com/g/retro-comp)
+-   Small Computer Central (https://smallcomputercentral.com/)
+
+A complete list of the currently supported platforms is found in the
+[Installation] section.
 
 General features include:
 
+-   Z80 Family CPUs including Z80, Z180, and Z280
 -   Banked memory services for several banking designs
--   Disk drivers for RAM, ROM, Floppy, IDE, CF, and SD
+-   Disk drivers for RAM, ROM, Floppy, IDE ATA/ATAPI, CF, SD, USB, Zip,
+    Iomega
 -   Serial drivers including UART (16550-like), ASCI, ACIA, SIO
 -   Video drivers including TMS9918, SY6545, MOS8563, HD6445
 -   Keyboard (PS/2) drivers via VT8242 or PPI interfaces
@@ -41,11 +47,11 @@ ROM firmware itself:
 
 A dynamic disk drive letter assignment mechanism allows mapping
 operating system drive letters to any available disk media.
-Additionally, mass storage devices (IDE Disk, CF Card, SD Card) support
-the use of multiple slices (up to 256 per device). Each slice contains a
-complete CP/M filesystem and can be mapped independently to any drive
-letter. This overcomes the inherent size limitations in legacy OSes and
-allows up to 2GB of accessible storage on a single device.
+Additionally, mass storage devices (IDE Disk, CF Card, SD Card, etc.)
+support the use of multiple slices (up to 256 per device). Each slice
+contains a complete CP/M filesystem and can be mapped independently to
+any drive letter. This overcomes the inherent size limitations in legacy
+OSes and allows up to 2GB of accessible storage on a single device.
 
 The pre-built ROM firmware images are generally suitable for most users.
 However, it is also very easy to modify and build custom ROM images that
@@ -65,7 +71,7 @@ changing media.
 By design, RomWBW isolates all of the hardware specific functions in the
 ROM chip itself. The ROM provides a hardware abstraction layer such that
 all of the operating systems and applications on a disk will run on any
-RomWBW-based system. To put it simply, you can take a disk (or CF/SD
+RomWBW-based system. To put it simply, you can take a disk (or CF/SD/USB
 Card) and move it between systems transparently.
 
 A tool is provided that allows you to access a FAT-12/16/32 filesystem.
@@ -78,16 +84,18 @@ OSes such as Windows, MacOS, and Linux very easy.
 ACQUIRING ROMWBW
 
 
-The RomWBW Repository on GitHub is the official distribution location
-for all project source and documentation. The fully-built distribution
-releases are available on the RomWBW Releases Page of the repository. On
-this page, you will normally see a Development Snapshot as well as
-recent stable releases. Unless you have a specific reason, I suggest you
-stick to the most recent stable release. Expand the “Assets” drop-down
-for the release you want to download, then select the asset named
-RomWBW-vX.X.X-Package.zip. The Package asset includes all pre-built ROM
-and Disk images as well as full source code. The other assets contain
-only source code and do not have the pre-built ROM or disk images.
+The RomWBW Repository (https://github.com/wwarthen/RomWBW) on GitHub is
+the official distribution location for all project source and
+documentation. The fully-built distribution releases are available on
+the RomWBW Releases Page (https://github.com/wwarthen/RomWBW/releases)
+of the repository. On this page, you will normally see a Development
+Snapshot as well as recent stable releases. Unless you have a specific
+reason, I suggest you stick to the most recent stable release. Expand
+the “Assets” drop-down for the release you want to download, then select
+the asset named RomWBW-vX.X.X-Package.zip. The Package asset includes
+all pre-built ROM and Disk images as well as full source code. The other
+assets contain only source code and do not have the pre-built ROM or
+disk images.
 
 All source code and distributions are maintained on GitHub. Code
 contributions are very welcome.

Source/Apps/Build.cmd

@@ -1,13 +1,10 @@
 @echo off
 setlocal
 
-set TOOLS=../../Tools
+set TOOLS=..\..\Tools
 set APPBIN=..\..\Binary\Apps
-
 set PATH=%TOOLS%\tasm32;%TOOLS%\zxcc;%PATH%
-
 set TASMTABS=%TOOLS%\tasm32
-
 set CPMDIR80=%TOOLS%/cpm/
 
 call :asm syscopy || exit /b

Source/Apps/FDU/fdu.asm

@@ -48,7 +48,8 @@
 ;   2020-04-29: v5.5	ADDED SUPPORT FOR ETCHED PIXELS FDC
 ;   2020-12-12: v5.6	UPDATED SMALLZ80 TO NEW I/O ADDRESSES
 ;   2021-03-24: v5.7    ADDED SOME SINGLE-SIDED FORMATS
-;   2021-07-26: v5.8	ADDED SUPPORT MBC FDC
+;   2021-07-26: v5.8	ADDED SUPPORT FOR NHYODYNE (MBC) FDC
+;   2023-12-10: v5.9	ADDED SUPPORT FOR DUODYNE (DUO) FDC
 ;			
 ;_______________________________________________________________________________
 ;
@@ -85,6 +86,7 @@ FDC_SMZ80	.EQU		8
 FDC_DYNO	.EQU		9
 FDC_EPFDC	.EQU		10
 FDC_MBC		.EQU		11
+FDC_DUO		.EQU		12
 ;
 ; FDC MODE
 ;
@@ -219,8 +221,8 @@ INIT5:
 	XOR	A
 	RET
 		
-STR_BANNER	.DB	"Floppy Disk Utility (FDU) v5.8, 26-Jul-2021$"
-STR_BANNER2	.DB	"Copyright (C) 2021, Wayne Warthen, GNU GPL v3","$"
+STR_BANNER	.DB	"Floppy Disk Utility (FDU) v5.9, 10-Dec-2023$"
+STR_BANNER2	.DB	"Copyright (C) 2023, Wayne Warthen, GNU GPL v3","$"
 STR_HBIOS	.DB	" [HBIOS]$"
 STR_UBIOS	.DB	" [UBIOS]$"
 ;
@@ -292,6 +294,7 @@ FDCTBL:	;	LABEL		CONFIG DATA
 	.DW	STR_DYNO,	CFG_DYNO
 	.DW	STR_EPFDC,	CFG_EPFDC
 	.DW	STR_MBC,	CFG_MBC
+	.DW	STR_DUO,	CFG_DUO
 FDCCNT	.EQU	($-FDCTBL)/4	; FD CONTROLLER COUNT
 ;
 ; FDC LABEL STRINGS
@@ -307,7 +310,8 @@ STR_RCWDC	.TEXT	"RC-WDC$"
 STR_SMZ80	.TEXT	"SMZ80$"
 STR_DYNO	.TEXT	"DYNO$"
 STR_EPFDC	.TEXT	"EPFDC$"
-STR_MBC		.TEXT	"MBC$"
+STR_MBC		.TEXT	"NHYODYNE$"
+STR_DUO		.TEXT	"DUODYNE$"
 ;
 ; FDC CONFIGURATION BLOCKS
 ;
@@ -448,7 +452,18 @@ CFG_MBC:
 	.DB	035H	; CONFIGURATION CONTROL REGISTER
 	.DB	036H	; DACK (WHEN READ)
 	.DB	037H	; TERMINAL COUNT (W/ DACK)
-	.DB	0FFH	; NOT USED BY ZETA SBC V2
+	.DB	0FFH	; NOT USED
+	.DB	_PCAT	; MODE=
+;
+CFG_DUO:
+	.DB	080H	; FDC MAIN STATUS REGISTER
+	.DB	081H	; FDC DATA PORT
+	.DB	0FFH	; DATA INPUT REGISTER
+	.DB	086H	; DIGITAL OUTPUT REGISTER (WHEN WRITTEN)
+	.DB	085H	; CONFIGURATION CONTROL REGISTER
+	.DB	086H	; DACK (WHEN READ)
+	.DB	087H	; TERMINAL COUNT (W/ DACK)
+	.DB	0FFH	; NOT USED
 	.DB	_PCAT	; MODE=
 ;
 FDCID	.DB	0			; FDC IDENTIFIER (0 INDEXED)
@@ -470,7 +485,8 @@ FSS_MENU:
 	.TEXT	"  (I) SmallZ80 Expansion\r\n"
 	.TEXT	"  (J) Dyno-Card FDC, D1030\r\n"
 	.TEXT	"  (K) RCBus EPFDC\r\n"
-	.TEXT	"  (L) Multi-Board Computer FDC\r\n"
+	.TEXT	"  (L) Nhyodyne FDC\r\n"
+	.TEXT	"  (M) Duodyne FDC\r\n"
 	.TEXT	"  (X) Exit\r\n"
 	.TEXT	"=== OPTION ===> $\r\n"
 ;	
@@ -1561,6 +1577,7 @@ MD_MAP:
 		.DB	%00000001	; DYNO	POLL
 		.DB	%00000001	; EPFDC	POLL
 		.DB	%00000001	; MBC	POLL
+		.DB	%00000001	; DUO	POLL
 ;
 ; MEDIA DESCRIPTION BLOCK
 ;
@@ -2021,7 +2038,7 @@ FM_DRAW0B:	; ZETA, DIO3
 	LD	A,(FST_DOR)
 	AND	00000010B
 	JR	FM_DRAW1
-FM_DRAW0C:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC, MBC
+FM_DRAW0C:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC, MBC, DUO
 	LD	A,(FST_DOR)
 	AND	11110000B
 	JR	FM_DRAW1
@@ -2174,7 +2191,7 @@ FM_MOTOR0B:	; ZETA, DIO3
 	LD	A,(FST_DOR)
 	AND	00000010B
 	JR	FM_MOTOR1
-FM_MOTOR0C:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC, MBC
+FM_MOTOR0C:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC, MBC, DUO
 	LD	A,(FST_DOR)
 	AND	11110000B
 	JR	FM_MOTOR1
@@ -2913,7 +2930,7 @@ FC_INIT1:	; DIO
 FC_INIT2:	; ZETA, DIO3
 	LD	A,(FCD_DORB)
 	JR	FC_INIT5
-FC_INIT3:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC, MBC
+FC_INIT3:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC, MBC, DUO
 	LD	A,(FCD_DORC)
 	JR	FC_INIT5
 FC_INIT4:	; WDSMC
@@ -2957,7 +2974,7 @@ FC_RESETFDC1:	; ZETA, DIO3, RCSMC
 	POP	AF
 	OUT	(C),A
 	JR	FC_RESETFDC3
-FC_RESETFDC2:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC, MBC
+FC_RESETFDC2:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC, MBC, DUO
 	LD	A,0
 	OUT	(C),A
 	LD	A,(FST_DOR)
@@ -2984,7 +3001,7 @@ FC_PULSETC:
 	;RES	0,A
 	;OUT	(C),A
 	;JR	FC_PULSETC2
-;FC_PULSETC1:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC, MBC
+;FC_PULSETC1:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC, MBC, DUO
 	;LD	C,(IY+CFG_TC)
 	;IN	A,(C)
 	;JR	FC_PULSETC2
@@ -3016,7 +3033,7 @@ FC_MOTORON2:	; ZETA, DIO3
 	LD	HL,FST_DOR		; POINT TO FDC_DOR
 	SET	1,(HL)
 	JR	FC_MOTORON5
-FC_MOTORON3:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC, MBC
+FC_MOTORON3:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC, MBC, DUO
 	LD	HL,FST_DOR		; POINT TO FDC_DOR
 	LD	A,(HL)			; START WITH CURRENT DOR
 	AND	11111100B		; GET RID OF ANY ACTIVE DS BITS
@@ -3080,7 +3097,7 @@ FC_MOTOROFF2:	; ZETA, DIO3
 	LD	HL,FST_DOR		; POINT TO FDC_DOR
 	RES	1,(HL)
 	JR	FC_MOTOROFF5
-FC_MOTOROFF3:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC, MBC
+FC_MOTOROFF3:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC, MBC, DUO
 	LD	HL,FST_DOR		; POINT TO FDC_DOR
 	LD	A,DORC_INIT
 	LD	(HL),A
@@ -3950,7 +3967,7 @@ DORB_BR500	.EQU	10100000B	; 500KBPS
 ;
 DORB_INIT	.EQU	DORB_BR250
 ;
-; *** DIDE/N8/ZETA2/RCWDC/SMZ80/DYNO/EPFDC/MBC ***
+; *** DIDE/N8/ZETA2/RCWDC/SMZ80/DYNO/EPFDC/MBC/DUO ***
 ;
 DORC_INIT	.EQU	00001100B	; SOFT RESET INACTIVE, DMA ENABLED
 ;

Source/Apps/FDU/fdu.doc

@@ -1,14 +1,15 @@
 ================================================================
-Floppy Disk Utility (FDU) v5.3 for RetroBrew Computers 
-Disk IO / Zeta / Dual-IDE / N8 / RCBus / SmallZ80 / Dyno
+Floppy Disk Utility (FDU) v5.9 for RetroBrew Computers 
+Disk IO / Zeta / Dual-IDE / N8 / RCBus / SmallZ80 / Dyno / Nhyodyne / Duodyne
 ================================================================
 
-Updated January 5, 2020
+Updated December 12, 2023
 by Wayne Warthen (wwarthen@gmail.com)
 
 Application to test the hardware functionality of the Floppy 
 Disk Controller (FDC) on the ECB DISK I/O, DISK I/O V3, ZETA 
-SBC, Dual IDE w/ Floppy, or N8 board.
+SBC, Dual IDE w/ Floppy, N8, RCBus, SmallZ80, Dyno, Nhyodyne,
+Duodyne systems.
  
 The intent is to provide a testbed that allows direct testing 
 of all possible media types and modes of access.  The 
@@ -77,9 +78,10 @@ supported:
  - RCBus
  - SmallZ80
  - Dyno
- - MBC
+ - Nhyodyne (MBC)
+ - Duodyne (DUO)
 
-You must be using either a RomWBW or UBA based OS version.
+You must be using either a RomWBW or UNA based OS version.
 
 You must have one of the following floppy disk controllers:
 
@@ -93,7 +95,8 @@ You must have one of the following floppy disk controllers:
  - RCBus Scott Baker WDC-based Floppy Module
  - SmallZ80 FDC
  - Dyno FDC
- - MBC FDC
+ - Nhyodyne (MBC) FDC
+ - Duodyne (DUO) FDC
  
 Finally, you will need a floppy drive connected via an 
 appropriate cable:
@@ -165,8 +168,11 @@ hardwired I/O ranges are assumed in the code.
 Dyno does not have any relevant jumper settings.  The 
 hardwired I/O ranges are assumed in the code.
 
-The MBC FDC is expected to be strapped to use neither INT nor NMI.  It
-is also not expected to use DMA.
+The Nhyodyne (MBC) FDC is expected to be strapped to use neither INT
+nor NMI.  It is also not expected to use DMA.
+
+The Duodyne (DUO) FDC is expected to be strapped to use neither INT
+nor NMI.  It is also not expected to use DMA.
 
 Modes of Operation
 ------------------
@@ -533,4 +539,7 @@ WW 3/24/2021: v5.7
   - Added support for a few single-sided formats
 
 WW 7/26/2021: v5.8
-  - Added support for MBC FDC
+  - Added support for Nhyodyne (MBC) FDC
+
+WW 12/10/2023: v5.9
+  - Added support for Duodyne (DUO) FDC

Source/Apps/Test/ps2info/ps2info.asm

@@ -7,20 +7,24 @@
 ; keyboard, and mouse.
 ;
 ; WBW 2022-03-28: Add menu driven port selection
-;                 Add support for RHYOPHYRE
+;                 Add support for Rhyophyre
 ; WBW 2022-04-01: Add menu for test functions
 ; WBW 2022-04-02: Fix prtchr register saving/recovery
+; WBW 2023-10-19: Add support for Duodyne
 ;
 ;=======================================================================
 ;
 ; PS/2 Keyboard/Mouse controller port addresses (adjust as needed)
 ;
-; MBC:
+; Nhyodyne:
 iocmd_mbc	.equ	$E3	; PS/2 controller command port address
 iodat_mbc	.equ	$E2	; PS/2 controller data port address
-; RPH:
+; Rhyophyre:
 iocmd_rph	.equ	$8D	; PS/2 controller command port address
 iodat_rph	.equ	$8C	; PS/2 controller data port address
+; Duodyne:
+iocmd_duo	.equ	$4D	; PS/2 controller command port address
+iodat_duo	.equ	$4C	; PS/2 controller data port address
 ;
 cpumhz	.equ	8	; for time delay calculations (not critical)
 ;
@@ -77,10 +81,12 @@ setup1:
 	jr	z,setup1
 	call	upcase
 	call	prtchr
-	cp	'1'			; MBC
+	cp	'1'			; Nhyodyne
 	jr	z,setup_mbc
-	cp	'2'			; RHYOPHYRE
+	cp	'2'			; Rhyophyre
 	jr	z,setup_rph
+	cp	'3'			; Duodyne
+	jr	z,setup_duo
 	cp	'X'
 	jr	z,exit
 	jr	setup
@@ -101,6 +107,14 @@ setup_rph:
 	ld	de,str_rph
 	jr	setup2
 ;
+setup_duo:
+	ld	a,iocmd_duo
+	ld	(iocmd),a
+	ld	a,iodat_duo
+	ld	(iodat),a
+	ld	de,str_duo
+	jr	setup2
+;
 setup2:
 	call	prtstr
 	call	crlf2
@@ -181,6 +195,12 @@ test_kbd:
 ;
 	call	ctlr_test
 	jr	nz,test_kbd_fail
+;
+	ld	a,$20			; kbd enabled, mse disabled, no ints
+	call	ctlr_setup
+	jr	nz,test_kbd_fail
+;
+	call	ctlr_flush
 ;
 	call	test_kbd_basic
 	jr	nz,test_kbd_fail
@@ -228,9 +248,13 @@ test_mse:
 	ld	a,$10			; kbd disabled, mse enabled, no ints
 	call	ctlr_setup
 	jr	nz,test_mse_fail
+;
+	call	ctlr_flush
 ;
 	call	mse_reset
 	jr	nz,test_mse_fail
+;
+	call	ctlr_flush
 ;
 	call	mse_ident
 	jr	nz,test_mse_fail
@@ -262,15 +286,21 @@ test_kbdmse:
 	ld	a,$00			; kbd enabled, mse enabled, no ints
 	call	ctlr_setup
 	jr	nz,test_kbdmse_fail
+;
+	call	ctlr_flush
 ;
 	call	kbd_reset
 	jr	nz,test_kbdmse_fail
+;
+	call	ctlr_flush
 ;
 	ld	a,2
 	call	kbd_setsc
 ;
 	call	mse_reset
 	jr	nz,test_kbdmse_fail
+;
+	call	ctlr_flush
 ;
 	call	mse_stream
 	jr	nz,test_kbdmse_fail
@@ -290,15 +320,13 @@ test_kbdmse_fail:
 ; inventory the supported scan code sets.
 ;
 test_kbd_basic:
-	ld	a,$20			; Xlat off for this checking
-	call	ctlr_setup
-	ret	nz
-;
 	call	kbd_reset
 	ret	nz
+;
+	call	ctlr_flush
 ;
 	call	kbd_ident
-	;ret	nz
+	ret	nz
 ;
 	ld	b,3			; Loop control, 3 scan code sets
 	ld	c,1			; Current scan code number
@@ -436,6 +464,19 @@ ctlr_setup:
 	xor	a
 	ret
 ;
+; Flush incoming data buffer
+;
+ctlr_flush:
+	call	crlf2
+	ld	de,str_ctlr_flush
+	call	prtstr
+ctlr_flush1:
+	call	delay			; small delay
+	call	check_read		; data pending?
+	ret	nz			; return if nothing there
+	call	get_data_dbg		; get and discard byte
+	jr	ctlr_flush1		; loop
+;
 ; Perform a keyboard reset
 ;
 kbd_reset:
@@ -612,13 +653,17 @@ mse_reset:
 	call	crlf2
 	ld	de,str_mse_reset
 	call	prtstr
-	ld	a,$f2			; Identify mouse command
+	ld	a,$ff			; Identify mouse command
 	call	put_data_mse_dbg
 	jp	c,err_ctlr_to		; handle controller error
 	call	get_data_dbg
 	jp	c,err_ctlr_to		; handle controller error
 	cp	$fa			; Is it an ack as expected?
 	jp	nz,err_mse_reset
+	call	get_data_dbg
+	jp	c,err_ctlr_to		; handle controller error
+	cp	$aa			; Success?
+	jp	nz,err_mse_reset
 	call	crlf
 	ld	de,str_mse_reset_ok
 	call	prtstr
@@ -634,18 +679,61 @@ mse_ident:
 	ld	a,$f2			; Identify mouse command
 	call	put_data_mse_dbg
 	jp	c,err_ctlr_to		; handle controller error
+mse_ident0:
 	call	get_data_dbg
 	jp	c,err_ctlr_to		; handle controller error
+
+	;cp	$00			; extraneous?
+	;jr	z,mse_ident0		; ignore it, get another
+
 	cp	$fa			; Is it an ack as expected?
 	jp	nz,err_mse_ident
-	call	get_data_dbg
-	jp	c,err_ctlr_to		; handle controller error
+	; Now we need to receive 0-2 bytes.  There is no way to know
+	; how many are coming, so we receive bytes until there is a
+	; timeout error.  Timeout is shortened here so that we don't
+	; have to wait seconds for the routine to complete normally.
+	; A short timeout is more than sufficient here.
+	ld	ix,workbuf
+	ld	a,(timeout)		; save current timeout
 	push	af
+	ld	a,stimout		; set a short timeout
+	ld	(timeout),a
+	ld	b,8			; buf max
+	ld	c,0			; buf len
+mse_ident1:
+	push	bc
+	call	get_data_dbg
+	pop	bc
+	jr	c,mse_ident2
+	ld	(ix),a
+	inc	ix
+	inc	c
+	djnz	mse_ident1
+mse_ident2:
+	pop	af			; restore original timeout
+	ld	(timeout),a
 	call	crlf
 	ld	de,str_mse_ident_disp
 	call	prtstr
-	pop	af
-	call	prtdecb
+	ld	a,'['
+	call	prtchr
+	ld	ix,workbuf
+	ld	a,c			; bytes to print
+	or	a			; check for zero
+	jr	z,mse_ident4		; handle zero
+	ld	b,a			; setup loop counter
+	jr	mse_ident3a
+mse_ident3:
+	ld	a,','
+	call	prtchr
+mse_ident3a:
+	ld	a,(ix)
+	call	prthex
+	inc	ix
+	djnz	mse_ident3
+mse_ident4:
+	ld	a,']'
+	call	prtchr
 	xor	a
 	ret
 ;
@@ -658,8 +746,13 @@ mse_stream:
 	ld	a,$f4			; Stream packets cmd
 	call	put_data_mse_dbg
 	jp	c,err_ctlr_to		; handle controller error
+mse_stream0:
 	call	get_data_dbg
 	jp	c,err_ctlr_to		; handle controller error
+
+	;cp	$00			; extraneous?
+	;jr	z,mse_stream0		; ignore it, get another
+
 	cp	$FA			; Is it an ack as expected?
 	jp	nz,err_mse_stream
 	xor	a
@@ -1344,14 +1437,16 @@ delay1:
 ; Constants
 ;=======================================================================
 ;
-str_banner		.db	"PS/2 Keyboard/Mouse Information v0.6a, 2-Apr-2022",0
+str_banner		.db	"PS/2 Keyboard/Mouse Information v0.8, 6-Nov-2023",0
 str_hwmenu		.db	"PS/2 Controller Port Options:\r\n\r\n"
-			.db	"  1 - MBC\r\n"
-			.db	"  2 - RHYOPHYRE\r\n"
+			.db	"  1 - Nhyodyne\r\n"
+			.db	"  2 - Rhyophyre\r\n"
+			.db	"  3 - Duodyne\r\n"
 			.db	"  X - Exit Application\r\n"
 			.db	"\r\nSelection? ",0
-str_mbc			.db	"MBC",0
-str_rph			.db	"RHYOPHYRE",0
+str_mbc			.db	"Nhyodyne",0
+str_rph			.db	"Rhyophyre",0
+str_duo			.db	"Duodyne",0
 str_menu		.db	"PS/2 Testing Options:\r\n\r\n"
 			.db	"  C - Test PS/2 Controller\r\n"
 			.db	"  K - Test PS/2 Keyboard\r\n"
@@ -1382,6 +1477,7 @@ str_trans_off		.db	"***** Testing Keyboard with Scan Code Translation DISABLED *
 str_trans_on		.db	"***** Testing Keyboard with Scan Code Translation ENABLED *****",0
 str_basic_mse		.db	"***** Basic Mouse Tests *****",0
 str_kbdmse			.db	"***** Test All Devices Combined *****",0
+str_ctlr_flush		.db	"Flushing controller input buffer",0
 str_kbd_reset		.db	"Attempting Keyboard Reset",0
 str_kbd_reset_ok	.db	"Keyboard Reset OK",0
 str_err_kbd_reset	.db	"Keyboard Reset Failed",0

Source/BPBIOS/Build.cmd

@@ -3,8 +3,8 @@ setlocal
 
 pushd ZCPR33 && call Build || exit /b & popd
 
-set PATH=%PATH%;..\..\Tools\zxcc;..\..\Tools\cpmtools;
-
+set TOOLS=..\..\Tools
+set PATH=%PATH%;%TOOLS%\zxcc;%TOOLS%\cpmtools;
 set CPMDIR80=%TOOLS%/cpm/
 
 call :makebp 33
@@ -48,7 +48,8 @@ if exist bp%VER%.prn del bp%VER%.prn || exit /b
 ren bpbio-ww.prn bp%VER%.prn || exit /b
 if exist bp%VER%.err del bp%VER%.err || exit /b
 ren bpbio-ww.err bp%VER%.err || exit /b
-copy bpbio-ww.rel bp%VER%.rel || exit /b
+if exist bp%VER%.rel del bp%VER%.rel || exit /b
+ren bpbio-ww.rel bp%VER%.rel || exit /b
 
 rem pause
 

Source/BPBIOS/Makefile

@@ -1,44 +1,37 @@
 VERSIONS = \
-	33t 33tbnk \
-	33n 33nbnk \
-	34t 34tbnk \
-	34n 34nbnk \
-	41tbnk 41nbnk
+	33 33bnk \
+	33 33bnk \
+	34 34bnk \
+	34 34bnk \
+	41bnk
 
-HD0IMG = ../../Binary/hd_bp.img
 IMGFILES = $(foreach ver,$(VERSIONS),bp$(ver).img)
 DISTFILES = *.zex *.rel myterm.z3t
 
-OTHERS = zcpr33n.rel zcpr33t.rel \
-	bpbio-ww.rel bpsys.dat bpsys.bak bpbio-ww.err def-ww.lib *.img
+OTHERS = zcpr33.rel bp*.prn bp*.rel \
+	bpbio-ww.rel bpsys.dat bpsys.bak bpbio-ww.err def-ww.lib bp*.img
 
 TOOLS = ../../Tools
 
 SUBDIRS = ZCPR33
 include $(TOOLS)/Makefile.inc
 
-$(HD0IMG): $(IMGFILES)
-	if [ -f $(HD0IMG) ] ; then \
-		for f in $(IMGFILES) $(DISTFILES) ; do \
-			$(BINDIR)/cpmrm -f wbw_hd0 $(HD0IMG) 0:$$f ; \
-		done ; \
-		$(CPMCP) -f wbw_hd0 $(HD0IMG) $(IMGFILES) $(DISTFILES) 0: ; \
-	fi
-
-zcpr33n.rel zcpr33t.rel:
+zcpr33.rel:
 	(cd ZCPR33 ; make)
 
-all:: $(HD0IMG)
+all:: $(IMGFILES)
 
-clean::
-	@rm -f $(HD0IMG)
+# clean::
+# 	$(MAKE) --directory ZCPR3 clean
 
-%.img: zcpr33n.rel zcpr33t.rel
+%.img: zcpr33.rel
 	$(eval VER := $(subst .img,,$(subst bp,,$@)))
 	cp def-ww-z$(VER).lib def-ww.lib
 	rm -f bpbio-ww.rel
 	$(ZXCC) ZMAC -BPBIO-WW -/P
 	mv bpbio-ww.prn bp$(VER).prn
+	if [ -f bpbio-ww.err ] ; then mv bpbio-ww.err bp$(VER).err; fi
+	mv bpbio-ww.rel bp$(VER).rel
 	cp bp$(VER).dat bpsys.dat
 	$(ZXCC) ./bpbuild.com -bpsys.dat 0 < bpbld1.rsp
 	cp bpsys.img bpsys.dat

Source/BPBIOS/ZCPR33/Build.cmd

@@ -1,8 +1,8 @@
 @echo off
 setlocal
 
-set PATH=%PATH%;..\..\..\Tools\zxcc;..\..\..\Tools\cpmtools;
-
+set TOOLS=..\..\..\Tools
+set PATH=%PATH%;%TOOLS%\zxcc;%TOOLS%\cpmtools;
 set CPMDIR80=%TOOLS%/cpm/
 
 copy ..\z3base.lib . || exit /b

Source/BPBIOS/ZCPR33/Makefile

@@ -1,5 +1,5 @@
-OBJECTS = zcpr33n.rel zcpr33t.rel
-OTHERS = z3basen.lib z3baset.lib
+OBJECTS = zcpr33.rel
+OTHERS = z3base.lib *.prn *.rel
 TOOLS = ../../../Tools
 DEST = ..
 
@@ -7,12 +7,7 @@ include $(TOOLS)/Makefile.inc
 
 DIFFPATH = $(DIFFTO)/Source/BPBIOS
 
-zcpr33t.rel: ../z3baset.lib
-	cp ../z3baset.lib z3baset.lib
-	$(ZXCC) ZMAC -zcpr33t.z80 -/P
-	rm z3baset.lib
-
-zcpr33n.rel: ../z3basen.lib
-	cp ../z3basen.lib z3basen.lib
-	$(ZXCC) ZMAC -zcpr33n.z80 -/P
-	rm z3basen.lib
+zcpr33.rel: ../z3base.lib
+	cp ../z3base.lib z3base.lib
+	$(ZXCC) ZMAC -zcpr33.z80 -/P
+	rm z3base.lib

Source/BPBIOS/cboot-ww.z80

@@ -102,6 +102,9 @@ CBOOT:
 ; BPCNFG to configure a generic IMG file for specific Hard Drive Partitions.
 
 CBOOT0:
+	LD	BC,HBF_SYSRES_INT	; HB Func: Internal Reset
+	CALL	HBX_INVOKE		; Do it
+
 	LD	HL,BRAME	; Get end of banked RAM
 	LD	(HISAV),HL	;   and save for later use
 	  IF  HARDDSK

Source/BPBIOS/deblock.z80

@@ -268,16 +268,15 @@ MATCH:	LD	A,(SECMSK)	; Get the sector mask
 ;
 ; Modified to use HBIOS host buffer
 ;
-	; HSTBUF is always in HBIOS bank where I/O is done
-	LD	A,(TPABNK)	; TPA BANK
-	DEC	A		; HBIOS bank is one below
-	LD	C,A
+	; HSTBUF is always in HBIOS bank where I/O is actually done
+	LD	A,(HB_BNKBIOS)	; HBIOS bank id
+	LD	C,A		; Set Read Source Bank
 	  IF  BANKED
-	LD	A,(DMABNK)	; Set Read Destination Bank
+	LD	A,(DMABNK)	; Read Destination Bank
 	  ELSE
-	LD	A,(TPABNK)	; Set Read Destination Bank
+	LD	A,(TPABNK)	; Read Destination Bank
 	  ENDIF
-	LD	B,A
+	LD	B,A		; Set Read Destination Bank
 	LD	A,(READOP)	; Direction?
 	OR	A
 	JR	NZ,OKBNKS	; ..jump if read

Source/BPBIOS/def-ww-z33.lib

@@ -133,8 +133,8 @@ BNK1	EQU	BID_COM		;   Second TPA Bank (Common Bank)	48000H
 BNK2	EQU	BID_SYS		; System Bank (BIOS, DOS, CPR)		50000H
 BNKU	EQU	00H		; User Area Bank			58000H
 				; (set to 0 to disable)
-BNK3	EQU	BID_RAMD	; First Bank for RAM disk		60000H
-BNKM	EQU	BID_RAMM	; Maximum Bank #			F8000H
+BNK3	EQU	BID_BUF		; First Bank for RAM disk		60000H
+BNKM	EQU	BID_BUF		; Maximum Bank #			F8000H
 
 	  IF  NO	; REMOVE CODE - NOT NEEDED WITH HBIOS makes a
        			; nice resource for Z180 programing in general

Source/BPBIOS/def-ww-z33bnk.lib

@@ -133,8 +133,8 @@ BNK1	EQU	BID_COM		;   Second TPA Bank (Common Bank)	48000H
 BNK2	EQU	BID_SYS		; System Bank (BIOS, DOS, CPR)		50000H
 BNKU	EQU	00H		; User Area Bank			58000H
 				; (set to 0 to disable)
-BNK3	EQU	BID_RAMD	; First Bank for RAM disk		60000H
-BNKM	EQU	BID_RAMM	; Maximum Bank #			F8000H
+BNK3	EQU	BID_BUF		; First Bank for RAM disk		60000H
+BNKM	EQU	BID_BUF		; Maximum Bank #			F8000H
 
 	  IF  NO	; REMOVE CODE - NOT NEEDED WITH HBIOS makes a
        			; nice resource for Z180 programing in general

Source/BPBIOS/def-ww-z34.lib

@@ -133,8 +133,8 @@ BNK1	EQU	BID_COM		;   Second TPA Bank (Common Bank)	48000H
 BNK2	EQU	BID_SYS		; System Bank (BIOS, DOS, CPR)		50000H
 BNKU	EQU	00H		; User Area Bank			58000H
 				; (set to 0 to disable)
-BNK3	EQU	BID_RAMD	; First Bank for RAM disk		60000H
-BNKM	EQU	BID_RAMM	; Maximum Bank #			F8000H
+BNK3	EQU	BID_BUF		; First Bank for RAM disk		60000H
+BNKM	EQU	BID_BUF		; Maximum Bank #			F8000H
 
 	  IF  NO	; REMOVE CODE - NOT NEEDED WITH HBIOS makes a
        			; nice resource for Z180 programing in general

Source/BPBIOS/def-ww-z34bnk.lib

@@ -133,8 +133,8 @@ BNK1	EQU	BID_COM		;   Second TPA Bank (Common Bank)	48000H
 BNK2	EQU	BID_SYS		; System Bank (BIOS, DOS, CPR)		50000H
 BNKU	EQU	00H		; User Area Bank			58000H
 				; (set to 0 to disable)
-BNK3	EQU	BID_RAMD	; First Bank for RAM disk		60000H
-BNKM	EQU	BID_RAMM	; Maximum Bank #			F8000H
+BNK3	EQU	BID_BUF		; First Bank for RAM disk		60000H
+BNKM	EQU	BID_BUF		; Maximum Bank #			F8000H
 
 	  IF  NO	; REMOVE CODE - NOT NEEDED WITH HBIOS makes a
        			; nice resource for Z180 programing in general

Source/BPBIOS/def-ww-z41bnk.lib

@@ -133,8 +133,8 @@ BNK1	EQU	BID_COM		;   Second TPA Bank (Common Bank)	48000H
 BNK2	EQU	BID_SYS		; System Bank (BIOS, DOS, CPR)		50000H
 BNKU	EQU	00H		; User Area Bank			58000H
 				; (set to 0 to disable)
-BNK3	EQU	BID_RAMD	; First Bank for RAM disk		60000H
-BNKM	EQU	BID_RAMM	; Maximum Bank #			F8000H
+BNK3	EQU	BID_BUF		; First Bank for RAM disk		60000H
+BNKM	EQU	BID_BUF		; Maximum Bank #			F8000H
 
 	  IF  NO	; REMOVE CODE - NOT NEEDED WITH HBIOS makes a
        			; nice resource for Z180 programing in general

Source/BPBIOS/dpbhd-ww.lib

@@ -46,7 +46,7 @@
 ; NOTE: No Skew Table needed since Hard Disk Format is locked w/No Skew 
 
 ;.....
-; Currently, BPBIOS supports 2 memory drive devices and 3 phyical hard 
+; Currently, BPBIOS supports 2 memory drive devices and 3 physical hard 
 ;	drive like devices.  BPBIOS can support seven but unfortunately
 ;	BPCNFG only supports 3 hard drive like devices and the source 
 ;	code is not available, so menu 4 is meaningless.  Devices 
@@ -64,26 +64,22 @@
 ;
 ;	Starting with ver 2.8 of HBIOS, devices are discovered at boot
 ;	time and assigned device numbers.  Since devices are tested in
-;	a certain order, the device numbers are somewhat predicably 
+;	a certain order, the device numbers are somewhat predictably 
 ;	assigned.  Memory drives are discovered first.  IDE drives are 
 ;	discovered next so that IDE Hard drives including CF cards are 
 ;	assigned device 2 and device 3 if a slave drive is supported by
 ;	the interface.  Next comes the SD drive and is assigned device 3
 ;	or 4 depending on the whether there is an ide slave drive.
-;	USB drive is assigned device 4 or 5 .  For SIMH HDSK0 is device 0
+;	USB drive is assigned device 4 or 5.  For SIMH HDSK0 is device 0
 ;	and HDSK1 is device 1.  Memory drives are now handled as LBA
 ;	devices, ie like hard drives.
 ;
 ; The following non-memory drive capacities and configurations used for 
-; the SIMH, SD and IDE drives: Slice geometry is 256, 512 byte sectors, 
-; 1 head per track and 1 with one reserved track, a block size of 4096 
-; bytes with 512 directory entries.  An equivalent geometry is 16 
-; sectors and 16 heads per track.  Internally BPBIOS uses a uniform 
-; logical organization with 64 logical records per logical track.  
-; Thus there are 16 logical tracks per physical track with 1040 
-; logical (65 physical) tracks per slice.  If all partitions are not 
-; physically present, the missing partitions can be disabled in the 
-; BPBCNFG configuration file or by hand.  Note that HBIOS uses LBA, 
+; the SIMH, SD and IDE drives: Track geometry is 16 512 byte sectors.
+; A slice is exactly 64 tracks, with 1 of the 64 tracks as a system
+; track.  There are 1024 directory entries per slice. If all partitions
+; are not physically present, the missing partitions can be disabled in
+; the BPBCNFG configuration file or by hand.  Note that HBIOS uses LBA, 
 ; Logical Block Addressing, for non-floppy drives.
 ;
 ; For SBC V1,2, ZETA, MARK IV and N8, the following non-memory partitions 
@@ -94,26 +90,26 @@
 ;	partition	Size	Blocks	Block 	Offset in
 ;			MByte		Size	logical tracks
 ;====================================================================
-;	   C		 8	 2048	4096	1*16          = 16
-;	   D		 8	 2048	4096	(1+65)*16     = 1056
-;	   E		 8	 2048	4096	(1+2*65)*16   = 2096
-;	   F		 8	 2048	4096	(1+3*65)*16   = 3136
-;	   G		 8	 2048	4096	(1+4*65)*16   = 4176
-;	   H		 8	 2048	4096	(1+5*65)*16   = 5216
-;	   I		 8	 2048	4096	(1+6*65)*16   = 6256
-;	   J		 8	 2048	4096	(1+7*65)*16   = 7296
+;	   C		 8	 2044	4096	128+(1024*0)+2 = 130
+;	   D		 8	 2044	4096	128+(1024*1)+2 = 1154
+;	   E		 8	 2044	4096	128+(1024*2)+2 = 2178
+;	   F		 8	 2044	4096	128+(1024*3)+2 = 3202
+;	   G		 8	 2044	4096	128+(1024*4)+2 = 4226
+;	   H		 8	 2044	4096	128+(1024*5)+2 = 5250
+;	   I		 8	 2044	4096	128+(1024*6)+2 = 6274
+;	   J		 8	 2044	4096	128+(1024*7)+2 = 7298
 ;
 ; These are capacities and configurations used for SD card:
 ;
 ;	partition	Size	Blocks	Block 	Offset
 ;			MByte		Size	logical tracks
 ;====================================================================
-;	   K		 8	 2048	4096	1*16          = 16
-;	   L		 8	 2048	4096	(1+65)*16     = 1056
-;	   M		 8	 2048	4096	(1+2*65)*16   = 2096
-;	   N		 8	 2048	4096	(1+3*65)*16   = 3136
+;	   K		 8	 2044	4096	128+(1024*0)+2 = 130
+;	   L		 8	 2044	4096	128+(1024*1)+2 = 1154
+;	   M		 8	 2044	4096	128+(1024*2)+2 = 2178
+;	   N		 8	 2044	4096	128+(1024*3)+2 = 3202
 ;
-; RAM drive is paritition A while ROM drive is partition B. 
+; RAM drive is partition A while ROM drive is partition B. 
 ;
 ; For example, a typical Memory drive configuration is: 
 ;
@@ -199,17 +195,17 @@ DPBROM:	DEFW	64		; Sectors/Track
 				;  even though real layout is 256 physical
 				;  sectors per track
 	DEFB	0		; Physical tracks/side (No Meaning in HD)
-HSIZ0	EQU	2048		; # of blocks in first Partition  (1024 trks)
+HSIZ0	EQU	2048 - 4	; # of blocks in first Partition  (1022 trks)
 				;	
 DPB50:	DEFW	64		; Sctrs/Trk	
 	DEFB	5		; Blk Shf Fctr	
 	DEFB	31		; Block Mask	
 	DEFB	1		; Extent Mask	
-	DEFW	HSIZ0-1		; Disk Size-1	
-	DEFW	511		; Dir Max-1 - 4 blocks	
-	DEFB	0F0H,0		; Alloc 0,1 - 4 blocks	
+	DEFW	HSIZ0-1		; Disk Size-1
+	DEFW	1024-1		; Dir Max-1
+	DEFB	0FFH,0		; Alloc 0,1
 	DEFW	0		; Check Size	
-	DEFW	16		; Trk Offset	
+	DEFW	128+(1024*0)+2	; Trk Offset
 	  ENDIF
 ;
 ;.....
@@ -226,17 +222,17 @@ DPB50:	DEFW	64		; Sctrs/Trk
 				; sectors per track
 	DEFB	0		; Physical tracks/side (No Meaning in HD)
 
-HSIZ1	EQU	2048		; # of blocks in Second Partition  (1024 trks)
+HSIZ1	EQU	2048 - 4	; # of blocks in Second Partition  (1022 trks)
 				;		
 DPB51:	DEFW	64		; Scts/Trk	
 	DEFB	5		; Blk Shf Fctr
 	DEFB	31		; Block Mask	
 	DEFB	1		; Extent Mask	
 	DEFW	HSIZ1-1		; Disk Size-1	
-	DEFW	511		; Dir Max-1	4 blocks
-	DEFB	0F0H,0		; Alloc 0,1	
+	DEFW	1024-1		; Dir Max-1
+	DEFB	0FFH,0		; Alloc 0,1
 	DEFW	0		; Check size	
-	DEFW	(1+65)*16	; Track offset	1056
+	DEFW	128+(1024*1)+2	; Trk Offset
 	  ENDIF
 ;
 ;.....
@@ -253,21 +249,21 @@ DPB51:	DEFW	64		; Scts/Trk
 				; sectors per track
 	DEFB	0		; Physical tracks/side (No Meaning in HD)
 
-HSIZ2	EQU	2048		; # of blocks in third Partition (1024 tracks)
+HSIZ2	EQU	2048 - 4	; # of blocks in Second Partition  (1022 trks)
 				;	
 DPB52:	DEFW	64		; Scts/Trk	
 	DEFB	5		; Blk Shf Fctr	
 	DEFB	31		; Block Mask	
 	DEFB	1		; Extent Mask	
 	DEFW	HSIZ2-1		; Disk Size-1	
-	DEFW	511		; Dir Max-1	4 blocks
-	DEFB	0F0H,0		; Alloc 0,1	
+	DEFW	1024-1		; Dir Max-1
+	DEFB	0FFH,0		; Alloc 0,1
 	DEFW	0		; Check size	
-	DEFW	(1+2*65)*16	; Track offset = 2096
+	DEFW	128+(1024*2)+2	; Trk Offset
 	  ENDIF
 ;
 ;.....
-; Partition F.  HBIOS Disk 0, Slice 4
+; Partition F.  HBIOS Disk 0, Slice 3
 
 	  IF  DRV_F
 	DEFB	'HBDSK0:3 ','F'+80H ; Id - 10 bytes
@@ -280,17 +276,17 @@ DPB52:	DEFW	64		; Scts/Trk
 				; sectors per track
 	DEFB	0		; Physical tracks/side (No Meaning in HD)
 
-HSIZ3	EQU	2048		; # of blocks in Fourth Partition (1024 tracks)
+HSIZ3	EQU	2048 - 4	; # of blocks in Second Partition  (1022 trks)
 				;	
 DPB53:	DEFW	64		; Scts/Trk	
 	DEFB	5		; Blk Shf Fctr	
 	DEFB	31		; Block Mask	
 	DEFB	1		; Extent Mask	
 	DEFW	HSIZ3-1		; Disk Size-1	
-	DEFW	511		; Dir Max-1	4 blocks
-	DEFB	0F0H,0		; Alloc 0,1	
+	DEFW	1024-1		; Dir Max-1
+	DEFB	0FFH,0		; Alloc 0,1
 	DEFW	0		; Check size	
-	DEFW	(1+3*65)*16	; Track offset = 3136
+	DEFW	128+(1024*3)+2	; Trk Offset
 	  ENDIF
 ;	
 ;.....
@@ -307,17 +303,17 @@ DPB53:	DEFW	64		; Scts/Trk
 				; sectors per track
 	DEFB	0		; Physical tracks/side (No Meaning in HD)
 
-HSIZ4	EQU	2048		; # of blocks in first Partition  (1024 trks)
+HSIZ4	EQU	2048 - 4	; # of blocks in Second Partition  (1022 trks)
 				;	
 DPB54:	DEFW	64		; Sctrs/Trk	
 	DEFB	5		; Blk Shf Fctr
 	DEFB	31		; Block Mask
 	DEFB	1		; Extent Mask
 	DEFW	HSIZ4-1		; Disk Size - 1
-	DEFW	511		; Dir Max-1	4 blocks
-	DEFB	0F0H,0		; Alloc 0,1	
+	DEFW	1024-1		; Dir Max-1
+	DEFB	0FFH,0		; Alloc 0,1
 	DEFW	0		; Check size	
-	DEFW	(1+4*65)*16	; Track offset = 16
+	DEFW	128+(1024*4)+2	; Trk Offset
 	  ENDIF
 ;
 ;.....
@@ -334,17 +330,17 @@ DPB54:	DEFW	64		; Sctrs/Trk
 				;   sectors per track
 	DEFB	0		; Physical tracks/side (No Meaning in HD)
 
-HSIZ5	EQU	2048		; # of blocks in Second Partition  (1024 trks)
+HSIZ5	EQU	2048 - 4	; # of blocks in Second Partition  (1022 trks)
 				;		
 DPB55:	DEFW	64		; Sctrs/Trk - actually 256	
 	DEFB	5		; Blk Shf Fctr	
 	DEFB	31		; Block Mask	
 	DEFB	1		; Extent Mask	
 	DEFW	HSIZ5-1		; Disk Size-1	
-	DEFW	511		; Dir Max-1	
-	DEFB	0F0H,0		; Alloc 0,1 - 4 blocks	
+	DEFW	1024-1		; Dir Max-1
+	DEFB	0FFH,0		; Alloc 0,1
 	DEFW	0		; Check Size	
-	DEFW	(1+5*65)*16	; Trk Offset = 1056
+	DEFW	128+(1024*5)+2	; Trk Offset
 	  ENDIF
 ;
 ;.....
@@ -361,17 +357,17 @@ DPB55:	DEFW	64		; Sctrs/Trk - actually 256
 				; sectors per track
 	DEFB	0		; Physical tracks/side (No Meaning in HD)
 
-HSIZ6	EQU	2048		; # of blocks in third Partition (1024 tracks)
+HSIZ6	EQU	2048 - 4	; # of blocks in Second Partition  (1022 trks)
 				;	
 DPB56:	DEFW	64		; Scts/Trk	
 	DEFB	5		; Blk Shf Fctr	
 	DEFB	31		; Block Mask	
 	DEFB	1		; Extent Mask	
 	DEFW	HSIZ6-1		; Disk Size-1	
-	DEFW	511		; Dir Max-1	4 blocks
-	DEFB	0F0H,0		; Alloc 0,1	
+	DEFW	1024-1		; Dir Max-1
+	DEFB	0FFH,0		; Alloc 0,1
 	DEFW	0		; Check size	
-	DEFW	(1+6*65)*16	; Track offset	= 2096
+	DEFW	128+(1024*6)+2	; Trk Offset
 	  ENDIF
 
 ;.....
@@ -388,17 +384,17 @@ DPB56:	DEFW	64		; Scts/Trk
 				; sectors per track
 	DEFB	0		; Physical tracks/side (No Meaning in HD)
 
-HSIZ7	EQU	2048		; # of blocks in Fourth Partition (1024 tracks)
+HSIZ7	EQU	2048 - 4	; # of blocks in Second Partition  (1022 trks)
 				;
 DPB57:	DEFW	64		; Scts/Trk	
 	DEFB	5		; Blk Shf Fctr	
 	DEFB	31		; Block Mask	
 	DEFB	1		; Extent Mask	
 	DEFW	HSIZ7-1		; Disk Size-1	
-	DEFW	511		; Dir Max-1	4 blocks
-	DEFB	0F0H,0		; Alloc 0,1	
+	DEFW	1024-1		; Dir Max-1
+	DEFB	0FFH,0		; Alloc 0,1
 	DEFW	0		; Check size	
-	DEFW	(1+7*65)*16	; Track offset = 3136
+	DEFW	128+(1024*7)+2	; Trk Offset
 	  ENDIF
 ;
 ;.....
@@ -414,17 +410,18 @@ DPB57:	DEFW	64		; Scts/Trk
 				;  even though real layout is 256 physical
 				;  sectors per track
 	DEFB	0		; Physical tracks/side (No Meaning in HD)
-HSIZ8	EQU	2048		; # of blocks in first Partition  (1024 trks)
+
+HSIZ8	EQU	2048 - 4	; # of blocks in Second Partition  (1022 trks)
 				;	
 DPB58:	DEFW	64		; Sctrs/Trk	
 	DEFB	5		; Blk Shf Fctr	
 	DEFB	31		; Block Mask	
 	DEFB	1		; Extent Mask	
 	DEFW	HSIZ8-1		; Disk Size-1	
-	DEFW	511		; Dir Max-1 - 4 blocks	
-	DEFB	0F0H,0		; Alloc 0,1 - 4 blocks	
+	DEFW	1024-1		; Dir Max-1
+	DEFB	0FFH,0		; Alloc 0,1
 	DEFW	0		; Check Size	
-	DEFW	16		; Trk Offset	
+	DEFW	128+(1024*0)+2	; Trk Offset
 	  ENDIF
 ;
 ;.....
@@ -441,17 +438,17 @@ DPB58:	DEFW	64		; Sctrs/Trk
 				; sectors per track
 	DEFB	0		; Physical tracks/side (No Meaning in HD)
 
-HSIZ9	EQU	2048		; # of blocks in Second Partition  (1024 trks)
+HSIZ9	EQU	2048 - 4	; # of blocks in Second Partition  (1022 trks)
 				;		
 DPB59:	DEFW	64		; Scts/Trk	
 	DEFB	5		; Blk Shf Fctr
 	DEFB	31		; Block Mask	
 	DEFB	1		; Extent Mask	
 	DEFW	HSIZ9-1		; Disk Size-1	
-	DEFW	511		; Dir Max-1	4 blocks
-	DEFB	0F0H,0		; Alloc 0,1	
+	DEFW	1024-1		; Dir Max-1
+	DEFB	0FFH,0		; Alloc 0,1
 	DEFW	0		; Check size	
-	DEFW	(1+65)*16	; Track offset	1056
+	DEFW	128+(1024*1)+2	; Trk Offset
 	  ENDIF
 ;
 ;.....
@@ -468,17 +465,17 @@ DPB59:	DEFW	64		; Scts/Trk
 				; sectors per track
 	DEFB	0		; Physical tracks/side (No Meaning in HD)
 
-HSIZ10	EQU	2048		; # of blocks in Second Partition  (1024 trks)
+HSIZ10	EQU	2048 - 4	; # of blocks in Second Partition  (1022 trks)
 				;		
 DPB60:	DEFW	64		; Scts/Trk
 	DEFB	5		; Blk Shf Fctr
 	DEFB	31		; Block Mask	
 	DEFB	1		; Extent Mask	
-	DEFW	HSIZ10		; Disk Size-1	
-	DEFW	511		; Dir Max-1	4 blocks
-	DEFB	0F0H,0		; Alloc 0,1	
+	DEFW	HSIZ10-1		; Disk Size-1	
+	DEFW	1024-1		; Dir Max-1
+	DEFB	0FFH,0		; Alloc 0,1
 	DEFW	0		; Check size	
-	DEFW	(1+2*65)*16	; Track offset	2096
+	DEFW	128+(1024*2)+2	; Trk Offset
 	  ENDIF
 ;
 ;.....
@@ -492,18 +489,17 @@ DPB60:	DEFW	64		; Scts/Trk
 	DEFB	16		; Logical Sectors per track
 	DEFB	0		; Physical tracks/side (No Meaning in HD)
 
-HSIZ11	EQU	2048		; # of blocks in Forth Logical Drive 
-				;   (1024 tracks)
+HSIZ11	EQU	2048 - 4	; # of blocks in Second Partition  (1022 trks)
 
 DPB61:	DEFW	64		; Scts/Trk
 	DEFB	5		; Blk Shf Fctr
 	DEFB	31		; Block Mask
 	DEFB	1		; Extent Mask
 	DEFW	HSIZ11-1 	; Disk Size-1
-	DEFW	511		; Dir Max-1
-	DEFB	0F0H,0		; Alloc 0,1
+	DEFW	1024-1		; Dir Max-1
+	DEFB	0FFH,0		; Alloc 0,1
 	DEFW	0		; Check size
-	DEFW	(1+3*65)*16	; Track offset	3136
+	DEFW	128+(1024*3)+2	; Trk Offset
 	  ENDIF
 		
 ;=========== End of Hard Disk DPBs ===========

Source/BPBIOS/hard-ww.z80

@@ -183,7 +183,6 @@ HDSK_RW1:
 	POP	BC              ; RESTORE INCOMING FUNCTION, DEVICE/UNIT
 	RET	NZ              ; ABORT IF SEEK RETURNED AN ERROR W/ ERROR IN A
 	LD	HL,(HB_DSKBUF)  ; GET BUFFER ADDRESS
-	;LD	D,BID_HB	; BUFFER IN HBIOS BANK
 	LD	A,(HB_BNKBIOS)	; BUFFER IN HBIOS BANK
 	LD	D,A		; PUT IN D
 	LD	E,1		; ONE SECTOR

Source/BPBIOS/hbios.z80

@@ -9,6 +9,7 @@
 HBF_ALLOC	EQU	0F6H		; HBIOS Func: ALLOCATE Heap Memory
 HBF_PEEK	EQU	0FAH		; HBIOS Func: Peek Byte
 HBF_POKE	EQU	0FBH		; HBIOS Func: Poke Byte
+HBF_SYSRES_INT	EQU	0F000H		; HBIOS Func: Internal Reset
 HBF_MEMINFO	EQU	0F8F1H		; HBIOS Func: Get Memory Info
 HBF_BNKINFO	EQU	0F8F2H		; HBIOS Func: Get Bank Info
 ;
@@ -43,22 +44,23 @@ HBX_CPYLEN	EQU	0FFE8H
 ; call here, make required changes, then update the
 ; BIOSJT to point directly to the normal SELMEM routine for
 ; all subsequent calls.
+;
+; When called, the incoming bank id will be the original hard-coded
+; bank id prior to any adjustments.  These original bank id's are
+; coded to be an offset from the ending HBIOS RAM bank id which
+; is (80h + RAM banks).  See romwbw.lib.  We update the requested
+; bank id for this initial call to make it the proper absolute
+; HBIOS bank id.
+;
+; See romwbw.lib for additional RAM bank layout information.
 
-	; BPBIOS	HBIOS		Typical
-	; ------------	--------------	--------------
-	;  -1: <COMMON>	BID_COM		90h - 1 = 8Fh
-	;  -2: TPABNK	BID_USR         90h - 2 = 8Eh
-	;  -3: <HBIOS>	BID_BIOS	90h - 3 = 8Dh	
-	;  -4: SYSBNK	BID_AUX		90h - 4 = 8Ch
-	;  -9: BNKM	BID_AUX-5	90h - 9 = 87h
-	; -16: RAMBNK	RAMD0		90h - 16 = 80h
-	
 HB_SELMEM:
-	PUSH	AF
 	PUSH	BC
 	PUSH	DE
 	PUSH	HL
 	
+	PUSH	AF		; Save incoming bank request
+	
 	  IF HB_DEBUG AND FALSE
 	CALL	PRTSTRD
 	DEFB	'[HB_SELMEM: $'
@@ -68,23 +70,30 @@ HB_SELMEM:
 	  ENDIF
 	
 	LD	BC,HBF_BNKINFO	; HBIOS BNKINFO function
-	CALL	HBX_INVOKE	; DO IT, D=BID_BIOS, E=BID_USER
-	LD	A,D		; BID_BIOS
-	LD	(HB_BNKBIOS),A	; SET HB_BNKBIOS
-	ADD	A,3		; HBIOS + 3
-	LD	(HB_BNKEND),A	; ... is the ending RAM bank
-	  IF BANKED
-	LD	(BNKADJ+1),A	; Dynamically update SELBNK
-	  ENDIF
-	  
+	CALL	HBX_INVOKE	; Do it, D=BIOS bank, E=USER (TPA) bank
+	LD	A,D		; BIOS bank
+	LD	(HB_BNKBIOS),A	; Save it for later (deblock & hard-ww)
+	LD	A,E		; USER (TPA) bank
+	LD	(TPABNK),A	; Update BP register
+	DEC	A		; SYS bank is one below USER
+	LD	(SYSBNK),A	; Update BP register
+	DEC	A		; HBIOS BUF bank is one more below
+	;LD	(UABNK),A	; Set BPBIOS USER bank
+	LD	(RAMBNK),A	; Update BP RAM disk bank register
+	LD	(MAXBNK),A	; Update ending bank register
+	
 	LD	HL,SELMEM	; Future SELMEM calls will
 	LD	(BIOSJT+(27*3)+1),HL	; ... go to real SELMEM
 	
+	POP	BC		; Recover requested bank to B
+	LD	A,(TPABNK)	; Get TPA bank
+	ADD	2		; Offset to ending RAM bank id
+	ADD	B		; Adjust for incoming request
+	
 	POP	HL
 	POP	DE
 	POP	BC
-	POP	AF
-	JP	SELMEM
+	JP	SELMEM		; Continue to normal SELMEM
 	
 ;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
 ; Move Data - Possibly between banks.  This resembles CP/M 3, but
@@ -97,15 +106,10 @@ HB_SELMEM:
 ;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
 
 HB_MOVE:
-	PUSH	HL
-	LD	HL,HB_BNKEND
 	LD	A,(HB_SRCBNK)
-	ADD	A,(HL)		; Adjust for HBIOS bank ids
 	LD	(HBX_SRCBNK),A
 	LD	A,(HB_DSTBNK)
-	ADD	A,(HL)		; Adjust for HBIOS bank ids
 	LD	(HBX_DSTBNK),A
-	POP	HL
 	CALL	HBX_BNKCPY
 	PUSH	HL
 	LD	HL,(TPABNK)	; Get TPA Bank #
@@ -141,6 +145,5 @@ HB_XMOVE:
 HB_SRCBNK:	DEFS	1	; Move Source Bank #
 HB_DSTBNK:	DEFS	1	; Move Destination Bank #
 HB_BNKBIOS:	DEFS	1	; Bank id of HBIOS bank
-HB_BNKEND:	DEFS	1	; End of available RAM banks (last bank + 1)
 HB_DSKBUF:	DEFS	2	; Address of physical disk buffer in HBIOS bank
 

Source/BPBIOS/ibmv-ww.z80

@@ -115,10 +115,22 @@ SELMEM:	LD	(USRBNK),A	; Update user bank
 ;  Must preserve all Registers including Flags.
 ;  All Bank Switching MUST be done by this routine
 ;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
+;
+; Parameter to BNKADJ (ADD) is set dynamically at initialization.
 
 SELBNK:	PUSH	AF		; Save regs
 SELBN0:	LD	(CURBNK),A	; Save as current bank #
-BNKADJ:	ADD	A,90H		; Adjust for HBIOS bank ids
+
+	  IF HB_DEBUG AND FALSE
+
+	CALL	PRTSTRD
+	DEFB	'[SELBNK: $'
+	CALL	PRTHEXBYTE
+	CALL	PRTSTRD
+	DEFB	']$'
+
+	  ENDIF
+
 	CALL	HBX_BNKSEL
 	POP	AF		; restore regs
 	RET
@@ -172,7 +184,7 @@ FRGETB:
 	PUSH	BC		; Save BC
 	PUSH	DE		; Save DE
 	LD	B,0FAH		; HBIOS Peek function
-	LD	D,C		; Bank in D
+	LD	D,C
 	CALL	HBX_INVOKE	; Do it
 	LD	A,E		; Value to A
 	POP	DE		; Restore DE
@@ -203,8 +215,8 @@ FRPUTB:
 	PUSH	BC		; Save BC
 	PUSH	DE		; Save DE
 	LD	B,0FBH		; HBIOS Poke function
-	LD	D,C		; Bank in D
 	LD	E,A		; Value in E
+	LD	D,C
 	CALL	HBX_INVOKE	; Do it
 	POP	DE		; Restore DE
 	POP	BC		; Restore BC

Source/BPBIOS/romwbw.lib

@@ -48,20 +48,33 @@ DRV_P		SET	NO		; YES if system has flopy drives
 ;
 ; RAM/ROM Bank Reserve
 ;
-HB_RAMRESV	EQU	8		; RAM reserve is 8 banks
+HB_RAMRESV	EQU	5		; RAM reserve is 5 banks
 HB_ROMRESV	EQU	4		; ROM reserve is 4 banks
 ;
 ; Layout of RAM banks
 ;
-; TODO: Query system via HBIOS API to determine the actual bank
-; assignments, then adjust BPBIOS operation accordingly.
+; The BID_xxx values below are used to set the initial values of
+; the BPBIOS bank registers (see def-ww-xxx.lib and HB_SELMEM in
+; hbios.z80).  The running values of the BPBIOS bank registers (TPABNK,
+; SYSBNK, etc.) are set to absolute HBIOS bank ids in hbios.z80 during
+; startup.
 ;
-BID_RAMD	EQU	-16	; 90h - 16 = 80h
-BID_RAMM	EQU	-9	; 90h - 9 = 87h
-BID_SYS		EQU	-4	; 90h - 4 = 8Ch
-BID_HB		EQU	-3	; 90h - 3 = 8Dh
-BID_USR		EQU	-2	; 90h - 2 = 8Eh
-BID_COM		EQU	-1	; 90h - 1 = 8Fh
+; The values below are expressed as an offset from the ending HBIOS
+; RAM bank id.  They map to HBIOS bank ids
+; by subtracting from the ending HBIOS bank id (N).  HBIOS RAM bank ids
+; start at 80h.  The ending HBIOS bank id is (80h + RAM banks).  The
+; typical layout assumes 16 banks of RAM starting at HBIOS bank id 80h
+; and ending at bank id 90h (N = 90h).
+;
+; BPBIOS					HBIOS (TYPICAL)
+; --------------------------------------	---------------
+; <HBIOS>					80h   (80h)
+; <RAMD>					81h   (81h)
+; <RAMM>					N - 5 (8Bh)
+BID_BUF	EQU	-4	; BNK3 -> RAMBNK	N - 4 (8Ch)
+BID_SYS	EQU	-3	; BNK2 -> SYSBNK	N - 3 (8Dh)		
+BID_USR	EQU	-2	; BNK0 -> TPABNK	N - 2 (8Eh)		
+BID_COM	EQU	-1	; BNK1 ->		N - 1 (8Fh)		
 ;
 HB_EI	MACRO
 	EI

Source/Build.cmd

@@ -4,11 +4,13 @@ setlocal
 :: call BuildDoc || exit /b
 call BuildProp || exit /b
 call BuildShared || exit /b
-:: call BuildBP || exit /b
+call BuildBP || exit /b
 call BuildImages || exit /b
 call BuildROM %* || exit /b
 call BuildZRC || exit /b
+call BuildZ1RCC || exit /b
 call BuildZZRCC || exit /b
+call BuildZRC512 || exit /b
 
 if "%1" == "dist" (
   call Clean || exit /b

Source/BuildZ1RCC.cmd

@@ -0,0 +1,4 @@
+@echo off
+setlocal
+
+pushd Z1RCC && call Build || exit /b & popd

Source/BuildZRC512.cmd

@@ -0,0 +1,4 @@
+@echo off
+setlocal
+
+pushd ZRC512 && call Build || exit /b & popd

Source/CPM3/boot.z80

@@ -13,7 +13,7 @@
 	extrn	@dtbl,@ctbl
 	extrn	@date,@hour,@min,@sec
 	extrn	@srch1
-	extrn	@hbbio
+	extrn	@hbbio,@hbusr
 	extrn	addhla
 	extrn	phex16, phex8
 	extrn	cin, cout
@@ -46,7 +46,7 @@ tpa$bank	equ 0
 	; Clone page zero from bank 0 to additional banks
 	ld	b,2			; last bank
 	ld	c,0			; src bank
-init$2:
+init$1:
 	push	bc			; save bank id's
 	call	?xmove			; set src/dest banks
 	ld	bc,0100h		; size is one page
@@ -54,7 +54,7 @@ init$2:
 	ld	de,0			; src adr is 0
 	call	?move			; do it
 	pop	bc			; restore bank id's
-	djnz	init$2			; loop till done
+	djnz	init$1			; loop till done
 	
 	endif
 
@@ -62,6 +62,35 @@ init$2:
 	ld	hl,signon$msg		; signon message
 	call	?pmsg			; print it
 
+	if banked
+	
+	; Confirm that HBIOS is configured with enough RAM banks
+	; to accommodate banked version of CP/M 3.  We use 2
+	; additional banks which live below the user bank.  So we
+	; check that the these don't overlap with the RomWBW HBIOS
+	; bank.
+
+	ld	bc,0F8F2h	; HBIOS GET BNKINFO
+	call	0FFF0h		; D: BIOS Bank, E: User Bank
+	ld	a,d
+	ld	(@hbbio),a
+	ld	a,e
+	ld	(@hbusr),a
+	
+	sub	3		; 2 extra banks (+1 for compare)
+	cp	d		; lowest cpm bank - hbios bank
+	jr	nc,init$2	; continue if space available
+	
+	ld	hl,noram$msg	; signon message
+	call	?pmsg		; print it
+
+	ld	b,0F0h		; HBIOS system reset
+	ld	c,1h		; reset type warm (back to loader)
+	call	0FFFFh		; do it
+
+	endif
+
+init$2:
 	; Check for HBIOS/CBIOS mismatch
 	ld	b,0F1h			; hbios version
 	rst	08			; do it, de=maj/min/up/pat
@@ -731,6 +760,10 @@ clrflg		db	0		; RAM disk cleared flag
 clr$msg		db	'RAM Disk Initialized',13,10,13,10,0
 vermis$msg	db	7,'*** WARNING: HBIOS/CBIOS Version Mismatch ***',13,10,13,10,0
 
+	if banked
+noram$msg	db	7,'*** ERROR: Insufficient RAM for banked CP/M 3 ***',13,10,13,10,0
+	endif
+
 	if zpm
 
 signon$msg	db	13,10,'ZPM3'

Source/Clean.cmd

@@ -22,4 +22,5 @@ pushd Prop && call Clean & popd
 pushd RomDsk && call Clean & popd
 pushd Doc && call Clean & popd
 pushd ZRC && call Clean & popd
+pushd Z1RCC && call Clean & popd
 pushd ZZRCC && call Clean & popd

Source/Doc/Book.h

@@ -30,7 +30,9 @@ header-includes:
       {\scshape \bfseries \fontsize{48pt}{56pt} \selectfont $doc_product$ \par}
       {\bfseries \fontsize{32pt}{36pt} \selectfont $doc_title$ \par}
       \vspace{24pt}
-      {\huge $doc_ver$ \\ $doc_date$ \par}
+      {\huge $doc_ver$ \par}
+      \vspace{12pt}
+      {\large Updated $doc_date$ \par}
       \vspace{24pt}
       {\large \itshape $doc_orgname$ \\ \href{http://$doc_orgurl$}{$doc_orgurl$} \par}
       \vspace{12pt}

Source/Doc/ReadMe.md

@@ -10,14 +10,23 @@ A wide variety of platforms are supported including those
 produced by these developer communities:
 
 * [RetroBrew Computers](https://www.retrobrewcomputers.org)
-* [RC2014](https://rc2014.co.uk), [RC2014-Z80](https://groups.google.com/g/rc2014-z80)
-* [retro-comp](https://groups.google.com/forum/#!forum/retro-comp)
+  (<https://www.retrobrewcomputers.org>)
+* [RC2014](https://rc2014.co.uk) (<https://rc2014.co.uk>), \
+  [RC2014-Z80](https://groups.google.com/g/rc2014-z80)
+  (<https://groups.google.com/g/rc2014-z80>)
+* [Retro Computing](https://groups.google.com/g/retro-comp)
+  (<https://groups.google.com/g/retro-comp>)
 * [Small Computer Central](https://smallcomputercentral.com/)
+  (<https://smallcomputercentral.com/>)
+
+A complete list of the currently supported platforms is found in the
+[Installation] section.
 
 General features include:
 
+* Z80 Family CPUs including Z80, Z180, and Z280
 * Banked memory services for several banking designs
-* Disk drivers for RAM, ROM, Floppy, IDE, CF, and SD
+* Disk drivers for RAM, ROM, Floppy, IDE ATA/ATAPI, CF, SD, USB, Zip, Iomega
 * Serial drivers including UART (16550-like), ASCI, ACIA, SIO
 * Video drivers including TMS9918, SY6545, MOS8563, HD6445
 * Keyboard (PS/2) drivers via VT8242 or PPI interfaces
@@ -34,12 +43,12 @@ ROM firmware itself:
 * ROM BASIC (Nascom BASIC and Tasty BASIC)
 * ROM Forth
 
-A dynamic disk drive letter assignment mechanism allows mapping
-operating system drive letters to any available disk media.
-Additionally, mass storage devices (IDE Disk, CF Card, SD Card) support
-the use of multiple slices (up to 256 per device). Each slice contains
-a complete CP/M filesystem and can be mapped independently to any
-drive letter. This overcomes the inherent size limitations in legacy
+A dynamic disk drive letter assignment mechanism allows mapping 
+operating system drive letters to any available disk media. 
+Additionally, mass storage devices (IDE Disk, CF Card, SD Card, etc.) 
+support the use of multiple slices (up to 256 per device). Each slice 
+contains a complete CP/M filesystem and can be mapped independently to 
+any drive letter. This overcomes the inherent size limitations in legacy
 OSes and allows up to 2GB of accessible storage on a single device.
 
 The pre-built ROM firmware images are generally suitable for most
@@ -61,7 +70,7 @@ By design, RomWBW isolates all of the hardware specific functions in
 the ROM chip itself.  The ROM provides a hardware abstraction layer
 such that all of the operating systems and applications on a disk
 will run on any RomWBW-based system.  To put it simply, you can take
-a disk (or CF/SD Card) and move it between systems transparently.
+a disk (or CF/SD/USB Card) and move it between systems transparently.
 
 A tool is provided that allows you to access a FAT-12/16/32 filesystem. 
 The FAT filesystem may be coresident on the same disk media as RomWBW 
@@ -70,18 +79,19 @@ OSes such as Windows, MacOS, and Linux very easy.
 
 # Acquiring RomWBW
 
-The [RomWBW Repository](https://github.com/wwarthen/RomWBW) on GitHub is
-the official distribution location for all project source and
-documentation.  The fully-built distribution releases are available on
-the [RomWBW Releases Page](https://github.com/wwarthen/RomWBW/releases)
-of the repository.  On this page, you will normally see a Development
-Snapshot as well as recent stable releases. Unless you have a specific
-reason, I suggest you stick to the most recent stable release. Expand
-the "Assets" drop-down for the release you want to download, then select
-the asset named RomWBW-vX.X.X-Package.zip. The Package asset includes
-all pre-built ROM and Disk images as well as full source code. The other
-assets contain only source code and do not have the pre-built ROM or
-disk images.
+The [RomWBW Repository](https://github.com/wwarthen/RomWBW)
+(<https://github.com/wwarthen/RomWBW>) on GitHub is the official 
+distribution location for all project source and documentation.  The 
+fully-built distribution releases are available on the
+[RomWBW Releases Page](https://github.com/wwarthen/RomWBW/releases)
+(<https://github.com/wwarthen/RomWBW/releases>) of the repository.  On 
+this page, you will normally see a Development Snapshot as well as 
+recent stable releases. Unless you have a specific reason, I suggest you
+ stick to the most recent stable release. Expand the "Assets" drop-down 
+for the release you want to download, then select the asset named 
+RomWBW-vX.X.X-Package.zip. The Package asset includes all pre-built ROM 
+and Disk images as well as full source code. The other assets contain 
+only source code and do not have the pre-built ROM or disk images.
 
 All source code and distributions are maintained on GitHub. Code
 contributions are very welcome.

Source/HBIOS/Build.cmd

@@ -33,6 +33,16 @@ PowerShell -ExecutionPolicy Unrestricted .\Build.ps1 %* || exit /b
 
 call build_env.cmd
 
+::
+:: Start of the actual build process for a given ROM.
+::
+
+echo.
+echo ============================================================
+echo %ROMName% for Z%CPUType% CPU
+echo ============================================================
+echo.
+
 ::
 :: Create a small app that is used to export key build variables of the build.
 :: Then run the app to output a file with the variables.  Finally, read the
@@ -43,12 +53,6 @@ tasm -t80 -g3 -dCMD hbios_env.asm hbios_env.com hbios_env.lst || exit /b
 zxcc hbios_env >hbios_env.cmd
 call hbios_env.cmd
 
-::
-:: Start of the actual build process for a given ROM.
-::
-
-echo Building %ROMSize%K ROM %ROMName% for Z%CPUType% CPU...
-
 ::
 :: UNA is a special case, check for it and jump if needed.
 ::
@@ -214,8 +218,10 @@ call Build RCZ80 skz || exit /b
 :: call Build RCZ80 duart || exit /b
 call Build RCZ80 zrc || exit /b
 call Build RCZ80 zrc_ram || exit /b
+call Build RCZ80 zrc512 || exit /b
 call Build RCZ180 ext || exit /b
 call Build RCZ180 nat || exit /b
+call Build RCZ180 z1rcc || exit /b
 call Build RCZ280 ext || exit /b
 call Build RCZ280 nat || exit /b
 call Build RCZ280 zz80mb || exit /b
@@ -234,5 +240,7 @@ call Build Z80RETRO std || exit /b
 call Build S100 std || exit /b
 call Build DUO std || exit /b
 call Build HEATH std || exit /b
+call Build EPITX std || exit /b
+:: call Build MON std || exit /b
 
 goto :eof

Source/HBIOS/Build.ps1

@@ -27,8 +27,8 @@ $ErrorAction = 'Stop'
 # UNA BIOS is simply imbedded, it is not built here.
 #
 
-$PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "Z80RETRO", "DUO", "UNA", "HEATH"
-$PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO", "RPH", "S100"
+$PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "Z80RETRO", "DUO", "UNA", "HEATH", "MON"
+$PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO", "RPH", "S100", "EPITX"
 $PlatformListZ280 = "RCZ280"
 
 #

Source/HBIOS/Build.sh

@@ -15,6 +15,7 @@ if [ "${ROM_PLATFORM}" == "dist" ] ; then
 	ROM_PLATFORM="N8"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="RCZ180"; ROM_CONFIG="ext"; bash Build.sh
 	ROM_PLATFORM="RCZ180"; ROM_CONFIG="nat"; bash Build.sh
+	ROM_PLATFORM="RCZ180"; ROM_CONFIG="z1rcc"; bash Build.sh
 	ROM_PLATFORM="RCZ280"; ROM_CONFIG="ext"; bash Build.sh
 	ROM_PLATFORM="RCZ280"; ROM_CONFIG="nat"; bash Build.sh
 	ROM_PLATFORM="RCZ280"; ROM_CONFIG="zz80mb"; bash Build.sh
@@ -29,6 +30,7 @@ if [ "${ROM_PLATFORM}" == "dist" ] ; then
 	ROM_PLATFORM="RCZ80"; ROM_CONFIG="skz"; bash Build.sh
 	ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc"; bash Build.sh
 	ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc_ram"; bash Build.sh
+	ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc512"; bash Build.sh
 	ROM_PLATFORM="RPH"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="SBC"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="SBC"; ROM_CONFIG="simh"; bash Build.sh
@@ -46,6 +48,8 @@ if [ "${ROM_PLATFORM}" == "dist" ] ; then
 	ROM_PLATFORM="ZETA"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="ZETA2"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="HEATH"; ROM_CONFIG="std"; bash Build.sh
+	ROM_PLATFORM="EPITX"; ROM_CONFIG="std"; bash Build.sh
+#	ROM_PLATFORM="MON"; ROM_CONFIG="std"; bash Build.sh
 	exit
 fi
 

Source/HBIOS/Config/EPITX_std.asm

@@ -0,0 +1,64 @@
+;
+;==================================================================================================
+;   Z180 Mini ITX STANDARD CONFIGURATION
+;==================================================================================================
+;
+; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
+; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
+; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
+; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
+; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
+; YOUR FILE IN THE BUILD PROCESS.
+;
+; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
+; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
+; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
+; SETTINGS.
+;
+; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
+; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
+; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
+; DIRECTORIES ABOVE THIS ONE).
+;
+#DEFINE	PLATFORM_NAME	"Z180 MiniITX"
+;
+#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
+;
+#include "cfg_epitx.asm"
+;
+CRTACT		.SET	TRUE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+;
+CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
+;
+Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
+Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+;
+HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+;
+LEDENABLE	.SET	FALSE		; ENABLE STATUS LED (SINGLE LED)
+;
+DSRTCENABLE	.SET	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+INTRTCENABLE	.SET	TRUE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+;
+UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+ASCIENABLE	.SET	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+;
+TMSENABLE	.SET	TRUE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+;
+AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
+;
+FDENABLE	.SET	TRUE		; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
+FDMODE		.SET	FDMODE_EPFDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3]
+;
+IDEENABLE	.SET	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+;
+PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+;
+SDENABLE	.SET	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+;
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)

Source/HBIOS/Config/MON_std.asm

@@ -0,0 +1,30 @@
+;
+;==================================================================================================
+;   MONSPUTER Z80 STANDARD CONFIGURATION
+;==================================================================================================
+;
+; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
+; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
+; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
+; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
+; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
+; YOUR FILE IN THE BUILD PROCESS.
+;
+; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
+; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
+; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
+; SETTINGS.
+;
+; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
+; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
+; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
+; DIRECTORIES ABOVE THIS ONE).
+;
+#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
+;
+#include "cfg_mon.asm"
+;
+CPUOSC		.SET	4000000		; CPU OSC FREQ IN MHZ
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP

Source/HBIOS/Config/RCZ180_z1rcc.asm

@@ -0,0 +1,76 @@
+;
+;==================================================================================================
+;   RCBUS Z180 Z1RCC CONFIGURATION (ROMLESS)
+;==================================================================================================
+;
+; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
+; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
+; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
+; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
+; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
+; YOUR FILE IN THE BUILD PROCESS.
+;
+; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
+; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
+; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
+; SETTINGS.
+;
+; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
+; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
+; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
+; DIRECTORIES ABOVE THIS ONE).
+;
+#DEFINE PLATFORM_NAME "Z1RCC", " [", CONFIG, "]"
+;
+#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
+;
+#include "cfg_rcz180.asm"
+;
+CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+;
+FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+;
+MEMMGR		.SET	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
+;
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.SET	0		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+;
+Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
+Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+;
+MDROM		.SET	FALSE		; MD: ENABLE ROM DISK
+MDRAM		.SET	TRUE		; MD: ENABLE RAM DISK
+;
+DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+INTRTCENABLE	.SET	TRUE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+;
+UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+ASCIENABLE	.SET	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+;
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
+MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+;
+;
+AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
+AYMODE		.SET	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+;
+FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
+;
+IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY
+;
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)

Source/HBIOS/Config/RCZ280_zzrcc.asm

@@ -28,7 +28,7 @@
 ;
 #include "cfg_rcz280.asm"
 ;
-CPUOSC		.SET	14745600	; CPU OSC FREQ IN MHZ
+CPUOSC		.SET	29491200	; CPU OSC FREQ IN MHZ
 INTMODE		.SET	3		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;

Source/HBIOS/Config/RCZ280_zzrcc_ram.asm

@@ -28,7 +28,7 @@
 ;
 #include "cfg_rcz280.asm"
 ;
-CPUOSC		.SET	14745600	; CPU OSC FREQ IN MHZ
+CPUOSC		.SET	29491200	; CPU OSC FREQ IN MHZ
 INTMODE		.SET	3		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;

Source/HBIOS/Config/RCZ80_zrc.asm

@@ -27,13 +27,15 @@
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;
 #include "cfg_rcz80.asm"
+;
 CPUOSC		.SET	14745600	; CPU OSC FREQ IN MHZ
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
 FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
-FPSW_ENABLE     .SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
 ;
-RAMSIZE		.SET	1536		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.SET	256		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
 MEMMGR		.SET	MM_ZRC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
 ;
 UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)

Source/HBIOS/Config/RCZ80_zrc512.asm

@@ -0,0 +1,68 @@
+;
+;==================================================================================================
+;   RCBUS Z80 ZRC512 CONFIGURATION
+;==================================================================================================
+;
+; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
+; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
+; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
+; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
+; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
+; YOUR FILE IN THE BUILD PROCESS.
+;
+; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
+; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
+; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
+; SETTINGS.
+;
+; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
+; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
+; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
+; DIRECTORIES ABOVE THIS ONE).
+;
+#DEFINE PLATFORM_NAME "ZRC512", " [", CONFIG, "]"
+;
+#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
+;
+#include "cfg_rcz80.asm"
+;
+CPUOSC		.SET	22000000	; CPU OSC FREQ IN MHZ
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+;
+FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+;
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.SET	0		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+MEMMGR		.SET	MM_ZRC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
+;
+MDROM		.SET	FALSE		; MD: ENABLE ROM DISK
+;
+UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+ACIAENABLE	.SET	TRUE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+;
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
+MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+VRCENABLE	.SET	TRUE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+;
+AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
+AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+;
+FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
+;
+IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY
+IMMENABLE	.SET	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+;
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)

Source/HBIOS/Config/RCZ80_zrc_ram.asm

@@ -28,7 +28,7 @@
 ;
 #include "cfg_rcz80.asm"
 ;
-CPUOSC		.SET	7372800		; CPU OSC FREQ IN MHZ
+CPUOSC		.SET	14745600	; CPU OSC FREQ IN MHZ
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
 FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
@@ -50,7 +50,7 @@ TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
 MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
 VRCENABLE	.SET	TRUE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
-VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
 ;
 AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]

Source/HBIOS/Config/SCZ180_sc131.asm

@@ -52,3 +52,4 @@ PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM
 SDENABLE	.SET	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
 SDMODE		.SET	SDMODE_SC	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
 SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
+CHENABLE	.SET	FALSE		; CH: ENABLE CH375/376 USB SUPPORT

Source/HBIOS/Config/ZETA_std.asm

@@ -26,7 +26,7 @@
 ;
 #include "cfg_zeta.asm"
 ;
-CPUOSC		.SET	20000000	; CPU OSC FREQ IN MHZ
+CPUOSC		.SET	8000000		; CPU OSC FREQ IN MHZ
 INTMODE		.SET	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 CRTACT		.SET	TRUE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;

Source/HBIOS/acia.asm

@@ -178,10 +178,26 @@ ACIA1_INT:
 ;
 ACIA_INTRCV:
         ; CHECK TO SEE IF SOMETHING IS ACTUALLY THERE
+	CALL	DELAY
         LD      C,(IY+3)                ; CMD/STAT PORT TO C
         IN      A,(C)                   ; GET STATUS
-        RRA                             ; READY BIT TO CF
-        RET     NC                      ; NOTHING AVAILABLE ON CURRENT CHANNEL
+	LD	B,A
+	AND	$01			; ISOLATE READY BIT
+	JR	NZ,ACIA_INTRCV1
+;
+#IF FALSE
+	CALL	PC_LT
+	LD	A,B
+	CALL	PRTHEXBYTE
+	INC	C
+	IN	A,(C)
+	CALL	PRTHEXBYTE
+	CALL	PC_GT
+	OR	$FF
+#ENDIF
+;
+	RET
+	
 ;
 ACIA_INTRCV1:
         ; RECEIVE CHARACTER INTO BUFFER
@@ -701,6 +717,13 @@ ACIA0_CFG:
         .DW     ACIA0_INT                ; INT HANDLER POINTER
         .DW     (ACIA0CLK / ACIA0DIV) & $FFFF   ; CLOCK FREQ AS
         .DW     (ACIA0CLK / ACIA0DIV) >> 16     ; ... DWORD VALUE
+;
+	.ECHO	"ACIA: IO="
+	.ECHO	ACIA0BASE
+#IF (INTMODE == 1)
+	.ECHO	", INTERRUPTS ENABLED"
+#ENDIF
+	.ECHO	"\n"
 ;
 ACIA_CFGSIZ     .EQU    $ - ACIA_CFG    ; SIZE OF ONE CFG TABLE ENTRY
 ;
@@ -717,6 +740,13 @@ ACIA1_CFG:
         .DW     ACIA1_INT                ; INT HANDLER POINTER
         .DW     (ACIA1CLK / ACIA1DIV) & $FFFF   ; CLOCK FREQ AS
         .DW     (ACIA1CLK / ACIA1DIV) >> 16     ; ... DWORD VALUE
+;
+	.ECHO	"ACIA: IO="
+	.ECHO	ACIA1BASE
+#IF (INTMODE == 1)
+	.ECHO	", INTERRUPTS ENABLED"
+#ENDIF
+	.ECHO	"\n"
 ;
 #ENDIF
 ;

Source/HBIOS/asci.asm

@@ -836,6 +836,13 @@ ASCI1_CFG:
 	.DB	ASCI1_BASE		; BASE PORT
 	.DW	ASCI1CFG		; LINE CONFIGURATION
 	.DW	ASCI1_RCVBUF		; POINTER TO RCV BUFFER STRUCT
+;
+	.ECHO	"ASCI: IO="
+	.ECHO	ASCI1_BASE
+#IF ((ASCIINTS) & (INTMODE >0))
+	.ECHO	", INTERRUPTS ENABLED"
+#ENDIF
+	.ECHO	"\n"
 ;
 ASCI_CFGSIZ	.EQU	$ - ASCI_CFG	; SIZE OF ONE CFG TABLE ENTRY
 ;
@@ -847,6 +854,13 @@ ASCI0_CFG:
 	.DB	ASCI0_BASE		; BASE PORT
 	.DW	ASCI0CFG		; LINE CONFIGURATION
 	.DW	ASCI0_RCVBUF		; POINTER TO RCV BUFFER STRUCT
+;
+	.ECHO	"ASCI: IO="
+	.ECHO	ASCI0_BASE
+#IF ((ASCIINTS) & (INTMODE >0))
+	.ECHO	", INTERRUPTS ENABLED"
+#ENDIF
+	.ECHO	"\n"
 ;
 #ELSE
 ;
@@ -858,6 +872,13 @@ ASCI0_CFG:
 	.DB	ASCI0_BASE		; BASE PORT
 	.DW	ASCI0CFG		; LINE CONFIGURATION
 	.DW	ASCI0_RCVBUF		; POINTER TO RCV BUFFER STRUCT
+;
+	.ECHO	"ASCI: IO="
+	.ECHO	ASCI0_BASE
+#IF ((ASCIINTS) & (INTMODE >0))
+	.ECHO	", INTERRUPTS ENABLED"
+#ENDIF
+	.ECHO	"\n"
 ;
 ASCI_CFGSIZ	.EQU	$ - ASCI_CFG	; SIZE OF ONE CFG TABLE ENTRY
 ;
@@ -869,8 +890,14 @@ ASCI1_CFG:
 	.DB	ASCI1_BASE		; BASE PORT
 	.DW	ASCI1CFG		; LINE CONFIGURATION
 	.DW	ASCI1_RCVBUF		; POINTER TO RCV BUFFER STRUCT
+;
+	.ECHO	"ASCI: IO="
+	.ECHO	ASCI1_BASE
+#IF ((ASCIINTS) & (INTMODE > 0))
+	.ECHO	", INTERRUPTS ENABLED"
+#ENDIF
+	.ECHO	"\n"
 ;
 #ENDIF
 ;
-;
 ASCI_CFGCNT	.EQU	($ - ASCI_CFG) / ASCI_CFGSIZ

Source/HBIOS/ay38910.asm

@@ -19,12 +19,15 @@
 ;  VOLTAGE LEVEL OUTPUT ON A AY-3-8910 IS LOW AND AROUND 2V ON YM2149.
 ;
 AY_RCSND	.EQU	0		; 0 = EB MODULE, 1=MF MODULE
+;
+	.ECHO	"AY38910: MODE="
 ;
 #IF (AYMODE == AYMODE_SCG)
 AY_RSEL		.EQU	$9A
 AY_RDAT		.EQU	$9B
 AY_RIN		.EQU	AY_RSEL
 AY_ACR		.EQU	$9C
+		.ECHO	"SCG"
 #ENDIF
 ;
 #IF (AYMODE == AYMODE_N8)
@@ -32,30 +35,35 @@ AY_RSEL		.EQU	$9C
 AY_RDAT		.EQU	$9D
 AY_RIN		.EQU	AY_RSEL
 AY_ACR		.EQU	N8_DEFACR
+		.ECHO	"N8"
 #ENDIF
 ;
 #IF (AYMODE == AYMODE_RCZ80)
 AY_RSEL		.EQU	$D8
 AY_RDAT		.EQU	$D0
 AY_RIN		.EQU	AY_RSEL+AY_RCSND
+		.ECHO	"RCZ80"
 #ENDIF
 ;
 #IF (AYMODE == AYMODE_RCZ180)
 AY_RSEL		.EQU	$68
 AY_RDAT		.EQU	$60
 AY_RIN		.EQU	AY_RSEL+AY_RCSND
+		.ECHO	"RCZ180"
 #ENDIF
 ;
 #IF (AYMODE == AYMODE_MSX)
 AY_RSEL		.EQU	$A0
 AY_RDAT		.EQU	$A1
 AY_RIN		.EQU	$A2
+		.ECHO	"MSX"
 #ENDIF
 ;
 #IF (AYMODE == AYMODE_LINC)
 AY_RSEL		.EQU	$33
 AY_RDAT		.EQU	$32
 AY_RIN		.EQU	$32
+		.ECHO	"LINC"
 #ENDIF
 ;
 #IF (AYMODE == AYMODE_MBC)
@@ -63,7 +71,14 @@ AY_RSEL		.EQU	$A0
 AY_RDAT		.EQU	$A1
 AY_RIN		.EQU	AY_RSEL
 AY_ACR		.EQU	$A2
+		.ECHO	"MBC"
 #ENDIF
+;
+	.ECHO	", IO="
+	.ECHO	AY_RSEL
+	.ECHO	", CLOCK="
+	.ECHO	AY_CLK
+	.ECHO	" HZ\n"
 ;
 ;======================================================================
 ;
@@ -107,10 +122,6 @@ AY_NOISECNT	.EQU	1		; COUNT NUMBER OF NOISE CHANNELS
 ;#ELSE					; PRESCALE THE TONE PERIOD
 ;AY_SCALE	.EQU	3		; DATA TO MAINTAIN MAXIMUM
 ;#ENDIF					; RANGE AND ACCURACY
-;
-	.ECHO	"AY38910 CLOCK: "
-	.ECHO	AY_CLK
-	.ECHO	"\n"
 ;
 #INCLUDE "audio.inc"
 ;

Source/HBIOS/bqrtc.asm

@@ -91,6 +91,10 @@ BQRTC_UTI	.EQU	%00001000
 
 BQRTC_BUFSIZE	.EQU	6		; 6 BYTE BUFFER (YYMMDDHHMMSS)
 
+		.ECHO	"BQRTC: IO="
+		.ECHO	BQRTC_BASE
+		.ECHO	"\n"
+
 ; RTC Device Initialization Entry
 
 BQRTC_INIT:

Source/HBIOS/cfg_duo.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_DUO		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+PLATFORM	.EQU	PLT_DUO		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,7 @@ DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
 MPGSEL_0	.EQU	$50		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$51		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$52		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
@@ -46,15 +46,15 @@ RTCIO		.EQU	$94		; RTC LATCH REGISTER ADR
 KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
 KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
 ;
-CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCENABLE	.EQU	TRUE		; ENABLE ZILOG CTC SUPPORT
 CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
-CTCBASE		.EQU	$B0		; CTC BASE I/O ADDRESS
+CTCBASE		.EQU	$60		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	TRUE		; ENABLE CTC PERIODIC TIMER
 CTCMODE		.EQU	CTCMODE_CTR	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
 CTCPRE		.EQU	256		; PRESCALE CONSTANT (1-256)
 CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
-CTCOSC		.EQU	(4915200/8)	; CTC CLOCK FREQUENCY
+CTCOSC		.EQU	(7372800/8)	; CTC CLOCK FREQUENCY
 ;
 PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
 PCFBASE		.EQU	$56		; PCF8584 BASE I/O ADDRESS
@@ -65,11 +65,11 @@ SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
-FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
-FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
-FPLED_DSKACT	.EQU	FALSE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
-FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
-FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+FPLED_ENABLE	.EQU	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.EQU	$42		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.EQU	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.EQU	$42		; FP: PORT ADDRESS FOR FP SWITCHES
 ;
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
@@ -88,6 +88,7 @@ PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
 VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
@@ -122,17 +123,18 @@ DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
 UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTOSC		.EQU	7372800		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
 UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	TRUE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
 UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
-UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+UARTDUAL	.EQU	TRUE		; UART: AUTO-DETECT DUAL UART
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
@@ -140,18 +142,18 @@ Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 ;
 ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ;
-SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
 SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO0BASE	.EQU	$B0		; SIO 0: REGISTERS BASE ADR
-SIO0ACLK	.EQU	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BASE	.EQU	$60		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.EQU	(7372800/4)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
-SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO0BCLK	.EQU	(4915200/8)	; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACTCC	.EQU	0		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.EQU	(7372800/4)	; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
-SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCTCC	.EQU	1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
 XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
@@ -176,8 +178,8 @@ MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
 ;
-FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.EQU	FDMODE_MBC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDENABLE	.EQU	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.EQU	FDMODE_DUO	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
@@ -209,10 +211,10 @@ IDE2DATHI	.EQU	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
 IDE2A8BIT	.EQU	TRUE		; IDE 2A (MASTER): 8 BIT XFER
 IDE2B8BIT	.EQU	TRUE		; IDE 2B (MASTER): 8 BIT XFER
 ;
-PPIDEENABLE	.EQU	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDEENABLE	.EQU	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
 PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
-PPIDE0BASE	.EQU	$60		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0BASE	.EQU	$88		; PPIDE 0: PPI REGISTERS BASE ADR
 PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
 PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 PPIDE1BASE	.EQU	$20		; PPIDE 1: PPI REGISTERS BASE ADR
@@ -222,21 +224,22 @@ PPIDE2BASE	.EQU	$14		; PPIDE 2: PPI REGISTERS BASE ADR
 PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
-SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_JUHA	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.EQU	TRUE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
-CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHENABLE	.EQU	TRUE		; CH: ENABLE CH375/376 USB SUPPORT
 CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
-CH0BASE		.EQU	$BE		; CH 0: BASE I/O ADDRESS
+CH0BASE		.EQU	$4E		; CH 0: BASE I/O ADDRESS
 CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
-CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
+CH0SDENABLE	.EQU	TRUE		; CH 0: ENABLE SD DISK
 CH1BASE		.EQU	$FF		; CH 1: BASE I/O ADDRESS
 CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
 CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
@@ -254,16 +257,16 @@ ESPCONENABLE	.EQU	TRUE		; ESP: ENABLE ESP32 CONSOLE IO DRIVER VIDEO/KBD SUPPORT
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 HDSKTRACE	.EQU	1		; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 ;
-PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOENABLE	.EQU	TRUE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
 PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
-PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+PIO0BASE	.EQU	$68		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$6C		; PIO 1: REGISTERS BASE ADR
 ;
-LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTENABLE	.EQU	TRUE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
 LPTMODE		.EQU	LPTMODE_SPP	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
 LPTCNT		.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
 LPTTRACE	.EQU	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-LPT0BASE	.EQU	$E8		; LPT 0: REGISTERS BASE ADR
+LPT0BASE	.EQU	$48		; LPT 0: REGISTERS BASE ADR
 LPT1BASE	.EQU	$EC		; LPT 1: REGISTERS BASE ADR
 ;
 PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)

Source/HBIOS/cfg_dyno.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_DYNO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+PLATFORM	.EQU	PLT_DYNO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,7 @@ DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
 RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
@@ -90,6 +90,7 @@ PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
 VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
@@ -136,6 +137,7 @@ UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
 UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART

Source/HBIOS/cfg_epitx.asm

@@ -0,0 +1,330 @@
+;
+;==================================================================================================
+;   ROMWBW 2.X CONFIGURATION DEFAULTS FOR SC Z180 VARIANTS (SC126, SC130, ETC.)
+;==================================================================================================
+;
+; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
+; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
+; UNDER THIS DIRECTORY.
+;
+; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
+; FOR THE PLATFORM.
+;
+#DEFINE PLATFORM_NAME "MiniITX"
+;
+#INCLUDE "hbios.inc"
+;
+PLATFORM	.EQU	PLT_EPITX	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+;
+BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+;
+CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
+INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;
+RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
+RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+;
+Z180_BASE	.EQU	$C0		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
+Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
+Z180_MEMWAIT	.EQU	0		; Z180: MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.EQU	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+Z180_TIMER	.EQU	TRUE		; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
+;
+RTCIO		.EQU	$0C		; RTC LATCH REGISTER ADR - TODO
+;
+KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+;
+CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
+CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
+;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
+SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+;
+WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+;
+FPENABLE	.EQU	FALSE		; ENABLES FRONT PANEL SWITCHES
+FPBASE		.EQU	$00		; FRONT PANEL I/O PORT BASE ADDRESS
+DIAGENABLE	.EQU	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
+DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
+DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
+;
+FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_DSKACT	.EQU	FALSE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+;
+DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+;
+LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
+LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|RTC]
+LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
+LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+;
+DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+;
+BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
+CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+; TODO - ADD PS/2 BITBANGER
+VDAEMU_SERKBD	.EQU	$00		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYENABLE	.EQU	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+;
+DSRTCENABLE	.EQU	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
+DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+;
+DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+;
+BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+;
+INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+;
+RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
+HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+;
+DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+;
+DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+DUARTCNT	.EQU	2		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
+DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
+DUART0ACFG	.EQU	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
+DUART0BCFG	.EQU	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
+DUART1BASE	.EQU	$40		; DUART 1: BASE ADDRESS OF CHIP
+DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
+DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
+;
+UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
+UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
+UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
+UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
+UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
+UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
+UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+;
+ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+ASCISWAP	.EQU	FALSE		; ASCI: SWAP CHANNELS
+ASCIBOOT	.EQU	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
+ASCI0CFG	.EQU	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
+ASCI1CFG	.EQU	DEFSERCFG	; ASCI 1: SERIAL LINE CONFIG
+;
+Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+;
+ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+;
+SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.EQU	SER_115200_8N1	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.EQU	7372800		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.EQU	SER_115200_8N1	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
+SIO1ACLK	.EQU	7372800		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1ACFG	.EQU	SER_115200_8N1	; SIO 1A: SERIAL LINE CONFIG
+SIO1ACTCC	.EQU	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1BCLK	.EQU	7372800		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1BCFG	.EQU	SER_115200_8N1	; SIO 1B: SERIAL LINE CONFIG
+SIO1BCTCC	.EQU	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+;
+XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+;
+VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
+TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+;
+MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+;
+FDENABLE	.EQU	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.EQU	FDMODE_EPFDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+;
+RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+;
+IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.EQU	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT		.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.EQU	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE0BASE	.EQU	$10		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.EQU	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.EQU	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.EQU	TRUE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.EQU	TRUE		; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.EQU	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE1BASE	.EQU	$00		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.EQU	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.EQU	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.EQU	TRUE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.EQU	TRUE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.EQU	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE2BASE	.EQU	$00		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.EQU	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.EQU	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.EQU	TRUE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.EQU	TRUE		; IDE 2B (MASTER): 8 BIT XFER
+;
+PPIDEENABLE	.EQU	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.EQU	$20		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1BASE	.EQU	$00		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE2BASE	.EQU	$00		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+;
+SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.EQU	SDMODE_EPITX	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|EPITX]
+SDPPIBASE	.EQU	$40		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
+SDTRACE		.EQU	2		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.EQU	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$3E		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.EQU	$3C		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	TRUE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+;
+PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+;
+PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
+HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+;
+LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTMODE		.EQU	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTCNT		.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
+LPTTRACE	.EQU	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+LPT0BASE	.EQU	$0C		; LPT 0: REGISTERS BASE ADR
+LPT1BASE	.EQU	$00		; LPT 1: REGISTERS BASE ADR
+;
+PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
+PPACNT		.EQU	1		; PPA: NUMBER OF PPA DEVICES (1-2)
+PPATRACE	.EQU	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPAMODE		.EQU	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
+PPA0BASE	.EQU	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
+PPA1BASE	.EQU	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
+;
+IMMENABLE	.EQU	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+IMMCNT		.EQU	1		; IMM: NUMBER OF IMM DEVICES (1-2)
+IMMTRACE	.EQU	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IMMMODE		.EQU	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
+IMM0BASE	.EQU	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
+IMM1BASE	.EQU	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
+;
+SYQENABLE	.EQU	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
+SYQCNT		.EQU	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
+SYQTRACE	.EQU	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SYQMODE		.EQU	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
+SYQ0BASE	.EQU	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQ1BASE	.EQU	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
+;
+PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+;
+UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+;
+SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
+SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
+;
+AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
+AYMODE		.EQU	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
+;
+SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+;
+DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
+;
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_heath.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_HEATH	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+PLATFORM	.EQU	PLT_HEATH	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,7 @@ DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.AS
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
@@ -90,6 +90,7 @@ PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
 VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
@@ -136,6 +137,7 @@ UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
 UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART

Source/HBIOS/cfg_master.asm

@@ -12,7 +12,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -31,7 +31,7 @@ DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_NONE		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MEMMGR		.EQU	MM_NONE		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
 RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
@@ -119,6 +119,7 @@ PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
 VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
@@ -166,6 +167,7 @@ UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
 UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
@@ -301,12 +303,12 @@ CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
 CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
-CH0BASE		.EQU	$BE		; CH 0: BASE I/O ADDRESS
+CHCNT		.EQU	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$3E		; CH 0: BASE I/O ADDRESS
 CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
 CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
-CH1BASE		.EQU	$FF		; CH 1: BASE I/O ADDRESS
-CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
+CH1BASE		.EQU	$3C		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	TRUE		; CH 1: ENABLE USB DISK
 CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
 ;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)

Source/HBIOS/cfg_mbc.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_MBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+PLATFORM	.EQU	PLT_MBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,7 @@ DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_MBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MEMMGR		.EQU	MM_MBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
 ;
@@ -85,6 +85,7 @@ PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
 VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
@@ -125,6 +126,7 @@ UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
 UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
@@ -225,6 +227,7 @@ SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
 CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
 ;

Source/HBIOS/cfg_mk4.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_MK4		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+PLATFORM	.EQU	PLT_MK4		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,7 @@ DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
 RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 ;
 Z180_BASE	.EQU	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
@@ -90,6 +90,7 @@ PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
 VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
@@ -130,6 +131,7 @@ UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
 UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	TRUE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	TRUE		; UART: AUTO-DETECT 4UART UART
@@ -234,6 +236,7 @@ SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	TRUE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
 CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
 ;

Source/HBIOS/cfg_mon.asm

@@ -0,0 +1,328 @@
+;
+;==================================================================================================
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR MONSPUTER Z80
+;==================================================================================================
+;
+; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
+; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
+; UNDER THIS DIRECTORY.
+;
+; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
+; FOR THE PLATFORM.
+;
+#DEFINE PLATFORM_NAME "Monsputer", " [", CONFIG, "]"
+;
+#INCLUDE "hbios.inc"
+;
+PLATFORM	.EQU	PLT_MON		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+;
+BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+;
+CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.EQU	4000000		; CPU OSC FREQ IN MHZ
+INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;
+RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+MEMMGR		.EQU	MM_MON		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
+;
+RTCIO		.EQU	$C0		; RTC LATCH REGISTER ADR
+;
+KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+;
+CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
+CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
+CTCMODE		.EQU	CTCMODE_TIM16	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
+CTCPRE		.EQU	256		; PRESCALE CONSTANT (1-256)
+CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
+CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
+CTCOSC		.EQU	CPUOSC		; CTC CLOCK FREQUENCY
+;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
+SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+SKZDIV		.EQU	DIV_1		; UART CLK (CLK2) DIVIDER FOR Z80-512K
+;
+WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+WDOGIO		.EQU	$6E		; WATCHDOG REGISTER ADR
+;
+FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+;
+DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+;
+LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
+LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|RTC]
+LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
+LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+;
+DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+;
+BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
+CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYENABLE	.EQU	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+;
+DSRTCENABLE	.EQU	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
+DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+;
+DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+;
+BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+;
+INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+;
+RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
+HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+;
+DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+;
+DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+DUARTCNT	.EQU	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
+DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
+DUART0ACFG	.EQU	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
+DUART0BCFG	.EQU	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
+DUART1BASE	.EQU	$40		; DUART 1: BASE ADDRESS OF CHIP
+DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
+DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
+;
+UARTENABLE	.EQU	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
+UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
+UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
+UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
+UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
+UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
+UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+;
+ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+;
+Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+;
+ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+ACIADEBUG	.EQU	FALSE		; ACIA: ENABLE DEBUG OUTPUT
+ACIACNT		.EQU	1		; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
+ACIA0BASE	.EQU	$80		; ACIA 0: REGISTERS BASE ADR
+ACIA0CLK	.EQU	CPUOSC		; ACIA 0: OSC FREQ IN HZ
+ACIA0DIV	.EQU	1		; ACIA 0: SERIAL CLOCK DIVIDER
+ACIA0CFG	.EQU	DEFSERCFG	; ACIA 0: SERIAL LINE CONFIG  (SEE STD.ASM)
+ACIA1BASE	.EQU	$40		; ACIA 1: REGISTERS BASE ADR
+ACIA1CLK	.EQU	CPUOSC		; ACIA 1: OSC FREQ IN HZ
+ACIA1DIV	.EQU	1		; ACIA 1: SERIAL CLOCK DIVIDER
+ACIA1CFG	.EQU	DEFSERCFG	; ACIA 1: SERIAL LINE CONFIG  (SEE STD.ASM)
+;
+SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.EQU	CPUOSC		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
+SIO1ACLK	.EQU	CPUOSC		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1ACFG	.EQU	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
+SIO1ACTCC	.EQU	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1BCLK	.EQU	CPUOSC		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1BCFG	.EQU	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
+SIO1BCTCC	.EQU	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+;
+XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+;
+VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
+TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+;
+MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+;
+FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+;
+RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+;
+IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.EQU	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT		.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.EQU	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE0BASE	.EQU	$10		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.EQU	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.EQU	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.EQU	TRUE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.EQU	TRUE		; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.EQU	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE1BASE	.EQU	$00		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.EQU	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.EQU	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.EQU	TRUE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.EQU	TRUE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.EQU	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE2BASE	.EQU	$00		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.EQU	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.EQU	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.EQU	TRUE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.EQU	TRUE		; IDE 2B (MASTER): 8 BIT XFER
+;
+PPIDEENABLE	.EQU	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.EQU	$20		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1BASE	.EQU	$00		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE2BASE	.EQU	$00		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+;
+SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.EQU	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$3E		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.EQU	$3C		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	TRUE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+;
+PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+;
+PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
+HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+;
+LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTMODE		.EQU	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTCNT		.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
+LPTTRACE	.EQU	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+LPT0BASE	.EQU	$0C		; LPT 0: REGISTERS BASE ADR
+LPT1BASE	.EQU	$00		; LPT 1: REGISTERS BASE ADR
+;
+PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
+PPACNT		.EQU	1		; PPA: NUMBER OF PPA DEVICES (1-2)
+PPATRACE	.EQU	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPAMODE		.EQU	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
+PPA0BASE	.EQU	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
+PPA1BASE	.EQU	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
+;
+IMMENABLE	.EQU	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+IMMCNT		.EQU	1		; IMM: NUMBER OF IMM DEVICES (1-2)
+IMMTRACE	.EQU	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IMMMODE		.EQU	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
+IMM0BASE	.EQU	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
+IMM1BASE	.EQU	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
+;
+SYQENABLE	.EQU	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
+SYQCNT		.EQU	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
+SYQTRACE	.EQU	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SYQMODE		.EQU	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
+SYQ0BASE	.EQU	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQ1BASE	.EQU	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
+;
+PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+;
+UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+;
+SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
+SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
+;
+AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
+AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
+;
+SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+;
+DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.EQU	DMAMODE_RC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
+;
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_n8.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_N8		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+PLATFORM	.EQU	PLT_N8		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,7 @@ DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_N8		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MEMMGR		.EQU	MM_N8		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
 RAMBIAS		.EQU	0		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 ;
 Z180_BASE	.EQU	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
@@ -92,6 +92,7 @@ PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
 VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
@@ -132,6 +133,7 @@ UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
 UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	TRUE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	TRUE		; UART: AUTO-DETECT 4UART UART
@@ -236,6 +238,7 @@ SDPPIBASE	.EQU	N8_PPI0		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
 CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
 ;

Source/HBIOS/cfg_rcz180.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+PLATFORM	.EQU	PLT_RCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,7 @@ DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.AS
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
 RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
@@ -96,6 +96,7 @@ PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
 VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
@@ -142,6 +143,7 @@ UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
 UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
@@ -251,16 +253,16 @@ SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
-CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHENABLE	.EQU	TRUE		; CH: ENABLE CH375/376 USB SUPPORT
 CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
-CH0BASE		.EQU	$BE		; CH 0: BASE I/O ADDRESS
+CHCNT		.EQU	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$3E		; CH 0: BASE I/O ADDRESS
 CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
 CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
-CH1BASE		.EQU	$FF		; CH 1: BASE I/O ADDRESS
-CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
+CH1BASE		.EQU	$3C		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	TRUE		; CH 1: ENABLE USB DISK
 CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
 ;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)

Source/HBIOS/cfg_rcz280.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RCZ280	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+PLATFORM	.EQU	PLT_RCZ280	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z280	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,7 @@ DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.AS
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
 RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
@@ -90,6 +90,7 @@ PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
 VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
@@ -136,6 +137,7 @@ UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
 UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
@@ -255,16 +257,16 @@ SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
-CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHENABLE	.EQU	TRUE		; CH: ENABLE CH375/376 USB SUPPORT
 CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
-CH0BASE		.EQU	$BE		; CH 0: BASE I/O ADDRESS
+CHCNT		.EQU	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$3E		; CH 0: BASE I/O ADDRESS
 CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
 CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
-CH1BASE		.EQU	$FF		; CH 1: BASE I/O ADDRESS
-CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
+CH1BASE		.EQU	$3C		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	TRUE		; CH 1: ENABLE USB DISK
 CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
 ;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)

Source/HBIOS/cfg_rcz80.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RCZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+PLATFORM	.EQU	PLT_RCZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,7 @@ DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.AS
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
@@ -90,6 +90,7 @@ PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
 VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
@@ -136,6 +137,7 @@ UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
 UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
@@ -250,16 +252,16 @@ SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
-CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHENABLE	.EQU	TRUE		; CH: ENABLE CH375/376 USB SUPPORT
 CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
-CH0BASE		.EQU	$BE		; CH 0: BASE I/O ADDRESS
+CHCNT		.EQU	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$3E		; CH 0: BASE I/O ADDRESS
 CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
 CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
-CH1BASE		.EQU	$FF		; CH 1: BASE I/O ADDRESS
-CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
+CH1BASE		.EQU	$3C		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	TRUE		; CH 1: ENABLE USB DISK
 CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
 ;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)

Source/HBIOS/cfg_rph.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RPH		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+PLATFORM	.EQU	PLT_RPH		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	TRUE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,7 @@ DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_RPH		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MEMMGR		.EQU	MM_RPH		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
 RAMBIAS		.EQU	0		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 ;
 Z180_BASE	.EQU	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
@@ -90,6 +90,7 @@ PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
 VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
@@ -130,6 +131,7 @@ UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
 UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
@@ -225,6 +227,7 @@ SDPPIBASE	.EQU	RPH_PPI0	; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
 CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
 ;

Source/HBIOS/cfg_s100.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_S100	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+PLATFORM	.EQU	PLT_S100	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,7 @@ DEFSERCFG	.EQU	SER_57600_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
 RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
@@ -90,6 +90,7 @@ PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
 VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
@@ -136,6 +137,7 @@ UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
 UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART

Source/HBIOS/cfg_sbc.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,7 @@ DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MEMMGR		.EQU	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
 ;
@@ -85,6 +85,7 @@ PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
 VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
@@ -125,6 +126,7 @@ UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
 UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	TRUE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	TRUE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	TRUE		; UART: AUTO-DETECT 4UART UART
@@ -224,6 +226,7 @@ SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
 CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
 ;

Source/HBIOS/cfg_scz180.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_SCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+PLATFORM	.EQU	PLT_SCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,7 @@ DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.AS
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
 RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
@@ -90,6 +90,7 @@ PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
 VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
@@ -135,6 +136,7 @@ UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
 UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
@@ -245,16 +247,16 @@ SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
-CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHENABLE	.EQU	TRUE		; CH: ENABLE CH375/376 USB SUPPORT
 CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
-CH0BASE		.EQU	$BE		; CH 0: BASE I/O ADDRESS
+CHCNT		.EQU	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$3E		; CH 0: BASE I/O ADDRESS
 CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
 CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
-CH1BASE		.EQU	$FF		; CH 1: BASE I/O ADDRESS
-CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
+CH1BASE		.EQU	$3C		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	TRUE		; CH 1: ENABLE USB DISK
 CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
 ;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)

Source/HBIOS/cfg_una.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "../UBIOS/ubios.inc"
 ;
-;PLATFORM	.EQU	PLT_UNA		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+;PLATFORM	.EQU	PLT_UNA		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_UNA	; HARDWARE BIOS: BIOS_[WBW|UNA]
 ;

Source/HBIOS/cfg_z80retro.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_Z80RETRO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+PLATFORM	.EQU	PLT_Z80RETRO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,7 @@ DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
 MPGSEL_0	.EQU	$60		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$61		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$62		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
@@ -88,6 +88,7 @@ PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
 VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
@@ -122,6 +123,7 @@ UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
 UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
@@ -198,6 +200,7 @@ SDMODE		.EQU	SDMODE_Z80R	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
 CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
 ;

Source/HBIOS/cfg_zeta.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_ZETA	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+PLATFORM	.EQU	PLT_ZETA	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; BIOS_[WBW|UNA]: HARDWARE BIOS
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -28,13 +28,13 @@ BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
 ;
 CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
-CPUOSC		.EQU	20000000	; CPU OSC FREQ IN MHZ
+CPUOSC		.EQU	8000000		; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MEMMGR		.EQU	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
 ;
@@ -77,6 +77,7 @@ PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
 VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
@@ -112,6 +113,7 @@ UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
 UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
@@ -169,6 +171,7 @@ SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
 CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
 ;

Source/HBIOS/cfg_zeta2.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_ZETA2	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
+PLATFORM	.EQU	PLT_ZETA2	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -34,7 +34,7 @@ DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
@@ -88,6 +88,7 @@ PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
 VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
@@ -123,6 +124,7 @@ UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
 UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
@@ -180,6 +182,7 @@ SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
 CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
 ;

Source/HBIOS/ch.asm

@@ -18,9 +18,8 @@
 ;    added to the RESET routine when using CH376.
 ;
 ; TODO:
-;  - Implement auto-recovery on error status.
-;
-CHUSB_FASTIO	.EQU	TRUE		; USE INIR/OTIR?
+;  - Implement auto-recovery on error status?
+;  - !!! Move CH_MODE to config variable !!!
 ;
 ; PORT OFFSETS FROM BASE PORT
 ;
@@ -33,6 +32,12 @@ CHTYP_NONE	.EQU	0		; NONE
 CHTYP_375	.EQU	1		; CH375
 CHTYP_376	.EQU	2		; CH376
 ;
+; CH MODE MANAGEMENT
+;
+CH_MODE_UNK	.EQU	0		; CURRENT MODE UNKNOWN
+CH_MODE_USB	.EQU	1		; CURRENT MODE = USB
+CH_MODE_SD	.EQU	2		; CURRENT MODE = SD
+;
 ; CH375/376 COMMANDS
 ;
 CH_CMD_VER	.EQU	$01		; GET IC VER
@@ -41,6 +46,7 @@ CH_CMD_EXIST	.EQU	$06		; CHECK EXISTS
 CH_CMD_MAXLUN	.EQU	$0A		; GET MAX LUN NUMBER
 CH_CMD_PKTSEC	.EQU	$0B		; SET PACKETS PER SECTOR
 CH_CMD_SETRETRY	.EQU	$0B		; SET RETRIES
+CH_CMD_FILESIZE	.EQU	$0C		; GET FILE SIZE (376)
 CH_CMD_MODE	.EQU	$15		; SET USB MODE
 CH_CMD_TSTCON	.EQU	$16		; TEST CONNECT
 CH_CMD_ABRTNAK	.EQU	$17		; ABORT DEVICE NAK RETRIES
@@ -49,7 +55,16 @@ CH_CMD_RD6	.EQU	$27		; READ USB DATA (375 & 376)
 CH_CMD_RD5	.EQU	$28		; READ USB DATA (375)
 CH_CMD_WR5	.EQU	$2B		; WRITE USB DATA (375)
 CH_CMD_WR6	.EQU	$2C		; WRITE USB DATA (376)
+CH_CMD_WRREQDAT	.EQU	$2D		; WRITE REQUESTED DATA (376)
+CH_CMD_SET_FN	.EQU	$2F		; SET FILENAME (376)
 CH_CMD_DSKMNT	.EQU	$31		; DISK MOUNT
+CH_CMD_FOPEN	.EQU	$32		; FILE OPEN (376)
+CH_CMD_FCREAT	.EQU	$34		; FILE CREATE (376)
+CH_CMD_BYTE_LOC	.EQU	$39		; BYTE LOCATE
+CH_CMD_BYTERD	.EQU	$3A		; BYTE READ
+CH_CMD_BYTERDGO	.EQU	$3B		; BYTE READ GO
+CH_CMD_BYTEWR	.EQU	$3C		; BYTE WRITE
+CH_CMD_BYTEWRGO	.EQU	$3D		; BYTE WRITE GO
 CH_CMD_DSKCAP	.EQU	$3E		; DISK CAPACITY
 CH_CMD_AUTOSET	.EQU	$4D		; USB AUTO SETUP
 CH_CMD_DSKINIT	.EQU	$51		; DISK INIT
@@ -87,6 +102,10 @@ CH_CFG0:	; DEVICE 0
 	.DW	CHUSB_CFG0		; USB SUB-DRIVER INIT ADR
 	.DB	CH0SDENABLE		; ENABLE SD CARD SUB-DRIVER
 	.DW	CHSD_CFG0		; SD CARD SUB-DRIVER INIT ADR
+;
+	.ECHO	"CH: IO="
+	.ECHO	CH0BASE
+	.ECHO	"\n"
 #ENDIF
 ;
 #IF (CHCNT >= 2)
@@ -98,6 +117,10 @@ CH_CFG1:	; DEVICE 1
 	.DW	CHUSB_CFG1		; USB SUB-DRIVER INIT ADR
 	.DB	CH1SDENABLE		; ENABLE SD CARD SUB-DRIVER
 	.DW	CHSD_CFG1		; SD CARD SUB-DRIVER INIT ADR
+;
+	.ECHO	"CH: IO="
+	.ECHO	CH1BASE
+	.ECHO	"\n"
 #ENDIF
 ;
 #IF ($ - CH_CFGTBL) != (CHCNT * CH_CFGSIZ)
@@ -129,8 +152,17 @@ CH_INIT2:
 	LD	A,(IY+CH_IOBASE)	; GET IO BASE ADDRES
 	CALL	PRTHEXBYTE		; DISPLAY IT
 ;
+	XOR	A			; UNKNOWN MODE
+	LD	(CH_MODE),A		; SAVE IT
 	;CALL	CH_FLUSH		; FLUSH DEVICE OUTPUT QUEUE
-	CALL	CH_RESET		; FULL CH37X RESET
+;
+	; I AM ENCOUNTERING SOME CH376 CHIPS THAT GO HAYWIRE AFTER A
+	; RESET COMMAND.  THEY STOP RESPONDING FOR A VERY LONG TIME.
+	; I AM SEEING THIS ONLY ON "LC TECH" ADAPTERS AND ONLY ON Z80
+	; SYSTEMS (NOT Z180).  NO IDEA WHAT IS GOING ON, SO I AM
+	; GIVING UP FOR NOW AND REMOVING THE RESET.
+	;CALL	CH_RESET		; FULL CH37X RESET
+;
 	CALL	CH_DETECT		; DETECT CHIP PRESENCE
 	JR	Z,CH_INIT3		; GO AHEAD IF CHIP FOUND
 	LD	DE,CH_STR_NOHW		; NOT PRESENT
@@ -347,18 +379,63 @@ CH_GETVER:
 	CALL	CH_RD			; GET VERSION BYTE
 	RET				; DONE
 ;
+; SET MODE TO VALUE IN A
+; AVOID CHANGING MODES IF CURRENT MODE = NEW MODE
+; THE CH376 DOES NOT SEEM TO MAINTAIN SEPARATE OPERATING CONTEXTS FOR
+; THE USB AND SD DEVICES.  IF BOTH ARE IN OPERATION, THEN A MODE
+; SWITCH REQUIRES A COMPLETE REINITIALIZATION OF THE REQUESTED
+; DEVICE.
+;
+CH_SETMODE:
+	PUSH	BC			; SAVE BC
+	PUSH	DE			; SAVE DE
+	PUSH	HL			; SAVE HL
+	;PRTS("\r\nSETMODE:$")		; *DEBUG*
+	LD	L,A			; SAVE REQUESTED MODE
+	LD	A,(CH_MODE)		; GET CURRENT MODE
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CP	L			; COMPARE
+	JR	Z,CH_SETMODE_Z		; IF EQUAL, DONE
+;
+	; NEED TO CHANGE MODES
+	LD	A,L			; GET REQUESTED MODE
+	CP	CH_MODE_USB		; USB?
+	JR	Z,CH_SETMODE_USB	; IF SO, DO IT
+	CP	CH_MODE_SD		; SD?
+	JR	Z,CH_SETMODE_SD		; IF SO, DO IT
+	OR	$FF			; SIGNAL ERROR
+	JR	CH_SETMODE_Z		; BAIL OUT
+;
+CH_SETMODE_USB:
+	CALL	CHUSB_RESET		; FULL USB STACK RESET
+	JR	CH_SETMODE_Z		; MOVE ON
+;
+CH_SETMODE_SD:
+	CALL	CHSD_RESET		; FULL SD STACK RESET
+	JR	CH_SETMODE_Z		; MOVE ON
+;
+CH_SETMODE_Z:
+	POP	HL			; RECOVER HL
+	POP	DE			; RECOVER DE
+	POP	BC			; RECOVER BC
+	RET				; DONE
 ;
 ;
-CH_STR_NOHW		.TEXT	" NOT PRESENT$"
-CH_STR_UPGRADE		.TEXT	" !!!UPGRADE REQUIRED!!!$"
 ;
-CH_STR_375		.TEXT	"CH375$"
-CH_STR_376		.TEXT	"CH376$"
+CH_MODE		.DB	CH_MODE_UNK
+;
+CH_STR_NOHW	.TEXT	" NOT PRESENT$"
+;
+CH_STR_375	.TEXT	"CH375$"
+CH_STR_376	.TEXT	"CH376$"
 ;
 ;==================================================================================================
 ; CH375/376 USB SUB-DRIVER
 ;==================================================================================================
 ;
+CHUSB_FASTIO	.EQU	TRUE		; USE INIR/OTIR?
+;
 ; CHUSB DEVICE STATUS
 ;
 CHUSB_STOK	.EQU	0
@@ -368,7 +445,7 @@ CHUSB_STIOERR	.EQU	-3
 CHUSB_STTO	.EQU	-4
 CHUSB_STNOTSUP	.EQU	-5
 ;
-; CH DEVICE CONFIGURATION
+; CHUSB DEVICE CONFIGURATION
 ;
 CHUSB_CFGSIZ	.EQU	12		; SIZE OF USB CFG TBL ENTRIES
 ;
@@ -389,6 +466,12 @@ CHUSB_CFG0:
 	.DB	0			; DEVICE STATUS
 	.DW	0,0			; DEVICE CAPACITY
 	.DW	0,0			; CURRENT LBA
+;
+  #IF (CH0USBENABLE)
+	.ECHO	"CHUSB: IO="
+	.ECHO	CH0BASE
+	.ECHO	"\n"
+  #ENDIF
 #ENDIF
 ;
 #IF (CHCNT >= 2)
@@ -399,6 +482,12 @@ CHUSB_CFG1:
 	.DB	0			; DEVICE STATUS
 	.DW	0,0			; DEVICE CAPACITY
 	.DW	0,0			; CURRENT LBA
+;
+  #IF (CH1USBENABLE)
+	.ECHO	"CHUSB: IO="
+	.ECHO	CH1BASE
+	.ECHO	"\n"
+  #ENDIF
 #ENDIF
 ;
 #IF ($ - CHUSB_CFGTBL) != (CHCNT * CHUSB_CFGSIZ)
@@ -481,6 +570,10 @@ CHUSB_DEFMED:
 ;
 ;
 CHUSB_READ:
+	LD	A,CH_MODE_USB		; REQUEST USB MODE
+	CALL	CH_SETMODE		; DO IT
+	JP	NZ,CHUSB_CMDERR		; HANDLE ERROR
+;
 	CALL	HB_DSKREAD		; HOOK HBIOS DISK READ SUPERVISOR
 	LD	(CHUSB_DSKBUF),HL	; SAVE DISK BUFFER ADDRESS
 	LD	A,CH_CMD_DSKRD		; DISK READ COMMAND
@@ -542,6 +635,10 @@ CHUSB_READ2:
 ;
 ;
 CHUSB_WRITE:
+	LD	A,CH_MODE_USB		; REQUEST USB MODE
+	CALL	CH_SETMODE		; DO IT
+	JP	NZ,CHUSB_CMDERR		; HANDLE ERROR
+;
 	CALL	HB_DSKWRITE		; HOOK HBIOS DISK WRITE SUPERVISOR
 	LD	(CHUSB_DSKBUF),HL	; SAVE DISK BUFFER ADDRESS
 	LD	A,CH_CMD_DSKWR		; DISK READ COMMAND
@@ -631,7 +728,7 @@ CHUSB_STATUS:
 ; RESET THE INTERFACE AND REDISCOVER MEDIA
 ;
 CHUSB_RESET:
-	;PRTS("\n\rRESET:$")		; *DEBUG*
+	;PRTS("\n\rRES USB:$")		; *DEBUG*
 	;CALL	CH_FLUSH		; DISCARD ANY GARBAGE
 	;CALL	CH_RESET		; FULL CH37X RESET
 ;
@@ -656,6 +753,9 @@ CHUSB_RESET:
 	;CALL	PC_SPACE		; *DEBUG*
 	;CALL	PRTHEXBYTE		; *DEBUG*
 	CALL	CH_NAP			; SMALL WAIT
+;
+	LD	A,CH_MODE_USB		; WE ARE NOW IN USB MODE
+	LD	(CH_MODE),A		; SAVE IT
 ;
 	; INITIALIZE DISK
 	LD	B,24			; TRY A FEW TIMES
@@ -671,29 +771,28 @@ CHUSB_RESET1:
 	;CALL	PC_SPACE		; *DEBUG*
 	;CALL	PRTHEXBYTE		; *DEBUG*
 	CP	$14			; SUCCESS?
-	JR	Z,CHUSB_RESET2		; IF SO, CONTINUE
-	;JR	Z,CHUSB_RESET1A		; IF SO, CHECK READY
+	JR	Z,CHUSB_RESET1A		; IF SO, CHECK READY
 	CP	$16			; NO MEDIA
 	JP	Z,CHUSB_NOMEDIA		; HANDLE IT
 	CALL	CH_NAP			; SMALL DELAY
 	DJNZ	CHUSB_RESET1		; LOOP AS NEEDED
 	JP	CHUSB_TO		; HANDLE TIMEOUT
-;;;;
-;;;CHUSB_RESET1A:
-;;;	CALL	CHUSB_DSKRES		; DISK RESET
-;;;	CP	$14			; GOOD?
-;;;	JR	Z,CHUSB_RESET2
-;;;	CALL	CHUSB_DSKRDY		; CHECK IF DISK READY
-;;;	CP	$14			; GOOD?
-;;;	JR	Z,CHUSB_RESET2		; IF SO, MOVE ON
-;;;	DJNZ	CHUSB_RESET1		; KEEP TRYING
+;
+CHUSB_RESET1A:
+	;CALL	CHUSB_DSKRES		; DISK RESET
+	;CP	$14			; GOOD?
+	;JR	Z,CHUSB_RESET2
+	;CALL	CHUSB_DSKRDY		; CHECK IF DISK READY
+	;CP	$14			; GOOD?
+	;JR	Z,CHUSB_RESET2		; IF SO, MOVE ON
+	;DJNZ	CHUSB_RESET1		; KEEP TRYING
 ;
 CHUSB_RESET2:
 	; USE OF CH376 DISK_MOUNT COMMAND SEEMS TO IMPROVE
 	; COMPATIBILITY WITH SOME OLDER USB THUMBDRIVES.
 	LD	A,(IY+CH_TYPE)		; CH37X TYPE?
 	CP	CHTYP_376		; IS CH376?
-	CALL	Z,CHUSB_DSKMNT		; IF SO, ISSUE MOUNT
+	CALL	Z,CHUSB_DSKMNT		; IF SO, TRY MOUNT, IGNORE ERRS
 	;CALL	CHUSB_AUTOSET		; *DEBUG*
 	;CALL	CHUSB_TSTCON		; *DEBUG*
 	;CALL	CHUSB_MAXLUN		; *DEBUG*
@@ -714,7 +813,7 @@ CHUSB_RESET2:
 CHUSB_DEVICE:
 	LD	D,DIODEV_CHUSB		; D := DEVICE TYPE
 	LD	E,(IY+CH_DEV)		; E := PHYSICAL DEVICE NUMBER
-	LD	C,%01110011		; USB HARD DISK ATTRIBUTES
+	LD	C,%00110011		; USB HARD DISK ATTRIBUTES
 	LD	H,(IY+CH_TYPE)		; H := MODE
 	LD	L,(IY+CH_IOBASE)	; L := BASE I/O ADDRESS
 	XOR	A			; SIGNAL SUCCESS
@@ -791,28 +890,34 @@ CHUSB_DSKMNT:
 	;CALL	PRTHEXBYTE		; *DEBUG*
 	CP	$14			; SUCCESS?
 	RET	NZ			; ABORT IF NOT
+;
+#IF FALSE
 	CALL	CH_CMD_RD		; SEND READ COMMAND
 	CALL	CH_RD			; GET LENGTH
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
 	LD	B,A			; LOOP COUNTER
 	LD	HL,HB_WRKBUF		; USE WORK BUFFER FOR DATA
-DSKMNT1:
+CHUSB_DSKMNT1:
 	CALL	CH_RD			; GET A BYTE
 	LD	(HL),A			; SAVE IT
 	INC	HL			; BUMP BUF PTR
-	DJNZ	DSKMNT1			; LOOP FOR ALL DATA
+	DJNZ	CHUSB_DSKMNT1		; LOOP FOR ALL DATA
 ;
 	;LD	DE,HB_WRKBUF		; *DEBUG*
 	;CALL	DUMP_BUFFER		; *DEBUG*
 ;
-	;CALL	CHUSB_PRTPREFIX		; PRINT DEVICE PREFIX
-	;LD	HL,HB_WRKBUF + 8
-	;LD	B,28
-DSKMNT2:
-	;LD	A,(HL)
-	;INC	HL
-	;CALL	COUT
-	;DJNZ	DSKMNT2
+	CALL	CHUSB_PRTPREFIX		; PRINT DEVICE PREFIX
+	LD	HL,HB_WRKBUF + 8
+	LD	B,28
+CHUSB_DSKMNT2:
+	LD	A,(HL)
+	INC	HL
+	CALL	COUT
+	DJNZ	CHUSB_DSKMNT2
+#ENDIF
 ;
+	XOR	A
 	RET
 ;
 ; PERFORM DISK SIZE
@@ -1081,17 +1186,30 @@ CHUSB_STR_ST_MAP:
 CHUSB_STR_STOK		.TEXT	"OK$"
 CHUSB_STR_STNOMEDIA	.TEXT	"NO MEDIA$"
 CHUSB_STR_STCMDERR	.TEXT	"COMMAND ERROR$"
-CHUSB_STR_STIOERR		.TEXT	"IO ERROR$"
+CHUSB_STR_STIOERR	.TEXT	"IO ERROR$"
 CHUSB_STR_STTO		.TEXT	"TIMEOUT$"
 CHUSB_STR_STNOTSUP	.TEXT	"NOT SUPPORTED$"
 CHUSB_STR_STUNK		.TEXT	"UNKNOWN ERROR$"
-
 ;
 ;==================================================================================================
 ; CH375/376 SD CARD SUB-DRIVER
 ;==================================================================================================
 ;
-; CH DEVICE CONFIGURATION
+#DEFINE	CHSD_IMGFILE "DISK.IMG"
+;
+CHSD_FASTIO	.EQU	TRUE		; USE INIR/OTIR?
+;
+; CHUSB DEVICE STATUS
+;
+CHSD_STOK	.EQU	0
+CHSD_STNOMEDIA	.EQU	-1
+CHSD_STCMDERR	.EQU	-2
+CHSD_STIOERR	.EQU	-3
+CHSD_STTO	.EQU	-4
+CHSD_STNOTSUP	.EQU	-5
+CHSD_STNOFILE	.EQU	-6
+;
+; CHSD DEVICE CONFIGURATION
 ;
 CHSD_CFGSIZ	.EQU	12		; SIZE OF USB CFG TBL ENTRIES
 ;
@@ -1112,6 +1230,12 @@ CHSD_CFG0:
 	.DB	0			; DEVICE STATUS
 	.DW	0,0			; DEVICE CAPACITY
 	.DW	0,0			; CURRENT LBA
+;
+  #IF (CH0SDENABLE)
+	.ECHO	"CHSD: IO="
+	.ECHO	CH0BASE
+	.ECHO	"\n"
+  #ENDIF
 #ENDIF
 ;
 #IF (CHCNT >= 2)
@@ -1122,6 +1246,12 @@ CHSD_CFG1:
 	.DB	0			; DEVICE STATUS
 	.DW	0,0			; DEVICE CAPACITY
 	.DW	0,0			; CURRENT LBA
+;
+  #IF (CH1SDENABLE)
+	.ECHO	"CHSD: IO="
+	.ECHO	CH1BASE
+	.ECHO	"\n"
+  #ENDIF
 #ENDIF
 ;
 #IF ($ - CHSD_CFGTBL) != (CHCNT * CHSD_CFGSIZ)
@@ -1144,36 +1274,581 @@ CHSD_INIT:
 	INC	A			; BUMP TO NEXT UNIT NUM TO ASSIGN
 	LD	(CHSD_DEVNUM),A		; SAVE IT
 ;
-	CALL	NEWLINE			; FORMATTING
-	PRTS("CHSD$")			; LABEL FOR IO ADDRESS
-	LD	A,(IY+CH_DEV)		; GET DEVICE NUM
-	CALL	PRTDECB			; PRINT IT
-	CALL	PC_COLON		; FORMATTING
+	; ADD UNIT TO GLOBAL DISK UNIT TABLE
+	LD	BC,CHSD_FNTBL		; BC := FUNC TABLE ADR
+	PUSH	IY			; CFG ENTRY POINTER
+	POP	DE			; COPY TO DE
+	CALL	DIO_ADDENT		; ADD ENTRY TO GLOBAL DISK DEV TABLE
 ;
+	CALL	CHSD_RESET		; RESET & DISCOVER MEDIA
+#IF (CHSDTRACE <= 1)
+	CALL	NZ,CHSD_PRTSTAT
+#ENDIF
+	RET	NZ			; ABORT ON FAILURE
+;
+	; START PRINTING DEVICE INFO
+	CALL	CHSD_PRTPREFIX		; PRINT DEVICE PREFIX
+;
+	; PRINT STORAGE CAPACITY (BLOCK COUNT)
+	PRTS(" BLOCKS=0x$")		; PRINT FIELD LABEL
+	LD	A,CHSD_MEDCAP		; OFFSET TO CAPACITY FIELD
+	CALL	LDHLIYA			; HL := IY + A, REG A TRASHED
+	CALL	LD32			; GET THE CAPACITY VALUE
+	CALL	PRTHEX32		; PRINT HEX VALUE
+;
+	; PRINT STORAGE SIZE IN MB
+	PRTS(" SIZE=$")			; PRINT FIELD LABEL
+	LD	B,11			; 11 BIT SHIFT TO CONVERT BLOCKS --> MB
+	CALL	SRL32			; RIGHT SHIFT
+	CALL	PRTDEC32		; PRINT DWORD IN DECIMAL
+	PRTS("MB$")			; PRINT SUFFIX
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; DRIVER FUNCTION TABLE
+;
+CHSD_FNTBL:
+	.DW	CHSD_STATUS
+	.DW	CHSD_RESET
+	.DW	CHSD_SEEK
+	.DW	CHSD_READ
+	.DW	CHSD_WRITE
+	.DW	CHSD_VERIFY
+	.DW	CHSD_FORMAT
+	.DW	CHSD_DEVICE
+	.DW	CHSD_MEDIA
+	.DW	CHSD_DEFMED
+	.DW	CHSD_CAP
+	.DW	CHSD_GEOM
+#IF (($ - CHSD_FNTBL) != (DIO_FNCNT * 2))
+	.ECHO	"*** INVALID CHSD FUNCTION TABLE ***\n"
+#ENDIF
+;
+CHSD_VERIFY:
+CHSD_FORMAT:
+CHSD_DEFMED:
+	SYSCHKERR(ERR_NOTIMPL)		; NOT IMPLEMENTED
+	RET
+;
+;
+;
+CHSD_READ:
+	LD	A,CH_MODE_SD		; REQUEST SD MODE
+	CALL	CH_SETMODE		; DO IT
+	JP	NZ,CHSD_CMDERR		; HANDLE ERROR
+;
+	CALL	HB_DSKREAD		; HOOK HBIOS DISK READ SUPERVISOR
+	LD	(CHSD_DSKBUF),HL	; SAVE DISK BUFFER ADDRESS
+	CALL	CHSD_RWSTART		; SET LBA OFFSET
+	RET	NZ
+;
+	;PRTS("\n\rREAD:$")		; *DEBUG*
+	LD	A,CH_CMD_BYTERD		; BYTE READ
+	CALL	CH_CMD			; SEND COMMAND
+	CALL	CH_NAP
+	LD	A,0			; LSB
+	CALL	CH_WR			; SEND IT
+	LD	A,2			; MSB
+	CALL	CH_WR			; SEND IT
+	CALL	CH_POLL			; GET RESULT
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CP	$1D			; DATA READY TO READ?
+	JP	NZ,CHSD_IOERR		; HANDLE I/O ERROR
+;
+	LD	HL,(CHSD_DSKBUF)
+CHSD_READ1:
+	CALL	CH_CMD_RD		; SEND READ USB DATA CMD
+	CALL	CH_RD			; GET DATA LENGTH
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+;
+#IF (CHSD_FASTIO)
+	LD	B,A			; BYTE COUNT TO READ
+	LD	C,(IY+CH_IOBASE)	; BASE PORT
+	INIR				; DO IT FAST
+#ELSE
+	LD	B,A			; SAVE IT
+CHSD_READ2:
+	CALL	CH_RD			; GET DATA BYTE
+	LD	(HL),A			; SAVE IN BUFFER
+	INC	HL			; INC BUF PTR
+	DJNZ	CHSD_READ2		; LOOP TILL DONE W/ ALL BYTES
+#ENDIF
+;
+	LD	A,CH_CMD_BYTERDGO	; BYTE READ GO COMMAND
+	CALL	CH_CMD			; SEND IT
+	CALL	CH_NAP
+	CALL	CH_POLL			; GET RESULT
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CP	$1D			; MORE?
+	JR	Z,CHSD_READ1		; IF SO, GET MORE
+	CP	$14			; GOOD FINISH?
+	JP	NZ,CHSD_IOERR		; HANDLE ERROR
+;
+	; INCREMENT LBA
+	PUSH	HL			; SAVE HL
+	LD	A,CHSD_LBA		; LBA OFFSET
+	CALL	LDHLIYA			; HL := IY + A, REG A TRASHED
+	CALL	INC32HL			; INCREMENT THE VALUE
+	POP	HL			; RESTORE HL
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+;
+;
+CHSD_WRITE:
+	LD	A,CH_MODE_SD		; REQUEST SD MODE
+	CALL	CH_SETMODE		; DO IT
+	JP	NZ,CHSD_CMDERR		; HANDLE ERROR
+;
+	CALL	HB_DSKWRITE		; HOOK HBIOS DISK WRITE SUPERVISOR
+	LD	(CHSD_DSKBUF),HL	; SAVE DISK BUFFER ADDRESS
+	CALL	CHSD_RWSTART		; SET LBA OFFSET'
+	RET	NZ
+;
+	;PRTS("\n\rWRITE:$")		; *DEBUG*
+	LD	A,CH_CMD_BYTEWR		; BYTE WRITE
+	CALL	CH_CMD			; SEND COMMAND
+	LD	A,0			; LSB
+	CALL	CH_WR			; SEND IT
+	LD	A,2			; MSB
+	CALL	CH_WR			; SEND IT
+	CALL	CH_POLL			; GET RESULT
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CP	$1E			; DATA READY TO GO?
+	JP	NZ,CHSD_IOERR		; HANDLE I/O ERROR
+;
+	LD	HL,(CHSD_DSKBUF)
+CHSD_WRITE1:
+	LD	A,CH_CMD_WRREQDAT	; WRITE REQUESTED DATA CMD
+	CALL	CH_CMD			; SEND IT
+	CALL	CH_RD			; GET DATA LENGTH
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+;
+#IF (CHSD_FASTIO)
+	LD	B,A			; BYTE COUNT TO WRITE
+	LD	C,(IY+CH_IOBASE)	; BASE PORT
+	OTIR				; DO IT FAST
+#ELSE
+	LD	B,A			; SAVE IT
+CHSD_WRITE2:
+	CALL	CH_WR			; WRITE DATA BYTE
+	LD	(HL),A			; SAVE IN BUFFER
+	INC	HL			; INC BUF PTR
+	DJNZ	CHSD_WRITE2		; LOOP TILL DONE W/ ALL BYTES
+#ENDIF
+;
+	LD	A,CH_CMD_BYTEWRGO	; BYTE WRITE GO COMMAND
+	CALL	CH_CMD			; SEND IT
+	CALL	CH_NAP
+	CALL	CH_POLL			; GET RESULT
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CP	$1E			; MORE?
+	JR	Z,CHSD_WRITE1		; IF SO, SEND MORE
+	CP	$14			; GOOD FINISH?
+	JP	NZ,CHSD_IOERR		; HANDLE ERROR
+;
+	; INCREMENT LBA
+	PUSH	HL			; SAVE HL
+	LD	A,CHSD_LBA		; LBA OFFSET
+	CALL	LDHLIYA			; HL := IY + A, REG A TRASHED
+	CALL	INC32HL			; INCREMENT THE VALUE
+	POP	HL			; RESTORE HL
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; SEEK TO CURRENT LBA
+;
+CHSD_RWSTART:
+	;PRTS("\n\rRWST:$")		; *DEBUG*
+	LD	A,CH_CMD_BYTE_LOC	; BYTE LOCATE COMMAND (SEEK)
+	CALL	CH_CMD			; SEND IT
+;
+	; GET CURRENT LBA OFFSET
+	LD	A,CHSD_LBA		; OFFSET TO CAPACITY FIELD
+	CALL	LDHLIYA			; HL := IY + A, REG A TRASHED
+	CALL	LD32			; OFFSET = DE:HL
+;
+	; CONVERT OFFSET FROM LBA TO BYTE
+	LD	B,9
+CHSD_RWSTART1:
+	SLA	L
+	RL	H
+	RL	E
+	RL	D
+	DJNZ	CHSD_RWSTART1
+	;CALL	PRTHEX32		; *DEBUG*
+;
+	; SEND THE BYTE OFFSET (LSB FIRST)
+	LD	A,L
+	CALL	CH_WR
+	LD	A,H
+	CALL	CH_WR
+	LD	A,E
+	CALL	CH_WR
+	LD	A,D
+	CALL	CH_WR
+;
+	CALL	CH_POLL			; WAIT FOR RESPONSE
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CP	$14			; CHECK RESULT
+	JP	NZ,CHUSB_CMDERR		; HANDLE CMD ERROR
+;
+	XOR	A
+	RET
+;
+;
+;
+CHSD_STATUS:
+	; RETURN UNIT STATUS
+	LD	A,(IY+CHSD_STAT)	; GET STATUS OF SELECTED DEVICE
+	OR	A			; SET FLAGS
+	RET				; AND RETURN
+;
+; RESET THE INTERFACE AND REDISCOVER MEDIA
+;
+CHSD_RESET:
+	;PRTS("\n\rRES SD:$")		; *DEBUG*
+;
+	; ACTIVATE SD MODE
+	LD	A,CH_CMD_MODE		; SET MODE COMMAND
+	CALL	CH_CMD			; SEND IT
+	LD	A,3			; SD MODE
+	CALL	CH_WR			; SEND IT
+	CALL	CH_NAP			; SMALL WAIT
+	CALL	CH_RD			; GET RESULT
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CALL	CH_NAP			; SMALL WAIT
+;
+	LD	A,CH_MODE_SD		; WE ARE NOW IN SD MODE
+	LD	(CH_MODE),A		; SAVE IT
+;
+	CALL	CHSD_DSKMNT		; MOUNT DISK
+	RET	NZ
+;
+	; OPEN DISK IMAGE FILE
+	LD	DE,CHSD_FNAME
+	CALL	CHSD_FOPEN
+	RET	NZ
+;
+	; GET FILESIZE
+	CALL	CHSD_FILESIZE
+	RET	NZ
+;
+	; SET STATUS AND RETURN
+	XOR	A			; CLEAR STATUS
+	LD	(IY+CHSD_STAT),A	; RECORD STATUS
+	OR	A			; SET FLAGS
+	RET				; AND RETURN
+;
+;
+;
+CHSD_DEVICE:
+	LD	D,DIODEV_CHSD		; D := DEVICE TYPE
+	LD	E,(IY+CH_DEV)		; E := PHYSICAL DEVICE NUMBER
+	LD	C,%00110010		; SD HARD DISK ATTRIBUTES
+	LD	H,(IY+CH_TYPE)		; H := MODE
+	LD	L,(IY+CH_IOBASE)	; L := BASE I/O ADDRESS
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; CHSD_GETMED
+;
+CHSD_MEDIA:
+	LD	A,E			; GET FLAGS
+	OR	A			; SET FLAGS
+	JR	Z,CHSD_MEDIA1		; JUST REPORT CURRENT STATUS AND MEDIA
+	CALL	CHSD_RESET		; RESET CHSD INTERFACE
+;
+CHSD_MEDIA1:
+	LD	A,(IY+CHSD_STAT)	; GET STATUS
+	OR	A			; SET FLAGS
+	LD	D,0			; NO MEDIA CHANGE DETECTED
+	LD	E,MID_HD		; ASSUME WE ARE OK
+	RET	Z			; RETURN IF GOOD INIT
+	LD	E,MID_NONE		; SIGNAL NO MEDIA
+	LD	A,ERR_NOMEDIA		; NO MEDIA ERROR
+	OR	A			; SET FLAGS
+	RET				; AND RETURN
+;
+;
+;
+CHSD_SEEK:
+	BIT	7,D			; CHECK FOR LBA FLAG
+	CALL	Z,HB_CHS2LBA		; CLEAR MEANS CHS, CONVERT TO LBA
+	RES	7,D			; CLEAR FLAG REGARDLESS (DOES NO HARM IF ALREADY LBA)
+	LD	(IY+CHSD_LBA+0),L	; SAVE NEW LBA
+	LD	(IY+CHSD_LBA+1),H	; ...
+	LD	(IY+CHSD_LBA+2),E	; ...
+	LD	(IY+CHSD_LBA+3),D	; ...
+	XOR	A			; SIGNAL SUCCESS
+	RET				; AND RETURN
+;
+;
+;
+CHSD_CAP:
+	LD	A,(IY+CHSD_STAT)	; GET STATUS
+	PUSH	AF			; SAVE IT
+	LD	A,CHSD_MEDCAP		; OFFSET TO CAPACITY FIELD
+	CALL	LDHLIYA			; HL := IY + A, REG A TRASHED
+	CALL	LD32			; GET THE CURRENT CAPACITY INTO DE:HL
+	LD	BC,512			; 512 BYTES PER BLOCK
+	POP	AF			; RECOVER STATUS
+	OR	A			; SET FLAGS
+	RET
+;
+;
+;
+CHSD_GEOM:
+	; FOR LBA, WE SIMULATE CHS ACCESS USING 16 HEADS AND 16 SECTORS
+	; RETURN HS:CC -> DE:HL, SET HIGH BIT OF D TO INDICATE LBA CAPABLE
+	CALL	CHSD_CAP		; GET TOTAL BLOCKS IN DE:HL, BLOCK SIZE TO BC
+	LD	L,H			; DIVIDE BY 256 FOR # TRACKS
+	LD	H,E			; ... HIGH BYTE DISCARDED, RESULT IN HL
+	LD	D,16 | $80		; HEADS / CYL = 16, SET LBA CAPABILITY BIT
+	LD	E,16			; SECTORS / TRACK = 16
+	RET				; DONE, A STILL HAS CHSD_CAP STATUS
+;
+; CH37X HELPER ROUTINES
+;
+;
+; PERFORM DISK MOUNT
+;
+CHSD_DSKMNT:
+	;PRTS("\n\rMOUNT:$")		; *DEBUG*
+	LD	A,CH_CMD_DSKMNT		; DISK QUERY
+	CALL	CH_CMD			; DO IT
+	CALL	CH_POLL			; WAIT FOR RESPONSE
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CP	$82			; NO DISK?
+	JP	Z,CHSD_NOMEDIA		; HANDLE NO MEDIA ERROR
+	CP	$14			; SUCCESS?
+	JP	NZ,CHSD_CMDERR		; HANDLE ERROR
+;
+#IF FALSE
+	CALL	CH_CMD_RD		; SEND READ COMMAND
+	CALL	CH_RD			; GET LENGTH
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	LD	B,A			; LOOP COUNTER
+	LD	HL,HB_WRKBUF		; USE WORK BUFFER FOR DATA
+CHSD_DSKMNT1:
+	CALL	CH_RD			; GET A BYTE
+	LD	(HL),A			; SAVE IT
+	INC	HL			; BUMP BUF PTR
+	DJNZ	CHSD_DSKMNT1		; LOOP FOR ALL DATA
+;
+	;LD	DE,HB_WRKBUF		; *DEBUG*
+	;CALL	DUMP_BUFFER		; *DEBUG*
+;
+	CALL	CHSD_PRTPREFIX		; PRINT DEVICE PREFIX
+	LD	HL,HB_WRKBUF + 8
+	LD	B,28
+CHSD_DSKMNT2:
+	LD	A,(HL)
+	INC	HL
+	CALL	COUT
+	DJNZ	CHSD_DSKMNT2
+#ENDIF
+;
+	XOR	A
+	RET
+;
+; SET FILE NAME
+;
+CHSD_SETFNAME:
+	;PRTS("\n\rSETFNAME:$")		; *DEBUG*
+	LD	A,CH_CMD_SET_FN		; SET FILE NAME COMMAND
+	CALL	CH_CMD			; SEND IT
+	CALL	CH_NAP
+	;CALL	DELAY			; MAY NOT BE NEEDED
+	;CALL	PC_SPACE		; *DEBUG*
+CHSD_SETFNAME1:
+	;CALL	DELAY
+	LD	A,(DE)			; GET NEXT BYTE
+	INC	DE			; BUMP POINTER
+	CALL	CH_WR			; SEND IT
+	;CALL	COUT			; *DEBUG*
+	OR	A			; CHECK FOR NUL (EOS)
+	RET	Z			; IF NUL, DONE
+	JR	CHSD_SETFNAME1		; SEND MORE CHARACTERS
+;
+; OPEN FILE
+;
+CHSD_FOPEN:
+	CALL	CHSD_SETFNAME
+	;PRTS("\n\rFOPEN:$")		; *DEBUG*
+	LD	A,CH_CMD_FOPEN		; FILE OPEN  COMMAND
+	CALL	CH_CMD			; SEND IT
+	CALL	CH_POLL			; WAIT FOR RESULT
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CP	$42			; MISSING FILE?
+	JP	Z,CHSD_NOFILE		; HANDLE ERROR
+	CP	$14			; SUCCESS?
+	JP	NZ,CHSD_IOERR		; HANDLE ERROR
+	RET				; RETURN WITH ZF SET APPROPRIATELY
+;
+; GET FILE SIZE
+;
+CHSD_FILESIZE:
+	;PRTS("\n\rFSIZE:$")
+	LD	A,CH_CMD_FILESIZE	; FILE SIZE COMMAND
+	CALL	CH_CMD			; SEND IT
+	LD	A,$68			; REQUIRED CMD PARAMETER
+	CALL	CH_WR			; SEND IT
+	CALL	CH_NAP
+	LD	A,CHSD_MEDCAP		; MEDIA CAPACITY OFFSET
+	CALL	LDHLIYA			; HL := IY + A, REG A TRASHED
+	PUSH	HL			; SAVE ADDRESS
+	CALL	CH_RD
+	LD	L,A
+	CALL	CH_RD
+	LD	H,A
+	CALL	CH_RD
+	LD	E,A
+	CALL	CH_RD
+	LD	D,A
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEX32		; *DEBUG*
+	LD	B,9			; ROTATE 9 BITS FOR DIV 512
+CHSD_FILESIZE1:
+	SRL	D
+	RR	E
+	RR	H
+	RR	L
+	DJNZ	CHSD_FILESIZE1		; LOOP TILL DONE
+	POP	BC			; RECOVER ADDRESS TO BC
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEX32		; *DEBUG*
+	CALL	ST32			; STORE IT
+	XOR	A			; SIGNAL SUCCESS
+	RET				; AND DONE
+;
+; ERROR HANDLERS
+;
+;
+CHSD_NOFILE:
+	LD	A,CHSD_STNOFILE
+	JR	CHSD_ERR
+;
+CHSD_NOMEDIA:
+	LD	A,CHSD_STNOMEDIA
+	JR	CHSD_ERR
+;
+CHSD_CMDERR:
+	LD	A,CHSD_STCMDERR
+	JR	CHSD_ERR
+;
+CHSD_IOERR:
+	LD	A,CHSD_STIOERR
+	JR	CHSD_ERR
+;
+CHSD_TO:
+	LD	A,CHSD_STTO
+	JR	CHSD_ERR
+;
+CHSD_NOTSUP:
+	LD	A,CHSD_STNOTSUP
+	JR	CHSD_ERR
+;
+CHSD_ERR:
+	LD	(IY+CHSD_STAT),A	; SAVE NEW STATUS
+;
+CHSD_ERR2:
+#IF (CHSDTRACE >= 2)
+	CALL	CHSD_PRTSTAT
+#ENDIF
+	OR	A			; SET FLAGS
+	RET
+;
+;
+;
+CHSD_PRTERR:
+	RET	Z			; DONE IF NO ERRORS
+	; FALL THRU TO CHSD_PRTSTAT
+;
+; PRINT FULL DEVICE STATUS LINE
+;
+CHSD_PRTSTAT:
+	PUSH	AF
+	PUSH	DE
+	PUSH	HL
+	LD	A,(IY+CHSD_STAT)
+	CALL	CHSD_PRTPREFIX		; PRINT UNIT PREFIX
+	CALL	PC_SPACE		; FORMATTING
+	CALL	CHSD_PRTSTATSTR
+	POP	HL
+	POP	DE
+	POP	AF
+	RET
+;
+; PRINT STATUS STRING
+;
+CHSD_PRTSTATSTR:
+	PUSH	AF
+	PUSH	DE
+	PUSH	HL
+	LD	A,(IY+CHSD_STAT)
+	NEG
+	LD	HL,CHSD_STR_ST_MAP
+	ADD	A,A
+	CALL	ADDHLA
+	LD	E,(HL)
+	INC	HL
+	LD	D,(HL)
+	CALL	WRITESTR
+	POP	HL
+	POP	DE
+	POP	AF
+	RET
+;
+; PRINT DIAGNONSTIC PREFIX
+;
+CHSD_PRTPREFIX:
+	PUSH	AF
+	CALL	NEWLINE
+	PRTS("CHSD$")
+	LD	A,(IY+CH_DEV)		; GET CURRENT DEVICE NUM
+	CALL	PRTDECB
+	CALL	PC_COLON
+	POP	AF
 	RET
-
-
-CHSD_DEVNUM	.DB	0		; TEMP DEVICE NUM USED DURING INIT
-
-
-
-
-
 ;
-;=============================================================================
 ; DATA STORAGE
-;=============================================================================
 ;
-CH_FWVER		.DW	0,0	; MMNNBBB (M=MAJOR, N=MINOR, B=BUILD)
+CHSD_DEVNUM	.DB	0		; TEMP DEVICE NUM USED DURING INIT
+CHSD_DSKBUF	.DW	0
 ;
-CHSD_IOFNADR		.DW	0	; PENDING IO FUNCTION ADDRESS
+CHSD_FNAME	.DB	"/", CHSD_IMGFILE, 0
 ;
-CHSD_DSKBUF		.DW	0
+CHSD_STR_ST_MAP:
+	.DW		CHSD_STR_STOK
+	.DW		CHSD_STR_STNOMEDIA
+	.DW		CHSD_STR_STCMDERR
+	.DW		CHSD_STR_STIOERR
+	.DW		CHSD_STR_STTO
+	.DW		CHSD_STR_STNOTSUP
+	.DW		CHSD_STR_STNOFILE
 ;
-CHSD_DSKSTAT		.DB	0
-CHSD_ERRCODE		.DW	0,0
-CHSD_CSDBUF		.FILL	16,0
-;
-CHSD_CMD		.DB	0
-;
-CHSD_TIMEOUT		.DW	$0000	; FIX: MAKE THIS CPU SPEED RELATIVE
+CHSD_STR_STOK		.TEXT	"OK$"
+CHSD_STR_STNOMEDIA	.TEXT	"NO MEDIA$"
+CHSD_STR_STCMDERR	.TEXT	"COMMAND ERROR$"
+CHSD_STR_STIOERR	.TEXT	"IO ERROR$"
+CHSD_STR_STTO		.TEXT	"TIMEOUT$"
+CHSD_STR_STNOTSUP	.TEXT	"NOT SUPPORTED$"
+CHSD_STR_STNOFILE	.TEXT	"MISSING "
+			.TEXT	CHSD_IMGFILE
+			.TEXT	" FILE$"
+CHSD_STR_STUNK		.TEXT	"UNKNOWN ERROR$"

Source/HBIOS/ctc.asm

@@ -28,6 +28,8 @@ CTC_TIM256CFG	.EQU	%00110111	; CTC TIMER/256 MODE CONFIG
 #IF (CTCTIMER & (INTMODE != 2))
 	.ECHO	"*** WARNING: CTC TIMER DISABLED -- INTMODE 2 REQUIRED!!!\n"
 #ENDIF
+	.ECHO	"CTC: IO="
+	.ECHO	CTCBASE
 ;
 #IF (CTCTIMER & (INTMODE == 2))
 ;
@@ -109,13 +111,24 @@ CTC_DIV		.EQU	CTCOSC / CTC_PRESCL / TICKFREQ
 CTC_DIVHI	.EQU	CTCPRE
 CTC_DIVLO	.EQU	(CTC_DIV / CTC_DIVHI)
 ;
-	.ECHO "CTC DIVISOR: "
+
+	.ECHO	", TIMER MODE="
+  #IF (CTCMODE == CTCMODE_CTR)
+		.ECHO	"COUNTER"
+  #ENDIF
+  #IF (CTCMODE == CTCMODE_TIM16)
+		.ECHO	"TIMER/16"
+  #ENDIF
+  #IF (CTCMODE == CTCMODE_TIM256)
+		.ECHO	"TIMER/256"
+  #ENDIF
+	.ECHO ", DIVISOR="
 	.ECHO CTC_DIV
-	.ECHO ", HI: "
+	.ECHO ", HI="
 	.ECHO CTC_DIVHI
-	.ECHO ", LO: "
+	.ECHO ", LO="
 	.ECHO CTC_DIVLO
-	.ECHO "\n"
+	.ECHO ", INTERRUPTS ENABLED"
 ;
   #IF ((CTC_DIV == 0) | (CTC_DIV > $FFFF))
 	.ECHO "COMPUTED CTC DIVISOR IS UNUSABLE!\n"
@@ -134,6 +147,8 @@ CTC_DIVLO	.EQU	(CTC_DIV / CTC_DIVHI)
 CTCTIVT		.EQU	INT_CTC0A + CTCTIMCH
 ;
 #ENDIF
+;
+	.ECHO "\n"
 ;
 ;==================================================================================================
 ; CTC PRE-INITIALIZATION

Source/HBIOS/cvdu.asm

@@ -17,6 +17,8 @@
 ;======================================================================
 ;
 CVDU_BASE	.EQU	$E0
+;
+		.ECHO	"CVDU: MODE="
 ;
 #IF (CVDUMODE == CVDUMODE_ECB)
 CVDU_KBDDATA	.EQU	CVDU_BASE + $02	; KBD CTLR DATA PORT
@@ -24,6 +26,7 @@ CVDU_KBDST	.EQU	CVDU_BASE + $0A	; KBD CTLR STATUS/CMD PORT
 CVDU_STAT	.EQU	CVDU_BASE + $04	; READ M8563 STATUS
 CVDU_REG	.EQU	CVDU_BASE + $04	; SELECT M8563 REGISTER
 CVDU_DATA	.EQU	CVDU_BASE + $0C	; READ/WRITE M8563 DATA
+		.ECHO	"ECB"
 #ENDIF
 ;
 #IF (CVDUMODE == CVDUMODE_MBC)
@@ -32,7 +35,15 @@ CVDU_KBDST	.EQU	CVDU_BASE + $03	; KBD CTLR STATUS/CMD PORT
 CVDU_STAT	.EQU	CVDU_BASE + $04	; READ M8563 STATUS
 CVDU_REG	.EQU	CVDU_BASE + $04	; SELECT M8563 REGISTER
 CVDU_DATA	.EQU	CVDU_BASE + $05	; READ/WRITE M8563 DATA
+		.ECHO	"MBC"
 #ENDIF
+;
+		.ECHO	", IO="
+		.ECHO	CVDU_BASE
+		.ECHO	", KBD MODE=PS/2"
+		.ECHO	", KBD IO="
+		.ECHO	CVDU_KBDDATA
+		.ECHO	"\n"
 ;
 CVDU_ROWS	.EQU	25
 CVDU_COLS	.EQU	80

Source/HBIOS/dma.asm

@@ -2,17 +2,31 @@
 ; Z80 DMA DRIVER
 ;==================================================================================================
 ;
+;
+	.ECHO	"DMA: MODE="
+;
 #IF ((DMAMODE == DMAMODE_ECB) | (DMAMODE == DMAMODE_MBC))
 DMA_IO		.EQU	DMABASE
 DMA_CTL		.EQU	DMABASE + 1
 DMA_USEHALF	.EQU	TRUE
+  #IF (DMAMODE == DMAMODE_ECB)
+	.ECHO	"ECB"
+  #ENDIF
+  #IF (DMAMODE == DMAMODE_MBC)
+	.ECHO	"MBC"
+  #ENDIF
 #ENDIF
 ;
 #IF (DMAMODE == DMAMODE_DUO)
 DMA_IO		.EQU	DMABASE
 DMA_CTL		.EQU	DMABASE + 3
 DMA_USEHALF	.EQU	FALSE
+	.ECHO	"DUO"
 #ENDIF
+;S
+	.ECHO	", IO="
+	.ECHO	DMA_IO
+	.ECHO	"\n"
 ;
 DMA_CONTINUOUS			.equ 	%10111101	; + Pulse
 DMA_BYTE			.equ 	%10011101	; + Pulse

Source/HBIOS/ds1501rtc.asm

@@ -53,42 +53,42 @@
 ;  +---+--+--+-----+----+----+----+----+----+----+------------------+----------------+
 ;  |14-1F |              Reserved                |                  |                |
 ;  +------+--+-----+----+----+----+----+----+----+------------------+----------------+
-
+;
 ;  * = Unused bits; unwritable and read as 0.
 ;  0 = should be set to 0 for valid time/calendar range.
 ;  Clock calendar data is BCD. Automatic leap year adjustment.
 ;  Day-Of-Week coded as Sunday = 1 through Saturday = 7.
-
+;
 ; Constants
-
-;By defining 2 bases, this allows some flexibility for address decoding
-DS1501NVM_BASE      .EQU    DS1501RTC_BASE + $10
+;
+; By defining 2 bases, this allows some flexibility for address decoding
+DS1501NVM_BASE		.EQU	DS1501RTC_BASE + $10
 
-DS1501RTC_SEC	    .EQU	DS1501RTC_BASE + $00
-DS1501RTC_MIN	    .EQU	DS1501RTC_BASE + $01
-DS1501RTC_HOUR	    .EQU	DS1501RTC_BASE + $02
+DS1501RTC_SEC		.EQU	DS1501RTC_BASE + $00
+DS1501RTC_MIN		.EQU	DS1501RTC_BASE + $01
+DS1501RTC_HOUR		.EQU	DS1501RTC_BASE + $02
 DS1501RTC_WEEK_DAY	.EQU	DS1501RTC_BASE + $03
-DS1501RTC_DAY	    .EQU	DS1501RTC_BASE + $04
-DS1501RTC_MONTH	    .EQU	DS1501RTC_BASE + $05
-DS1501RTC_YEAR	    .EQU	DS1501RTC_BASE + $06
-DS1501RTC_CENT      .EQU	DS1501RTC_BASE + $07
+DS1501RTC_DAY		.EQU	DS1501RTC_BASE + $04
+DS1501RTC_MONTH		.EQU	DS1501RTC_BASE + $05
+DS1501RTC_YEAR		.EQU	DS1501RTC_BASE + $06
+DS1501RTC_CENT		.EQU	DS1501RTC_BASE + $07
 DS1501RTC_SEC_ALM	.EQU	DS1501RTC_BASE + $08
 DS1501RTC_MIN_ALM	.EQU	DS1501RTC_BASE + $09
 DS1501RTC_HOUR_ALM	.EQU	DS1501RTC_BASE + $0A
 DS1501RTC_DAY_ALM	.EQU	DS1501RTC_BASE + $0B
-DS1501RTC_WDOG1     .EQU	DS1501RTC_BASE + $0C
-DS1501RTC_WDOG2 	.EQU	DS1501RTC_BASE + $0D
+DS1501RTC_WDOG1		.EQU	DS1501RTC_BASE + $0C
+DS1501RTC_WDOG2		.EQU	DS1501RTC_BASE + $0D
 DS1501RTC_CONTROLA	.EQU	DS1501RTC_BASE + $0E
 DS1501RTC_CONTROLB	.EQU	DS1501RTC_BASE + $0F
-
+;
 DS1501RTC_RAMADDR	.EQU	DS1501NVM_BASE + $00
 DS1501RTC_RAMDATA	.EQU	DS1501NVM_BASE + $03
-
-DS1501RTC_HIGH	.EQU	%11110000
-DS1501RTC_LOW	.EQU	%00001111
-
-;ControlA bit masks
-;BLF1| BLF2| PRS| PAB| TDF| KSF| WDF|IRQF
+;
+DS1501RTC_HIGH		.EQU	%11110000
+DS1501RTC_LOW		.EQU	%00001111
+;
+; ControlA bit masks
+; BLF1| BLF2| PRS| PAB| TDF| KSF| WDF|IRQF
 DS1501RTC_IRQF	.EQU	%00000001
 DS1501RTC_WDF	.EQU	%00000010
 DS1501RTC_KSF	.EQU	%00000100
@@ -97,9 +97,9 @@ DS1501RTC_PAB	.EQU	%00010000
 DS1501RTC_PRS 	.EQU	%00100000
 DS1501RTC_BLF2  .EQU	%01000000
 DS1501RTC_BLF1	.EQU	%10000000
-
-;ControlB bit masks
-;TE| CS| BME| TPE| TIE| KIE| WDE| WDS|
+;
+; ControlB bit masks
+; TE| CS| BME| TPE| TIE| KIE| WDE| WDS|
 DS1501RTC_WDS 	.EQU	%00000001
 DS1501RTC_WDE	.EQU	%00000010
 DS1501RTC_KIE	.EQU	%00000100
@@ -108,29 +108,36 @@ DS1501RTC_TPE	.EQU	%00010000
 DS1501RTC_BME 	.EQU	%00100000
 DS1501RTC_CS    .EQU	%01000000
 DS1501RTC_TE	.EQU	%10000000
-
+;
 DS1501RTC_BUFSIZE	.EQU	6		; 6 BYTE BUFFER (YYMMDDHHMMSS)
 
+	.ECHO	"DS1501RTC: RTCIO="
+	.ECHO	DS1501RTC_BASE
+	.ECHO	", NVMIO="
+	.ECHO	DS1501NVM_BASE
+	.ECHO	"\n"
+;
 ; RTC Device Initialization Entry
-
+;
 DS1501RTC_INIT:
 	CALL	NEWLINE				; Formatting
 	PRTS("DS1501RTC: IO=0x$")
 	LD	A, DS1501RTC_BASE
 	CALL	PRTHEXBYTE
-
+;
 	CALL	NEWLINE				; Formatting
 	PRTS("DS1501NVM: IO=0x$")
 	LD	A, DS1501NVM_BASE
 	CALL	PRTHEXBYTE
-
-    IN	A,(DS1501RTC_CONTROLB)      ;clear any pending interrupt flags
-
+;
+	IN	A,(DS1501RTC_CONTROLB)		; Clear any pending interrupt flags
+;
 	XOR	A				; Zero A
-    OR      DS1501RTC_TE            ;enable time updates
-    OUT	(DS1501RTC_CONTROLB), A
-
+	OR	DS1501RTC_TE			; Enable time updates
+	OUT	(DS1501RTC_CONTROLB), A
+;
 	CALL	DS1501RTC_LOAD
+;
 	; DISPLAY CURRENT TIME
 	PRTS("  $")
 	LD	A, (DS1501RTC_BUF_MON)
@@ -150,44 +157,36 @@ DS1501RTC_INIT:
 	PRTS(":$")
 	LD	A, (DS1501RTC_BUF_SEC)
 	CALL	PRTHEXBYTE
-
+;
 	LD	BC,DS1501RTC_DISPATCH
 	CALL	RTC_SETDISP
-
+;
 	XOR	A				; Signal success
 	RET
-
+;
 ; RTC Device Function Dispatch Entry
 ;   A: Result (OUT), 0=OK, Z=OK, NZ=Error
 ;   B: Function (IN)
-
+;
 DS1501RTC_DISPATCH:
 	LD	A, B				; Get requested function
 	AND	$0F				; Isolate Sub-Function
-	JP	Z, DS1501RTC_GETTIM			; Get Time
+	JP	Z, DS1501RTC_GETTIM		; Get Time
 	DEC	A
-	JP	Z, DS1501RTC_SETTIM			; Set Time
+	JP	Z, DS1501RTC_SETTIM		; Set Time
 	DEC	A
-	JP	Z, DS1501RTC_GETBYT			; Get NVRAM Byte Value
+	JP	Z, DS1501RTC_GETBYT		; Get NVRAM Byte Value
 	DEC	A
-	JP	Z, DS1501RTC_SETBYT			; Set NVRAM Byte Value
+	JP	Z, DS1501RTC_SETBYT		; Set NVRAM Byte Value
 	DEC	A
-	JP	Z, DS1501RTC_GETBLK			; Get NVRAM Data Block Value
+	JP	Z, DS1501RTC_GETBLK		; Get NVRAM Data Block Value
 	DEC	A
-	JP	Z, DS1501RTC_SETBLK			; Set NVRAM Data Block Value
+	JP	Z, DS1501RTC_SETBLK		; Set NVRAM Data Block Value
 	DEC	A
-	JP	Z, DS1501RTC_GETALM			; Get Alarm
+	JP	Z, DS1501RTC_GETALM		; Get Alarm
 	DEC	A
-	JP	Z, DS1501RTC_SETALM			; Set Alarm
+	JP	Z, DS1501RTC_SETALM		; Set Alarm
 ;
-; NVRAM FUNCTIONS ARE NOT IMPLEMENTED YET
-;
-DS1501RTC_GETBYT:
-DS1501RTC_SETBYT:
-DS1501RTC_GETBLK:
-DS1501RTC_SETBLK:
-	CALL	PANIC
-
 ; RTC Get Time
 ;   A: Result (OUT), 0=OK, Z=OK, NZ=Error
 ;   HL: Date/Time Buffer (OUT)
@@ -228,7 +227,7 @@ DS1501RTC_SETTIM:
 	LD	(HB_SRCBNK), A			; Set it
 	LD	A, BID_BIOS			; Copy to BIOS bank
 	LD	(HB_DSTBNK), A			; Set it
-	LD	DE, DS1501RTC_BUF			; Destination Address
+	LD	DE, DS1501RTC_BUF		; Destination Address
 	LD	BC, DS1501RTC_BUFSIZE		; Length is 6 bytes
 #IF (INTMODE == 1)
 	DI
@@ -241,27 +240,123 @@ DS1501RTC_SETTIM:
 	LD	HL, DS1501RTC_BUF
 	CALL	DS1501RTC_SUSPEND
 	LD	A, (HL)
-	OUT	(DS1501RTC_YEAR), A			; Write Year
+	OUT	(DS1501RTC_YEAR), A		; Write Year
 	INC	HL
 	LD	A, (HL)
 	OUT	(DS1501RTC_MONTH), A		; Write Month
 	INC	HL
 	LD	A, (HL)
-	OUT	(DS1501RTC_DAY), A			; Write Day
+	OUT	(DS1501RTC_DAY), A		; Write Day
 	INC	HL
 	LD	A, (HL)
-	OUT	(DS1501RTC_HOUR), A			; Write Hour
+	OUT	(DS1501RTC_HOUR), A		; Write Hour
 	INC	HL
 	LD	A, (HL)
-	OUT	(DS1501RTC_MIN), A			; Write Minute
+	OUT	(DS1501RTC_MIN), A		; Write Minute
 	INC	HL
 	LD	A, (HL)
-	OUT	(DS1501RTC_SEC), A			; Write Second
+	OUT	(DS1501RTC_SEC), A		; Write Second
 	CALL	DS1501RTC_RESUME
-	; clean up and return
+;
+	; Clean up and return
 	XOR	A				; Signal success
 	RET					; And return
-
+;
+; RTC Get Byte
+;
+DS1501RTC_GETBYT:
+;
+; C Index
+; E Value
+; Set address
+;
+	LD	B, C
+	LD	C, DS1501RTC_RAMADDR
+	OUT	(C), B
+;
+	; Get data
+	IN	A, (DS1501RTC_RAMDATA)
+	LD	E,A
+;
+	; Return success
+	XOR	
+;
+	RET
+;
+; RTC Set Byte
+;
+DS1501RTC_SETBYT:
+;
+; C Index
+; E Value
+; Set address
+;
+	LD	B, C
+	LD	C, DS1501RTC_RAMADDR
+	OUT	(C), B
+;	
+	; Set data
+	LD	A,E
+	OUT	(DS1501RTC_RAMDATA), A
+;	
+	; Return success
+	XOR	A
+	RET
+;
+; RTC Get Block
+;
+DS1501RTC_GETBLK:
+;
+; HL Buffer Address
+;
+	LD	B, 0				; 256 Bytes
+;	
+	; Set BME
+	IN	A, (DS1501RTC_CONTROLB)
+	OR	DS1501RTC_BME
+	OUT	(DS1501RTC_CONTROLB), A
+;	
+	XOR	A
+	OUT	(DS1501RTC_RAMADDR), A
+	LD	C, DS1501RTC_RAMDATA
+	INIR
+;	
+	; Clear BME
+	IN	A, (DS1501RTC_CONTROLB)
+	AND	~DS1501RTC_BME
+	OUT	(DS1501RTC_CONTROLB), A
+;	
+	; Return success
+	XOR	A
+	RET
+;
+; RTC Set Block
+;
+DS1501RTC_SETBLK:
+;
+; HL Buffer Address
+;
+	LD B, 0					; 256 Bytes
+;
+	; Set BME
+	IN	A, (DS1501RTC_CONTROLB)
+	OR	DS1501RTC_BME
+	OUT	(DS1501RTC_CONTROLB), A
+;
+	XOR	A
+	OUT	(DS1501RTC_RAMADDR), A
+	LD	C, DS1501RTC_RAMDATA
+	OTIR
+;
+	; Clear BME
+	IN	A, (DS1501RTC_CONTROLB)
+	AND	~DS1501RTC_BME
+	OUT	(DS1501RTC_CONTROLB), A
+;
+	; Return success
+	XOR	A
+	RET
+;
 ; RTC Get Alarm
 ;   A: Result (OUT), 0=OK, Z=OK, NZ=Error
 ;   HL: Date/Time Buffer (OUT)
@@ -291,6 +386,7 @@ DS1501RTC_GETALM:
 	LD	(HL), A
 	CALL	DS1501RTC_RESUME
 	POP	HL				; Restore address of source buffer
+;
 	; Now copy to read destination (Interbank Save)
 	LD	A, BID_BIOS			; Copy from BIOS bank
 	LD	(HB_SRCBNK), A			; Set it
@@ -321,7 +417,7 @@ DS1501RTC_SETALM:
 	LD	(HB_SRCBNK), A			; Set it
 	LD	A, BID_BIOS			; Copy to BIOS bank
 	LD	(HB_DSTBNK), A			; Set it
-	LD	DE, DS1501RTC_BUF			; Destination Address
+	LD	DE, DS1501RTC_BUF		; Destination Address
 	LD	BC, DS1501RTC_BUFSIZE		; Length is 6 bytes
 #IF (INTMODE == 1)
 	DI
@@ -345,49 +441,50 @@ DS1501RTC_SETALM:
 	LD	A, (HL)
 	OUT	(DS1501RTC_SEC_ALM), A		; Write Second
 	CALL	DS1501RTC_RESUME
-	; clean up and return
+;
+	; Clean up and return
 	XOR	A				; Signal success
 	RET					; And return
-
+;
 DS1501RTC_SUSPEND:
 	IN	A, (DS1501RTC_CONTROLB)		; Suspend Clock
 	AND	~DS1501RTC_TE
 	OUT	(DS1501RTC_CONTROLB), A
 	RET
-
+;
 DS1501RTC_RESUME:
 	IN	A, (DS1501RTC_CONTROLB)		; Resume Clock
 	OR	DS1501RTC_TE
 	OUT	(DS1501RTC_CONTROLB), A
 	RET
-
+;
 DS1501RTC_LOAD:
 	LD	HL, DS1501RTC_BUF
 	PUSH	HL				; Save address of source buffer
 	CALL	DS1501RTC_SUSPEND
-	IN	A, (DS1501RTC_YEAR)			; Read Year
+	IN	A, (DS1501RTC_YEAR)		; Read Year
 	LD	(HL), A
 	INC	HL
 	IN	A, (DS1501RTC_MONTH)		; Read Month
 	LD	(HL), A
 	INC	HL
-	IN	A, (DS1501RTC_DAY)			; Read Day
+	IN	A, (DS1501RTC_DAY)		; Read Day
 	LD	(HL), A
 	INC	HL
-	IN	A, (DS1501RTC_HOUR)			; Read Hour
+	IN	A, (DS1501RTC_HOUR)		; Read Hour
 	LD	(HL), A
 	INC	HL
-	IN	A, (DS1501RTC_MIN)			; Read Minute
+	IN	A, (DS1501RTC_MIN)		; Read Minute
 	LD	(HL), A
 	INC	HL
-	IN	A, (DS1501RTC_SEC)			; Read Second
+	IN	A, (DS1501RTC_SEC)		; Read Second
 	LD	(HL), A
 	CALL	DS1501RTC_RESUME
 	POP	HL				; Restore address of source buffer
 	RET
-
+;
 ; Working Variables
-
+;
 DS1501RTC_BUF:
 DS1501RTC_BUF_YEAR:	.DB	0		; Year
 DS1501RTC_BUF_MON:	.DB	0		; Month

Source/HBIOS/ds7rtc.asm

@@ -22,6 +22,8 @@ DS7_READ   	.EQU    (DS7_DS1307 | DS7_R)	; READ
 DS7_WRITE 	.EQU    (DS7_DS1307 | DS7_W)	; WRITE
 ;
 DS7_CTL		.EQU	(DS7_OUT | DS7_SQWE | DS7_RATE)
+;
+		.ECHO	"DS1307: ENABLED\n"
 ;
 ;-----------------------------------------------------------------------------
 ; DS1307 INITIALIZATION

Source/HBIOS/dsrtc.asm

@@ -88,6 +88,8 @@
 ; D2	--	--	--	--	--	--	--	--	--		--	--
 ; D1	----	--	--	--	--	--	--	--	--		CLKSEL	--
 ; D0	RTC_IN	RTC_IN	RTC_IN	RTC_IN	RTC_IN	RTC_IN	--	--	RTC_IN		RTC_IN	RTC_IN
+;
+	.ECHO	"DSRTC: MODE="
 ;
 #IF (DSRTCMODE == DSRTCMODE_STD)
 ;
@@ -113,6 +115,8 @@ DS1d8k		.EQU	%10100111	; 1 DOIDE 8K RESISTOR
 DS2d2k		.EQU	%10101001	; 2 DIODES 2K RESISTOR
 DS2d4k		.EQU	%10101010	; 2 DIODES 4K RESISTOR
 DS2d8k		.EQU	%10101011	; 2 DIODES 8K RESISTOR
+;
+		.ECHO	"STD"
 ;
 #ENDIF
 ;
@@ -129,8 +133,14 @@ DSRTC_MASK	.EQU	%00001111	; MASK FOR BITS WE OWN IN RTC LATCH PORT
 DSRTC_IDLE	.EQU	%00001000	; QUIESCENT STATE
 ;
 #DEFINE	DSRTC_OPRVAL	DSRTC_RTCVAL
+;
+		.ECHO	"MFPIC"
 ;
 #ENDIF
+;
+		.ECHO	", IO="
+		.ECHO	DSRTC_IO
+		.ECHO	"\n"
 ;
 DSRTC_BUFSIZ	.EQU	7		; 7 BYTE BUFFER (YYMMDDHHMMSSWW)
 ;

Source/HBIOS/duart.asm

@@ -822,6 +822,10 @@ DUART0A_CFG:
 	.DW	DUART0_ACR		; IY+6	POINTER TO SHADOW ACR FOR THIS CHIP
 	.DW	DUART0ACFG		; IY+8	LINE CONFIGURATION
 	.DB	1			; IY+10	MULTIPLIER WRT 3.6864MHZ CLOCK
+;
+	.ECHO	"DUART: IO="
+	.ECHO	DUART0BASE + $00
+	.ECHO	", CHANNEL A\n"
 ;
 DUART_CFGSIZ	.EQU	$ - DUART_CFG	; SIZE OF ONE CFG TABLE ENTRY
 ;
@@ -835,6 +839,10 @@ DUART0B_CFG:
 	.DW	DUART0_ACR		; POINTER TO SHADOW ACR FOR THIS CHIP
 	.DW	DUART0BCFG		; LINE CONFIGURATION
 	.DB	1			; MULTIPLIER WRT 3.6864MHZ CLOCK
+;
+	.ECHO	"DUART: IO="
+	.ECHO	DUART0BASE + $08
+	.ECHO	", CHANNEL B\n"
 ;
 #IF (DUARTCNT >= 2)
 ;
@@ -848,6 +856,10 @@ DUART1A_CFG:
 	.DW	DUART1_ACR		; POINTER TO SHADOW ACR FOR THIS CHIP
 	.DW	DUART1ACFG		; LINE CONFIGURATION
 	.DB	1			; MULTIPLIER WRT 3.6864MHZ CLOCK
+;
+	.ECHO	"DUART: IO="
+	.ECHO	DUART1BASE + $00
+	.ECHO	", CHANNEL A\n"
 ;
 DUART1B_CFG:
 	; 2ND DUART MODULE CHANNEL B
@@ -859,6 +871,10 @@ DUART1B_CFG:
 	.DW	DUART1_ACR		; POINTER TO SHADOW ACR FOR THIS CHIP
 	.DW	DUART1BCFG		; LINE CONFIGURATION
 	.DB	1			; MULTIPLIER WRT 3.6864MHZ CLOCK
+;
+	.ECHO	"DUART: IO="
+	.ECHO	DUART1BASE + $08
+	.ECHO	", CHANNEL B\n"
 ;
 #ENDIF
 ;

Source/HBIOS/esp.asm

@@ -53,6 +53,10 @@ ESP_CFG_IO	.EQU	1		; ESP I/O PORT
 ESP_CFG_ST	.EQU	2		; ESP STATUS PORT
 ESP_CFG_RDYMSK	.EQU	3		; ESP READY MASK
 ESP_CFG_BSYMSK	.EQU	4		; ESP BUSY MASK
+;
+	.ECHO	"ESP: IO="
+	.ECHO	ESP_IOBASE
+	.ECHO	"\n"
 ;
 ; GLOBAL ESP INITIALIZATION
 ;
@@ -343,6 +347,8 @@ ESP_STR_UPGRADE		.TEXT	"!!!UPGRADE REQUIRED!!!$"
 ;
 ESPCON_ROWS	.EQU	25		; VGA DISPLAY ROWS
 ESPCON_COLS	.EQU	80		; VGA DISPLAY COLS
+;
+	.ECHO	"ESPCON: ENABLED\n"
 ;
 ;
 ;
@@ -685,7 +691,8 @@ ESPSER0_CFG:
 	.DB	ESP_0_RDY			; ESP READY BIT MASK
 	.DB	ESP_0_BUSY			; ESP BUSY BIT MASK
 	.DW	ESPSER_LINECFG			; LINE CONFIGURATION
-
+;
+	.ECHO	"ESPSER: DEVICE=0\n"
 ;
 ESPSER1_CFG:
 	.DB	0				; DEVICE NUMBER (UPDATED DURING INIT)
@@ -694,6 +701,8 @@ ESPSER1_CFG:
 	.DB	ESP_1_RDY			; ESP READY BIT MASK
 	.DB	ESP_1_BUSY			; ESP BUSY BIT MASK
 	.DW	ESPSER_LINECFG			; LINE CONFIGURATION
+;
+	.ECHO	"ESPSER: DEVICE=1\n"
 ;
 ;
 ;

Source/HBIOS/fd.asm

@@ -14,6 +14,7 @@ FDC_DATA	.EQU	$37		; 8272 DATA PORT
 FDC_DIR		.EQU	$38		; DATA INPUT REGISTER
 FDC_DOR		.EQU	$3A		; DIGITAL OUTPUT REGISTER (LATCH)
 FDC_DMA		.EQU	$3C		; PSEUDO DMA DATA PORT
+  #DEFINE FDMODE_STR "DIO"
 #ENDIF
 #IF (FDMODE = FDMODE_ZETA2)
 FDC_MSR		.EQU	$30		; 8272 MAIN STATUS REGISTER
@@ -21,6 +22,7 @@ FDC_DATA	.EQU	$31		; 8272 DATA PORT
 FDC_DOR		.EQU	$38		; DIGITAL OUTPUT REGISTER
 FDC_DCR		.EQU	$28		; CONFIGURATION CONTROL REGISTER
 FDC_TC		.EQU	$38		; TERMINAL COUNT (W/ DACK)
+  #DEFINE FDMODE_STR "ZETA2"
 #ENDIF
 #IF (FDMODE == FDMODE_DIDE)
 FDC_BID		.EQU	$20		; IO RANGE 20H-3FH
@@ -31,6 +33,7 @@ FDC_DCR		.EQU	$2D		; DCR
 FDC_DACK	.EQU	$3C		; DACK
 FDC_TC		.EQU	$3D		; TERMINAL COUNT (W/ DACK)
 FDC_DMA		.EQU	$3C		; NOT USED BY DIDE
+  #DEFINE FDMODE_STR "DIDE"
 #ENDIF
 #IF (FDMODE == FDMODE_N8)
 FDC_MSR		.EQU	$8C		; 8272 MAIN STATUS REGISTER
@@ -40,11 +43,13 @@ FDC_DCR		.EQU	$91		; DCR
 FDC_DACK	.EQU	$90		; DACK
 FDC_TC		.EQU	$93		; TERMINAL COUNT (W/ DACK)
 FDC_DMA		.EQU	$3C		; NOT USED BY N8
+  #DEFINE FDMODE_STR "N8"
 #ENDIF
 #IF (FDMODE == FDMODE_RCSMC)
 FDC_MSR		.EQU	$50		; 8272 MAIN STATUS REGISTER
 FDC_DATA	.EQU	$51		; 8272 DATA PORT
 FDC_DOR		.EQU	$58		; DIGITAL OUTPUT REGISTER (LATCH)
+  #DEFINE FDMODE_STR "RCSMC"
 #ENDIF
 #IF (FDMODE == FDMODE_RCWDC)
 FDC_MSR		.EQU	$50		; 8272 MAIN STATUS REGISTER
@@ -52,6 +57,7 @@ FDC_DATA	.EQU	$51		; 8272 DATA PORT
 FDC_DOR		.EQU	$58		; DIGITAL OUTPUT REGISTER
 FDC_DCR		.EQU	$48		; CONFIGURATION CONTROL REGISTER
 FDC_TC		.EQU	$58		; TERMINAL COUNT (W/ DACK)
+  #DEFINE FDMODE_STR "RCWDC"
 #ENDIF
 #IF (FDMODE == FDMODE_DYNO)
 FDC_BASE        .EQU    $84
@@ -60,6 +66,7 @@ FDC_DATA	.EQU	FDC_BASE + $01	; 8272 DATA PORT
 FDC_DOR		.EQU	FDC_BASE + $02	; DIGITAL OUTPUT REGISTER
 FDC_DCR		.EQU	FDC_BASE + $03	; CONFIGURATION CONTROL REGISTER
 FDC_TC		.EQU	FDC_BASE + $02	; TERMINAL COUNT (W/ DACK)
+  #DEFINE FDMODE_STR "DYNO"
 #ENDIF
 #IF (FDMODE == FDMODE_EPFDC)
 FDC_MSR		.EQU	$48		; 8272 MAIN STATUS REGISTER
@@ -67,6 +74,7 @@ FDC_DATA	.EQU	$49		; 8272 DATA PORT
 FDC_DOR		.EQU	$4A		; DIGITAL OUTPUT REGISTER
 FDC_DCR		.EQU	$4B		; CONFIGURATION CONTROL REGISTER
 FDC_TC		.EQU	$4C		; TERMINAL COUNT (W/ DACK)
+  #DEFINE FDMODE_STR "EPFDC"
 #ENDIF
 #IF (FDMODE == FDMODE_MBC)
 FDC_MSR		.EQU	$30		; 8272 MAIN STATUS REGISTER
@@ -74,7 +82,17 @@ FDC_DATA	.EQU	$31		; 8272 DATA PORT
 FDC_DOR		.EQU	$36		; DIGITAL OUTPUT REGISTER
 FDC_DCR		.EQU	$35		; CONFIGURATION CONTROL REGISTER
 FDC_TC		.EQU	$37		; TERMINAL COUNT (W/ DACK)
+  #DEFINE FDMODE_STR "MBC"
 #ENDIF
+#IF (FDMODE == FDMODE_DUO)
+FDC_MSR		.EQU	$80		; 8272 MAIN STATUS REGISTER
+FDC_DATA	.EQU	$81		; 8272 DATA PORT
+FDC_DOR		.EQU	$86		; DIGITAL OUTPUT REGISTER
+FDC_DCR		.EQU	$85		; CONFIGURATION CONTROL REGISTER
+FDC_TC		.EQU	$87		; TERMINAL COUNT (W/ DACK)
+  #DEFINE FDMODE_STR "DUO"
+#ENDIF
+;
 ;
 ; DISK OPERATIONS
 ;
@@ -133,6 +151,33 @@ FD_CFGTBL:
 	.DB	0			; HOST SECTOR
 	.DB	0			; HOST HEAD
 	.DB	FD0TYPE			; DRIVE TYPE
+;
+	.ECHO	"FD: MODE="
+	.ECHO	FDMODE_STR
+	.ECHO	", IO="
+	.ECHO	FDC_MSR
+	.ECHO	", DRIVE 0"
+	.ECHO	", TYPE="
+  #IF (FD0TYPE == FDT_NONE
+	.ECHO	"NONE"
+  #ENDIF
+  #IF (FD0TYPE == FDT_3DD
+	.ECHO	"3.5\" DD"
+  #ENDIF
+  #IF (FD0TYPE == FDT_3HD
+	.ECHO	"3.5\" HD"
+  #ENDIF
+  #IF (FD0TYPE == FDT_5DD
+	.ECHO	"5.25\" DD"
+  #ENDIF
+  #IF (FD0TYPE == FDT_5HD
+	.ECHO	"5.25\" HD"
+  #ENDIF
+  #IF (FD0TYPE == FDT_8
+	.ECHO	"8\" DD"
+  #ENDIF
+	.ECHO	"\n"
+;
 #IF (FD_DEVCNT >= 2)
 	; DEVICE 1, PRIMARY SLAVE
 	.DB	1			; DRIVER DEVICE NUMBER
@@ -143,6 +188,32 @@ FD_CFGTBL:
 	.DB	0			; HOST SECTOR
 	.DB	0			; HOST HEAD
 	.DB	FD1TYPE			; DRIVE TYPE
+;
+	.ECHO	"FD: MODE="
+	.ECHO	FDMODE_STR
+	.ECHO	", IO="
+	.ECHO	FDC_MSR
+	.ECHO	", DRIVE 1"
+	.ECHO	", TYPE="
+  #IF (FD1TYPE == FDT_NONE
+	.ECHO	"NONE"
+  #ENDIF
+  #IF (FD1TYPE == FDT_3DD
+	.ECHO	"3.5\" DD"
+  #ENDIF
+  #IF (FD1TYPE == FDT_3HD
+	.ECHO	"3.5\" HD"
+  #ENDIF
+  #IF (FD1TYPE == FDT_5DD
+	.ECHO	"5.25\" DD"
+  #ENDIF
+  #IF (FD1TYPE == FDT_5HD
+	.ECHO	"5.25\" HD"
+  #ENDIF
+  #IF (FD1TYPE == FDT_8
+	.ECHO	"8\" DD"
+  #ENDIF
+	.ECHO	"\n"
 #ENDIF
 ;
 #IF ($ - FD_CFGTBL) != (FD_DEVCNT * FD_CFGSIZ)
@@ -452,7 +523,7 @@ DOR_INIT	.EQU	11100000B	; INITIAL DEFAULT LATCH VALUE
 ;
 ; *** DIDE/N8/ZETA V2 ***
 ;
-#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC) | (FDMODE == FDMODE_DYNO) | (FDMODE == FDMODE_EPFDC) | (FDMODE == FDMODE_MBC))
+#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC) | (FDMODE == FDMODE_DYNO) | (FDMODE == FDMODE_EPFDC) | (FDMODE == FDMODE_MBC) | (FDMODE == FDMODE_DUO))
 DOR_INIT	.EQU	00001100B	; SOFT RESET INACTIVE, DMA ENABLED
 DOR_BR250	.EQU	DOR_INIT
 DOR_BR500	.EQU	DOR_INIT
@@ -749,6 +820,10 @@ FD_INIT:
 #IF (FDMODE == FDMODE_MBC)
 	PRTS("MBC$")
 #ENDIF
+;
+#IF (FDMODE == FDMODE_DUO)
+	PRTS("DUO$")
+#ENDIF
 ;	
 	PRTS(" IO=0x$")
 	LD	A,FDC_MSR
@@ -1392,7 +1467,7 @@ FC_SETDOR:
 ;
 ; SET FST_DCR
 ;
-#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC) | (FDMODE == FDMODE_DYNO) | (FDMODE == FDMODE_EPFDC) | (FDMODE == FDMODE_MBC))
+#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC) | (FDMODE == FDMODE_DYNO) | (FDMODE == FDMODE_EPFDC) | (FDMODE == FDMODE_MBC) | (FDMODE == FDMODE_DUO))
 ;
 FC_SETDCR
 	LD	(FST_DCR),A
@@ -1424,7 +1499,7 @@ FC_RESETFDC:
 #IF ((FDMODE == FDMODE_ZETA) | (FDMODE == FDMODE_DIO3) | (FDMODE == FDMODE_RCSMC))
 	RES	7,A
 #ENDIF
-#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC) | (FDMODE == FDMODE_DYNO) | (FDMODE == FDMODE_EPFDC) | (FDMODE == FDMODE_MBC))
+#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC) | (FDMODE == FDMODE_DYNO) | (FDMODE == FDMODE_EPFDC) | (FDMODE == FDMODE_MBC) | (FDMODE == FDMODE_DUO))
 	LD	A,0
 #ENDIF
 	CALL	FC_SETDOR
@@ -1441,7 +1516,7 @@ FC_RESETFDC:
 FC_PULSETC:
 ; PULSING TC NO LONGER REQUIRED BECAUSE WE ONLY READ A SINGLE SECTOR
 ;
-;#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC) | (FDMODE == FDMODE_DYNO) | (FDMODE == FDMODE_EPFDC) | (FDMODE == FDMODE_MBC))
+;#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC) | (FDMODE == FDMODE_DYNO) | (FDMODE == FDMODE_EPFDC) | (FDMODE == FDMODE_MBC) | (FDMODE == FDMODE_DUO))
 ;	IN	A,(FDC_TC)
 ;#ELSE
 ;	LD	A,(FST_DOR)
@@ -1498,7 +1573,7 @@ FC_MOTORON1:
 	CP	C			; COMPARE TO NEW MOTOR BITS
 	RET	Z			; SKIP DELAY, MOTOR WAS ALREADY ON
 #ENDIF
-#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC) | (FDMODE == FDMODE_DYNO) | (FDMODE == FDMODE_EPFDC) | (FDMODE == FDMODE_MBC))
+#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC) | (FDMODE == FDMODE_DYNO) | (FDMODE == FDMODE_EPFDC) | (FDMODE == FDMODE_MBC) | (FDMODE == FDMODE_DUO))
 	; SETUP DCR FOR DIDE HARDWARE
 	LD	A,(FCD_DCR)		; GET NEW DCR VALUE
 	CALL	FC_SETDCR		; AND IMPLEMENT IT

Source/HBIOS/gdc.asm

@@ -36,16 +36,33 @@ GDC_COLS	.EQU	80
 ; *** TODO: CGA AND EGA ARE PLACEHOLDERS.  THESE EQUATES SHOULD
 ; BE USED TO ALLOW FOR MULTIPLE MONITOR TIMINGS AND/OR FONT
 ; DEFINITIONS.
+;
+	.ECHO	"GDC: MODE="
+;
+#IF (GDCMODE == GDCMODE_ECB)
+	.ECHO	"ECB"
+#ENDIF
+#IF (GDCMODE == GDCMODE_RPH)
+	.ECHO	"RPH"
+#ENDIF
+;
+	.ECHO	", DISPLAY="
 ;
 #IF (GDCMON == GDCMON_CGA)
   #DEFINE	USEFONTCGA
   #DEFINE	GDC_FONT FONTCGA
+	.ECHO	"CGA"
 #ENDIF
 ;
 #IF (GDCMON == GDCMON_EGA)
   #DEFINE	USEFONT8X16
   #DEFINE	GDC_FONT FONT8X16
+	.ECHO	"EGA"
 #ENDIF
+;
+	.ECHO	", IO="
+	.ECHO	GDC_BASE
+	.ECHO	"\n"
 ;
 TERMENABLE	.SET	TRUE		; INCLUDE TERMINAL PSEUDODEVICE DRIVER
 ;
@@ -70,7 +87,7 @@ GDC_INIT:
 #ENDIF	
 #IF (GDCMON == GDCMON_EGA)
 	PRTS(" EGA$")
-#ENDIF	
+#ENDIF
 ;
 	PRTS(" IO=0x$")
 	LD	A,GDC_BASE

Source/HBIOS/hbios.asm

@@ -71,6 +71,8 @@
 ;
 #DEFINE	HBIOS
 ;
+SUPCTS	.EQU	FALSE		; SUPPRESS CTS DURING HBIOS BOOT
+;
 ; MAKE SURE EXACTLY ONE OF ROMBOOT, APPBOOT, IMGBOOT IS DEFINED.
 ;
 MODCNT	.EQU	0
@@ -215,6 +217,24 @@ RTCDEF		.SET	RTCDEF | %00001000	; INITIAL SPEED LOW
 ;
 ;
 ;
+#IF (FPLED_ENABLE | FPSW_ENABLE)
+	.ECHO	"FP: "
+  #IF (FPLED_ENABLE)
+	.ECHO	"LEDIO="
+	.ECHO	FPLED_IO
+  #ENDIF
+  #IF (FPLED_ENABLE & FPSW_ENABLE)
+	.ECHO	", "
+  #ENDIF
+  #IF (FPSW_ENABLE)
+	.ECHO	"SWIO="
+	.ECHO	FPSW_IO
+  #ENDIF
+	.ECHO	"\n"
+#ENDIF
+;
+;
+;
 #IFNDEF	APPBOOT
 ;
 	.ORG	0
@@ -590,6 +610,25 @@ HBX_ROM:
 	RET				; DONE
 #ENDIF
 ;
+#IF (MEMMGR == MM_MON)
+;
+; CURRENTLY ASSUMES FIRST 16 PAGES ARE RAM FOLLOWED BY 16 PAGES OF ROM.
+; SO, WE MAP HBIOS BANKS $00-$0F (ROM SELECT) TO $10-$%1F AND HBIOS
+; BANKS $80-$8F (RAM SELECT) TO $00-$0F.
+;
+	BIT	7,A			; BIT 7 SET REQUESTS RAM PAGE
+	JR	Z,HBX_ROM		; NOT SET, SELECT ROM PAGE
+	RES	7,A			; RAM PAGE REQUESTED: CLEAR ROM BIT
+	OUT	($FF),A			; DO IT
+	RET				; AND DONE
+;
+HBX_ROM:
+	ADD	A,$10			; OFFSET INTO ROM BANKS
+	OUT	($FF),A			; DO IT
+	RET				; DONE
+#ENDIF
+;
+;
 ;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
 ; Copy Data - Possibly between banks.  This resembles CP/M 3, but
 ;  usage of the HL and DE registers is reversed.
@@ -991,7 +1030,8 @@ HBX_BUF_END	.EQU	$
 	.DW	0			; HB_DSTADR: BNKCPY DESTINATION ADDRESS
 	.DB	BID_USR			; HB_DSTBNK: BNKCPY DESTINATION BANK ID
 	.DW	0			; HB_CPYLEN: BNKCPY LENGTH
-	.FILL	4,0			; FILLER, RESERVED FOR FUTURE HBIOS USE
+	.DW	0			; RESERVED FOR OPTIONAL TICK CTR, PLATFORM DEPENDENT
+	.DW	0			; RESERVED FOR FUTURE HBIOS USE
 	.DB	0			; SHADOW VALUE FOR RTC LATCH PORT
 	.DB	$FE			; HB_LOCK: HBIOS MUTEX LOCK
 	JP	HBX_INVOKE		; HB_INVOKE: FIXED ADR ENTRY FOR HBX_INVOKE (ALT FOR RST 08)
@@ -1114,12 +1154,17 @@ BOOTWAIT:
 	JR	NZ,BOOTWAIT
 #ENDIF
 ;
-;#IF ((PLATFORM == PLT_MBC) | (PLATFORM == PLT_SBC))
-	; INITIALIZE RTC LATCH BYTE
+	; EARLY RTC LATCH BYTE INITIALIZATION
 	; FOR SOME PLATFORMS THIS CONTROLS HI/LO SPEED CIRCUIT
-	LD	A,(RTCDEFVAL)		; GET DEFAULT VALUE
+	; NOTE: WE WANT TO USE (RTCDEFVAL) HERE, BUT THE Z2 MEMORY
+	; MANAGER STARTS UP WITH THE FIRST 16K OF ROM MAPPED TO ALL
+	; 4 16K BANKS OF CPU SPACE.  SO, IF RTCDEVFAL IS LOCATED AFTER
+	; PAST 16K, WE DON'T HAVE ACCESS TO IT.  FOR NOW, WE JUST USE
+	; RTCDEF WHICH IS SUBOPTIMAL, BUT PROBABLY DOES NOT CAUSE ANY
+	; PROBLEMS.
+	;LD	A,(RTCDEFVAL)		; GET DEFAULT VALUE
+	LD	A,RTCDEF		; DEFAULT VALUE
 	OUT	(RTCIO),A		; SET IT
-;#ENDIF
 ;
 #IF (PLATFORM == PLT_N8)
 	LD	A,N8_DEFACR		; ENSURE N8 ACR
@@ -1141,7 +1186,9 @@ BOOTWAIT:
 	XOR	A			; LED IS INVERTED, TURN IT ON
   #ENDIF
   #IF (LEDMODE == LEDMODE_RTC)
-	LD	A,(RTCDEFVAL)		; DEFAULT LATCH VALUE
+	; CAN'T USE (RTCDEFVAL) YET, SEE COMMENTS ABOVE
+	;LD	A,(RTCDEFVAL)		; DEFAULT LATCH VALUE
+	LD	A,RTCDEF		; DEFAULT LATCH VALUE
 	OR	%00000001		; LED 0 ON
   #ENDIF
 	OUT	(LEDPORT),A
@@ -1347,6 +1394,41 @@ Z280_INITZ:
 	OUT	(FPLED_IO),A
 #ENDIF
 
+;
+; Z180 MINI-ITX MADNESS TO INITIALIZE THE PPIO. WE HAVE THE MAIN RAM AT
+; $8000 AND ROM AT $0 AT THIS POINT AND THE Z180 MMU SET UP. NOW
+; GET THE 82C55 PROGRAMMED.
+;
+#IF (PLATFORM == PLT_EPITX)
+	; THE 82C55 IS BRAINDEAD AND FLIPS OUTPUT LINES TO 0 WHEN WE SET
+	; THE MODE. WE BOOT WITH THE ROM ENABLED BUT THE RESET WILL ENABLE
+	; LOW RAM. SOME MENTAL BACKFLIPS REQUIRED TO MAKE THIS WORK
+	LD	HL,BOOTFLIP
+	LD	DE,$8000
+	LD	BC,$10
+	LDIR
+	JP	$8000
+;
+BOOTFLIP:
+	; SET THE MODE. ALSO CLEARS ALL THE OUTPUT BITS SO WE BLIP THE
+	; I2C, KEYBOARD ETC BUT NOBODY WILL CARE. HOWEVER WE ALSO FLIP
+	; TO ALL RAM MODE HENCE THIS IS EXECUTED HIGH
+	; A OUT B IN C HIGH IN C LOW IN
+	LD	A,$8B
+	OUT	($43),A
+	LD	A,$FF
+	OUT	($40),A
+	JP	ROMRESUME
+;
+ROMRESUME:
+	; THIS WILL GLITCH EXTRAM ON SO WE MUST NOW BE IN ROM
+	LD	A,$8A		; C LOW NOW OUTPUT
+	OUT	($43),A
+	LD	A,$FF
+	OUT	($42),A		; EXTRAM OFF, RAM BACK IN, SPI 7
+	; AND DONE. MODE REMAINS THIS WAY FOREVER
+;
+#ENDIF
 ;
 ; WE USE THE TWO BYTES IMMEDIATELY BELOW THE PROXY TO STORE A COUPLE
 ; VALUES TEMPORARILY BECAUSE WE MAY BE OPERATING IN ROM AT THIS POINT.
@@ -1432,11 +1514,15 @@ S100MON_SKIP:
 	LD	A,(HB_CURBNK)		; GET HB_CURBNK
 	LD	(HBX_LOC - 2),A		; ... AND SAVE TEMP FOR APPBNK
 ;
-; THE RTCVAL FIELD OF THE PROXY DATA NEEDS TO BE INITIALIZED HERE
-; BECAUSE IT CANNOT BE PRE-INITIALIZED (SEE COMMENTS ABOVE WHERE
-; RTCVAL EQUATE IS DEFINED).
+; WE CAN NOW DO THE REAL INITIALIZATION OF THE RTC LATCH BASED ON
+; (RTCDEFVAL).  AT THIS POINT WE SHOULD HAVE ACCESS TO THE ROM LOCATION
+; WHERE RTCDEFVAL IS STORED AND THE PROXY IS INSTALLED IN UPPER RAM
+; WHERE WE WILL STORE THE WORKING SHADOW COPY (HB_RTCVAL).
+; SEE COMMENTS ABOVE REGARDING THE FUNKY WAY THAT THE RTCDEFVAL IS
+; CREATED.
 ;
 	LD	A,(RTCDEFVAL)
+	OUT	(RTCIO),A		; SET IT
 	LD	(HB_RTCVAL),A
 ;
 #IFDEF TESTING
@@ -1599,51 +1685,43 @@ MBC_SINGLE:
 ;
 #ENDIF
 ;
-; IF ALREADY EXECUTING IN RAM, BYPASS RAM BANK INSTALLATION
-;
-	LD	A,(HB_RAMFLAG)
-	OR	A
-	JR	NZ,HB_START1
-;
-; IF BID_BOOT AND BID_BIOS ARE THE SAME, THEN IT IS NEVER APPROPRIATE
-; TO COPY THE HBIOS IMAGE FROM BID_BOOT TO BID_BIOS.  THIS IS TYPICALLY
-; THE CASE FOR A ROMLESS SYSTEM.
-;
-#IF (BID_BOOT != BID_BIOS)
-;
 ; INSTALL HBIOS IN RAM BANK
 ;
 	LD	A,(HB_CURBNK)
+;
+	; CHECK TO SEE IF WE ARE ALREADY RUNNING IN THE HBIOS
+	; BANK AND SKIP THE COPY IF SO (DON'T COPY OVER OURSELVES).
+	; THIS SITUATION OCCURS ON A ROMLESS STARTUP OR WHEN DOING A
+	; FULL RESTART OF A SYSTEM USING THE EXISTING HBIOS COPY.
+	CP	BID_BIOS
+	JR	Z,HB_START1
+;
 	LD	(HB_SRCBNK),A
 	LD	A,BID_BIOS
 	LD	(HB_DSTBNK),A
 	LD	HL,0
 	LD	DE,0
 	LD	BC,$8000
-  #IF (MEMMGR == MM_Z280)
+#IF (MEMMGR == MM_Z280)
 	CALL	Z280_BNKCPY
-  #ELSE
+#ELSE
 	CALL	HBX_BNKCPY
-  #ENDIF
+#ENDIF
 ;
 ; TRANSITION TO HBIOS IN RAM BANK
 ;
-  #IF (MEMMGR == MM_Z280)
+#IF (MEMMGR == MM_Z280)
 	LD	A,BID_BIOS
 	LD	B,$10			; FIRST SYSTEM PDR
 	CALL	Z280_BNKSEL
 	JR	HB_START1
-  #ELSE
+#ELSE
 	LD	A,BID_BIOS		; BIOS BANK ID
 	LD	IX,HB_START1		; EXECUTION RESUMES HERE
 	CALL	HBX_BNKCALL		; CONTINUE IN RAM BANK, DO NOT RETURN
 	HALT				; WE SHOULD NOT COME BACK HERE!
-  #ENDIF
-;
 #ENDIF
 ;
-HB_RAMFLAG	.DB	FALSE		; INITIALLY FALSE, SET TO TRUE BELOW AFTER RAM TRANSITION
-;
 ; EXECUTION RESUMES HERE AFTER SWITCH TO RAM BANK
 ;
 HB_START1:				; BNKCALL ARRIVES HERE, BUT NOW RUNNING IN RAM BANK
@@ -1857,11 +1935,13 @@ HB_CPU1:
 ;
 ; CLEAR DISPATCH TABLE ENTRIES
 ;
-	XOR	A		; ZERO
-	LD	(CIO_CNT),A	; CIO DEVICES
-	LD	(DIO_CNT),A	; DIO DEVICES
-	LD	(VDA_CNT),A	; VDA DEVICES
-	LD	(SND_CNT),A	; SND DEVICES
+	XOR	A			; ZERO
+	LD	(CIO_CNT),A		; CIO DEVICES
+	LD	(DIO_CNT),A		; DIO DEVICES
+	LD	(VDA_CNT),A		; VDA DEVICES
+	LD	(SND_CNT),A		; SND DEVICES
+	LD	(RTC_DISPACT),A		; RTC DEVICE
+	LD	(DSKY_DISPACT),A	; DSKY DEVICE
 ;
 #IF (DSRTCENABLE)
 	CALL	DSRTC_PREINIT
@@ -2060,7 +2140,7 @@ HB_CPU3:
 	LD	A,(CB_CPUMHZ)		; CPU SPEED TO ACCUM AND INIT
 	CALL	DELAY_INIT		; .. SPEED COMPENSATED DELAY
 ;
-#IF (INTMODE == 2)
+#IF ((INTMODE == 2) | ((INTMODE == 1) & (CPUFAM == CPU_Z180)))
 	; SETUP Z80 IVT AND INT MODE 2
 	LD	A,HBX_IVT >> 8		; SETUP HI BYTE OF IVT ADDRESS
 	LD	I,A			; ... AND PLACE IT IN I REGISTER
@@ -2071,7 +2151,9 @@ HB_CPU3:
 	OUT0	(Z180_IL),A		; ... AND PLACE IN Z180 IL REGISTER
   #ENDIF
 
+  #IF (INTMODE == 2)
 	IM	2			; SWITCH TO INT MODE 2
+  #ENDIF
 #ENDIF
 ;
 #IF (INTMODE == 3)
@@ -2300,8 +2382,36 @@ HB_BOOTDLY:
 	JR	C,HB_CONRDY		; IF TOO HIGH, JUST USE FAILSAFE
 	LD	A,BOOTCON		; GET REQUESTED CONSOLE DEV
 	LD	(CB_CONDEV),A		; SAVE IT
+;
 HB_CONRDY:
 ;
+#IF (SUPCTS)
+;
+; MOST SERIAL PORTS ARE CONFIGURED WITH HARDWARE FLOW CONTROL ENABLED.
+; IF THERE IS A PROBLEM WITH THE CTS SIGNAL, THEN OUTPUT TO THE CONSOLE
+; WILL BE STALLED WHICH CAN LEAD A USER TO THINK THE SYSTEM IS TOTALLY
+; DEAD WHEN, IN FACT, IT IS JUST WAITING FOR CTS TO BE ASSERTED.  ALSO,
+; IF THE USER IS BOOTING TO A CRT DEVICE AND DISCONNECTS THE CONSOLE
+; SERIAL PORT, THE SYSTEM WILL WAIT FOR RTS AND NEVER BOOT.  SO, HERE
+; WE SAVE THE ACTIVE CONSOLE CONFIGURATION, THEN TURN OFF HARDWARE
+; FLOW CONTROL.  THE ORIGINAL CONFIGURATION WILL BE RESTORED BELOW
+; PRIOR TO LAUNCING THE ROM LOADER.
+;
+	; RETRIEVE THE CONFIG FROM THE CONSOLE PORT
+	LD	B,BF_CIOQUERY		; HBIOS QUERY CIO CONFIG
+	LD	A,(CB_CONDEV)		; GET CONSOLE DEVICE
+	LD	(HB_BOOTCONSAV),A	; SAVE IT FOR LATER
+	LD	C,A			; BOOT CONSOLE TO C
+	CALL	HB_DISPATCH		; INTERNAL HBIOS CALL
+	LD	(HB_CONCFGSAV),DE	; SAVE CONFIG
+	RES	5,D			; CLEAR RTS BIT
+	LD	B,BF_CIOINIT		; HBIOS CIO INIT
+	LD	A,(CB_CONDEV)		; GET CONSOLE DEVICE
+	LD	C,A			; BOOT CONSOLE TO C
+	CALL	HB_DISPATCH		; INTERNAL HBIOS CALL
+;
+#ENDIF
+;
 #IF (WBWDEBUG == USEMIO)		; OUTPUT ANY CACHED DEBUG TEXT
 	LD	HL,MIOOUTPTR
 	LD	E,(HL)
@@ -2825,19 +2935,27 @@ HB_FP1:
 ;
 HB_FP2:
 	; IF SEC SWITCH IS SET, WE WANT TO BUMP TO SECONDARY
-	; CRT OR SERIAL DEVICE.  FOR NOW, WE ARE GOING TO CHEAT AND
-	; JUST INCREMENT THE CONSOLE DEVICE UNIT.  THIS SHOULD WORK
-	; ASSUMING NORMAL ORDERING OF THE CHARACTER DEVICE UNITS.
+	; CRT OR SERIAL DEVICE. IF AN OVERRIDE IS SPECIFIED USING
+	; SECCON, USE THAT, OTHERWISE INCREMENT THE DEFAULT UNIT.
+	; THIS SHOULD WORK ASSUMING NORMAL ORDERING OF THE
+	; CHARACTER DEVICE UNITS.
 	LD	A,B			; RECOVER SWITCH SETTINGS
 	AND	SW_SEC			; TEST SEC BIT
 	JR	Z,HB_FPZ		; IF NOT SET, THEN ALL DONE
 ;
-	; INCREMENT CONSOLE UNIT, BUT MAKE SURE IT DOES NOT EXCEED
-	; THE HIGHEST CHAR UNIT IN SYSTEM.
 	LD	A,(CIO_CNT)		; GET CHAR UNIT COUNT
 	LD	B,A			; MOVE TO B
+	LD	A,SECCON		; GET SEC CONSOLE SETTING
+	CP	$FF			; $FF MEANS USE INCREMENT
+	JR	NZ,HB_FP3		; BYPASS IF NOT $FF 
+;
+	; INCREMENT CONSOLE UNIT
 	LD	A,(HB_NEWCON)		; GET NEW CONSOLE UNIT
 	INC	A			; BUMP TO SECONDARY
+;
+HB_FP3:
+	; MAKE SURE NEW CONSOLE UNIT DOES NOT EXCEED THE HIGHEST
+	; CHAR UNIT IN SYSTEM.
 	CP	B			; A (UNIT) >= B (CNT)?
 	JR	NC,HB_FPZ		; ABORT IF UNIT TOO HIGH
 	LD	(HB_NEWCON),A		; UPDATE NEW CONSOLE UNIT
@@ -2848,6 +2966,19 @@ HB_FPZ:
 ;
 INITSYS3:
 ;
+#IF (SUPCTS)
+;
+; RESTORE BOOT CONSOLE CONFIGURATION
+;
+	CALL	LDELAY			; ALLOW SERIAL PORT TO FLUSH
+	LD	B,BF_CIOINIT		; HBIOS CIO INIT
+	LD	A,(HB_BOOTCONSAV)	; ORIGINAL BOOT CONSOLE DEVICE
+	LD	C,A			; BOOT CONSOLE TO C
+	LD	DE,(HB_CONCFGSAV)	; SAVED ORIGINAL CONSOLE CFG
+	CALL	HB_DISPATCH		; INTERNAL HBIOS CALL
+;
+#ENDIF
+;
 ; IF WE ARE GOING TO SWITCH CONSOLES, IT IS IMPLEMENTED HERE.  A
 ; MESSAGE IS PRINTED ON THE OLD CONSOLE INDICATING WHERE THE NEW
 ; CONSOLE IS AND THE NEW CONSOLE RECEIVES AN HBIOS BANNER.
@@ -5380,10 +5511,10 @@ HB_BADINTCNT	.DB	0
 	LD	A,L
 	RRCA
 	RRCA
-	CALL PRTHEXBYTE
-	PRTS("H: $")
-
+	;CALL PRTHEXBYTE
+	;PRTS("H: $")
 	CALL	XREGDMP
+	CALL	NEWLINE
 	;CALL	CONTINUE
 	OR	$FF			; SIGNAL INTERRUPT HANDLED
 	RET
@@ -7721,6 +7852,11 @@ HB_BOOTCON	.DB	0		; INITIAL BOOT CONSOLE SAVE AREA
 HB_BOOTCFG	.DW	0		; CONSOLE CONFIG SAVE AREA
 HB_NEWCON	.DB	0		; NEW CONSOLE TO SWITCH TO
 ;
+#IF (SUPCTS)
+HB_BOOTCONSAV	.DB	0		; INITIAL BOOT CONSOLE SAVE AREA
+HB_CONCFGSAV	.DW	0		; CONSOLE CONFIG SAVE AREA
+#ENDIF
+;
 HB_HASFP	.DB	0		; NON-ZERO MEANS FP EXISTS
 ;
 HB_WRKBUF	.FILL	512,0		; INTERNAL DISK BUFFER

Source/HBIOS/hbios.inc

@@ -153,6 +153,8 @@ PLT_Z80RETRO	.EQU	15		; Z80 RETRO COMPUTER
 PLT_S100	.EQU	16		; S100 COMPUTERS Z180 SYSTEM
 PLT_DUO		.EQU	17		; DUODYNE Z80 SYSTEM
 PLT_HEATH	.EQU	18		; HEATHKIT H8 Z80 SYSTEM
+PLT_EPITX	.EQU	19		; Z180 MINI-ITX
+PLT_MON		.EQU	20		; MONSPUTER
 ;
 ; HBIOS GLOBAL ERROR RETURN VALUES
 ;

Source/HBIOS/hdsk.asm

@@ -21,6 +21,12 @@ HDSK_CFGSIZ	.EQU	6		; SIZE OF CFG TBL ENTRIES
 HDSK_DEV	.EQU	0		; OFFSET OF DEVICE NUMBER (BYTE)
 HDSK_STAT	.EQU	1		; OFFSET OF STATUS (BYTE)
 HDSK_LBA	.EQU	2		; OFFSET OF LBA (DWORD)
+;
+	.ECHO	"HDSK: IO="
+	.ECHO	HDSK_IO
+	.ECHO	", DEVICE COUNT="
+	.ECHO	HDSK_DEVCNT
+	.ECHO	"\n"
 ;
 HDSK_CFGTBL:
 	; DEVICE 0

Source/HBIOS/ide.asm

@@ -213,6 +213,27 @@ IDE_DEV0M:	; DEVICE 0, MASTER
 	.DB	IDE0DATLO		; IO BASE ADDRESS
 	.DB	IDE0DATHI		; IO BASE ADDRESS
 	.DW	IDE_DEV0S		; PARTNER
+;
+	.ECHO	"IDE: MODE="
+  #IF (IDE0MODE == IDEMODE_NONE)
+	.ECHO	"NONE"
+  #ENDIF
+  #IF (IDE0MODE == IDEMODE_DIO)
+	.ECHO	"DIO"
+  #ENDIF
+  #IF (IDE0MODE == IDEMODE_DIDE)
+	.ECHO	"DIDE"
+  #ENDIF
+  #IF (IDE0MODE == IDEMODE_MK4)
+	.ECHO	"MK4"
+  #ENDIF
+  #IF (IDE0MODE == IDEMODE_RC)
+	.ECHO	"RC"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	IDE0BASE
+	.ECHO	", MASTER"
+	.ECHO	"\n"
 ;
 IDE_DEV0S:	; DEVICE 0, SLAVE
 	.DB	$FE			; DRIVER DEVICE NUMBER (FILLED DYNAMICALLY)
@@ -227,6 +248,27 @@ IDE_DEV0S:	; DEVICE 0, SLAVE
 	.DB	IDE0DATLO		; IO BASE ADDRESS
 	.DB	IDE0DATHI		; IO BASE ADDRESS
 	.DW	IDE_DEV0M		; PARTNER
+;
+	.ECHO	"IDE: MODE="
+  #IF (IDE0MODE == IDEMODE_NONE)
+	.ECHO	"NONE"
+  #ENDIF
+  #IF (IDE0MODE == IDEMODE_DIO)
+	.ECHO	"DIO"
+  #ENDIF
+  #IF (IDE0MODE == IDEMODE_DIDE)
+	.ECHO	"DIDE"
+  #ENDIF
+  #IF (IDE0MODE == IDEMODE_MK4)
+	.ECHO	"MK4"
+  #ENDIF
+  #IF (IDE0MODE == IDEMODE_RC)
+	.ECHO	"RC"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	IDE0BASE
+	.ECHO	", SLAVE"
+	.ECHO	"\n"
 #ENDIF
 ;
 #IF (IDECNT >= 2)
@@ -244,6 +286,27 @@ IDE_DEV1M:	; DEVICE 1, MASTER
 	.DB	IDE1DATLO		; IO BASE ADDRESS
 	.DB	IDE1DATHI		; IO BASE ADDRESS
 	.DW	IDE_DEV1S		; PARTNER
+;
+	.ECHO	"IDE: MODE="
+  #IF (IDE1MODE == IDEMODE_NONE)
+	.ECHO	"NONE"
+  #ENDIF
+  #IF (IDE1MODE == IDEMODE_DIO)
+	.ECHO	"DIO"
+  #ENDIF
+  #IF (IDE1MODE == IDEMODE_DIDE)
+	.ECHO	"DIDE"
+  #ENDIF
+  #IF (IDE1MODE == IDEMODE_MK4)
+	.ECHO	"MK4"
+  #ENDIF
+  #IF (IDE1MODE == IDEMODE_RC)
+	.ECHO	"RC"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	IDE1BASE
+	.ECHO	", MASTER"
+	.ECHO	"\n"
 ;
 IDE_DEV1S:	; DEVICE 1, SLAVE
 	.DB	$FE			; DRIVER DEVICE NUMBER (FILLED DYNAMICALLY)
@@ -258,6 +321,27 @@ IDE_DEV1S:	; DEVICE 1, SLAVE
 	.DB	IDE1DATLO		; IO BASE ADDRESS
 	.DB	IDE1DATHI		; IO BASE ADDRESS
 	.DW	IDE_DEV1M		; PARTNER
+;
+	.ECHO	"IDE: MODE="
+  #IF (IDE1MODE == IDEMODE_NONE)
+	.ECHO	"NONE"
+  #ENDIF
+  #IF (IDE1MODE == IDEMODE_DIO)
+	.ECHO	"DIO"
+  #ENDIF
+  #IF (IDE1MODE == IDEMODE_DIDE)
+	.ECHO	"DIDE"
+  #ENDIF
+  #IF (IDE1MODE == IDEMODE_MK4)
+	.ECHO	"MK4"
+  #ENDIF
+  #IF (IDE1MODE == IDEMODE_RC)
+	.ECHO	"RC"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	IDE1BASE
+	.ECHO	", SLAVE"
+	.ECHO	"\n"
 #ENDIF
 ;
 #IF (IDECNT >= 3)
@@ -275,6 +359,27 @@ IDE_DEV2M:	; DEVICE 2, MASTER
 	.DB	IDE2DATLO		; IO BASE ADDRESS
 	.DB	IDE2DATHI		; IO BASE ADDRESS
 	.DW	IDE_DEV2S		; PARTNER
+;
+	.ECHO	"IDE: MODE="
+  #IF (IDE2MODE == IDEMODE_NONE)
+	.ECHO	"NONE"
+  #ENDIF
+  #IF (IDE2MODE == IDEMODE_DIO)
+	.ECHO	"DIO"
+  #ENDIF
+  #IF (IDE2MODE == IDEMODE_DIDE)
+	.ECHO	"DIDE"
+  #ENDIF
+  #IF (IDE2MODE == IDEMODE_MK4)
+	.ECHO	"MK4"
+  #ENDIF
+  #IF (IDE2MODE == IDEMODE_RC)
+	.ECHO	"RC"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	IDE2BASE
+	.ECHO	", MASTER"
+	.ECHO	"\n"
 ;
 IDE_DEV2S:	; DEVICE 2, SLAVE
 	.DB	$FE			; DRIVER DEVICE NUMBER (FILLED DYNAMICALLY)
@@ -289,6 +394,27 @@ IDE_DEV2S:	; DEVICE 2, SLAVE
 	.DB	IDE2DATLO		; IO BASE ADDRESS
 	.DB	IDE2DATHI		; IO BASE ADDRESS
 	.DW	IDE_DEV1M		; PARTNER
+;
+	.ECHO	"IDE: MODE="
+  #IF (IDE2MODE == IDEMODE_NONE)
+	.ECHO	"NONE"
+  #ENDIF
+  #IF (IDE2MODE == IDEMODE_DIO)
+	.ECHO	"DIO"
+  #ENDIF
+  #IF (IDE2MODE == IDEMODE_DIDE)
+	.ECHO	"DIDE"
+  #ENDIF
+  #IF (IDE2MODE == IDEMODE_MK4)
+	.ECHO	"MK4"
+  #ENDIF
+  #IF (IDE2MODE == IDEMODE_RC)
+	.ECHO	"RC"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	IDE2BASE
+	.ECHO	", SLAVE"
+	.ECHO	"\n"
 #ENDIF
 ;
 #IF ($ - IDE_CFGTBL) != (IDE_DEVCNT * IDE_CFGSIZ)
@@ -1265,8 +1391,8 @@ IDE_RESET:
 ; IMMEDIATELY.  A SMALL WAIT IS PERFORMED HERE TO GIVE SUCH DEVICES
 ; A BETTER CHANCE TO SUCCEED LATER.
 ;
-;;;	CALL	LDELAY			; DELAY FOR SLAVE INIT
-	LD	DE,150000 / 16		; 
+;	LD	DE,150000 / 16		; 
+	LD	DE,300000 / 16		; 
 	CALL	VDELAY			; SMALL DELAY
 ;
 	JR	IDE_RESET3		; SKIP SOFT RESET

Source/HBIOS/imm.asm

@@ -1525,6 +1525,17 @@ IMM0_CFG:	; DEVICE 0
 	.DB	IMM0BASE		; IO BASE ADDRESS
 	.DW	0,0			; DEVICE CAPACITY
 	.DW	0,0			; CURRENT LBA
+;
+	.ECHO	"IMM: MODE="
+  #IF (IMMMODE == IMMMODE_SPP)
+	.ECHO	"SPP"
+  #ENDIF
+  #IF (IMMMODE == IMMMODE_MG014)
+	.ECHO	"MG014"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	IMM0BASE
+	.ECHO	"\n"
 #ENDIF
 ;
 #IF (IMMCNT >= 2)
@@ -1536,6 +1547,17 @@ IMM1_CFG:	; DEVICE 1
 	.DB	IMM1BASE		; IO BASE ADDRESS
 	.DW	0,0			; DEVICE CAPACITY
 	.DW	0,0			; CURRENT LBA
+;
+	.ECHO	"IMM: MODE="
+  #IF (IMMMODE == IMMMODE_SPP)
+	.ECHO	"SPP"
+  #ENDIF
+  #IF (IMMMODE == IMMMODE_MG014)
+	.ECHO	"MG014"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	IMM1BASE
+	.ECHO	"\n"
 #ENDIF
 ;
 #IF ($ - IMM_CFG) != (IMMCNT * IMM_CFGSIZ)

Source/HBIOS/intrtc.asm

@@ -4,6 +4,8 @@
 ;==================================================================================================
 ;
 INTRTC_BUFSIZ	.EQU	6	; SIX BYTE BUFFER (YYMMDDHHMMSS)
+;
+		.ECHO	"INTRTC: ENABLED\n"
 ;
 ; RTC DEVICE INITIALIZATION ENTRY
 ;

Source/HBIOS/kbd.asm

@@ -55,6 +55,8 @@ KBD_RSTATE	.DB	0	; STATE BITS FOR "RIGHT" KEYS
 KBD_STATUS	.DB	0	; CURRENT STATUS BITS (SEE ABOVE)
 KBD_REPEAT	.DB	0	; CURRENT REPEAT RATE
 KBD_IDLE	.DB	0	; IDLE COUNT
+;
+	.ECHO	"KBD: ENABLED\n"
 ;
 ;__________________________________________________________________________________________________
 ; KEYBOARD INITIALIZATION

Source/HBIOS/lpt.asm

@@ -346,10 +346,10 @@ LPT_DETECT:
 	LD	A,$A5			; TEST VALUE
 	OUT	(C),A			; PUSH VALUE TO PORT
 	IN	A,(C)			; GET PORT VALUE
-#IF (LPTTRACE >= 3)
+  #IF (LPTTRACE >= 3)
 	CALL	PC_SPACE
 	CALL	PRTHEXBYTE
-#ENDIF
+  #ENDIF
 	CP	$A5			; CHECK FOR TEST VALUE
 	JR	Z,LPT_DETECT1		; FOUND IT
 	LD	A,LPTMODE_NONE		; NOT FOUND
@@ -420,6 +420,17 @@ LPT0_CFG:
 	.DB	0			; MODULE ID
 	.DB	LPT0BASE		; BASE PORT
 	.DW	0			; LINE CONFIGURATION
+;
+	.ECHO	"LPT: MODE="
+  #IF (LPTMODE == LPTMODE_SPP)
+	.ECHO	"SPP"
+  #ENDIF
+  #IF (LPTMODE == LPTMODE_MG014)
+	.ECHO	"MG014"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	LPT0BASE
+	.ECHO	"\n"
 ;
 LPT_CFGSIZ	.EQU	$ - LPT_CFG	; SIZE OF ONE CFG TABLE ENTRY
 ;
@@ -432,6 +443,17 @@ LPT1_CFG:
 	.DB	1			; MODULE ID
 	.DB	LPT1BASE		; BASE PORT
 	.DW	0			; LINE CONFIGURATION
+;
+	.ECHO	"LPT: MODE="
+  #IF (LPTMODE == LPTMODE_SPP)
+	.ECHO	"SPP"
+  #ENDIF
+  #IF (LPTMODE == LPTMODE_MG014)
+	.ECHO	"MG014"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	LPT1BASE
+	.ECHO	"\n"
 ;
 #ENDIF
 ;

Source/HBIOS/md.asm

@@ -39,6 +39,8 @@ MD_CFGTBL:
 	.DW	0,0			; CURRENT LBA
 	.DB	MID_MDRAM		; DEVICE MEDIA ID
 	.DB	MD_ARAM			; DEVICE ATTRIBUTE
+;
+	.ECHO	"MD: TYPE=RAM\n"
 #ENDIF
 ;
 #IF (MDROM)
@@ -48,6 +50,8 @@ MD_CFGTBL:
 	.DW	0,0			; CURRENT LBA
 	.DB	MID_MDROM		; DEVICE MEDIA ID
 	.DB	MD_AROM			; DEVICE ATTRIBUTE
+;
+	.ECHO	"MD: TYPE=ROM\n"
 #ENDIF
 ;
 MD_DEVCNT	.EQU	($ - MD_CFGTBL) / MD_CFGSIZ

Source/HBIOS/pcf.asm

@@ -93,6 +93,10 @@ PCF_PINTO	.EQU	65000
 PCF_ACKTO	.EQU	65000
 PCF_BBTO	.EQU	65000
 PCF_LABDLY	.EQU	65000
+;
+	.ECHO	"PCF: IO="
+	.ECHO	PCF_BASE
+	.ECHO	"\n"
 ;
 ; DATA PORT REGISTERS
 ;

Source/HBIOS/pio.asm

@@ -307,6 +307,10 @@ PIO0A_CFG:
 	.DB	PIO0A_DAT		; DATA PORT
 	.DW	DEFSERCFG		; LINE CONFIGURATION
 	.DW	PIO0A_RCVBUF		; POINTER TO RCV BUFFER STRUCT
+;
+	.ECHO	"PIO: IO="
+	.ECHO	PIO0BASE
+	.ECHO	", CHANNEL A\n"
 ;
 PIO_CFGSIZ	.EQU	$ - PIO_CFG	; SIZE OF ONE CFG TABLE ENTRY
 ;
@@ -319,6 +323,10 @@ PIO0B_CFG:
 	.DB	PIO0B_DAT		; DATA PORT
 	.DW	DEFSERCFG		; LINE CONFIGURATION
 	.DW	PIO0B_RCVBUF		; POINTER TO RCV BUFFER STRUCT
+;
+	.ECHO	"PIO: IO="
+	.ECHO	PIO0BASE
+	.ECHO	", CHANNEL B\n"
 ;
 #IF (PIOCNT >= 2)
 ;
@@ -331,6 +339,10 @@ PIO1A_CFG:
 	.DB	PIO1A_DAT		; DATA PORT
 	.DW	DEFSERCFG		; LINE CONFIGURATION
 	.DW	PIO1A_RCVBUF		; POINTER TO RCV BUFFER STRUCT
+;
+	.ECHO	"PIO: IO="
+	.ECHO	PIO1BASE
+	.ECHO	", CHANNEL A\n"
 ;
 	; PIO1 CHANNEL B
 PIO1B_CFG:
@@ -341,6 +353,10 @@ PIO1B_CFG:
 	.DB	PIO1B_DAT		; DATA PORT
 	.DW	DEFSERCFG		; LINE CONFIGURATION
 	.DW	PIO1B_RCVBUF		; POINTER TO RCV BUFFER STRUCT
+;
+	.ECHO	"PIO: IO="
+	.ECHO	PIO1BASE
+	.ECHO	", CHANNEL B\n"
 ;
 #ENDIF
 ;