Applications Document Overhaul by MartinR

- ROM Applications document has been consolidated into the Applications document
- Martin has done a significant overhaul of the Applications document

Co-Authored-By: MartinR <174514335+martinr-uk@users.noreply.github.com>

.gitignore

@@ -99,6 +99,7 @@ Tools/unix/zx/zx
 !Source/ZRC512/*.bin
 !Source/Z1RCC/*.bin
 !Source/ZZRCC/*.bin
+!Source/FZ80/*.bin
 !Tools/cpm/**
 !Tools/unix/zx/*
 !Tools/zx/*

Binary/Apps/Clean.cmd

@@ -8,5 +8,6 @@ if exist *.hlp del *.hlp
 if exist Tunes\*.pt? del Tunes\*.pt?
 if exist Tunes\*.mym del Tunes\*.mym
 if exist Tunes\*.vgm del Tunes\*.vgm
+if exist bbcbasic.txt del bbcbasic.txt
 
 pushd Test && call Clean || exit /b 1 & popd

Binary/Apps/Makefile

@@ -8,4 +8,4 @@ all::
 	mkdir -p Tunes
 
 clean::
-	@rm -f *.bin *.com *.img *.rom *.pdf *.log *.eeprom *.ovr *.hlp *.doc *.COM *.BIN Tunes/*.mym Tunes/*.pt? Tunes/*.vgm
+	@rm -f *.bin *.com *.img *.rom *.pdf *.log *.eeprom *.ovr *.hlp *.doc *.COM *.BIN Tunes/*.mym Tunes/*.pt? Tunes/*.vgm bbcbasic.txt

Binary/Apps/Test/inttest.doc

@@ -0,0 +1,44 @@
+INTTEST
+=======
+
+RomWBW includes an API allowing applications to "hook" interrupts.
+The `INTTEST` utility allows you to test this functionality.
+
+
+** Syntax **
+
+`INTTEST`
+
+
+** Usage **
+
+`INTTEST` is an interactive application.  At startup, it will display
+a list of the interrupt vector slots in your system along with the
+current vector address for each of them.
+
+It then prompts you to enter the slot number (in hex) of a vector to
+hook.  After entering this, the application will watch the hooked
+vector and countdown from 0xFF to 0x00 as interrupts are noted.
+
+When the counter reaches 0x00, the interrupt is unhooked and the
+application terminates.  The application can also be terminated by
+pressing <esc>.
+
+
+** Notes **
+
+If your system is running without interrupts active, the application
+will terminate immediately.
+
+All slots have vectors even if the corresponding interrupt is not
+doing anything.  In this case, the vector is pointing to the "bad
+interrupt" handler.
+
+If you hook a vector that is not receiving any interrupts, the
+down-counter will not do anything.
+
+
+** Etymology* *
+
+The `INTTEST` command is an original product and the source code is
+provided in the RomWBW distribution.

Doc/CPM/ReadMe.txt

@@ -7,8 +7,8 @@
 ***********************************************************************
 
 This directory ("Doc/CPM") is part of the RomWBW System Software
-distribution archive.  It contains documentation for the CP/M
-operating system components of the system.
+distribution archive.  It contains documentation for the CP/M and
+CP/M work-alike operating system components of the system.
 
 
 CPM Manual ("CPM Manual.pdf")

Doc/ChangeLog.txt

@@ -15,6 +15,15 @@ Version 3.5
 - WBW: Auto restore TMS video on user reset (CP/M warm boot)
 - L?B: Added support for NABU w/ RomWBW Option Board
 - M?P: Reorganization of Doc directory introducing subfolders
+- WBW: Upgraded BBCBASIC to v5.00
+- W?S: Updated FLASH utility to v1.3.9
+- WBW: Support RCBus PS/2 Keyboard (EP/Sally)
+- M?R: Update Timer app to display output in decimal
+- WBW: Preliminary support for S100 FPGA Z80 platform
+- WBW: Added simple serial (SSER) driver
+- WBW: Added preliminary support for S100 FPGA Z80 SD Cards
+- M?R: Consolidated ROM Applications document into the Applications document
+- M?R: Reviewed and substantially improved the Applications document
 
 Version 3.4
 -----------

ReadMe.md

@@ -3,7 +3,7 @@
 **RomWBW ReadMe** \
 Version 3.5 \
 Wayne Warthen  ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \
-13 May 2024
+03 Jul 2024
 
 # Overview
 
@@ -112,22 +112,20 @@ functionality.
 
 Complete instructions for installation and operation of RomWBW are found
 in the [RomWBW User
-Guide](https://github.com/wwarthen/RomWBW/raw/dev/Doc/RomWBW%20User%20Guide.pdf).
+Guide](https://github.com/wwarthen/RomWBW/raw/master/Doc/RomWBW%20User%20Guide.pdf).
 
 ## Documentation
 
 Documentation for RomWBW includes:
 
 - [RomWBW User
-  Guide](https://github.com/wwarthen/RomWBW/raw/dev/Doc/RomWBW%20User%20Guide.pdf)
+  Guide](https://github.com/wwarthen/RomWBW/raw/master/Doc/RomWBW%20User%20Guide.pdf)
 - [RomWBW System
-  Guide](https://github.com/wwarthen/RomWBW/raw/dev/Doc/RomWBW%20System%20Guide.pdf)
+  Guide](https://github.com/wwarthen/RomWBW/raw/master/Doc/RomWBW%20System%20Guide.pdf)
 - [RomWBW
-  Applications](https://github.com/wwarthen/RomWBW/raw/dev/Doc/RomWBW%20Applications.pdf)
-- [RomWBW ROM
-  Applications](https://github.com/wwarthen/RomWBW/raw/dev/Doc/RomWBW%20ROM%20Applications.pdf)
+  Applications](https://github.com/wwarthen/RomWBW/raw/master/Doc/RomWBW%20Applications.pdf)
 - [RomWBW
-  Errata](https://github.com/wwarthen/RomWBW/raw/dev/Doc/RomWBW%20Errata.pdf)
+  Errata](https://github.com/wwarthen/RomWBW/raw/master/Doc/RomWBW%20Errata.pdf)
 
 # Acknowledgments
 

ReadMe.txt

@@ -1,6 +1,6 @@
 RomWBW ReadMe
 Wayne Warthen (wwarthen@gmail.com)
-13 May 2024
+03 Jul 2024
 
 
 
@@ -122,7 +122,6 @@ Documentation for RomWBW includes:
 -   RomWBW User Guide
 -   RomWBW System Guide
 -   RomWBW Applications
--   RomWBW ROM Applications
 -   RomWBW Errata
 
 

Source/Apps/BBCBASIC/Build.cmd

@@ -0,0 +1,23 @@
+@echo off
+setlocal
+
+set TOOLS=..\..\..\Tools
+
+set PATH=%TOOLS%\zxcc;%PATH%
+
+set CPMDIR80=%TOOLS%/cpm/
+
+zxcc z80asm -dist/FM
+zxcc z80asm -main/FM
+zxcc z80asm -exec/FM
+zxcc z80asm -eval/FM
+zxcc z80asm -asmb/FM
+zxcc z80asm -cmos/FM
+zxcc z80asm -math/FM
+zxcc z80asm -hook/FM
+zxcc z80asm -data/FM
+
+zxcc slrnk -/v,/a:0100,dist,main,exec,eval,asmb,math,hook,cmos,/p:4B00,data,bbcbasic/n,/e
+
+copy /Y bbcbasic.com ..\..\..\Binary\Apps\ || exit /b
+copy /Y bbcbasic.txt ..\..\..\Binary\Apps\ || exit /b

Source/Apps/BBCBASIC/Clean.cmd

@@ -0,0 +1,9 @@
+@echo off
+setlocal
+
+if exist *.com del *.com
+if exist *.lst del *.lst
+if exist *.hex del *.hex
+if exist *.prn del *.prn
+if exist *.rel del *.rel
+if exist *.sym del *.sym

Source/Apps/BBCBASIC/Makefile

@@ -0,0 +1,11 @@
+OBJECTS = bbcbasic.com
+DOCS = bbcbasic.txt
+DEST = ../../../Binary/Apps
+DOCDEST = ../../../Binary/Apps
+TOOLS = ../../../Tools
+OTHERS = *.rel
+
+include $(TOOLS)/Makefile.inc
+
+bbcbasic.com: dist.rel main.rel exec.rel eval.rel asmb.rel cmos.rel math.rel hook.rel data.rel
+	$(ZXCC) SLRNK -/V,/A:0100,DIST,MAIN,EXEC,EVAL,ASMB,MATH,HOOK,CMOS,/P:4B00,DATA,BBCBASIC/N,/E

Source/Apps/BBCBASIC/bbcbasic.txt

@@ -1,3 +1,20 @@
+This is a RomWBW HBIOS adaptation of BBCBASIC v5.00.  The
+cursor and screen management assumes the use of an ANSI/VT-100 terminal
+which is generally correct for RomWBW.  Support for a hardware system
+timer is also implemented.  If your system does not have a hardware
+timer, the TIME function will always return 0 and the timeout
+parameter of the INKEY(n) function will not be observed (will never
+timeout).
+
+What follows is some basic information on BBCBASIC from the
+distribution.  Note that it starts with the v3.00 information and
+later on provides information on the changes in v5.00.
+
+-- WBW 1:15 PM 5/30/2024
+
+
+
+
                               BBC BASIC (Z80)
 
                          Generic CP/M Version 3.00
@@ -366,4 +383,73 @@
      198  Disk full                254  Bad command
      200  Close error              255  CP/M error
      204  Bad name
-
+
+
+New features in BBC BASIC (Z80) version 5.00, May 2024:
+
+1. BASIC V statements
+
+1.1  WHILE...ENDWHILE
+1.2  Multi-line IF...THEN...ELSE...ENDIF
+1.3  CASE...WHEN...OTHERWISE...ENDCASE
+1.4  LOCAL DATA / RESTORE DATA
+1.5  ON ERROR LOCAL / RESTORE ERROR
+1.6  DIM var LOCAL size 
+1.7  ERROR err, message$
+1.8  RESTORE +n
+1.9  SWAP var1,var2
+1.10 BPUT #file,string$[;]
+1.11 QUIT
+
+2. BASIC V functions
+
+2.1  DIM(array()[,sub])
+2.2  END (pointer to free space)
+2.3  REPORT$
+2.4  Binary constants
+2.5  LEFT$ & RIGHT$ with last parameter omitted
+2.6  MOD(array)
+2.7  SUM(array)
+2.8  SUMLEN(array)
+2.9  GET$#file 
+
+3. BASIC V whole array operations
+
+3.1  Pass a whole array to a FN/PROC
+3.2  Pass a whole array to CALL
+3.3  Whole array assignment
+3.4  Whole array arithmetic *
+3.5  Array dot-product operator
+3.6  Array initialisation lists
+3.7  Array compound assignment (+= etc.)
+3.8  Make a whole array LOCAL
+3.9  DIM a LOCAL array (on the stack) + 
+
+* String array expressions A$() = B$() + C$() are not currently supported.
++ LOCAL string arrays should be initialised to their maximum needed length
+  to eliminate the risk of a memory leak each time the PROC/FN is called:
+     LOCAL a$() : DIM a$(size%) : a$() = STRING$(max%, "a") : a$() = ""
+
+4. Miscellaneous BASIC V features
+
+4.1  Bit-shifts <<, >>, >>>
+4.2  Floating-point indirection (|)
+4.3  RETURNed parameters from FN/PROC
+4.4  Compound assignment (+=, -=, *=, /= etc.)
+4.5  Assigning to a sub-string: LEFT$()=, MID$()= , RIGHT$()=
+4.6  Hooks for CIRCLE,ELLIPSE,FILL,LINE,MOUSE,ORIGIN,RECTANGLE,TINT,SYS,WAIT
+4.7  Hooks for WIDTH function, TINT function, MODE function
+
+5. Extensions to Acorn's BASIC V, compatible with BB4W, BBCSDL and BBCTTY
+
+5.1  EXIT REPEAT / WHILE / FOR [var]
+5.2  Address-of operator ^
+5.3  Byte variables and arrays (& suffix)
+5.4  'BY len' and 'TO term' qualifiers to GET$#file
+5.5  ELSE IF <condition> THEN; (trailing semicolon)
+5.6  == synonymous with = in comparisons
+5.7  DIM a global array inside a FN/PROC (use RETURN)
+
+Note: The token for PUT has changed from &CE in version 3 to &0E in version 5.
+If this token is present in existing programs it will list as ENDWHILE rather
+than PUT, and the programs will need to be modified to restore functionality.

Source/Apps/BBCBASIC/data.z80

@@ -0,0 +1,69 @@
+	TITLE	BBC BASIC (C) R.T.RUSSELL 1981-2024
+	NAME	('DATA')
+;
+;RAM MODULE FOR BBC BASIC INTERPRETER
+;FOR USE WITH VERSION 5.0 OF BBC BASIC
+;(C) COPYRIGHT R.T.RUSSELL 1981-2024
+;
+	GLOBAL	ACCS
+	GLOBAL	BUFFER
+	GLOBAL	ONERSP
+	GLOBAL	LIBASE
+	GLOBAL	PAGE
+	GLOBAL	LOMEM
+	GLOBAL	FREE
+	GLOBAL	HIMEM
+	GLOBAL	RANDOM
+	GLOBAL	COUNT
+	GLOBAL	WIDTH
+	GLOBAL	ERL
+	GLOBAL	ERR
+	GLOBAL	ERRTRP
+	GLOBAL	ERRTXT
+	GLOBAL	TRACEN
+	GLOBAL	AUTONO
+	GLOBAL	INCREM
+	GLOBAL	LISTON
+	GLOBAL	DATPTR
+	GLOBAL	FNPTR
+	GLOBAL	PROPTR
+	GLOBAL	STAVAR
+	GLOBAL	OC
+	GLOBAL	PC
+	GLOBAL	DYNVAR
+	GLOBAL	CURLIN
+	GLOBAL	USER
+;
+;n.b. ACCS, BUFFER & STAVAR must be on page boundaries.
+;
+ACCS:	DEFS	256		;STRING ACCUMULATOR
+BUFFER:	DEFS	256		;STRING INPUT BUFFER
+STAVAR:	DEFS	27*4		;STATIC VARIABLES
+OC	EQU	STAVAR+15*4	;CODE ORIGIN (O%)
+PC	EQU	STAVAR+16*4	;PROGRAM COUNTER (P%)
+DYNVAR:	DEFS	54*2		;DYN. VARIABLE POINTERS
+FNPTR:	DEFS	2		;DYN. FUNCTION POINTER
+PROPTR:	DEFS	2		;DYN. PROCEDURE POINTER
+;
+PAGE:	DEFS	2		;START OF USER PROGRAM
+LOMEM:	DEFS	2		;START OF DYN. STORAGE
+FREE:	DEFS	2		;FIRST FREE-SPACE BYTE
+HIMEM:	DEFS	2		;FIRST BYTE ABOVE STACK
+LIBASE:	DEFS	2		;START OF FIRST LIBRARY
+;
+TRACEN:	DEFS	2		;TRACE FLAG AND NUMBER
+AUTONO:	DEFS	2		;AUTO FLAG AND NUMBER
+ERRTRP:	DEFS	2		;ON ERROR STMT POINTER \
+ONERSP:	DEFS	2		;ON ERROR LOCAL STKPTR /
+ERRTXT:	DEFS	2		;ERROR MESSAGE POINTER
+DATPTR:	DEFS	2		;DATA POINTER
+ERL:	DEFS	2		;LINE NO OF LAST ERROR
+CURLIN:	DEFS	2		;POINTER TO CURRENT LINE
+RANDOM:	DEFS	5		;RANDOM NUMBER
+COUNT:	DEFS	1		;PRINT POSITION
+WIDTH:	DEFS	1		;PRINT WIDTH
+ERR:	DEFS	1		;ERROR NUMBER
+LISTON:	DEFS	1		;LISTO & OPT FLAG
+INCREM:	DEFS	1		;AUTO INCREMENT
+;
+USER:	END

Source/Apps/BBCBASIC/dist.z80

@@ -1,7 +1,8 @@
-	TITLE	BBCDIST.Z80 (C) R.T.RUSSELL 1982
+	TITLE	BBCDIST.Z80 (C) R.T.RUSSELL 1982-2024
+	NAME	('DIST3')
 ;
-;BBC BASIC (Z80) - CP/M VERSION 2.30 & 3.00
-;(C) COPYRIGHT R.T.RUSSELL, 1982.
+;BBC BASIC (Z80) - CP/M VERSION 2.20 & 3.00
+;(C) COPYRIGHT R.T.RUSSELL, 1982-2024.
 ;ALL RIGHTS RESERVED.
 ;
 ;THIS PROGRAM ALLOWS THE USER TO ADAPT BBC BASIC TO THE
@@ -13,11 +14,14 @@
 ;PLEASE NOTE THAT A Z80 PROCESSOR AND CP/M VERSION 2.2
 ;OR LATER ARE REQUIRED.
 ;
-;R.T.RUSSELL, 11-03-1984, 03-05-1989
-;ALTERNATE REGISTERS SAVED FOR BDOS CALL, 04-06-2000
+;R.T.RUSSELL, 11-03-1984, 03-05-1989, 12-05-2024
 ;
 CPM	EQU	5
 COLD	EQU	200H
+;
+CR	EQU	0DH
+LF	EQU	0AH
+ESC	EQU	1BH
 ;
 	GLOBAL	CLRSCN
 	GLOBAL	PUTCSR
@@ -26,14 +30,18 @@ COLD	EQU	200H
 	GLOBAL	GETIME
 	GLOBAL	GETKEY
 	GLOBAL	BYE
+	GLOBAL	BEGIN
+;	GLOBAL	BDOS
 ;
-	ASEG
-	ORG	100H
+;	EXTRN	PRTDEC16
+;
+	;ASEG
+	;ORG	100H
 ;
 ;JUMP TABLE - BASIC makes calls to hardware-dependent
 ;features via this table:
 ;
-	JP	INIT
+BEGIN:	JP	INIT
 CLRSCN:	JP	CLS		;CLEAR SCREEN
 PUTCSR:	JP	PCSR		;SET CURSOR POSN.
 GETCSR:	JP	GCSR		;READ CURSOR POSN.
@@ -42,30 +50,33 @@ GETIME:	JP	GTIME		;READ ELAPSED TIME
 GETKEY:	JP	INKEY		;READ KEY (TIME LIMIT)
 BYE:	JP	REBOOT		;RETURN TO CP/M
 ;
-;THE CODE WHICH FOLLOWS IS A SKELETON VERSION SUITABLE
-;FOR ANY CP/M SYSTEM.  IT HAS BEEN CONFIGURED FOR A VT100 TO SOME DEGREE
-;BY PETER SCHORN.
+;BDOS	- Save the IX and IY registers and before performing a
+;	  CP/M function call.
+;
+BDOS:	PUSH	IX
+	PUSH	IY
+	CALL	CPM
+	POP	IY
+	POP	IX
+	RET
 ;
-
-PRSTR	EQU	9
-
 ;INIT	- Perform hardware initialisation (if any).
 ;
-INIT:	LD	A,2
-	INC	A
-	LD	DE,NOTZ80
-	JP	PE,FAIL
-	LD	C,12
-	CALL	BDOS
-	OR	A
-	LD	DE,NOTV2
-	JP	NZ,COLD
-FAIL:	LD	C,PRSTR
+INIT:	LD	HL,40H		;CPM/HBIOS MARKER LOC
+	LD	A,'W'
+	CP	(HL)
+	JR	NZ,FAIL
+	INC	HL
+	LD	A,NOT 'W'
+	CP	(HL)
+	JR	NZ,FAIL
+	JP	COLD
+FAIL:	LD	DE,NOTHB
+	LD	C,9
 	CALL	BDOS
 	RST	0
 ;
-NOTZ80:	DEFB	'Wrong processor$'
-NOTV2:	DEFB	'Wrong CP/M version$'
+NOTHB:	DEFB	'CP/M w/ HBIOS required$'
 ;
 ;REBOOT	- Switch off interrupts and return to CP/M
 ;
@@ -75,31 +86,34 @@ REBOOT:	RST	0
 ;  	  Outputs: DEHL = elapsed time (centiseconds)
 ; 	  Destroys: A,D,E,H,L,F
 ;
-GTIME:	LD	DE,0
-	LD	HL,0
-	RET
+GTIME:	JR	TICKS
 ;
 ;PTIME	- Load elapsed-time clock.
 ;   	  Inputs: DEHL = time to load (centiseconds)
 ; 	  Destroys: A,D,E,H,L,F
 ;
-PTIME:	RET
-;
-;CLS	- Clear screen for VT100.
-; 	  Destroys: A,D,E,H,L,F
-;
-CLS:	PUSH	BC		; save BC
-	LD	C,PRSTR		; command for output string
-	LD	DE,CLSSTR	; start address of string
-	CALL	BDOS		; output to terminal
-	POP	BC		; restore BC
+PTIME:
+	LD	BC,0F9D0H
+	SRL	D
+	RR	E
+	RR	H
+	RR	L
+	RST	08
+	RET
+;
+; Get OS elapsed-time clock
+;  Outputs: DEHL = time (centiseconds)
+; Destroys: A,B,C,D,E,H,L,F
+;
+TICKS:	LD	BC,0F8D0H
+	RST	08
+	SLA	L
+	RL	H
+	RL	E
+	RL	D
 	RET
-CLSSTR:	DEFB	27,'[2J$'	; VT100 string for clear screen
-
 ;
 ;INKEY	- Sample keyboard with specified wait.
-;	  This version uses a simple software timing loop.
-;	  Modify to use hardware/interrupt timer if available.
 ;   	  Inputs: HL = Time to wait (centiseconds)
 ;  	  Outputs: Carry reset indicates time-out.
 ;                  If carry set, A = character typed.
@@ -107,52 +121,64 @@ CLSSTR:	DEFB	27,'[2J$'	; VT100 string for clear screen
 ;
 INKEY:	PUSH	BC
 	PUSH	HL
+	CALL	TICKS
+	POP	DE
+	ADD	HL,DE
+WAIT:	PUSH	HL
 	LD	C,6
 	LD	E,0FFH
-	CALL	BDOS		;CONSOLE INPUT
+	CALL	BDOS
 	POP	HL
-	POP	BC
 	OR	A
 	SCF
-	RET	NZ		;KEY PRESSED
-	OR	H
-	OR	L
-	RET	Z		;TIME-OUT
-	PUSH	BC
-	LD	A,-1
-	LD	BC,1250		;DELAY CONSTANT
-WAIT:	DEC	BC
-	CP	B
-	JP	NZ,WAIT		;WAIT FOR APPROX 10ms
-	POP	BC
-	DEC	HL
-	JR	INKEY
+	JR	NZ,INKEY1
+	PUSH	HL
+	CALL	TICKS
+	POP	DE
+	SBC	HL,DE
+	EX	DE,HL
+	JR	C,WAIT	
+INKEY1:	POP	BC
+	RET
+;
+;CLS	- Clear screen.
+;	  (Customise to suit your VDU)
+; 	  Destroys: A,D,E,H,L,F
+;
+CLS:
+	LD	DE,CLSSTR
+	LD	C,9
+	JP	BDOS
+;
+CLSSTR:	DEFB	ESC,'[H',ESC,'[2J$'
 ;
 ;PCSR	- Move cursor to specified position.
 ;   	  Inputs: DE = horizontal position (LHS=0)
 ;                 HL = vertical position (TOP=0)
-; called by TAB(column, row)
+; 	  Destroys: A,D,E,H,L,F
+;
 PCSR:	LD	B,L		; vertical = line (row)
 	CALL	CONV		; normalized and convert to decimal
 	LD	(LIN),HL	; and store into string
 	LD	B,E		; horizontal = column
 	CALL	CONV		; normalized and convert to decimal
 	LD	(COL),HL	; and store into string
-	LD	C,PRSTR		; output string command
+	LD	C,9		; output string command
 	LD	DE,CURS		; start of string
-	JR	BDOS		; output string to terminal
-
+	JP	BDOS		; output string to terminal
+;
 ; VT100 sequence for cursor positioning
 CURS:	DEFB	27, '['
 LIN:	DEFW	0		; high byte, low byte for decimal line
 	DEFB	';'
 COL:	DEFW	0		; high byte, low byte for decimal column
 	DEFB	'H$'
-
+;
 ; convert binary B (0 <= B < 99, not checked) into B+1 in decimal.
 ; L = upper byte, H = lower byte. ready for LD (...), HL
 ; destroys A, B, L, H
 ; optimized for space over time
+;
 CONV:	INC	B		; normalize, home in VT100 is (1,1)
 	LD	A,'0'		; A is counter for low byte of result
 	LD	L,A		; L is counter for high byte of result
@@ -164,35 +190,7 @@ CONVLP:	INC	A		; now B times increment AL in decimal
 CONT:	DJNZ	CONVLP		; B times
 	LD	H,A		; put low byte into right place
 	RET
-
-
-;BDOS   - Save the IX and IY and alternate registers
-;         before performing a CP/M function call.
 ;
-BDOS:	PUSH	IX
-	PUSH	IY
-        EXX
-        PUSH    BC
-        PUSH    DE
-        PUSH    HL
-        EXX
-        EX      AF,AF'
-        PUSH    AF
-        EX      AF,AF'
-	CALL	CPM
-        EX      AF,AF'
-        POP     AF
-        EX      AF,AF'
-        EXX
-        POP     HL
-        POP     DE
-        POP     BC
-        EXX
-	POP	IY
-	POP	IX
-	RET
-
-
 ;GCSR	- Return cursor coordinates.
 ;   	  Outputs:  DE = X coordinate (POS)
 ;                   HL = Y coordinate (VPOS)
@@ -202,24 +200,42 @@ GCSR:	LD	DE,0
 	LD	HL,0
 	RET
 ;
-	IF	$ GT 1F4H
+;COUT - Output a character to the console
+;   Inputs: A = character
+; Destroys: A,F
+;
+COUT:	PUSH	BC
+	PUSH	DE
+	PUSH	HL
+	LD	E,A
+	LD	C,2
+	CALL	BDOS
+	POP	HL
+	POP	DE
+	POP	BC
+	RET
+;
+	;IF	$ GT 1F0H
+	IF	$-BEGIN GT 0F0H
 	ERROR	'INSUFFICIENT SPACE'
 	ENDIF
 ;
-	ORG	1F4H
+	;ORG	1F0H
+	DEFS	0F0H - ($ - BEGIN)
 ;
+OFFLO:	DEFW	0		;TIME OFFSET LO
+OFFHI:	DEFW	0		;TIME OFFSET HI
 	DEFB	80		;WIDTH
-	DEFB	'E' AND 1FH	;CURSOR UP
-	DEFB	'X' AND 1FH	;CURSOR DOWN
-	DEFB	'A' AND 1FH	;START OF LINE
-	DEFB	'F' AND 1FH	;END OF LINE
-	DEFB	'T' AND 1FH	;DELETE TO END OF LINE
-	DEFB	'H' AND 1FH	;BACKSPACE
-	DEFB	'U' AND 1FH	;CANCEL LINE
-	DEFB	'S' AND 1FH	;CURSOR LEFT
-	DEFB	'D' AND 1FH	;CURSOR RIGHT
-	DEFB	'G' AND 1FH	;DELETE CHARACTER
-	DEFB	'V' AND 1FH	;INSERT CHARACTER
+	DEFB	'G' AND 1FH	;CURSOR UP
+	DEFB	'O' AND 1FH	;CURSOR DOWN
+	DEFB	'F' AND 1FH	;START OF LINE
+	DEFB	'N' AND 1FH	;END OF LINE
+	DEFB	'X' AND 1FH	;DELETE TO END OF LINE
+	DEFB	08H		;BACKSPACE & DELETE
+	DEFB	'U' AND 1FH	;DEL TO START OF LINE
+	DEFB	'J' AND 1FH	;CURSOR LEFT
+	DEFB	'L' AND 1FH	;CURSOR RIGHT
+	DEFB	'R' AND 1FH	;DELETE CHARACTER
+	DEFB	'Q' AND 1FH	;INS/OVR TOGGLE
 ;
 FIN:	END
-

Source/Apps/BBCBASIC/hook.z80

@@ -0,0 +1,64 @@
+	NAME	('HOOK')
+;
+	GLOBAL	CLG
+	GLOBAL	COLOUR
+	GLOBAL	DRAW
+	GLOBAL	ENVEL
+	GLOBAL	GCOL
+	GLOBAL	MODE
+	GLOBAL	MOVE
+	GLOBAL	PLOT
+	GLOBAL	SOUND
+	GLOBAL	PUTIMS
+	GLOBAL	CIRCLE
+	GLOBAL	ELLIPSE
+	GLOBAL	FILL
+	GLOBAL	MOUSE
+	GLOBAL	ORIGIN
+	GLOBAL	RECTAN
+	GLOBAL	LINE
+	GLOBAL	TINT
+	GLOBAL	WAIT
+	GLOBAL	SYS
+;
+	GLOBAL	ADVAL
+	GLOBAL	POINT
+	GLOBAL	GETIMS
+	GLOBAL	TINTFN
+	GLOBAL	MODEFN
+	GLOBAL	WIDFN
+;
+	EXTRN	EXTERR
+;
+CLG:
+COLOUR:
+DRAW:
+ENVEL:
+GCOL:
+MODE:
+MOVE:
+PLOT:
+SOUND:
+ADVAL:
+POINT:
+GETIMS:
+PUTIMS:
+CIRCLE:
+ELLIPSE:
+FILL:
+MOUSE:
+ORIGIN:
+RECTAN:
+LINE:
+TINT:
+TINTFN:
+MODEFN:
+WIDFN:
+WAIT:
+SYS:
+	XOR	A
+	CALL	EXTERR
+	DEFM	'Sorry'
+	DEFB	0
+;
+	END

Source/Apps/Build.cmd

@@ -30,6 +30,7 @@ pushd VGM && call Build || exit /b & popd
 pushd cpuspd && call Build || exit /b & popd
 pushd Survey && call Build || exit /b & popd
 pushd HTalk && call Build || exit /b & popd
+pushd BBCBASIC && call Build || exit /b & popd
 
 copy *.com %APPBIN%\ || exit /b
 

Source/Apps/Clean.cmd

@@ -19,3 +19,4 @@ pushd VGM && call Clean || exit /b 1 & popd
 pushd cpuspd && call Clean || exit /b 1 & popd
 pushd Survey && call Clean || exit /b 1 & popd
 pushd HTalk && call Clean || exit /b 1 & popd
+pushd BBCBASIC && call Clean || exit /b 1 & popd

Source/Apps/Makefile

@@ -1,6 +1,6 @@
 OBJECTS = sysgen.com syscopy.com assign.com format.com talk.com \
 	mode.com rtc.com timer.com rtchb.com
-SUBDIRS = HTalk XM FDU FAT Tune Test ZMP ZMD Dev VGM cpuspd Survey
+SUBDIRS = HTalk XM FDU FAT Tune Test ZMP ZMD Dev VGM cpuspd Survey BBCBASIC
 DEST = ../../Binary/Apps
 TOOLS =../../Tools
 

Source/Apps/Test/inttest/Build.cmd

@@ -8,4 +8,5 @@ set TASMTABS=%TOOLS%\tasm32
 tasm -t180 -g3 -fFF inttest.asm inttest.com inttest.lst || exit /b
 
 copy /Y inttest.com ..\..\..\..\Binary\Apps\Test\ || exit /b
+copy /Y inttest.doc ..\..\..\..\Binary\Apps\Test\ || exit /b
 

Source/Apps/Test/inttest/Makefile

@@ -1,5 +1,7 @@
 OBJECTS = inttest.com
+DOCS = inttest.doc
 DEST = ../../../../Binary/Apps/Test
+DOCDEST = ../../../../Binary/Apps/Test
 TOOLS =../../../../Tools
 
 USETASM=1

Source/Apps/Test/inttest/inttest.asm

@@ -176,6 +176,8 @@ estidx:
 	jr	z,hkim
 	cp	2
 	jr	z,hkim
+	cp	3
+	jr	z,hkim
 	ret
 ;
 ; Setup interrupt handler
@@ -545,8 +547,8 @@ stack	.equ	$		; stack top
 ;
 ; Messages
 ;
-msgban	.db	"INTTEST v1.2, 15-May-2019",13,10
-	.db	"Copyright (C) 2019, Wayne Warthen, GNU GPL v3",0
+msgban	.db	"INTTEST v1.3, 16-May-2024",13,10
+	.db	"Copyright (C) 2024, Wayne Warthen, GNU GPL v3",0
 msginfo	.db	"Interrupt information request...",0
 msgmode	.db	"  Active interrupt mode: ",0
 msgcnt	.db	"  Vector entries in use: ",0

Source/Apps/Test/inttest/inttest.doc

@@ -0,0 +1,44 @@
+INTTEST
+=======
+
+RomWBW includes an API allowing applications to "hook" interrupts.
+The `INTTEST` utility allows you to test this functionality.
+
+
+** Syntax **
+
+`INTTEST`
+
+
+** Usage **
+
+`INTTEST` is an interactive application.  At startup, it will display
+a list of the interrupt vector slots in your system along with the
+current vector address for each of them.
+
+It then prompts you to enter the slot number (in hex) of a vector to
+hook.  After entering this, the application will watch the hooked
+vector and countdown from 0xFF to 0x00 as interrupts are noted.
+
+When the counter reaches 0x00, the interrupt is unhooked and the
+application terminates.  The application can also be terminated by
+pressing <esc>.
+
+
+** Notes **
+
+If your system is running without interrupts active, the application
+will terminate immediately.
+
+All slots have vectors even if the corresponding interrupt is not
+doing anything.  In this case, the vector is pointing to the "bad
+interrupt" handler.
+
+If you hook a vector that is not receiving any interrupts, the
+down-counter will not do anything.
+
+
+** Etymology* *
+
+The `INTTEST` command is an original product and the source code is
+provided in the RomWBW distribution.

Source/Apps/Test/ps2info/ps2info.asm

@@ -11,6 +11,7 @@
 ; WBW 2022-04-01: Add menu for test functions
 ; WBW 2022-04-02: Fix prtchr register saving/recovery
 ; WBW 2023-10-19: Add support for Duodyne
+; WBW 2024-06-10: Add support for RC2014
 ;
 ;=======================================================================
 ;
@@ -25,6 +26,10 @@ iodat_rph	.equ	$8C	; PS/2 controller data port address
 ; Duodyne:
 iocmd_duo	.equ	$4D	; PS/2 controller command port address
 iodat_duo	.equ	$4C	; PS/2 controller data port address
+; RC2014 (EP/Sally)
+iocmd_rc	.equ	$64	; PS/2 controller command port address
+iodat_rc	.equ	$60	; PS/2 controller data port address
+
 ;
 cpumhz	.equ	8	; for time delay calculations (not critical)
 ;
@@ -87,6 +92,8 @@ setup1:
 	jr	z,setup_rph
 	cp	'3'			; Duodyne
 	jr	z,setup_duo
+	cp	'4'			; RC2014 EP/Sally
+	jr	z,setup_rc
 	cp	'X'
 	jr	z,exit
 	jr	setup
@@ -115,6 +122,14 @@ setup_duo:
 	ld	de,str_duo
 	jr	setup2
 ;
+setup_rc:
+	ld	a,iocmd_rc
+	ld	(iocmd),a
+	ld	a,iodat_rc
+	ld	(iodat),a
+	ld	de,str_rc
+	jr	setup2
+;
 setup2:
 	call	prtstr
 	call	crlf2
@@ -1437,16 +1452,18 @@ delay1:
 ; Constants
 ;=======================================================================
 ;
-str_banner		.db	"PS/2 Keyboard/Mouse Information v0.8, 6-Nov-2023",0
+str_banner		.db	"PS/2 Keyboard/Mouse Information v0.9, 10-Jun-2024",0
 str_hwmenu		.db	"PS/2 Controller Port Options:\r\n\r\n"
 			.db	"  1 - Nhyodyne\r\n"
 			.db	"  2 - Rhyophyre\r\n"
 			.db	"  3 - Duodyne\r\n"
+			.db	"  4 - RC2014\r\n"
 			.db	"  X - Exit Application\r\n"
 			.db	"\r\nSelection? ",0
 str_mbc			.db	"Nhyodyne",0
 str_rph			.db	"Rhyophyre",0
 str_duo			.db	"Duodyne",0
+str_rc			.db	"RC2014 (Saly)",0
 str_menu		.db	"PS/2 Testing Options:\r\n\r\n"
 			.db	"  C - Test PS/2 Controller\r\n"
 			.db	"  K - Test PS/2 Keyboard\r\n"

Source/Apps/timer.asm

@@ -1,9 +1,10 @@
 ;===============================================================================
 ; TIMER - Display system timer value
-;
+; Version 1.21 30-June-2024
 ;===============================================================================
 ;
 ;	Author:  Wayne Warthen (wwarthen@gmail.com)
+;	Updated: MartinR (June 2024)
 ;_______________________________________________________________________________
 ;
 ; Usage:
@@ -14,38 +15,58 @@
 ;
 ; Operation:
 ;   Reads and displays system timer value.
+;
+; This code will only execute on a Z80 CPU (or derivitive)
+;
+; This source code assembles with TASM V3.2 under Windows-11 using the
+; following command line:
+;	tasm -80 -g3 -l TIMER.ASM TIMER.COM
+;	ie: Z80 CPU; output format 'binary' named .COM (rather than .OBJ)
+;	and includes a symbol table as part of the listing file.
 ;_______________________________________________________________________________
 ;
 ; Change Log:
 ;   2018-01-14 [WBW] Initial release
 ;   2018-01-17 [WBW] Add HBIOS check
 ;   2019-11-08 [WBW] Add seconds support
+;   2024-06-30 [MR ] Display values in decimal rather than hexadecimal
+;_______________________________________________________________________________
+;
+; Includes binary-to-decimal subroutine by Alwin Henseler
+; Located at: https://www.msx.org/forum/development/msx-development/32-bit-long-ascii
 ;_______________________________________________________________________________
 ;
 ; ToDo:
+;	Display the elapsed time in HH:MM:SS
 ;_______________________________________________________________________________
 ;
-#include "../ver.inc"
+#include "../ver.inc"		; Used for building RomWBW
+;#include "ver.inc"		; Used for testing purposes during code development
 ;
 ;===============================================================================
 ; Definitions
 ;===============================================================================
 ;
-stksiz	.equ	$40		; Working stack size
-;
-restart	.equ	$0000		; CP/M restart vector
-bdos	.equ	$0005		; BDOS invocation vector
-;
-ident	.equ	$FFFE		; loc of RomWBW HBIOS ident ptr
+stksiz		.equ	$80	; Working stack size (was $40)
+;		                
+restart		.equ	$0000	; CP/M restart vector
+bdos		.equ	$0005	; BDOS invocation vector
+;		                
+ident		.equ	$FFFE	; loc of RomWBW HBIOS ident ptr
 ;
 bf_sysver	.equ	$F1	; BIOS: VER function
 bf_sysget	.equ	$F8	; HBIOS: SYSGET function
-bf_sysset	.equ	$F9	; HBIOS: SYSGET function
+bf_sysset	.equ	$F9	; HBIOS: SYSSET function
 bf_sysgettimer	.equ	$D0	; TIMER subfunction
 bf_syssettimer	.equ	$D0	; TIMER subfunction
 bf_sysgetsecs	.equ	$D1	; SECONDS subfunction
 bf_syssetsecs	.equ	$D1	; SECONDS subfunction
 ;
+; ASCII Control Characters
+;
+lf		.equ 	$0A	; Line Feed
+cr		.equ 	$0D	; Carriage Return
+;
 ;===============================================================================
 ; Code Section
 ;===============================================================================
@@ -73,17 +94,17 @@ exit:	; clean up and return to command processor
 ; Initialization
 ;
 init:
-	call	crlf		; formatting
-	ld	de,msgban	; point to version message part 1
-	call	prtstr		; print it
-;
-	call	idbio		; identify active BIOS
-	cp	1		; check for HBIOS
-	jp	nz,errbio	; handle BIOS error
-;
+	call	crlf			; formatting
+	ld	de,msgban		; point to version message part 1
+	call	prtstr			; print it
+;	
+	call	idbio			; identify active BIOS
+	cp	1			; check for HBIOS
+	jp	nz,errbio		; handle BIOS error
+;	
 	ld	a,rmj << 4 | rmn	; expected HBIOS ver
-	cp	d		; compare with result above
-	jp	nz,errbio	; handle BIOS error
+	cp	d			; compare with result above
+	jp	nz,errbio		; handle BIOS error
 ;
 initx
 	; initialization complete
@@ -120,9 +141,9 @@ process0:
 	call	crlf2		; formatting
 ;
 process1:
-	ld	b,bf_sysget	; HBIOS SYSGET function
+	ld	b,bf_sysget		; HBIOS SYSGET function
 	ld	c,bf_sysgettimer	; TIMER subfunction
-	rst	08		; call HBIOS, DE:HL := timer value
+	rst	08			; call HBIOS, DE:HL := timer value
 	
 	ld	a,(first)
 	or	a
@@ -135,28 +156,50 @@ process1:
 	cp	l		; compare to current LSB
 	jr	z,process2	; if equal, bypass display
 
-process1a:	
+;*******************************************************************************
+	
+; Code added/amended to print values in decimal
+; MartinR June2024	
+
+process1a:
 	; save and print new value
-	ld	a,l		; new LSB value to A
-	ld	(last),a	; save as last value
-	call	prtcr		; back to start of line
-	;call	nz,prthex32	; display it
-	call	prthex32	; display it
-	ld	de,strtick	; tag
-	call	prtstr		; display it
+	ld	a,l			; new LSB value to A
+	ld	(last),a		; save as last value
+	call	prtcr			; back to start of line
+	
+	call	b2d32			; Convert DE:HL into ASCII; Start of ASCII buffer returned in HL
+	ex	de,hl
+	call	prtstr			; Display the value
+	
+	ld	de,strtick		; "Ticks" message 
+	call	prtstr			; Display it
 
 	; get and print seconds value
-	ld	b,bf_sysget	; HBIOS SYSGET function
-	ld	c,bf_sysgetsecs	; SECONDS subfunction
-	rst	08		; call HBIOS, DE:HL := seconds value
-	call	prthex32	; display it
-	ld	a,'.'		; fraction separator
-	call	prtchr		; print it
-	ld	a,c		; get fractional component
-	call	prthex		; print it
-	ld	de,strsec	; tag
-	call	prtstr		; display it
-;
+	ld	b,bf_sysget		; HBIOS SYSGET function
+	ld	c,bf_sysgetsecs		; SECONDS subfunction
+	rst	08			; Call HBIOS; DE:HL := seconds value; C := fractional part
+	push	bc			; Preserve the fractional part on the stack
+
+	call	b2d32			; Convert DE:HL into ASCII; Start of ASCII buffer returned in HL
+	ex	de,hl
+	call	prtstr			; Display the value
+
+	ld	a,'.'			; Fraction separator, ie decimal point
+	call	prtchr			; Print it
+
+	pop	bc			; Retrieve fractional part into A
+	ld	a,c
+	sla	a			; Double the 50Hz 'ticks' value to give 1/100s of a second
+
+	call	b2d8			; Convert into ASCII - up to 3 digits
+	ex	de,hl			; Start of ASCII buffer returned in HL
+	call	prtstr			; Display fractional part of the value
+	
+	ld	de,strsec		; "Seconds" message
+	call	prtstr			; Display it
+
+;*******************************************************************************
+		
 process2:
 	ld	a,(cont)	; continuous display?
 	or	a		; test for true/false
@@ -269,9 +312,9 @@ prtdot:
 ;
 prtcr:
 ;
-	; shortcut to print a dot preserving all regs
+	; shortcut to print carriage return preserving all regs
 	push	af		; save af
-	ld	a,13		; load CR value
+	ld	a,cr		; load CR value
 	call	prtchr		; print it
 	pop	af		; restore af
 	ret			; done
@@ -477,6 +520,124 @@ err2:	; without the string
 	or	$FF		; signal error
 	ret			; done
 ;
+;
+;===============================================================================
+; Subroutine to print decimal numbers
+;===============================================================================
+;
+; Combined routine for conversion of different sized binary numbers into
+; directly printable ASCII(Z)-string
+; Input value in registers, number size and -related to that- registers to fill
+; is selected by calling the correct entry:
+;
+;   entry        input    decimal value 0 to:
+;   b2d8             A                    255  (3 digits)
+;   b2d16           HL                  65535   5   "
+;   b2d24         E:HL               16777215   8   "
+;   b2d32        DE:HL             4294967295  10   "
+;   b2d48     BC:DE:HL        281474976710655  15   "
+;   b2d64  IX:BC:DE:HL   18446744073709551615  20   "
+;
+; The resulting string is placed into a small buffer attached to this routine,
+; this buffer needs no initialization and can be modified as desired.
+; The number is aligned to the right, and leading 0's are replaced with spaces.
+; On exit HL points to the first digit, (B)C = number of decimals
+; This way any re-alignment / postprocessing is made easy.
+; Changes: AF,BC,DE,HL,IX
+;
+; by Alwin Henseler
+; https://msx.org/forum/topic/who-who/dutch-hardware-guy-pops-back-sort
+;
+; Found at:
+; https://www.msx.org/forum/development/msx-development/32-bit-long-ascii
+;
+; Tweaked to assemble using TASM 3.2 by MartinR 23June2024
+;
+b2d8:	ld	h,0
+	ld	l,a
+b2d16:	ld	e,0
+b2d24:	ld	d,0
+b2d32:	ld	bc,0
+b2d48:	ld	ix,0		; zero all non-used bits
+b2d64:	ld	(b2dinv),hl
+	ld	(b2dinv+2),de
+	ld	(b2dinv+4),bc
+	ld	(b2dinv+6),ix	; place full 64-bit input value in buffer
+	ld	hl,b2dbuf
+	ld	de,b2dbuf+1
+	ld	(hl),' '
+b2dfilc:.equ	$-1		; address of fill-character
+	ld	bc,18
+	ldir			; fill 1st 19 bytes of buffer with spaces
+	ld	(b2dend-1),bc	; set BCD value to "0" & place terminating 0
+	ld	e,1		; no. of bytes in BCD value
+	ld	hl,b2dinv+8	; (address MSB input)+1
+	ld	bc,$0909
+	xor	a
+b2dskp0:dec	b
+	jr	z,b2dsiz	; all 0: continue with postprocessing
+	dec	hl
+	or	(hl)		; find first byte <> 0
+	jr	z,b2dskp0
+b2dfnd1:dec	c
+	rla
+	jr	nc,b2dfnd1	; determine no. of most significant 1-bit
+	rra
+	ld	d,a		; byte from binary input value
+b2dlus2:push	hl
+	push	bc
+b2dlus1:ld	hl,b2dend-1	; address LSB of bcd value
+	ld	b,e		; current length of BCD value in bytes
+	rl	d		; highest bit from input value -> carry
+b2dlus0:ld	a,(hl)
+	adc	a,a
+	daa
+	ld	(hl),a		; double 1 BCD byte from intermediate result
+	dec	hl
+	djnz	b2dlus0		; and go on to double entire BCD value (+carry!)
+	jr	nc,b2dnxt
+	inc	e		; carry at MSB -> BCD value grew 1 byte larger
+	ld	(hl),1		; initialize new MSB of BCD value
+b2dnxt:	dec	c
+	jr	nz,b2dlus1	; repeat for remaining bits from 1 input byte
+	pop	bc		; no. of remaining bytes in input value
+	ld	c,8		; reset bit-counter
+	pop	hl		; pointer to byte from input value
+	dec	hl
+	ld	d,(hl)		; get next group of 8 bits
+	djnz	b2dlus2		; and repeat until last byte from input value
+b2dsiz:	ld	hl,b2dend	; address of terminating 0
+	ld	c,e		; size of bcd value in bytes
+	or	a
+	sbc	hl,bc		; calculate address of MSB BCD
+	ld	d,h
+	ld	e,l
+	sbc	hl,bc
+	ex	de,hl		; HL=address BCD value, de=start of decimal value
+	ld	b,c		; no. of bytes BCD
+	sla	c		; no. of bytes decimal (possibly 1 too high)
+	ld	a,'0'
+	rld			; shift bits 4-7 of (HL) into bit 0-3 of A
+	cp	'0'		; (HL) was > 9h?
+	jr	nz,b2dexph	; if yes, start with recording high digit
+	dec	c		; correct number of decimals
+	inc	de		; correct start address
+	jr	b2dexpl		; continue with converting low digit
+b2dexp:	rld			; shift high digit (HL) into low digit of a
+b2dexph:ld	(de),a		; record resulting ascii-code
+	inc	de
+b2dexpl:rld
+	ld	(de),a
+	inc	de
+	inc	hl		; next BCD-byte
+	djnz	b2dexp		; and go on to convert each BCD-byte into 2 ASCII
+	sbc	hl,bc		; return with HL pointing to 1st decimal
+	ret
+
+b2dinv	.fill	8		; space for 64-bit input value (LSB first)
+b2dbuf	.fill	20		; space for 20 decimal digits
+b2dend	.db	0		; space for terminating character
+;
 ;===============================================================================
 ; Storage Section
 ;===============================================================================
@@ -487,20 +648,21 @@ first	.db	$FF		; first pass flag (true at start)
 ;
 stksav	.dw	0		; stack pointer saved at start
 	.fill	stksiz,0	; stack
-stack	.equ	$		; stack top
+stack	.equ $			; new stack top
 ;
 ; Messages
 ;
-msgban	.db	"TIMER v1.1, 10-Nov-2019",13,10
-	.db	"Copyright (C) 2019, Wayne Warthen, GNU GPL v3",0
-msguse	.db	"Usage: TIMER [/C] [/?]",13,10
-	.db	"  ex. TIMER           (display current timer value)",13,10
-	.db	"      TIMER /?        (display version and usage)",13,10
+msgban	.db	"TIMER v1.21, 30-Jun-2024",cr,lf
+	.db	"Copyright (C) 2019, Wayne Warthen, GNU GPL v3",cr,lf
+	.db	"Updated by MartinR 2024",0
+msguse	.db	"Usage: TIMER [/C] [/?]",cr,lf
+	.db	"  ex. TIMER           (display current timer value)",cr,lf
+	.db	"      TIMER /?        (display version and usage)",cr,lf
 	.db	"      TIMER /C        (display timer value continuously)",0
 msgprm	.db	"Parameter error (TIMER /? for usage)",0
 msgbio	.db	"Incompatible BIOS or version, "
 	.db	"HBIOS v", '0' + rmj, ".", '0' + rmn, " required",0
-strtick	.db	" Ticks, ",0
-strsec	.db	" Seconds",0
+strtick	.db	" Ticks     ",0
+strsec	.db	" Seconds  ",0
 ;
-	.end
+		.end

Source/Build.cmd

@@ -11,6 +11,7 @@ call BuildZRC || exit /b
 call BuildZ1RCC || exit /b
 call BuildZZRCC || exit /b
 call BuildZRC512 || exit /b
+call BuildFZ80 || exit /b
 
 if "%1" == "dist" (
   call Clean || exit /b

Source/BuildFZ80.cmd

@@ -0,0 +1,4 @@
+@echo off
+setlocal
+
+pushd FZ80 && call Build || exit /b & popd

Source/CBIOS/cbios.asm

@@ -2747,10 +2747,12 @@ CLRRAM2:
 #ENDIF
 	LD	A,(BNKUSER)		; SWITCH BACK TO USER BANK
 	CALL	HB_BNKSEL		; SELECT BANK
+	EI				; INTERRUPTS OK AGAIN
 	CALL	NEWLINE2		; FORMATTING
 	LD	DE,STR_INITRAMDISK	; RAM DISK INIT MESSAGE
 	CALL	WRITESTR		; DISPLAY IT
-	LD	A,(BNKRAMD)		; SWITCH BACK TO FIRST BANK
+	DI				; DISABLE INTERRUPTS AGAIN
+	LD	A,(BNKRAMD)		; SWITCH BACK TO FIRST RAM BANK
 	CALL	HB_BNKSEL		; SELECT BANK
 	LD	HL,0			; SOURCE ADR FOR FILL
 	LD	BC,$2000		; LENGTH OF FILL IS 8K

Source/Doc/Basic.h

@@ -1,6 +1,7 @@
 $define{doc_ver}{Version 3.5}$
 $define{doc_product}{RomWBW}$
-$define{doc_root}{https://github.com/wwarthen/RomWBW/raw/dev/Doc}$
+$define{file_root}{https://github.com/wwarthen/RomWBW/raw/master}$
+$define{doc_root}{$file_root$/Doc}$
 $ifndef{doc_title}$ $define{doc_title}{Document Title}$ $endif$
 $ifndef{doc_author}$ $define{doc_author}{Wayne Warthen}$ $endif$
 $define{doc_date}{$date{%d %b %Y}$}$
@@ -10,7 +11,6 @@ $define{doc_orgurl}{www.retrobrewcomputers.org}$
 $define{doc_user}{[RomWBW User Guide]($doc_root$/RomWBW User Guide.pdf)}$
 $define{doc_sys}{[RomWBW System Guide]($doc_root$/RomWBW System Guide.pdf)}$
 $define{doc_apps}{[RomWBW Applications]($doc_root$/RomWBW Applications.pdf)}$
-$define{doc_romapps}{[RomWBW ROM Applications]($doc_root$/RomWBW ROM Applications.pdf)}$
 $define{doc_catalog}{[RomWBW Disk Catalog]($doc_root$/RomWBW Disk Catalog.pdf)}$
 $define{doc_errata}{[RomWBW Errata]($doc_root$/RomWBW Errata.pdf)}$
 

Source/Doc/Build.cmd

@@ -15,7 +15,6 @@ call :GenDoc ReadMe
 call :GenDoc UserGuide
 call :GenDoc SystemGuide
 call :GenDoc Applications
-call :GenDoc ROM_Applications
 call :GenDoc Catalog
 call :GenDoc Errata
 
@@ -24,7 +23,6 @@ if exist ReadMe.txt copy ReadMe.txt ..\..\ReadMe.txt || exit /b
 if exist UserGuide.pdf copy UserGuide.pdf "..\..\Doc\RomWBW User Guide.pdf" || exit /b
 if exist SystemGuide.pdf copy SystemGuide.pdf "..\..\Doc\RomWBW System Guide.pdf" || exit /b
 if exist Applications.pdf copy Applications.pdf "..\..\Doc\RomWBW Applications.pdf" || exit /b
-if exist ROM_Applications.pdf copy ROM_Applications.pdf "..\..\Doc\RomWBW ROM Applications.pdf" || exit /b
 if exist Catalog.pdf copy Catalog.pdf "..\..\Doc\RomWBW Disk Catalog.pdf" || exit /b
 if exist Errata.pdf copy Errata.pdf "..\..\Doc\RomWBW Errata.pdf" || exit /b
 

Source/Doc/Makefile

@@ -3,7 +3,7 @@
 # and available on commandline for this build to work!!!
 # Typically "sudo apt install gpp pandoc texlive-latex-extra texlive-luatex texlive-fonts-extra fonts-roboto"
 #
-OBJECTS = ReadMe.gfm ReadMe.txt UserGuide.pdf SystemGuide.pdf Applications.pdf ROM_Applications.pdf Catalog.pdf Errata.pdf
+OBJECTS = ReadMe.gfm ReadMe.txt UserGuide.pdf SystemGuide.pdf Applications.pdf Catalog.pdf Errata.pdf
 # DEST = ../../Doc
 TOOLS = ../../Tools
 OTHERS = *.tmp
@@ -36,6 +36,5 @@ deploy :
 	cp UserGuide.pdf         "../../Doc/RomWBW User Guide.pdf"
 	cp SystemGuide.pdf       "../../Doc/RomWBW System Guide.pdf"
 	cp Applications.pdf      "../../Doc/RomWBW Applications.pdf"
-	cp ROM_Applications.pdf  "../../Doc/RomWBW ROM Applications.pdf"
 	cp Catalog.pdf           "../../Doc/RomWBW Disk Catalog.pdf"
 	cp Errata.pdf             "../../Doc/RomWBW Errata.pdf"

Source/Doc/ROM_Applications.md

@@ -1,635 +0,0 @@
-$define{doc_title}{ROM Applications}$
-$define{doc_author}{Phillip Summers}$
-$define{doc_authmail}{}$
-$include{"Book.h"}$
-
-# Summary
-
-RomWBW includes a small selection of built in utilities and
-programming languages.
-
-`\clearpage`{=latex}
-
-# RomWBW Monitor
-
-The Monitor program is a low level utility that can be used 
-for testing and programming. It allows programs to be entered,
-memory to be examined, and input/output devices to be read or
-written to.
-
-It's key advantage is that is available at boot up. 
-
-Its key disadvantages are that code cannot be entered in assembly 
-language and there is no ability to save to memory devices.
-
-The available memory area for programming is `0200-EDFFh`.
-The following areas are reserved:
-
-Memory Area | Function
-------------|-----------------------------------
-`0000-00FFh`| Jump and restart (RST) vectors
-`0100-01FFh`| HBIOS configuration block
-`EE00-FDFFh`| MONITOR
-`FE00-FFFFh`| HBIOS proxy
-
-Commands can be entered at the command prompt `>` 
-Automatic case conversion takes place on command entry and all 
-arguments are expected to be in hex format.
-
-The current memory bank in low memory is displayed before the prompt i.e.:
-
-`8E>`
-
-The Monitor allows access to all memory locations but ROM and
-Flash memory cannot be written to. Memory outside the normal
-address range can be accessed using the B command. The first
-256 bytes `0000-01FF` is critical for the HBIOS operation.
-Changing banks may make this information inaccessible.
-
-Refer to the RomWBW Architecture manual for details memory banking.
-
-A quick guide to using the Monitor program follows:
-
-## ? - Displays a summary of available commands.
-
-```
-Monitor Commands (all values in hex):
-B                    - Boot system
-D xxxx [yyyy]        - Dump memory from xxxx to yyyy
-F xxxx yyyy zz       - Fill memory from xxxx to yyyy with zz
-H                    - Halt system
-I xxxx               - Input from port xxxx
-K                    - Keyboard echo
-L                    - Load Intel hex data
-M xxxx yyyy zzzz     - Move memory block xxxx-yyyy to zzzz
-O xxxx yy            - Output value yy to port xxxx
-P xxxx               - Program RAM at address xxxx
-R xxxx [[yy] [zzzz]] - Run code at address xxxx
-                       Pass yy and zzzz to register A and BC
-T xxxx	             - X-modem transfer to memory location xxxx
-S xx                 - Set bank to xx
-X                    - Exit monitor
-```
-
-## Cold Boot
-
-B - Performs a cold boot of the ROMWBW system. A complete
-re-initialization of the system is performed and the system
-returns to the Boot Loader prompt.
-
-## Dump Memory
-
-D xxxx [yyyy] - Dump memory from hex location xxxx to yyyy
-on the screen as lines of 16 hexadecimal bytes with their
-ASCII equivalents (if within a set range, else a '.' is
-printed). If the end address is omitted then 256 bytes is
-displayed. 
-
-A good tool to see where code is located, check
-for version id, obtain details for chip configurations and
-execution paths.
-
-Examples: `D 100 1FF`
-
-```
-0100: 10 0B 01 5A 33 45 4E 56 01 00 00 2A 06 00 F9 11  ...Z3ENV...*..ù.
-0110: DE 38 37 ED 52 4D 44 0B 6B 62 13 36 00 ED B0 21  Þ87íRMD.kb.6.í°!
-0120: 7D 32 E5 21 80 00 4E 23 06 00 09 36 00 21 81 00  }2å!..N#...6.!..
-0130: E5 CD 6C 1F C1 C1 E5 2A C9 8C E5 CD 45 05 E5 CD  åÍl.ÁÁå*É.åÍE.åÍ
-0140: 59 1F C3 00 00 C3 AE 01 C3 51 04 C3 4C 02 C3 57  Y.Ã..î.ÃQ.ÃL.ÃW
-0150: 02 C3 64 02 C3 75 02 C3 88 02 C3 B2 03 C3 0D 04  .Ãd.Ãu.Ã..ò.Ã..
-0160: C3 19 04 C3 22 04 C3 2A 04 C3 35 04 C3 40 04 C3  Ã..Ã".Ã*.Ã5.Ã@.Ã
-0170: 48 04 C3 50 04 C3 50 04 C3 50 04 C3 8F 02 C3 93  H.ÃP.ÃP.ÃP.Ã..Ã.
-0180: 02 C3 94 02 C3 95 02 C3 85 04 C3 C7 04 C3 D1 01  .Ã..Ã..Ã..ÃÇ.ÃÑ.
-0190: C3 48 02 C3 E7 04 C3 56 03 C3 D0 01 C3 D0 01 C3  ÃH.Ãç.ÃV.ÃÐ.ÃÐ.Ã
-01A0: D0 01 C3 D0 01 C3 D0 01 C3 D0 01 01 02 01 CD 6B  Ð.ÃÐ.ÃÐ.ÃÐ....Ík
-01B0: 04 54 68 69 73 20 66 75 6E 63 74 69 6F 6E 20 6E  .This function n
-01C0: 6F 74 20 73 75 70 70 6F 72 74 65 64 2E 0D 0A 00  ot supported....
-01D0: C9 3E FF 32 3C 00 3A 5D 00 FE 20 28 14 D6 30 32  É>ÿ2<.:].þ (.Ö02
-01E0: AB 01 32 AD 01 3A 5E 00 FE 20 28 05 D6 30 32 AC  «.2­.:^.þ (.Ö02¬
-01F0: 01 C5 01 F0 F8 CF E5 26 00 0E 0A CD 39 02 7D 3C  .Å.ðøÏå&...Í9.}<
-```
-
-## Fill Memory
-
-F xxxx yyyy zz - Fill memory from hex xxxx to yyyy with
-a single value of zz over the full range. The Dump command
-can be used to confirm that the fill completed as expected. A
-good way to zero out memory areas before writing machine data
-for debug purposes.
-
-## Halt System
-
-H - Halt system. A Z80 HALT instruction is executed. The
-system remains in the halt state until the system is
-physically rebooted. Interrupts will not restart the
-system. On systems that support a HALT status LED, the
-LED will be illuminated.
-
-## Input from port
-
-I xxxx - Input data from port xxxx and display to the screen.
-This command is used to read values from hardware I/O ports
-and display the contents in hexadecimal. 
-
-## Keyboard Echo
-
-K - Echo any key-presses from the terminal. Press 'ESC' key
-to quit. This facility provides that any key stroke sent to
-the computer will be echoed back to the terminal. File down
-loads will be echoed as well while this facility is ‘on’.
-
-## Load Hex format file into memory
-
-L - Load a Intel Hex format file via the terminal program.
-The load address is defined in the hex file of the
-assembled code.
-
-The terminal emulator program should be configured to
-give a delay at the end of each line to allow the monitor
-enough time to parse the line and move the data to memory.
-
-Keep in mind that this will be a transient unless the
-system support battery backed memory. Saving to memory drive 
-is not supported.
-
-## Move memory
-
-M xxxx yyyy zzzz - Move hex memory block xxxx to yyyy to
-memory starting at hex location zzzz. Care should be taken
-to insure that there is enough memory at the destination so
-that code does not get over-written or memory wrapped around.
-
-## Output to port
-
-O xxxx yy - Output data byte xx to port xxxx. This command is
-used to send hexadecimal values to hardware I/O ports to
-verify their operation and is the companion to the I operation.
-Use clip leaded LEDs to confirm the data written.
-
-## Program memory location
-
-P xxxx - Program memory location xxxx. This routine will
-allow you to program a hexadecimal value 'into memory starting
-at location xxxx. Press 'Enter' on a blank line to
-return to the Monitor prompt.
-
-The limitation around programming memory is that it must be 
-entered in hexadecimal. An alternative is to use the L command
-to load a program that has been assembled to a hex file on the
-remote computer.
-
-An excellent online resource for looking up opcodes for entry
-can be found here: [https://clrhome.org/table](https://clrhome.org/table)
-
-## Run program
-
-R xxxx [[yy] [zzzz]] - Run program at location xxxx. If optional
-arguments yy and zzzz are entered they are loaded into the
-A and BC register respectively. The return address of the
-Monitor is saved on the stack so the program can return
-to the monitor. On return to the monitor, the contents of
-the A, HL, DE and BC registers are displayed.
-
-## Set bank
-
-S xx - Change the bank in memory to xx. Memory addresses
-0000-7FFF (i.e. bottom 32k) are affected. Because the
-interrupt vectors are stored in the bottom page of this
-range, this function is disable when interrupt mode 1 is
-being used (IM1). Interrupt mode 2 is not affected as the
-associated jump vectors are stored in high memory. 
-
-Changing the bank also impacts the restart vectors (RST),
-so executing code that call the HBIOS using the RST 08
-assembly code will not work.
-
-The monitor stack resides in high memory and is not affected
-but any code that changes the stack to low memory will be
-affected.
-
-### Bank codes and descriptions
-
-TYPE | DESCRIPTION        |BANK| DETAILS
------|--------------------|----|---------------------
-RAM  | COMMON BANK        | 9F | 1024K RAM SYSTEM
-RAM  | USER BANK          | 9E | 1024K RAM SYSTEM
-RAM  | BIOS BANK          | 9D | 1024K RAM SYSTEM
-RAM  | AUX BANK           | 9C | 1024K RAM SYSTEM
-RAM  | OS BUFFERS END     | 9B | 1024K RAM SYSTEM
-RAM  | OS BUFFERS START   | 98 | 1024K RAM SYSTEM
-RAM  | RAM DRIVE END	  | 97 | 1024K RAM SYSTEM
-RAM  | COMMON BANK        | 8F | 512K RAM SYSTEM
-RAM  | USER BANK          | 8E | 512K RAM SYSTEM
-RAM  | BIOS BANK          | 8D | 512K RAM SYSTEM
-RAM  | AUX BANK           | 8C | 512K RAM SYSTEM
-RAM  | OS BUFFERS         | 8B | 512K RAM SYSTEM
-RAM  | OS BUFFERS         | 8A | 512K RAM SYSTEM
-RAM  | OS BUFFERS         | 89 | 512K RAM SYSTEM
-RAM  | OS BUFFERS         | 88 | 512K RAM SYSTEM
-RAM  | RAM DRIVE END	  | 87 | 512K RAM SYSTEM
-RAM  | RAM DRIVE START    | 80 |
-ROM  | BOOT BANK          | 00 | COLD START & HBIOS
-ROM  | LOADER & IMAGES    | 01 | MONITOR, FORTH
-ROM  | ROM IMAGES CONTD.  | 02 | BASIC, ETC
-ROM  | FAT FILESYSTEM     | 03 | UNA ONLY, ELSE UNUSED
-ROM  | ROM DRIVE START    | 04 |
-ROM  | ROM DRIVE END      | 0F | 512K ROM SYSTEM
-ROM  | ROM DRIVE END      | 1F | 1024K ROM SYSTEM
-
-## X-modem transfer
-
-T xxxx - Receive an X-modem file transfer and load it into
-memory starting at location xxxx. 
-
-128 byte blocks and checksum mode is the only supported 
-protocol.
-
-If the monitor is assembled with the DSKY functionality,
-this feature will be exclude due to space limitations.
-
-
-## NOTES:
-
-The RTC utility on the CP/M ROM disk provides facilities
-to manipulate the Real Time Clock non-volatile Memory. 
-Use the C or Z option from the Boot Loader to load CP/M 
-and then run RTC to see the options list.
-
-# FORTH
-
-CamelForth is the version of Forth included as part of the boot
-ROM in ROMWBW. It has been converted from the Z80 CP/M version
-published here [www.camelforth.com/page.php?5](www.camelforth.com/page.php?5). The author is Brad
-Rodriguez who is a prolific Forth enthusiast, whose work can be
-found here: [www.bradrodriguez/papers/index.html](www.bradrodriguez/papers/index.html)
-
-For those are who are not familiar with Forth, I recommend the
-wikipedia article [en.wikipedia.org/wiki/Forth_(programming_language](en.wikipedia.org/wiki/Forth_(programming_language))
-and the Forth Interest Group website [www.forth.org](www.forth.org)
-
-## Important things to know
-
-Forth is case sensitive.
-
-To exit back to the boot loader type ***bye***
-
-To get a list of available words type ***WORDS***
-
-To reset Forth to its initial state type ***COLD***
-
-Most of the code you find on the internet will not run unless modified or additional Forth
-words are added to the dictionary.
-
-This implementation does not support loading or saving of programs. All programs
-need to be typed in. Additionally, screen editing and code blocks are not supported.
-
-## Structure of Forth source files
-
-File          | Description
---------------|-----------------------------
-camel80.azm   | Code Primitives
- camel80d.azm | CPU Dependencies
- camel80h.azm | High Level words
- camel80r.azm | ROMWBW additions
-glosshi.txt   | Glossary of high level words
-glosslo.txt   | Glossary of low level words
-glossr.txt    | Glossary of ROMWBW additions
-
-## ROMWBW Additions
-
-Extensions and changes to this implementation compared to the original distribution are:
-
-The source code has been converted from Z80mr assembler to Hector Peraza's zsm.
-
-An additional file camel80r.azm has been added for including additional words to 
-the dictionary at build time. However, as currently configured there is very little space
-allocated for addition words. Exceeding the allocated ROM space will generate an error
-message when building.
-
-James Bowman's double precision words have been added from his RC2014 version:
-[https://github.com/jamesbowman/camelforth-z80](https://github.com/jamesbowman/camelforth-z80)
-
-Word    | Syntax                     | Description
---------|----------------------------|---------------------------------
-D+	| d1 d2 -- d1+d2             | Add double numbers
-2>R	| d --                       | 2 to R
-2R>	| d --                       | fetch 2 from R
-M*/	| d1 n2 u3 --  d=(d1*n2)/u3  | double precision mult. div
-SVC	| hl de bc n -- hl de bc af  | Execute a ROMWBW function
-P!	| n p --                     | Write a byte to a I/O port
-P@      | p -- n                     | Read a byte from and I/O port
-
-# BASIC
-
-For those who are not familiar with BASIC, it stands for Beginners All purpose Symbolic
-Instruction Code. 
-
-ROMWBW contains two versions of ROM BASIC, a full implementation and a "tiny" BASIC.
-
-The full implementation is a version of Microsoft BASIC from the NASCOM Computer.
-
-A comprehensive instruction manual is available in the Doc\\Contrib directory.
-
-## ROMWBW specific features
-
-- Sound
-- Graphics
-- Terminal Support
-
-## ROMWBW unsupported features
-
-- This ROM-hosted implementation does not support cassette or disk
-  access for loading and saving programs.
-
-# TastyBASIC
-
-TastyBASIC offers a minimal implementation of BASIC that is only 2304 bytes in size. 
-It originates from Li-Chen Wang's Palo Alto Tiny BASIC from around 1976. It's small size suited the tiny memory capacities of the time. This implementation is by Dimitri Theulings and his
-original source can be found here [https://github.com/dimitrit/tastybasic](https://github.com/dimitrit/tastybasic)
-
-## Features / Limitations
-
-- This ROM-hosted implementation does not support disk access for
-  loading and saving programs.
-- Integer arithmetic, numbers -32767 to 32767
-- Singles letter variables A-Z
-- 1-dimensional array support
-- Strings are not supported
-
-## Direct Commands
-
-- `LIST`,`RUN`, `NEW`, `CLEAR`, `BYE`
-
-## Statements
-
-- `LET`, `IF`, `GOTO`, `GOSUB RETURN`, `REM`, `FOR TO NEXT STEP`, `INPUT`, `PRINT`, `POKE`, `END`
-
-## Functions
-
-- `PEEK`, `RND`, `ABS`, `USR`, `SIZE`
-
-## Operators
-
-- `>=`, `#`, `>`, `=`, `<=`, `<`
-
-- Operator precedence is supported.
-
-Type ***BYE*** to return to the monitor.
-
-# Play a Game
-
-## 2048
-
-2048 is a puzzle game that can be both mindless and challenging. It
-appears deceptively simple but failure can creep up on you suddenly.
-
-It requires an ANSI/VT-100 compatible colour terminal to play.
-
-2048 is like a sliding puzzle game except the puzzle tiles are 
-numbers instead of pictures. Instead of moving a single tile all 
-tiles are moved simultaneously in the same direction. Where two 
-tiles of the same number collide, they are reduced to one tile with
-the combined value. After every move a new tile is added with
-a starting value of 2. 
-
-The goal is to create a tile of 2048 before all tile locations are
-occupied. Reaching the highest points score, which is the sum of all
-the tiles is a secondary goal. The game will automatically end when 
-there are no more possible moves.
-
-Play consists of entering a direction to move. Directions can be entered
-using any of three different keyboard direction sets.
-
-```
-Direction | Keys
-----------|----------
-Up        | w ^E 8
-Down      | s ^X 2
-Left      | a ^S 4
-Right     | d ^D 6
-```
-The puzzle board is a 4x4 grid. At start, the grid will be populated
-with two 2 tiles. An example game sequence is shown below with new
-tiles to the game shown in brackets.
-
-```
-Start             Move 1 - Up       Move 2 - Left     Move 3 - Left
-+---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+
-|   |   |   |(2)| |   |   |   | 4 | | 4 |   |   |   | | 4 |   |   |   |
-+---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+
-|   |   |   |   | |   |   |   |   | |   |   |   |(4)| | 4 |   |   |   |
-+---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+
-|   |   |   |(2)| |   |   |   |   | |   |   |   |   | |   |   |   |   |
-+---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+
-|   |   |   |   | |   |   |(2)|   | | 2 |   |   |   | | 2 |   |(2)|   |
-+---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+
-
-Move 4 - Left     Move 5 - Up       Move 6 - Right    Move 7 - Up
-+---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+
-| 4 |   |   |   | | 8 |   |   | 4 | |   |   | 8 | 4 | |   |   | 8 | 8 |
-+---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+
-| 4 |   |   |(4)| | 4 |   |   |   | |   |   |   | 4 | |   |   |   | 2 |
-+---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+
-|   |   |   |   | |   |   |   |   | |   |   |   |   | |   |   |   |   |
-+---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+
-| 4 |   |   |   | |(2)|   |   |   | |(2)|   |   | 2 | |(2)|   |   |   |
-+---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+
-```
-This is how I lost this game:
-```
-+---+---+---+---+
-| 4 | 2 | 16| 4 |
-+---+---+---+---+
-| 32| 64| 8 | 2 |
-+---+---+---+---+
-| 4 | 8 |128| 32|
-+---+---+---+---+
-|(2)| 16| 8 | 4 |
-+---+---+---+---+
-```
-Press Q at any time to bring up the option to Quit or Restart the game.
-
-# Network Boot
-
-# Xmodem Flash Updater
-
-The ROMWBW Xmodem flash updater provides the capability to update ROMWBW from the boot loader using  an x-modem file transfer. It offers similar capabilities to Will Sowerbutts FLASH4 utility except that the flashing process occurs during the file transfer. 
-
-These are the key differences between the two methods are:
-
-Xmodem Flash Updater            | FLASH4
---------------------------------|-----------------
-Available from the boot loader   | Well proven and tested
-Xmodem transfer is integrated    | Wider range of supported chips and hardware
-Integrated checksum utilities    | Wider range of supported platforms
-Capability to copy a ROM image   | Only reprograms sectors that have changed
-More convenient one step process | Ability save and verify ROM images
-No intermediate storage required | Progress display while flashing
-.                                | Displays chip identification information
-.                                | Faster file transfer
-                                 
-The major disadvantages of the Updater is that it is new and relatively untested. There is the risk that a failed transfer will result in a partially flashed and unbootable ROM. There are some limitations on serial transfer speeds.
- 
-The updater utility was initially intended to support the Retrobrew SBC-V2-005 platform using Atmel 39SF040 flash chips but has now been extended to be more generic in operation.
-
-Supported flash chips are 
-39SF040, 29F040,  AT49F040, AT29C040, M29F040 , MX29F040,  A29010B, A29040B
-
-The Atmel 39SF040 chip is recommended as it can erase and write 4Kb sectors. Other chips require the whole chip to be erased.
-
-## Usage
-
-In most cases, completing a ROM update is a simple as:
-
-1. Booting to the boot loader prompt
-2. Selecting option X - Xmodem Flash Updater
-3. Selecting option U - Update
-4. Initiating an X-modem transfer of your ROM image on your console device
-5. Selecting option R - Reboot
-
-If your console device is not able to transfer a ROM image i.e. your console is a VDU then you will have to use the console options to identify which character-input/output device is to be used as the serial device for transfer.
-
-When your console is the serial device used for the transfer, no progress information is displayed as this would disrupt the x-modem file transfer. If you use an alternate character-input/output devices as the serial device for the transfer then progress information will be displayed on the console device.
-
-Due to different platform processor speeds,  serials speeds and flow control capabilities the default console or serial device speed may need to be reduced for a successful transfer and flash to occur. The **Set Console Interface/Baud code** option at the Boot Loader can be used to change the speed if required. Additionally, the Updater has options to set to and revert from a recommended speed. 
-
-See the ROMWBW Applications guide for additional information on performing upgrades.
-
-## Console Options
-
-Option ( C ) - Set Console Device
-
-Option ( S ) - Set Serial Device
-
-By default the updater assumes that the current console is a serial device and that the ROM file to be flashed will also be transferred across this device, so the Console and Serial device are both the same.
-
-Either device can be can be change to another character-input/output device but the updater will always expect to receive the x-modem transfer on the **Serial Device**
-
-The advantage of transferring on a different device to the console is that progress information can be displayed during the transfer.
-
-Option ( > ) - Set Recommended Baud Rate
-
-Option ( < ) - Revert to Original Baud Rate
-
-## Programming options
-
-Option ( U ) - Begin Update
-
-The will begin the update process. The updater will expect to start receiving
-an x-modem file on the serial device unit.
-
-X-modem sends the file in packets of 128 bytes. The updater will cache 32
-packets which is 1 flash sector and then write that sector to the
-flash device.
-
-If using separate console, bank and sector progress information will shown
-
-```
-BANK 00 s00 s01 s02 s03 s04 s05 s06 s06 s07
-BANK 01 s00 s01 s02 s03 s04 s05 s06 s06 s07
-BANK 02 s00 s01 s02 s03 s04 s05 s06 s06 s07 etc
-```
-
-The x-modem file transfer protocol does not provide any filename or size
-information for the transfer so the updater does not perform any checks
-on the file suitability.
-
-The updater expects the file size to be a multiple of 4 kilobytes and
-will write all data received to the flash device. A system update
-file (128kb .img) or complete ROM can be received and written (512kb or
-1024kb .rom)
-
-If the update fails it is recommended that you retry before rebooting or
-exiting to the Boot loader as your machine may not be bootable.
-
-Option ( D ) - Duplicate flash #1 to flash #2
- 
-This option will make a copy of flash #1 onto flash #2. The purpose of this is to enable
- making a backup copy of the current flash. Intended for systems using 2x512Kb Flash devices.
-
-Option ( V ) - Toggle Write Verify
-
-By default each flash sector will be verified after being written. Slight
-performance improvements can be gained if turned off and could be used if
-you are experiencing reliable transfers and flashing.
-
-## Exit options
-
-Option ( R ) - Reboot
-
-Execute a cold reboot. This should be done after a successful update. If
-you perform a cold reboot after a failed update then it is likely that
-your system will be unusable and removing and reprogramming the flash
-will be required.
-
-Option ( Q ) - Quit to boot loader. 
-
-The SBC Boot Loader is reloaded from ROM and
-executed. After a successful update a Reboot should be performed. However,
-in the case of a failed update this option could be used to attempt to
-load CP/M and perform the normal x-modem / flash process to recover.
-
-## CRC Utility options
-
-Option ( 1 ) and ( 2 ) - Calculate and display CRC32 of 1st or 2nd 512k ROM.
-Option ( 3 ) - Calculate and display CRC32 of a 1024k (2x512Kb) ROM.
-
-Can be used to verify if a ROM image has been transferred and flashed correctly. Refer  to the Teraterm section below for details on configuring the automatic display of a files CRC after it has been transferred.
-
-In Windows, right clicking on a file should also give you a context menu option CRC SHA which will allow you to select a CRC32 calculation to be done on the selected file.
-
-## Tera Term macro configuration 
-
-Macros are a useful tool for automatic common tasks. There are a number of instances where using macros to facilitate the update process could be worthwhile if you are:
-
-* Following the ROMWBW development builds.
-* Doing lots of configuration changes.
-* Doing development on ROMWBW drivers
-
-Macros can be used to automate sending ROM updates or images and for my own purposed I have set up a separate macro for transferring each of the standard build ROM, my own custom configuration ROM and update ROM.
-
-An example macro file to send an *.upd file, using checksum mode and display the crc32 value of the transmitted file:
-
-```
-Xmodem send, checksum, display crc32
-xmodemsend '\\desktop\users\phillip\documents\github\romwbw\binary\sbc_std_cust.upd' 1
-crc32file crc '\\desktop\users\phillip\documents\github\romwbw\binary\sbc_std_cust.rom'
-sprintf '0x%08x' crc
-messagebox inputstr 'crc32'
-```
-
-## Serial speed guidelines
-
-As identified in the introduction, there are limitations on serial speed depending on processor speed and flow control settings. Listed below are some of the results identified during testing.
-
-Platform / Configuration       | Processor Speed | Maximum Serial Speed
--------------------------------|-----------------|---------------------
-SBC-V2  UART no flow control   | 2mhz            | 9600
-SBC-V2  UART no flow control   | 4mhz            | 19200
-SBC-V2  UART no flow control   | 5mhz            | 19200
-SBC-V2  UART no flow control   | 8mhz            | 38400
-SBC-V2  UART no flow control   | 10mhz           | 38400
-SBC-V2  USB-FIFO 2mhz+         |                 | n/a
-SBC-MK4 ASCI no flow control   | 18.432mhz       | 9600
-SBC-MK4 ASCI with flow control | 18.432mhz       | 38400
-
-The **Set Recommend Baud Rate** option in the Updater menu follows the following guidelines.
-
-Processor Speed | Baud Rate
-----------------|----------
-1Mhz            | 4800
-2-3Mhz          | 9600
-4-7Mhz          | 19200
-8-20Mhz         | 38400
-
-These can be customized in the updater.asm source code in the CLKTBL table  if desired.
-Feedback to the ROMWBW developers on these guidelines would be appreciated.
-
-## Notes:
-- All testing was done with Teraterm x-modem, Forcing checksum mode using macros was found to give  the most reliable transfer.
-- Partial writes can be completed with 39SF040 chips. Other chips require entire flash to be erased before being written.
-- An SBC V2-005 MegaFlash or Z80 MBC required for 1mb flash support. The Updater assumes both chips are same type
-- Failure handling has not been tested.
-- Timing broadly calibrated on a Z80 SBC-v2
-- UNA BIOS not supported

Source/Doc/ReadMe.md

@@ -114,7 +114,6 @@ Documentation for $doc_product$ includes:
 * $doc_user$
 * $doc_sys$
 * $doc_apps$
-* $doc_romapps$
 * $doc_errata$
 
 # Acknowledgments

Source/Doc/SystemGuide.md

@@ -126,6 +126,142 @@ execution.
 
 ![Bank Switched Memory Layout](Graphics/BankSwitchedMemory){ width=100% }
 
+## Bank Id
+
+RomWBW utilizes a specific assignment of memory banks for dedicated
+purposes.  A numeric Bank Id is used to refer to the memory banks.  The
+Bank Id is a single byte.  In general, the Bank Id simply refers to each
+of the 32K banks in sequential order.  In other words, Bank Id 0 is the
+first physical 32K, Bank Id 1 is the second, etc.  However, the high
+order bit of the Bank Id has a special meaning.  If it is 0, it indicates
+a ROM bank is being referred to.  If it is 1, it indicates a RAM bank
+is being referred to.
+
+For example, let's say we have a typical system with 512KB of ROM and
+512KB of RAM.  The Bank Ids would look like this:
+
+| Physical Memory   | Type | Physical Bank | Bank Id   |
+|-------------------|------|---------------|-----------|
+| 0x000000-0x007FFF | ROM  | 0             | 0x00      |
+| 0x008000-0x00FFFF | ROM  | 1             | 0x01      |
+| 0x010000-0x07FFFF | ROM  | 2-15          | 0x02-0x0F |
+| 0x080000-0x087FFF | RAM  | 16            | 0x80      |
+| 0x088000-0x08FFFF | RAM  | 17            | 0x81      |
+| 0x090000-0x0FFFFF | RAM  | 18-31         | 0x82-0x8F |
+
+Note that Bank Id 0x00 is **always** the first bank of ROM and 0x80 is
+**always** the first bank of RAM.  If there were more banks of physical ROM,
+they would be assigned Bank Ids starting with 0x10.  Likewise, additional
+bank of physical RAM would be assigned Bank Ids starting with 0x90.
+
+The Bank Id is used in all RomWBW API functions when referring to
+the mapping of banks to the lower 32K bank area of the processor.  In
+this way, all RomWBW functions can refer to a generic Bank Id without
+needing to understand how a specific hardware platform accesses the
+physical memory areas.  A single routine within the HBIOS is implemented
+for each memory manager that maps Bank Ids to physical memory.
+
+## Bank Assignments
+
+RomWBW requires dedicated banks of memory for specific purposes.  It
+uses Bank Ids via an algorithm to make these assignments.  The following
+table describes the way the banks are assigned.  The Typical column
+shows the specific values that would be assigned for a common system
+with 512KB of ROM and 512KB of RAM (nROM=16, nRAM=16).
+
+| Bank Id           | Identity  | Typical | Purpose                                  |
+|-------------------|-----------|---------|------------------------------------------|
+| 0x00              |BID_BOOT   | 0x00    | Boot Bank (HBIOS image)                  |
+| 0x01              |BID_IMG0   | 0x01    | Boot Loader, Monitor, ROM OSes, ROM Apps |
+| 0x02              |BID_IMG1   | 0x02    | ROM Apps                                 |
+| 0x03              |BID_IMG2   | 0x03    | \<Reserved\>                             |
+| 0x04              |BID_ROMD0  | 0x04    | First ROM Disk Bank                      |
+| nROM - 1          |           | 0x0F    | Last ROM Disk Bank                       |
+| 0x80              |BID_BIOS   | 0x80    | HBIOS (working copy)                     |
+| 0x81              |BID_RAMD0  | 0x81    | First RAM Disk Bank                      |
+| 0x80 + nRAM - 8   |           | 0x88    | Last RAM Disk Bank                       |
+| 0x80 + nRAM - 7   |BID_APP0   | 0x89    | First Application Bank                   |
+| 0x80 + nRAM - 5   |           | 0x8B    | Last Application Bank                    |
+| 0x80 + nRAM - 4   |BID_BUF    | 0x8C    | OS Disk Buffers                          |
+| 0x80 + nRAM - 3   |BID_AUX    | 0x8D    | OS Code Bank                             |
+| 0x80 + nRAM - 2   |BID_USR    | 0x8E    | User Bank (CP/M TPA)                     |
+| 0x80 + nRAM - 1   |BID_COM    | 0x8F    | Common Bank                              |
+
+In this table, nROM and nRAM refer to the number of corresponding
+ROM and RAM banks in the the system.
+
+The contents of the banks referred to above are described in more detail
+below:
+
+Boot Bank:
+
+: The Boot Bank receives control when a system is first powered
+on.  It contains a ROM (read-only) copy of the HBIOS.  At boot, it does
+minimal hardware initialization, then copies itself to the HBIOS bank
+in RAM, then resumes execution from the RAM bank.
+
+Boot Loader:
+
+: The application that handles loading of ROM or Disk based applications
+including operating systems.  It copies itself to a RAM bank at the
+start of it's execution.
+
+Monitor:
+
+: The application that implements the basic system monitor functions.
+It copies itself to a RAM bank at the start of it's execution.
+
+ROM OSes:
+
+: Code images of CP/M 2.2 and Z-System which are copied to RAM and
+executed when a ROM-based operating system is selected in the Boot
+Loader.
+
+ROM Applications:
+
+: Various ROM-based application images such as BASIC, FORTH, etc.  They
+can be selected in the Boot Loader.  The Boot Loader will copy the
+application image to a RAM bank, then transfer control to it.
+
+ROM Disk:
+
+: A sequential series of banks assigned to provide the system ROM Disk
+contents.
+
+HBIOS:
+
+: This bank hosts the running copy of the RomWBW HBIOS.
+
+RAM Disk:
+
+: A sequential series of banks assigned to provide the system RAM Disk.
+
+Application Bank:
+
+: A sequential series of banks that are available for use by applications
+that wish to utilize banked memory.
+
+OS Disk Buffers:
+
+: This bank is used by CP/M 3 and ZPM3 for disk buffer storage.
+
+OS Code Bank:
+
+: This bank is used by CP/M 3 and ZPM3 as an alternate bank for code.
+This allows these operating systems to make additional TPA space
+available for applications.
+
+User Bank:
+
+: This is the default bank for applications to use.  This includes the
+traditional TPA space for CP/M.
+
+Common Bank:
+
+: This bank is mapped to the upper 32K of the processors memory space.
+It is a fixed mapping that is never changed in normal RomWBW operation
+hence the name "Common".
+
 # System Boot Process
 
 A multi-phase boot strategy is employed. This is necessary because at
@@ -2272,14 +2408,19 @@ to see if it is incrementing.
 |----------------------------------------|----------------------------------------|
 | B: 0xF8                                | A: Status                              |
 | C: 0xD1                                | DEHL: Seconds Count                    |
-|                                        | C: Ticks per Second                    |
+|                                        | C: Remainder Ticks                     |
 
-Return the a Seconds Count (DEHL) with the number of seconds that have 
+Return the Seconds Count (DEHL) with the number of seconds that have 
 elapsed since the system was started.  This is a double-word binary 
-value.  Additionally, the number of Ticks per Second (C) is returned.  
-The returned Status (A) is a standard HBIOS result code.
+value.  Additionally, Remainder Ticks (C) is returned and contains the number
+of ticks that have elapsed within the current second.
 
-This availability of the Seconds Count (DEHL) is dependent on having a 
+Note that Remainder Ticks (C) will have a value from 0 to 49 since there are
+50 ticks per second.  So, Remainder Ticks does not represent a fraction of the
+current second.  Remainder Ticks (C) can be doubled to derive the hundredths of
+milliseconds elapsed within the current second.
+
+The availability of the Seconds Count (DEHL) is dependent on having a 
 system timer active.  If the hardware configuration has no system timer,
 then Seconds Count (DEHL) will not increment.
 

Source/Doc/UserGuide.md

@@ -11,11 +11,8 @@ companion documents you should refer to as appropriate:
   of RomWBW.  It includes a reference for the RomWBW HBIOS API
   functions.
 
-* $doc_romapps$ is a reference for the ROM-hosted applications provided
-  with RomWBW including the monitor, programming languages, etc.
-
-* $doc_apps$ is a reference for the OS-hosted proprietary command
-  line applications that were created to enhance RomWBW.
+* $doc_apps$ is a reference for the ROM-hosted and OS-hosted applications
+  created or customized to enhance the operation of RomWBW.
 
 * $doc_catalog$ is a reference for the contents of the disk images
   provided with RomWBW.  It is somewhat out of date at this time.
@@ -264,6 +261,7 @@ is discussed in [Customizing RomWBW].
 | [Heath H8 Z80 System]^10^                                      | H8      | HEATH_std.rom         | 115200        |
 | [EP Mini-ITX Z180]^11^                                         | RCBus?  | EPITX_std.rom         | 115200        |
 | [NABU w/ RomWBW Option Board]^10^                              | NABU    | NABU_std.rom          | 115200        |
+| [S100 FPGA Z80]^9^                                             | S100    | FZ80_std.rom          | 9600          |
 
 | ^1^Designed by Andrew Lynch
 | ^2^Designed by Sergey Kiselev
@@ -390,7 +388,7 @@ At the Boot Loader prompt, you can type `H <enter>` for help.  You
 can type `L <enter>` to list the available built-in ROM applications.
 If your terminal supports ANSI escape sequences, you can try the
 'P' command to play a simple on-screen game.  Instructions for the
-game are found in $doc_romapps$.
+game are found in $doc_apps$.
 
 If all of this seems fine, your ROM has been successfully programmed.
 See the [Boot Loader Operation] section of this document for further
@@ -644,7 +642,7 @@ return to the Boot Loader menu.  If you are interested in creating a
 custom application to run here, review the "usrrom.asm" file in the
 Source/HBIOS folder of the distribution.
 
-Each of the ROM Applications is documented in $doc_romapps$.  Some
+Each of the ROM Applications is documented in $doc_apps$.  Some
 of the applications (such as BASIC) also have their own independent
 manual in the Doc directory of the distribution.  The OSes included
 in the ROM (CP/M 2.2 & Z-System) are described in the Operating Systems
@@ -2628,7 +2626,19 @@ selecting slice 0 of the corresponding hard disk unit at
 the RomWBW Boot Loader prompt.  Do not attempt to use
 CP/M slices on the same disk.
 
-Refer to the ReadMe.txt file in Source/pSys for more details.
+Due to limitations in the p-System configuration mechanism, it does
+not recognize the arrow keys of an ANSI Terminal.  To work around
+this, the following control keys have been defined:
+
+| Function   | Key        |
+|------------|------------|
+| Up         | ctrl+E     |
+| Down       | ctrl+X     |
+| Left       | ctrl+S     |
+| Right      | ctrl+D     |
+
+Refer to [Source/pSys/ReadMe.txt]($file_root$/Source/pSys/ReadMe.txt)
+for more details about the p-System adaptation.
 
 #### Documentation
 
@@ -5879,6 +5889,33 @@ S- MD: TYPE=RAM
 
 `\clearpage`{=latex}
 
+### S100 FPGA Z80
+
+#### ROM Image File:  FZ80_std.rom
+
+|                   |               |
+|-------------------|---------------|
+| Default CPU Speed | 8.000 MHz     |
+| Interrupts        | None          |
+| System Timer      | None          |
+| Serial Default    | 9600 Baud     |
+| Memory Manager    | Z2            |
+| ROM Size          | 0 KB          |
+| RAM Size          | 512 KB        |
+
+##### Supported Hardware (see [Appendix B - Device Summary]):
+
+FP: LEDIO=255
+SSER: IO=52
+SCON: IO=0
+MD: TYPE=RAM
+PPIDE: IO=48, MASTER
+PPIDE: IO=48, SLAVE
+
+##### Notes:
+
+- Requires matching FPGA code
+
 ## Appendix B - Device Summary
 
 The table below briefly describes each of the possible devices that

Source/FZ80/Bank Layout.txt

@@ -0,0 +1,18 @@
+FPGA Z80 has no real ROM.  It has a single 512K RAM chip.
+
+The ROMless startup mode treats the entire 512KB as RAM.  384KB of RAM 
+must be preloaded by the FPGA Monitor CF Loader.  There will be no ROM 
+disk available under RomWBW.  There will be a RAM Disk and it's initial 
+contents will be seeded by the image loaded by the CF Loader.
+
+Bank		Contents	Description
+--------	--------	-----------
+0x0		BIOS		HBIOS Bank (operating)
+0x1		IMG0		ROM Loader, Monitor, ROM OSes
+0x2		IMG1		ROM Applications
+0x3		IMG2		Reserved
+0x4-0xB		RAMD		RAM Disk Banks
+0xC		BUF		OS Buffers (CP/M3)
+0xD		AUX		Aux Bank (CP/M 3, BPBIOS, etc.)
+0xE		USR		User Bank (CP/M TPA, etc.)
+0xF		COM		Common Bank, Upper 32KB

Source/FZ80/Build.cmd

@@ -0,0 +1,21 @@
+@echo off
+setlocal
+
+set TOOLS=../../Tools
+
+set PATH=%TOOLS%\srecord;%PATH%
+
+if exist ..\..\Binary\FZ80_std.rom call :build_fz80
+
+goto :eof
+
+:build_fz80
+
+srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x1B8 0x200 fz80_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x80000 0xE0000 ..\..\Binary\FZ80_std.rom -binary -offset 0x80000 -o temp.dat -binary
+move temp.dat ..\..\Binary\hd1k_fz80_prefix.dat
+
+copy /b ..\..\Binary\hd1k_fz80_prefix.dat + ..\..\Binary\hd1k_cpm22.img + ..\..\Binary\hd1k_zsdos.img + ..\..\Binary\hd1k_nzcom.img + ..\..\Binary\hd1k_cpm3.img + ..\..\Binary\hd1k_zpm3.img + ..\..\Binary\hd1k_ws4.img ..\..\Binary\hd1k_fz80_combo.img || exit /b
+
+goto :eof

Source/FZ80/Clean.cmd

@@ -0,0 +1,3 @@
+@echo off
+setlocal
+

Source/FZ80/FZ80 Disk Layout.txt

@@ -0,0 +1,19 @@
+FZ80 Disk Prefix Layout
+=======================
+
+---- Bytes ----   --- Sectors ---
+Start   Length    Start   Length    Description
+------- -------   ------- -------   ---------------------------
+0x00000 0x001BE   0       1         Unused
+0x001B8 0x00048                     RomWBW Partition Table
+0x00200 0x1EE00   1       7FE00     Unused
+0x80000 0x60000   1024    768       RomWBW
+0x100000          2048              Start of slices (partition 0x1E)
+
+Notes
+-----
+
+- FPGA Z80 Monitor reads 384KB (RomWBW) from sectors 1024-1791 of CF into first 384KB of physical RAM
+- FPGA Z80 ZRC Monitor maps first 32KB of physical RAM to first 32KB of CPU RAM and starts execution at 0x0000
+
+-- WBW 3:18 PM 6/30/2024

Source/FZ80/Makefile

@@ -0,0 +1,24 @@
+HD1KFZ80PREFIX = hd1k_fz80_prefix.dat
+HD1KFZ80COMBOIMG = hd1k_fz80_combo.img
+FZ80ROM = ../../Binary/FZ80_std.rom
+HD1KIMGS = ../../Binary/hd1k_cpm22.img ../../Binary/hd1k_zsdos.img ../../Binary/hd1k_nzcom.img \
+	../../Binary/hd1k_cpm3.img ../../Binary/hd1k_zpm3.img ../../Binary/hd1k_ws4.img
+
+OBJECTS := $(HD1KFZ80PREFIX) $(HD1KFZ80COMBOIMG)
+
+DEST=../../Binary
+
+TOOLS = ../../Tools
+
+include $(TOOLS)/Makefile.inc
+
+DIFFPATH = $(DIFFTO)/Binary
+
+$(HD1KFZ80PREFIX):
+	srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x1B8 0x200 fz80_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x80000 0xE0000 $(FZ80ROM) -binary -offset 0x80000 -o temp.dat -binary
+	mv temp.dat $@
+
+$(HD1KFZ80COMBOIMG): $(HD1KFZ80PREFIX) $(HD1KIMGS)
+	cat $^ > $@

Source/HBIOS/Build.cmd

@@ -72,7 +72,7 @@ copy ..\Fonts\font*.asm . || exit /b
 
 tasm -t%CPUType% -g3 -dROMBOOT hbios.asm hbios_rom.bin hbios_rom.lst || exit /b
 tasm -t%CPUType% -g3 -dAPPBOOT hbios.asm hbios_app.bin hbios_app.lst || exit /b
-tasm -t%CPUType% -g3 -dIMGBOOT hbios.asm hbios_img.bin hbios_img.lst || exit /b
+::tasm -t%CPUType% -g3 -dIMGBOOT hbios.asm hbios_img.bin hbios_img.lst || exit /b
 
 ::
 :: Build ROM Components
@@ -242,7 +242,8 @@ call Build S100 std || exit /b
 call Build DUO std || exit /b
 call Build HEATH std || exit /b
 call Build EPITX std || exit /b
-call Build NABU std || exit /b
 :: call Build MON std || exit /b
+call Build NABU std || exit /b
+call Build FZ80 std || exit /b
 
 goto :eof

Source/HBIOS/Build.ps1

@@ -27,7 +27,7 @@ $ErrorAction = 'Stop'
 # UNA BIOS is simply imbedded, it is not built here.
 #
 
-$PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "Z80RETRO", "DUO", "UNA", "HEATH", "MON", "NABU"
+$PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "Z80RETRO", "DUO", "UNA", "HEATH", "MON", "NABU", "FZ80"
 $PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO", "RPH", "S100", "EPITX"
 $PlatformListZ280 = "RCZ280"
 

Source/HBIOS/Build.sh

@@ -50,8 +50,9 @@ if [ "${ROM_PLATFORM}" == "dist" ] ; then
 	ROM_PLATFORM="ZETA2"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="HEATH"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="EPITX"; ROM_CONFIG="std"; bash Build.sh
-	ROM_PLATFORM="NABU"; ROM_CONFIG="std"; bash Build.sh
 #	ROM_PLATFORM="MON"; ROM_CONFIG="std"; bash Build.sh
+	ROM_PLATFORM="NABU"; ROM_CONFIG="std"; bash Build.sh
+	ROM_PLATFORM="FZ80"; ROM_CONFIG="std"; bash Build.sh
 	exit
 fi
 

Source/HBIOS/Config/FZ80_std.asm

@@ -0,0 +1,34 @@
+;
+;==================================================================================================
+;   S100 FPGZ Z80 STANDARD CONFIGURATION
+;==================================================================================================
+;
+; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
+; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
+; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
+; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
+; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
+; YOUR FILE IN THE BUILD PROCESS.
+;
+; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
+; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
+; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
+; SETTINGS.
+;
+; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
+; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
+; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
+; DIRECTORIES ABOVE THIS ONE).
+;
+#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
+;
+#include "cfg_fz80.asm"
+;
+CPUOSC		.SET	8000000		; CPU OSC FREQ IN MHZ
+CRTACT		.SET	TRUE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+;
+; SD CARD SUPPORT CURRENTLY BROKEN
+SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDTRACE		.SET	3		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/ay38910.asm

@@ -19,6 +19,15 @@
 ;  UNUSED BITS CAN BE READ BACK AND WRITTEN ON YM.
 ;  VOLTAGE LEVEL OUTPUT ON A AY-3-8910 IS LOW AND AROUND 2V ON YM2149.
 ;
+; THERE ARE TWO VARIANTS OF AY-3-8910 SOUND CARDS THAT HAVE BEEN
+; PRODUCED FOR THE RCBUS.  THE ONE PRODUCED BY ED BRINDLEY (EB) USES
+; THE SAME PORT FOR REGISTER SELECT (RSEL) AND REGISTER IN (RIN).
+; THE ONE PRODUCED BY MARTEN FELDTMANN (MF) USES THE PORT FOLLOWING
+; REGISTER SELECT (RSEL) FOR THE REGISTER IN (RIN) PORT.  THE FOLLOWING
+; EQUATE MUST BE SET CORRECTLY FOR THE HARDWARE BEING USED.  THIS
+; HAS NOT BEEN MOVED TO A CONFIG VARIABLE BECAUSE THE MF MODULE IS
+; RARELY ENCOUNTERED IN THE WILD.
+;
 AY_RCSND	.EQU	0		; 0 = EB MODULE, 1=MF MODULE
 ;
 	DEVECHO	"AY38910: MODE="
@@ -219,7 +228,7 @@ AY_FND:	LD	IY, AY_IDAT		; SETUP FUNCTION TABLE
 ;
 	CALL	AY_INIT			; SET DEFAULT CHIP CONFIGURATION
 ;
-	LD	E,$07			; SET VOLUME TO 50%
+	LD	E,$08			; SET VOLUME TO 50%
 	CALL	AY_SETV			; ON ALL CHANNELS
 ;
 ;	LD	DE,(AY_R2CHBP*256)+$55	; BEEP ON CHANNEL B (CENTER)
@@ -227,14 +236,19 @@ AY_FND:	LD	IY, AY_IDAT		; SETUP FUNCTION TABLE
 	LD	DE,(AY_R3CHBP*256)+$00
 	CALL	AY_WRTPSG		; R03 = $00 = XXXX0000
 ;
-#IF ((SYSTIM != TM_NONE) & (AYMODE != AYMODE_DUO))
+#IF (SYSTIM != TM_NONE)
 	LD	A, TICKFREQ / 3		; SCHEDULE IN 1/3 SECOND TO TURN OFF SOUND
 	LD	(AY_TIMTIK), A
 ;
-	LD	HL, (VEC_TICK + 1)	; GET CUR TICKS VECTOR
-	LD	(AY_TIMHOOK), HL	; SAVE IT INTERNALLY
-	LD	HL, AY_TIMER		; INSTALL TIMER HOOK HANDLER
-	LD	(VEC_TICK + 1), HL
+	; RESET THE AY_TIMER BYPASS
+	LD	HL,AY_TIMER1
+	LD	(AY_TIMER + 1),HL
+;
+	; HOOK THE TICK VECTOR
+	LD	HL,(VEC_TICK + 1)	; GET CUR TICKS VECTOR
+	LD	(AY_TIMHOOK + 1),HL	; SAVE IT INTERNALLY
+	LD	HL,AY_TIMER		; INSTALL TIMER HOOK HANDLER
+	LD	(VEC_TICK + 1),HL
 ;
 	LD	A, $02			; NOT READY & IN INTERUPT HANDLER
 	LD	(AY_READY), A
@@ -249,27 +263,27 @@ AY_FND:	LD	IY, AY_IDAT		; SETUP FUNCTION TABLE
 	XOR	A			; SUCCESSFULL INIT
 	RET
 ;
-#IF ((SYSTIM != TM_NONE) & (AYMODE != AYMODE_DUO))
+#IF (SYSTIM != TM_NONE)
 AY_TIMER:
-	LD	A, (AY_TIMTIK)
+	JP	AY_TIMER1		; SELF MODIFIED TO BYPASS HANDLER
+AY_TIMER1:
+	LD	A,(AY_TIMTIK)
 	DEC	A
 	LD	(AY_TIMTIK), A
-	JR	NZ, AY_TIMER1
+	JR	NZ,AY_TIMHOOK
 ;
 	LD	E,$00			; SET VOLUME OFF
 	CALL	AY_SETV			; ON ALL CHANNELS
 	LD	A, $01			; READY & NOT IN INTERUPT HANDLER
 	LD	(AY_READY), A
 ;
-	LD	DE, AY_TIMER		; MAKE AY_TIMER A NO_OP HANDLER
-	LD	HL, AY_TIMER1
-	LD	BC, 3
-	LDIR
+	; MAKE AY_TIMER A NO-OP HANDLER
+	LD	HL,(AY_TIMHOOK + 1)
+	LD	(AY_TIMER + 1),HL
 ;
-AY_TIMER1:
+AY_TIMHOOK:
 	JP	0			; OVERWRITTEN WITH NEXT HANDLER
-AY_TIMHOOK:	.EQU	$ - 2
-
+;
 AY_TIMTIK	.DB	0		; COUNT DOWN TO FINISH BOOT BEEP
 #ENDIF
 ;

Source/HBIOS/cfg_duo.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_DUO		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+PLATFORM	.EQU	PLT_DUO		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -124,6 +124,15 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
+SSERDATA	.EQU	$FF		; SSER: DATA PORT
+SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+;
 DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
 UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
@@ -230,7 +239,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_dyno.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_DYNO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+PLATFORM	.EQU	PLT_DYNO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -126,6 +126,15 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
+SSERDATA	.EQU	$FF		; SSER: DATA PORT
+SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+;
 DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 DUARTCNT	.EQU	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
 DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
@@ -245,7 +254,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_epitx.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_EPITX	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+PLATFORM	.EQU	PLT_EPITX	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -128,6 +128,15 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
+SSERDATA	.EQU	$FF		; SSER: DATA PORT
+SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+;
 DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 DUARTCNT	.EQU	2		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
 DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
@@ -247,7 +256,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_EPITX	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|EPITX]
+SDMODE		.EQU	SDMODE_EPITX	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	$40		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
 SDTRACE		.EQU	2		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_fz80.asm

@@ -0,0 +1,347 @@
+;
+;==================================================================================================
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR S100 FPGA Z80
+;==================================================================================================
+;
+; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
+; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
+; UNDER THIS DIRECTORY.
+;
+; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
+; FOR THE PLATFORM.
+;
+#DEFINE PLATFORM_NAME "S100 FPGA Z80", " [", CONFIG, "]"
+;
+#INCLUDE "hbios.inc"
+;
+PLATFORM	.EQU	PLT_FZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+;
+BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+AUTOCON		.EQU	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
+;
+CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.EQU	8000000		; CPU OSC FREQ IN MHZ
+INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;
+RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.EQU	0		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+APP_BNKS	.EQU	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
+MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
+MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
+;
+RTCIO		.EQU	$C0		; RTC LATCH REGISTER ADR
+;
+KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+;
+CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
+CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
+CTCMODE		.EQU	CTCMODE_TIM16	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
+CTCPRE		.EQU	256		; PRESCALE CONSTANT (1-256)
+CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
+CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
+CTCOSC		.EQU	CPUOSC		; CTC CLOCK FREQUENCY
+;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
+SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+SKZDIV		.EQU	DIV_1		; UART CLK (CLK2) DIVIDER FOR Z80-512K
+;
+WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+WDOGIO		.EQU	$6E		; WATCHDOG REGISTER ADR
+;
+FPLED_ENABLE	.EQU	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.EQU	$FF		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_INV	.EQU	FALSE		; FP: LED BITS ARE INVERTED
+FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
+;
+DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+;
+LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
+LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
+LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
+LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+;
+DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+;
+BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
+CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYENABLE	.EQU	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+;
+DSRTCENABLE	.EQU	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
+DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+;
+DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+;
+BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+;
+INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+;
+RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
+HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+;
+DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+;
+SSERENABLE	.EQU	TRUE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.EQU	$34		; SSER: STATUS PORT
+SSERDATA	.EQU	$35		; SSER: DATA PORT
+SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.EQU	TRUE		; SSER: OUTPUT READY BIT INVERTED
+;
+DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+DUARTCNT	.EQU	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
+DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
+DUART0ACFG	.EQU	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
+DUART0BCFG	.EQU	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
+DUART1BASE	.EQU	$40		; DUART 1: BASE ADDRESS OF CHIP
+DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
+DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
+;
+UARTENABLE	.EQU	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
+UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
+UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
+UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
+UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
+UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
+UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
+UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+;
+ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+;
+Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+;
+ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+ACIADEBUG	.EQU	FALSE		; ACIA: ENABLE DEBUG OUTPUT
+ACIACNT		.EQU	1		; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
+ACIA0BASE	.EQU	$80		; ACIA 0: REGISTERS BASE ADR
+ACIA0CLK	.EQU	CPUOSC		; ACIA 0: OSC FREQ IN HZ
+ACIA0DIV	.EQU	1		; ACIA 0: SERIAL CLOCK DIVIDER
+ACIA0CFG	.EQU	DEFSERCFG	; ACIA 0: SERIAL LINE CONFIG  (SEE STD.ASM)
+ACIA1BASE	.EQU	$40		; ACIA 1: REGISTERS BASE ADR
+ACIA1CLK	.EQU	CPUOSC		; ACIA 1: OSC FREQ IN HZ
+ACIA1DIV	.EQU	1		; ACIA 1: SERIAL CLOCK DIVIDER
+ACIA1CFG	.EQU	DEFSERCFG	; ACIA 1: SERIAL LINE CONFIG  (SEE STD.ASM)
+;
+SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.EQU	CPUOSC		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
+SIO1ACLK	.EQU	CPUOSC		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1ACFG	.EQU	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
+SIO1ACTCC	.EQU	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1BCLK	.EQU	CPUOSC		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1BCFG	.EQU	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
+SIO1BCTCC	.EQU	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+;
+XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+;
+VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80]
+TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	TRUE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+;
+MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.EQU	FALSE		; MD: ENABLE ROM DISK
+MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+;
+FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+;
+RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+;
+IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.EQU	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT		.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.EQU	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE0BASE	.EQU	$10		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.EQU	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.EQU	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.EQU	TRUE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.EQU	TRUE		; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.EQU	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE1BASE	.EQU	$00		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.EQU	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.EQU	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.EQU	TRUE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.EQU	TRUE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.EQU	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE2BASE	.EQU	$00		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.EQU	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.EQU	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.EQU	TRUE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.EQU	TRUE		; IDE 2B (MASTER): 8 BIT XFER
+;
+PPIDEENABLE	.EQU	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.EQU	$30		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1BASE	.EQU	$00		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE2BASE	.EQU	$00		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+;
+SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.EQU	SDMODE_FZ80	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
+SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.EQU	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$3E		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.EQU	$3C		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	TRUE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+;
+PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+;
+PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
+HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+;
+LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTMODE		.EQU	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTCNT		.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
+LPTTRACE	.EQU	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+LPT0BASE	.EQU	$0C		; LPT 0: REGISTERS BASE ADR
+LPT1BASE	.EQU	$00		; LPT 1: REGISTERS BASE ADR
+;
+PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
+PPACNT		.EQU	1		; PPA: NUMBER OF PPA DEVICES (1-2)
+PPATRACE	.EQU	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPAMODE		.EQU	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
+PPA0BASE	.EQU	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
+PPA1BASE	.EQU	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
+;
+IMMENABLE	.EQU	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+IMMCNT		.EQU	1		; IMM: NUMBER OF IMM DEVICES (1-2)
+IMMTRACE	.EQU	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IMMMODE		.EQU	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
+IMM0BASE	.EQU	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
+IMM1BASE	.EQU	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
+;
+SYQENABLE	.EQU	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
+SYQCNT		.EQU	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
+SYQTRACE	.EQU	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SYQMODE		.EQU	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
+SYQ0BASE	.EQU	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQ1BASE	.EQU	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
+;
+PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+;
+UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+;
+SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
+SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
+;
+AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
+AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+;
+SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+;
+DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.EQU	DMAMODE_RC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
+;
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_heath.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_HEATH	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+PLATFORM	.EQU	PLT_HEATH	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -126,6 +126,15 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
+SSERDATA	.EQU	$FF		; SSER: DATA PORT
+SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+;
 DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 DUARTCNT	.EQU	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
 DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
@@ -250,7 +259,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_master.asm

@@ -12,7 +12,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -155,6 +155,15 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
+SSERDATA	.EQU	$FF		; SSER: DATA PORT
+SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+;
 DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 DUARTCNT	.EQU	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
 DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
@@ -297,7 +306,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_NONE	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_NONE	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_mbc.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_MBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+PLATFORM	.EQU	PLT_MBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -121,6 +121,15 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
+SSERDATA	.EQU	$FF		; SSER: DATA PORT
+SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+;
 DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
 UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
@@ -227,7 +236,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_JUHA	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_JUHA	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_mk4.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_MK4		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+PLATFORM	.EQU	PLT_MK4		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -126,6 +126,15 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
+SSERDATA	.EQU	$FF		; SSER: DATA PORT
+SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+;
 DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
 UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
@@ -236,7 +245,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MK4	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_MK4	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_mon.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_MON		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+PLATFORM	.EQU	PLT_MON		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -121,6 +121,15 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
+SSERDATA	.EQU	$FF		; SSER: DATA PORT
+SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+;
 DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 DUARTCNT	.EQU	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
 DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
@@ -245,7 +254,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_n8.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_N8		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+PLATFORM	.EQU	PLT_N8		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -128,6 +128,15 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
+SSERDATA	.EQU	$FF		; SSER: DATA PORT
+SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+;
 DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
 UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
@@ -238,7 +247,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_CSIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_CSIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	N8_PPI0		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_nabu.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_NABU	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+PLATFORM	.EQU	PLT_NABU	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -30,7 +30,7 @@ AUTOCON		.EQU	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
 CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	3580000		; CPU OSC FREQ IN MHZ
-INTMODE		.EQU	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
@@ -116,7 +116,7 @@ DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
 BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
 BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
 ;
-INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+INTRTCENABLE	.EQU	TRUE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
 RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
 ;
@@ -126,6 +126,15 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
+SSERDATA	.EQU	$FF		; SSER: DATA PORT
+SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+;
 DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 DUARTCNT	.EQU	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
 DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
@@ -250,7 +259,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_rcz180.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+PLATFORM	.EQU	PLT_RCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -132,6 +132,15 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
+SSERDATA	.EQU	$FF		; SSER: DATA PORT
+SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+;
 DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 DUARTCNT	.EQU	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
 DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
@@ -251,7 +260,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_rcz280.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RCZ280	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+PLATFORM	.EQU	PLT_RCZ280	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
 CPUFAM		.EQU	CPU_Z280	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -126,6 +126,15 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
+SSERDATA	.EQU	$FF		; SSER: DATA PORT
+SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+;
 DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 DUARTCNT	.EQU	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
 DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
@@ -255,7 +264,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_rcz80.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RCZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+PLATFORM	.EQU	PLT_RCZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -126,6 +126,15 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
+SSERDATA	.EQU	$FF		; SSER: DATA PORT
+SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+;
 DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 DUARTCNT	.EQU	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
 DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
@@ -250,7 +259,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_rph.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RPH		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+PLATFORM	.EQU	PLT_RPH		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	TRUE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -126,6 +126,15 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
+SSERDATA	.EQU	$FF		; SSER: DATA PORT
+SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+;
 DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
 UARTENABLE	.EQU	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
@@ -227,7 +236,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_CSIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_CSIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	RPH_PPI0	; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_s100.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_S100	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+PLATFORM	.EQU	PLT_S100	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -126,6 +126,15 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
+SSERDATA	.EQU	$FF		; SSER: DATA PORT
+SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+;
 DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 DUARTCNT	.EQU	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
 DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
@@ -245,7 +254,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_SC	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_SC	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_sbc.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -121,6 +121,15 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
+SSERDATA	.EQU	$FF		; SSER: DATA PORT
+SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+;
 DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
 UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
@@ -226,7 +235,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_JUHA	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_JUHA	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_scz180.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_SCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+PLATFORM	.EQU	PLT_SCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -126,6 +126,15 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
+SSERDATA	.EQU	$FF		; SSER: DATA PORT
+SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+;
 DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 DUARTCNT	.EQU	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
 DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
@@ -245,7 +254,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_SC	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_SC	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_una.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "../UBIOS/ubios.inc"
 ;
-;PLATFORM	.EQU	PLT_UNA		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+;PLATFORM	.EQU	PLT_UNA		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_UNA	; HARDWARE BIOS: BIOS_[WBW|UNA]
 ;

Source/HBIOS/cfg_z80retro.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_Z80RETRO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+PLATFORM	.EQU	PLT_Z80RETRO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -119,6 +119,15 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
+SSERDATA	.EQU	$FF		; SSER: DATA PORT
+SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+;
 DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
 UARTENABLE	.EQU	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
@@ -201,7 +210,7 @@ PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
 PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_Z80R	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_Z80R	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE

Source/HBIOS/cfg_zeta.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_ZETA	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+PLATFORM	.EQU	PLT_ZETA	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; BIOS_[WBW|UNA]: HARDWARE BIOS
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -108,6 +108,15 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
+SSERDATA	.EQU	$FF		; SSER: DATA PORT
+SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+;
 DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
 UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
@@ -171,7 +180,7 @@ PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
 PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_zeta2.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_ZETA2	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+PLATFORM	.EQU	PLT_ZETA2	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -119,6 +119,15 @@ SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
+SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
+SSERDATA	.EQU	$FF		; SSER: DATA PORT
+SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+;
 DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
 UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
@@ -182,7 +191,7 @@ PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
 PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/fd.asm

@@ -894,11 +894,11 @@ FD_DETECT:
 	IN	A,(FDC_MSR)	; ... AND REREAD THE STATUS
 	;CALL	PC_SPACE	; *DEBUG*
 	;CALL	PRTHEXBYTE	; *DEBUG*
-
+;
 FD_DETECT1:
 	CP	$80		; WE EXPECT $80
-	RET	Z		; IF SO, ALL DONE
-
+	JR	Z,FD_DETECT2	; IF SO, CONTINUE CHECKING
+;
 	; WE HAVE SEEN AN FDC THAT NEEDS A SECOND READ TO GET
 	; DESIRED VALUE, SO TRY ONE MORE TIME
 	CALL	DLY32		; WAIT A BIT
@@ -906,7 +906,19 @@ FD_DETECT1:
 	;CALL	PC_SPACE	; *DEBUG*
 	;CALL	PRTHEXBYTE	; *DEBUG*
 	CP	$80		; CHECK FOR CORRECT VALUE
-	RET			; RETURN WITH ZF ACCORDING TO RESULT
+	RET	NZ		; RETURN IF FAILED WITH ZF RESET
+;
+FD_DETECT2:
+	; AS A FINAL TEST, WE REREAD THE MSR USING A DIFFERENT
+	; OPCODE.  THIS SHOULD ELIMINATE ANY FALSE POSITIVES FROM
+	; A FLOATING BUS.
+	CALL	DLY32		; WAIT A BIT
+	LD	C,FDC_MSR	; POINT TO MSR PORT
+	IN	A,(C)		; READ USING (C) FORM OF INPUT
+	;CALL	PC_SPACE	; *DEBUG*
+	;CALL	PRTHEXBYTE	; *DEBUG*
+	CP	$80		; CHECK FOR CORRECT VALUE
+	RET			; RETURN WITH ZF SET CORRECTLY
 ;
 ; UNIT INITIALIZATION
 ;

Source/HBIOS/hbios.asm

@@ -32,15 +32,17 @@
 ;   HBIOS APPLICATION BINARY.  THE APPENDED OS IMAGES ARE COPIED TO THE AUX RAM
 ;   BANK AND LAUNCHED AFTER HBIOS HAS INSTALLED ITSELF.
 ;
-;;;; - IMGBOOT: BOOT FROM AN IMAGE FILE THAT HAS BEEN PLACED IN THE USER BANK
-;;;;
-;;;;   WHEN IMGBOOT IS DEFINED, THE FILE IS ASSEMBLED SUCH THAT IT CAN BE PRELOADED
-;;;;   INTO THE RAM USER BANK BY AN EXTERNAL PROCESS THAT SUBSEQUENTLY LAUNCHES
-;;;;   THE CODE AT ADDRESS 0.  THE MOST COMMON EXAMPLE OF THIS IS THE UNA FSFAT
-;;;;   TOOL WHICH CAN LOAD AN IMAGE FROM A DOS FAT FILESYSTEM PROVIDING A SIMPLE
-;;;;   WAY TO LOAD A TEST COPY OF HBIOS.  AS IS THE CASE WITH APPBOOT, IT IS ASSUMED
-;;;;   THAT AN OS IMAGES FILE IS APPENDED TO THE END OF THE IMAGE AND IS LAUNCHED
-;;;;   AFTER HBIOS IS INSTALLED.
+; - IMGBOOT: BOOT FROM AN IMAGE FILE THAT HAS BEEN PLACED IN THE USER BANK
+;
+;   NOTE: THIS BOOT MODE IS DEPRECATED.
+;
+;   WHEN IMGBOOT IS DEFINED, THE FILE IS ASSEMBLED SUCH THAT IT CAN BE PRELOADED
+;   INTO THE RAM USER BANK BY AN EXTERNAL PROCESS THAT SUBSEQUENTLY LAUNCHES
+;   THE CODE AT ADDRESS 0.  THE MOST COMMON EXAMPLE OF THIS IS THE UNA FSFAT
+;   TOOL WHICH CAN LOAD AN IMAGE FROM A DOS FAT FILESYSTEM PROVIDING A SIMPLE
+;   WAY TO LOAD A TEST COPY OF HBIOS.  AS IS THE CASE WITH APPBOOT, IT IS ASSUMED
+;   THAT AN OS IMAGES FILE IS APPENDED TO THE END OF THE IMAGE AND IS LAUNCHED
+;   AFTER HBIOS IS INSTALLED.
 ;
 ; INCLUDE FILE NESTING:
 ;
@@ -102,11 +104,18 @@
 ;
 #DEFINE	HBIOS
 ;
+; INCLUDE GENERIC STUFF
+;
+#INCLUDE "std.asm"
+;
 ; MAKE SURE EXACTLY ONE OF ROMBOOT, APPBOOT, IMGBOOT IS DEFINED.
 ;
-MODCNT	.EQU	0
+MODCNT		.EQU	0
+BOOTMODE	.EQU	0
+;
 #IFDEF ROMBOOT
-MODCNT	.SET	MODCNT + 1
+BOOTMODE	.SET	BM_ROMBOOT
+MODCNT		.SET	MODCNT + 1
 ;
   #DEFINE BNKINFO
   #DEFINE MEMINFO
@@ -114,12 +123,17 @@ MODCNT	.SET	MODCNT + 1
   #DEFINE SYSINFO
 ;
 #ENDIF
+;
 #IFDEF APPBOOT
-MODCNT	.SET	MODCNT + 1
+BOOTMODE	.SET	BM_APPBOOT
+MODCNT		.SET	MODCNT + 1
 #ENDIF
-#IFDEF IMGBOOT
-MODCNT	.SET	MODCNT + 1
+;
+#IFDEF IMGBOOT		; *** DEPRECATED ***
+BOOTMODE	.SET	BM_IMGBOOT
+MODCNT		.SET	MODCNT + 1
 #ENDIF
+;
 #IF (MODCNT != 1)
 	.ECHO	"*** ERROR: PLEASE DEFINE ONE AND ONLY ONE OF ROMBOOT, APPBOOT, IMGBOOT!!!\n"
 	!!!	; FORCE AN ASSEMBLY ERROR
@@ -141,10 +155,6 @@ MODCNT	.SET	MODCNT + 1
   #DEFINE MEMECHO \;
 #ENDIF
 ;
-; INCLUDE GENERIC STUFF
-;
-#INCLUDE "std.asm"
-;
 SUPCTS	.EQU	FALSE		; SUPPRESS CTS DURING HBIOS BOOT
 ;
 ; HELPER MACROS
@@ -195,7 +205,8 @@ SUPCTS	.EQU	FALSE		; SUPPRESS CTS DURING HBIOS BOOT
   #ENDIF
   #IF (LEDMODE == LEDMODE_NABU)
     #DEFINE DIAG(N)	PUSH	AF
-    #DEFCONT \		LD	A,+((N << 3) & %00011000)
+    ;#DEFCONT \		LD	A,+((N << 3) & %00011000)
+    #DEFCONT \		LD	A,+((N << 3) & %00111000)
     #DEFCONT \		OUT	(LEDPORT),A
     #DEFCONT \		POP	AF
   #ENDIF
@@ -427,6 +438,7 @@ CB_CRTDEV	.DB	$FF		; PRIMARY CRT UNIT, $FF UNTIL AFTER HBIOS INIT
 CB_CONDEV	.DB	$FF		; CONSOLE UNIT, $FF UNTIL AFTER HBIOS INIT
 ;
 CB_DIAGLVL	.DB	DIAGLVL		; ROMWBW HBIOS DIAGNOSTIC LEVEL
+CB_BOOTMODE	.DB	BOOTMODE	; HBIOS BOOTMODE
 ;
 ; MEMORY MANAGEMENT VARIABLES START AT $20
 ;
@@ -497,6 +509,13 @@ HBX_IDENT:
 ;
 HBX_INVOKE:
 ;
+#IF (INTMODE == 0)
+	; IF SOMETHING IN USERLAND ENABLES INTERRUPTS AND WE ARE NOT
+	; CONFIGURED TO USE THEM, THEN SHUT THEM BACK OFF AGAIN FOR
+	; SAFETY.
+	DI
+#ENDIF
+;
 #IF (HBIOS_MUTEX == TRUE)
 	PUSH	HL			; SAVE HL
 	LD	HL,HB_LOCK		; POINT TO LOCK
@@ -596,11 +615,7 @@ HBX_ROM:
 	BIT	7,A			; BIT 7 SET REQUESTS RAM PAGE
 	JR	Z,HBX_ROM		; NOT SET, SELECT ROM PAGE
 	RES	7,A			; RAM PAGE REQUESTED: CLEAR ROM BIT
-  #IF (PLATFORM == PLT_DUO)
-	ADD	A,64			; ADD 64 x 32K - RAM STARTS FROM 2048K
-  #ELSE
-	ADD	A,16			; ADD 16 x 32K - RAM STARTS FROM 512K
-  #ENDIF
+	ADD	A,ROMSIZE / 32		; STARTING RAM BANK NUMBER OFFSET
 ;
 HBX_ROM:
 	RLCA				; TIMES 2 - GET 16K PAGE INSTEAD OF 32K
@@ -1037,26 +1052,26 @@ HBX_INTSTK	.EQU	$
 ;
 #ENDIF
 ;
-; HBIOS INTERRUPT SLOT ASSIGNMENTS
+; HBIOS INTERRUPT MODE 2 SLOT ASSIGNMENTS (SEE STD.ASM)
 ;
-; #	Z80		Z180
-; ---	--------------	--------------
-; 0	CTC0A		INT1 -+
-; 1	CTC0B		INT2  |
-; 2	CTC0C		TIM0  |
-; 3	CTC0D		TIM1  |
-; 4	UART0		DMA0  +- Z180 INTERNAL
-; 5	UART1		DMA1  |
-; 6			CSIO  |
-; 7	SIO0		SER0  |
-; 8	SIO1		SER1 -+
-; 9	PIO0A		PIO0A
-; 10	PIO0B		PIO0B
-; 11	PIO1A		PIO1A
-; 12	PIO1B		PIO1B
-; 13			SIO0
-; 14			SIO1
-; 15
+; #	Z80/Z280	Z180            MBC		DUO		NABU		
+; ---	--------------	--------------  --------------	--------------	--------------	
+; 0	CTC0A		INT1 -+               -+	      -+	HCCARCV -+	
+; 1	CTC0B		INT2  |                |	       |	HCCASND  |		
+; 2	CTC0C		TIM0  |                | IM2	       | IM2	NABUKB	 | IM2	
+; 3	CTC0D		TIM1  |                | INT	       | INT	VDP	 | INT		
+; 4	UART0		DMA0  | Z180	UART0  | VEC	UART0  | VEC	OPTCRD0  | VEC		
+; 5	UART1		DMA1  | CPU	UART1  | GEN	UART1  | GEN	OPTCRD1  | GEN		
+; 6			CSIO  |                |	       |	OPTCRD2  |		
+; 7	SIO0		SER0  |               -+	      -+	OPTCRD3 -+		
+; 8	SIO1		SER1 -+         SIO0		SIO0		
+; 9	PIO0A		PIO0A           SIO1		SIO1		
+; 10	PIO0B		PIO0B           PIO0A		PIO0A		
+; 11	PIO1A		PIO1A           PIO0B		PIO0B		
+; 12	PIO1B		PIO1B           CTC0A		CTC0A		
+; 13			SIO0            CTC0B		CTC0B		
+; 14			SIO1            CTC0C		CTC0C			
+; 15					CTC0D		CTC0D
 ;
 	; IVT MUST START AT PAGE BOUNDARY
 	ALIGN($100)
@@ -1155,13 +1170,6 @@ HBX_RETI:
 	PUSH	BC			; SAVE BC
 	PUSH	DE			; SAVE DE
 	PUSH	IY			; SAVE IY
-;
-#IF (PLATFORM == PLT_NABU)
-	PUSH	HL
-	LD	HL,($FFEA)		; TICCNT COPIED TO...
-	LD	($000B),HL		; ...LOW MEMORY FOR CP/M
-	POP	HL
-#ENDIF
 ;
 	LD	A,BID_BIOS		; HBIOS BANK
 	CALL	HBX_BNKSEL_INT		; SELECT IT
@@ -1341,13 +1349,26 @@ HB_START:
 	CALL	HB_APPBOOT		; PREPARE APP BOOT
 	RET	NZ			; RETURN ON ERROR
 ;
-HB_APPBOOT_Z:
-;
 #ENDIF
+;
+HB_RESTART:
 ;
 	DI				; NO INTERRUPTS
 	IM	1			; INTERRUPT MODE 1
 ;
+#IFDEF APPBOOT
+;
+	; IF THIS IS AN APPLICATION BOOT, WE CAPTURE THE CURRENT BANK ID
+	; AND UPDATE THE PROXY IMAGE.  LATER, WHEN THE PROXY IMAGE IS COPIED
+	; TO IT'S RUNNING LOCATION AT TOP OF RAM, THE CORRECT HB_CURBNK
+	; VALUE WILL BE INSTALLED. NOTE: THE ADDRESSES IN THE PROXY
+	; IMAGE ARE FOR IT'S RUNNING LOCATION, SO WE NEED TO USE *MATH*
+	; TO DERIVE THE LOCATION OF HB_CURBNK IN THE IMAGE.
+	LD	A,(HB_CURBNK)
+	LD	(HB_CURBNK - HBX_LOC + HBX_IMG),A
+;
+#ENDIF
+;
 #IF ((PLATFORM == PLT_DUO) & TRUE)
 	; THIS ARBITRARY DELAY SEEMS TO HELP DUODYNE CPU V1.0 SYSTEMS
 	; STARTUP CLEANLY.  DOUDYNE CPU V1.1 INTRODUCES A RESET
@@ -1460,11 +1481,11 @@ BOOTWAIT:
 	; LEFT ALONE.
 ;
 	; INITIALIZE ALL OF THE USER PAGE DESCRIPTORS WITH BLOCK MOVE
-#IFDEF APPBOOT
+    #IFDEF APPBOOT
 	LD	A,$08			; FIRST USER PDR IN HI MEM
-#ELSE
+    #ELSE
 	LD	A,$00			; FIRST USER PDR
-#ENDIF
+    #ENDIF
 	OUT	(Z280_MMUPDRPTR),A	; SET THE PDR POINTER
 	LD	HL,Z280_BOOTPDRTBL	; START OF PDR VALUES TABLE
 	LD	C,Z280_MMUBLKMOV	; PDR BLOCK MOVE PORT
@@ -1472,11 +1493,11 @@ BOOTWAIT:
 	OTIRW				; OTIRW PROGS PDRS SEQUENTIALLY
 ;
 	; INITIALIZE ALL OF THE SYSTEM PAGE DESCRIPTORS WITH BLOCK MOVE
-#IFDEF APPBOOT
+    #IFDEF APPBOOT
 	LD	A,$18			; FIRST SYSTEM PDR IN HI MEM
-#ELSE
+    #ELSE
 	LD	A,$10			; FIRST SYSTEM PDR
-#ENDIF
+    #ENDIF
 	OUT	(Z280_MMUPDRPTR),A	; SET THE PDR POINTER
 	LD	HL,Z280_BOOTPDRTBL	; START OF PDR VALUES TABLE
 	LD	C,Z280_MMUBLKMOV	; PDR BLOCK MOVE PORT
@@ -1493,7 +1514,7 @@ BOOTWAIT:
 	ALIGN(2)			; WORD ALIGN THE PDR TABLE
 ;
 Z280_BOOTPDRTBL:
-#IFNDEF APPBOOT
+    #IFNDEF APPBOOT
 	; LOWER 32 K (BANKED)
 	.DW	((Z2_BANK(BID_BOOT) + 0) << 4) | $A
 	.DW	((Z2_BANK(BID_BOOT) + 1) << 4) | $A
@@ -1503,7 +1524,7 @@ Z280_BOOTPDRTBL:
 	.DW	((Z2_BANK(BID_BOOT) + 5) << 4) | $A
 	.DW	((Z2_BANK(BID_BOOT) + 6) << 4) | $A
 	.DW	((Z2_BANK(BID_BOOT) + 7) << 4) | $A
-#ENDIF
+    #ENDIF
 	; UPPER 32 K (COMMON)
 	.DW	((Z2_BANK(BID_COM) + 0) << 4) | $A
 	.DW	((Z2_BANK(BID_COM) + 1) << 4) | $A
@@ -1683,7 +1704,8 @@ ROMRESUME:
   #ELSE
 	; NORMAL ZETA 2 SYSTEM HAS FIXED 512K OF RAM.  SETUP COMMON
 	; FOR TOP 32K OF THIS.
-	LD	A,64 - 2
+	;LD	A,64 - 2
+	LD	A,((ROMSIZE + RAMSIZE) / 16) - 2
   #ENDIF
 ;
 	OUT	(MPGSEL_2),A		; PROG THIRD 16K MMU REGISTER
@@ -1692,6 +1714,12 @@ ROMRESUME:
 	; ENABLE PAGING
 	LD	A,1
 	OUT	(MPGENA),A		; ENABLE MMU NOW
+;
+  #IF (PLATFORM == PLT_FZ80)
+	; REMOVE FPGA ROM MONITOR FROM THE CPU ADDRESS SPACE
+	LD	A,%00000010
+	OUT	($07),A
+  #ENDIF
 #ENDIF
 ;
 ;--------------------------------------------------------------------------------------------------
@@ -2012,6 +2040,41 @@ CB_IDS:	LD	(HL),A				; POPULATE CB_BIDCOM
 	LD	(RTC_DISPACT),A		; RTC DEVICE
 	LD	(DSKY_DISPACT),A	; DSKY DEVICE
 ;
+; CLEAR INTERRUPT VECTOR TABLES
+;
+; THIS IS REALLY ONLY REQUIRED ON A RESTART, BUT IT DOESN'T HURT TO
+; DO IT ALL THE TIME.
+;
+	LD	HL,HB_IVT + 1		; FIRST VECTOR (IM2)
+	LD	B,16			; CLEAR 16 VECTORS
+	CALL	HB_CLRIVT		; DO IT
+	LD	HL,HB_IM1INT + 1	; FIRST VECTOR (IM1)
+	LD	B,8			; CLEAR 8 VECTORS
+	CALL	HB_CLRIVT		; DO IT
+	XOR	A			; ZERO ACCUM
+	LD	(HB_IM1CNT),A		; ... TO CLEAR IM1 VECTOR CNT
+	LD	HL,HB_IM1INT		; POINTER TO START OF IM1 IVT
+	LD	(HB_IM1PTR),HL		; ... TO CLEAR IM1 PTR
+	
+	LD	HL,HB_TICK
+	LD	(VEC_TICK + 1),HL
+	LD	HL,HB_SECOND
+	LD	(VEC_SECOND + 1),HL
+	
+	JR	HB_CLRIVT_Z		; DONE, JUMP OVER SUBROUTINE
+;
+HB_CLRIVT:
+	LD	(HL),HB_BADINT & $FF
+	INC	HL
+	LD	(HL),HB_BADINT >> 8
+	INC	HL
+	INC	HL
+	INC	HL
+	DJNZ	HB_CLRIVT
+	RET
+;
+HB_CLRIVT_Z:
+;
 ; INITIALIZE HEAP STORAGE
 ;
 	; INITIALIZE POINTERS
@@ -2707,34 +2770,6 @@ NXTMIO:	LD	A,(HL)
 NOT_REC_M2:
 ;
 	FPLEDS(DIAG_08)
-
-#IF (PLATFORM == PLT_NABU) & TRUE
-;
-	; GET CURRENT VALUE OF PSG ENABLE REGISTER
-	LD	A,7
-	OUT	(NABU_RSEL),A
-	NOP
-	IN	A,(NABU_RDAT)
-	LD	B,A
-;
-	; GET CURRENT VALUE OF PSG ENABLE REGISTER
-	LD	A,7
-	OUT	(NABU_RSEL),A
-	NOP
-	IN	A,(NABU_RDAT)
-	LD	C,A
-;
-	; DUMP IT
-	CALL	PC_ASTERISK
-	LD	A,B
-	CALL	PRTHEXBYTE
-	LD	A,C
-	CALL	PRTHEXBYTE
-	CALL	PC_ASTERISK
-;
-#ENDIF
-
-
 ;
 ;--------------------------------------------------------------------------------------------------
 ; IO PORT SCAN
@@ -2987,6 +3022,11 @@ HB_Z280BUS1:
 	LDCTL	HL,(C)
 	CALL	PRTHEXWORDHL
 	CALL	PC_SPACE
+	PRTS("ISR=$")
+	LD	C,Z280_ISR		; INTERRUPT STATUS REGISTER
+	LDCTL	HL,(C)
+	CALL	PRTHEXWORDHL
+	CALL	PC_SPACE
 	PRTS("BTCR=$")
 	LD	C,Z280_BTCR		; BUS TIMING AND CONTROL REGISTER
 	LDCTL	HL,(C)
@@ -3216,6 +3256,12 @@ HB_WDZ:
 	AND	%00000001		; ISOLATE CONSOLE BIT
 	JR	NZ,INITSYS3		; NOT SET, BYPASS CONSOLE SWITCH
   #ENDIF
+;
+  #IF (PLATFORM == PLT_FZ80)
+	IN	A,($36)			; GET IO BYTE
+	AND	%00000001		; ISOLATE CONSOLE BIT
+	JR	Z,INITSYS3		; NOT SET, BYPASS CONSOLE SWITCH
+  #ENDIF
 ;
 	LD	A,(CB_CRTDEV)		; GET CRT DISPLAY DEVICE
 	LD	(HB_NEWCON),A		; AND QUEUE TO SWITCH
@@ -3527,6 +3573,9 @@ HB_INITRLEN	.EQU	(($ - HB_INIT_REC) / 2)
 ;
 HB_PCINITTBL:
 ;
+#IF (SSERENABLE)
+	.DW	SSER_PREINIT
+#ENDIF
 #IF (ASCIENABLE)
 	.DW	ASCI_PREINIT
 #ENDIF
@@ -3605,6 +3654,9 @@ HB_INITTBL:
 #IF (SPKENABLE)
 	.DW	SP_INIT			; AUDIBLE INDICATOR OF BOOT START
 #ENDIF
+#IF (SSERENABLE)
+	.DW	SSER_INIT
+#ENDIF
 #IF (ASCIENABLE)
 	.DW	ASCI_INIT
 #ENDIF
@@ -4538,31 +4590,38 @@ SYS_RESWARM:
 ;
 SYS_RESCOLD:
 ;
-#IF (MEMMGR == MM_Z280)
+#IFDEF APPBOOT
+	JP	HB_RESTART
+#ELSE
+;
+; MAKE ROM BOOT BANK ACTIVE IN LOW SYS MEM
+;
+  #IF (MEMMGR == MM_Z280)
 	; FOR Z280, NEED TO REMAP THE LOW 32K IN SYSTEM MODE AND
 	; CONTINUE AT ADDRESS ZERO.  WE CANNOT RETURN HERE AFTER THE
 	; BNKSEL IS DONE BECAUSE THE SYSTEM BANK HAS BEEN CHANGED!
-	; SO, WE PRESET THE STACK TO CAUSE A JUMP TO ADDRESS ZERO
-	; ON RETURN FROM THE BNKSEL.  SLICK, RIGHT?
+	; SO, WE PRESET THE STACK TO CAUSE A JUMP TO THE RESTART
+	; ADDRESS ON RETURN FROM THE BNKSEL.  SLICK, RIGHT?
 	DI				; KILL INTERRUPTS
 	LD	SP,HBX_LOC		; STACK IN HIGH MEMORY
-	LD	HL,0			; VALUE TO RESUME
+	LD	HL,HB_RESTART		; RESUME AT RESTART ADDRESS
 	PUSH	HL			; ... IS PRESET ON STACK
-;
-	; MAKE ROM BOOT BANK ACTIVE IN LOW SYS MEM
-	LD	A,BID_BOOT		; BOOT BANK
+	LD	A,BID_BOOT		; BANK TO LAUNCH RESTART
 	LD	B,$10			; FIRST SYS PDR
 	JP	Z280_BNKSEL		; DO IT AND RESUME FROM STACK
-#ELSE
+  #ELSE
+	; FOR OTHER THAN Z280, JUST DO AN INTERBANK CALL TO THE
+	; RESTART ADDRESS.
 	DI
 	LD	SP,HBX_LOC		; STACK JUST BELOW HBIOS PROXY
-	LD	A,BID_BOOT		; BOOT BANK
-	LD	IX,0			; ADDRESS ZERO
+	LD	A,BID_BOOT		; BANK TO LAUNCH RESTART
+	LD	IX,HB_RESTART		; RESUME AT RESTART ADDRESS
 	CALL	HB_BNKCALL		; DOES NOT RETURN
+  #ENDIF
 #ENDIF
 ;
 ; HOOK CALLED WHEN A USERLAND RESET IS INVOKED, TYPICALLY VIA A JUMP
-; TO LOGICAL CPU ADDRESS $0000
+; TO CPU ADDRESS $0000
 ;
 ; CREDIT TO PHILLIP STEVENS FOR SUGGESTING AND SIGNIFICANT CONTRIBUTIONS
 ; TO THE Z180 INVALID OPCODE TRAP ENHANCEMENT.
@@ -5541,7 +5600,7 @@ SYS_INTINFO:
 	LD	A,(HB_IM1CNT)		; RETURN IM1 CALL LIST SIZE
 	LD	E,A
 #ENDIF
-#IF (INTMODE == 2)
+#IF ((INTMODE == 2) | (INTMODE == 3))
 	LD	E,HBX_IVTCNT		; RETURN INT VEC TABLE SIZE
 #ENDIF
 	XOR	A			; INDICATE SUCCESS
@@ -5560,7 +5619,7 @@ SYS_INTVECADR:
 	INC	A			; ALLOW FOR EXTRA ENTRY TO APPEND AT END
 	LD	C,A			; SAVE IN C FOR COMPARE
 #ENDIF
-#IF (INTMODE == 2)
+#IF ((INTMODE == 2) | (INTMODE == 3))
 	LD	C,HBX_IVTCNT		; GET CURRENT ENTRY COUNT
 #ENDIF
 	LD	A,E			; INCOMING INDEX POSITION TO A
@@ -5578,7 +5637,7 @@ SYS_INTGET1:
 #IF (INTMODE == 1)
 	LD	DE,HB_IM1INT		; DE := START OF VECTOR TABLE
 #ENDIF
-#IF (INTMODE == 2)
+#IF ((INTMODE == 2) | (INTMODE == 3))
 	LD	DE,HB_IVT		; DE := START OF VECTOR TABLE
 #ENDIF
 	ADD	HL,DE			; HL := ADR OF VECTOR
@@ -6026,9 +6085,9 @@ HB_TIMDBG1:
 ; THESE CAN BE HOOKED AS DESIRED BY DRIVERS
 ;
 VEC_TICK:
-	JP	HB_TICK			; TICK PROCESSING VECTOR
+	JP	HB_TICK			; TICKS PROCESSING VECTOR
 VEC_SECOND:
-	JP	HB_SECOND		; SECOND PROCESSING VECTOR
+	JP	HB_SECOND		; SECONDS PROCESSING VECTOR
 ;
 ; TIMER HANDLERS
 ;
@@ -7756,6 +7815,8 @@ PS_SDLPT	.TEXT	"LPT$"
 PS_SDESPCON	.TEXT	"ESPCON$"
 PS_SDESPSER	.TEXT	"ESPSER$"
 PS_SDSCON	.TEXT	"SCON$"
+PS_SDEF		.TEXT	"EF$"
+PS_SDSSER	.TEXT	"SSER$"
 ;
 ; CHARACTER SUB TYPE STRINGS
 ;
@@ -7918,6 +7979,16 @@ SIZ_RP5RTC	.EQU	$ - ORG_RP5RTC
 		MEMECHO	SIZ_RP5RTC
 		MEMECHO	" bytes.\n"
 #ENDIF
+;
+#IF (SSERENABLE)
+ORG_SSER	.EQU	$
+  #INCLUDE "sser.asm"
+SIZ_SSER	.EQU	$ - ORG_SSER
+		MEMECHO	"SSER occupies "
+		MEMECHO	SIZ_SSER
+		MEMECHO	" bytes.\n"
+#ENDIF
+;
 #IF (ASCIENABLE)
 ORG_ASCI	.EQU	$
   #INCLUDE "asci.asm"
@@ -8484,15 +8555,6 @@ STR_APPBOOT	.DB	"\r\n\r\n*** Launching RomWBW HBIOS v", BIOSVER, ", ", TIMESTAMP
 		.DB	"\r\n\r\n    ", PLATFORM_NAME, "$"
 ;
 HB_APPBOOT2:
-	; IF THIS IS AN APPLICATION BOOT, WE CAPTURE THE CURRENT BANK ID
-	; AND UPDATE THE PROXY IMAGE.  LATER, WHEN THE PROXY IMAGE IS COPIED
-	; TO IT'S RUNNING LOCATION AT TOP OF RAM, THE CORRECT HB_CURBNK
-	; VALUE WILL BE INSTALLED. NOTE: THE ADDRESSES IN THE PROXY
-	; IMAGE ARE FOR IT'S RUNNING LOCATION.  WE NEED TO USE *MATH*
-	; TO DERIVE THE LOCATION OF HB_CURBNK IN THE IMAGE.
-	LD	A,(HB_CURBNK)
-	LD	(HB_CURBNK - HBX_LOC + HBX_IMG),A
-;
 	; FOR AN APPLICATION BOOT, WE ALSO COPY THE CONCATENATED OS
 	; IMAGES TO THE AUX BANK WHERE WE WILL JUMP TO ROMLDR LATER.
 	; THE AUX BANK WILL BE DESTROYED IF CP/M 3 IS LOADED.  WE DON'T
@@ -8512,12 +8574,15 @@ HB_APPBOOT2:
 	; WE NEED TO SWITCH FROM USER MODE TO SYSTEM MODE, BUT CONTINUE
 	; RUNNING IN THE CURRENT BANK.  THIS IS A LITTLE MESSY.
 ;
-	; FIRST, OVERLAY PROXY CODE WITH NEW CODE SO WE CAN USE THE
+	; FIRST, OVERLAY PROXY CODE WITH FRESH CODE SO WE CAN USE THE
 	; PROXY ROUTINES SAFELY.
+	
+	LD	A,(HB_CURBNK)		; GET CURBNK
 	LD	DE,HBX_LOC		; RUNNING LOCATION
 	LD	HL,HBX_IMG		; LOCATION IN IMAGE
 	LD	BC,HBX_SIZ		; SIZE
 	LDIR				; INSTALL IT
+	LD	(HB_CURBNK),A		; RESTORE CURBNK
 ;
 	; NEXT, COPY A BIT OF CODE TO DO THE SYSTEM TRANSITION TO
 	; UPPER MEM. WE CAN BORROW THE PROXY BOUNCE BUFFER FOR THIS.
@@ -8541,7 +8606,7 @@ Z280_GOSYS:
 	LD	A,(HB_CURBNK)		; CURRENT BANK
 	LD	B,$10			; FIRST SYSTEM PDR
 	CALL	Z280_BNKSEL		; DO THE SWITCH
-	JP	HB_APPBOOT_Z		; AND RESUME BOOT
+	JP	HB_RESTART		; AND RESUME BOOT
 ;
 Z280_GOSYS_LEN	.EQU	$ - Z280_GOSYS
 ;

Source/HBIOS/hbios.inc

@@ -158,24 +158,25 @@ PLT_EPITX	.EQU	19		; Z180 MINI-ITX
 PLT_MON		.EQU	20		; MONSPUTER
 PLT_STDZ180	.EQU	21		; GENESIS Z180 SYSTEM
 PLT_NABU	.EQU	22		; NABU PERSONAL COMPUTER
+PLT_FZ80	.EQU	23		; S100 FPGA Z80
 ;
 ; HBIOS GLOBAL ERROR RETURN VALUES
 ;
-ERR_NONE		.EQU	0	; SUCCESS
-;
-ERR_UNDEF		.EQU	-1	; UNDEFINED ERROR
-ERR_NOTIMPL		.EQU	-2	; FUNCTION NOT IMPLEMENTED
-ERR_NOFUNC		.EQU	-3	; INVALID FUNCTION
-ERR_NOUNIT		.EQU	-4	; INVALID UNIT NUMBER
-ERR_NOMEM		.EQU	-5	; OUT OF MEMORY
-ERR_RANGE		.EQU	-6	; PARAMETER OUT OF RANGE
-ERR_NOMEDIA		.EQU	-7	; MEDIA NOT PRESENT
-ERR_NOHW		.EQU	-8	; HARDWARE NOT PRESENT
-ERR_IO			.EQU	-9	; I/O ERROR
-ERR_READONLY		.EQU	-10	; WRITE REQUEST TO READ-ONLY MEDIA
-ERR_TIMEOUT		.EQU	-11	; DEVICE TIMEOUT
-ERR_BADCFG		.EQU	-12	; INVALID CONFIGURATION
-ERR_INTERNAL		.EQU	-13	; INTERNAL ERROR
+ERR_NONE	.EQU	0		; SUCCESS
+;	
+ERR_UNDEF	.EQU	-1		; UNDEFINED ERROR
+ERR_NOTIMPL	.EQU	-2		; FUNCTION NOT IMPLEMENTED
+ERR_NOFUNC	.EQU	-3		; INVALID FUNCTION
+ERR_NOUNIT	.EQU	-4		; INVALID UNIT NUMBER
+ERR_NOMEM	.EQU	-5		; OUT OF MEMORY
+ERR_RANGE	.EQU	-6		; PARAMETER OUT OF RANGE
+ERR_NOMEDIA	.EQU	-7		; MEDIA NOT PRESENT
+ERR_NOHW	.EQU	-8		; HARDWARE NOT PRESENT
+ERR_IO		.EQU	-9		; I/O ERROR
+ERR_READONLY	.EQU	-10		; WRITE REQUEST TO READ-ONLY MEDIA
+ERR_TIMEOUT	.EQU	-11		; DEVICE TIMEOUT
+ERR_BADCFG	.EQU	-12		; INVALID CONFIGURATION
+ERR_INTERNAL	.EQU	-13		; INTERNAL ERROR
 ;
 ; HBIOS DIAG OPTIONS
 ;
@@ -323,6 +324,7 @@ CIODEV_ESPCON	.EQU	$0C
 CIODEV_ESPSER	.EQU	$0D
 CIODEV_SCON	.EQU	$0E
 CIODEV_EF	.EQU	$0F
+CIODEV_SSER	.EQU	$10
 ;
 ; SUB TYPES OF CHAR DEVICES
 ;
@@ -432,6 +434,7 @@ HCB_SERDEV	.EQU	$10		; PRIMARY SERIAL DEVICE/UNIT (BYTE)
 HCB_CRTDEV	.EQU	$11		; CRT DISPLAY DEVICE/UNIT (BYTE)
 HCB_CONDEV	.EQU	$12		; ACTIVE CONSOLE DEVICE/UNIT (BYTE)
 HCB_DIAGLVL	.EQU	$13		; HBIOS DIAGNOSTIC LEVEL (BYTE)
+HCB_BOOTMODE	.EQU	$14		; HBIOS BOOTMODE (BYTE)
 ;
 HCB_HEAP	.EQU	$20		; DWORD ADDRESS OF START OF HEAP
 HCB_HEAPTOP	.EQU	$22		; DWORD ADDRESS OF TOP OF HEAP

Source/HBIOS/nabu.asm

@@ -1,15 +1,12 @@
 ;
 ;==================================================================================================
-; NABU INTERRUPT INTERCEPTOR
+; NABU HARDWARE DRIVER
 ;==================================================================================================
 ;
-NABU_INT1CLR	.EQU	$68
-NABU_TICCNT	.EQU	$FFEA		; TICCNT AT $FFEA IS COPIED DOWN TO $000B
-;
 ; NABU INTERRUPT ENABLE PORT AND STATUS PORTS ARE MANAGED BY THE
 ; PSG IO PORTS.
 ;
-; INTERRUPT ENABLE (OUTPUT) - PSG PORT A
+; NABU CONTROL PORT - INTERRUPT ENABLE (OUTPUT) - PSG PORT A
 ;
 ;	D7 - HCCA Receive
 ;	D6 - HCCA Send
@@ -20,7 +17,13 @@ NABU_TICCNT	.EQU	$FFEA		; TICCNT AT $FFEA IS COPIED DOWN TO $000B
 ;	D1 - Option Card 2 (J11)
 ;	DO - Option Card 3 (J12)
 ;
-; STATUS BYTE (INPUT) - PSG PORT B
+; THE CONTROL PORT IS WRITE ONLY AND THE BITS NEED TO BE MANAGED IN
+; MULTIPLE DRIVERS.  BELOW, WE ALLOCATE NBAU_CTLVAL AS A SHADOW
+; REGISTER FOR THE CONTROL PORT.  IT IS INITIALIZED TO ZERO HERE
+; (ALL INTS DISABLED).  THE INDIVIDUAL BITS ARE SET AS APPROPIATE IN
+; THE DRIVERS THAT WANT THE INTERRUPTS ENABLED (NABUKB, TMS).
+;
+; NABU STATUS PORT - STATUS BYTE (INPUT) - PSG PORT B
 ;
 ;	D7 - N.C.
 ;	D6 - Overrun Error (HCCA UART)
@@ -33,91 +36,54 @@ NABU_TICCNT	.EQU	$FFEA		; TICCNT AT $FFEA IS COPIED DOWN TO $000B
 ;
 ; PORTS TO MANAGE PSG
 ;
-NABU_RSEL	.EQU	$41		; SELECT PSG REGISTER
-NABU_RDAT	.EQU	$40		; WRITE TO SELECTED REGISTER
-NABU_RIN	.EQU	$40		; READ FROM SELECTED REGISTER
+NABU_BASE	.EQU	$40		; BASE PORT FOR NABU PSG
+NABU_RSEL	.EQU	NABU_BASE + 1	; SELECT PSG REGISTER
+NABU_RDAT	.EQU	NABU_BASE + 0	; WRITE TO SELECTED REGISTER
+NABU_RIN	.EQU	NABU_BASE + 0	; READ FROM SELECTED REGISTER
 ;
 	DEVECHO	"NABU: IO="
-	DEVECHO	NABU_INT1CLR
+	DEVECHO	NABU_BASE
 	DEVECHO	"\n"
 ;
-;
 ; HARDWARE RESET PRIOR TO ROMWBW CONSOLE INITIALIZATION
 ;
 NABU_PREINIT:
+;
+	; RESET SHADOW REGISTER IN CASE WE ARE DOING AN HBIOS
+	; RESTART IN PLACE
+	XOR	A			; ALL INTERRUPTS DISABLED
+	LD	(NABU_CTLVAL),A		; SAVE IT
+;
 	; INITIALIZE THE NABU PSG I/O PORTS
-	; PORT A IN WRITE MODE AND SET ALL BITS TO ZERO
-	; PORT B IN READ MODE
+	; PORT A (CONTROL PORT) IN WRITE MODE
+	; PORT B (STATUS PORT) IN READ MODE
+	; INITIALIZE THE CONTROL REGISTER
 ;
-	CALL	NABU_SETPSG	
-;
-;#IF (INTMODE == 1)
-;	; ADD TO INTERRUPT CHAIN
-;	LD	HL,NABU_STAT
-;	CALL	HB_ADDIM1		; ADD TO IM1 CALL LIST
-;#ENDIF
-;
-;#IF (INTMODE == 2)
-;	LD	HL,NABU_STAT
-;	LD	(IVT(INT_NABUKB)),HL	; IVT INDEX
-;#ENDIF
-;	RET
-;
-NABU_INIT:
-	CALL	NEWLINE			; FORMATTING
-	PRTS("NABU: INT1$")
-;	XOR	A
-;	OUT	(NABU_INT1CLR),A
-	RET				; DONE
-;
-NABU_SETPSG:
 	; SET I/O PORT MODES
 	LD	A,7			; PSG R7 (ENABLE REG)
 	OUT	(NABU_RSEL),A		; SELECT IT
-	LD	A,%01111111		; PORT B INPUT, PORT A OUPUT
+	LD	A,%01111111		; PORT B INPUT, PORT A OUPUT, AUDIO CHANNELS DISABLED
 	OUT	(NABU_RDAT),A		; SET IT
 ;
-	; SET PORT A TO VALUE 0
+	; INITIALIZE PORT A VALUE
 	LD	A,14			; PSG R14 (PORT A DATA)
 	OUT	(NABU_RSEL),A		; SELECT IT
-#IF (INTMODE > 0)
-  #IF (TMSTIMENABLE == TRUE)
-	LD	A,%00110000		; ENABLE NABU KB & VDP INTS
-  #ELSE
-	LD	A,%00100000		; ENABLE NABU KB INTS
-  #ENDIF
-#ELSE
-	XOR	A
-#ENDIF
-	OUT	(NABU_RDAT),A		; SET IT
+	LD	A,(NABU_CTLVAL)		; GET CTL VALUE SHADOW REG
+	OUT	(NABU_RDAT),A		; WRITE TO HARDWARE
 ;
-	LD	A,15
-	OUT	(NABU_RSEL),A
-	IN	A,(NABU_RIN)
-	RET
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
 ;
-;  INTERRUPT ENTRY POINT
+; POST CONSOLE INITIALIZATION
 ;
-NABU_STAT:
-;	CALL	NABU_SETPSG
-;	XOR	A
-;	OUT	(NABU_INT1CLR),A	; CLEAR THE INTERRUPT
-	LD	HL,(NABU_TICCNT)	; INCREMENT NABU TICK COUNTER
-	
-	
-	INC	HL			; ... IN HBIOS PROXY
-	LD	(NABU_TICCNT),HL
-;	LD	A,(NABU_HBTICK)		; INCREMENT INTERNAL TICK CTR
-;	INC	A
-;	LD	(NABU_HBTICK),A
-;	CP	$0A			; CALL HB_TICK EVERY 10 INTERRUPTS (50HZ)
-;	RET	NZ			; NOT TIME THEN JUST RETURN
-	CALL	HB_TICK			; DO NORMAL HBIOS TICK
-	XOR	A
-;	LD	(NABU_HBTICK),A		; RESET HBTICK COUNTER
-	INC	A			; INTERRUPT HANDLED
-	RET
+NABU_INIT:
+	CALL	NEWLINE			; FORMATTING
+	PRTS("NABU: IO=$")
+	LD	A,NABU_BASE
+	CALL	PRTHEXBYTE
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
 ;
-NABU_HBTICK:
-	.DB	0			; INTERNAL TICK CTR
+; DATA STORAGE
 ;
+NABU_CTLVAL	.DB	0		; SHADOW VAL FOR NABU CONTROL REGISTER

Source/HBIOS/nabukb.asm

@@ -21,52 +21,16 @@
 ; WILL TRANSLATE SPECIAL KEYS ($E0-$FF) TO ROMWBW EQUIVALENTS.  ALL
 ; OTHER KEYS WILL BE PASSED THROUGH AS IS.
 ;
-; KBPORT EQU	$90
-;
-; POLL FOR INPUT
-; KBLOOP:
-;	IN	A,(KBPORT+1)
-;	BIT	1,A    
-;	JR	Z,KBLOOP
-;	IN	A,(KBPORT)
-;
-; INIT:
-;	XOR	A
-;	CALL	SUB12
-;	CALL	SUB12
-;	CALL	SUB12
-;	CALL	SUB12
-;	CALL	SUB12
-;	LD	A,40H
-;	CALL	SUB12
-;	LD	A,4EH
-;	CALL	SUB12
-;	LD	A,04H
-;	CALL	SUB12
-;
 NABUKB_IODAT	.EQU	$90		; KEYBOARD DATA (READ)
 NABUKB_IOSTAT	.EQU	$91		; STATUS (READ), CMD (WRITE)
+;
+;
+NABUKB_BUFSZ	.EQU	16		; RECEIVE RING BUFFER SIZE
 ;
 	DEVECHO	"NABUKB: IO="
 	DEVECHO	NABUKB_IODAT
 	DEVECHO	"\n"
 ;
-; SETUP INTERRUPT HANDLING, IF ENABLED
-;
-NABUKB_PREINIT:
-#IF (INTMODE == 1)
-	; ADD TO INTERRUPT CHAIN
-	LD	HL,NABUKB_INT
-	CALL	HB_ADDIM1		; ADD TO IM1 CALL LIST
-#ENDIF
-;
-#IF (INTMODE == 2)
-	; INSTALL VECTOR
-	LD	HL,NABUKB_INT
-	LD	(IVT(INT_NABUKB)),HL	; IVT INDEX
-#ENDIF
-	RET
-;
 ; INITIALZIZE THE KEYBOARD CONTROLLER.
 ;
 NABUKB_INIT:
@@ -87,6 +51,28 @@ NABUKB_INIT:
 	CALL	NABUKB_PUT
 	LD	A,$04		; ENABLE RECV
 	CALL	NABUKB_PUT
+;
+#IF (INTMODE == 1)
+	; ADD TO INTERRUPT CHAIN
+	LD	HL,NABUKB_INT
+	CALL	HB_ADDIM1		; ADD TO IM1 CALL LIST
+#ENDIF
+;
+#IF (INTMODE == 2)
+	; INSTALL VECTOR
+	LD	HL,NABUKB_INT
+	LD	(IVT(INT_NABUKB)),HL	; IVT INDEX
+#ENDIF
+;
+#IF (INTMODE > 0)
+	; ENABLE KEYBOARD INTERRUPTS ON NABU INTERRUPT CONTROLLER
+	LD	A,14			; PSG R14 (PORT A DATA)
+	OUT	(NABU_RSEL),A		; SELECT IT
+	LD	A,(NABU_CTLVAL)		; GET NABU CTL PORT SHADOW REG
+	SET	5,A			; ENABLE VDP INTERRUPTS
+	LD	(NABU_CTLVAL),A		; UPDATE SHADOW REG
+	OUT	(NABU_RDAT),A		; WRITE TO HARDWARE
+#ENDIF
 ;
 	XOR	A
 	RET
@@ -105,96 +91,149 @@ NABUKB_INT:
 ;
 	;CALL	PC_LT			; *DEBUG*
 	IN	A,(NABUKB_IODAT)	; GET THE KEY
-	LD	E,A			; STASH IN REG E
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	;CALL	PC_COMMA		; *DEBUG*
+	CALL	NABUKB_XB		; TRANSLATE THE KEY
 	;CALL	PRTHEXBYTE		; *DEBUG*
 	;CALL	PC_GT			; *DEBUG*
-;
-	LD	A,(NABUKB_KSTAT)	; GET KEY BUFFER STAT
-	OR	A			; SET FLAGS
-	RET	NZ			; BUFFER FULL, BAIL OUT W/ NZ (INT HANDLED), KEY DISCARDED
-;
-	LD	A,E			; RECOVER THE KEY CODE
-	CALL	NABUKB_XB		; TRANSLATE AND BUFFER KEY
-	OR	$FF			; SIGNAL INT HANDLED
-	RET				; DONE
+	JR	C,NABUKB_INTRCV4	; ABORT IF UNUSABLE KEY
+	LD	B,A			; SAVE BYTE READ
+	LD	HL,NABUKB_RCVBUF	; SET HL TO START OF BUF STRUCT
+	LD	A,(HL)			; GET COUNT
+	CP	NABUKB_BUFSZ		; COMPARE TO BUFFER SIZE
+	JR	Z,NABUKB_INTRCV4	; BAIL OUT IF BUFFER FULL, RCV BYTE DISCARDED
+	INC	A			; INCREMENT THE COUNT
+	LD	(HL),A			; AND SAVE IT
+	INC	HL			; HL NOW HAS ADR OF HEAD PTR
+	PUSH	HL			; SAVE ADR OF HEAD PTR
+	LD	A,(HL)			; DEREFERENCE HL
+	INC	HL
+	LD	H,(HL)
+	LD	L,A			; HL IS NOW ACTUAL HEAD PTR
+	LD	(HL),B			; SAVE CHARACTER RECEIVED IN BUFFER AT HEAD
+	INC	HL			; BUMP HEAD POINTER
+	POP	DE			; RECOVER ADR OF HEAD PTR
+	LD	A,L			; GET LOW BYTE OF HEAD PTR
+	SUB	NABUKB_BUFSZ+4		; SUBTRACT SIZE OF BUFFER AND POINTER
+	CP	E			; IF EQUAL TO START, HEAD PTR IS PAST BUF END
+	JR	NZ,NABUKB_INTRCV3	; IF NOT, BYPASS
+	LD	H,D			; SET HL TO
+	LD	L,E			; ... HEAD PTR ADR
+	INC	HL			; BUMP PAST HEAD PTR
+	INC	HL
+	INC	HL
+	INC	HL			; ... SO HL NOW HAS ADR OF ACTUAL BUFFER START
+NABUKB_INTRCV3:
+	EX	DE,HL			; DE := HEAD PTR VAL, HL := ADR OF HEAD PTR
+	LD	(HL),E			; SAVE UPDATED HEAD PTR
+	INC	HL
+	LD	(HL),D
+NABUKB_INTRCV4:
+	OR	$FF			; NZ SET TO INDICATE INT HANDLED
+	RET				; AND RETURN
 ;
 #ENDIF
 ;
 ; NORMAL HBIOS CHAR INPUT STATUS.  IF INTERRUPTS ARE NOT ACTIVE, THEN
 ; KEYBOARD POLLING IS IMPLEMENTED HERE.
 ;
+#IF (INTMODE == 0)
 NABUKB_STAT:
 	LD	A,(NABUKB_KSTAT)	; GET KEY WAITING STATUS
 	OR	A			; SET FLAGS
-#IF (INTMODE > 0)
-	JR	Z,NABUKB_STATX		; BAIL OUT W/ Z (NO KEY)
-	RET				; KEY WAITING, ALL SET
-#ELSE
 	RET	NZ			; KEY WAITING, ALL SET
 	IN	A,(NABUKB_IOSTAT)	; GET KBD STATUS
 	AND	$02			; CHECK DATA RDY BIT
 	JR	Z,NABUKB_STATX		; BAIL OUT W/ Z (NO KEY)
 	IN	A,(NABUKB_IODAT)	; GET THE KEY
-	CALL	NABUKB_XB		; TRANSLATE AND BUFFER KEY
-	LD	A,(NABUKB_KSTAT)	; GET NEW KEY WAITING STATUS
+	CALL	NABUKB_XB		; TRANSLATE/FILTER
+	JR	C,NABUKB_STATX		; IF CF SET, IGNORE
+	LD	(NABUKB_KEY),A		; BUFFER IT
+	LD	A,1			; SIGNAL KEY WAITING
+	LD	(NABUKB_KSTAT),A	; SAVE IT
 	OR	A			; SET FLAGS
 	RET				; DONE
-#ENDIF
 ;
 NABUKB_STATX:
 	XOR	A			; SIGNAL NO CHAR READY
 	JP	CIO_IDLE		; RETURN VIA IDLE PROCESSOR
 ;
-; ROUTINE TO TRANSLATE AND BUFFER INCOMING NABU KEYBOARD KEYCODES
+#ELSE
+NABUKB_STAT:
+	LD	A,(NABUKB_BUFCNT)	; GET BUFFER UTILIZATION COUNT
+	OR	A			; SET FLAGS
+	JP	Z,CIO_IDLE		; NOT READY, RETURN VIA IDLE PROCESSING
+	RET				; DONE
+#ENDIF
+;
+; ROUTINE TO FILTER AND TRANSLATE INCOMING NABU KEYBOARD KEYCODES
+; ENTER WITH RAW KEY CODE IN A
+; RESULT IN A, CF SET IF THE KEY SHOULD BE DISCARDED
 ;
 NABUKB_XB:
+	; $00 - $7F ARE NORMAL ASCII CHARS (PASS THROUGH)
 	BIT	7,A			; HIGH BIT IS SPECIAL CHAR
-	JR	Z,NABUKB_XB2		; IF NORMAL CHAR, BUFFER IT
-	CP	$90			; START OF ERR CODES
-	JR	C,NABUKB_XB1		; NOT ERR CODE, CONTINUE
+	JR	Z,NABUKB_XB2		; IF NORMAL CHAR, RETURN W/ CF CLEAR
+	; $80-$8F ARE JOSYSTICK PREFIXES (PASS THESE THROUGH)
+	CP	$90			; END OF JOYSTICK PREFIXES
+	JR	C,NABUKB_XB2		; IF JOY PRE, RETURN W/ CF CLEAR
+	; $90-$9F ARE KEYBOARD ERROR CODES (IGNORE THESE)
 	CP	$A0			; END OF ERR CODES
-	JR	NC,NABUKB_XB1		; NOT ERR CODE, CONTINUE
-	RET				; DISCARD ERR CODE AND RETURN
-NABUKB_XB1:
-	CP	$E0			; SPECIAL CHARACTER?
-	JR	C,NABUKB_XB2		; IF NOT, SKIP XLAT, BUFFER KEY
-	CALL	NABUKB_XLAT		; IF SO, TRANSLATE IT
-	RET	C			; CF INDICATES INVALID, DISCARD AND RETURN
-NABUKB_XB2:
-	LD	(NABUKB_KEY),A		; BUFFER IT
-	LD	A,1			; SIGNAL KEY WAITING
-	LD	(NABUKB_KSTAT),A	; SAVE IT
-	RET				; DONE
-;
-; ROUTINE TO TRANSLATE SPECIAL NABU KEYBOARD KEY CODES
-;
-NABUKB_XLAT:
+	JR	C,NABUKB_XB1		; IF ERR CODE, RETURN W/ CF SET
+	; $A0-$BF ARE JOYSTICK DATA (PASS THESE THROUGH)
+	CP	$C0			; END OF JOYSTICK DATA
+	JR	C,NABUKB_XB2		; IF JOY DATA, RETURN W/ CF CLEAR
+	; $C0-$DF ARE UNUSED CODES (IGNORE THESE)
+	CP	$E0			; END OF UNUSED CODES
+	JR	C,NABUKB_XB1		; IF UNUSED CODE, RETURN W/ CF SET
 	; NABU KEYBOARD USES $E0-$FF FOR SPECIAL KEYS
 	; HERE WE TRANSLATE TO ROMWBW SPECIAL KEYS AS BEST WE CAN
-	; CF IS SET ON RETURN IF KEY IS INVALID (NO TRANSLATION)
 	SUB	$E0			; ZERO OFFSET
-	RET	C			; ABORT IF < $E0, CF SET!
 	LD	HL,NABUKB_XTBL		; POINT TO XLAT TABLE
 	CALL	ADDHLA			; OFFSET BY SPECIAL KEY VAL
 	LD	A,(HL)			; GET TRANSLATED VALUE
 	OR	A			; CHECK FOR N/A (0)
 	RET	NZ			; XLAT OK, RET W/ CF CLEAR
-	SCF				; SIGNAL INVALID
+NABUKB_XB1:
+	; RETURN W/ CF SET (DISCARD RESULT)
+	SCF				; ELSE SIGNAL INVALID
 	RET				; DONE
-;
-NABUKB_XLAT1:
-	SCF				; SIGNAL INVALID
-	RET				; AND DONE
+NABUKB_XB2:
+	; RETURN W/ CF CLEAR (KEEP RESULT)
+	OR	A			; CLEAR CF
+	RET				; RETURN, CF CLEAR
 ;
 ; FLUSH KEYBOARD BUFFER
 ;
 NABUKB_FLUSH:
+#IF (INTMODE == 0)
 	XOR	A
 	LD	(NABUKB_KSTAT),A
+#ELSE
+	; RESET THE RECEIVE BUFFER
+	LD	DE,NABUKB_RCVBUF	; DE := CNT
+	XOR	A			; A := 0
+	LD	(DE),A			; _CNT = 0
+	INC	DE			; DE := ADR OF _HD
+	PUSH	DE			; SAVE IT
+	INC	DE
+	INC	DE
+	INC	DE
+	INC	DE			; DE := ADR OF _BUF
+	POP	HL			; HL := ADR OF _HD
+	LD	(HL),E
+	INC	HL
+	LD	(HL),D			; _HD := _BUF
+	INC	HL
+	LD	(HL),E
+	INC	HL
+	LD	(HL),D			; _TL := _BUF
+#ENDIF
 	RET
 ;
 ; WAIT FOR A KEY TO BE READY AND RETURN IT.
 ;
+#IF (INTMODE == 0)
 NABUKB_READ:
 	CALL	NABUKB_STAT		; CHECK FOR KEY READY
 	JR	Z,NABUKB_READ		; LOOP TIL ONE IS READY
@@ -205,6 +244,46 @@ NABUKB_READ:
 	LD	D,A			; NO KEYSTATE
 	LD	(NABUKB_KSTAT),A	; CLEAR KEY WAITING STATUS
 	RET				; AND RETURN
+#ELSE
+;
+NABUKB_READ:
+	CALL	NABUKB_STAT		; SEE IF CHAR AVAILABLE
+	JR	Z,NABUKB_READ		; LOOP UNTIL SO
+	HB_DI				; AVOID COLLISION WITH INT HANDLER
+	LD	HL,NABUKB_RCVBUF	; SET HL TO START OF BUF STRUCT
+	LD	A,(HL)			; GET COUNT
+	DEC	A			; DECREMENT COUNT
+	LD	(HL),A			; SAVE UPDATED COUNT
+	INC	HL			; HL := ADR OF TAIL PTR
+	INC	HL			; "
+	INC	HL			; "
+	PUSH	HL			; SAVE ADR OF TAIL PTR
+	LD	A,(HL)			; DEREFERENCE HL
+	INC	HL
+	LD	H,(HL)
+	LD	L,A			; HL IS NOW ACTUAL TAIL PTR
+	LD	C,(HL)			; C := CHAR TO BE RETURNED
+	INC	HL			; BUMP TAIL PTR
+	POP	DE			; RECOVER ADR OF TAIL PTR
+	LD	A,L			; GET LOW BYTE OF TAIL PTR
+	SUB	NABUKB_BUFSZ+2		; SUBTRACT SIZE OF BUFFER AND POINTER
+	CP	E			; IF EQUAL TO START, TAIL PTR IS PAST BUF END
+	JR	NZ,NABUKB_READ2		; IF NOT, BYPASS
+	LD	H,D			; SET HL TO
+	LD	L,E			; ... TAIL PTR ADR
+	INC	HL			; BUMP PAST TAIL PTR
+	INC	HL			; ... SO HL NOW HAS ADR OF ACTUAL BUFFER START
+NABUKB_READ2:
+	EX	DE,HL			; DE := TAIL PTR VAL, HL := ADR OF TAIL PTR
+	LD	(HL),E			; SAVE UPDATED TAIL PTR
+	INC	HL			; "
+	LD	(HL),D			; "
+	LD	E,C			; MOVE CHAR TO RETURN TO E
+	HB_EI				; INTERRUPTS OK AGAIN
+	XOR	A			; SIGNAL SUCCESS
+	RET				; AND DONE
+;
+#ENDIF
 ;
 ; HELPER ROUTINE TO WRITE 
 ;
@@ -219,8 +298,20 @@ NABUKB_PUT:
 ;
 ;
 ;
-NABUKB_KSTAT	.DB	0	; KEY STATUS
-NABUKB_KEY	.DB	0	; KEY BUFFER
+#IF (INTMODE == 0)
+NABUKB_KSTAT	.DB	0		; KEY STATUS
+NABUKB_KEY	.DB	0		; KEY BUFFER
+#ELSE
+;
+; RECEIVE BUFFER
+;
+NABUKB_RCVBUF:
+NABUKB_BUFCNT	.DB	0		; CHARACTERS IN RING BUFFER
+NABUKB_HD	.DW	NABUKB_BUF	; BUFFER HEAD POINTER
+NABUKB_TL	.DW	NABUKB_BUF	; BUFFER TAIL POINTER
+NABUKB_BUF	.FILL	NABUKB_BUFSZ,0	; RECEIVE RING BUFFER
+NABUKB_BUFEND	.EQU	$		; END OF BUFFER
+#ENDIF
 ;
 ; THIS TABLE TRANSLATES THE NABU KEYBOARD SPECIAL CHARS INTO
 ; ANALOGOUS ROMWBW STANDARD SPECIAL CHARACTERS.  THE TABLE STARTS WITH

Source/HBIOS/romldr.asm

@@ -47,7 +47,6 @@ cmdbuf	.equ	$80	; cmd buf is in second half of page zero
 cmdmax	.equ	60	; max cmd len (arbitrary), must be < bufsiz
 bufsiz	.equ	$80	; size of cmd buf
 ;
-;;int_im1	.equ	$FF00	; IM1 vector target for RomWBW HBIOS proxy
 hbx_int		.equ	$FF60	; IM1 vector target for RomWBW HBIOS proxy
 ;
 bid_cur	.equ	-1	; used below to indicate current bank
@@ -132,16 +131,22 @@ start:
 	di
 #endif
 ;
-; Switch to user RAM bank
+; Switch to user RAM bank and establish boot mode
 ;
 #if (BIOS == BIOS_WBW)
+	; Get the boot mode
+	ld	b,BF_SYSPEEK		; HBIOS func: PEEK
+	ld	d,BID_BIOS		; BIOS bank
+	ld	hl,HCB_LOC + HCB_BOOTMODE	; boot mode byte
+	rst	08
+	ld	a,e			; put in A
+	ld	(bootmode),a		; save it
+;
 	ld	b,BF_SYSSETBNK		; HBIOS func: set bank
 	ld	c,BID_USR		; select user bank
 	rst	08			; do it
 	ld	a,c			; previous bank to A
 	ld	(bid_ldr),a		; save previous bank for later
-	;;;bit	7,a			; starting from ROM?
-	cp	BID_IMG0		; ROM startup?
 #endif
 ;
 #if (BIOS == BIOS_UNA)
@@ -149,16 +154,22 @@ start:
 	ld	de,BID_USR		; select user bank
 	rst	08			; do it
 	ld	(bid_ldr),de		; save previous bank for later
+;
+	ld	a,BM_ROMBOOT		; assume ROM boot
 	bit	7,d			; starting from ROM?
+	jr	z,start1		; if so, skip ahead
+	ld	a,BM_APPBOOT		; else this is APP boot
+start1:
+	ld	(bootmode),a		; save it
 #endif
 ;
 	; For app mode startup, use alternate table
-	ld	hl,ra_tbl		; assume ROM startup
-	jr	z,start1		; if so, ra_tbl OK, skip ahead
-	ld	hl,ra_tbl_app		; not ROM boot, get app tbl loc
-	ld	a,$ff			; signal for app boot
-	ld	(appboot),a		; ... goes in flag
-start1:
+	ld	hl,ra_tbl		; assume ROM application table
+	ld	a,(bootmode)		; get boot mode
+	cp	BM_ROMBOOT		; ROM boot?
+	jr	z,start2		; if so, ra_tbl OK, skip ahead
+	ld	hl,ra_tbl_app		; switch to RAM application table
+start2:
 	ld	(ra_tbl_loc),hl		; and overlay pointer
 ;
 ; Copy original page zero into user page zero
@@ -178,9 +189,9 @@ start1:
 ;
 #if (BIOS == BIOS_WBW)
 	; Get the current console unit
-	ld	b,BF_SYSPEEK		; HBIOS func: POKE
+	ld	b,BF_SYSPEEK		; HBIOS func: PEEK
 	ld	d,BID_BIOS		; BIOS bank
-	ld	hl,HCB_LOC + HCB_CONDEV	; Con unit num in HCB
+	ld	hl,HCB_LOC + HCB_CONDEV	; console unit num in HCB
 	rst	08			; do it
 	ld	a,e			; put in A
 	ld	(curcon),a		; save it
@@ -208,10 +219,10 @@ start1:
 	call	nl2			; formatting
 	ld	hl,str_banner		; display boot banner
 	call	pstr			; do it
-	ld	a,(appboot)		; get app boot flag
-	or	a			; set flags
+	ld	a,(bootmode)		; get app boot flag
+	cp	BM_APPBOOT		; APP boot?
 	ld	hl,str_appboot		; signal application boot mode
-	call	nz,pstr			; print if app boot active
+	call	z,pstr			; print if APP boot
 	call	clrbuf			; zero fill the cmd buffer
 ;
 #if ((BIOS == BIOS_WBW) & FPSW_ENABLE)
@@ -2404,8 +2415,8 @@ ra_ent		.equ	12
 ;
 ; Note: The loadable ROM images are placed in ROM banks BID_IMG0 and
 ; BID_IMG1.  However, RomWBW supports a mechanism to load a complete
-; new system dynamically as a runnable application (see appboot and
-; imgboot in hbios.asm).  In this case, the contents of BID_IMG0 will
+; new system dynamically as a runnable application (see appboot
+; in hbios.asm).  In this case, the contents of BID_IMG0 will
 ; be pre-loaded into the currently executing ram bank thereby allowing
 ; those images to be dynamically loaded as well.  To support this
 ; concept, a pseudo-bank called bid_cur is used to specify the images
@@ -2425,14 +2436,13 @@ ra_entsiz	.equ	$ - ra_tbl
 ra_ent(str_smon,  'S',	   $FF,	  bid_cur , $8000,       $8000,   $0001,   s100mon)
   #endif
 #endif
-ra_ent(str_zsys,  'Z',	   KY_FW, BID_IMG0, ZSYS_IMGLOC, CPM_LOC, CPM_SIZ, CPM_ENT)
 ra_ent(str_cpm22, 'C',	   KY_BK, BID_IMG0, CPM_IMGLOC,  CPM_LOC, CPM_SIZ, CPM_ENT)
+ra_ent(str_zsys,  'Z',	   KY_FW, BID_IMG0, ZSYS_IMGLOC, CPM_LOC, CPM_SIZ, CPM_ENT)
 #if (BIOS == BIOS_WBW)
-ra_ent(str_fth,	  'F',	   KY_EX, BID_IMG1, FTH_IMGLOC,  FTH_LOC, FTH_SIZ, FTH_LOC)
 ra_ent(str_bas,	  'B',	   KY_DE, BID_IMG1, BAS_IMGLOC,  BAS_LOC, BAS_SIZ, BAS_LOC)
 ra_ent(str_tbas,  'T',	   KY_EN, BID_IMG1, TBC_IMGLOC,  TBC_LOC, TBC_SIZ, TBC_LOC)
+ra_ent(str_fth,	  'F',	   KY_EX, BID_IMG1, FTH_IMGLOC,  FTH_LOC, FTH_SIZ, FTH_LOC)
 ra_ent(str_play,  'P',	   $FF,	  BID_IMG1, GAM_IMGLOC,  GAM_LOC, GAM_SIZ, GAM_LOC)
-ra_ent(str_egg,	  'E'+$80, $FF,   BID_IMG1, EGG_IMGLOC,  EGG_LOC, EGG_SIZ, EGG_LOC)
 ra_ent(str_net,   'N',	   $FF,	  BID_IMG1, NET_IMGLOC,  NET_LOC, NET_SIZ, NET_LOC)
 ra_ent(str_upd,   'X',	   $FF,	  BID_IMG1, UPD_IMGLOC,  UPD_LOC, UPD_SIZ, UPD_LOC)
 ra_ent(str_user,  'U',	   $FF,	  BID_IMG1, USR_IMGLOC,  USR_LOC, USR_SIZ, USR_LOC)
@@ -2440,6 +2450,7 @@ ra_ent(str_user,  'U',	   $FF,	  BID_IMG1, USR_IMGLOC,  USR_LOC, USR_SIZ, USR_LO
 #if (DSKYENABLE)
 ra_ent(str_dsky,  'Y'+$80, KY_GO, BID_IMG0, MON_IMGLOC,  MON_LOC, MON_SIZ, MON_DSKY)
 #endif
+ra_ent(str_egg,	  'E'+$80, $FF,   BID_IMG1, EGG_IMGLOC,  EGG_LOC, EGG_SIZ, EGG_LOC)
 		.dw	0		; table terminator
 ;
 ra_tbl_app:
@@ -2488,7 +2499,7 @@ dma		.dw	0		; address for load
 sps		.dw	0		; sectors per slice
 mediaid		.db	0		; media id
 ;
-appboot		.db	0		; app boot if != 0
+bootmode	.db	0		; ROM, APP, or IMG boot
 ra_tbl_loc	.dw	0		; points to active ra_tbl
 bootunit	.db	0		; boot disk unit
 bootslice	.db	0		; boot disk slice
@@ -2503,7 +2514,6 @@ ciocnt		.db	1		; count of char units
 savcon		.db	0		; con save for conpoll
 conpend		.db	$ff		; pending con unit (first <space> pressed)
 #endif
-
 ;
 ;=======================================================================
 ; Pad remainder of ROM Loader

Source/HBIOS/scon.asm

@@ -5,7 +5,7 @@
 ;
 ; TODO:
 ;
-SCON_IOBASE	.EQU	$00
+SCON_IOBASE	.EQU	$0000			; NOTE: 16-BIT I/O
 ;
 SCON_STATUS	.EQU	SCON_IOBASE
 SCON_DATA	.EQU	SCON_IOBASE + 1
@@ -25,6 +25,9 @@ SCON_ROWS	.EQU	40
 SCON_INIT:
 	CALL	NEWLINE
 	PRTS("SCON:$")
+	PRTS(" IO=0x$")			; FORMATTING
+	LD	A,SCON_IOBASE
+	CALL	PRTHEXBYTE
 ;
 	; DISPLAY CONSOLE DIMENSIONS
 	CALL	PC_SPACE
@@ -67,14 +70,18 @@ SCON_FNTBL:
 SCON_IN:
 	CALL	SCON_IST		; CHECK FOR CHAR PENDING
 	JR	Z,SCON_IN		; WAIT FOR IT IF NECESSARY
-	IN0	A,(SCON_DATA)		; READ THE CHAR FROM PROPIO
+	;IN0	A,(SCON_DATA)		; READ THE CHAR FROM PROPIO
+	LD	BC,SCON_DATA		; DATA PORT (16 BIT I/O)
+	IN	A,(C)			; READ THE CHAR FROM PROPIO
 	LD	E,A
 	RET
 ;
 ;
 ;
 SCON_IST:
-	IN0	A,(SCON_STATUS)		; READ LINE STATUS REGISTER
+	;IN0	A,(SCON_STATUS)		; READ LINE STATUS REGISTER
+	LD	BC,SCON_STATUS		; STATUS PORT (16-BIT I/O)
+	IN	A,(C)			; READ LINE STATUS REGISTER
 	AND	SCON_KBDRDY		; ISOLATE KBDRDY
 	JP	Z,CIO_IDLE		; RETURN VIA IDLE PROCESSING
 	OR	$FF			; SET A=$FF TO SIGNAL READY
@@ -86,13 +93,17 @@ SCON_OUT:
 	CALL	SCON_OST		; CHECK FOR OUTPUT READY
 	JR	Z,SCON_OUT		; WAIT IF NECESSARY
 	LD	A,E			; RECOVER THE CHAR TO WRITE
-	OUT0	(SCON_DATA),A		; WRITE THE CHAR TO PROPIO
+	;OUT0	(SCON_DATA),A		; WRITE THE CHAR TO PROPIO
+	LD	BC,SCON_DATA		; DATA PORT (16 BIT I/O)
+	OUT	(C),A			; WRITE THE CHAR TO PROPIO
 	RET
 ;
 ;
 ;
 SCON_OST:
-	IN0	A,(SCON_STATUS)		; READ LINE STATUS REGISTER
+	;IN0	A,(SCON_STATUS)		; READ LINE STATUS REGISTER
+	LD	BC,SCON_STATUS		; STATUS PORT (16-BIT I/O)
+	IN	A,(C)			; READ LINE STATUS REGISTER
 	AND	SCON_DSPRDY 		; ISOLATE DSPRDY
 	JP	Z,CIO_IDLE		; RETURN VIA IDLE PROCESSING
 	OR	$FF			; SET A=$FF TO SIGNAL READY

Source/HBIOS/sd.asm

@@ -294,7 +294,7 @@ SD_CS1		.EQU	%00010000	; IN/OUT:SD_OPREG:4 = CS1, SDCARD1 CS, IN=1 Card present
   #ENDIF
 SD_IOBASE	.EQU	SD_BASE		; IOBASE
 SD_INVCS	.EQU	FALSE		; INVERT CS
-		DEVECHO	"DUO"
+		DEVECHO	"MT"
 #ENDIF
 ;
 ;
@@ -372,10 +372,10 @@ SD_CS0		.EQU	%00000100	; SELECT
 SD_DI		.EQU	%00000001	; DATA IN (CARD <- CPU) MOSI
 SD_DO		.EQU	%00000001	; DATA OUT (CARD -> CPU) MISO
 SD_CINIT	.EQU	FALSE		; INITIALIZE OUTPUT PORT
-SD_INVCS	.EQU	FALSE		; INVERT CS
+SD_INVCS	.EQU	TRUE		; INVERT CS
 		DEVECHO	"Z80R"
 #ENDIF
-
+;
 ; FOR NOW WE JUST HOOK UP ONE UNIT. THERE ARE EIGHT PORTS FOR DIFFERENT
 ; THINGS BUT THIS WILL GET US GOING
 #IF (SDMODE == SDMODE_EPITX)		; Z180 ITX - CSIO, 82C55 for CS
@@ -389,6 +389,39 @@ SD_IOBASE	.EQU	SD_OPRREG	; IOBASE
 SD_INVCS	.EQU	FALSE		; INVERT CS
 		DEVECHO	"EPITX"
 #ENDIF
+;
+; S100 FPGA Z80 SPI-BASED SD CARD
+;
+; BASE PORT: $6C
+;   BASE + 0: DATA IN/OUT
+;   BASE + 1: SPI CLOCK SPEED (0=LOW 4KHZ, 1=HIGH 10MHZ)
+;   BASE + 2: SELECT (W), STATUS (R)
+;   BASE + 3: START READ (IN OPCODE), START WRITE (OUT OPCODE), ANY VALUE
+;   
+; STATUS BITS:
+;   7: BUSY (1=BUSY)
+;   0: PRIMARY DEVICE SELECT STATUS (1=SELECTED)
+;   1: SECONDARY DEVICE SELECT STATUS  (1=SELECTED)
+;
+; SELECT BITS (INVERTED!!!):
+;   0: PRIMARY DEVICE, USE VALUE ~$01
+;   1: SECONDARY DEVICE, USE VALUE ~$02
+;
+#IF (SDMODE == SDMODE_FZ80)		; S100 FPGA Z80
+SD_IOBASE	.EQU	$6C		; IOBASE
+SD_DATA		.EQU	SD_IOBASE + 0	; DATA IN/OUT PORT
+SD_CLKSEL	.EQU	SD_IOBASE + 1	; CLOCK SPEED SELECT PORT
+SD_SELSTAT	.EQU	SD_IOBASE + 2	; DEVICE SELECT PORT (W) / STATUS (R)
+SD_ACTION	.EQU	SD_IOBASE + 3	; INITIATE R/W ACTION VIA IN/OUT
+;
+SD_DEVMAX	.EQU	2		; NUMBER OF PHYSICAL UNITS (SOCKETS)
+SD_OPRREG	.EQU	SD_SELSTAT	; SELECT/STATUS PORT
+SD_OPRDEF	.EQU	$FF		; QUIESCENT STATE
+SD_CS0		.EQU	%00000001	; PRIMARY DEVICE SELECT BIT
+SD_CS1		.EQU	%00000010	; SECONDARY DEVICE SELECT BIT
+SD_INVCS	.EQU	TRUE		; INVERT CS
+		DEVECHO	"FZ80"
+#ENDIF
 ;
 		DEVECHO	", IO="
 		DEVECHO	SD_IOBASE
@@ -640,6 +673,13 @@ SD_INIT:
 	LD	A,SD_TRDR
 	CALL	PRTHEXBYTE
 #ENDIF
+;
+#IF (SDMODE == SDMODE_FZ80)
+	PRTS(" MODE=FZ80$")
+	PRTS(" IO=0x$")
+	LD	A,SD_IOBASE
+	CALL	PRTHEXBYTE
+#ENDIF
 ;
 	CALL	SD_PROBE		; CHECK FOR HARDWARE
 	JR	Z,SD_INIT00		; CONTINUE IF PRESENT
@@ -1083,6 +1123,11 @@ SD_INITCARD:
 #IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
 	CALL	SD_CSIO_DEF		; ENSURE CSIO AT DEFAULT SPEED
 #ENDIF
+;
+#IF (SDMODE == SDMODE_FZ80)
+	;;; FORCE SLOW SPEED HERE?
+	;;; CALL SD_SELECT?
+#ENDIF
 ;
 	; WAKE UP THE CARD, KEEP DIN HI (ASSERTED) AND /CS HI (DEASSERTED)
 	LD	B,$10	; MIN 74 CLOCKS REQUIRED, WE USE 128 ($10 * 8)
@@ -1486,8 +1531,10 @@ SD_GOIDLE:
 ;
 SD_GOIDLE1:
 	; SEEMS TO HELP SOME CARDS?
-	;CALL	SD_SELECT		; ASSERT CS
-	;CALL	SD_DONE			; SEND 8 CLOCKS AND DEASSERT CS
+	;;; DEBUG
+	CALL	SD_SELECT		; ASSERT CS
+	CALL	SD_DONE			; SEND 8 CLOCKS AND DEASSERT CS
+	;;; DEBUG
 
 	; SMALL DELAY HERE HELPS SOME CARDS
 	;;LD	DE,300			; 16US * 300 = ~5MS
@@ -1884,6 +1931,15 @@ SD_SETUP:
 	LD	(SD_OPRVAL),A
 	OUT	(SD_OPRREG),A
 #ENDIF
+;
+#IF (SDMODE == SDMODE_FZ80)
+	LD	A,SD_OPRDEF		; DEFAULT SELECT VALUE
+	LD	(SD_OPRVAL),A		; PUT IN SHADOW
+	OUT	(SD_OPRREG),A		; WRITE TO PORT
+	XOR	A			; LOW SPEED OPERATION
+	LD	(SD_CLKSEL),A		; DO IT
+	CALL	SD_DESELECT		; MAKE SURE CARD(S) ARE NOT SELECTED
+#ENDIF
 ;
 	XOR	A
 	RET
@@ -1931,7 +1987,7 @@ SD_SELECT:
 ;	CALL	SD_WAITTX
 ;#ENDIF
 ;
-#IF ((SDMODE == SDMODE_SC) | SDMODE == SDMODE_MT))
+#IF ((SDMODE == SDMODE_SC) | (SDMODE == SDMODE_MT) | (SDMODE == SDMODE_FZ80))
 	LD	A,(IY+SD_DEV)		; GET CURRENT DEVICE
 	OR	A			; SET FLAGS
 	LD	A,(SD_OPRVAL)		; GET CURRENT OPRVAL BACK
@@ -1949,21 +2005,21 @@ SD_SELECT1:
 	OR	SD_CS1
   #ENDIF
 #ELSE
-#IF (SDMODE == SDMODE_EPITX)
+  #IF (SDMODE == SDMODE_EPITX)
 	LD	A,(SD_OPRVAL)
 	AND	$F8
 	OR	SD_CS0			; WILL DO 1-7 LATER
-#ELSE
+  #ELSE
 	LD	A,(SD_OPRVAL)		; GET CURRENT OPRVAL BACK
 	OR	SD_CS0
-#ENDIF
+  #ENDIF
 #ENDIF
 ;
 SD_SELECT2:
 ; ADJUST BIT(S) FOR INTERFACES USING INVERTED CS BITS
 ;#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC))
 #IF (SD_INVCS)
-  #IF ((SDMODE == SDMODE_SC) & (SD_DEVCNT > 1))
+  #IF (((SDMODE == SDMODE_SC) | (SDMODE == SDMODE_FZ80)) & (SD_DEVCNT > 1))
 	XOR	SD_CS0 | SD_CS1
   #ELSE
 	XOR	SD_CS0
@@ -1994,20 +2050,25 @@ SD_DESELECT:
 	; TRACES.
 	CALL	DLY32			; DELAY FOR FINAL BIT
 #ENDIF
+;
+#IF (SDMODE == SDMODE_FZ80)
+	CALL	SD_WAITBSY
+#ENDIF
 ;
 	LD	A,(SD_OPRVAL)
 #IF (((SDMODE == SDMODE_SC) | (SDMODE_MT)) & (SD_DEVCNT > 1))
 	AND	~(SD_CS0 | SD_CS1)
 #ELSE
-#if (SDMODE == SDMODE_EPITX)
+#IF (SDMODE == SDMODE_EPITX)
 	OR	7			; CHAN 7 IS USED FOR DESELECTS
 #ELSE
 	AND	~SD_CS0
 #ENDIF
 #ENDIF
 ; ADJUST BIT(S) FOR INTERFACES USING INVERTED CS BITS
-#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_PIO) | (SDMODE == SDMODE_Z80R))
-  #IF ((SDMODE == SDMODE_SC) & (SD_DEVCNT > 1))
+;;;#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_PIO) | (SDMODE == SDMODE_Z80R))
+#IF (SD_INVCS)
+  #IF (((SDMODE == SDMODE_SC) | (SDMODE == SDMODE_FZ80)) & (SD_DEVCNT > 1))
 	XOR	SD_CS0 | SD_CS1
   #ELSE
 	XOR	SD_CS0
@@ -2037,24 +2098,40 @@ SD_WAITRX:
 ;
 #ENDIF
 ;
+#IF (SDMODE == SDMODE_FZ80)
+;
+; WAIT WHILE FPGA SPI INTERFACE IS BUSY SENDING OR RECEIVING
+;
+SD_WAITBSY:
+	PUSH	AF
+	CALL	PC_PERIOD		; *DEBUG*
+	;;;CALL	DLY32
+	IN	A,(SD_SELSTAT)
+	BIT	7,A
+	JR	NZ,SD_WAITBSY
+	;;;CALL	DLY32
+	POP	AF
+	RET
+#ENDIF
+;
 ; SEND ONE BYTE
 ;
 SD_PUT:
 ;
 #IF (SDMODE == SDMODE_MT)
 	OUT	(SD_WRTR),A
-#ELSE
+#ENDIF
 ;
-  #IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
+#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
 	CALL	MIRROR			; MSB<-->LSB MIRROR BITS, RESULT IN C
 	CALL	SD_WAITTX		; MAKE SURE WE ARE DONE SENDING
 	OUT0	(SD_TRDR),C		; PUT BYTE IN BUFFER
 	IN0	A,(SD_CNTR)
 	SET	4,A			; SET TRANSMIT ENABLE
 	OUT0	(SD_CNTR),A
-  #ELSE
-
-    #IF (SDMODE == SDMODE_Z80R)
+#ENDIF
+;
+#IF (SDMODE == SDMODE_Z80R)
 	; USE C - THE CALLING CODE FOR COMMAND SEND FAILS TO SAVE HL/DE
 	; WHILST THE OTHER PATHS DO ?
         LD	C,A
@@ -2090,8 +2167,9 @@ SD_PUT:
 	RLA
 	OUT	(SD_IOREG),A
 	OUT	(SD_IOCLK),A
-    #ELSE
-
+#ENDIF
+;
+#IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_N8) | (SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_DSD) | (SDMODE == SDMODE_USR) | (SDMODE == SDMODE_PIO))
       #IF (SDMODE == SDMODE_UART)
 	XOR	$FF			; DI IS INVERTED ON UART
       #ENDIF
@@ -2110,8 +2188,17 @@ SD_PUT1:
 	DJNZ	SD_PUT1			; REPEAT FOR ALL 8 BITS
 	LD	A,(SD_OPRVAL)		; LOAD CURRENT OPR VALUE
 	OUT	(SD_OPRREG),A		; LEAVE WITH CLOCK LOW
-    #ENDIF
-  #ENDIF
+#ENDIF
+;
+#IF (SDMODE == SDMODE_FZ80)
+	CALL	SD_WAITBSY		; WAIT FOR PENDING ACTIVITY
+	OUT	(SD_DATA),A		; POST THE VALUE
+	OUT	(SD_ACTION),A		; INITIATE THE WRITE
+	;;;CALL	SD_WAITBSY
+
+	CALL	PC_SPACE		; *DEBUG*
+	CALL	PC_GT			; *DEBUG*
+	CALL	PRTHEXBYTE		; *DEBUG*
 #ENDIF
 	RET				; DONE
 ;
@@ -2122,8 +2209,9 @@ SD_GET:
 ;
 #IF (SDMODE == SDMODE_MT)
 	IN	A,(SD_RDTR)
-#ELSE
-  #IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
+#ENDIF
+;
+#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
 	CALL	SD_WAITTX		; MAKE SURE WE ARE DONE SENDING
 	IN0	A,(SD_CNTR)		; GET CSIO STATUS
 	SET	5,A			; START RECEIVER
@@ -2132,8 +2220,9 @@ SD_GET:
 	IN0	A,(SD_TRDR)		; GET RECEIVED BYTE
 	CALL	MIRROR			; MSB<-->LSB MIRROR BITS
 	LD	A,C			; KEEP RESULT
-  #ELSE
-    #IF (SDMODE == SDMODE_Z80R)
+#ENDIF
+;
+#IF (SDMODE == SDMODE_Z80R)
 	; MUST PRESERVE HL,DE
 	PUSH	DE
 	LD	A,1
@@ -2180,38 +2269,49 @@ SD_GET:
 	RL	E
 	LD	A,E
 	POP	DE
-    #ELSE
+#ENDIF
+;
+#IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_N8) | (SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_DSD) | (SDMODE == SDMODE_USR) | (SDMODE == SDMODE_PIO))
 	LD	B,8			; RECEIVE 8 BITS (LOOP 8 TIMES)
 	LD	A,(SD_OPRVAL)		; LOAD CURRENT OPR VALUE
 SD_GET1:
 	XOR	SD_CLK			; TOGGLE CLOCK
 	OUT	(SD_OPRREG),A		; UPDATE CLOCK
 	IN	A,(SD_INPREG)		; READ THE DATA WHILE CLOCK IS ACTIVE
-      #IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_PIO))
+  #IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_PIO))
 	RLA				; ROTATE INP:7 INTO CF
-      #ENDIF
-      #IF (SDMODE == SDMODE_N8)
+  #ENDIF
+  #IF (SDMODE == SDMODE_N8)
 	RLA				; ROTATE INP:6 INTO CF
 	RLA				; "
-      #ENDIF
-      #IF (SDMODE == SDMODE_UART)
+  #ENDIF
+  #IF (SDMODE == SDMODE_UART)
 	RLA				; ROTATE INP:5 INTO CF
 	RLA				; "
 	RLA				; "
-      #ENDIF
-      #IF (SDMODE == SDMODE_DSD)
+  #ENDIF
+  #IF (SDMODE == SDMODE_DSD)
 	RRA				; ROTATE INP:0 INTO CF
-      #ENDIF
+  #ENDIF
 	RL	C			; ROTATE CF INTO C:0
 	LD	A,(SD_OPRVAL)		; BACK TO INITIAL VALUES (TOGGLE CLOCK)
 	OUT	(SD_OPRREG),A		; DO IT
 	DJNZ	SD_GET1			; REPEAT FOR ALL 8 BITS
 	LD	A,C			; GET BYTE RECEIVED INTO A
-      #IF (SDMODE == SDMODE_UART)
+  #IF (SDMODE == SDMODE_UART)
 	XOR	$FF			; DO IS INVERTED ON UART
-      #ENDIF
-    #ENDIF
   #ENDIF
+#ENDIF
+;
+#IF (SDMODE == SDMODE_FZ80)
+	CALL	SD_WAITBSY		; WAIT FOR PENDING ACTIVITY
+	IN	A,(SD_ACTION)		; INITIATE READ
+	CALL	SD_WAITBSY		; WAIT FOR DONE
+	IN	A,(SD_DATA)		; GET THE VALUE
+	;;;CALL	SD_WAITBSY
+	CALL	PC_SPACE		; *DEBUG*
+	CALL	PC_LT			; *DEBUG*
+	CALL	PRTHEXBYTE		; *DEBUG*
 #ENDIF
 	RET
 ;

Source/HBIOS/spk.asm

@@ -40,6 +40,7 @@ SP_RTCIOMSK	.EQU	00000100B
 SP_PENDING_PERIOD	.DW	SP_NOTE_C8	; PENDING PERIOD (16 BITS)
 SP_PENDING_VOLUME	.DB	$FF		; PENDING VOL (8 BITS)
 SP_PENDING_DURATION	.DW	0		; PENDING DURATION (16 BITS)
+SP_TBLRDY		.DB	0		; IF != 0, NOTE TABLE IS READY
 ;
 	DEVECHO	"SPK: IO="
 	DEVECHO	RTCIO
@@ -59,8 +60,18 @@ SP_INIT:
 	PRTS("SPK: IO=0x$")
 	LD	A,RTCIO
 	CALL	PRTHEXBYTE
+;	
+	; RESET DEFAULTS IN CASE OF AN IN-PLACE HBIOS RESTART
+	LD	HL,SP_NOTE_C8
+	LD	(SP_PENDING_PERIOD),HL
+	LD	A,$FF
+	LD	(SP_PENDING_VOLUME),A
+	XOR	A
+	LD	(SP_PENDING_DURATION),A
+;	
 	CALL	SP_SETTBL		; SETUP TONE TABLE
 	CALL	SP_PLAY			; PLAY DEFAULT NOTE
+;
 	XOR	A
 	RET
 ;
@@ -164,6 +175,13 @@ SP_QUERY_DEV:
 ;======================================================================
 ;
 SP_SETTBL:
+	; IN CASE OF HBIOS RESTART IN PLACE, WE CHECK TO SEE IF THE
+	; NOT TABLE IS ALREADY INITIALIZED (READY).  IF SO, WE DON'T
+	; WANT TO DO IT AGAIN.
+	LD	A,(SP_TBLRDY)
+	OR	A
+	RET	NZ
+;
 	LD	BC,(CB_CPUMHZ)		; GET MHZ CPU SPEED (IN C).
 ;	 
 SP_SETTBL3:
@@ -202,6 +220,10 @@ SP_SETBL4:
 	INC	HL			; TO NEXT
 ;
 	DJNZ	SP_SETTBL2		; NEXT NOTE
+;
+	OR	$FF			; SIGNAL TABLE READY
+	LD	(SP_TBLRDY),A		; SAVE IT
+;
 	RET
 ;
 ;======================================================================

Source/HBIOS/sser.asm

@@ -0,0 +1,116 @@
+;
+;==================================================================================================
+; SIMPLE SERIAL DRIVER
+;==================================================================================================
+;
+; TODO:
+;
+		DEVECHO	"SSER: IO="
+		DEVECHO	SSERSTATUS
+		DEVECHO	"\n"
+;
+;
+;
+SSER_PREINIT:
+;
+; ADD OURSELVES TO CIO DISPATCH TABLE
+;
+	LD	D,0			; PHYSICAL UNIT IS ZERO
+	LD	E,CIODEV_SSER		; DEVICE TYPE
+	LD	BC,SSER_FNTBL		; BC := FUNCTION TABLE ADDRESS
+	CALL	CIO_ADDENT		; ADD ENTRY, A := UNIT ASSIGNED
+;
+	XOR	A
+	RET
+;
+;
+;
+SSER_INIT:
+	CALL	NEWLINE
+	PRTS("SSER:$")
+	PRTS(" IO=0x$")			; FORMATTING
+	LD	A,SSERSTATUS
+	CALL	PRTHEXBYTE
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; DRIVER FUNCTION TABLE
+;
+SSER_FNTBL:
+	.DW	SSER_IN
+	.DW	SSER_OUT
+	.DW	SSER_IST
+	.DW	SSER_OST
+	.DW	SSER_INITDEV
+	.DW	SSER_QUERY
+	.DW	SSER_DEVICE
+#IF (($ - SSER_FNTBL) != (CIO_FNCNT * 2))
+	.ECHO	"*** INVALID SSER FUNCTION TABLE ***\n"
+#ENDIF
+;
+;
+;
+SSER_IN:
+	CALL	SSER_IST		; CHECK FOR CHAR PENDING
+	JR	Z,SSER_IN		; WAIT FOR IT IF NECESSARY
+	IN	A,(SSERDATA)		; READ THE CHAR
+	LD	E,A
+	RET
+;
+;
+;
+SSER_IST:
+	IN	A,(SSERSTATUS)		; READ LINE STATUS REGISTER
+#IF (SSERIINV)
+	CPL
+#ENDIF
+	AND	SSERIRDY		; ISOLATE DATA READY
+	JP	Z,CIO_IDLE		; RETURN VIA IDLE PROCESSING
+	OR	$FF			; SET A=$FF TO SIGNAL READY
+	RET				; RETURN
+;
+;
+;
+SSER_OUT:
+	CALL	SSER_OST		; CHECK FOR OUTPUT READY
+	JR	Z,SSER_OUT		; WAIT IF NECESSARY
+	LD	A,E			; RECOVER THE CHAR TO WRITE
+	OUT	(SSERDATA),A		; WRITE THE CHAR
+	RET
+;
+;
+;
+SSER_OST:
+	IN	A,(SSERSTATUS)		; READ LINE STATUS REGISTER
+#IF (SSEROINV)
+	CPL
+#ENDIF
+	AND	SSERORDY 		; ISOLATE OUTPUT RDY
+	JP	Z,CIO_IDLE		; RETURN VIA IDLE PROCESSING
+	OR	$FF			; SET A=$FF TO SIGNAL READY
+	RET				; RETURN
+;
+;
+;
+SSER_INITDEV:
+	SYSCHKERR(ERR_NOTIMPL)
+	RET
+;
+;
+;
+SSER_QUERY:
+	LD	DE,SSERCFG
+	XOR	A
+	RET
+;
+;
+;
+SSER_DEVICE:
+	LD	D,CIODEV_SSER		; D := DEVICE TYPE
+	LD	E,0			; E := DEVICE NUM, ALWAYS 0
+	LD	C,$00			; C := DEVICE TYPE, 0x00 IS RS-232
+	LD	H,0			; H := 0, DRIVER HAS NO MODES
+	LD	L,SSERSTATUS		; L := BASE I/O ADDRESS
+	XOR	A			; SIGNAL SUCCESS
+	RET

Source/HBIOS/std.asm

@@ -24,6 +24,8 @@
 ; 20. MON	Jacques Pelletier's Monsputer
 ; 21. STDZ180	Genesis Z180 System
 ; 22. NABU	NABU w/ Les Bird's RomWBW Option Board
+; 23. FZ80	S100 Computers FPGA Z80
+; 
 ;
 ; INCLUDE BUILD VERSION
 ;
@@ -70,6 +72,12 @@ BIOS_NONE	.EQU	0		; NO BIOS TYPE DEFINED
 BIOS_WBW	.EQU	1		; ROMWBW HBIOS
 BIOS_UNA	.EQU	2		; UNA UBIOS
 ;
+; HBIOS BOOT MODES
+;
+BM_ROMBOOT	.EQU	1		; ROM BOOT
+BM_APPBOOT	.EQU	2		; APPLICATION BOOT
+BM_IMGBOOT	.EQU	3		; IMAGE BOOT (DEPRECATED)
+;
 ; MEMORY MANAGERS
 ;
 MM_NONE		.EQU	0
@@ -214,6 +222,7 @@ SDMODE_USR	.EQU	10		; USER DEFINED (in sd.asm) (NOT COMPLETE)
 SDMODE_PIO	.EQU	11		; Z80 PIO bitbang
 SDMODE_Z80R	.EQU	12		; Z80 Retro
 SDMODE_EPITX	.EQU	13		; Mini ITX Z180
+SDMODE_FZ80	.EQU	14		; S100 FPGA Z80
 ;
 ; AY SOUND CHIP MODE SELECTIONS
 ;
@@ -856,7 +865,7 @@ APP_BNKS	.SET	0
 ;;;BID_ROMDN	.EQU	BID_ROMD0 + ROMD_BNKS - 1	; LAST ROM DRIVE BANK
 ;;;BID_APPN	.EQU	BID_APP0 + APP_BNKS - 1		; LAST APP BANK
 ;
-#IF TRUE
+#IFDEF SYSINFO
 	.ECHO "------------- CAPACITY -----------------\n"
 	.ECHO "ROMBANKS:  " \ .ECHO ROMBANKS  \ .ECHO "\n"
 	.ECHO "RAMBANKS:  " \ .ECHO RAMBANKS  \ .ECHO "\n"
@@ -978,13 +987,82 @@ MON_SERIAL	.EQU	MON_LOC + (1 * 3)	; MONITOR ENTRY (SERIAL PORT)
 ;
 ; INTERRUPT MODE 2 SLOT ASSIGNMENTS
 ;
-#IF (((CPUFAM == CPU_Z180) | (CPUFAM == CPU_Z280)) & (INTMODE > 0))
+#IF ((CPUFAM == CPU_Z80) & (INTMODE == 2))
 
+  #IF (PLATFORM == PLT_MBC)
+;
+; MBC Z80 INTERRUPTS
+;
+INT_UART0	.EQU	4	; UART 0
+INT_UART1	.EQU	5	; UART 1
+INT_SIO0	.EQU	8	; ZILOG SIO 0, CHANNEL A & B
+INT_SIO1	.EQU	9	; ZILOG SIO 1, CHANNEL A & B
+INT_PIO0A	.EQU	10	; ZILOG PIO 0, CHANNEL A
+INT_PIO0B	.EQU	11	; ZILOG PIO 0, CHANNEL B
+INT_CTC0A	.EQU	12	; ZILOG CTC 0, CHANNEL A
+INT_CTC0B	.EQU	13	; ZILOG CTC 0, CHANNEL B
+INT_CTC0C	.EQU	14	; ZILOG CTC 0, CHANNEL C
+INT_CTC0D	.EQU	15	; ZILOG CTC 0, CHANNEL D
+  #ENDIF
+
+  #IF (PLATFORM == PLT_DUO)
+;
+; DUO Z80 IM2 INTERRUPTS
+;
+INT_UART0	.EQU	4	; UART 0
+INT_UART1	.EQU	5	; UART 1
+INT_SIO0	.EQU	8	; ZILOG SIO 0, CHANNEL A & B
+INT_SIO1	.EQU	9	; ZILOG SIO 1, CHANNEL A & B
+INT_PIO0A	.EQU	10	; ZILOG PIO 0, CHANNEL A
+INT_PIO0B	.EQU	11	; ZILOG PIO 0, CHANNEL B
+INT_CTC0A	.EQU	12	; ZILOG CTC 0, CHANNEL A
+INT_CTC0B	.EQU	13	; ZILOG CTC 0, CHANNEL B
+INT_CTC0C	.EQU	14	; ZILOG CTC 0, CHANNEL C
+INT_CTC0D	.EQU	15	; ZILOG CTC 0, CHANNEL D
+  #ENDIF
+
+  #IF (PLATFORM == PLT_NABU)
+;
+; NABU Z80 IM2 INTERRUPTS
+;
+INT_HCCARCV	.EQU	0	; CABLE ADAPTER RECEIVE
+INT_HCCASND	.EQU	1	; CABLE ADAPTER SEND
+INT_NABUKB	.EQU	2	; KEYBOARD RECEIVE
+INT_VDP		.EQU	3	; VDP VERTICAL RETRACE
+INT_OPTCRD0	.EQU	4	; OPTION CARD 0
+INT_OPTCRD1	.EQU	5	; OPTION CARD 1
+INT_OPTCRD2	.EQU	6	; OPTION CARD 2
+INT_OPTCRD3	.EQU	7	; OPTION CARD 3
+  #ENDIF
+
+  #IF ((PLATFORM != PLT_MBC) & (PLATFORM != PLT_DUO) & (PLATFORM != PLT_NABU))
+;
+; GENERIC Z80 M2 INTERRUPTS
+;
+INT_CTC0A	.EQU	0	; ZILOG CTC 0, CHANNEL A
+INT_CTC0B	.EQU	1	; ZILOG CTC 0, CHANNEL B
+INT_CTC0C	.EQU	2	; ZILOG CTC 0, CHANNEL C
+INT_CTC0D	.EQU	3	; ZILOG CTC 0, CHANNEL D
+INT_UART0	.EQU	4	; UART 0
+INT_UART1	.EQU	5	; UART 1
+INT_SIO0	.EQU	7	; ZILOG SIO 0, CHANNEL A & B
+INT_SIO1	.EQU	8	; ZILOG SIO 1, CHANNEL A & B
+INT_PIO0A	.EQU	9	; ZILOG PIO 0, CHANNEL A
+INT_PIO0B	.EQU	10	; ZILOG PIO 0, CHANNEL B
+INT_PIO1A	.EQU	11	; ZILOG PIO 1, CHANNEL A
+INT_PIO1B	.EQU	12	; ZILOG PIO 1, CHANNEL B
+  #ENDIF
+
+#ENDIF
+
+#IF ((CPUFAM == CPU_Z180) & (INTMODE > 0))
+;
+; Z180-BASED SYSTEMS
+;
 ; NOTE THAT Z180 PROCESSES ALL INTERNAL INTERRUPTS JUST LIKE
 ; IM2 EVEN WHEN CHIP IS IN IM1 MODE.  SO WE INCLUDE THE IM2
 ; INTERRUPT ASSIGNMENTS FOR IM1 BELOW.
-
-; Z180-BASED SYSTEMS
+;
 INT_INT1	.EQU	0	; Z180 INT 1
 INT_INT2	.EQU	1	; Z180 INT 2
 INT_TIM0	.EQU	2	; Z180 TIMER 0
@@ -1000,74 +1078,15 @@ INT_PIO1A	.EQU	11	; ZILOG PIO 1, CHANNEL A
 INT_PIO1B	.EQU	12	; ZILOG PIO 1, CHANNEL B
 INT_SIO0	.EQU	13	; ZILOG SIO 0, CHANNEL A & B
 INT_SIO1	.EQU	14	; ZILOG SIO 1, CHANNEL A & B
-
 #ENDIF
 
-#IF ((CPUFAM == CPU_Z80) & (INTMODE == 2))
-
-  #IF (PLATFORM == PLT_MBC)
+#IF ((CPUFAM == CPU_Z280) & (INTMODE >= 2))
 ;
-; MBC Z80 INTERRUPTS
+; Z280-BASED SYSTEMS
 ;
-;INT_CTC0A	.EQU	0	; ZILOG CTC 0, CHANNEL A
-;INT_CTC0B	.EQU	1	; ZILOG CTC 0, CHANNEL B
-;INT_CTC0C	.EQU	2	; ZILOG CTC 0, CHANNEL C
-;INT_CTC0D	.EQU	3	; ZILOG CTC 0, CHANNEL D
-INT_UART0	.EQU	4	; UART 0
-INT_UART1	.EQU	5	; UART 1
-INT_INT6	.EQU	6	;
-INT_INT7	.EQU	7	;
-INT_SIO0	.EQU	8	; ZILOG SIO 0, CHANNEL A & B
-INT_SIO1	.EQU	9	; ZILOG SIO 1, CHANNEL A & B
-INT_CTC0A	.EQU	12	; ZILOG CTC 0, CHANNEL A
-INT_CTC0B	.EQU	13	; ZILOG CTC 0, CHANNEL B
-INT_CTC0C	.EQU	14	; ZILOG CTC 0, CHANNEL C
-INT_CTC0D	.EQU	15	; ZILOG CTC 0, CHANNEL D
-;INT_PIO0A	.EQU	9	; ZILOG PIO 0, CHANNEL A
-;INT_PIO0B	.EQU	10	; ZILOG PIO 0, CHANNEL B
-;INT_PIO1A	.EQU	11	; ZILOG PIO 1, CHANNEL A
-;INT_PIO1B	.EQU	12	; ZILOG PIO 1, CHANNEL B
-
-  #ENDIF
-
-  #IF (PLATFORM == PLT_DUO)
+; FOR Z280 MODE 3, THESE APPLY TO THE INTA SIGNAL
+; THESE ARE IDENTICAL TO THE GENERIC Z80 ASSIGNMENTS
 ;
-; DUO Z80 IM2 INTERRUPTS
-;
-INT_UART0	.EQU	7	; UART 0
-INT_UART1	.EQU	6	; UART 1 ?????
-INT_CTC0A	.EQU	0	; ZILOG CTC 0, CHANNEL A
-INT_CTC0B	.EQU	1	; ZILOG CTC 0, CHANNEL B
-INT_CTC0C	.EQU	2	; ZILOG CTC 0, CHANNEL C
-INT_CTC0D	.EQU	3	; ZILOG CTC 0, CHANNEL D
-INT_SIO0	.EQU	6	; ZILOG SIO 0, CHANNEL A & B
-INT_SIO1	.EQU	8	; ZILOG SIO 1, CHANNEL A & B
-INT_PIO0A	.EQU	9	; ZILOG PIO 0, CHANNEL A
-INT_PIO0B	.EQU	10	; ZILOG PIO 0, CHANNEL B
-INT_PIO1A	.EQU	11	; ZILOG PIO 1, CHANNEL A
-INT_PIO1B	.EQU	12	; ZILOG PIO 1, CHANNEL B
-
-  #ENDIF
-
-  #IF (PLATFORM == PLT_NABU)
-;
-; NABU Z80 IM2 INTERRUPTS
-;
-INT_HCAARCV	.EQU	0	; UART 0
-INT_HCAASND	.EQU	1	; UART 1 ?????
-INT_NABUKB	.EQU	2	; ZILOG CTC 0, CHANNEL A
-INT_VDP		.EQU	3	; ZILOG CTC 0, CHANNEL B
-INT_OPTCRD0	.EQU	4	; ZILOG CTC 0, CHANNEL C
-INT_OPTCRD1	.EQU	5	; ZILOG CTC 0, CHANNEL D
-INT_OPTCRD2	.EQU	6	; ZILOG SIO 0, CHANNEL A & B
-INT_OPTCRD3	.EQU	7	; ZILOG SIO 1, CHANNEL A & B
-
-  #ENDIF
-
-  #IF ((PLATFORM != PLT_MBC) & (PLATFORM != PLT_DUO) & (PLATFORM != PLT_NABU))
-
-; GENERIC Z80 M2 INTERRUPTS
-
 INT_CTC0A	.EQU	0	; ZILOG CTC 0, CHANNEL A
 INT_CTC0B	.EQU	1	; ZILOG CTC 0, CHANNEL B
 INT_CTC0C	.EQU	2	; ZILOG CTC 0, CHANNEL C
@@ -1080,11 +1099,9 @@ INT_PIO0A	.EQU	9	; ZILOG PIO 0, CHANNEL A
 INT_PIO0B	.EQU	10	; ZILOG PIO 0, CHANNEL B
 INT_PIO1A	.EQU	11	; ZILOG PIO 1, CHANNEL A
 INT_PIO1B	.EQU	12	; ZILOG PIO 1, CHANNEL B
-
-  #ENDIF
-
 #ENDIF
 
+
 #DEFINE IVT(INTX) HB_IVT+(INTX * 4)+1
 #DEFINE VEC(INTX) INTX*2
 

Source/HBIOS/tms.asm

@@ -66,8 +66,8 @@ TMS_CMDREG	.EQU	$BF		; READ STATUS / WRITE REG SEL
 #IF (TMSMODE == TMSMODE_MSXKBD)
 TMS_DATREG	.EQU	$98		; READ/WRITE DATA
 TMS_CMDREG	.EQU	$99		; READ STATUS / WRITE REG SEL
-TMS_KBDDATA	.EQU	$E0		; KBD CTLR DATA PORT
-TMS_KBDST	.EQU	$E1		; KBD CTLR STATUS/CMD PORT
+TMS_KBDDATA	.EQU	$60		; KBD CTLR DATA PORT
+TMS_KBDST	.EQU	$64		; KBD CTLR STATUS/CMD PORT
 		DEVECHO	"MSXKBD"
 #ENDIF
 ;
@@ -179,10 +179,8 @@ NABUKBENABLE	.SET	TRUE		; INCLUDE NABU KEYBOARD SUPPORT
 ;======================================================================
 ;
 TMS_PREINIT:
-#IF (NABUKBENABLE == TRUE)
-	CALL NABUKB_PREINIT
-#ENDIF
-	; DISABLE INTERRUPT GENERATION
+	; DISABLE INTERRUPT GENERATION UNTIL AFTER INTERRUPT HANDLER
+	; HAS BEEN INSTALLED.
 	LD	A, (TMS_INITVDU_REG_1)
         RES	TMSINTEN, A             ; RESET INTERRUPT ENABLE BIT
 	LD	(TMS_INITVDU_REG_1), A
@@ -228,10 +226,10 @@ TMS_INIT:
 	PRTS("COLECO$")
 #ENDIF
 #IF (TMSMODE == TMSMODE_MSXKBD)
-	PRTS("RCKBD$")
+	PRTS("MSXKBD$")
 #ENDIF
 #IF (TMSMODE == TMSMODE_MSX9958)
-	PRTS("RC_V9958$")
+	PRTS("MSXV9958$")
 #ENDIF
 #IF (TMSMODE == TMSMODE_NABU40)
 	PRTS("NABU-40$")
@@ -255,16 +253,16 @@ TMS_INIT1:
 	CALL 	TMS_CRTINIT		; SETUP THE TMS CHIP REGISTERS
 	CALL	TMS_LOADFONT		; LOAD FONT DATA FROM ROM TO TMS STRORAGE
 	CALL	TMS_CLEAR		; CLEAR SCREEN, HOME CURSOR
-#IF (TMSMODE == TMSMODE_N8)
+#IF (PPKENABLE)
 	CALL	PPK_INIT		; INITIALIZE PPI KEYBOARD DRIVER
 #ENDIF
-#IF ((TMSMODE == TMSMODE_MSXKBD) | (TMSMODE == TMSMODE_MBC) | (TMSMODE == TMSMODE_DUO))
+#IF (KBDENABLE)
 	CALL	KBD_INIT		; INITIALIZE 8242 KEYBOARD DRIVER
 #ENDIF
-#IF MKYENABLE
+#IF (MKYENABLE)
 	CALL	MKY_INIT		; INITIALIZE MKY KEYBOARD DRIVER
 #ENDIF
-#IF ((TMSMODE == TMSMODE_NABU40) | (TMSMODE == TMSMODE_NABU80))
+#IF (NABUKBENABLE)
 	CALL	NABUKB_INIT		; INITIALIZE NABU KEYBOARD DRIVER
 #ENDIF
 
@@ -280,14 +278,24 @@ TMS_INIT1:
 	LD	(IVT(INT_VDP)),HL	; IVT INDEX
   #ENDIF
 ;
+	; ENABLE VDP INTERRUPTS NOW
 	LD	A, (TMS_INITVDU_REG_1)
 	SET	TMSINTEN,A		; SET INTERRUPT ENABLE BIT
 	LD	(TMS_INITVDU_REG_1),A
 	LD	C, TMSCTRL1
 	CALL	TMS_SET
+;
+  #IF ((TMSMODE == TMSMODE_NABU40) | (TMSMODE == TMSMODE_NABU80))
+	; ENABLE VDP INTERRUPTS ON NABU INTERRUPT CONTROLLER
+	LD	A,14			; PSG R14 (PORT A DATA)
+	OUT	(NABU_RSEL),A		; SELECT IT
+	LD	A,(NABU_CTLVAL)		; GET NABU CTL PORT SHADOW REG
+	SET	4,A			; ENABLE VDP INTERRUPTS
+	LD	(NABU_CTLVAL),A		; UPDATE SHADOW REG
+	OUT	(NABU_RDAT),A		; WRITE TO HARDWARE
+  #ENDIF
 ;
 #ENDIF
-
 ;
 	; ADD OURSELVES TO VDA DISPATCH TABLE
 	LD	BC,TMS_FNTBL		; BC := FUNCTION TABLE ADDRESS
@@ -320,38 +328,37 @@ TMS_FNTBL:
 	.DW	TMS_VDAFIL
 	.DW	TMS_VDACPY
 	.DW	TMS_VDASCR
-#IF (TMSMODE == TMSMODE_N8)
+#IF (PPKENABLE)
 	.DW	PPK_STAT
 	.DW	PPK_FLUSH
 	.DW	PPK_READ
 #ENDIF
-#IF  ((TMSMODE == TMSMODE_MSXKBD) | (TMSMODE == TMSMODE_MBC) | (TMSMODE == TMSMODE_DUO))
+#IF (KBDENABLE)
   	.DW	KBD_STAT
   	.DW	KBD_FLUSH
   	.DW	KBD_READ
 #ENDIF
-#IF ((TMSMODE == TMSMODE_NABU40) | (TMSMODE == TMSMODE_NABU80))
+#IF (MKYENABLE)
+  	.DW	MKY_STAT
+  	.DW	MKY_FLUSH
+  	.DW	MKY_READ
+#ENDIF
+#IF (NABUKBENABLE)
 	.DW	NABUKB_STAT
 	.DW	NABUKB_FLUSH
 	.DW	NABUKB_READ
 #ENDIF
-#IF ((TMSMODE == TMSMODE_MSX) | (TMSMODE == TMSMODE_MSX9958) | (TMSMODE == TMSMODE_SCG) | (TMSMODE == TMSMODE_COLECO))
-  #IF MKYENABLE
-  	.DW	MKY_STAT
-  	.DW	MKY_FLUSH
-  	.DW	MKY_READ
-  #ELSE
+#IF ((!PPKENABLE) & (!KBDENABLE) & (!NABUKBENABLE) & (!MKYENABLE))
   	.DW	TMS_STAT
   	.DW	TMS_FLUSH
   	.DW	TMS_READ
-  #ENDIF
 #ENDIF
 	.DW	TMS_VDARDC
 #IF (($ - TMS_FNTBL) != (VDA_FNCNT * 2))
 	.ECHO	"*** INVALID TMS FUNCTION TABLE ***\n"
 	!!!!!
 #ENDIF
-
+;
 TMS_VDAINI:
 	; RESET VDA
 	; CURRENTLY IGNORES VIDEO MODE AND BITMAP DATA
@@ -359,7 +366,7 @@ TMS_VDAINI:
 	CALL	TMS_CLEAR		; CLEAR SCREEN
 	XOR	A			; SIGNAL SUCCESS
 	RET
-
+;
 TMS_VDAQRY:
 	LD	C,$00			; MODE ZERO IS ALL WE KNOW
 	LD	D,TMS_ROWS		; ROWS
@@ -367,7 +374,7 @@ TMS_VDAQRY:
 	LD	HL,0			; EXTRACTION OF CURRENT BITMAP DATA NOT SUPPORTED YET
 	XOR	A			; SIGNAL SUCCESS
 	RET
-
+;
 TMS_VDARES:
 #IF (CPUFAM == CPU_Z180)
 	CALL	TMS_Z180IO

Source/HBIOS/updater.asm

@@ -131,7 +131,7 @@
 ;
 #INCLUDE	"std.asm"
 ;
-HBX_BNKSEL	.EQU	$FE2B
+HBX_BNKSEL	.EQU	$FFF3
 ;
 #DEFINE	HB_DI	DI
 #DEFINE	HB_EI	EI

Source/HBIOS/usrrom.asm

@@ -1,34 +1,114 @@
 ;
-; USRROM	TEMPLATE FOR A CUSTOM USER ROM
+;=============================================================================
+; USRROM.ASM - SAMPLE CUSTOM ROM USER APPLICATION
+;=============================================================================
 ;
-#INCLUDE	"std.asm"
+; VERSION 1.1	BY - MARTINR	31-MAY-2024
 ;
-CR	.EQU    0DH
-LF	.EQU    0AH
+; THIS IS AN EXAMPLE USER ROM APPLICATION THAT IS AUTOMATICALLY INCLUDED
+; IN THE ROMWBW ROM.  IT IS INVOKED FROM THE BOOT LOADER USING THE
+; 'U' (USER APPLICATION) OPTION.  YOU MAY REPLACE THIS SOURCE CODE WITH
+; YOUR OWN CUSTOM CODE.  IT WILL BE ASSEMBLED AND INCLUDED WITH YOUR
+; CUSTOM ROM BUILD.  REFER TO THE ROMWBW USER GUIDE FOR MORE INFORMATION.
 ;
-	.ORG    USR_LOC
+; THANKS AND CREDIT TO MARTIN R. FOR PROVIDING THIS APPLICATION!
 ;
-	LD	SP,USR_END
+; - THE SOURCE IS ASSEMBLED WITH THE TASM ASSEMBLER.
+; - THE APPLICATION MUST START (ORG) AT USR_LOC ($100)
+; - THE APPLICATION MUST BE EXACTLY USR_SIZ BYTES.  THIS IS AUTOMATICALLY
+;   ENFORCED AT THE END OF THE FILE.
+; - AT EXIT, THE APPLICATION SHOULD RETURN TO THE BOOT LOADER USING THE
+;   HBIOS WARM RESET FUNCTION AS DEMONSTRATED BELOW.
+; - THE APPLICATION MAY MAKE HBIOS FUNCTION CALLS WITHOUT RESTRICTION,
+;   BUT CANNOT USE ANY OS (CP/M) FUNCTIONS BECAUSE NO OS IS LOADED.
+; - THE APPLICATION MAY NOT CHANGE THE INTERRUPT MODE (WHICH IS DEFINED
+;   IN THE ROM CONFIGURATION).  THE SYSTEM'S INTERRUPT
+;   MODE CAN BE QUERIED BY AN HBIOS API CALL IF DESIRED.
+; - THE APPLICATION MAY TEMPORARILY DISABLE INTERRUPTS BY BRACKETING
+;   SECTIONS OF CODE WITH DI/EI AS NEEDED.  IF INTERRUPTS ARE
+;   TEMPORARILY DISABLED, THEY SHOULD NOT SHOULD NOT
+;   BE LEFT DISABLED ACROSS HBIOS API CALLS.
 ;
-	LD	HL,BOOTMSG		; INTRODUCTION
+; INCLUDE STD.ASM WHICH DEFINES SOME KEY EQUATES USED BELOW.  MOST
+; IMPORTANT ARE USR_LOC, USR_SIZ, AND USR_END.  IT ALSO DEFINES EQUATES
+; FOR THE HBIOS FUNCTION CALLS.
+;
+#INCLUDE "std.asm"
+;
+	.LIST
+;
+CR	.EQU	0DH
+LF	.EQU	0AH
+;
+ROWS	.EQU	8		; NUMBER OF PIXEL ROWS PER CHARACTER
+COLS	.EQU	8		; NUMBER OF PIXEL COLUMNS PER CHARACTER
+;
+; APPLICATION WILL WILL BE LOADED AT USR_LOC.  THEREFORE, THE CODE
+; MUST "ORG" AT THIS ADDRESS.  TO CHANGE THE LOAD LOCATION OF THIS
+; CODE, YOU CAN UPDATE USR_LOC IN STD.ASM.
+;
+	.ORG	USR_LOC
+;
+; PLACE STACK AT THE TOP OF AVAILABLE RAM (JUST BELOW THE HBIOS PROXY).
+;
+	LD	SP,HBX_LOC
+;
+;*****************************************************************************
+;
+; DISPLAY BANNER
+;
+	LD	A,CR
+	CALL	COUT
+	LD	A,LF
+	CALL	COUT		; COUT PRESERVES AF, BC, DE, & HL
+	CALL	COUT
+	CALL	COUT
+;
+	LD	HL,BANNER+1	; POINTER TO THE 8X8 CHARACTER BITMAPS
+	LD	D,ROWS		; D=ROWS PER CHARACTER
+;
+NXTLIN:	LD	A,(BANNER)	; FETCH THE NUMBER OF CHARACTERS IN THE BANNER
+	LD	E,A
+;
+NXTCHR:	LD	C,(HL)		; FETCH THE BIT PATTERN FOR THE CHARACTER-LINE
+	LD	B,COLS		; 8 COLUMNS PER CHARACTER-LINE
+NXTBIT:	SLA	C		; SHIFT-LEFT THE NEXT BIT INTO THE CARRY FLAG
+	JR	C, DOT
+	LD	A,' '		; IF NO-CARRY THEN PRINT A 'SPACE'
+	JR	GAP
+DOT:	LD	A,'X'		; IF A CARRY THEN PRINT AN 'X'
+GAP:	CALL	COUT		; COUT PRESERVES AF, BC, DE, & HL
+	DJNZ	NXTBIT		; GO ROUND AND PRINT ALL 8 BITS FOR THE CHARACTER-LINE
+;
+	INC	HL		; POINT TO NEXT CHARACTER-LINE
+	DEC	E
+	JR	NZ,NXTCHR	; GO ROUND AND PRINT THE NEXT CHARACTER
+;
+	LD	A,CR		; REACHED THE END OF A LINE, SO PRINT CRLF
+	CALL	COUT		; COUT PRESERVES AF, BC, DE, & HL
+	LD	A,LF
+	CALL	COUT
+;
+	DEC	D
+	JR	NZ,NXTLIN	; GO ROUND AND PRINT THE NEXT LINE
+;
+;*****************************************************************************
+;
+; FINISHED DISPLAYING THE BANNER, NOW END THE 'APP' TIDILY
+;
+	LD	HL,MESSAGE		; PRINT A MESSAGE
 	CALL	PRTSTR
-;
-	CALL	CIN			; DO STUFF
+	CALL	CIN			; AND WAIT FOR A KEYPRESS
 ;
 	LD	B,BF_SYSRESET		; SYSTEM RESTART
 	LD	C,BF_SYSRES_WARM	; WARM START
-	CALL	$FFF0			; CALL HBIOS
-;       RET
+	RST	08			; CALL HBIOS (DOES NOT RETURN)
 ;
+;*****************************************************************************
 ;
+; SUPPORT ROUTINES
 ;
-; PRINT A STRING AT ADDRESS SPECIFIED IN HL
-; STRING MUST BE TERMINATED BY '$'
-; USAGE:
-;   LD	HL,MYSTR
-;   CALL PRTSTR
-;   ...
-;   MYSTR: .DB  "HELLO$"
+; PRINT A STRING OF CHARACTERS STARTING AT HL, ENDING WITH '$'
 ;
 PRTSTR:	LD	A,(HL)
 	INC	HL
@@ -43,8 +123,8 @@ COUT:	PUSH	AF
 	PUSH	BC
 	PUSH	DE
 	PUSH	HL
-	LD	B,01H
-	LD	C,80H
+	LD	B,BF_CIOOUT
+	LD	C,CIO_CONSOLE
 	LD	E,A
 	RST	08
 	POP	HL
@@ -58,8 +138,8 @@ COUT:	PUSH	AF
 CIN:	PUSH	BC
 	PUSH	DE
 	PUSH	HL
-	LD	B,00H
-	LD	C,80H
+	LD	B,BF_CIOIN
+	LD	C,CIO_CONSOLE
 	RST	08
 	LD	A,E
 	POP	HL
@@ -67,18 +147,60 @@ CIN:	PUSH	BC
 	POP	BC
 	RET
 ;
-BOOTMSG:.DB	CR,LF,CR,LF
-	.DB	"No User ROM Installed."
-	.DB	CR,LF,CR,LF
+;*****************************************************************************
+;
+; DATA SECTION
+;
+BANNER:
+	.DB	6	; THE NUMBER OF CHARACTERS IN THE BANNER
+;
+#IF FALSE
+	; UPPER CASE LOGO ("ROMWBW")
+	.DB	%01111100, %00011100, %01000001, %01000001, %01111100, %01000001
+	.DB	%01000010, %00100010, %01100011, %01000001, %01000010, %01000001
+	.DB	%01000001, %01000001, %01010101, %01000001, %01000001, %01000001
+	.DB	%01000001, %01000001, %01001001, %00100010, %01111110, %00100010
+	.DB	%01111110, %01000001, %01000001, %00100010, %01000010, %00100010
+	.DB	%01000100, %01000001, %01000001, %00101010, %01000001, %00101010
+	.DB	%01000010, %00100010, %01000001, %00101010, %01000001, %00101010
+	.DB	%01000001, %00011100, %01000001, %00010100, %01111110, %00010100
+#ENDIF
+;
+#IF TRUE
+	; UPPER AND LOWER CASE LOGO ("RomWBW")
+	.DB	%00000000, %00000000, %00000000, %00000000, %00000000, %00000000
+	.DB	%01111000, %00000000, %00000000, %01000100, %01111000, %01000100
+	.DB	%01000100, %00000000, %00000000, %01000100, %01000100, %01000100
+	.DB	%01000100, %00111000, %00101000, %01000100, %01000100, %01000100
+	.DB	%01111000, %01000100, %01010100, %01010100, %01111000, %01010100
+	.DB	%01010000, %01000100, %01010100, %01010100, %01000100, %01010100
+	.DB	%01001000, %01000100, %01000100, %01101100, %01000100, %01101100
+	.DB	%01000100, %00111000, %01000100, %01000100, %01111000, %01000100
+#ENDIF
+;
+MESSAGE:
+	.DB	CR,LF,LF
+	.DB	"This is an example User Application - why not create your own?",CR,LF
+	.DB	"Please see the relevant User Guide section for more information."
+	.DB	CR,LF,LF,LF
 	.DB	"Press a key to return to Boot Loader.$"
 ;
 ; IT IS CRITICAL THAT THE FINAL BINARY BE EXACTLY USR_SIZ BYTES.
-; THIS GENERATES FILLER AS NEEDED.
-;				
+; THIS GENERATES FILLER AS NEEDED.  IT WILL ALSO FORCE AN ASSEMBLY
+; ERROR IF THE SIZE EXCEEDS THE SPACE ALLOCATED.
+;
 SLACK	.EQU	(USR_END - $)
-	.FILL	SLACK,00
+;
+#IF (SLACK < 0)
+	.ECHO	"*** USRAPP IS TOO BIG!!!\n"
+	!!!	; FORCE AN ASSEMBLY ERROR
+#ENDIF
+;
+	.FILL	SLACK,$00
 	.ECHO	"User ROM space remaining: "
 	.ECHO	SLACK
 	.ECHO	" bytes.\n"
-        .END
-
+;
+	.NOLIST
+;
+	.END

Source/HBIOS/util.asm

@@ -101,8 +101,8 @@ PRTCH:
 	PUSH	AF
 	LD	A,(HL)
 	CALL	COUT
-	POP	AF
 	INC	HL
+	POP	AF
 	EX	(SP),HL
 	RET
 ;

Source/Images/Common/UTILS/BBCDIST.SUB

@@ -1,13 +0,0 @@
-; patch BBCBASIC with BBCDIST
-; need M80 and L80
-xsub
-m80 =bbcdist/z
-l80 bbcdist,bbcdist/n/e
-ddt bbcbasic.org
-ibbcdist.com
-r
-g0
-save 58 bbcbasic.com
-era bbcdist.rel
-era bbcdist.com
-