Finalize S100 FPGA Z80 Onboard VGA/PS2 Support

- RomWBW will now "follow" the S100 monitors console selection for all 3 possibilities (USB Serial, Propeller Console, and Onboard VGA/PS2).

Doc/ChangeLog.txt

@@ -14,7 +14,7 @@ Version 3.5
 - DDW: Added support for Duodyne Media board
 - WBW: Auto restore TMS video on user reset (CP/M warm boot)
 - L?B: Added support for NABU w/ RomWBW Option Board
-- M?P: Reorganization of Doc directory introducing subfolders
+- MAP: Reorganization of Doc directory introducing subfolders
 - WBW: Upgraded BBCBASIC to v5.00
 - W?S: Updated FLASH utility to v1.3.9
 - WBW: Support RCBus PS/2 Keyboard (EP/Sally)
@@ -31,6 +31,9 @@ Version 3.5
 - M?R: Added hour/minute/second display to timer app
 - WBW: Substantial customization of NZ-COM disk image
 - WBW: Refactor build post-processing (ZRC, ZZRCC, etc.)
+- MAP: Improved section Real Time Clock in User Guide document
+- WBW: Support for Hitachi HD44780-based LCD display
+- DRJ: Added support for Genesis STD Bus Z180 platform
 
 Version 3.4
 -----------
@@ -699,4 +702,4 @@ interrupts disabled the BIOS will now start OK even if some vagrant
 hardware is asserting an interrupt (DISKIO).  Seems like this is better
 anyway -- general idea is that we only enable interupts precisely
 when desired for very specific controled purposes since there is no
-concept of interrupt dispatching available.
+concept of interrupt dispatching available.

Doc/Contrib/ZSystem.txt

@@ -20,7 +20,7 @@ Beyond the construction and integration of the actual DOS itself, the majority o
 
 The remainder of this document details the changes I made as I went along.  In all cases, my goal was to keep the result as close to the original distribution as possible.  I started by copying all of the files from the distribution (contained in zsdos2.zip) into Support\ZSDOS.  From there I tested, modified, updated, and customized as documented below.  Finally, I cherry picked files that made sense to include on the ZSystem ROM disks.
 
-1. CLOCKS.DAT has been updated to include the RomWBW clock driver, HBCLK.  I have also added the SIMHCLOK clock driver.
+1. CLOCKS.DAT has been updated to include the RomWBW clock driver, WBWCLK.  I have also added the SIMHCLOK clock driver.
 
 2. STAMPS.DAT has been replaced with an updated version.  The update was called STAMPS11.DAT and was found on the Walnut Creek CP/M CDROM.  The original version has a bug that prevents RSX (resident system extension) mode to load properly.
 

ReadMe.md

@@ -3,7 +3,7 @@
 **RomWBW ReadMe** \
 Version 3.5 \
 Wayne Warthen  ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \
-21 Aug 2024
+04 Sep 2024
 
 # Overview
 

ReadMe.txt

@@ -1,6 +1,6 @@
 RomWBW ReadMe
 Wayne Warthen (wwarthen@gmail.com)
-21 Aug 2024
+04 Sep 2024
 
 
 

Source/Apps/rtc.asm

@@ -33,6 +33,8 @@
 ;
 ;[2023/07/07] v1.9 Support DUODYNE
 ;
+;[2024/09/02] v1.10  Support Genesis STD Z180
+;
 ; Constants
 ;
 mask_data	.EQU	%10000000	; RTC data line
@@ -52,6 +54,7 @@ PORT_RCZ280	.EQU	$C0		; RTC port for RCZ280
 PORT_MBC	.EQU	$70		; RTC port for MBC
 PORT_RPH	.EQU	$84		; RTC port for RHYOPHYRE
 PORT_DUO	.EQU	$94		; RTC port for DUODYNE
+PORT_STDZ180 .EQU $84         ; RTC Port for STD Bus Z180 board
 
 
 BDOS		.EQU	5		; BDOS invocation vector
@@ -1143,7 +1146,13 @@ HINIT:
 	CP	17		; DUODYNE
 	JP	Z,RTC_INIT2
 ;
-	; Unknown platform
+	LD	C,PORT_STDZ180
+	LD	DE,PLT_STDZ180
+	CP	21		; STD Z180
+	JP	Z,RTC_INIT2
+;
+
+; Unknown platform
 	LD	DE,PLTERR	; BIOS error message
 	LD	C,9		; BDOS string display function
 	CALL	BDOS		; Do it
@@ -1769,6 +1778,7 @@ PLT_RCZ280	.TEXT	", RCBus Z280 RTC Module Latch Port 0xC0\r\n$"
 PLT_MBC		.TEXT	", MBC RTC Latch Port 0x70\r\n$"
 PLT_RPH		.TEXT	", RHYOPHYRE RTC Latch Port 0x84\r\n$"
 PLT_DUO		.TEXT	", DUODYNE RTC Latch Port 0x70\r\n$"
+PLT_STDZ180 .TEXT ", STD Z180 RTC Module latch port 0x84\r\n$"
 
 ;
 ; Generic FOR-NEXT loop algorithm

Source/Doc/Catalog.md

@@ -217,9 +217,9 @@ on using the applications and files listed.
 | `INITDIR.COM`  | ZSDOS      | ZSDOS Prepare disks for P2DOS Stamps |
 | `KERMIT.COM`   |     --     | Generic CP/M 2.2 Kermit communication application |
 | `LBREXT.COM`   |     --     | Extract library files |
-| `LDDS.COM`     | ZSDOS      | Clock driver |
-| `LDNZT.COM`    | ZSDOS      | Clock driver |
-| `LDP2D.COM`    | ZSDOS      | Clock driver |
+| `LDDS.COM`     | ZSDOS      | Load DateStamper date/time stamping resident extension |
+| `LDNZT.COM`    | ZSDOS      | Load NZT date/time stamping resident extension |
+| `LDP2D.COM`    | ZSDOS      | Load P2DOS date/time stamping resident extension |
 | `LIB.COM`      |     --     | DRI Library manager |
 | `LINK.COM`     |     --     | DRI CPM relocatable linker |
 | `LOAD.COM`     |     --     | DRI hex file loader into memory |
@@ -229,7 +229,7 @@ on using the applications and files listed.
 | `PMARC.COM`    |     --     | LHA file compressor |
 | `PMEXT.COM`    |     --     | Extractor for PMARC archives |
 | `PUTBG.COM`    | ZSDOS      | ZSDOS Prepare disk for backgrounder |
-| `PUTDS.COM`    | ZSDOS      | ZSDOS Prepare disk for datestamper |
+| `PUTDS.COM`    | ZSDOS      | ZSDOS Prepare disk for datestamper date/time stamping|
 | `RELOG.COM`    | ZSDOS      | ZSDOS relog disks after program that bypasses BDOS |
 | `RMAC.COM`     |     --     | DRI Relocatable Macro Assembler |
 | `SETTERM.COM`  | ZSDOS      | ZSDOS Installs terminal control codes into DateSamper utilities |

Source/Doc/SystemGuide.md

@@ -847,12 +847,19 @@ more of the defined media types.
 | MID_FD111     | 9      | 8" 1.11M Floppy                            |
 | MID_HD1K      | 10     | Hard Disk (LBA) w/ 1024 directory entries  |
 
+**NOTE**: HBIOS does not actually differentiate between MID_HD512 and
+MID_HD1K.  The use of these two formats is determined by the use of a
+partition table on the media and is implemented by the operating
+system itself.  HBIOS treats all hard disks as raw sectors. See
+[Function 0x18 -- Disk Media (DIOMEDIA)] for more information on the
+Media ID byte returned.
+
 HBIOS supports both Cylinder/Head/Sector (CHS) and Logical Block 
 Addresses (CHS) when locating a sector for I/O (see DIOSEEK function). 
 For devices that are natively CHS (e.g., floppy disk), the HBIOS driver 
 can convert LBA values to CHS values according to the geometry of the 
 current media.  For devices that are natively LBA (e.g., hard disk), the
- HBIOS driver simulates CHS using a fictitious geometry provided by the 
+HBIOS driver simulates CHS using a fictitious geometry provided by the 
 driver (typically 16 sectors per track and 16 heads per cylinder).
 
 ### Function 0x10 -- Disk Status (DIOSTATUS)
@@ -1065,6 +1072,12 @@ Report the Media ID (E) for the for media in the specified Disk Unit
 will be performed.  The Status (A) is a standard HBIOS result code. If 
 there is no media in device, function will return an error status.
 
+**NOTE**: This function will always return MID_HD512 for hard disk
+devices.  MID_HD1K is provided for use internally by operating systems
+that provide different filsystem formats depending on the partition
+table.  This function cannot be used to determine if an HD1K formatted
+partition exists on the hard disk.
+
 ### Function 0x19 -- Disk Define Media (DIODEFMED)
 
 | **Entry Parameters**                   | **Returned Values**                    |
@@ -1098,7 +1111,7 @@ DIOMEDIA function to force this if desired.
 | **Entry Parameters**                   | **Returned Values**                    |
 |----------------------------------------|----------------------------------------|
 | B: 0x1B                                | A: Status                              |
-| C: Disk Unit                           | D: Heads                               |
+| C: Disk Unit                           | D: Heads / LBA                         |
 |                                        | E: Sectors                             |
 |                                        | HL: Cylinder Count                     |
 |                                        | BC: Block Size                         |
@@ -1108,7 +1121,11 @@ device uses LBA mode addressing natively, then the drivers simulated
 geometry will be returned. The Status (A) is a standard HBIOS result 
 code.  If the media is unknown, an error will be returned.
 
-Heads (D) refers to the number of heads per cylinder.  Sectors (E)
+LBA capability is indicated by D:7.  When set, the device is capable
+of LBA addressing.  Refer to [Function 0x12 -- Disk Seek (DIOSEEK)]
+for more information on specifying LBA vs. CHS addresses.
+
+Heads (D:6-0) refers to the number of heads per cylinder.  Sectors (E)
 refers to the number of sectors per track.  Cylinder Count (HL) is the
 total number of cylinders addressable for the media.  Block Size (BC)
 is the number of bytes in one sector.

Source/Doc/UserGuide.md

@@ -262,6 +262,7 @@ is discussed in [Customizing RomWBW].
 | [EP Mini-ITX Z180]^11^                                      | RCBus?  | EPITX_std.rom                | 115200        |
 | [NABU w/ RomWBW Option Board]^10^                           | NABU    | NABU_std.rom                 | 115200        |
 | [S100 FPGA Z80]^9^                                          | S100    | FZ80_std.rom                 | 9600          |
+| [Genesis STD Z180]^12^                                      | STD     | GMZ180_std.rom               | 115200        |
 
 | ^1^Designed by Andrew Lynch
 | ^2^Designed by Sergey Kiselev
@@ -274,6 +275,7 @@ is discussed in [Customizing RomWBW].
 | ^9^Designed by John Monahan
 | ^10^Designed by Les Bird
 | ^11^Designed by Alan Cox
+| ^12^Designed by Doug Jackson
 
 RCBus refers to Spencer Owen's RC2014 bus specification and derivatives
 including RC26, RC40, RC80, and BP80.
@@ -2378,28 +2380,12 @@ call "ZSYS.SYS".  For example:
   or MAP, you may need to run “RELOG” to get the drive properly 
   recognized by ZSDOS.
 
-* RomWBW fully supports both DateStamper and P2DOS file date/time
-  stamping.  You must load the desired stamping module (`LDDS` for
-  DateStamper or `LDP2D` for P2DOS).  This could be automated using
-  a `PROFILE.SUB` file.  Follow the ZSDOS documentation to initialize
-  a disk for stamping.
-
 * ZSVSTAMP expects to be running under the ZCPR 3.X command processor. 
   By default, RomWBW uses ZCPR 1.0 (intentionally, to reduce space usage) 
   and ZSVSTAMP will just abort in this case. It will work fine if you 
   implement NZCOM. ZSVSTAMP is included solely to facilitate usage 
   if/when you install NZCOM.
 
-* FILEDATE only works with DateStamper style date stamping. If you run 
-  it on a drive that is not initialized for DateStamper, it will complain 
-  `FILEDATE, !!!TIME&.DAT missing`. This is normal and just means that 
-  you have not initialized that drive for DateStamper (using PUTDS).
-
-* ZXD will handle either DateStamper or P2DOS type date stamping. 
-  However, it **must** be configured appropriately. As distributed, it will 
-  look for P2DOS date stamps. Use ZCNFG to reconfigure it for P2DOS if 
-  that is what you are using.
-
 * Many of the tools can be configured (using either ZCNFG or DSCONFIG). 
   The configuration process modifies the actual application file itself. 
   This will fail if you try to modify one that is on the ROM disk because 
@@ -2410,10 +2396,6 @@ call "ZSYS.SYS".  For example:
   SETTERM. So, run SETTERM on DSCONFIG before using DSCONFIG to configure 
   DATSWEEP!
 
-* After using PUTDS to initialize a directory for ZDS date stamping, I 
-  am finding that it is necessary to run RELOG before the stamping 
-  routines will actually start working.
-
 * Generic CP/M PIP and ZSDOS path searching do not mix well if you use 
   PIP to copy to or from a directory in the ZSDOS search path. Best to 
   use COPY from the ZSDOS distribution.
@@ -3112,8 +3094,11 @@ SAMPLE2.TXT ==> 4:/SAMPLE2.TXT ... [OK]
 RomWBW supports a variety of real time clock hardware.  If your
 system has this hardware, then it will be able to maintain the
 current date and time even while your system is turned off.
+
 Additionally, depending on the operating system being used, you may be
 able to utilize date/time stamping of files.
+To facilitate this a CP/M clock driver (WBWCLK) has been included 
+inside `CLOCKS.DAT` that will read the clock via a RomWBW HBIOS call
 
 You can determine if your system has a real time clock present (and
 functioning) by looking at the boot messages.  Here is an example of
@@ -3139,6 +3124,8 @@ RomwWBW includes two utilities for displaying or setting the date/time
 stored by the RTC.  They are both a bit different and are briefly
 described below.
 
+A third utility `TESTCLOK` is also included as part of ZSDOS
+
 ### WDATE Utility
 
 The `WDATE` utility (contributed by Kevin Boone) is an application
@@ -3218,6 +3205,57 @@ Do **not** enable charging unless you are sure that your system
 supports this.  If your RTC is being powered by a normal battery, it
 would be dangerous to enable charging.
 
+### TESTCLOK Utility
+
+The `TESTCLOK` utility is used to test a selected CPM clock driver 
+loaded from the CLOCKS.DAT file. After selecting the location of CLOCKS.DAT 
+and the clock driver (45. WBWCLK) it displays the currently configured time 
+until a key is pressed. 
+
+```
+A>testclok
+
+TESTCLOK V1.0    Copyright (C) 1988    H.F. Bower / C.W. Cotrill
+
+Extract Clock from Library ([Y]/N) : Y
+Location of CLOCKS.DAT [A0:] : <RETURN> 
+
+  1. ACTRIX             2. ALSPA              3. AMPRO-LB         
+  4. ANLYTCL-PRD        5. AP2-CDZ180         6. AP2-THND/MT      
+  7. AP2-TIMASTR        8. AP2E+PCP-TM        9. AP2E+PCPI        
+ 10. AP2E-THUNDR       11. AP2E-TMASTR       12. BIG-BD-II        
+ 13. BP-BIOS           14. CCS-WALLCLK       15. CPUPRO-SSB1      
+ 16. ELECTR-MFIO       17. EPSON-QX10        18. ETS180IO+        
+ 19. H19-SUPER19       20. H19-ULTRA         21. H19-WATZMAN      
+ 22. H89-BITZERO       23. H89-PC12          24. H89-WIDGET       
+ 25. H89-WISE          26. H89UTI            27. HEATH-BIOS       
+ 28. HOUSEMASTER       29. K83-HOLMES        30. KAYPRO-84        
+ 31. KENMOR-ZTIM       32. KPRO-ADVENT       33. KPRO-LEGACY      
+ 34. MD3-MACK          35. MTN100K-DAY       36. ONEAC-ON!        
+ 37. OTRANA-ATCH       38. P&T-HEARTBT       39. QTSYS-S100       
+ 40. RELATIVE          41. S100-5832         42. SB180-HRTBT      
+ 43. SB180-XBIOS       44. SIMHCLOK          45. WBWCLK           
+ 46. XEROX-820         47. ZSDOS-BIOS       
+
+Enter Clock Driver Selection : 45
+
+..Loading : WBWCLK      ... 
+Linking Clock Module... OK
+RomWBW HBIOS Clock      1.1
+
+RomWBW Series HBIOS Clock
+
+Press any key to quit...
+
+ 19 Oct 2023  14:24:34
+```
+
+Since this runs at the CPM driver level it is useful as an end-to-end test
+to prove that date time stamping is able to read the correct time
+
+The `TESTCLOK` utility is provided by ZSDOS, plese see the ZSDOS Manual 
+for further information
+
 ## Date/Time File Stamping
 
 If an RTC is available in your system, then most operating systems
@@ -3226,10 +3264,16 @@ date/time of file creation, update, and or access in the directory.
 This capability is available in all of the RomWBW operating system
 except the original DRI CP/M 2.2.
 
-In some cases (such as ZSDOS), you must load an RSX (memory resident
-utility) to enable date/time stamping of files.  Additionally, you
-will need to initialize the directory.  The procedure varies in each
-operation system, so you must review the associated documentation.
+Three types of date/time stamping are supported using realtime clock 
+supported by RomWBW HBIOS. DateStamper, NZT and P2DOS.
+
+In some cases (such as ZSDOS), you must load an RSX (memory resident 
+utility) to enable date/time stamping of files. This could be automated 
+using a `PROFILE.SUB` file.
+Preconfigured loaders are provided, bypassing the need to use SETUPZST.
+
+Additionally, you will need to initialize the directory. The procedure varies
+depending on the date/time stamping mechanism, so you must review the associated documentation.
 
 The date/time stamping mechanisms for each operating system are
 generally not compatible.  If you initialize a directory for a type
@@ -3240,6 +3284,71 @@ mechanism.  Doing so may corrupt the directory.
 The RomWBW disk images do not have date/time stamping initialized.  This
 is to avoid any chance of directory corruption.
 
+### DateStamper
+
+DateStamper datestamping follows the standard set by Plu*Perfect Systems. 
+This method stores stamps in a disk file named `!!!TIME&.DAT`. 
+Only DateStamper stamping stores full time and date stamps for
+file Creation, Last Modification, and Last Access, 
+and may be used with any CP/M diskette format. In addition, 
+the DateStamper protocol is supported by a mature set of compatible utilities.
+
+Key Utilities
+
+* LDDS.COM - Load DateStamper date/time stamping resident extension. (RomWBW Provided)
+* PUTDS.COM - Prepare disk for DateStamper date/time stamping.
+
+After using PUTDS to initialize a directory for ZDS date stamping,
+it may be necessary to run RELOG before the stamping routines 
+will actually start working.
+
+### P2DOS (CP/M Plus compatible)
+
+CP/M Plus-type datestamping is also widely used due to the popularity 
+of CP/M Plus (also know as CP/M 3). CP/M Plus-type file datestamping uses 
+directory sectors to store file datestamps which may be accessed more quickly 
+by programs, but there is no Last File Access stamp. Finally, the range of 
+utilities for this type of stamps is more limited than for the DateStamper protocol.
+
+Key Utilities
+
+* LDP2D.COM - Load P2DOS date/time stamping resident extension. (RomWBW Provided)
+* INITDIR.COM - Prepares disks for P2DOS-type file stamping.
+
+### NZT
+
+_The use of NZT needs to be further documented_
+
+Key Utilities
+
+* LDNZT.COM - Load NZT date/time stamping resident extension. (RomWBW Provided)
+
+### Additional Notes
+
+The following files have been provided, customised and tested for for use in RomWBW
+
+* `CLOCKS.DAT` - Library of clock drivers, which has been updated to include 
+   the RomWBW clock driver WBWCLK, and also includes the SIMHCLOK clock driver.
+   The file is just a standard LU type library and is easily updated using NULU. 
+   The members are the relocatable binaries, but with the .REL extension removed.
+* `STAMPS.DAT` - Library of available date/time stamping modules for SETUPZST.
+   The file has been replaced with an updated version from the Walnut Creek CP/M CDROM. 
+   The original version has a bug that prevents RSX (resident system extension) mode 
+   to load properly.
+
+Additional Notes
+
+* `SETUPZST` (provided by ZSDOS) Should not normally be needed since the 
+   creation of the appropriate LDTIM loaders has already been performed.
+* `FILEDATE` only works with DateStamper style date stamping. If you run
+   it on a drive that is not initialized for DateStamper, it will complain
+   `FILEDATE, !!!TIME&.DAT missing`. This is normal and just means that
+   you have not initialized that drive for DateStamper (using PUTDS).
+* `ZXD` will handle either DateStamper or P2DOS type date stamping.
+   However, it **must** be configured appropriately. As distributed, it will
+   look for P2DOS date stamps. Use ZCNFG to reconfigure it for P2DOS if
+   that is what you are using.
+
 ## Timezone
 
 None of the operating systems distributed with RomWBW have any concept
@@ -5275,7 +5384,7 @@ the RomWBW HBIOS configuration.
 - CH: IO=60
 - CHUSB: IO=62
 - CHUSB: IO=60
-S- MD: TYPE=RAM
+- MD: TYPE=RAM
 - MD: TYPE=ROM
 - FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD
 - FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD
@@ -5990,6 +6099,36 @@ SD: MODE=FZ80, IO=108, UNITS=2
 
 - Requires matching FPGA code
 
+### Genesis STD Z180
+
+#### ROM Image File:  GMZ180_std.rom
+
+|                   |               |
+|-------------------|---------------|
+| Default CPU Speed | 18.432 MHz    |
+| Interrupts        | Mode 2        |
+| System Timer      | Z180          |
+| Serial Default    | 115200 Baud   |
+| Memory Manager    | Z180          |
+| ROM Size          | 512 KB        |
+| RAM Size          | 512 KB        |
+
+##### Supported Hardware (see [Appendix B - Device Summary]):
+
+DSRTC: MODE=STD, IO=132
+INTRTC: ENABLED
+ASCI: IO=192, INTERRUPTS ENABLED
+ASCI: IO=193, INTERRUPTS ENABLED
+MD: TYPE=RAM
+MD: TYPE=ROM
+IDE: MODE=GIDE, IO=32, MASTER
+IDE: MODE=GIDE, IO=32, SLAVE
+SD: MODE=GM, IO=132, UNITS=1
+
+##### Notes:
+
+- CPU speed will be dynamically measured at startup if DSRTC is present
+
 ## Appendix B - Device Summary
 
 The table below briefly describes each of the possible devices that
@@ -6016,6 +6155,7 @@ may be discovered by RomWBW in your system.
 | EMM       | Disk     | Disk drive on Parallel Port emm interface (Zip Drive)  |
 | FD        | Disk     | 8272 or compatible Floppy Disk Controller              |
 | FP        | System   | Simple LED & Switch Front Panel                        |
+| FV        | Video    | S100 FPGA Z80 Onboard VGA/Keyboard                     |
 | GDC       | Video    | uPD7220 Video Display Controller                       |
 | HDSK      | Disk     | SIMH Simulator Hard Disk                               |
 | ICM       | DsKy     | ICM7218-based Display/Keypad on PPI                    |
@@ -6024,6 +6164,7 @@ may be discovered by RomWBW in your system.
 | INTRTC    | RTC      | Interrupt-based Real Time Clock                        |
 | KBD       | Keyboard | 8242 PS/2 Keyboard Controller                          |
 | KIO       | System   | Zilog Serial/ Parallel Counter/Timer                   |
+| LCD       | System   | Hitachi HD44780-based LCD Display                      |
 | LPT       | Char     | Parallel I/O Controller                                |
 | MD        | Disk     | ROM/RAM Disk                                           |
 | MSXKYB    | Keyboard | MSX Compliant Matrix Keyboard                          |

Source/HBIOS/Build.cmd

@@ -232,6 +232,7 @@ call Build SCZ180 sc131_std || exit /b
 call Build SCZ180 sc140_std || exit /b
 call Build SCZ180 sc503_std || exit /b
 call Build SCZ180 sc700_std || exit /b
+call Build GMZ180 std || exit /b
 call Build DYNO std || exit /b
 call Build RPH std || exit /b
 call Build Z80RETRO std || exit /b

Source/HBIOS/Build.ps1

@@ -28,7 +28,7 @@ $ErrorAction = 'Stop'
 #
 
 $PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "Z80RETRO", "DUO", "UNA", "HEATH", "MON", "NABU", "FZ80"
-$PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO", "RPH", "S100", "EPITX"
+$PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO", "RPH", "S100", "EPITX", "GMZ180"
 $PlatformListZ280 = "RCZ280"
 
 #

Source/HBIOS/Build.sh

@@ -40,6 +40,7 @@ if [ "${ROM_PLATFORM}" == "dist" ] ; then
 	ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc140_std"; bash Build.sh
 	ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc503_std"; bash Build.sh
 	ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc700_std"; bash Build.sh
+	ROM_PLATFORM="GMZ180"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="DYNO"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="RPH"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="Z80RETRO"; ROM_CONFIG="std"; bash Build.sh

Source/HBIOS/Config/GMZ180_std.asm

@@ -0,0 +1,72 @@
+;
+;==================================================================================================
+;   STD Z180 STANDARD CONFIGURATION
+;==================================================================================================
+;
+; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
+; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
+; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
+; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
+; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
+; YOUR FILE IN THE BUILD PROCESS.
+;
+; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
+; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
+; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
+; SETTINGS.
+;
+; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
+; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
+; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
+; DIRECTORIES ABOVE THIS ONE).
+;
+#DEFINE PLATFORM_NAME "GM STD BUS Z180", " [", CONFIG, "]"
+;
+#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
+;
+#include "cfg_gmz180.asm"
+;
+CPUOSC	.SET	18432000	; CPU OSC FREQ IN MHZ
+CRTACT	.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+;
+Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
+Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+;
+LEDENABLE	.SET	FALSE		; ENABLE STATUS LED (SINGLE LED)
+LEDMODE	.SET	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
+;
+FPLED_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.SET	$00		; FP: PORT ADDRESS FOR FP LEDS
+;
+DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+INTRTCENABLE	.SET	TRUE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+;
+UARTENABLE	.SET	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+ASCIENABLE	.SET	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+;
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+TMSMODE	.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
+MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+;
+AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
+AYMODE		.SET	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+;
+FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE	.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+;
+IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+SDENABLE	.SET	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE	.SET	SDMODE_GM	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
+;
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)

Source/HBIOS/cfg_duo.asm

@@ -90,6 +90,9 @@ PKDENABLE	.EQU	TRUE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$88		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -196,6 +199,7 @@ VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK

Source/HBIOS/cfg_dyno.asm

@@ -92,6 +92,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -214,6 +217,7 @@ VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK

Source/HBIOS/cfg_epitx.asm

@@ -93,6 +93,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -216,6 +219,7 @@ VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK

Source/HBIOS/cfg_fz80.asm

@@ -92,6 +92,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -219,6 +222,7 @@ VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	TRUE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	TRUE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	FALSE		; MD: ENABLE ROM DISK

Source/HBIOS/cfg_gmz180.asm

@@ -0,0 +1,359 @@
+;
+;==================================================================================================
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR GENESIS MODULES STD BUS BASED Z180 VARIANTS 
+;==================================================================================================
+;
+; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
+; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
+; UNDER THIS DIRECTORY.
+;
+; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
+; FOR THE PLATFORM.
+;
+#DEFINE PLATFORM_NAME "GM STD BUS Z180", " [", CONFIG, "]"
+;
+#INCLUDE "hbios.inc"
+;
+PLATFORM	.EQU	PLT_GMZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+;
+BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+AUTOCON		.EQU	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
+;
+CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
+INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;
+RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+APP_BNKS	.EQU	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
+RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
+MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
+;
+Z180_BASE	.EQU	$C0		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
+Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
+Z180_MEMWAIT	.EQU	0		; Z180: MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.EQU	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+Z180_TIMER	.EQU	TRUE		; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
+;
+RTCIO		.EQU	$84		; RTC LATCH REGISTER ADR
+;
+KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+;
+CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
+CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
+;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
+SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+;
+WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+;
+FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_INV	.EQU	FALSE		; FP: LED BITS ARE INVERTED
+FPLED_DSKACT	.EQU	FALSE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
+;
+DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+;
+LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
+LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
+LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
+LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+;
+DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.EQU	FALSE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
+;
+BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
+CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+;
+DSRTCENABLE	.EQU	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
+DSRTCCHG	.EQU	TRUE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+;
+DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+;
+BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+;
+INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+;
+RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
+HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+;
+DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+;
+DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+;
+SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
+SSERDATA	.EQU	$FF		; SSER: DATA PORT
+SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+;
+DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+DUARTCNT	.EQU	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
+DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
+DUART0ACFG	.EQU	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
+DUART0BCFG	.EQU	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
+DUART1BASE	.EQU	$40		; DUART 1: BASE ADDRESS OF CHIP
+DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
+DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
+;
+UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.EQU	1		; UART: NUMBER OF CHIPS TO DETECT (1-8)
+UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.EQU	$80		; UART 0: REGISTERS BASE ADR
+UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.EQU	$88		; UART 1: REGISTERS BASE ADR
+UART1CFG	.EQU	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.EQU	$A0		; UART 2: REGISTERS BASE ADR
+UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.EQU	$A8		; UART 3: REGISTERS BASE ADR
+UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
+;
+ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+ASCISWAP	.EQU	FALSE		; ASCI: SWAP CHANNELS
+ASCIBOOT	.EQU	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
+ASCI0CFG	.EQU	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
+ASCI1CFG	.EQU	DEFSERCFG	; ASCI 1: SERIAL LINE CONFIG
+;
+Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+;
+ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+;
+SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
+SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.EQU	SER_115200_8N1	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.EQU	7372800		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.EQU	SER_115200_8N1	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
+SIO1ACLK	.EQU	7372800		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1ACFG	.EQU	SER_115200_8N1	; SIO 1A: SERIAL LINE CONFIG
+SIO1ACTCC	.EQU	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1BCLK	.EQU	7372800		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1BCFG	.EQU	SER_115200_8N1	; SIO 1B: SERIAL LINE CONFIG
+SIO1BCTCC	.EQU	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+;
+XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+;
+VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMS80COLS	.EQU	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
+TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+;
+MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+;
+FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+;
+RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+;
+IDEENABLE	.EQU	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.EQU	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT		.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.EQU	IDEMODE_GIDE	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
+IDE0BASE	.EQU	$20   		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.EQU	$20		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.EQU	$28		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.EQU	TRUE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.EQU	TRUE		; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.EQU	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
+IDE1BASE	.EQU	$00		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.EQU	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.EQU	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.EQU	TRUE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.EQU	TRUE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.EQU	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
+IDE2BASE	.EQU	$00		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.EQU	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.EQU	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.EQU	TRUE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.EQU	TRUE		; IDE 2B (MASTER): 8 BIT XFER
+;
+PPIDEENABLE	.EQU	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.EQU	$20		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1BASE	.EQU	$00		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE2BASE	.EQU	$00		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+;
+SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.EQU	SDMODE_GM	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM]
+SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.EQU	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$3E		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.EQU	$3C		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	TRUE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+;
+PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+;
+PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
+HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+;
+LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTMODE		.EQU	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTCNT		.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
+LPTTRACE	.EQU	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+LPT0BASE	.EQU	$18		; LPT 0: REGISTERS BASE ADR
+LPT1BASE	.EQU	$00		; LPT 1: REGISTERS BASE ADR
+;
+PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
+PPACNT		.EQU	1		; PPA: NUMBER OF PPA DEVICES (1-2)
+PPATRACE	.EQU	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPAMODE		.EQU	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
+PPA0BASE	.EQU	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
+PPA1BASE	.EQU	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
+;
+IMMENABLE	.EQU	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+IMMCNT		.EQU	1		; IMM: NUMBER OF IMM DEVICES (1-2)
+IMMTRACE	.EQU	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IMMMODE		.EQU	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
+IMM0BASE	.EQU	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
+IMM1BASE	.EQU	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
+;
+SYQENABLE	.EQU	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
+SYQCNT		.EQU	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
+SYQTRACE	.EQU	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SYQMODE		.EQU	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
+SYQ0BASE	.EQU	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQ1BASE	.EQU	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
+;
+PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+;
+UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+;
+SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
+SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
+;
+AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
+AYMODE		.EQU	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+;
+SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+;
+DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
+;
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_heath.asm

@@ -92,6 +92,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	TRUE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -219,6 +222,7 @@ VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK

Source/HBIOS/cfg_master.asm

@@ -121,6 +121,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -264,6 +267,7 @@ VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK

Source/HBIOS/cfg_mbc.asm

@@ -87,6 +87,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -193,6 +196,7 @@ VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK

Source/HBIOS/cfg_mk4.asm

@@ -92,6 +92,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -203,6 +206,7 @@ VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK

Source/HBIOS/cfg_mon.asm

@@ -87,6 +87,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -214,6 +217,7 @@ VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK

Source/HBIOS/cfg_n8.asm

@@ -94,6 +94,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	N8_PPI0		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -205,6 +208,7 @@ VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK

Source/HBIOS/cfg_nabu.asm

@@ -92,6 +92,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -219,6 +222,7 @@ VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK

Source/HBIOS/cfg_rcz180.asm

@@ -98,6 +98,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	TRUE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$AA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -220,6 +223,7 @@ VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK

Source/HBIOS/cfg_rcz280.asm

@@ -92,6 +92,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	TRUE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -224,6 +227,7 @@ VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK

Source/HBIOS/cfg_rcz80.asm

@@ -92,6 +92,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	TRUE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -219,6 +222,7 @@ VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK

Source/HBIOS/cfg_rph.asm

@@ -92,6 +92,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	RPH_PPI0	; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -193,6 +196,7 @@ VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK

Source/HBIOS/cfg_s100.asm

@@ -92,6 +92,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -214,6 +217,7 @@ VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK

Source/HBIOS/cfg_sbc.asm

@@ -87,6 +87,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -193,6 +196,7 @@ VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK

Source/HBIOS/cfg_scz180.asm

@@ -92,6 +92,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	TRUE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$AA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -214,6 +217,7 @@ VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK

Source/HBIOS/cfg_z80retro.asm

@@ -90,6 +90,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -200,6 +203,7 @@ VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK

Source/HBIOS/cfg_zeta.asm

@@ -79,6 +79,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -169,6 +172,7 @@ VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK

Source/HBIOS/cfg_zeta2.asm

@@ -90,6 +90,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -180,6 +183,7 @@ VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK

Source/HBIOS/esp.asm

@@ -364,7 +364,8 @@ ESPCON_INIT:
 	PUSH	IY			; COPY CONFIG ENTRY PTR
 	POP	DE			; ... TO DE
 	CALL	CIO_ADDENT		; ADD ENTRY, A := UNIT ASSIGNED
-	LD	(HCB + HCB_CRTDEV),A	; SET OURSELVES AS THE CRT DEVICE
+	;;;LD	(HCB + HCB_CRTDEV),A	; SET OURSELVES AS THE CRT DEVICE
+	CALL	CIO_SETCRT		; SET OURSELVES AS THE CRT DEVICE
 ;
 ; ANNOUNCE OURSLEVES
 ;

Source/HBIOS/fv.asm

@@ -0,0 +1,497 @@
+;======================================================================
+;	VIDEO DRIVER FOR FPGA VGA
+;	http://s100computers.com/My%20System%20Pages/FPGA%20Z80%20SBC/FPGA%20Z80%20SBC.htm
+;
+;	WRITTEN BY: WAYNE WARTHEN -- 9/2/2024
+;======================================================================
+;
+; FPGA VGA EXPOSES A FRAME BUFFER STARTING AT $E000.
+; PORT $08 CONTROLS ACCESS TO THE FRAME BUFFER.
+;   - WHEN $01, FRAME BUFFER APPEARS AT $E000 IN CPU ADDRESS SPACE
+;   - WHEN $00, FRAME BUFFER IS INACCESSIBLE BY CPU
+; PORT $C0: SET/GET CURSOR COL
+; PORT $C1: SET/GET CURSOR ROW
+; PORT $C2: CONTROLS VGA OUTPUT
+;  BIT 0: BLUE
+;  BIT 1: GREEN
+;  BIT 2: RED
+;  BIT 3: UNUSED?
+;  BIT 4: CURSOR MODE
+;  BIT 5: CURSOR BLINK
+;  BIT 6: CURSOR ENABLE
+;  BIT 7: VGA SIGNAL OUTPUT ENABLE
+; PORT $08: BUFFER SELECT, 1=SELECTED
+;
+; TODO:
+;
+;======================================================================
+; FPGA VGA DRIVER - CONSTANTS
+;======================================================================
+;
+FV_FBUF		.EQU	$E000		; ADDRESS OF FRAME BUFFER
+FV_BASE		.EQU	$C0		; BASE I/O ADDRESS
+FV_CCOL		.EQU	FV_BASE+0	; CUR COL PORT
+FV_CROW		.EQU	FV_BASE+1	; CUR ROW PORT
+FV_CTL		.EQU	FV_BASE+2	; VGA CONTROL PORT
+;
+FV_BUFCTL	.EQU	$08
+;
+FV_KBDDATA	.EQU	$03
+FV_KBDST	.EQU	$02
+;
+FV_ROWS	.EQU	40
+FV_COLS	.EQU	80
+;
+TERMENABLE	.SET	TRUE		; INCLUDE TERMINAL PSEUDODEVICE DRIVER
+;;;KBDENABLE	.SET	TRUE		; INCLUDE KBD KEYBOARD SUPPORT
+;
+		DEVECHO	"FV: IO="
+		DEVECHO	FV_BASE
+		DEVECHO	", KBD MODE=FV"
+		DEVECHO	", KBD IO="
+		DEVECHO	FV_KBDDATA
+		DEVECHO	"\n"
+;
+;======================================================================
+; FPGA VGA DRIVER - INITIALIZATION
+;======================================================================
+;
+FV_INIT:
+	LD	IY,FV_IDAT		; POINTER TO INSTANCE DATA
+;
+	CALL	NEWLINE			; FORMATTING
+	PRTS("FV: IO=0x$")
+	LD	A,FV_BASE
+	CALL	PRTHEXBYTE
+	CALL	FV_PROBE		; CHECK FOR HW PRESENCE
+	JR	Z,FV_INIT1		; CONTINUE IF HW PRESENT
+;
+	; HARDWARE NOT PRESENT
+	PRTS(" NOT PRESENT$")
+	OR	$FF			; SIGNAL FAILURE
+	RET
+;
+FV_INIT1:
+	; RECORD DRIVER ACTIVE
+	OR	$FF
+	LD	(FV_ACTIVE),A
+	; DISPLAY CONSOLE DIMENSIONS
+	LD	A,FV_COLS
+	CALL	PC_SPACE
+	CALL	PRTDECB
+	LD	A,'X'
+	CALL	COUT
+	LD	A,FV_ROWS
+	CALL	PRTDECB
+	PRTS(" TEXT$")
+
+	; HARDWARE INITIALIZATION
+	CALL 	FV_CRTINIT		; SETUP THE FPGA VGA CHIP REGISTERS
+	CALL	FV_VDAINI		; INITIALIZE
+	;CALL	KBD_INIT		; INITIALIZE KEYBOARD DRIVER
+
+	; ADD OURSELVES TO VDA DISPATCH TABLE
+	LD	BC,FV_FNTBL		; BC := FUNCTION TABLE ADDRESS
+	LD	DE,FV_IDAT		; DE := FPGA VGA INSTANCE DATA PTR
+	CALL	VDA_ADDENT		; ADD ENTRY, A := UNIT ASSIGNED
+
+	; INITIALIZE EMULATION
+	LD	C,A			; C := ASSIGNED VIDEO DEVICE NUM
+	LD	DE,FV_FNTBL		; DE := FUNCTION TABLE ADDRESS
+	LD	HL,FV_IDAT		; HL := FPGA VGA INSTANCE DATA PTR
+	CALL	TERM_ATTACH		; DO IT
+
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+;======================================================================
+; FPGA VGA DRIVER - VIDEO DISPLAY ADAPTER (VDA) FUNCTIONS
+;======================================================================
+;
+FV_FNTBL:
+	.DW	FV_VDAINI
+	.DW	FV_VDAQRY
+	.DW	FV_VDARES
+	.DW	FV_VDADEV
+	.DW	FV_VDASCS
+	.DW	FV_VDASCP
+	.DW	FV_VDASAT
+	.DW	FV_VDASCO
+	.DW	FV_VDAWRC
+	.DW	FV_VDAFIL
+	.DW	FV_VDACPY
+	.DW	FV_VDASCR
+	.DW	FV_STAT
+	.DW	FV_FLUSH
+	.DW	FV_READ
+	.DW	FV_VDARDC
+#IF (($ - FV_FNTBL) != (VDA_FNCNT * 2))
+	.ECHO	"*** INVALID FV FUNCTION TABLE ***\n"
+	!!!!!
+#ENDIF
+
+FV_VDAINI:
+	; RESET VDA
+	CALL	FV_VDARES	; RESET VDA
+	LD	HL,0		; ZERO
+	LD	(FV_POS),HL	; ... TO POSITION
+	LD	A,' '		; BLANK THE SCREEN
+	LD	DE,FV_ROWS*FV_COLS	; FILL ENTIRE BUFFER
+	CALL	FV_FILL		; DO IT
+	LD	DE,0		; ROW = 0, COL = 0
+	CALL	FV_XY		; SEND CURSOR TO TOP LEFT
+	CALL	FV_SHOWCUR	; NOW SHOW THE CURSOR
+	XOR	A		; SIGNAL SUCCESS
+	RET
+
+FV_VDAQRY:
+	LD	C,$00		; MODE ZERO IS ALL WE KNOW
+	LD	D,FV_ROWS	; ROWS
+	LD	E,FV_COLS	; COLS
+	LD	HL,0		; EXTRACTION OF CURRENT BITMAP DATA NOT SUPPORTED
+	XOR	A		; SIGNAL SUCCESS
+	RET
+
+FV_VDARES:
+	CALL	 FV_CRTINIT
+	XOR	A		; SIGNAL SUCCESS
+	RET
+
+FV_VDADEV:
+	LD	D,VDADEV_FV	; D := DEVICE TYPE
+	LD	E,0		; E := PHYSICAL UNIT IS ALWAYS ZERO
+	LD	H,0		; H := 0, DRIVER HAS NO MODES
+	LD	L,FV_BASE	; L := BASE I/O ADDRESS
+	XOR	A		; SIGNAL SUCCESS
+	RET
+
+FV_VDASCS:
+	SYSCHKERR(ERR_NOTIMPL)	; NOT IMPLEMENTED (YET)
+	RET
+
+FV_VDASCP:
+	CALL	FV_XY		; SET CURSOR POSITION
+	XOR	A		; SIGNAL SUCCESS
+	RET
+
+FV_VDASAT:
+	; ATTRIBUTES NOT SUPPORTED BY HARDWARE
+	XOR	A
+	RET
+
+FV_VDASCO:
+	; CHARACTER COLOR NOT SUPPORT BY HARDWARE
+	XOR	A		; SIGNAL SUCCESS
+	RET			; DONE
+
+FV_VDAWRC:
+	LD	A,E		; CHARACTER TO WRITE GOES IN A
+	CALL	FV_PUTCHAR	; PUT IT ON THE SCREEN
+	XOR	A		; SIGNAL SUCCESS
+	RET
+
+FV_VDAFIL:
+	LD	A,E		; FILL CHARACTER GOES IN A
+	EX	DE,HL		; FILL LENGTH GOES IN DE
+	CALL	FV_FILL		; DO THE FILL
+	XOR	A		; SIGNAL SUCCESS
+	RET
+
+FV_VDACPY:
+	; LENGTH IN HL, SOURCE ROW/COL IN DE, DEST IS FV_POS
+	; BLKCPY USES: HL=SOURCE, DE=DEST, BC=COUNT
+	PUSH	HL		; SAVE LENGTH
+	CALL	FV_XY2IDX	; ROW/COL IN DE -> SOURCE ADR IN HL
+	POP	BC		; RECOVER LENGTH IN BC
+	LD	DE,(FV_POS)	; PUT DEST IN DE
+	JP	FV_BLKCPY	; DO A BLOCK COPY
+
+FV_VDASCR:
+	LD	A,E		; LOAD E INTO A
+	OR	A		; SET FLAGS
+	RET	Z		; IF ZERO, WE ARE DONE
+	PUSH	DE		; SAVE E
+	JP	M,FV_VDASCR1	; E IS NEGATIVE, REVERSE SCROLL
+	CALL	FV_SCROLL	; SCROLL FORWARD ONE LINE
+	POP	DE		; RECOVER E
+	DEC	E		; DECREMENT IT
+	JR	FV_VDASCR	; LOOP
+FV_VDASCR1:
+	CALL	FV_RSCROLL	; SCROLL REVERSE ONE LINE
+	POP	DE		; RECOVER E
+	INC	E		; INCREMENT IT
+	JR	FV_VDASCR	; LOOP
+
+FV_STAT:
+	IN	A,(FV_KBDST)		; GET STATUS
+	AND	$01			; ISOLATE DATA WAITING BIT
+	JP	Z,CIO_IDLE		; NO DATA, EXIT VIA IDLE PROCESS
+	RET
+
+FV_FLUSH:
+	XOR	A			; SIGNAL SUCCESS
+	RET
+
+FV_READ:
+	CALL	FV_STAT			; GET STATUS
+	JR	Z,FV_READ		; LOOP TILL DATA READY
+	IN	A,(FV_KBDDATA)		; GET BYTE
+	LD	E,A			; PUT IN E FOR RETURN
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
+
+;----------------------------------------------------------------------
+; READ VALUE AT CURRENT VDU BUFFER POSITION
+; RETURN E = CHARACTER, B = COLOUR, C = ATTRIBUTES
+;----------------------------------------------------------------------
+
+FV_VDARDC:
+	CALL	FV_GETCHAR	; GET THE CHARACTER AT CUR CUR POS
+	LD	E,A		; PUT IN E
+	LD	BC,0		; COLOR AND ATTR NOT SUPPORTED
+	XOR	A		; SIGNAL SUCCESS
+	RET
+;
+;======================================================================
+; FPGA VGA DRIVER - PRIVATE DRIVER FUNCTIONS
+;======================================================================
+;
+;
+;----------------------------------------------------------------------
+; PROBE FOR FPGA VGA HARDWARE
+;----------------------------------------------------------------------
+;
+; ON RETURN, ZF SET INDICATES HARDWARE FOUND
+;
+FV_PROBE:
+	XOR	A			; ASSUME H/W EXISTS
+	RET
+;
+;----------------------------------------------------------------------
+; CRTC DISPLAY CONTROLLER CHIP INITIALIZATION
+;----------------------------------------------------------------------
+;
+FV_CRTINIT:
+	LD	A,%11001111		; WHITE ON BLACK, CURSOR ON, ENABLE OUTPUT
+	OUT	(FV_CTL),A		; WRITE TO CONTROL PORT
+	XOR	A			; ZERO ACCUM
+	RET				; DONE
+;
+;----------------------------------------------------------------------
+; SET CURSOR POSITION TO ROW IN D AND COLUMN IN E
+;----------------------------------------------------------------------
+;
+FV_XY:
+	CALL	FV_HIDECUR		; HIDE THE CURSOR
+	PUSH	DE			; SAVE NEW POSITION FOR NOW
+	CALL	FV_XY2IDX		; CONVERT ROW/COL TO BUF IDX
+	LD	(FV_POS),HL		; SAVE THE RESULT (DISPLAY POSITION)
+	POP	DE			; RECOVER INCOMING ROW/COL
+	LD	A,D			; GET ROW
+	OUT	(FV_CROW),A		; SET ROW REGISTER
+	LD	A,E			; GET COL
+	INC	A			; 1..79,0 (WHY???)
+	CP	80			; COL 80?
+	JR	NZ, FV_XY1		; SKIP IF NOT
+	XOR	A			; ELSE MAKE IT ZERO!
+FV_XY1:
+	OUT	(FV_CCOL),A		; SET COL REGISTER
+	JP	FV_SHOWCUR		; SHOW THE CURSOR AND EXIT
+;
+;----------------------------------------------------------------------
+; CONVERT XY COORDINATES IN DE INTO LINEAR INDEX IN HL
+; D=ROW, E=COL
+;----------------------------------------------------------------------
+;
+FV_XY2IDX:
+	LD	A,E			; SAVE COLUMN NUMBER IN A
+	LD	H,D			; SET H TO ROW NUMBER
+	LD	E,FV_COLS		; SET E TO ROW LENGTH
+	CALL	MULT8			; MULTIPLY TO GET ROW OFFSET, H * E = HL, E=0, B=0
+	LD	E,A			; GET COLUMN BACK
+	ADD	HL,DE			; ADD IT IN
+	RET				; RETURN
+;
+;----------------------------------------------------------------------
+; SHOW OR HIDE CURSOR
+;----------------------------------------------------------------------
+;
+FV_SHOWCUR:
+	LD	A,%11001111		; CONTROL PORT VALUE
+	;;;LD	A,%11111111		; CONTROL PORT VALUE
+	OUT	(FV_CTL),A		; SET REGISTER
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
+;
+FV_HIDECUR:
+	LD	A,%11001111		; CONTROL PORT VALUE
+	;;;LD	A,%11111111		; CONTROL PORT VALUE
+	OUT	(FV_CTL),A		; SET REGISTER
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
+;
+;----------------------------------------------------------------------
+; (DE)SELECT FRAME BUFFER
+;----------------------------------------------------------------------
+;
+FV_BUFSEL:
+	PUSH	AF
+	LD	A,$01
+	OUT	(FV_BUFCTL),A
+	POP	AF
+	RET
+;
+FV_BUFDESEL:
+	PUSH	AF
+	XOR	A
+	OUT	(FV_BUFCTL),A
+	POP	AF
+	RET
+;
+;----------------------------------------------------------------------
+; WRITE VALUE IN A TO CURRENT VDU BUFFER POSITION, ADVANCE CURSOR
+;----------------------------------------------------------------------
+;
+FV_PUTCHAR:
+	; WRITE CHAR AT CURRENT CURSOR POSITION.
+	PUSH	AF			; SAVE INCOMING CHAR
+	CALL	FV_HIDECUR		; HIDE CURSOR
+	CALL	FV_BUFSEL		; SELECT FRAME BUFFER
+	POP	AF
+	LD	HL,(FV_POS)		; GET CUR BUF POSITION
+	LD	DE,FV_FBUF		; START OF FRAME BUF
+	ADD	HL,DE			; ADD IT IN
+	LD	(HL),A			; PUT THE CHAR
+;
+	; SET NEW POSITION
+	LD	HL,(FV_POS)		; GET POSITION
+	INC	HL			; BUMP POSITION
+	LD	(FV_POS),HL		; SAVE NEW POSITION
+;
+	; PUT CUROR IN PLACE
+	LD	DE,FV_COLS		; COLS PER LINE
+	CALL	DIV16			; BC=ROW, HL=COL
+	LD	D,C
+	LD	E,L
+	CALL	FV_XY
+	CALL	FV_BUFDESEL		; DESELECT FRAME BUFFER
+	JP	FV_SHOWCUR		; SHOW IT AND RETURN
+;
+;----------------------------------------------------------------------
+; GET CHAR VALUE TO A FROM CURRENT VDU BUFFER POSITION
+;----------------------------------------------------------------------
+;
+FV_GETCHAR:
+	XOR	A
+	RET
+;
+;----------------------------------------------------------------------
+; FILL AREA IN BUFFER WITH SPECIFIED CHARACTER AND CURRENT COLOR/ATTRIBUTE
+; STARTING AT THE CURRENT FRAME BUFFER POSITION
+;   A: FILL CHARACTER
+;   DE: NUMBER OF CHARACTERS TO FILL
+;----------------------------------------------------------------------
+;
+FV_FILL:
+	PUSH	AF			; SAVE INCOMING FILL CHAR
+	CALL	FV_HIDECUR		; HIDE CURSOR
+	CALL	FV_BUFSEL		; SELECT BUFFER
+	LD	HL,(FV_POS)		; CUR POS TO HL
+	LD	BC,FV_FBUF		; ADR OF FRAME
+	ADD	HL,BC			; ADD IT IN
+	POP	AF
+	LD	C,A			; FILL CHAR TO C
+FV_FILL1:
+	LD	A,D			; CHECK FILL
+	OR	E			; ... COUNTER
+	JR	Z,FV_FILL2		; DONE IF ZERO
+	LD	(HL),C			; FILL ONE CHAR
+	INC	HL			; BUMP BUF PTR
+	DEC	DE			; DEC FILL COUNTER
+	JR	FV_FILL1		; LOOP
+;
+FV_FILL2:
+	CALL	FV_BUFDESEL		; DESELECT BUFFER
+	JP	FV_SHOWCUR		; EXIT VIA SHOW CURSOR
+;
+;----------------------------------------------------------------------
+; SCROLL ENTIRE SCREEN FORWARD BY ONE LINE (CURSOR POSITION UNCHANGED)
+;----------------------------------------------------------------------
+;
+FV_SCROLL:
+	CALL	FV_BUFSEL				; SELECT FRAME BUFFER
+;
+	; COPY "UP" ONE LINE
+	LD	HL,FV_FBUF + FV_COLS 			; FROM SECOND LINE
+	LD	DE,FV_FBUF				; TO FIRST LINE
+	LD	BC,+(FV_ROWS - 1) * FV_COLS		; ALL BUT ONE LINE
+	LDIR						; DO IT
+;
+	; FILL LAST LINE OF SCREEN
+	LD	HL,FV_FBUF + ((FV_ROWS - 1) * FV_COLS)	; LAST LINE
+	LD	A,' '					; FILL CHAR
+	LD	(HL),A					; COPY 1 CHAR
+	LD	DE,FV_FBUF + ((FV_ROWS - 1) * FV_COLS) + 1	; SECOND POS IN LAST LINE
+	LD	BC,FV_COLS - 1				; COLS PER LINE - 1
+	LDIR						; FILL IT
+;
+	CALL	FV_BUFDESEL				; DESELECT FRAME BUFFER
+	RET						; DONE
+;
+;----------------------------------------------------------------------
+; REVERSE SCROLL ENTIRE SCREEN BY ONE LINE (CURSOR POSITION UNCHANGED)
+;----------------------------------------------------------------------
+;
+FV_RSCROLL:
+	CALL	FV_BUFSEL				; SELECT FRAME BUFFER
+;
+	; COPY "DOWN" ONE LINE
+	LD	HL,FV_FBUF + (FV_COLS * (FV_ROWS - 1)) - 1 	; FROM END OF SECOND TO LAST LINE
+	LD	DE,FV_FBUF + (FV_COLS * FV_ROWS) - 1	; TO END OF LAST LINE
+	LD	BC,+(FV_ROWS - 1) * FV_COLS		; ALL BUT ONE LINE
+	LDDR						; DO IT IN REVERSE
+;
+	; FILL FIRST LINE OF SCREEN
+	LD	HL,FV_FBUF				; FIRST LINE
+	LD	A,' '					; FILL CHAR
+	LD	(HL),A					; COPY 1 CHAR
+	LD	DE,FV_FBUF + 1				; SECOND POS IN FIRST LINE
+	LD	BC,FV_COLS - 1				; COLS PER LINE - 1
+	LDIR						; FILL IT
+;
+	CALL	FV_BUFDESEL				; DESELECT FRAME BUFFER
+	RET						; DONE
+;
+;----------------------------------------------------------------------
+; BLOCK COPY BC BYTES FROM HL TO DE
+;----------------------------------------------------------------------
+;
+FV_BLKCPY:
+
+	CALL	FV_BUFSEL				; SELECT FRAME BUFFER
+	PUSH	BC					; SAVE LENGTH
+	LD	BC,FV_FBUF				; FRAME BUFFER ADR
+	ADD	HL,BC					; ADD TO SOURCE
+	EX	DE,HL					; EXCHANGE
+	ADD	HL,BC					; ADD TO DEST
+	EX	DE,HL					; EXCHANGE
+	POP	BC					; RECOVER LENGTH
+	LDIR						; LDIR DOES THE COPY
+	CALL	FV_BUFDESEL				; DESELECT FRAME BUFFER
+	RET						; DONE
+;
+;==================================================================================================
+;   FPGA VGA DRIVER - DATA
+;==================================================================================================
+;
+FV_POS		.DW 	0	; CURRENT DISPLAY POSITION
+FV_ACTIVE	.DB	FALSE	; FLAG FOR DRIVER ACTIVE
+;
+;==================================================================================================
+;   VGA DRIVER - INSTANCE DATA
+;==================================================================================================
+;
+FV_IDAT:
+	.DB	KBDMODE_FV	; FPGA VGA KEYBOARD CONTROLLER
+	.DB	FV_KBDST
+	.DB	FV_KBDDATA

Source/HBIOS/hbios.asm

@@ -67,7 +67,7 @@
 ;
 ; MEMORY LAYOUT:
 ;
-; 
+;
 ; DESCRIPTION			START	LENGTH
 ; ----------------------------- ------- -------
 ; Page Zero			0x0000	0x0100
@@ -97,7 +97,7 @@
 ; D4	~PSG_RES	~PSG_RES			~PSG_RES	ROM_A19		~PSG_RES
 ; D3	STATUS_LED	STATUS_LED	VDP_LED		PSG_LED		ROM_A18		PSG_LED
 ; D2	VDP_A14		VDP_A14						ROM_A17		VDP_LED
-; D1	~VDP_SYN	~VDP_SYN					ROM_A16	
+; D1	~VDP_SYN	~VDP_SYN					ROM_A16
 ; D0	~VDP_RES	~VDP_RES	VDP_RES				ROM_A15		VDP_RES
 ;
 ; PORT	SCG:0x9C	0x94		VDP:0x92	PSG:0xA2	0x80		MEDIA:0xA6
@@ -183,7 +183,7 @@ SUPCTS	.EQU	FALSE		; SUPPRESS CTS DURING HBIOS BOOT
 ; DUO: LED Port=0x94, bits 1-0, normal, shared w/ RTC port (LEDMODE_RTC)
 ; S100: LED Port = $0E, bit 2, inverted, dedicated port (LEDMODE_SC)
 ; NABU: LED Port = $00, bits 5-3, normal, shared w/ control port (LEDMODE_NABU)
-; 
+;
 #IF (LEDENABLE)
   #IF (LEDMODE == LEDMODE_STD)
     #DEFINE DIAG(N)	PUSH	AF
@@ -1077,23 +1077,23 @@ HBX_INTSTK	.EQU	$
 ;
 ; HBIOS INTERRUPT MODE 2 SLOT ASSIGNMENTS (SEE STD.ASM)
 ;
-; #	Z80/Z280	Z180            MBC		DUO		NABU		
-; ---	--------------	--------------  --------------	--------------	--------------	
-; 0	CTC0A		INT1 -+               -+	      -+	HCCARCV -+	
-; 1	CTC0B		INT2  |                |	       |	HCCASND  |		
-; 2	CTC0C		TIM0  |                | IM2	       | IM2	NABUKB	 | IM2	
-; 3	CTC0D		TIM1  |                | INT	       | INT	VDP	 | INT		
-; 4	UART0		DMA0  | Z180	UART0  | VEC	UART0  | VEC	OPTCRD0  | VEC		
-; 5	UART1		DMA1  | CPU	UART1  | GEN	UART1  | GEN	OPTCRD1  | GEN		
-; 6			CSIO  |                |	       |	OPTCRD2  |		
-; 7	SIO0		SER0  |               -+	      -+	OPTCRD3 -+		
-; 8	SIO1		SER1 -+         SIO0		SIO0		
-; 9	PIO0A		PIO0A           SIO1		SIO1		
-; 10	PIO0B		PIO0B           PIO0A		PIO0A		
-; 11	PIO1A		PIO1A           PIO0B		PIO0B		
-; 12	PIO1B		PIO1B           CTC0A		CTC0A		
-; 13			SIO0            CTC0B		CTC0B		
-; 14			SIO1            CTC0C		CTC0C			
+; #	Z80/Z280	Z180            MBC		DUO		NABU
+; ---	--------------	--------------  --------------	--------------	--------------
+; 0	CTC0A		INT1 -+               -+	      -+	HCCARCV -+
+; 1	CTC0B		INT2  |                |	       |	HCCASND  |
+; 2	CTC0C		TIM0  |                | IM2	       | IM2	NABUKB	 | IM2
+; 3	CTC0D		TIM1  |                | INT	       | INT	VDP	 | INT
+; 4	UART0		DMA0  | Z180	UART0  | VEC	UART0  | VEC	OPTCRD0  | VEC
+; 5	UART1		DMA1  | CPU	UART1  | GEN	UART1  | GEN	OPTCRD1  | GEN
+; 6			CSIO  |                |	       |	OPTCRD2  |
+; 7	SIO0		SER0  |               -+	      -+	OPTCRD3 -+
+; 8	SIO1		SER1 -+         SIO0		SIO0
+; 9	PIO0A		PIO0A           SIO1		SIO1
+; 10	PIO0B		PIO0B           PIO0A		PIO0A
+; 11	PIO1A		PIO1A           PIO0B		PIO0B
+; 12	PIO1B		PIO1B           CTC0A		CTC0A
+; 13			SIO0            CTC0B		CTC0B
+; 14			SIO1            CTC0C		CTC0C
 ; 15					CTC0D		CTC0D
 ;
 	; IVT MUST START AT PAGE BOUNDARY
@@ -1477,7 +1477,7 @@ BOOTWAIT:
 	LD	C,Z280_MSR		; MASTER STATUS REGISTER
 	LD	HL,$0000		; SYS MODE, NO INTERRUPTS
 	LDCTL	(C),HL			; DO IT
-;	
+;
 	; SET MAXIMUM I/O WAIT STATES FOR NOW
 	LD	C,Z280_BTCR		; BUS TIMING AND CONTROL REGISTER
 	LD	HL,$0033		; 3 I/O WAIT STATES ADDED
@@ -1880,23 +1880,23 @@ S100MON_SKIP:
 ; MBC BANK SELECT MASK SETUP
 ;--------------------------------------------------------------------------------------------------
 ;
-; THE MBC RAM BOARD CAN CONTAIN 1 OR 2 RAM CHIPS.  THE COMMON RAM BANK IS 
+; THE MBC RAM BOARD CAN CONTAIN 1 OR 2 RAM CHIPS.  THE COMMON RAM BANK IS
 ; FIXED BY HARDWARE TO BE THE TOP 32K OF THE *FIRST* RAM CHIP.  WHEN THERE
-; ARE 2 RAM CHIPS INSTALLED, THE HARDWARE WILL THUS PLACE THE COMMON RAM IN 
-; THE MIDDLE OF PHYSICAL RAM.  HBIOS REQUIRES THAT THE COMMON RAM BANK BE 
-; MAPPED TO THE VERY LAST 32K OF PHYSICAL RAM.  THIS IS REQUIRED SO THAT 
-; THE RAM DISK BANKS CAN BE SEQUENTIAL.  TO WORK AROUND THIS, WE USE AN 
-; XOR MASK THAT IS APPLIED DURING BANK SELECT.  THIS MASK WILL FLIP THE 
-; HIGH ORDER BANK SELECT BIT (WHEN 2 RAM CHIPS ARE USED) SO THAT THE TWO 
-; RAM CHIPS WIND UP "REVERSED" AND THE FIXED COMMON BANK WINDS UP AT THE 
+; ARE 2 RAM CHIPS INSTALLED, THE HARDWARE WILL THUS PLACE THE COMMON RAM IN
+; THE MIDDLE OF PHYSICAL RAM.  HBIOS REQUIRES THAT THE COMMON RAM BANK BE
+; MAPPED TO THE VERY LAST 32K OF PHYSICAL RAM.  THIS IS REQUIRED SO THAT
+; THE RAM DISK BANKS CAN BE SEQUENTIAL.  TO WORK AROUND THIS, WE USE AN
+; XOR MASK THAT IS APPLIED DURING BANK SELECT.  THIS MASK WILL FLIP THE
+; HIGH ORDER BANK SELECT BIT (WHEN 2 RAM CHIPS ARE USED) SO THAT THE TWO
+; RAM CHIPS WIND UP "REVERSED" AND THE FIXED COMMON BANK WINDS UP AT THE
 ; END OF THE RAM BANKS.  THE MASK IS SETUP HERE BASED ON THE NUMBER OF RAM
 ; CHIPS AND THEIR SIZE.  NOTE THAT THE NUMBER OF RAM CHIPS IS INFERRED BY
 ; THE TOTAL RAM SIZE.  A SINGLE CHIP WILL BE EITHER 128K OR 512K.  IF THE
 ; TOTAL RAM SIZE OF THE SYSTEM IS 256K OR 1M, THEN THERE MUST BE TWO CH
-; IPS.  THE RESULTING BANK SELECT MASK IS INSERTED INTO THE MBC BANK 
+; IPS.  THE RESULTING BANK SELECT MASK IS INSERTED INTO THE MBC BANK
 ; SELECT ROUTINE.
-; 
-#IF (MEMMGR == MM_MBC) 
+;
+#IF (MEMMGR == MM_MBC)
 ;
 	; ALTHOUGH DYNAMIC SYSTEM RAM SIZING IS NOT POSSIBLE FOR MBC
 	; (SEE COMMENTS ABOVE), WE ARE STILL DOING THE MASK SETUP
@@ -2015,7 +2015,7 @@ CB_IDS:	LD	(HL),A				; POPULATE CB_BIDCOM
 ;
 	LD	A,(CB_BIDUSR)
 	LD	(HB_SRCBNK),A			; POPULATE HB_SRCBNK
-	LD	(HB_DSTBNK),A			; POPULATE HB_DSTBNK		
+	LD	(HB_DSTBNK),A			; POPULATE HB_DSTBNK
 ;
 	LD	A,BID_RAM0			; POPULATE CB_BIDRAMD0	; START RAMBANK
 	LD	(HL),A
@@ -2148,6 +2148,11 @@ HB_START2:
 	LD	(RTC_DISPACT),A		; RTC DEVICE
 	LD	(DSKY_DISPACT),A	; DSKY DEVICE
 ;
+; INITIALIZE SOME HCB ENTRIES
+;
+	OR	$FF			; $FF TO ACCUM
+	LD	(CB_CRTDEV),A		; RESET CRT DEVICE
+;
 ; CLEAR INTERRUPT VECTOR TABLES
 ;
 ; THIS IS REALLY ONLY REQUIRED ON A RESTART, BUT IT DOESN'T HURT TO
@@ -2163,12 +2168,12 @@ HB_START2:
 	LD	(HB_IM1CNT),A		; ... TO CLEAR IM1 VECTOR CNT
 	LD	HL,HB_IM1INT		; POINTER TO START OF IM1 IVT
 	LD	(HB_IM1PTR),HL		; ... TO CLEAR IM1 PTR
-	
+
 	LD	HL,HB_TICK
 	LD	(VEC_TICK + 1),HL
 	LD	HL,HB_SECOND
 	LD	(VEC_SECOND + 1),HL
-	
+
 	JR	HB_CLRIVT_Z		; DONE, JUMP OVER SUBROUTINE
 ;
 HB_CLRIVT:
@@ -2299,6 +2304,9 @@ HB_CPU1:
 	LD	B,BF_DSKYSHOWSEG
 	CALL	DSKY_DISPATCH
 #ENDIF
+#IF (LCDENABLE)
+	CALL	LCD_PREINIT
+#ENDIF
 #IF (H8PENABLE)
 	CALL	H8P_PREINIT
 #ENDIF
@@ -2378,7 +2386,7 @@ HB_CPU2:
 	; ADJUST HL TO REFLECT HALF SPEED OPERATION
 	SRL	H		; ADJUST HL ASSUMING
 	RR	L		; HALF SPEED OPERATION
-;	
+;
   #IF (Z180_CLKDIV >= 1)
 	LD	A,(HB_CPUTYPE)	; GET CPU TYPE
 	CP	2		; Z8S180 REV K OR BETTER?
@@ -3321,11 +3329,27 @@ HB_WDZ:
   #ENDIF
 ;
   #IF (PLATFORM == PLT_FZ80)
+	; IOBYTE: XXXXXVVC
+	;              00-	FORCE ONBOARD VGA/PS2 KBD (FV)
+	;              --1	FORCE PROPELLER CONSOLE (SCON)
+	;              110	NORMAL USB SERIAL BOOT
+	;
+	; WE ASSUME THAT THE ONBOARD VGA (FV) IS ALWAYS DETECTED AND
+	; WILL BE THE CURRENT CRTDEV.  SCON IS ASSUMED TO BE THE
+	; DEVICE AT CRTDEV + 1.  THESE ARE REASONABLE ASSUMPTIONS
+	; UNLESS THE DRIVER DETECTION OR DRIVER ORDER IS CHANGED.
 	IN	A,($36)			; GET IO BYTE
-	AND	%00000001		; ISOLATE CONSOLE BIT
-	JR	Z,INITSYS3		; NOT SET, BYPASS CONSOLE SWITCH
+	AND	%00000110		; ISOLATE BITS
+	JR	Z,HB_CRTACT		; FORCE ONBOARD CRT
+	IN	A,($36)			; GET IO BYTE
+	AND	%00000001		; ISOLATE BIT
+	JR	Z,INITSYS3		; NORMAL USB SERIAL BOOT
+	LD	A,(CB_CRTDEV)		; GET CRT DEV
+	INC	A			; SWITCH FROM FV -> SCON
+	LD	(CB_CRTDEV),A		; SAVE IT AND DO CONSOLE SWITCH
   #ENDIF
 ;
+HB_CRTACT:
 	LD	A,(CB_CRTDEV)		; GET CRT DISPLAY DEVICE
 	LD	(HB_NEWCON),A		; AND QUEUE TO SWITCH
 ;
@@ -3387,7 +3411,7 @@ HB_FP2:
 	LD	B,A			; MOVE TO B
 	LD	A,SECCON		; GET SEC CONSOLE SETTING
 	CP	$FF			; $FF MEANS USE INCREMENT
-	JR	NZ,HB_FP3		; BYPASS IF NOT $FF 
+	JR	NZ,HB_FP3		; BYPASS IF NOT $FF
 ;
 	; INCREMENT CONSOLE UNIT
 	LD	A,(HB_NEWCON)		; GET NEW CONSOLE UNIT
@@ -3700,6 +3724,9 @@ HB_INITTBL:
 	.DW	PKD_INIT
   #ENDIF
 #ENDIF
+#IF (LCDENABLE)
+	.DW	LCD_INIT
+#ENDIF
 #IF (H8PENABLE)
 	.DW	H8P_INIT
 #ENDIF
@@ -3796,6 +3823,18 @@ HB_INITTBL:
 #IF (VRCENABLE)
 	.DW	VRC_INIT
 #ENDIF
+#IF (FVENABLE)
+	.DW	FV_INIT
+#ENDIF
+#IF (PRPENABLE)
+	.DW	PRP_INIT
+#ENDIF
+#IF (PPPENABLE)
+	.DW	PPP_INIT
+#ENDIF
+#IF (SCONENABLE)
+	.DW	SCON_INIT
+#ENDIF
 #IF (DMAENABLE)
 	.DW	DMA_INIT
 #ENDIF
@@ -3829,15 +3868,6 @@ HB_INITTBL:
 #IF (SYQENABLE)
 	.DW	SYQ_INIT
 #ENDIF
-#IF (PRPENABLE)
-	.DW	PRP_INIT
-#ENDIF
-#IF (PPPENABLE)
-	.DW	PPP_INIT
-#ENDIF
-#IF (SCONENABLE)
-	.DW	SCON_INIT
-#ENDIF
 #IF (CHENABLE)
 	.DW	CH_INIT
 #ENDIF
@@ -3971,6 +4001,24 @@ CIO_SIZ		.EQU	CIO_MAX * 4	; EACH ENTRY IS 4 BYTES
 CIO_CNT		.DB	0		; ENTRY COUNT PREFIX
 CIO_TBL		.FILL	CIO_SIZ,0	; SPACE FOR ENTRIES
 ;
+; CRT TYPE CHAR DEVICES CALL THIS TO REGISTER THAT THEY WANT TO BE THE
+; DEFAULT CRT DEVICE.  THIS ROUTINE WILL SET CB_CRTDEV WHEN CALLED THE
+; FIRST TIME.  SUBSEQUENT CALLS ARE IGNORED.  THIS ENSURES THAT THE
+; *FIRST* CRT DEVICE WINS.
+;
+CIO_SETCRT:
+	PUSH	AF			; SAVE INCOMING CRT DEV NUM
+	LD	A,(CB_CRTDEV)		; GET CURRENT CRT DEV NUM
+	INC	A			; $FF -> $00
+	JR	NZ,CIO_SETCRT_Z		; IF ALREADY SET, LEAVE IT ALONE
+	POP	AF			; RESTORE AF
+	LD	(CB_CRTDEV),A		; SAVE CRT DEV NUM
+	RET				; AND DONE
+;	
+CIO_SETCRT_Z:
+	POP	AF			; RESTORE AF
+	RET				; AND DONE
+;
 ;--------------------------------------------------------------------------------------------------
 ; DISK I/O DEVICE FUNCTION DISPATCHER
 ;--------------------------------------------------------------------------------------------------
@@ -4293,10 +4341,15 @@ HB_DSKFUNC	.DB	0		; CURRENT DISK FUNCTION
 ;   HL: ADDRESS OF 32-BIT SECTOR NUMBER (LITTLE-ENDIAN)
 ;   ALL REGISTERS PERSERVED
 ;
+HB_DSKACT:
+#IF (LCDENABLE)
+  #IF (LCDDSKACT)
+	CALL	LCD_DSKACT
+  #ENDIF
+#ENDIF
 #IF (DSKYENABLE)
   #IF (DSKYDSKACT)
 ;
-HB_DSKACT:
 	; SAVE EVERYTHING
 	PUSH	AF
 	PUSH	BC
@@ -4341,7 +4394,7 @@ HB_DSKACT2:
 	POP	DE
 	POP	BC
 	POP	AF
-	RET				; DONE
+	JR	HB_DSKACT_Z		; DONE
 ;
 ; THIS IS THE CHS VARIANT OF THE ABOVE.  THIS IS USED BY CHS ORIENTED
 ; DISK DRIVERS (BASICALLY JUST FLOPPY).
@@ -4366,6 +4419,9 @@ HB_DSKACTCHS:
   #ENDIF
 #ENDIF
 ;
+HB_DSKACT_Z:
+	RET
+;
 ;--------------------------------------------------------------------------------------------------
 ; REAL TIME CLOCK DEVICE DISPATCHER
 ;--------------------------------------------------------------------------------------------------
@@ -6591,7 +6647,7 @@ Z280_PRIVINST:
 	;;;HB_DI			; DO THE DI
 	XOR	A			; NO INTERRUPTS
 	LD	(HB_MSRSAV),A		; UPDATE SAVED MSR LSB
-	
+
 	INC	HL			; BUMP PAST IT
 	JR	Z280_PRIVINSTX
 ;
@@ -7035,7 +7091,7 @@ RS_IMAGE:
 RS_START:
 	LD	A,(HB_CURBNK)		; GET CURRENT BANK
 	PUSH	AF			; SAVE IT
-	
+
 	LD	C,0			; RUNNING BANK COUNT
 	LD	HL,$7FFF		; BYTE TEST ADDRESS
 	LD	IX,RS_ARY		; ORIG BYTE STORAGE ARRAY PTR
@@ -7067,7 +7123,7 @@ RS_LOOP1:
 	LD	(HL),A
 	OR	A			; ZERO?
 	JR	Z,RS_NEXT		; SKIP STORED VALUE CHECK
-	
+
 	; VERIFY ALL STORED VALUES
 	LD	B,C			; INIT LOOP COUNTER
 	LD	E,0			; INIT BANK ID
@@ -7084,7 +7140,7 @@ RS_LOOP3:
 RS_NEXT:
 	INC	C			; ADD 1 TO RAM BANK COUNT
 	JR	RS_LOOP1		; AND LOOP TILL DONE
-;	
+;
 RS_DONE:
 	LD	E,C			; FINAL BANK COUNT TO E
 	LD	A,C
@@ -7200,7 +7256,7 @@ FP_SETLEDS:
   #IF (FPLED_INV)
 	XOR	$FF			; INVERT BITS IF NEEDED
   #ENDIF
-	OUT	(FPLED_IO),A		; WRITE 
+	OUT	(FPLED_IO),A		; WRITE
 FP_SETLEDS1:
 	POP	HL			; RESTORE HL
 	RET				; DONE
@@ -7437,7 +7493,7 @@ PS_PRTDT:
 	LD	A,00001111B
 	CALL	PRTIDXMSK
 	CALL	PS_PAD18		; PAD TO 18 SPACES
-	RET	
+	RET
 ;
 ; PRINT DISK CAPACITY (UNIT IN C, ATTRIBUTE IN E)
 ;
@@ -7908,6 +7964,7 @@ PS_VDGDC	.TEXT	"GDC$"
 PS_VDTMS	.TEXT	"TMS$"
 PS_VDVGA	.TEXT	"VGA$"
 PS_VDVRC	.TEXT	"VRC$"
+PS_VDFV		.TEXT	"FV$"
 ;
 ; VIDEO TYPE STRINGS
 ;
@@ -7957,6 +8014,15 @@ SIZ_PKD	.EQU	$ - ORG_PKD
   #ENDIF
 #ENDIF
 ;
+#IF (LCDENABLE)
+ORG_LCD	.EQU	$
+  #INCLUDE "lcd.asm"
+SIZ_LCD	.EQU	$ - ORG_LCD
+		MEMECHO	"LCD occupies "
+		MEMECHO	SIZ_LCD
+		MEMECHO	" bytes.\n"
+#ENDIF
+;
 #IF (H8PENABLE)
 ORG_H8P	.EQU	$
   #INCLUDE "h8p.asm"
@@ -8209,6 +8275,15 @@ SIZ_VRC	.EQU	$ - ORG_VRC
 		MEMECHO	" bytes.\n"
 #ENDIF
 ;
+#IF (FVENABLE)
+ORG_FV	.EQU	$
+  #INCLUDE "fv.asm"
+SIZ_FV	.EQU	$ - ORG_FV
+		MEMECHO	"FV occupies "
+		MEMECHO	SIZ_FV
+		MEMECHO	" bytes.\n"
+#ENDIF
+;
 #IF (DMAENABLE)
 ORG_DMA	.EQU	$
 #INCLUDE "dma.asm"
@@ -8537,7 +8612,7 @@ HB_TICKS	.FILL	4,0		; 32 BIT TICK COUNTER
 HB_SECTCK	.DB	TICKFREQ	; TICK COUNTER FOR FRACTIONAL SECONDS
 HB_SECS		.FILL	4,0		; 32 BIT SECONDS COUNTER
 ;
-HB_CPUTYPE	.DB	0		; 0=Z80, 1=80180, 2=SL1960, 3=ASCI BRG
+HB_CPUTYPE	.DB	0		; 0=Z80, 1=Z180, 2=Z180-K, 3=Z180-N, 4=Z280
 HB_CPUOSC	.DW	CPUOSC		; ACTUAL CPU HARDWARE OSC FREQ IN KHZ
 ;
 HB_BATCOND	.DB	0		; BATTERY CONDITION (0=LOW, 1=OK)
@@ -8615,7 +8690,7 @@ HB_APPBOOT1:
 	; APPBOOT REQUIRES THAT THE COMMON BANK IS NOT CHANGED BY
 	; THE NEW CONFIG.  TEST FOR THIS AND DIAGNOSE IF SO.
 	LD	A,(HCB_BIDCOM)		; RUNNING COMMON BANK ID
-	
+
 	LD	B,BF_SYSGET		; HBIOS SYSGET
 	LD	C,BF_SYSGET_BNKINFO	; BANK INFORMATION
 	RST	08			; D = BIOS BANK ID
@@ -8824,7 +8899,7 @@ SLACK		.EQU	BNKTOP - $
 	!!!	; FORCE AN ASSEMBLY ERROR
 #ENDIF
 ;
-;;;#IF (SLACK < (1024 * 3))	
+;;;#IF (SLACK < (1024 * 3))
 ;;;	.ECHO	"*** ERROR: Low HEAP space!!!\n"
 ;;;	!!!	; FORCE AN ASSEMBLY ERROR
 ;;;#ENDIF

Source/HBIOS/hbios.inc

@@ -157,7 +157,7 @@ PLT_DUO		.EQU	17		; DUODYNE Z80 SYSTEM
 PLT_HEATH	.EQU	18		; HEATHKIT H8 Z80 SYSTEM
 PLT_EPITX	.EQU	19		; Z180 MINI-ITX
 PLT_MON		.EQU	20		; MONSPUTER
-PLT_STDZ180	.EQU	21		; GENESIS Z180 SYSTEM
+PLT_GMZ180	.EQU	21		; GENESIS Z180 SYSTEM
 PLT_NABU	.EQU	22		; NABU PERSONAL COMPUTER
 PLT_FZ80	.EQU	23		; S100 FPGA Z80
 ;
@@ -377,6 +377,7 @@ VDADEV_TMS	.EQU	$03		; N8 ONBOARD VDA SUBSYSTEM - TMS 9918
 VDADEV_VGA	.EQU	$04		; ECB VGA3 - HITACHI HD6445
 VDADEV_VRC	.EQU	$05		; VGARC
 VDADEV_EF	.EQU	$06		; EF9345
+VDADEV_FV	.EQU	$07		; S100 FPGA VGA
 ;
 ; SOUND DEVICE IDS
 ;

Source/HBIOS/hdsk.asm

@@ -239,13 +239,13 @@ HDSK_RW0:
 	XOR	A			; A = 0
 	LD	(HDSK_RC),A		; CLEAR RETURN CODE
 ;
-#IF (DSKYENABLE)
-  #IF (DSKYDSKACT)
+;;;#IF (DSKYENABLE)
+;;;  #IF (DSKYDSKACT)
 	LD	A,HDSK_LBA
 	CALL	LDHLIYA
 	CALL	HB_DSKACT		; SHOW ACTIVITY
-  #ENDIF
-#ENDIF
+;;;  #ENDIF
+;;;#ENDIF
 ;
 	; CONVERT LBA HHHH:LLLL (4 BYTES)
 	; TO HDSK TRACK/SECTOR TTTT:SS (3 BYTES)

Source/HBIOS/ide.asm

@@ -18,6 +18,7 @@
 ;	MK4	$80	N/A	N/A
 ;	RC	$10	N/A	N/A
 ;	SMB	$E0	N/A	N/A
+;	GIDE	$20	$20	$28  - Genesis IDE controller - Note Read Hi Low - Write - Low High   
 ;
 ;	+-----------------------------------------------------------------------+
 ;	| CONTROL BLOCK REGISTERS						|
@@ -224,6 +225,9 @@ IDE_DEV0M:	; DEVICE 0, MASTER
   #IF (IDE0MODE == IDEMODE_DIDE)
 	DEVECHO	"DIDE"
   #ENDIF
+  #IF (IDE0MODE == IDEMODE_GIDE)
+	DEVECHO	"GIDE"
+  #ENDIF
   #IF (IDE0MODE == IDEMODE_MK4)
 	DEVECHO	"MK4"
   #ENDIF
@@ -259,6 +263,9 @@ IDE_DEV0S:	; DEVICE 0, SLAVE
   #IF (IDE0MODE == IDEMODE_DIDE)
 	DEVECHO	"DIDE"
   #ENDIF
+  #IF (IDE0MODE == IDEMODE_GIDE)
+	DEVECHO	"GIDE"
+  #ENDIF
   #IF (IDE0MODE == IDEMODE_MK4)
 	DEVECHO	"MK4"
   #ENDIF
@@ -297,6 +304,9 @@ IDE_DEV1M:	; DEVICE 1, MASTER
   #IF (IDE1MODE == IDEMODE_DIDE)
 	DEVECHO	"DIDE"
   #ENDIF
+  #IF (IDE1MODE == IDEMODE_GIDE)
+	DEVECHO	"GIDE"
+  #ENDIF
   #IF (IDE1MODE == IDEMODE_MK4)
 	DEVECHO	"MK4"
   #ENDIF
@@ -332,6 +342,9 @@ IDE_DEV1S:	; DEVICE 1, SLAVE
   #IF (IDE1MODE == IDEMODE_DIDE)
 	DEVECHO	"DIDE"
   #ENDIF
+  #IF (IDE1MODE == IDEMODE_GIDE)
+	DEVECHO	"GIDE"
+  #ENDIF
   #IF (IDE1MODE == IDEMODE_MK4)
 	DEVECHO	"MK4"
   #ENDIF
@@ -370,6 +383,9 @@ IDE_DEV2M:	; DEVICE 2, MASTER
   #IF (IDE2MODE == IDEMODE_DIDE)
 	DEVECHO	"DIDE"
   #ENDIF
+  #IF (IDE2MODE == IDEMODE_GIDE)
+	DEVECHO	"GIDE"
+  #ENDIF
   #IF (IDE2MODE == IDEMODE_MK4)
 	DEVECHO	"MK4"
   #ENDIF
@@ -405,6 +421,9 @@ IDE_DEV2S:	; DEVICE 2, SLAVE
   #IF (IDE2MODE == IDEMODE_DIDE)
 	DEVECHO	"DIDE"
   #ENDIF
+  #IF (IDE2MODE == IDEMODE_GIDE)
+	DEVECHO	"GIDE"
+  #ENDIF
   #IF (IDE2MODE == IDEMODE_MK4)
 	DEVECHO	"MK4"
   #ENDIF
@@ -491,6 +510,9 @@ IDE_INIT2:
 	LD	DE,IDE_STR_MODE_RC	; MODE LABEL
 	CP	IDEMODE_RC		; TEST FOR MODE
 	JR	Z,IDE_INIT2A		; IF SO, DISPLAY IT
+	LD	DE,IDE_STR_MODE_GIDE	; MODE LABEL
+	CP	IDEMODE_GIDE		; TEST FOR MODE
+	JR	Z,IDE_INIT2A		; IF SO, DISPLAY IT
 	JR	IDE_INIT4		; NO MODE?  BYPASS ENTRY
 IDE_INIT2A:
 	CALL	WRITESTR		; DISPLAY MODE
@@ -920,13 +942,13 @@ IDE_PKT_RDSEC:
 #ENDIF
 	; SETUP LBA
 ;
-#IF (DSKYENABLE)
-  #IF (DSKYDSKACT)
+;;;#IF (DSKYENABLE)
+;;;  #IF (DSKYDSKACT)
 	LD	A,IDE_LBA
 	CALL	LDHLIYA
 	CALL	HB_DSKACT		; SHOW ACTIVITY
-  #ENDIF
-#ENDIF
+;;;  #ENDIF
+;;;#ENDIF
 ;
 	; 3 BYTES, LITTLE ENDIAN -> BIG ENDIAN
 	LD	HL,IDE_PKTCMD_RW10+3	; START OF LBA FIELD IN CDB (MSB)
@@ -989,13 +1011,13 @@ IDE_PKT_WRSEC:
 #ENDIF
 	; SETUP LBA
 ;
-#IF (DSKYENABLE)
-  #IF (DSKYDSKACT)
+;;;#IF (DSKYENABLE)
+;;;  #IF (DSKYDSKACT)
 	LD	A,IDE_LBA
 	CALL	LDHLIYA
 	CALL	HB_DSKACT		; SHOW ACTIVITY
-  #ENDIF
-#ENDIF
+;;;  #ENDIF
+;;;#ENDIF
 ;
 	; 3 BYTES, LITTLE ENDIAN -> BIG ENDIAN
 	LD	HL,IDE_PKTCMD_RW10+3	; START OF LBA FIELD IN CDB (MSB)
@@ -1021,13 +1043,13 @@ IDE_PKT_WRSEC:
 ;
 IDE_SETADDR:
 ;
-#IF (DSKYENABLE)
-  #IF (DSKYDSKACT)
+;;;#IF (DSKYENABLE)
+;;;  #IF (DSKYDSKACT)
 	LD	A,IDE_LBA
 	CALL	LDHLIYA
 	CALL	HB_DSKACT		; SHOW ACTIVITY
-  #ENDIF
-#ENDIF
+;;;  #ENDIF
+;;;#ENDIF
 	; SEND 3 LOWEST BYTES OF LBA IN REVERSE ORDER
 	; IDE_REG_LBA3 HAS ALREADY BEEN SET
 	; HSTLBA2-0 --> IDE_REG_LBA2-0
@@ -1253,10 +1275,17 @@ IDE_GET16:
 	RET
 ;
 IDE_GET16A:
+#IF (IDE0MODE == IDEMODE_GIDE)		; GENESIS BOARD IS REVERSED
+	LD	C,E			; PORT FOR MSB
+	INI				; GET IT, SAVE IT, AND DEC B
+	LD	C,D			; PORT FOR LSB
+	INI				; GET IT, SAVE IT, AND DEC B
+#ELSE
 	LD	C,D			; PORT FOR LSB
 	INI				; GET IT, SAVE IT, AND DEC B
 	LD	C,E			; PORT FOR MSB
 	INI				; GET IT, SAVE IT, AND DEC B
+#ENDIF
 	DEC	A
 	JR	NZ,IDE_GET16A		; LOOP TILL COUNTER EXHAUSTED
 	RET
@@ -1318,11 +1347,18 @@ IDE_PUT16:
 	RET
 ;
 IDE_PUT16A:
+#IF (IDE0MODE == IDEMODE_GIDE)		; GENESIS BOARD IS REVERSED
+	LD	C,E			; PORT FOR MSB
+	OUTI				; PUT IT AND DEC B
+	LD	C,D			; PORT FOR LSB
+	OUTI				; PUT IT AND DEC B
+#ELSE
 	LD	C,D			; PORT FOR LSB
 	OUTI				; PUT IT AND DEC B
 	LD	C,E			; PORT FOR MSB
 	OUTI				; PUT IT AND DEC B
 	DEC	A
+#ENDIF
 	JR	NZ,IDE_PUT16A		; LOOP TILL COUNTER EXHAUSTED
 	RET
 ;
@@ -1990,6 +2026,16 @@ IDE_OUT:
 	EX	(SP),HL			; GET PARM POINTER
 	PUSH	BC
 	PUSH	AF
+;
+#IF (IDE0MODE == IDEMODE_GIDE)    ; SET TOP BYTE TO 0 FOR GENESIS BOARD 
+	LD	A,(HL)
+	LD	C,(IY+IDE_DATAHI)
+	ADD	A,C
+	LD	C,A
+	LD    A,0
+	OUT	(C),A
+#ENDIF
+;
 	LD	A,(HL)
 	INC	HL
 	LD	C,(IY+IDE_IOBASE)
@@ -2189,6 +2235,7 @@ IDE_STR_MODE_DIO	.TEXT	"DIO$"
 IDE_STR_MODE_DIDE	.TEXT	"DIDE$"
 IDE_STR_MODE_MK4	.TEXT	"MK4$"
 IDE_STR_MODE_RC		.TEXT	"RC$"
+IDE_STR_MODE_GIDE	.TEXT	"GIDE$"
 ;
 IDE_STR_TYPEATA		.TEXT	" ATA$"
 IDE_STR_TYPEATAPI	.TEXT	" ATAPI$"

Source/HBIOS/imm.asm

@@ -343,13 +343,13 @@ IMM_IO:
 ;
 	LD	(IMM_DSKBUF),HL		; SAVE DISK BUFFER ADDRESS
 ;
-#IF (DSKYENABLE)
-  #IF (DSKYDSKACT)
+;;;#IF (DSKYENABLE)
+;;; #IF (DSKYDSKACT)
 	LD	A,IMM_LBA
 	CALL	LDHLIYA
 	CALL	HB_DSKACT		; SHOW ACTIVITY
-  #ENDIF
-#ENDIF
+;;;  #ENDIF
+;;;#ENDIF
 ;
 	; SETUP LBA
 	; 3 BYTES, LITTLE ENDIAN -> BIG ENDIAN

Source/HBIOS/lcd.asm

@@ -0,0 +1,392 @@
+;
+;==================================================================================================
+; HARDWARE SUPPORT FOR HITACHI HD44780 OR EQUIVALENT
+;==================================================================================================
+;
+; CURRENTLY ASSUMES A 20X4 DISPLAY
+;
+; TYPICAL PORTS USED ON RCBUS ECOSYSTEM:
+;
+;		PRIMARY		ALT
+; FUNCTION	$DA		$AA
+; DATA		$DB		$AB
+;
+LCD_FUNC	.EQU	LCDBASE + 0	; WRITE
+LCD_STAT	.EQU	LCDBASE + 0	; READ
+LCD_DATA	.EQU	LCDBASE + 1	; READ/WRITE
+;
+LCD_FUNC_CLEAR	.EQU	$01		; CLEAR DISPLAY
+LCD_FUNC_HOME	.EQU	$02		; HOME CURSOR & REMOVE ALL SHIFTING
+LCD_FUNC_ENTRY	.EQU	$04		; SET CUR DIR AND DISPLAY SHIFT
+LCD_FUNC_DISP	.EQU	$08		; DISP, CUR, BLINK ON/OFF
+LCD_FUNC_SHIFT	.EQU	$10		; MOVE CUR / SHIFT DISP
+LCD_FUNC_SET	.EQU	$20		; SET INTERFACE PARAMS
+LCD_FUNC_CGADR	.EQU	$40		; SET CGRAM ADRESS
+LCD_FUNC_DDADR	.EQU	$80		; SET DDRAM ADDRESS
+;
+	DEVECHO	"LCD: IO="
+	DEVECHO	LCDBASE
+	DEVECHO	"\n"
+;
+; HARDWARE RESET PRIOR TO ROMWBW CONSOLE INITIALIZATION
+;
+LCD_PREINIT:
+;
+	; RESET	LCD CONTROLLER, DELAYS ARE FIXED, BUSY FLAG
+	; CANNOT BE USED YET, CONTROLLER MAY NOT EXIST!
+	LD	A,LCD_FUNC_SET | %11000
+	OUT	(LCD_FUNC),A
+	LD	DE,50000/16		; WAIT >40MS, WE USE 50MS
+	CALL	VDELAY			; DO IT
+	LD	A,LCD_FUNC_SET | %11000
+	OUT	(LCD_FUNC),A
+	LD	DE,5000/16		; WAIT >4.1MS, WE USE 5MS
+	CALL	VDELAY			; DO IT
+	LD	A,LCD_FUNC_SET | %11000
+	OUT	(LCD_FUNC),A
+	LD	DE,5000/16		; WAIT >4.1MS, WE USE 5MS
+	CALL	VDELAY			; DO IT
+;
+	; TEST FOR PRESENCE...
+	CALL	LCD_DETECT		; PROBE FOR HARDWARE
+	LD	A,(LCD_PRESENT)		; GET PRESENCE FLAG
+	OR	A			; SET FLAGS
+	RET	Z			; BAIL OUT IF NOT PRESENT
+;
+	; WE CAN NOW DO NORMAL I/O W/ BUSY FLAG
+	LD	DE,LCD_INIT_SEQ		; INIT SEQUENCE
+	CALL	LCD_OUTFS		; SEND IT
+;
+	; PUT SOMETHING ON THE DISPLAY
+	LD	DE,LCD_STR_BAN
+	CALL	LCD_OUTDS
+;
+	; SECOND LINE
+	; CPU TYPE
+	LD	HL,$0100		; ROW 2, COL 0
+	CALL	LCD_GOTORC
+	LD	HL,LCD_CPU
+	LD	A,(HB_CPUTYPE)		; GET CPU TYPE
+	RRCA				; WORD OFFSET
+	CALL	ADDHLA			; ADD OFFSET
+	LD	E,(HL)			; GET LSB
+	INC	HL			; BUMP
+	LD	D,(HL)			; GET MSB
+	CALL	LCD_OUTDS
+	LD	DE,LCD_STR_XPU
+	CALL	LCD_OUTDS
+;
+	; "12.345 MHz" RIGHT JUSTIFIED
+	LD	HL,$010A		; ROW 2, COL 10
+	CALL	LCD_GOTORC
+	LD	HL,(CB_CPUKHZ)
+	PUSH	HL
+	LD	BC,10000		; 10 MHZ
+	SBC	HL,BC			; SUBTRACT
+	JR	NC,LCD_PREINIT1
+	LD	A,' '			; EXTRA PAD
+	CALL	LCD_OUTD
+LCD_PREINIT1:
+	POP	HL
+	CALL	LCD_PRTD3M		; PRINT AS DECIMAL WITH 3 DIGIT MANTISSA
+	LD	DE,LCD_STR_MHZ
+	CALL	LCD_OUTDS
+;
+	; THIRD LINE
+	LD	HL,$0200		; ROW 2, COL 0
+	CALL	LCD_GOTORC
+	LD	DE,LCD_STR_CFG
+	CALL	LCD_OUTDS
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
+;
+; POST CONSOLE INITIALIZATION
+;
+LCD_INIT:
+	CALL	NEWLINE			; FORMATTING
+	PRTS("LCD: IO=$")
+	LD	A,LCDBASE
+	CALL	PRTHEXBYTE
+;
+	LD	A,(LCD_PRESENT)		; GET PRESENCE FLAG
+	OR	A			; SET FLAGS
+	JR	Z,LCD_INIT1		; HANDLE NOT PRESENT
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
+;
+LCD_INIT1:
+	PRTS(" NOT PRESENT$")
+	OR	$FF
+	RET
+;
+; CALLED FROM HBIOS RIGHT BEFORE A DISK ACCESS
+;   HL: ADDRESS OF 32-BIT SECTOR NUMBER (LITTLE-ENDIAN)
+;
+; FORMAT: "Disk #99  R:12345678"
+;          01234567890123456789
+;
+LCD_DSKACT:
+	; SAVE EVERYTHING
+	PUSH	AF
+	PUSH	BC
+	PUSH	DE
+	PUSH	HL
+;
+	LD	A,(LCD_PRESENT)		; GET PRESENCE FLAG
+	OR	A			; SET FLAGS
+	JR	Z,LCD_DSKACT_Z		; HANDLE NOT PRESENT
+;
+	PUSH	HL
+	LD	HL,$0300		; ROW 3, COL 0
+	CALL	LCD_GOTORC		; SET DISPLAY ADDRESS
+	POP	HL
+;
+	LD	DE,LCD_STR_IO		; PREFIX
+	CALL	LCD_OUTDS		; SEND TO DISPLAY (COLS 0-5)
+;
+	LD	A,(HB_DSKUNIT)		; GET DISK UNIT NUM
+	CALL	LCD_DSKACT_BYTE		; SEND TO DISPLAY (COLS 6-7) HEX???
+;
+	LD	A,' '			; SEPARATOR
+	CALL	LCD_OUTD		; SEND TO DISPLAY (COL 8)
+	CALL	LCD_OUTD		; SEND TO DISPLAY (COL 9)
+;
+	LD	A,(HB_DSKFUNC)		; ACTIVE DISK FUNCTION
+	CP	BF_DIOWRITE		; WRITE?
+	LD	A,'W'			; ASSUME WRITE
+	JR	Z,LCD_DSKACT0		; GO AHEAD
+	LD	A,'R'			; OTHERWISE READ
+LCD_DSKACT0:
+	CALL	LCD_OUTD		; SEND CHAR (COL 10)
+;
+	LD	A,':'			; SEPARATOR
+	CALL	LCD_OUTD		; SEND TO DISPLAY (COL 11)
+;
+	LD	A,3			; POINT TO
+	CALL	ADDHLA			; END OF DWORD (MSB)
+	LD	B,4			; DO 4 BYTES
+;
+LCD_DSKACT1:
+	LD	A,(HL)			; GET BYTE
+	CALL	LCD_DSKACT_BYTE		; SEND TO DISPLAY (COLS 12-19)
+	DEC	HL			; DEC PTR
+	DJNZ	LCD_DSKACT1		; DO ALL 4 BYTES
+;
+LCD_DSKACT_Z:
+	; CLEAN UP AND GO AWAY
+	POP	HL
+	POP	DE
+	POP	BC
+	POP	AF
+	RET
+;
+LCD_DSKACT_BYTE:
+	PUSH	AF			; SAVE BYTE
+	RRCA				; DO TOP NIBBLE FIRST
+	RRCA
+	RRCA
+	RRCA
+	CALL	HEXCONV			; CONVERT NIBBLE TO ASCII
+	CALL	LCD_OUTD		; SEND TO DISPLAY
+	POP	AF			; RECOVER CURRENT BYTE
+	CALL	HEXCONV			; CONVERT NIBBLE TO ASCII
+	CALL	LCD_OUTD		; SEND TO DISPLAY
+	RET				; DONE
+;
+; DETECT PRESENCE OF LCD CONTROLLER BY WRITING AND READING BACK
+; TEST VALUES IN THE CONTROLLER RAM.
+; WE DO NOT USE THE NORMAL READ/WRITE ROUTINES BECAUSE WE DO
+; NOT WANT TO STALL WAITING ON THE BUSY FLAG IF THE CONTROLLER
+; IS NOT PRESENT
+;
+LCD_DETECT:
+	; FIRST PASS W/ TEST VALUE $AA
+	LD	C,$AA
+	CALL	LCD_DETECT_PASS
+	JR	NZ,LCD_DETECT1
+;
+	; SECOND PASS W/ TEST VALUE $55
+	LD	C,$55
+	CALL	LCD_DETECT_PASS
+	JR	NZ,LCD_DETECT1
+;
+	; LCD PRESENT
+	OR	$FF
+	JR	LCD_DETECT_Z
+;
+LCD_DETECT1:
+	; LCD NOT PRESENT
+	XOR	A
+	JR	LCD_DETECT_Z
+;
+LCD_DETECT_Z:
+	LD	(LCD_PRESENT),A
+	RET
+;
+; WRITE AND READBACK VALUE IN C TO THE FIRST BYTE OF DDRAM
+; RETURN WITH COMPARE RESULT
+;
+LCD_DETECT_PASS:
+	CALL	LCD_DELAY		; WAIT
+	LD	A,LCD_FUNC_DDADR
+	OUT	(LCD_FUNC),A		; POINT TO FIRST BYTE
+	CALL	LCD_DELAY		; WAIT
+	LD	A,C			; TEST VALUE
+	OUT	(LCD_DATA),A		; WRITE IT
+	CALL	LCD_DELAY		; WAIT
+	LD	A,LCD_FUNC_DDADR
+	OUT	(LCD_FUNC),A		; POINT TO FIRST BYTE
+	CALL	LCD_DELAY
+	IN	A,(LCD_DATA)		; GET VALUE
+	CP	C			; AS WRITTEN?
+	RET
+;
+; DELAY USED DURING DETECT, >37US
+;
+LCD_DELAY:
+	CALL	DELAY			; 16US
+	CALL	DELAY			; 16US
+	JP	DELAY			; 16US, TOTAL 48US
+;
+; SEND FUNCTION CODE IN A
+;
+LCD_OUTF:
+	PUSH	AF			; SAVE CODE
+LCD_OUTF1:
+	IN	A,(LCD_STAT)		; GET STATUS
+	AND	$80			; ISOLATE BUSY FLAG
+	JR	NZ,LCD_OUTF1		; LOOP TILL NOT BUSY
+	POP	AF			; RECOVER CODE
+	OUT	(LCD_FUNC),A		; SEND IT
+	RET				; DONE
+;
+; SEND FUNCTION STRING
+; DE=STRING ADDRESS, NULL TERMINATED
+;
+LCD_OUTFS:
+	LD	A,(DE)			; NEXT BYTE TO SEND
+	OR	A			; SET FLAGS
+	RET	Z			; DONE WHEN NULL REACHED
+	INC	DE			; BUMP POINTER
+	CALL	LCD_OUTF		; SEND IT
+	JR	LCD_OUTFS		; LOOP AS NEEDED
+;
+; SEND DATA BYTE IN A
+;
+LCD_OUTD:
+	PUSH	AF			; SAVE BYTE
+LCD_OUTD1:
+	IN	A,(LCD_STAT)		; GET STATUS
+	AND	$80			; ISOLATE BUSY FLAG
+	JR	NZ,LCD_OUTD1		; LOOP TILL NOT BUSY
+	POP	AF			; RECOVER BYTE
+	OUT	(LCD_DATA),A		; SEND IT
+	RET				; DONE
+;
+; SEND DATA STRING
+; DE=STRING ADDRESS, NULL TERMINATED
+;
+LCD_OUTDS:
+	LD	A,(DE)			; NEXT BYTE TO SEND
+	OR	A			; SET FLAGS
+	RET	Z			; DONE WHEN NULL REACHED
+	INC	DE			; BUMP POINTER
+	CALL	LCD_OUTD		; SEND IT
+	JR	LCD_OUTDS		; LOOP AS NEEDED
+;
+; GET DATA BYTE INTO A
+;
+LCD_IND:
+	IN	A,(LCD_STAT)		; GET STATUS
+	AND	$80			; ISOLATE BUSY FLAG
+	JR	NZ,LCD_IND		; LOOP TILL NOT BUSY
+	POP	AF			; RECOVER BYTE
+	IN	A,(LCD_DATA)		; GET IT
+	RET				; DONE
+;
+; GOTO ROW(H),COL(L)
+;
+LCD_GOTORC:
+	PUSH	HL			; SAVE INCOMING
+	LD	A,H			; ROW # TO A
+	LD	HL,LCD_ROWS		; POINT TO ROWS TABLE
+	CALL	ADDHLA			; INDEX TO ROW ENTRY
+	LD	A,(HL)			; GET RWO START
+	POP	HL			; RECOVER INCOMING
+	ADD	A,L			; ADD COLUMN
+	ADD	A,LCD_FUNC_DDADR	; APPLY FUNCTION BIT
+	JR	LCD_OUTF		; AND SEND IT
+;
+; PRINT VALUE OF HL AS THOUSANDTHS, IE. 0.000
+;
+LCD_PRTD3M:
+	PUSH	BC
+	PUSH	DE
+	PUSH	HL
+	LD	E,'0'
+	LD	BC,-10000
+	CALL	LCD_PRTD3M1
+	LD	E,0
+	LD	BC,-1000
+	CALL	LCD_PRTD3M1
+	LD	A,'.'
+	CALL	LCD_OUTD
+	LD	BC,-100
+	CALL	LCD_PRTD3M1
+	LD	C,-10
+	CALL	LCD_PRTD3M1
+	LD	C,-1
+	CALL	LCD_PRTD3M1
+	POP	HL
+	POP	DE
+	POP	BC
+	RET
+LCD_PRTD3M1:
+	LD	A,'0' - 1
+LCD_PRTD3M2:
+	INC	A
+	ADD	HL,BC
+	JR	C,LCD_PRTD3M2
+	SBC	HL,BC
+	CP	E
+	JR	Z,LCD_PRTD3M3
+	LD	E,0
+	CALL	LCD_OUTD
+LCD_PRTD3M3:
+	RET
+;
+; DATA STORAGE
+;
+LCD_PRESENT	.DB	0		; NON-ZERO WHEN HARDWARE DETECTED
+;
+LCD_ROWS	.DB	$00,$40,$14,$54	; ROW START INDEX
+;
+LCD_INIT_SEQ:
+	.DB	LCD_FUNC_SET | %11000	; FUNCTION SET, 2 LINES, 5X8 FONT
+	.DB	LCD_FUNC_DISP		; DISPLAY OFF
+	.DB	LCD_FUNC_CLEAR		; CLEAR DISPLAY, HOME CURSOR
+	.DB	LCD_FUNC_ENTRY | $02	; INCREMENT, NO SHIFT
+	.DB	LCD_FUNC_DISP | $04	; DISPLAY ON, NO CURSOR, NO BLINK
+	.DB	$00			; TERMINATOR
+;
+LCD_STR_BAN	.DB	"RomWBW v", BIOSVER, 0
+LCD_STR_CFG	.DB	"Build: ", CONFIG, 0
+LCD_STR_IO	.DB	"Disk #", 0
+LCD_STR_XPU	.DB	" CPU",0
+LCD_STR_SPD	.DB	"12.345",0
+LCD_STR_MHZ	.DB	" MHz",0
+;
+LCD_CPU		.DW	LCD_CPU_Z80
+		.DW	LCD_CPU_Z180
+		.DW	LCD_CPU_Z180K
+		.DW	LCD_CPU_Z180N
+		.DW	LCD_CPU_Z280
+;
+LCD_CPU_Z80	.DB	"Z80",0
+LCD_CPU_Z180	.DB	"Z180",0
+LCD_CPU_Z180K	.DB	"Z180-K",0
+LCD_CPU_Z180N	.DB	"Z180-N",0
+LCD_CPU_Z280	.DB	"Z280",0
+
+

Source/HBIOS/md.asm

@@ -64,6 +64,8 @@ MD_DEVCNT	.EQU	($ - MD_CFGTBL) / MD_CFGSIZ
 ;
 ;
 ;
+
+
 MD_INIT:
 #IF (MDFFENABLE)
 	CALL	MD_FINIT		; PROBE FLASH CAPABILITY
@@ -301,13 +303,13 @@ MD_RW:
 MD_RW1:
 	PUSH	BC			; SAVE COUNTERS
 ;
-#IF (DSKYENABLE)
-  #IF (DSKYDSKACT)
+;;;#IF (DSKYENABLE)
+;;;  #IF (DSKYDSKACT)
 	LD	A,MD_LBA
 	CALL	LDHLIYA
 	CALL	HB_DSKACT		; SHOW ACTIVITY
-  #ENDIF
-#ENDIF
+;;;  #ENDIF
+;;;#ENDIF
 ;
 	LD	HL,(MD_RWFNADR)		; GET PENDING IO FUNCTION ADDRESS
 #IF (MDFFENABLE)

Source/HBIOS/ppa.asm

@@ -339,13 +339,13 @@ PPA_IO:
 ;
 	LD	(PPA_DSKBUF),HL		; SAVE DISK BUFFER ADDRESS
 ;
-#IF (DSKYENABLE)
-  #IF (DSKYDSKACT)
+;;;#IF (DSKYENABLE)
+;;;  #IF (DSKYDSKACT)
 	LD	A,PPA_LBA
 	CALL	LDHLIYA
 	CALL	HB_DSKACT		; SHOW ACTIVITY
-  #ENDIF
-#ENDIF
+;;;  #ENDIF
+;;;#ENDIF
 ;
 	; SETUP LBA
 	; 3 BYTES, LITTLE ENDIAN -> BIG ENDIAN

Source/HBIOS/ppide.asm

@@ -830,13 +830,13 @@ PPIDE_PKT_RDSEC:
 #ENDIF
 	; SETUP LBA
 ;
-#IF (DSKYENABLE)
-  #IF (DSKYDSKACT)
+;;;#IF (DSKYENABLE)
+;;;  #IF (DSKYDSKACT)
 	LD	A,PPIDE_LBA
 	CALL	LDHLIYA
 	CALL	HB_DSKACT		; SHOW ACTIVITY
-  #ENDIF
-#ENDIF
+;;;  #ENDIF
+;;;#ENDIF
 ;
 	; 3 BYTES, LITTLE ENDIAN -> BIG ENDIAN
 	LD	HL,PPIDE_PKTCMD_RW10+3	; START OF LBA FIELD IN CDB (MSB)
@@ -899,13 +899,13 @@ PPIDE_PKT_WRSEC:
 #ENDIF
 	; SETUP LBA
 ;
-#IF (DSKYENABLE)
-  #IF (DSKYDSKACT)
+;;;#IF (DSKYENABLE)
+;;;  #IF (DSKYDSKACT)
 	LD	A,PPIDE_LBA
 	CALL	LDHLIYA
 	CALL	HB_DSKACT		; SHOW ACTIVITY
-  #ENDIF
-#ENDIF
+;;;  #ENDIF
+;;;#ENDIF
 ;
 	; 3 BYTES, LITTLE ENDIAN -> BIG ENDIAN
 	LD	HL,PPIDE_PKTCMD_RW10+3	; START OF LBA FIELD IN CDB (MSB)
@@ -931,13 +931,13 @@ PPIDE_PKT_WRSEC:
 ;
 PPIDE_SETADDR:
 ;
-#IF (DSKYENABLE)
-  #IF (DSKYDSKACT)
+;;;#IF (DSKYENABLE)
+;;;  #IF (DSKYDSKACT)
 	LD	A,PPIDE_LBA
 	CALL	LDHLIYA
 	CALL	HB_DSKACT		; SHOW ACTIVITY
-  #ENDIF
-#ENDIF
+;;;  #ENDIF
+;;;#ENDIF
 	; SEND 3 LOWEST BYTES OF LBA IN REVERSE ORDER
 	; IDE_REG_LBA3 HAS ALREADY BEEN SET
 	; HSTLBA2-0 --> IDE_REG_LBA2-0

Source/HBIOS/ppp.asm

@@ -276,7 +276,8 @@ PPPCON_INIT:
 	LD	E,CIODEV_PPPCON		; DEVICE TYPE
 	LD	BC,PPPCON_FNTBL		; BC := FUNCTION TABLE ADDRESS
 	CALL	CIO_ADDENT		; ADD ENTRY, A := UNIT ASSIGNED
-	LD	(HCB + HCB_CRTDEV),A	; SET OURSELVES AS THE CRT DEVICE
+	;;;LD	(HCB + HCB_CRTDEV),A	; SET OURSELVES AS THE CRT DEVICE
+	CALL	CIO_SETCRT		; SET OURSELVES AS THE CRT DEVICE
 ;
 	XOR	A
 	RET
@@ -948,11 +949,11 @@ PPPSD_SENDBLK:
 
 	LD	A,PPPSD_LBA		; OFFSET OF LBA
 	CALL	LDHLIYA			; HL := IY + A, REG A TRASHED
-#IF (DSKYENABLE)
-  #IF (DSKYDSKACT)
+;;;#IF (DSKYENABLE)
+;;;  #IF (DSKYDSKACT)
 	CALL	HB_DSKACT		; SHOW ACTIVITY
-  #ENDIF
-#ENDIF
+;;;  #ENDIF
+;;;#ENDIF
 	LD	B,4
 PPPSD_SENDBLK1:
 	LD	A,(HL)

Source/HBIOS/prp.asm

@@ -150,7 +150,8 @@ PRPCON_INIT:
 	LD	E,CIODEV_PRPCON		; DEVICE TYPE
 	LD	BC,PRPCON_FNTBL		; BC := FUNCTION TABLE ADDRESS
 	CALL	CIO_ADDENT		; ADD ENTRY, A := UNIT ASSIGNED
-	LD	(HCB + HCB_CRTDEV),A	; SET OURSELVES AS THE CRT DEVICE
+	;;;LD	(HCB + HCB_CRTDEV),A	; SET OURSELVES AS THE CRT DEVICE
+	CALL	CIO_SETCRT		; SET OURSELVES AS THE CRT DEVICE
 ;
 	XOR	A			; SIGNAL SUCCESS
 	RET
@@ -882,11 +883,11 @@ PRPSD_SETBLK:
 	LD	B,4			; 4 BYTES
 	LD	A,PRPSD_LBA		; OFFSET OF LBA
 	CALL	LDHLIYA			; HL := IY + A, REG A TRASHED
-#IF (DSKYENABLE)
-  #IF (DSKYDSKACT)
+;;;#IF (DSKYENABLE)
+;;;  #IF (DSKYDSKACT)
 	CALL	HB_DSKACT		; SHOW ACTIVITY
-  #ENDIF
-#ENDIF
+;;;  #ENDIF
+;;;#ENDIF
 	OTIR
 	RET
 ;

Source/HBIOS/rf.asm

@@ -333,13 +333,13 @@ RF_SETIO:
 ;
 RF_SETADR:
 ;
-#IF (DSKYENABLE)
-  #IF (DSKYDSKACT)
+;;;#IF (DSKYENABLE)
+;;;  #IF (DSKYDSKACT)
 	LD	A,RF_LBA
 	CALL	LDHLIYA
 	CALL	HB_DSKACT		; SHOW ACTIVITY
-  #ENDIF
-#ENDIF
+;;;  #ENDIF
+;;;#ENDIF
 ;
 	LD	A,(RF_IO)		; OUTPUT THE LOGICAL BLOCK
 	OR	RF_AL			; ADDRESS TO THE

Source/HBIOS/scon.asm

@@ -46,7 +46,8 @@ SCON_INIT:
 	LD	E,CIODEV_SCON		; DEVICE TYPE
 	LD	BC,SCON_FNTBL		; BC := FUNCTION TABLE ADDRESS
 	CALL	CIO_ADDENT		; ADD ENTRY, A := UNIT ASSIGNED
-	LD	(HCB + HCB_CRTDEV),A	; SET OURSELVES AS THE CRT DEVICE
+	;;;LD	(HCB + HCB_CRTDEV),A	; SET OURSELVES AS THE CRT DEVICE
+	CALL	CIO_SETCRT		; SET OURSELVES AS THE CRT DEVICE
 ;
 	XOR	A			; SIGNAL SUCCESS
 	RET

Source/HBIOS/sd.asm

@@ -125,8 +125,8 @@ SD_OPRREG	.EQU	RTCIO		; USES RTC LATCHES FOR OPERATION
 SD_OPRDEF	.EQU	%00000001	; QUIESCENT STATE
 SD_OPRMSK	.EQU	%10000111	; MASK FOR BITS WE OWN IN RTC LATCH PORT
 SD_INPREG	.EQU	RTCIO		; INPUT REGISTER IS RTC
-SD_CS0		.EQU	%00000100	; RTC:2 IS SELECT
-SD_CLK		.EQU	%00000010	; RTC:1 IS CLOCK
+SD_CS0	.EQU	%00000100	; RTC:2 IS SELECT
+SD_CLK	.EQU	%00000010	; RTC:1 IS CLOCK
 SD_DI		.EQU	%00000001	; RTC:0 IS DATA IN (CARD <- CPU)
 SD_DO		.EQU	%10000000	; RTC:7 IS DATA OUT (CARD -> CPU)
 SD_IOBASE	.EQU	SD_OPRREG	; IOBASE
@@ -242,7 +242,21 @@ SD_TRDR		.EQU	Z180_TRDR
 SD_IOBASE	.EQU	SD_OPRREG	; IOBASE
 SD_INVCS	.EQU	TRUE		; INVERT CS
 		DEVECHO	"SC"
+RTCDEF		.SET	RTCDEF | SD_OPRDEF	; SET DEFAULT IN HBIOS MAINLINE
+#ENDIF
 ;
+#IF (SDMODE == SDMODE_GM)		; GM
+SD_DEVMAX	.EQU	2		; NUMBER OF PHYSICAL UNITS (SOCKETS)
+SD_OPRREG	.EQU	RTCIO		; USES RTC LATCHES FOR OPERATION
+SD_OPRDEF	.EQU	%00000100	; QUIESCENT STATE (/CS1 & /CS2 DEASSERTED)
+SD_OPRMSK	.EQU	%00000100	; MASK FOR BITS WE OWN IN RTC LATCH PORT
+SD_CS0		.EQU	%00000100	; RTC:2 IS SELECT FOR PRIMARY SPI CARD
+SD_CS1		.EQU	%00000000	; RTC:3 IS SELECT FOR SECONDARY SPI CARD
+SD_CNTR		.EQU	Z180_CNTR
+SD_TRDR		.EQU	Z180_TRDR
+SD_IOBASE	.EQU	SD_OPRREG	; IOBASE
+SD_INVCS	.EQU	TRUE		; INVERT CS
+		DEVECHO	"GM"
 RTCDEF		.SET	RTCDEF | SD_OPRDEF	; SET DEFAULT IN HBIOS MAINLINE
 #ENDIF
 ;
@@ -608,7 +622,7 @@ SD_INIT:
 	CALL	PRTHEXBYTE
 #ENDIF
 ;
-#IF (SDMODE == SDMODE_SC)
+#IF ((SDMODE == SDMODE_SC) | (SDMODE == SDMODE_GM))
 	PRTS(" MODE=SC$")
   #IF (SDCSIOFAST)
 	PRTS(" FAST$")
@@ -1132,7 +1146,7 @@ SD_INITCARD1:
 	POP	BC			; RESTORE LOOP CONTROL
 	DJNZ	SD_INITCARD1		; LOOP AS NEEDED
 ;
-#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
+#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_GM) | (SDMODE == SDMODE_EPITX))
 	; MAKE SURE CSIO IS DONE SENDING DATA
 	CALL	SD_WAITTX		; WAIT FOR TE TO CLEAR
 	CALL	DLY32			; WAIT A BIT MORE FOR FINAL BIT
@@ -1312,7 +1326,7 @@ SD_INITCARD5:
 
 ; HIGH SPEED CSIO OPERATION IS NOW SET AT THE START OF SD_IO
 ;
-;#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC))
+;#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_GM))
 ;	; PER SPEC, THE CARD SHOULD NOW BE ABLE TO HANDLE FULL SPEED OPERATION
 ;	; SO, FOR CSIO OPERATION, WE SET CSIO TO MAXIMUM SPEED
 ;	CALL	SD_WAITTX		; MAKE SURE WE ARE DONE SENDING
@@ -1497,11 +1511,11 @@ SD_SETADDR:
 	PUSH	AF			; SAVE IT
 	LD	A,SD_LBA		; OFFSET OF LBA VALUE
 	CALL	LDHLIYA			; HL := IY + A, REG A TRASHED
-#IF (DSKYENABLE)
-  #IF (DSKYDSKACT)
+;;;#IF (DSKYENABLE)
+;;;  #IF (DSKYDSKACT)
 	CALL	HB_DSKACT		; SHOW ACTIVITY
-  #ENDIF
-#ENDIF
+;;;  #ENDIF
+;;;#ENDIF
 	CALL	LD32			; LOAD IT TO DE:HL, AF IS TRASHED
 	POP	AF			; GET CARD TYPE BACK
 	CP	SD_TYPESDHC		; IS IT V2 OR BETTER?
@@ -1874,7 +1888,7 @@ SD_DONE:
 	PUSH	AF
 	LD	A,$FF
 	CALL	SD_PUT
-#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
+#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX) | (SDMODE == SDMODE_GM))
 	; MAKE SURE CSIO IS DONE SENDING DATA
 	CALL	SD_WAITTX		; WAIT FOR TE TO CLEAR
 	CALL	DLY32			; WAIT A BIT MORE FOR FINAL BIT
@@ -1898,14 +1912,14 @@ SD_SETUP:
 	OUT	(SD_PPIX),A
 #ENDIF
 ;
-#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
+#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX) | (SDMODE == SDMODE_GM))
 	; CSIO SETUP FOR Z180 CSIO
 ;	LD	A,2			; DIV 80, 225KHZ @ 18MHZ CLK
 	LD	A,6			; DIV 1280, 14KHZ @ 18MHZ CLK
 	OUT0	(SD_CNTR),A
 #ENDIF
 ;
-#IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_N8) | (SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_SC))
+#IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_N8) | (SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_GM))
 	LD	A,(HB_RTCVAL)
 	LD	(SD_OPRVAL),A
 	OUT	(SD_OPRREG),A
@@ -2004,11 +2018,11 @@ SD_CHKWP:
 ;
 SD_SELECT:
 ;	; FINISH SENDING BEFORE ASSERTING CS!
-;#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC))
+;#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_GM))
 ;	CALL	SD_WAITTX
 ;#ENDIF
 ;
-#IF ((SDMODE == SDMODE_SC) | (SDMODE == SDMODE_MT) | (SDMODE == SDMODE_FZ80))
+#IF ((SDMODE == SDMODE_SC) | (SDMODE == SDMODE_MT) | (SDMODE == SDMODE_FZ80) | (SDMODE == SDMODE_GM))
 	LD	A,(IY+SD_DEV)		; GET CURRENT DEVICE
 	OR	A			; SET FLAGS
 	LD	A,(SD_OPRVAL)		; GET CURRENT OPRVAL BACK
@@ -2038,9 +2052,9 @@ SD_SELECT1:
 ;
 SD_SELECT2:
 ; ADJUST BIT(S) FOR INTERFACES USING INVERTED CS BITS
-;#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC))
+;#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_GM))
 #IF (SD_INVCS)
-  #IF (((SDMODE == SDMODE_SC) | (SDMODE == SDMODE_FZ80)) & (SD_DEVCNT > 1))
+  #IF (((SDMODE == SDMODE_SC) | (SDMODE == SDMODE_FZ80) | (SDMODE == SDMODE_GM)) & (SD_DEVCNT > 1))
 	XOR	SD_CS0 | SD_CS1
   #ELSE
 	XOR	SD_CS0
@@ -2049,7 +2063,7 @@ SD_SELECT2:
 	LD	(SD_OPRVAL),A
 	OUT	(SD_OPRREG),A
 ;;
-;#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC))
+;#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_GM))
 ;	CALL	DLY32			; DELAY FOR FINAL BIT
 ;#ENDIF
 ;
@@ -2058,7 +2072,7 @@ SD_SELECT2:
 ; DESELECT CARD
 ;
 SD_DESELECT:
-#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
+#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX) | (SDMODE == SDMODE_GM))
 	; DON'T REMOVE CS UNTIL WE ARE DONE SENDING!
 	CALL	SD_WAITTX		; WAIT FOR TE TO CLEAR
 ;
@@ -2077,7 +2091,7 @@ SD_DESELECT:
 #ENDIF
 ;
 	LD	A,(SD_OPRVAL)
-#IF (((SDMODE == SDMODE_SC) | (SDMODE_MT)) & (SD_DEVCNT > 1))
+#IF (((SDMODE == SDMODE_SC) | (SDMODE_MT) | (SDMODE == SDMODE_GM)) & (SD_DEVCNT > 1))
 	AND	~(SD_CS0 | SD_CS1)
 #ELSE
 #IF (SDMODE == SDMODE_EPITX)
@@ -2088,7 +2102,7 @@ SD_DESELECT:
 #ENDIF
 ; ADJUST BIT(S) FOR INTERFACES USING INVERTED CS BITS
 #IF (SD_INVCS)
-  #IF (((SDMODE == SDMODE_SC) | (SDMODE == SDMODE_FZ80)) & (SD_DEVCNT > 1))
+  #IF (((SDMODE == SDMODE_SC) | (SDMODE == SDMODE_FZ80) | (SDMODE == SDMODE_GM)) & (SD_DEVCNT > 1))
 	XOR	SD_CS0 | SD_CS1
   #ELSE
 	XOR	SD_CS0
@@ -2098,7 +2112,7 @@ SD_DESELECT:
 	OUT	(SD_OPRREG),A
 	RET
 ;
-#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
+#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX) | (SDMODE == SDMODE_GM))
 ;
 ; CSIO WAIT FOR TRANSMIT READY (TX REGISTER EMPTY)
 ;
@@ -2140,7 +2154,7 @@ SD_PUT:
 	OUT	(SD_WRTR),A
 #ENDIF
 ;
-#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
+#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX) | (SDMODE == SDMODE_GM))
 	CALL	MIRROR			; MSB<-->LSB MIRROR BITS, RESULT IN C
 	CALL	SD_WAITTX		; MAKE SURE WE ARE DONE SENDING
 	OUT0	(SD_TRDR),C		; PUT BYTE IN BUFFER
@@ -2227,7 +2241,7 @@ SD_GET:
 	IN	A,(SD_RDTR)
 #ENDIF
 ;
-#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
+#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX) | (SDMODE == SDMODE_GM))
 	CALL	SD_WAITTX		; MAKE SURE WE ARE DONE SENDING
 	IN0	A,(SD_CNTR)		; GET CSIO STATUS
 	SET	5,A			; START RECEIVER
@@ -2331,7 +2345,7 @@ SD_GET1:
 ;
 SD_SPD_STD:
 ;
-#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
+#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX) | (SDMODE == SDMODE_GM))
 	; SET CSIO FOR DEFAULT OPERATION
 	PUSH	AF			; PRESERVE AF
 	CALL	SD_WAITTX		; MAKE SURE WE ARE DONE SENDING
@@ -2346,7 +2360,7 @@ SD_SPD_STD:
 ;
 SD_SPD_SLOW:
 ;
-#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
+#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX) | (SDMODE == SDMODE_GM))
 	; SET CSIO FOR DEFAULT OPERATION
 	PUSH	AF			; PRESERVE AF
 	CALL	SD_WAITTX		; MAKE SURE WE ARE DONE SENDING
@@ -2361,7 +2375,7 @@ SD_SPD_SLOW:
 ;
 SD_SPD_FAST:
 ;
-#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
+#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX) | (SDMODE == SDMODE_GM))
 	; SET CSIO FOR HIGH SPEED OPERATION
 	PUSH	AF			; PRESERVE AF
 	CALL	SD_WAITTX		; MAKE SURE WE ARE DONE SENDING
@@ -2612,7 +2626,7 @@ SD_DSKBUF	.DW	0		; ADR OF ACTIVE DISK BUFFER
 ; MSB<-->LSB MIRROR BITS IN A, RESULT IN C
 ;
 MIRROR:
-#IF (((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX)) & SDCSIOFAST)
+#IF (((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX) | (SDMODE == SDMODE_GM)) & SDCSIOFAST)
 					; FASTEST BUT USES MOST CODE SPACE
 	LD	BC,MIRTAB		; 256 BYTE MIRROR TABLE
 	ADD	A,C			; ADD OFFSET
@@ -2645,7 +2659,7 @@ MIRROR2:
 ;
 ; LOOKUP TABLE TO MIRROR BITS IN A BYTE
 ;
-#IF (((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX)) & SDCSIOFAST)
+#IF (((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX) | (SDMODE == SDMODE_GM)) & SDCSIOFAST)
 
 MIRTAB	.DB 00H, 80H, 40H, 0C0H, 20H, 0A0H, 60H, 0E0H, 10H, 90H, 50H, 0D0H, 30H, 0B0H, 70H, 0F0H
 	.DB 08H, 88H, 48H, 0C8H, 28H, 0A8H, 68H, 0E8H, 18H, 98H, 58H, 0D8H, 38H, 0B8H, 78H, 0F8H

Source/HBIOS/std.asm

@@ -22,7 +22,7 @@
 ; 18. HEATH	Les Bird's Heath Z80 Board
 ; 19. EPITX	Alan Cox' Mini-ITX System
 ; 20. MON	Jacques Pelletier's Monsputer
-; 21. STDZ180	Genesis Z180 System
+; 21. GMZ180	Doug Jacksons' Genesis Z180 System
 ; 22. NABU	NABU w/ Les Bird's RomWBW Option Board
 ; 23. FZ80	S100 Computers FPGA Z80
 ; 
@@ -194,6 +194,7 @@ IDEMODE_DIO	.EQU	1		; DISKIO V1
 IDEMODE_DIDE	.EQU	2		; DUAL IDE
 IDEMODE_MK4	.EQU	3		; MARK IV ONBOARD IDE (8 BIT ONLY)
 IDEMODE_RC	.EQU	4		; RCBUS CF MODULE (8 BIT ONLY)
+IDEMODE_GIDE	.EQU	5		; GENESIS MODULES STD BUS IDE CONTROLLER
 ;
 ; PPIDE MODE SELECTIONS
 ;
@@ -223,6 +224,7 @@ SDMODE_PIO	.EQU	11		; Z80 PIO bitbang
 SDMODE_Z80R	.EQU	12		; Z80 Retro
 SDMODE_EPITX	.EQU	13		; Mini ITX Z180
 SDMODE_FZ80	.EQU	14		; S100 FPGA Z80
+SDMODE_GM	.EQU	15		; Genesis SD Driver
 ;
 ; AY SOUND CHIP MODE SELECTIONS
 ;
@@ -321,6 +323,7 @@ DMAMODE_VDG	.EQU	7		; VELESOFT DATAGEAR
 KBDMODE_NONE	.EQU	0
 KBDMODE_PS2	.EQU	1		; PS/2 KEYBOARD CONTROLLER
 KBDMODE_VRC	.EQU	2		; VGARC KEYBOARD CONTROLLER
+KBDMODE_FV	.EQU	3		; FPGA VGA KEYBOARD CONTROLLER
 ;
 ; SERIAL DEVICE CONFIGURATION CONSTANTS
 ;
@@ -492,6 +495,7 @@ KBDENABLE	.EQU	FALSE		; PS/2 KEYBOARD DRIVER
 PPKENABLE	.EQU	FALSE		; PPK KEYBOARD DRIVER
 MKYENABLE	.EQU	FALSE		; MSX KEYBOARD DRIVER
 NABUKBENABLE	.EQU	FALSE		; NABU KEYBOARD DRIVER
+FVKBDENABLE	.EQU	FALSE		; FPGA KEYBOARD DRIVER
 ;
 ; VIDEO MODES
 ;

Source/HBIOS/syq.asm

@@ -417,11 +417,11 @@ SYQ_IO:
 	LD	(SYQ_DSKBUF),HL		; SAVE DISK BUFFER ADDRESS
 	LD	A,SYQ_LBA		; LBA OFFSET IN CONFIG
 	CALL	LDHLIYA			; POINT TO LBA DWORD
-#IF (DSKYENABLE)
-  #IF (DSKYDSKACT)
+;;;#IF (DSKYENABLE)
+;;;  #IF (DSKYDSKACT)
 	CALL	HB_DSKACT		; SHOW ACTIVITY
-  #ENDIF
-#ENDIF
+;;;  #ENDIF
+;;;#ENDIF
 	CALL	LD32			; SET DE:HL TO LBA
 ;
 	CALL	SYQ_CMDSETUP		; SETUP ATA COMMAND BUF

Source/HBIOS/term.asm

@@ -76,7 +76,8 @@ TERM_ATTACH:
 	PUSH	HL			; COPY VDA INSTANCE DATA PTR
 	POP	DE			; ... TO DE
 	CALL	CIO_ADDENT		; ADD ENTRY, A := UNIT ASSIGNED
-	LD	(HCB + HCB_CRTDEV),A	; SET OURSELVES AS THE CRT DEVICE
+	;;;LD	(HCB + HCB_CRTDEV),A	; SET OURSELVES AS THE CRT DEVICE
+	CALL	CIO_SETCRT		; SET OURSELVES AS THE CRT DEVICE
 ;
 	; INCREMENT DEVICE COUNT
 	LD	HL,TERM_DEVCNT		; POINT TO DEVICE COUNT

Source/Images/d_bp/u0/support.txt

@@ -2,16 +2,16 @@ This library contains a number of support files, programs and scripts needed
 to bring up a fully functioning BPBIOS Zsystem.  These programs and files
 are used and/or loaded by the startup scripts.
 
-Some of the support files are startup ZEX scripts, some are Z3+ segment files, 
-others are Date and Time stamp drivers, some are command line editors and 
-history shells others are needed to initialize the RAMDRIVE as well as help files.  
+Some of the support files are startup ZEX scripts, some are Z3+ segment files,
+others are Date and Time stamp drivers, some are command line editors and
+history shells others are needed to initialize the RAMDRIVE as well as help files.
 
-The following table shows which files are needed to support each of the ten 
-BPBIOS variants (BP33, BP33BNK, BP34, BP34BNK & BBP41BNK). 
+The following table shows which files are needed to support each of the ten
+BPBIOS variants (BP33, BP33BNK, BP34, BP34BNK & BBP41BNK).
 
 Variant Name		BP33	BP33BNK	BP34	BP34BNK BP41BNK
 ================================================================
-bpbio.ndr				X	X	X	
+bpbio.ndr				X	X	X
 bpbioz33.ndr		X	X
 BPCNFG.COM		X	X	X	X	X
 EASE.COM		X	X
@@ -20,18 +20,18 @@ fcp-4.zrl		X	X
 fcp-4t.zrl				X	X	X
 RELOG			X	X	X	X	X
 HELPLSH.COM				X	X	X
-IF.COM			X       X	X	X	
+IF.COM			X       X	X	X
 jetldr.com		X	X	X	X	X
 LDTIMEC.COM		X	X		X
 LSH.COM					X	X	X
 LSHF.COM*				X	X	X
 LSHF.VAR*				X	X	X
-myterm.z3t		X	X	X	X	X 
-nzdec23d.z3t		X	X	X	X	X 
+myterm.z3t		X	X	X	X	X
+nzdec23d.z3t		X	X	X	X	X
 PUTDS.COM		X	X	X	X	X
 RAMFILES.TXT		X	X	X	X	X
 RCOPY.COM		X	X	X	X	X
-rcp-16h.zrl		X	X	X	X	
+rcp-16h.zrl		X	X	X	X
 SAVE.COM		X	X	X	X
 Z33.ZEX			X	X
 ZEX.COM			X	X	X	X	X
@@ -43,14 +43,14 @@ ZST.ZEX					X	X
 
 Instructions:
 	The support files are "crunched" and stored in the library file
-SUPPORT.LBR.  Place SUPPORT.LBR on the RAMDRIVE using for example 
+SUPPORT.LBR.  Place SUPPORT.LBR on the RAMDRIVE using for example
 XModem. Use LBREXT with the /U option to extract and uncrunch the
-files.  First extract ZEX.COM while logged onto the A: drive with the 
+files.  First extract ZEX.COM while logged onto the A: drive with the
 following command:
 	B0:LBREXT SUPPORT C0:ZEX.C?M /U
 Next place all the .COM files on C15: by typing:
 	B0:LBREXT SUPPORT C15:*.C?M /U
-The remaining files should be placed on C0:.  
+The remaining files should be placed on C0:.
 	B0:LBREXT SUPPORT C0:*.Z?X /U
 	B0:LBREXT SUPPORT C0:*.Z?L /U
 	B0:LBREXT SUPPORT C0:*.N?R /U
@@ -59,14 +59,14 @@ The remaining files should be placed on C0:.
 	B0:LBREXT SUPPORT C0:*.H?P /U
 
 Note in all BPBIOS variants that A: is the RAMDRIVE, B: is
-the ROMDRIVE and C: is the system drive.  Hard drive slices occupy C: 
+the ROMDRIVE and C: is the system drive.  Hard drive slices occupy C:
 through N: and floppy drives are O: & P:.  A short desciption
 of each of the support files follows:
 
 bpbioz33.ndr	- Named Directory Table for Z33
 bpbio.ndr	- Named Directory Table for Z34 & Z41
 BPCNFG.COM	- BPBIOS configuration program
-EASE.COM	- Command line editor & history shell for Z33* 
+EASE.COM	- Command line editor & history shell for Z33*
 EASE.HLP	- Help file for EASE
 fcp-4.zrl	- Z33 Flow Control Processor (handles IF, ELSE etc)
 fcp-4t.zrl	- Z34 & Z41 Flow Control Processor (IF is transient)
@@ -80,7 +80,7 @@ LSHF.COM	- LSH with a fixed length History file (runs faster)
 LSHF.VAR	- History file for LSHF
 myterm.z3t	- Terminal Capabilities file (defines ESC sequences etc)
 NZDEC23D.Z3T	- VT100 Terminal Capabilities File.
-PUTDS.COM	- Installs date stamping for RAM drive.
+PUTDS.COM	- Prepare disk for DateStamper date/time stamping.
 RAMFILES.TXT	- List of frequently used command (edit to suit)
 RCOPY.COM	- Copies files listed in RAMFILES.TXT to RAMDRIVE
 rcp-16h.zrl	- Zsystem Resident Command Processor
@@ -92,4 +92,4 @@ ZSCFG2.COM	- Configures ZSDOS 2
 ZSTF.ZEX	- Automatically executed Startup script for BP41BNK
 ZST.ZEX		- Automatically executed Startup script for BP34*
 
-Note that clock & datestamping drivers are builtin to Z41.
+Note that clock & datestamping drivers are builtin to Z41.

Source/ZSDOS/Clock/ReadMe.txt

@@ -2,10 +2,10 @@ This directory contains the source and assembled versions of the
 ZSystem Clock Drivers for RomWBW HBIOS.
 
 The wbwclk.z80 source file can be compiled using Build.cmd which will
-produce a relocatable binary (hbclk.rel).
+produce a relocatable binary (wbwclk.rel).
 
-The relocatable binary should be added/updated in the STAMPS.DAT
-library.  The STAMPS.DAT file is just a standard LU type library and
+The relocatable binary should be added/updated in the CLOCKS.DAT
+library.  The CLOCKS.DAT file is just a standard LU type library and
 is easily updated using NULU.  The members are the relocatable
 binaries, but with the .REL extension removed.
 

Source/ver.inc

@@ -2,7 +2,7 @@
 #DEFINE	RMN	5
 #DEFINE	RUP	0
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.5.0-dev.72"
+#DEFINE BIOSVER	"3.5.0-dev.76"
 #define rmj	RMJ
 #define rmn	RMN
 #define rup	RUP

Source/ver.lib

@@ -3,5 +3,5 @@ rmn	equ	5
 rup	equ	0
 rtp	equ	0
 biosver	macro
-	db	"3.5.0-dev.72"
+	db	"3.5.0-dev.76"
 	endm